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"toplevel" in verilog output is hardcoded #420

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bjourne opened this issue Jun 13, 2022 · 0 comments
Open

"toplevel" in verilog output is hardcoded #420

bjourne opened this issue Jun 13, 2022 · 0 comments
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beginner friendly A good target for undergrads to contribute to PyRTL enhancement Proposed feature requests and improvements

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@bjourne
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bjourne commented Jun 13, 2022

When outputting your design to verilog using output_to_verilog the name of the module is always set to "toplevel". It would be great if you could pass the module name as a parameter to that function.
@timsherwood timsherwood added enhancement Proposed feature requests and improvements beginner friendly A good target for undergrads to contribute to PyRTL labels Jul 29, 2022
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