diff --git a/generator/static/ip_cores/addfp_double.ip b/generator/static/ip_cores/addfp_double.ip
index 2dd0ab3..00777c3 100644
--- a/generator/static/ip_cores/addfp_double.ip
+++ b/generator/static/ip_cores/addfp_double.ip
@@ -1,574 +1,611 @@
-
- Intel Corporation
- addfp_double
- fp_functions_0
- 17.1
-
-
- a
-
-
-
-
-
- a
-
-
- a
-
-
-
-
-
- associatedClock
- associatedClock
- clk
-
-
- associatedReset
- associatedReset
- areset
-
-
- prSafe
- Partial Reconfiguration Safe
- false
-
-
-
-
- areset
-
-
-
-
-
- reset
-
-
- areset
-
-
-
-
-
- associatedClock
- Associated clock
- clk
-
-
- synchronousEdges
- Synchronous edges
- DEASSERT
-
-
-
-
- b
-
-
-
-
-
- b
-
-
- b
-
-
-
-
-
- associatedClock
- associatedClock
- clk
-
-
- associatedReset
- associatedReset
- areset
-
-
- prSafe
- Partial Reconfiguration Safe
- false
-
-
-
-
- clk
-
-
-
-
-
- clk
-
-
- clk
-
-
-
-
-
- clockRate
- Clock rate
- 0
-
-
- externallyDriven
- Externally driven
- false
-
-
- ptfSchematicName
- PTF schematic name
-
-
-
-
-
- q
-
-
-
-
-
- q
-
-
- q
-
-
-
-
-
- associatedClock
- associatedClock
- clk
-
-
- associatedReset
- associatedReset
-
-
-
- prSafe
- Partial Reconfiguration Safe
- false
-
-
-
+
+ Intel Corporation
+ addfp_double
+ fp_functions_0
+ 19.1
+
+
+ clk
+
+
+
+
+
+
+
+ clk
+
+
+ clk
+
+
+
+
+
+
+
+
+ clockRate
+ Clock rate
+ 0
+
+
+ externallyDriven
+ Externally driven
+ false
+
+
+ ptfSchematicName
+ PTF schematic name
+
+
+
+
+
+ areset
+
+
+
+
+
+
+
+ reset
+
+
+ areset
+
+
+
+
+
+
+
+
+ associatedClock
+ Associated clock
+ clk
+
+
+ synchronousEdges
+ Synchronous edges
+ DEASSERT
+
+
+
+
+ a
+
+
+
+
+
+
+
+ a
+
+
+ a
+
+
+
+
+
+
+
+
+ associatedClock
+ associatedClock
+ clk
+
+
+ associatedReset
+ associatedReset
+ areset
+
+
+ prSafe
+ Partial Reconfiguration Safe
+ false
+
+
+
+
+ b
+
+
+
+
+
+
+
+ b
+
+
+ b
+
+
+
+
+
+
+
+
+ associatedClock
+ associatedClock
+ clk
+
+
+ associatedReset
+ associatedReset
+ areset
+
+
+ prSafe
+ Partial Reconfiguration Safe
+ false
+
+
+
+
+ q
+
+
+
+
+
+
+
+ q
+
+
+ q
+
+
+
+
+
+
+
+
+ associatedClock
+ associatedClock
+ clk
+
+
+ associatedReset
+ associatedReset
+
+
+
+ prSafe
+ Partial Reconfiguration Safe
+ false
+
+
+
-
-
- ui.blockdiagram.direction
- OUTPUT
-
-
+
+
+ ui.blockdiagram.direction
+ OUTPUT
+
+
-
-
-
-
-
-
- QUARTUS_SYNTH
- :quartus.altera.com:
- altera_fp_functions
-
- QUARTUS_SYNTH
-
-
-
-
-
- clk
-
- in
-
-
- STD_LOGIC
- QUARTUS_SYNTH
-
-
-
-
-
- areset
-
- in
-
-
- STD_LOGIC
- QUARTUS_SYNTH
-
-
-
-
-
- a
-
- in
-
- 0
- 63
-
-
-
- STD_LOGIC_VECTOR
- QUARTUS_SYNTH
-
-
-
-
-
- b
-
- in
-
- 0
- 63
-
-
-
- STD_LOGIC_VECTOR
- QUARTUS_SYNTH
-
-
-
-
-
- q
-
- out
-
- 0
- 63
-
-
-
- STD_LOGIC_VECTOR
- QUARTUS_SYNTH
-
-
-
-
-
-
-
+
+
+
+
+
+
+ QUARTUS_SYNTH
+ :quartus.altera.com:
+ QUARTUS_SYNTH
+
+
+
+
+ QUARTUS_SYNTH
+ altera_fp_functions
+
+ QUARTUS_SYNTH
+
+
+
+
+
+ clk
+
+ in
+
+
+ STD_LOGIC
+ QUARTUS_SYNTH
+
+
+
+
+
+ areset
+
+ in
+
+
+ STD_LOGIC
+ QUARTUS_SYNTH
+
+
+
+
+
+ a
+
+ in
+
+
+ 0
+ 63
+
+
+
+
+ STD_LOGIC_VECTOR
+ QUARTUS_SYNTH
+
+
+
+
+
+ b
+
+ in
+
+
+ 0
+ 63
+
+
+
+
+ STD_LOGIC_VECTOR
+ QUARTUS_SYNTH
+
+
+
+
+
+ q
+
+ out
+
+
+ 0
+ 63
+
+
+
+
+ STD_LOGIC_VECTOR
+ QUARTUS_SYNTH
+
+
+
+
+
+
+
- Intel Corporation
- addfp_double
- altera_fp_functions
- 17.1
+ Intel Corporation
+ addfp_double
+ altera_fp_functions
+ 19.1
-
-
- FUNCTION_FAMILY
- Family
- ARITH
-
-
- ARITH_function
- Name
- ADD
-
-
- CONVERT_function
- Name
- FXP_FP
-
-
- ALL_function
- Name
- ADD
-
-
- EXP_LOG_function
- Name
- EXPE
-
-
- TRIG_function
- Name
- SIN
-
-
- COMPARE_function
- Name
- MIN
-
-
- ROOTS_function
- Name
- SQRT
-
-
- derivedfunction
- derivedfunction
- ADD
-
-
- fp_format
- Format
- double
-
-
- fp_exp
- Exponent
- 8
-
-
- fp_exp_derived
- fp_exp_derived
- 11
-
-
- fp_man
- Mantissa
- 23
-
-
- fp_man_derived
- fp_man_derived
- 52
-
-
- exponent_width
- Exponent Width
- 23
-
-
- frequency_target
- Target
- 200
-
-
- latency_target
- Target
- 7
-
-
- performance_goal
- Goal
- latency
-
-
- rounding_mode
- Mode
- nearest with tie breaking away from zero
-
-
- rounding_mode_derived
- Mode
- nearest with tie breaking to even
-
-
- use_rounding_mode
- use_rounding_mode
- true
-
-
- faithful_rounding
- Relax rounding to round up or down to reduce resource usage
- false
-
-
- gen_enable
- Generate an enable port
- false
-
-
- divide_type
- Method
- 0
-
-
- select_signal_enable
- Use Select Signal
- true
-
-
- scale_by_pi
- Represent angle as multiple of Pi
- false
-
-
- number_of_inputs
- Input Vector Dimension
- 2
-
-
- trig_no_range_reduction
- Inputs are within range -2pi to +2pi
- false
-
-
- report_resources_to_xml
- report_resources_to_xml
- false
-
-
- fxpt_width
- Width
- 32
-
-
- fxpt_fraction
- Fraction
- 0
-
-
- fxpt_sign
- Sign
- 1
-
-
- frequency_feedback
- frequency_feedback
- 157
-
-
- latency_feedback
- latency_feedback
- 0
-
-
- force_elaborate
- force_elaborate
- 1
-
-
- fp_out_format
- Output Format
- single
-
-
- fp_out_exp
- Output Exponent
- 8
-
-
- fp_out_exp_derived
- fp_out_exp_derived
- 8
-
-
- fp_out_man
- Output Mantissa
- 23
-
-
- fp_out_man_derived
- fp_out_man_derived
- 8
-
-
- fp_in_format
- Input Format
- single
-
-
- fp_in_exp
- Input Exponent
- 8
-
-
- fp_in_exp_derived
- fp_in_exp_derived
- 8
-
-
- fp_in_man
- Input Mantissa
- 23
-
-
- fp_in_man_derived
- fp_in_man_derived
- 8
-
-
- enable_hard_fp
- intel_fpga_FP_FUNCTIONS
- true
-
-
- manual_dsp_planning
- intel_fpga_FP_FUNCTIONS
- true
-
-
- forceRegisters
- forceRegisters
- 1111
-
-
- RES_DSP_param
- Multiplies
- 0
-
-
- RES_LUT_param
- LUTs
- 1778
-
-
- RES_MBIT_param
- Memory Bits
- 0
-
-
- RES_MBLOCK_param
- Memory Blocks
- 0
-
-
- selected_device_family
- selected_device_family
- Arria 10
-
-
- selected_device_speedgrade
- selected_device_speedgrade
- 2
-
-
- validation_failed
- validation_failed
- false
-
-
+
+
+ FUNCTION_FAMILY
+ Family
+ ARITH
+
+
+ ARITH_function
+ Name
+ ADD
+
+
+ CONVERT_function
+ Name
+ FXP_FP
+
+
+ ALL_function
+ Name
+ ADD
+
+
+ EXP_LOG_function
+ Name
+ EXPE
+
+
+ TRIG_function
+ Name
+ SIN
+
+
+ COMPARE_function
+ Name
+ MIN
+
+
+ ROOTS_function
+ Name
+ SQRT
+
+
+ derivedfunction
+ derivedfunction
+ ADD
+
+
+ fp_format
+ Format
+ double
+
+
+ fp_exp
+ Exponent
+ 8
+
+
+ fp_exp_derived
+ fp_exp_derived
+ 11
+
+
+ fp_man
+ Mantissa
+ 23
+
+
+ fp_man_derived
+ fp_man_derived
+ 52
+
+
+ exponent_width
+ Exponent Width
+ 23
+
+
+ frequency_target
+ Target
+ 200
+
+
+ latency_target
+ Target
+ 7
+
+
+ performance_goal
+ Goal
+ latency
+
+
+ rounding_mode
+ Mode
+ nearest with tie breaking away from zero
+
+
+ rounding_mode_derived
+ Mode
+ nearest with tie breaking to even
+
+
+ use_rounding_mode
+ use_rounding_mode
+ true
+
+
+ faithful_rounding
+ Relax rounding to round up or down to reduce resource usage
+ false
+
+
+ gen_enable
+ Generate an enable port
+ false
+
+
+ divide_type
+ Method
+ 0
+
+
+ select_signal_enable
+ Use Select Signal
+ true
+
+
+ scale_by_pi
+ Represent angle as multiple of Pi
+ false
+
+
+ number_of_inputs
+ Input Vector Dimension
+ 2
+
+
+ trig_no_range_reduction
+ Inputs are within range -2pi to +2pi
+ false
+
+
+ report_resources_to_xml
+ report_resources_to_xml
+ false
+
+
+ fxpt_width
+ Width
+ 32
+
+
+ fxpt_fraction
+ Fraction
+ 0
+
+
+ fxpt_sign
+ Sign
+ 1
+
+
+ frequency_feedback
+ frequency_feedback
+ 157
+
+
+ latency_feedback
+ latency_feedback
+ 0
+
+
+ force_elaborate
+ force_elaborate
+ 1
+
+
+ fp_out_format
+ Output Format
+ single
+
+
+ fp_out_exp
+ Output Exponent
+ 8
+
+
+ fp_out_exp_derived
+ fp_out_exp_derived
+ 8
+
+
+ fp_out_man
+ Output Mantissa
+ 23
+
+
+ fp_out_man_derived
+ fp_out_man_derived
+ 8
+
+
+ fp_in_format
+ Input Format
+ single
+
+
+ fp_in_exp
+ Input Exponent
+ 8
+
+
+ fp_in_exp_derived
+ fp_in_exp_derived
+ 8
+
+
+ fp_in_man
+ Input Mantissa
+ 23
+
+
+ fp_in_man_derived
+ fp_in_man_derived
+ 8
+
+
+ enable_hard_fp
+ Enable Hard Floating Point
+ true
+
+
+ manual_dsp_planning
+ Enable Hard Floating Point
+ true
+
+
+ forceRegisters
+ forceRegisters
+ 1111
+
+
+ RES_DSP_param
+ Multiplies
+ 0
+
+
+ RES_LUT_param
+ LUTs
+ 1778
+
+
+ RES_MBIT_param
+ Memory Bits
+ 0
+
+
+ RES_MBLOCK_param
+ Memory Blocks
+ 0
+
+
+ selected_device_family
+ selected_device_family
+ Arria 10
+
+
+ selected_device_speedgrade
+ selected_device_speedgrade
+ 2
+
+
+ validation_failed
+ validation_failed
+ false
+
+
-
-
- device
- Device
- 10AX115N2F40E2LG
-
-
- deviceFamily
- Device family
- Arria 10
-
-
- deviceSpeedGrade
- Device Speed Grade
- 2
-
-
- generationId
- Generation Id
- 0
-
-
- bonusData
- bonusData
- bonusData
+
+
+ device
+ Device
+ 10AX115N2F40E2LG
+
+
+ deviceFamily
+ Device family
+ Arria 10
+
+
+ deviceSpeedGrade
+ Device Speed Grade
+ 2
+
+
+ generationId
+ Generation Id
+ 0
+
+
+ bonusData
+ bonusData
+ bonusData
{
element fp_functions_0
{
@@ -579,26 +616,26 @@
}
}
}
-
-
-
- hideFromIPCatalog
- Hide from IP Catalog
- true
-
-
- lockedInterfaceDefinition
- lockedInterfaceDefinition
-
-
-
- systemInfos
- systemInfos
-
-
-]]>
-
-
+
+
+
+ hideFromIPCatalog
+ Hide from IP Catalog
+ true
+
+
+ lockedInterfaceDefinition
+ lockedInterfaceDefinition
+
+
+
+ systemInfos
+ systemInfos
+ <systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>
+
+
@@ -620,5 +657,5 @@
false
false
-
-
\ No newline at end of file
+
+
\ No newline at end of file
diff --git a/generator/static/ip_cores/addfp_single.ip b/generator/static/ip_cores/addfp_single.ip
index c901386..115015a 100644
--- a/generator/static/ip_cores/addfp_single.ip
+++ b/generator/static/ip_cores/addfp_single.ip
@@ -1,574 +1,611 @@
-
- Intel Corporation
- addfp_single
- fp_functions_0
- 17.1
-
-
- a
-
-
-
-
-
- a
-
-
- a
-
-
-
-
-
- associatedClock
- associatedClock
- clk
-
-
- associatedReset
- associatedReset
- areset
-
-
- prSafe
- Partial Reconfiguration Safe
- false
-
-
-
-
- areset
-
-
-
-
-
- reset
-
-
- areset
-
-
-
-
-
- associatedClock
- Associated clock
- clk
-
-
- synchronousEdges
- Synchronous edges
- DEASSERT
-
-
-
-
- b
-
-
-
-
-
- b
-
-
- b
-
-
-
-
-
- associatedClock
- associatedClock
- clk
-
-
- associatedReset
- associatedReset
- areset
-
-
- prSafe
- Partial Reconfiguration Safe
- false
-
-
-
-
- clk
-
-
-
-
-
- clk
-
-
- clk
-
-
-
-
-
- clockRate
- Clock rate
- 0
-
-
- externallyDriven
- Externally driven
- false
-
-
- ptfSchematicName
- PTF schematic name
-
-
-
-
-
- q
-
-
-
-
-
- q
-
-
- q
-
-
-
-
-
- associatedClock
- associatedClock
- clk
-
-
- associatedReset
- associatedReset
-
-
-
- prSafe
- Partial Reconfiguration Safe
- false
-
-
-
+
+ Intel Corporation
+ addfp_single
+ fp_functions_0
+ 19.1
+
+
+ clk
+
+
+
+
+
+
+
+ clk
+
+
+ clk
+
+
+
+
+
+
+
+
+ clockRate
+ Clock rate
+ 0
+
+
+ externallyDriven
+ Externally driven
+ false
+
+
+ ptfSchematicName
+ PTF schematic name
+
+
+
+
+
+ areset
+
+
+
+
+
+
+
+ reset
+
+
+ areset
+
+
+
+
+
+
+
+
+ associatedClock
+ Associated clock
+ clk
+
+
+ synchronousEdges
+ Synchronous edges
+ DEASSERT
+
+
+
+
+ a
+
+
+
+
+
+
+
+ a
+
+
+ a
+
+
+
+
+
+
+
+
+ associatedClock
+ associatedClock
+ clk
+
+
+ associatedReset
+ associatedReset
+ areset
+
+
+ prSafe
+ Partial Reconfiguration Safe
+ false
+
+
+
+
+ b
+
+
+
+
+
+
+
+ b
+
+
+ b
+
+
+
+
+
+
+
+
+ associatedClock
+ associatedClock
+ clk
+
+
+ associatedReset
+ associatedReset
+ areset
+
+
+ prSafe
+ Partial Reconfiguration Safe
+ false
+
+
+
+
+ q
+
+
+
+
+
+
+
+ q
+
+
+ q
+
+
+
+
+
+
+
+
+ associatedClock
+ associatedClock
+ clk
+
+
+ associatedReset
+ associatedReset
+
+
+
+ prSafe
+ Partial Reconfiguration Safe
+ false
+
+
+
-
-
- ui.blockdiagram.direction
- OUTPUT
-
-
+
+
+ ui.blockdiagram.direction
+ OUTPUT
+
+
-
-
-
-
-
-
- QUARTUS_SYNTH
- :quartus.altera.com:
- altera_fp_functions
-
- QUARTUS_SYNTH
-
-
-
-
-
- clk
-
- in
-
-
- STD_LOGIC
- QUARTUS_SYNTH
-
-
-
-
-
- areset
-
- in
-
-
- STD_LOGIC
- QUARTUS_SYNTH
-
-
-
-
-
- a
-
- in
-
- 0
- 31
-
-
-
- STD_LOGIC_VECTOR
- QUARTUS_SYNTH
-
-
-
-
-
- b
-
- in
-
- 0
- 31
-
-
-
- STD_LOGIC_VECTOR
- QUARTUS_SYNTH
-
-
-
-
-
- q
-
- out
-
- 0
- 31
-
-
-
- STD_LOGIC_VECTOR
- QUARTUS_SYNTH
-
-
-
-
-
-
-
+
+
+
+
+
+
+ QUARTUS_SYNTH
+ :quartus.altera.com:
+ QUARTUS_SYNTH
+
+
+
+
+ QUARTUS_SYNTH
+ altera_fp_functions
+
+ QUARTUS_SYNTH
+
+
+
+
+
+ clk
+
+ in
+
+
+ STD_LOGIC
+ QUARTUS_SYNTH
+
+
+
+
+
+ areset
+
+ in
+
+
+ STD_LOGIC
+ QUARTUS_SYNTH
+
+
+
+
+
+ a
+
+ in
+
+
+ 0
+ 31
+
+
+
+
+ STD_LOGIC_VECTOR
+ QUARTUS_SYNTH
+
+
+
+
+
+ b
+
+ in
+
+
+ 0
+ 31
+
+
+
+
+ STD_LOGIC_VECTOR
+ QUARTUS_SYNTH
+
+
+
+
+
+ q
+
+ out
+
+
+ 0
+ 31
+
+
+
+
+ STD_LOGIC_VECTOR
+ QUARTUS_SYNTH
+
+
+
+
+
+
+
- Intel Corporation
- addfp_single
- altera_fp_functions
- 17.1
+ Intel Corporation
+ addfp_single
+ altera_fp_functions
+ 19.1
-
-
- FUNCTION_FAMILY
- Family
- ARITH
-
-
- ARITH_function
- Name
- ADD
-
-
- CONVERT_function
- Name
- FXP_FP
-
-
- ALL_function
- Name
- ADD
-
-
- EXP_LOG_function
- Name
- EXPE
-
-
- TRIG_function
- Name
- SIN
-
-
- COMPARE_function
- Name
- MIN
-
-
- ROOTS_function
- Name
- SQRT
-
-
- derivedfunction
- derivedfunction
- ADD
-
-
- fp_format
- Format
- single
-
-
- fp_exp
- Exponent
- 8
-
-
- fp_exp_derived
- fp_exp_derived
- 8
-
-
- fp_man
- Mantissa
- 23
-
-
- fp_man_derived
- fp_man_derived
- 23
-
-
- exponent_width
- Exponent Width
- 23
-
-
- frequency_target
- Target
- 200
-
-
- latency_target
- Target
- 3
-
-
- performance_goal
- Goal
- latency
-
-
- rounding_mode
- Mode
- nearest with tie breaking away from zero
-
-
- rounding_mode_derived
- Mode
- nearest with tie breaking to even
-
-
- use_rounding_mode
- use_rounding_mode
- true
-
-
- faithful_rounding
- Relax rounding to round up or down to reduce resource usage
- false
-
-
- gen_enable
- Generate an enable port
- false
-
-
- divide_type
- Method
- 0
-
-
- select_signal_enable
- Use Select Signal
- true
-
-
- scale_by_pi
- Represent angle as multiple of Pi
- false
-
-
- number_of_inputs
- Input Vector Dimension
- 2
-
-
- trig_no_range_reduction
- Inputs are within range -2pi to +2pi
- false
-
-
- report_resources_to_xml
- report_resources_to_xml
- false
-
-
- fxpt_width
- Width
- 32
-
-
- fxpt_fraction
- Fraction
- 0
-
-
- fxpt_sign
- Sign
- 1
-
-
- frequency_feedback
- frequency_feedback
- 0
-
-
- latency_feedback
- latency_feedback
- 0
-
-
- force_elaborate
- force_elaborate
- 0
-
-
- fp_out_format
- Output Format
- single
-
-
- fp_out_exp
- Output Exponent
- 8
-
-
- fp_out_exp_derived
- fp_out_exp_derived
- 8
-
-
- fp_out_man
- Output Mantissa
- 23
-
-
- fp_out_man_derived
- fp_out_man_derived
- 8
-
-
- fp_in_format
- Input Format
- single
-
-
- fp_in_exp
- Input Exponent
- 8
-
-
- fp_in_exp_derived
- fp_in_exp_derived
- 8
-
-
- fp_in_man
- Input Mantissa
- 23
-
-
- fp_in_man_derived
- fp_in_man_derived
- 8
-
-
- enable_hard_fp
- intel_fpga_FP_FUNCTIONS
- true
-
-
- manual_dsp_planning
- intel_fpga_FP_FUNCTIONS
- true
-
-
- forceRegisters
- forceRegisters
- 1111
-
-
- RES_DSP_param
- Multiplies
- 0
-
-
- RES_LUT_param
- LUTs
- 0
-
-
- RES_MBIT_param
- Memory Bits
- 0
-
-
- RES_MBLOCK_param
- Memory Blocks
- 0
-
-
- selected_device_family
- selected_device_family
- Arria 10
-
-
- selected_device_speedgrade
- selected_device_speedgrade
- 2
-
-
- validation_failed
- validation_failed
- false
-
-
+
+
+ FUNCTION_FAMILY
+ Family
+ ARITH
+
+
+ ARITH_function
+ Name
+ ADD
+
+
+ CONVERT_function
+ Name
+ FXP_FP
+
+
+ ALL_function
+ Name
+ ADD
+
+
+ EXP_LOG_function
+ Name
+ EXPE
+
+
+ TRIG_function
+ Name
+ SIN
+
+
+ COMPARE_function
+ Name
+ MIN
+
+
+ ROOTS_function
+ Name
+ SQRT
+
+
+ derivedfunction
+ derivedfunction
+ ADD
+
+
+ fp_format
+ Format
+ single
+
+
+ fp_exp
+ Exponent
+ 8
+
+
+ fp_exp_derived
+ fp_exp_derived
+ 8
+
+
+ fp_man
+ Mantissa
+ 23
+
+
+ fp_man_derived
+ fp_man_derived
+ 23
+
+
+ exponent_width
+ Exponent Width
+ 23
+
+
+ frequency_target
+ Target
+ 200
+
+
+ latency_target
+ Target
+ 3
+
+
+ performance_goal
+ Goal
+ latency
+
+
+ rounding_mode
+ Mode
+ nearest with tie breaking away from zero
+
+
+ rounding_mode_derived
+ Mode
+ nearest with tie breaking to even
+
+
+ use_rounding_mode
+ use_rounding_mode
+ true
+
+
+ faithful_rounding
+ Relax rounding to round up or down to reduce resource usage
+ false
+
+
+ gen_enable
+ Generate an enable port
+ false
+
+
+ divide_type
+ Method
+ 0
+
+
+ select_signal_enable
+ Use Select Signal
+ true
+
+
+ scale_by_pi
+ Represent angle as multiple of Pi
+ false
+
+
+ number_of_inputs
+ Input Vector Dimension
+ 2
+
+
+ trig_no_range_reduction
+ Inputs are within range -2pi to +2pi
+ false
+
+
+ report_resources_to_xml
+ report_resources_to_xml
+ false
+
+
+ fxpt_width
+ Width
+ 32
+
+
+ fxpt_fraction
+ Fraction
+ 0
+
+
+ fxpt_sign
+ Sign
+ 1
+
+
+ frequency_feedback
+ frequency_feedback
+ 0
+
+
+ latency_feedback
+ latency_feedback
+ 0
+
+
+ force_elaborate
+ force_elaborate
+ 0
+
+
+ fp_out_format
+ Output Format
+ single
+
+
+ fp_out_exp
+ Output Exponent
+ 8
+
+
+ fp_out_exp_derived
+ fp_out_exp_derived
+ 8
+
+
+ fp_out_man
+ Output Mantissa
+ 23
+
+
+ fp_out_man_derived
+ fp_out_man_derived
+ 8
+
+
+ fp_in_format
+ Input Format
+ single
+
+
+ fp_in_exp
+ Input Exponent
+ 8
+
+
+ fp_in_exp_derived
+ fp_in_exp_derived
+ 8
+
+
+ fp_in_man
+ Input Mantissa
+ 23
+
+
+ fp_in_man_derived
+ fp_in_man_derived
+ 8
+
+
+ enable_hard_fp
+ Enable Hard Floating Point
+ true
+
+
+ manual_dsp_planning
+ Enable Hard Floating Point
+ true
+
+
+ forceRegisters
+ forceRegisters
+ 1111
+
+
+ RES_DSP_param
+ Multiplies
+ 0
+
+
+ RES_LUT_param
+ LUTs
+ 0
+
+
+ RES_MBIT_param
+ Memory Bits
+ 0
+
+
+ RES_MBLOCK_param
+ Memory Blocks
+ 0
+
+
+ selected_device_family
+ selected_device_family
+ Arria 10
+
+
+ selected_device_speedgrade
+ selected_device_speedgrade
+ 2
+
+
+ validation_failed
+ validation_failed
+ false
+
+
-
-
- device
- Device
- 10AX115N2F40E2LG
-
-
- deviceFamily
- Device family
- Arria 10
-
-
- deviceSpeedGrade
- Device Speed Grade
- 2
-
-
- generationId
- Generation Id
- 0
-
-
- bonusData
- bonusData
- bonusData
+
+
+ device
+ Device
+ 10AX115N2F40E2LG
+
+
+ deviceFamily
+ Device family
+ Arria 10
+
+
+ deviceSpeedGrade
+ Device Speed Grade
+ 2
+
+
+ generationId
+ Generation Id
+ 0
+
+
+ bonusData
+ bonusData
+ bonusData
{
element fp_functions_0
{
@@ -579,26 +616,26 @@
}
}
}
-
-
-
- hideFromIPCatalog
- Hide from IP Catalog
- true
-
-
- lockedInterfaceDefinition
- lockedInterfaceDefinition
-
-
-
- systemInfos
- systemInfos
-
-
-]]>
-
-
+
+
+
+ hideFromIPCatalog
+ Hide from IP Catalog
+ true
+
+
+ lockedInterfaceDefinition
+ lockedInterfaceDefinition
+
+
+
+ systemInfos
+ systemInfos
+ <systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>
+
+
@@ -620,5 +657,5 @@
false
false
-
-
\ No newline at end of file
+
+
\ No newline at end of file
diff --git a/generator/static/ip_cores/multfp_double.ip b/generator/static/ip_cores/multfp_double.ip
index fc4f468..2fb4826 100644
--- a/generator/static/ip_cores/multfp_double.ip
+++ b/generator/static/ip_cores/multfp_double.ip
@@ -1,574 +1,611 @@
-
- Intel Corporation
- multfp_double
- fp_functions_0
- 17.1
-
-
- a
-
-
-
-
-
- a
-
-
- a
-
-
-
-
-
- associatedClock
- associatedClock
- clk
-
-
- associatedReset
- associatedReset
- areset
-
-
- prSafe
- Partial Reconfiguration Safe
- false
-
-
-
-
- areset
-
-
-
-
-
- reset
-
-
- areset
-
-
-
-
-
- associatedClock
- Associated clock
- clk
-
-
- synchronousEdges
- Synchronous edges
- DEASSERT
-
-
-
-
- b
-
-
-
-
-
- b
-
-
- b
-
-
-
-
-
- associatedClock
- associatedClock
- clk
-
-
- associatedReset
- associatedReset
- areset
-
-
- prSafe
- Partial Reconfiguration Safe
- false
-
-
-
-
- clk
-
-
-
-
-
- clk
-
-
- clk
-
-
-
-
-
- clockRate
- Clock rate
- 0
-
-
- externallyDriven
- Externally driven
- false
-
-
- ptfSchematicName
- PTF schematic name
-
-
-
-
-
- q
-
-
-
-
-
- q
-
-
- q
-
-
-
-
-
- associatedClock
- associatedClock
- clk
-
-
- associatedReset
- associatedReset
-
-
-
- prSafe
- Partial Reconfiguration Safe
- false
-
-
-
+
+ Intel Corporation
+ multfp_double
+ fp_functions_0
+ 19.1
+
+
+ clk
+
+
+
+
+
+
+
+ clk
+
+
+ clk
+
+
+
+
+
+
+
+
+ clockRate
+ Clock rate
+ 0
+
+
+ externallyDriven
+ Externally driven
+ false
+
+
+ ptfSchematicName
+ PTF schematic name
+
+
+
+
+
+ areset
+
+
+
+
+
+
+
+ reset
+
+
+ areset
+
+
+
+
+
+
+
+
+ associatedClock
+ Associated clock
+ clk
+
+
+ synchronousEdges
+ Synchronous edges
+ DEASSERT
+
+
+
+
+ a
+
+
+
+
+
+
+
+ a
+
+
+ a
+
+
+
+
+
+
+
+
+ associatedClock
+ associatedClock
+ clk
+
+
+ associatedReset
+ associatedReset
+ areset
+
+
+ prSafe
+ Partial Reconfiguration Safe
+ false
+
+
+
+
+ b
+
+
+
+
+
+
+
+ b
+
+
+ b
+
+
+
+
+
+
+
+
+ associatedClock
+ associatedClock
+ clk
+
+
+ associatedReset
+ associatedReset
+ areset
+
+
+ prSafe
+ Partial Reconfiguration Safe
+ false
+
+
+
+
+ q
+
+
+
+
+
+
+
+ q
+
+
+ q
+
+
+
+
+
+
+
+
+ associatedClock
+ associatedClock
+ clk
+
+
+ associatedReset
+ associatedReset
+
+
+
+ prSafe
+ Partial Reconfiguration Safe
+ false
+
+
+
-
-
- ui.blockdiagram.direction
- OUTPUT
-
-
+
+
+ ui.blockdiagram.direction
+ OUTPUT
+
+
-
-
-
-
-
-
- QUARTUS_SYNTH
- :quartus.altera.com:
- altera_fp_functions
-
- QUARTUS_SYNTH
-
-
-
-
-
- clk
-
- in
-
-
- STD_LOGIC
- QUARTUS_SYNTH
-
-
-
-
-
- areset
-
- in
-
-
- STD_LOGIC
- QUARTUS_SYNTH
-
-
-
-
-
- a
-
- in
-
- 0
- 63
-
-
-
- STD_LOGIC_VECTOR
- QUARTUS_SYNTH
-
-
-
-
-
- b
-
- in
-
- 0
- 63
-
-
-
- STD_LOGIC_VECTOR
- QUARTUS_SYNTH
-
-
-
-
-
- q
-
- out
-
- 0
- 63
-
-
-
- STD_LOGIC_VECTOR
- QUARTUS_SYNTH
-
-
-
-
-
-
-
+
+
+
+
+
+
+ QUARTUS_SYNTH
+ :quartus.altera.com:
+ QUARTUS_SYNTH
+
+
+
+
+ QUARTUS_SYNTH
+ altera_fp_functions
+
+ QUARTUS_SYNTH
+
+
+
+
+
+ clk
+
+ in
+
+
+ STD_LOGIC
+ QUARTUS_SYNTH
+
+
+
+
+
+ areset
+
+ in
+
+
+ STD_LOGIC
+ QUARTUS_SYNTH
+
+
+
+
+
+ a
+
+ in
+
+
+ 0
+ 63
+
+
+
+
+ STD_LOGIC_VECTOR
+ QUARTUS_SYNTH
+
+
+
+
+
+ b
+
+ in
+
+
+ 0
+ 63
+
+
+
+
+ STD_LOGIC_VECTOR
+ QUARTUS_SYNTH
+
+
+
+
+
+ q
+
+ out
+
+
+ 0
+ 63
+
+
+
+
+ STD_LOGIC_VECTOR
+ QUARTUS_SYNTH
+
+
+
+
+
+
+
- Intel Corporation
- multfp_double
- altera_fp_functions
- 17.1
+ Intel Corporation
+ multfp_double
+ altera_fp_functions
+ 19.1
-
-
- FUNCTION_FAMILY
- Family
- ARITH
-
-
- ARITH_function
- Name
- MUL
-
-
- CONVERT_function
- Name
- FXP_FP
-
-
- ALL_function
- Name
- ADD
-
-
- EXP_LOG_function
- Name
- EXPE
-
-
- TRIG_function
- Name
- SIN
-
-
- COMPARE_function
- Name
- MIN
-
-
- ROOTS_function
- Name
- SQRT
-
-
- derivedfunction
- derivedfunction
- MUL
-
-
- fp_format
- Format
- double
-
-
- fp_exp
- Exponent
- 8
-
-
- fp_exp_derived
- fp_exp_derived
- 11
-
-
- fp_man
- Mantissa
- 23
-
-
- fp_man_derived
- fp_man_derived
- 52
-
-
- exponent_width
- Exponent Width
- 23
-
-
- frequency_target
- Target
- 200
-
-
- latency_target
- Target
- 5
-
-
- performance_goal
- Goal
- latency
-
-
- rounding_mode
- Mode
- nearest with tie breaking away from zero
-
-
- rounding_mode_derived
- Mode
- nearest with tie breaking to even
-
-
- use_rounding_mode
- use_rounding_mode
- true
-
-
- faithful_rounding
- Relax rounding to round up or down to reduce resource usage
- false
-
-
- gen_enable
- Generate an enable port
- false
-
-
- divide_type
- Method
- 0
-
-
- select_signal_enable
- Use Select Signal
- false
-
-
- scale_by_pi
- Represent angle as multiple of Pi
- false
-
-
- number_of_inputs
- Input Vector Dimension
- 2
-
-
- trig_no_range_reduction
- Inputs are within range -2pi to +2pi
- false
-
-
- report_resources_to_xml
- report_resources_to_xml
- false
-
-
- fxpt_width
- Width
- 32
-
-
- fxpt_fraction
- Fraction
- 0
-
-
- fxpt_sign
- Sign
- 1
-
-
- frequency_feedback
- frequency_feedback
- 154
-
-
- latency_feedback
- latency_feedback
- 6
-
-
- force_elaborate
- force_elaborate
- 1
-
-
- fp_out_format
- Output Format
- single
-
-
- fp_out_exp
- Output Exponent
- 8
-
-
- fp_out_exp_derived
- fp_out_exp_derived
- 8
-
-
- fp_out_man
- Output Mantissa
- 23
-
-
- fp_out_man_derived
- fp_out_man_derived
- 8
-
-
- fp_in_format
- Input Format
- single
-
-
- fp_in_exp
- Input Exponent
- 8
-
-
- fp_in_exp_derived
- fp_in_exp_derived
- 8
-
-
- fp_in_man
- Input Mantissa
- 23
-
-
- fp_in_man_derived
- fp_in_man_derived
- 8
-
-
- enable_hard_fp
- intel_fpga_FP_FUNCTIONS
- true
-
-
- manual_dsp_planning
- intel_fpga_FP_FUNCTIONS
- true
-
-
- forceRegisters
- forceRegisters
- 1111
-
-
- RES_DSP_param
- Multiplies
- 8
-
-
- RES_LUT_param
- LUTs
- 481
-
-
- RES_MBIT_param
- Memory Bits
- 0
-
-
- RES_MBLOCK_param
- Memory Blocks
- 0
-
-
- selected_device_family
- selected_device_family
- Arria 10
-
-
- selected_device_speedgrade
- selected_device_speedgrade
- 2
-
-
- validation_failed
- validation_failed
- false
-
-
+
+
+ FUNCTION_FAMILY
+ Family
+ ARITH
+
+
+ ARITH_function
+ Name
+ MUL
+
+
+ CONVERT_function
+ Name
+ FXP_FP
+
+
+ ALL_function
+ Name
+ ADD
+
+
+ EXP_LOG_function
+ Name
+ EXPE
+
+
+ TRIG_function
+ Name
+ SIN
+
+
+ COMPARE_function
+ Name
+ MIN
+
+
+ ROOTS_function
+ Name
+ SQRT
+
+
+ derivedfunction
+ derivedfunction
+ MUL
+
+
+ fp_format
+ Format
+ double
+
+
+ fp_exp
+ Exponent
+ 8
+
+
+ fp_exp_derived
+ fp_exp_derived
+ 11
+
+
+ fp_man
+ Mantissa
+ 23
+
+
+ fp_man_derived
+ fp_man_derived
+ 52
+
+
+ exponent_width
+ Exponent Width
+ 23
+
+
+ frequency_target
+ Target
+ 200
+
+
+ latency_target
+ Target
+ 5
+
+
+ performance_goal
+ Goal
+ latency
+
+
+ rounding_mode
+ Mode
+ nearest with tie breaking away from zero
+
+
+ rounding_mode_derived
+ Mode
+ nearest with tie breaking to even
+
+
+ use_rounding_mode
+ use_rounding_mode
+ true
+
+
+ faithful_rounding
+ Relax rounding to round up or down to reduce resource usage
+ false
+
+
+ gen_enable
+ Generate an enable port
+ false
+
+
+ divide_type
+ Method
+ 0
+
+
+ select_signal_enable
+ Use Select Signal
+ false
+
+
+ scale_by_pi
+ Represent angle as multiple of Pi
+ false
+
+
+ number_of_inputs
+ Input Vector Dimension
+ 2
+
+
+ trig_no_range_reduction
+ Inputs are within range -2pi to +2pi
+ false
+
+
+ report_resources_to_xml
+ report_resources_to_xml
+ false
+
+
+ fxpt_width
+ Width
+ 32
+
+
+ fxpt_fraction
+ Fraction
+ 0
+
+
+ fxpt_sign
+ Sign
+ 1
+
+
+ frequency_feedback
+ frequency_feedback
+ 154
+
+
+ latency_feedback
+ latency_feedback
+ 6
+
+
+ force_elaborate
+ force_elaborate
+ 1
+
+
+ fp_out_format
+ Output Format
+ single
+
+
+ fp_out_exp
+ Output Exponent
+ 8
+
+
+ fp_out_exp_derived
+ fp_out_exp_derived
+ 8
+
+
+ fp_out_man
+ Output Mantissa
+ 23
+
+
+ fp_out_man_derived
+ fp_out_man_derived
+ 8
+
+
+ fp_in_format
+ Input Format
+ single
+
+
+ fp_in_exp
+ Input Exponent
+ 8
+
+
+ fp_in_exp_derived
+ fp_in_exp_derived
+ 8
+
+
+ fp_in_man
+ Input Mantissa
+ 23
+
+
+ fp_in_man_derived
+ fp_in_man_derived
+ 8
+
+
+ enable_hard_fp
+ Enable Hard Floating Point
+ true
+
+
+ manual_dsp_planning
+ Enable Hard Floating Point
+ true
+
+
+ forceRegisters
+ forceRegisters
+ 1111
+
+
+ RES_DSP_param
+ Multiplies
+ 8
+
+
+ RES_LUT_param
+ LUTs
+ 481
+
+
+ RES_MBIT_param
+ Memory Bits
+ 0
+
+
+ RES_MBLOCK_param
+ Memory Blocks
+ 0
+
+
+ selected_device_family
+ selected_device_family
+ Arria 10
+
+
+ selected_device_speedgrade
+ selected_device_speedgrade
+ 2
+
+
+ validation_failed
+ validation_failed
+ false
+
+
-
-
- device
- Device
- 10AX115N2F40E2LG
-
-
- deviceFamily
- Device family
- Arria 10
-
-
- deviceSpeedGrade
- Device Speed Grade
- 2
-
-
- generationId
- Generation Id
- 0
-
-
- bonusData
- bonusData
- bonusData
+
+
+ device
+ Device
+ 10AX115N2F40E2LG
+
+
+ deviceFamily
+ Device family
+ Arria 10
+
+
+ deviceSpeedGrade
+ Device Speed Grade
+ 2
+
+
+ generationId
+ Generation Id
+ 0
+
+
+ bonusData
+ bonusData
+ bonusData
{
element fp_functions_0
{
@@ -579,26 +616,26 @@
}
}
}
-
-
-
- hideFromIPCatalog
- Hide from IP Catalog
- true
-
-
- lockedInterfaceDefinition
- lockedInterfaceDefinition
-
-
-
- systemInfos
- systemInfos
-
-
-]]>
-
-
+
+
+
+ hideFromIPCatalog
+ Hide from IP Catalog
+ true
+
+
+ lockedInterfaceDefinition
+ lockedInterfaceDefinition
+
+
+
+ systemInfos
+ systemInfos
+ <systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>
+
+
@@ -619,5 +656,5 @@
false
false
-
-
\ No newline at end of file
+
+
\ No newline at end of file
diff --git a/generator/static/ip_cores/multfp_single.ip b/generator/static/ip_cores/multfp_single.ip
index f6569d0..a372078 100644
--- a/generator/static/ip_cores/multfp_single.ip
+++ b/generator/static/ip_cores/multfp_single.ip
@@ -1,574 +1,611 @@
-
- Intel Corporation
- multfp_single
- fp_functions_0
- 17.1
-
-
- a
-
-
-
-
-
- a
-
-
- a
-
-
-
-
-
- associatedClock
- associatedClock
- clk
-
-
- associatedReset
- associatedReset
- areset
-
-
- prSafe
- Partial Reconfiguration Safe
- false
-
-
-
-
- areset
-
-
-
-
-
- reset
-
-
- areset
-
-
-
-
-
- associatedClock
- Associated clock
- clk
-
-
- synchronousEdges
- Synchronous edges
- DEASSERT
-
-
-
-
- b
-
-
-
-
-
- b
-
-
- b
-
-
-
-
-
- associatedClock
- associatedClock
- clk
-
-
- associatedReset
- associatedReset
- areset
-
-
- prSafe
- Partial Reconfiguration Safe
- false
-
-
-
-
- clk
-
-
-
-
-
- clk
-
-
- clk
-
-
-
-
-
- clockRate
- Clock rate
- 0
-
-
- externallyDriven
- Externally driven
- false
-
-
- ptfSchematicName
- PTF schematic name
-
-
-
-
-
- q
-
-
-
-
-
- q
-
-
- q
-
-
-
-
-
- associatedClock
- associatedClock
- clk
-
-
- associatedReset
- associatedReset
-
-
-
- prSafe
- Partial Reconfiguration Safe
- false
-
-
-
+
+ Intel Corporation
+ multfp_single
+ fp_functions_0
+ 19.1
+
+
+ clk
+
+
+
+
+
+
+
+ clk
+
+
+ clk
+
+
+
+
+
+
+
+
+ clockRate
+ Clock rate
+ 0
+
+
+ externallyDriven
+ Externally driven
+ false
+
+
+ ptfSchematicName
+ PTF schematic name
+
+
+
+
+
+ areset
+
+
+
+
+
+
+
+ reset
+
+
+ areset
+
+
+
+
+
+
+
+
+ associatedClock
+ Associated clock
+ clk
+
+
+ synchronousEdges
+ Synchronous edges
+ DEASSERT
+
+
+
+
+ a
+
+
+
+
+
+
+
+ a
+
+
+ a
+
+
+
+
+
+
+
+
+ associatedClock
+ associatedClock
+ clk
+
+
+ associatedReset
+ associatedReset
+ areset
+
+
+ prSafe
+ Partial Reconfiguration Safe
+ false
+
+
+
+
+ b
+
+
+
+
+
+
+
+ b
+
+
+ b
+
+
+
+
+
+
+
+
+ associatedClock
+ associatedClock
+ clk
+
+
+ associatedReset
+ associatedReset
+ areset
+
+
+ prSafe
+ Partial Reconfiguration Safe
+ false
+
+
+
+
+ q
+
+
+
+
+
+
+
+ q
+
+
+ q
+
+
+
+
+
+
+
+
+ associatedClock
+ associatedClock
+ clk
+
+
+ associatedReset
+ associatedReset
+
+
+
+ prSafe
+ Partial Reconfiguration Safe
+ false
+
+
+
-
-
- ui.blockdiagram.direction
- OUTPUT
-
-
+
+
+ ui.blockdiagram.direction
+ OUTPUT
+
+
-
-
-
-
-
-
- QUARTUS_SYNTH
- :quartus.altera.com:
- altera_fp_functions
-
- QUARTUS_SYNTH
-
-
-
-
-
- clk
-
- in
-
-
- STD_LOGIC
- QUARTUS_SYNTH
-
-
-
-
-
- areset
-
- in
-
-
- STD_LOGIC
- QUARTUS_SYNTH
-
-
-
-
-
- a
-
- in
-
- 0
- 31
-
-
-
- STD_LOGIC_VECTOR
- QUARTUS_SYNTH
-
-
-
-
-
- b
-
- in
-
- 0
- 31
-
-
-
- STD_LOGIC_VECTOR
- QUARTUS_SYNTH
-
-
-
-
-
- q
-
- out
-
- 0
- 31
-
-
-
- STD_LOGIC_VECTOR
- QUARTUS_SYNTH
-
-
-
-
-
-
-
+
+
+
+
+
+
+ QUARTUS_SYNTH
+ :quartus.altera.com:
+ QUARTUS_SYNTH
+
+
+
+
+ QUARTUS_SYNTH
+ altera_fp_functions
+
+ QUARTUS_SYNTH
+
+
+
+
+
+ clk
+
+ in
+
+
+ STD_LOGIC
+ QUARTUS_SYNTH
+
+
+
+
+
+ areset
+
+ in
+
+
+ STD_LOGIC
+ QUARTUS_SYNTH
+
+
+
+
+
+ a
+
+ in
+
+
+ 0
+ 31
+
+
+
+
+ STD_LOGIC_VECTOR
+ QUARTUS_SYNTH
+
+
+
+
+
+ b
+
+ in
+
+
+ 0
+ 31
+
+
+
+
+ STD_LOGIC_VECTOR
+ QUARTUS_SYNTH
+
+
+
+
+
+ q
+
+ out
+
+
+ 0
+ 31
+
+
+
+
+ STD_LOGIC_VECTOR
+ QUARTUS_SYNTH
+
+
+
+
+
+
+
- Intel Corporation
- multfp_single
- altera_fp_functions
- 17.1
+ Intel Corporation
+ multfp_single
+ altera_fp_functions
+ 19.1
-
-
- FUNCTION_FAMILY
- Family
- ARITH
-
-
- ARITH_function
- Name
- MUL
-
-
- CONVERT_function
- Name
- FXP_FP
-
-
- ALL_function
- Name
- ADD
-
-
- EXP_LOG_function
- Name
- EXPE
-
-
- TRIG_function
- Name
- SIN
-
-
- COMPARE_function
- Name
- MIN
-
-
- ROOTS_function
- Name
- SQRT
-
-
- derivedfunction
- derivedfunction
- MUL
-
-
- fp_format
- Format
- single
-
-
- fp_exp
- Exponent
- 8
-
-
- fp_exp_derived
- fp_exp_derived
- 8
-
-
- fp_man
- Mantissa
- 23
-
-
- fp_man_derived
- fp_man_derived
- 23
-
-
- exponent_width
- Exponent Width
- 23
-
-
- frequency_target
- Target
- 200
-
-
- latency_target
- Target
- 3
-
-
- performance_goal
- Goal
- latency
-
-
- rounding_mode
- Mode
- nearest with tie breaking away from zero
-
-
- rounding_mode_derived
- Mode
- nearest with tie breaking to even
-
-
- use_rounding_mode
- use_rounding_mode
- true
-
-
- faithful_rounding
- Relax rounding to round up or down to reduce resource usage
- false
-
-
- gen_enable
- Generate an enable port
- false
-
-
- divide_type
- Method
- 0
-
-
- select_signal_enable
- Use Select Signal
- false
-
-
- scale_by_pi
- Represent angle as multiple of Pi
- false
-
-
- number_of_inputs
- Input Vector Dimension
- 2
-
-
- trig_no_range_reduction
- Inputs are within range -2pi to +2pi
- false
-
-
- report_resources_to_xml
- report_resources_to_xml
- false
-
-
- fxpt_width
- Width
- 32
-
-
- fxpt_fraction
- Fraction
- 0
-
-
- fxpt_sign
- Sign
- 1
-
-
- frequency_feedback
- frequency_feedback
- 804
-
-
- latency_feedback
- latency_feedback
- 3
-
-
- force_elaborate
- force_elaborate
- 0
-
-
- fp_out_format
- Output Format
- single
-
-
- fp_out_exp
- Output Exponent
- 8
-
-
- fp_out_exp_derived
- fp_out_exp_derived
- 8
-
-
- fp_out_man
- Output Mantissa
- 23
-
-
- fp_out_man_derived
- fp_out_man_derived
- 8
-
-
- fp_in_format
- Input Format
- single
-
-
- fp_in_exp
- Input Exponent
- 8
-
-
- fp_in_exp_derived
- fp_in_exp_derived
- 8
-
-
- fp_in_man
- Input Mantissa
- 23
-
-
- fp_in_man_derived
- fp_in_man_derived
- 8
-
-
- enable_hard_fp
- intel_fpga_FP_FUNCTIONS
- true
-
-
- manual_dsp_planning
- intel_fpga_FP_FUNCTIONS
- true
-
-
- forceRegisters
- forceRegisters
- 1111
-
-
- RES_DSP_param
- Multiplies
- 2
-
-
- RES_LUT_param
- LUTs
- 0
-
-
- RES_MBIT_param
- Memory Bits
- 0
-
-
- RES_MBLOCK_param
- Memory Blocks
- 0
-
-
- selected_device_family
- selected_device_family
- Arria 10
-
-
- selected_device_speedgrade
- selected_device_speedgrade
- 2
-
-
- validation_failed
- validation_failed
- false
-
-
+
+
+ FUNCTION_FAMILY
+ Family
+ ARITH
+
+
+ ARITH_function
+ Name
+ MUL
+
+
+ CONVERT_function
+ Name
+ FXP_FP
+
+
+ ALL_function
+ Name
+ ADD
+
+
+ EXP_LOG_function
+ Name
+ EXPE
+
+
+ TRIG_function
+ Name
+ SIN
+
+
+ COMPARE_function
+ Name
+ MIN
+
+
+ ROOTS_function
+ Name
+ SQRT
+
+
+ derivedfunction
+ derivedfunction
+ MUL
+
+
+ fp_format
+ Format
+ single
+
+
+ fp_exp
+ Exponent
+ 8
+
+
+ fp_exp_derived
+ fp_exp_derived
+ 8
+
+
+ fp_man
+ Mantissa
+ 23
+
+
+ fp_man_derived
+ fp_man_derived
+ 23
+
+
+ exponent_width
+ Exponent Width
+ 23
+
+
+ frequency_target
+ Target
+ 200
+
+
+ latency_target
+ Target
+ 3
+
+
+ performance_goal
+ Goal
+ latency
+
+
+ rounding_mode
+ Mode
+ nearest with tie breaking away from zero
+
+
+ rounding_mode_derived
+ Mode
+ nearest with tie breaking to even
+
+
+ use_rounding_mode
+ use_rounding_mode
+ true
+
+
+ faithful_rounding
+ Relax rounding to round up or down to reduce resource usage
+ false
+
+
+ gen_enable
+ Generate an enable port
+ false
+
+
+ divide_type
+ Method
+ 0
+
+
+ select_signal_enable
+ Use Select Signal
+ false
+
+
+ scale_by_pi
+ Represent angle as multiple of Pi
+ false
+
+
+ number_of_inputs
+ Input Vector Dimension
+ 2
+
+
+ trig_no_range_reduction
+ Inputs are within range -2pi to +2pi
+ false
+
+
+ report_resources_to_xml
+ report_resources_to_xml
+ false
+
+
+ fxpt_width
+ Width
+ 32
+
+
+ fxpt_fraction
+ Fraction
+ 0
+
+
+ fxpt_sign
+ Sign
+ 1
+
+
+ frequency_feedback
+ frequency_feedback
+ 804
+
+
+ latency_feedback
+ latency_feedback
+ 3
+
+
+ force_elaborate
+ force_elaborate
+ 0
+
+
+ fp_out_format
+ Output Format
+ single
+
+
+ fp_out_exp
+ Output Exponent
+ 8
+
+
+ fp_out_exp_derived
+ fp_out_exp_derived
+ 8
+
+
+ fp_out_man
+ Output Mantissa
+ 23
+
+
+ fp_out_man_derived
+ fp_out_man_derived
+ 8
+
+
+ fp_in_format
+ Input Format
+ single
+
+
+ fp_in_exp
+ Input Exponent
+ 8
+
+
+ fp_in_exp_derived
+ fp_in_exp_derived
+ 8
+
+
+ fp_in_man
+ Input Mantissa
+ 23
+
+
+ fp_in_man_derived
+ fp_in_man_derived
+ 8
+
+
+ enable_hard_fp
+ Enable Hard Floating Point
+ true
+
+
+ manual_dsp_planning
+ Enable Hard Floating Point
+ true
+
+
+ forceRegisters
+ forceRegisters
+ 1111
+
+
+ RES_DSP_param
+ Multiplies
+ 2
+
+
+ RES_LUT_param
+ LUTs
+ 0
+
+
+ RES_MBIT_param
+ Memory Bits
+ 0
+
+
+ RES_MBLOCK_param
+ Memory Blocks
+ 0
+
+
+ selected_device_family
+ selected_device_family
+ Arria 10
+
+
+ selected_device_speedgrade
+ selected_device_speedgrade
+ 2
+
+
+ validation_failed
+ validation_failed
+ false
+
+
-
-
- device
- Device
- 10AX115N2F40E2LG
-
-
- deviceFamily
- Device family
- Arria 10
-
-
- deviceSpeedGrade
- Device Speed Grade
- 2
-
-
- generationId
- Generation Id
- 0
-
-
- bonusData
- bonusData
- bonusData
+
+
+ device
+ Device
+ 10AX115N2F40E2LG
+
+
+ deviceFamily
+ Device family
+ Arria 10
+
+
+ deviceSpeedGrade
+ Device Speed Grade
+ 2
+
+
+ generationId
+ Generation Id
+ 0
+
+
+ bonusData
+ bonusData
+ bonusData
{
element fp_functions_0
{
@@ -579,26 +616,26 @@
}
}
}
-
-
-
- hideFromIPCatalog
- Hide from IP Catalog
- true
-
-
- lockedInterfaceDefinition
- lockedInterfaceDefinition
-
-
-
- systemInfos
- systemInfos
-
-
-]]>
-
-
+
+
+
+ hideFromIPCatalog
+ Hide from IP Catalog
+ true
+
+
+ lockedInterfaceDefinition
+ lockedInterfaceDefinition
+
+
+
+ systemInfos
+ systemInfos
+ <systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>
+
+
@@ -619,5 +656,5 @@
false
false
-
-
\ No newline at end of file
+
+
\ No newline at end of file
diff --git a/generator/static/ip_cores/subfp_double.ip b/generator/static/ip_cores/subfp_double.ip
index 630d524..977d7ae 100644
--- a/generator/static/ip_cores/subfp_double.ip
+++ b/generator/static/ip_cores/subfp_double.ip
@@ -1,574 +1,611 @@
-
- Intel Corporation
- subfp_double
- fp_functions_0
- 17.1
-
-
- a
-
-
-
-
-
- a
-
-
- a
-
-
-
-
-
- associatedClock
- associatedClock
- clk
-
-
- associatedReset
- associatedReset
- areset
-
-
- prSafe
- Partial Reconfiguration Safe
- false
-
-
-
-
- areset
-
-
-
-
-
- reset
-
-
- areset
-
-
-
-
-
- associatedClock
- Associated clock
- clk
-
-
- synchronousEdges
- Synchronous edges
- DEASSERT
-
-
-
-
- b
-
-
-
-
-
- b
-
-
- b
-
-
-
-
-
- associatedClock
- associatedClock
- clk
-
-
- associatedReset
- associatedReset
- areset
-
-
- prSafe
- Partial Reconfiguration Safe
- false
-
-
-
-
- clk
-
-
-
-
-
- clk
-
-
- clk
-
-
-
-
-
- clockRate
- Clock rate
- 0
-
-
- externallyDriven
- Externally driven
- false
-
-
- ptfSchematicName
- PTF schematic name
-
-
-
-
-
- q
-
-
-
-
-
- q
-
-
- q
-
-
-
-
-
- associatedClock
- associatedClock
- clk
-
-
- associatedReset
- associatedReset
-
-
-
- prSafe
- Partial Reconfiguration Safe
- false
-
-
-
+
+ Intel Corporation
+ subfp_double
+ fp_functions_0
+ 19.1
+
+
+ clk
+
+
+
+
+
+
+
+ clk
+
+
+ clk
+
+
+
+
+
+
+
+
+ clockRate
+ Clock rate
+ 0
+
+
+ externallyDriven
+ Externally driven
+ false
+
+
+ ptfSchematicName
+ PTF schematic name
+
+
+
+
+
+ areset
+
+
+
+
+
+
+
+ reset
+
+
+ areset
+
+
+
+
+
+
+
+
+ associatedClock
+ Associated clock
+ clk
+
+
+ synchronousEdges
+ Synchronous edges
+ DEASSERT
+
+
+
+
+ a
+
+
+
+
+
+
+
+ a
+
+
+ a
+
+
+
+
+
+
+
+
+ associatedClock
+ associatedClock
+ clk
+
+
+ associatedReset
+ associatedReset
+ areset
+
+
+ prSafe
+ Partial Reconfiguration Safe
+ false
+
+
+
+
+ b
+
+
+
+
+
+
+
+ b
+
+
+ b
+
+
+
+
+
+
+
+
+ associatedClock
+ associatedClock
+ clk
+
+
+ associatedReset
+ associatedReset
+ areset
+
+
+ prSafe
+ Partial Reconfiguration Safe
+ false
+
+
+
+
+ q
+
+
+
+
+
+
+
+ q
+
+
+ q
+
+
+
+
+
+
+
+
+ associatedClock
+ associatedClock
+ clk
+
+
+ associatedReset
+ associatedReset
+
+
+
+ prSafe
+ Partial Reconfiguration Safe
+ false
+
+
+
-
-
- ui.blockdiagram.direction
- OUTPUT
-
-
+
+
+ ui.blockdiagram.direction
+ OUTPUT
+
+
-
-
-
-
-
-
- QUARTUS_SYNTH
- :quartus.altera.com:
- altera_fp_functions
-
- QUARTUS_SYNTH
-
-
-
-
-
- clk
-
- in
-
-
- STD_LOGIC
- QUARTUS_SYNTH
-
-
-
-
-
- areset
-
- in
-
-
- STD_LOGIC
- QUARTUS_SYNTH
-
-
-
-
-
- a
-
- in
-
- 0
- 63
-
-
-
- STD_LOGIC_VECTOR
- QUARTUS_SYNTH
-
-
-
-
-
- b
-
- in
-
- 0
- 63
-
-
-
- STD_LOGIC_VECTOR
- QUARTUS_SYNTH
-
-
-
-
-
- q
-
- out
-
- 0
- 63
-
-
-
- STD_LOGIC_VECTOR
- QUARTUS_SYNTH
-
-
-
-
-
-
-
+
+
+
+
+
+
+ QUARTUS_SYNTH
+ :quartus.altera.com:
+ QUARTUS_SYNTH
+
+
+
+
+ QUARTUS_SYNTH
+ altera_fp_functions
+
+ QUARTUS_SYNTH
+
+
+
+
+
+ clk
+
+ in
+
+
+ STD_LOGIC
+ QUARTUS_SYNTH
+
+
+
+
+
+ areset
+
+ in
+
+
+ STD_LOGIC
+ QUARTUS_SYNTH
+
+
+
+
+
+ a
+
+ in
+
+
+ 0
+ 63
+
+
+
+
+ STD_LOGIC_VECTOR
+ QUARTUS_SYNTH
+
+
+
+
+
+ b
+
+ in
+
+
+ 0
+ 63
+
+
+
+
+ STD_LOGIC_VECTOR
+ QUARTUS_SYNTH
+
+
+
+
+
+ q
+
+ out
+
+
+ 0
+ 63
+
+
+
+
+ STD_LOGIC_VECTOR
+ QUARTUS_SYNTH
+
+
+
+
+
+
+
- Intel Corporation
- subfp_double
- altera_fp_functions
- 17.1
+ Intel Corporation
+ subfp_double
+ altera_fp_functions
+ 19.1
-
-
- FUNCTION_FAMILY
- Family
- ARITH
-
-
- ARITH_function
- Name
- SUB
-
-
- CONVERT_function
- Name
- FXP_FP
-
-
- ALL_function
- Name
- ADD
-
-
- EXP_LOG_function
- Name
- EXPE
-
-
- TRIG_function
- Name
- SIN
-
-
- COMPARE_function
- Name
- MIN
-
-
- ROOTS_function
- Name
- SQRT
-
-
- derivedfunction
- derivedfunction
- SUB
-
-
- fp_format
- Format
- double
-
-
- fp_exp
- Exponent
- 8
-
-
- fp_exp_derived
- fp_exp_derived
- 11
-
-
- fp_man
- Mantissa
- 23
-
-
- fp_man_derived
- fp_man_derived
- 52
-
-
- exponent_width
- Exponent Width
- 23
-
-
- frequency_target
- Target
- 200
-
-
- latency_target
- Target
- 7
-
-
- performance_goal
- Goal
- latency
-
-
- rounding_mode
- Mode
- nearest with tie breaking away from zero
-
-
- rounding_mode_derived
- Mode
- nearest with tie breaking to even
-
-
- use_rounding_mode
- use_rounding_mode
- true
-
-
- faithful_rounding
- Relax rounding to round up or down to reduce resource usage
- false
-
-
- gen_enable
- Generate an enable port
- false
-
-
- divide_type
- Method
- 0
-
-
- select_signal_enable
- Use Select Signal
- true
-
-
- scale_by_pi
- Represent angle as multiple of Pi
- false
-
-
- number_of_inputs
- Input Vector Dimension
- 2
-
-
- trig_no_range_reduction
- Inputs are within range -2pi to +2pi
- false
-
-
- report_resources_to_xml
- report_resources_to_xml
- false
-
-
- fxpt_width
- Width
- 32
-
-
- fxpt_fraction
- Fraction
- 0
-
-
- fxpt_sign
- Sign
- 1
-
-
- frequency_feedback
- frequency_feedback
- 157
-
-
- latency_feedback
- latency_feedback
- 0
-
-
- force_elaborate
- force_elaborate
- 0
-
-
- fp_out_format
- Output Format
- single
-
-
- fp_out_exp
- Output Exponent
- 8
-
-
- fp_out_exp_derived
- fp_out_exp_derived
- 8
-
-
- fp_out_man
- Output Mantissa
- 23
-
-
- fp_out_man_derived
- fp_out_man_derived
- 8
-
-
- fp_in_format
- Input Format
- single
-
-
- fp_in_exp
- Input Exponent
- 8
-
-
- fp_in_exp_derived
- fp_in_exp_derived
- 8
-
-
- fp_in_man
- Input Mantissa
- 23
-
-
- fp_in_man_derived
- fp_in_man_derived
- 8
-
-
- enable_hard_fp
- intel_fpga_FP_FUNCTIONS
- true
-
-
- manual_dsp_planning
- intel_fpga_FP_FUNCTIONS
- true
-
-
- forceRegisters
- forceRegisters
- 1111
-
-
- RES_DSP_param
- Multiplies
- 0
-
-
- RES_LUT_param
- LUTs
- 1778
-
-
- RES_MBIT_param
- Memory Bits
- 0
-
-
- RES_MBLOCK_param
- Memory Blocks
- 0
-
-
- selected_device_family
- selected_device_family
- Arria 10
-
-
- selected_device_speedgrade
- selected_device_speedgrade
- 2
-
-
- validation_failed
- validation_failed
- false
-
-
+
+
+ FUNCTION_FAMILY
+ Family
+ ARITH
+
+
+ ARITH_function
+ Name
+ SUB
+
+
+ CONVERT_function
+ Name
+ FXP_FP
+
+
+ ALL_function
+ Name
+ ADD
+
+
+ EXP_LOG_function
+ Name
+ EXPE
+
+
+ TRIG_function
+ Name
+ SIN
+
+
+ COMPARE_function
+ Name
+ MIN
+
+
+ ROOTS_function
+ Name
+ SQRT
+
+
+ derivedfunction
+ derivedfunction
+ SUB
+
+
+ fp_format
+ Format
+ double
+
+
+ fp_exp
+ Exponent
+ 8
+
+
+ fp_exp_derived
+ fp_exp_derived
+ 11
+
+
+ fp_man
+ Mantissa
+ 23
+
+
+ fp_man_derived
+ fp_man_derived
+ 52
+
+
+ exponent_width
+ Exponent Width
+ 23
+
+
+ frequency_target
+ Target
+ 200
+
+
+ latency_target
+ Target
+ 7
+
+
+ performance_goal
+ Goal
+ latency
+
+
+ rounding_mode
+ Mode
+ nearest with tie breaking away from zero
+
+
+ rounding_mode_derived
+ Mode
+ nearest with tie breaking to even
+
+
+ use_rounding_mode
+ use_rounding_mode
+ true
+
+
+ faithful_rounding
+ Relax rounding to round up or down to reduce resource usage
+ false
+
+
+ gen_enable
+ Generate an enable port
+ false
+
+
+ divide_type
+ Method
+ 0
+
+
+ select_signal_enable
+ Use Select Signal
+ true
+
+
+ scale_by_pi
+ Represent angle as multiple of Pi
+ false
+
+
+ number_of_inputs
+ Input Vector Dimension
+ 2
+
+
+ trig_no_range_reduction
+ Inputs are within range -2pi to +2pi
+ false
+
+
+ report_resources_to_xml
+ report_resources_to_xml
+ false
+
+
+ fxpt_width
+ Width
+ 32
+
+
+ fxpt_fraction
+ Fraction
+ 0
+
+
+ fxpt_sign
+ Sign
+ 1
+
+
+ frequency_feedback
+ frequency_feedback
+ 157
+
+
+ latency_feedback
+ latency_feedback
+ 0
+
+
+ force_elaborate
+ force_elaborate
+ 0
+
+
+ fp_out_format
+ Output Format
+ single
+
+
+ fp_out_exp
+ Output Exponent
+ 8
+
+
+ fp_out_exp_derived
+ fp_out_exp_derived
+ 8
+
+
+ fp_out_man
+ Output Mantissa
+ 23
+
+
+ fp_out_man_derived
+ fp_out_man_derived
+ 8
+
+
+ fp_in_format
+ Input Format
+ single
+
+
+ fp_in_exp
+ Input Exponent
+ 8
+
+
+ fp_in_exp_derived
+ fp_in_exp_derived
+ 8
+
+
+ fp_in_man
+ Input Mantissa
+ 23
+
+
+ fp_in_man_derived
+ fp_in_man_derived
+ 8
+
+
+ enable_hard_fp
+ Enable Hard Floating Point
+ true
+
+
+ manual_dsp_planning
+ Enable Hard Floating Point
+ true
+
+
+ forceRegisters
+ forceRegisters
+ 1111
+
+
+ RES_DSP_param
+ Multiplies
+ 0
+
+
+ RES_LUT_param
+ LUTs
+ 1778
+
+
+ RES_MBIT_param
+ Memory Bits
+ 0
+
+
+ RES_MBLOCK_param
+ Memory Blocks
+ 0
+
+
+ selected_device_family
+ selected_device_family
+ Arria 10
+
+
+ selected_device_speedgrade
+ selected_device_speedgrade
+ 2
+
+
+ validation_failed
+ validation_failed
+ false
+
+
-
-
- device
- Device
- 10AX115N2F40E2LG
-
-
- deviceFamily
- Device family
- Arria 10
-
-
- deviceSpeedGrade
- Device Speed Grade
- 2
-
-
- generationId
- Generation Id
- 0
-
-
- bonusData
- bonusData
- bonusData
+
+
+ device
+ Device
+ 10AX115N2F40E2LG
+
+
+ deviceFamily
+ Device family
+ Arria 10
+
+
+ deviceSpeedGrade
+ Device Speed Grade
+ 2
+
+
+ generationId
+ Generation Id
+ 0
+
+
+ bonusData
+ bonusData
+ bonusData
{
element fp_functions_0
{
@@ -579,26 +616,26 @@
}
}
}
-
-
-
- hideFromIPCatalog
- Hide from IP Catalog
- true
-
-
- lockedInterfaceDefinition
- lockedInterfaceDefinition
-
-
-
- systemInfos
- systemInfos
-
-
-]]>
-
-
+
+
+
+ hideFromIPCatalog
+ Hide from IP Catalog
+ true
+
+
+ lockedInterfaceDefinition
+ lockedInterfaceDefinition
+
+
+
+ systemInfos
+ systemInfos
+ <systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>
+
+
@@ -620,5 +657,5 @@
false
false
-
-
\ No newline at end of file
+
+
\ No newline at end of file
diff --git a/generator/static/ip_cores/subfp_single.ip b/generator/static/ip_cores/subfp_single.ip
index 59f38a4..b95d27d 100644
--- a/generator/static/ip_cores/subfp_single.ip
+++ b/generator/static/ip_cores/subfp_single.ip
@@ -1,574 +1,611 @@
-
- Intel Corporation
- subfp_single
- fp_functions_0
- 17.1
-
-
- a
-
-
-
-
-
- a
-
-
- a
-
-
-
-
-
- associatedClock
- associatedClock
- clk
-
-
- associatedReset
- associatedReset
- areset
-
-
- prSafe
- Partial Reconfiguration Safe
- false
-
-
-
-
- areset
-
-
-
-
-
- reset
-
-
- areset
-
-
-
-
-
- associatedClock
- Associated clock
- clk
-
-
- synchronousEdges
- Synchronous edges
- DEASSERT
-
-
-
-
- b
-
-
-
-
-
- b
-
-
- b
-
-
-
-
-
- associatedClock
- associatedClock
- clk
-
-
- associatedReset
- associatedReset
- areset
-
-
- prSafe
- Partial Reconfiguration Safe
- false
-
-
-
-
- clk
-
-
-
-
-
- clk
-
-
- clk
-
-
-
-
-
- clockRate
- Clock rate
- 0
-
-
- externallyDriven
- Externally driven
- false
-
-
- ptfSchematicName
- PTF schematic name
-
-
-
-
-
- q
-
-
-
-
-
- q
-
-
- q
-
-
-
-
-
- associatedClock
- associatedClock
- clk
-
-
- associatedReset
- associatedReset
-
-
-
- prSafe
- Partial Reconfiguration Safe
- false
-
-
-
+
+ Intel Corporation
+ subfp_single
+ fp_functions_0
+ 19.1
+
+
+ clk
+
+
+
+
+
+
+
+ clk
+
+
+ clk
+
+
+
+
+
+
+
+
+ clockRate
+ Clock rate
+ 0
+
+
+ externallyDriven
+ Externally driven
+ false
+
+
+ ptfSchematicName
+ PTF schematic name
+
+
+
+
+
+ areset
+
+
+
+
+
+
+
+ reset
+
+
+ areset
+
+
+
+
+
+
+
+
+ associatedClock
+ Associated clock
+ clk
+
+
+ synchronousEdges
+ Synchronous edges
+ DEASSERT
+
+
+
+
+ a
+
+
+
+
+
+
+
+ a
+
+
+ a
+
+
+
+
+
+
+
+
+ associatedClock
+ associatedClock
+ clk
+
+
+ associatedReset
+ associatedReset
+ areset
+
+
+ prSafe
+ Partial Reconfiguration Safe
+ false
+
+
+
+
+ b
+
+
+
+
+
+
+
+ b
+
+
+ b
+
+
+
+
+
+
+
+
+ associatedClock
+ associatedClock
+ clk
+
+
+ associatedReset
+ associatedReset
+ areset
+
+
+ prSafe
+ Partial Reconfiguration Safe
+ false
+
+
+
+
+ q
+
+
+
+
+
+
+
+ q
+
+
+ q
+
+
+
+
+
+
+
+
+ associatedClock
+ associatedClock
+ clk
+
+
+ associatedReset
+ associatedReset
+
+
+
+ prSafe
+ Partial Reconfiguration Safe
+ false
+
+
+
-
-
- ui.blockdiagram.direction
- OUTPUT
-
-
+
+
+ ui.blockdiagram.direction
+ OUTPUT
+
+
-
-
-
-
-
-
- QUARTUS_SYNTH
- :quartus.altera.com:
- altera_fp_functions
-
- QUARTUS_SYNTH
-
-
-
-
-
- clk
-
- in
-
-
- STD_LOGIC
- QUARTUS_SYNTH
-
-
-
-
-
- areset
-
- in
-
-
- STD_LOGIC
- QUARTUS_SYNTH
-
-
-
-
-
- a
-
- in
-
- 0
- 31
-
-
-
- STD_LOGIC_VECTOR
- QUARTUS_SYNTH
-
-
-
-
-
- b
-
- in
-
- 0
- 31
-
-
-
- STD_LOGIC_VECTOR
- QUARTUS_SYNTH
-
-
-
-
-
- q
-
- out
-
- 0
- 31
-
-
-
- STD_LOGIC_VECTOR
- QUARTUS_SYNTH
-
-
-
-
-
-
-
+
+
+
+
+
+
+ QUARTUS_SYNTH
+ :quartus.altera.com:
+ QUARTUS_SYNTH
+
+
+
+
+ QUARTUS_SYNTH
+ altera_fp_functions
+
+ QUARTUS_SYNTH
+
+
+
+
+
+ clk
+
+ in
+
+
+ STD_LOGIC
+ QUARTUS_SYNTH
+
+
+
+
+
+ areset
+
+ in
+
+
+ STD_LOGIC
+ QUARTUS_SYNTH
+
+
+
+
+
+ a
+
+ in
+
+
+ 0
+ 31
+
+
+
+
+ STD_LOGIC_VECTOR
+ QUARTUS_SYNTH
+
+
+
+
+
+ b
+
+ in
+
+
+ 0
+ 31
+
+
+
+
+ STD_LOGIC_VECTOR
+ QUARTUS_SYNTH
+
+
+
+
+
+ q
+
+ out
+
+
+ 0
+ 31
+
+
+
+
+ STD_LOGIC_VECTOR
+ QUARTUS_SYNTH
+
+
+
+
+
+
+
- Intel Corporation
- subfp_single
- altera_fp_functions
- 17.1
+ Intel Corporation
+ subfp_single
+ altera_fp_functions
+ 19.1
-
-
- FUNCTION_FAMILY
- Family
- ARITH
-
-
- ARITH_function
- Name
- SUB
-
-
- CONVERT_function
- Name
- FXP_FP
-
-
- ALL_function
- Name
- ADD
-
-
- EXP_LOG_function
- Name
- EXPE
-
-
- TRIG_function
- Name
- SIN
-
-
- COMPARE_function
- Name
- MIN
-
-
- ROOTS_function
- Name
- SQRT
-
-
- derivedfunction
- derivedfunction
- SUB
-
-
- fp_format
- Format
- single
-
-
- fp_exp
- Exponent
- 8
-
-
- fp_exp_derived
- fp_exp_derived
- 8
-
-
- fp_man
- Mantissa
- 23
-
-
- fp_man_derived
- fp_man_derived
- 23
-
-
- exponent_width
- Exponent Width
- 23
-
-
- frequency_target
- Target
- 200
-
-
- latency_target
- Target
- 3
-
-
- performance_goal
- Goal
- latency
-
-
- rounding_mode
- Mode
- nearest with tie breaking away from zero
-
-
- rounding_mode_derived
- Mode
- nearest with tie breaking to even
-
-
- use_rounding_mode
- use_rounding_mode
- true
-
-
- faithful_rounding
- Relax rounding to round up or down to reduce resource usage
- false
-
-
- gen_enable
- Generate an enable port
- false
-
-
- divide_type
- Method
- 0
-
-
- select_signal_enable
- Use Select Signal
- true
-
-
- scale_by_pi
- Represent angle as multiple of Pi
- false
-
-
- number_of_inputs
- Input Vector Dimension
- 2
-
-
- trig_no_range_reduction
- Inputs are within range -2pi to +2pi
- false
-
-
- report_resources_to_xml
- report_resources_to_xml
- false
-
-
- fxpt_width
- Width
- 32
-
-
- fxpt_fraction
- Fraction
- 0
-
-
- fxpt_sign
- Sign
- 1
-
-
- frequency_feedback
- frequency_feedback
- 0
-
-
- latency_feedback
- latency_feedback
- 0
-
-
- force_elaborate
- force_elaborate
- 0
-
-
- fp_out_format
- Output Format
- single
-
-
- fp_out_exp
- Output Exponent
- 8
-
-
- fp_out_exp_derived
- fp_out_exp_derived
- 8
-
-
- fp_out_man
- Output Mantissa
- 23
-
-
- fp_out_man_derived
- fp_out_man_derived
- 8
-
-
- fp_in_format
- Input Format
- single
-
-
- fp_in_exp
- Input Exponent
- 8
-
-
- fp_in_exp_derived
- fp_in_exp_derived
- 8
-
-
- fp_in_man
- Input Mantissa
- 23
-
-
- fp_in_man_derived
- fp_in_man_derived
- 8
-
-
- enable_hard_fp
- intel_fpga_FP_FUNCTIONS
- true
-
-
- manual_dsp_planning
- intel_fpga_FP_FUNCTIONS
- true
-
-
- forceRegisters
- forceRegisters
- 1111
-
-
- RES_DSP_param
- Multiplies
- 0
-
-
- RES_LUT_param
- LUTs
- 0
-
-
- RES_MBIT_param
- Memory Bits
- 0
-
-
- RES_MBLOCK_param
- Memory Blocks
- 0
-
-
- selected_device_family
- selected_device_family
- Arria 10
-
-
- selected_device_speedgrade
- selected_device_speedgrade
- 2
-
-
- validation_failed
- validation_failed
- false
-
-
+
+
+ FUNCTION_FAMILY
+ Family
+ ARITH
+
+
+ ARITH_function
+ Name
+ SUB
+
+
+ CONVERT_function
+ Name
+ FXP_FP
+
+
+ ALL_function
+ Name
+ ADD
+
+
+ EXP_LOG_function
+ Name
+ EXPE
+
+
+ TRIG_function
+ Name
+ SIN
+
+
+ COMPARE_function
+ Name
+ MIN
+
+
+ ROOTS_function
+ Name
+ SQRT
+
+
+ derivedfunction
+ derivedfunction
+ SUB
+
+
+ fp_format
+ Format
+ single
+
+
+ fp_exp
+ Exponent
+ 8
+
+
+ fp_exp_derived
+ fp_exp_derived
+ 8
+
+
+ fp_man
+ Mantissa
+ 23
+
+
+ fp_man_derived
+ fp_man_derived
+ 23
+
+
+ exponent_width
+ Exponent Width
+ 23
+
+
+ frequency_target
+ Target
+ 200
+
+
+ latency_target
+ Target
+ 3
+
+
+ performance_goal
+ Goal
+ latency
+
+
+ rounding_mode
+ Mode
+ nearest with tie breaking away from zero
+
+
+ rounding_mode_derived
+ Mode
+ nearest with tie breaking to even
+
+
+ use_rounding_mode
+ use_rounding_mode
+ true
+
+
+ faithful_rounding
+ Relax rounding to round up or down to reduce resource usage
+ false
+
+
+ gen_enable
+ Generate an enable port
+ false
+
+
+ divide_type
+ Method
+ 0
+
+
+ select_signal_enable
+ Use Select Signal
+ true
+
+
+ scale_by_pi
+ Represent angle as multiple of Pi
+ false
+
+
+ number_of_inputs
+ Input Vector Dimension
+ 2
+
+
+ trig_no_range_reduction
+ Inputs are within range -2pi to +2pi
+ false
+
+
+ report_resources_to_xml
+ report_resources_to_xml
+ false
+
+
+ fxpt_width
+ Width
+ 32
+
+
+ fxpt_fraction
+ Fraction
+ 0
+
+
+ fxpt_sign
+ Sign
+ 1
+
+
+ frequency_feedback
+ frequency_feedback
+ 0
+
+
+ latency_feedback
+ latency_feedback
+ 0
+
+
+ force_elaborate
+ force_elaborate
+ 0
+
+
+ fp_out_format
+ Output Format
+ single
+
+
+ fp_out_exp
+ Output Exponent
+ 8
+
+
+ fp_out_exp_derived
+ fp_out_exp_derived
+ 8
+
+
+ fp_out_man
+ Output Mantissa
+ 23
+
+
+ fp_out_man_derived
+ fp_out_man_derived
+ 8
+
+
+ fp_in_format
+ Input Format
+ single
+
+
+ fp_in_exp
+ Input Exponent
+ 8
+
+
+ fp_in_exp_derived
+ fp_in_exp_derived
+ 8
+
+
+ fp_in_man
+ Input Mantissa
+ 23
+
+
+ fp_in_man_derived
+ fp_in_man_derived
+ 8
+
+
+ enable_hard_fp
+ Enable Hard Floating Point
+ true
+
+
+ manual_dsp_planning
+ Enable Hard Floating Point
+ true
+
+
+ forceRegisters
+ forceRegisters
+ 1111
+
+
+ RES_DSP_param
+ Multiplies
+ 0
+
+
+ RES_LUT_param
+ LUTs
+ 0
+
+
+ RES_MBIT_param
+ Memory Bits
+ 0
+
+
+ RES_MBLOCK_param
+ Memory Blocks
+ 0
+
+
+ selected_device_family
+ selected_device_family
+ Arria 10
+
+
+ selected_device_speedgrade
+ selected_device_speedgrade
+ 2
+
+
+ validation_failed
+ validation_failed
+ false
+
+
-
-
- device
- Device
- 10AX115N2F40E2LG
-
-
- deviceFamily
- Device family
- Arria 10
-
-
- deviceSpeedGrade
- Device Speed Grade
- 2
-
-
- generationId
- Generation Id
- 0
-
-
- bonusData
- bonusData
- bonusData
+
+
+ device
+ Device
+ 10AX115N2F40E2LG
+
+
+ deviceFamily
+ Device family
+ Arria 10
+
+
+ deviceSpeedGrade
+ Device Speed Grade
+ 2
+
+
+ generationId
+ Generation Id
+ 0
+
+
+ bonusData
+ bonusData
+ bonusData
{
element fp_functions_0
{
@@ -579,26 +616,26 @@
}
}
}
-
-
-
- hideFromIPCatalog
- Hide from IP Catalog
- true
-
-
- lockedInterfaceDefinition
- lockedInterfaceDefinition
-
-
-
- systemInfos
- systemInfos
-
-
-]]>
-
-
+
+
+
+ hideFromIPCatalog
+ Hide from IP Catalog
+ true
+
+
+ lockedInterfaceDefinition
+ lockedInterfaceDefinition
+
+
+
+ systemInfos
+ systemInfos
+ <systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>
+
+
@@ -620,5 +657,5 @@
false
false
-
-
\ No newline at end of file
+
+
\ No newline at end of file