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Tim RudyTim Rudy
Tim Rudy
authored and
Tim Rudy
committed
Change variable naming convention
1 parent b75e5e4 commit 7bf61a9

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3 files changed

+97
-97
lines changed

3 files changed

+97
-97
lines changed

‎BaudRateGenerator.v

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -17,8 +17,8 @@ localparam TX_ACC_MAX = CLOCK_RATE / (2 * BAUD_RATE);
1717
localparam RX_ACC_WIDTH = $clog2(RX_ACC_MAX);
1818
localparam TX_ACC_WIDTH = $clog2(TX_ACC_MAX);
1919

20-
reg [RX_ACC_WIDTH-1:0] rxCounter = 0;
21-
reg [TX_ACC_WIDTH-1:0] txCounter = 0;
20+
reg [RX_ACC_WIDTH-1:0] rx_counter = 0;
21+
reg [TX_ACC_WIDTH-1:0] tx_counter = 0;
2222

2323
initial begin
2424
rxClk = 1'b0;
@@ -27,19 +27,19 @@ end
2727

2828
always @(posedge clk) begin
2929
// rx clock
30-
if (rxCounter == RX_ACC_MAX[RX_ACC_WIDTH-1:0]) begin
31-
rxCounter <= 0;
32-
rxClk <= ~rxClk;
30+
if (rx_counter == RX_ACC_MAX[RX_ACC_WIDTH-1:0]) begin
31+
rx_counter <= 0;
32+
rxClk <= ~rxClk;
3333
end else begin
34-
rxCounter <= rxCounter + 1'b1;
34+
rx_counter <= rx_counter + 1'b1;
3535
end
3636

3737
// tx clock
38-
if (txCounter == TX_ACC_MAX[TX_ACC_WIDTH-1:0]) begin
39-
txCounter <= 0;
40-
txClk <= ~txClk;
38+
if (tx_counter == TX_ACC_MAX[TX_ACC_WIDTH-1:0]) begin
39+
tx_counter <= 0;
40+
txClk <= ~txClk;
4141
end else begin
42-
txCounter <= txCounter + 1'b1;
42+
tx_counter <= tx_counter + 1'b1;
4343
end
4444
end
4545

‎Uart8Receiver.v

Lines changed: 67 additions & 67 deletions
Original file line numberDiff line numberDiff line change
@@ -27,28 +27,28 @@ module Uart8Receiver (
2727
output reg [7:0] out // received data
2828
);
2929

30-
reg [2:0] state = `RESET;
31-
reg [2:0] bitIndex = 3'b0; // index for 8-bit data
32-
reg [1:0] inShiftReg = 2'b0; // shift reg for input signal conditioning
33-
reg [3:0] inHoldReg = 4'b0; // shift reg for stop signal hold time check
34-
reg [3:0] sampleCount = 4'b0; // count ticks for 16x oversample
35-
reg [3:0] validCount = 4'b0; // count ticks before clearing output data
36-
reg [7:0] receivedData = 8'b0; // storage for the deserialized data
37-
wire inSample;
30+
reg [2:0] state = `RESET;
31+
reg [2:0] bit_index = 3'b0; // index for 8-bit data
32+
reg [1:0] in_shift_reg = 2'b0; // shift reg for input signal conditioning
33+
reg [3:0] in_hold_reg = 4'b0; // shift reg for stop signal hold time check
34+
reg [3:0] sample_count = 4'b0; // count ticks for 16x oversample
35+
reg [3:0] valid_count = 4'b0; // count ticks before clearing output data
36+
reg [7:0] received_data = 8'b0; // storage for the deserialized data
37+
wire in_sample;
3838

3939
/*
4040
* Double-register the incoming data:
4141
*
4242
* This prevents metastability problems crossing into rx clock domain
4343
*
44-
* After registering, only the {inSample} wire is to be accessed - the
44+
* After registering, only the {in_sample} wire is to be accessed - the
4545
* earlier, unconditioned signal {in} must be ignored
4646
*/
4747
always @(posedge clk) begin
48-
inShiftReg <= { inShiftReg[0], in };
48+
in_shift_reg <= { in_shift_reg[0], in };
4949
end
5050

51-
assign inSample = inShiftReg[1];
51+
assign in_sample = in_shift_reg[1];
5252

5353
/*
5454
* End the validity of output data after precise time of one serial bit cycle:
@@ -61,10 +61,10 @@ assign inSample = inShiftReg[1];
6161
* from STOP_BIT state
6262
*/
6363
always @(posedge clk) begin
64-
if (|validCount) begin
65-
validCount <= validCount + 4'b1;
66-
if (&validCount) begin // reached 15 - timed output interval ends
67-
out <= 8'b0;
64+
if (|valid_count) begin
65+
valid_count <= valid_count + 4'b1;
66+
if (&valid_count) begin // reached 15 - timed output interval ends
67+
out <= 8'b0;
6868
end
6969
end
7070
end
@@ -76,14 +76,14 @@ always @(posedge clk) begin
7676

7777
case (state)
7878
`RESET: begin
79-
busy <= 1'b0;
80-
done <= 1'b0;
81-
err <= 1'b0;
82-
sampleCount <= 4'b0;
83-
receivedData <= 8'b0;
84-
out <= 8'b0;
79+
busy <= 1'b0;
80+
done <= 1'b0;
81+
err <= 1'b0;
82+
sample_count <= 4'b0;
83+
received_data <= 8'b0;
84+
out <= 8'b0;
8585
if (en) begin
86-
state <= `IDLE;
86+
state <= `IDLE;
8787
end
8888
end
8989

@@ -96,50 +96,50 @@ always @(posedge clk) begin
9696
*
9797
* Then start the count for the proceeding full baud intervals
9898
*/
99-
if (!inSample) begin
100-
sampleCount <= sampleCount + 4'b1;
101-
if (&sampleCount[2:0]) begin // reached 7
102-
busy <= 1'b1;
103-
done <= 1'b0;
104-
err <= 1'b0;
105-
sampleCount <= 4'b0; // start the full interval count over
106-
state <= `START_BIT;
99+
if (!in_sample) begin
100+
sample_count <= sample_count + 4'b1;
101+
if (&sample_count[2:0]) begin // reached 7
102+
busy <= 1'b1;
103+
done <= 1'b0;
104+
err <= 1'b0;
105+
sample_count <= 4'b0; // start the full interval count over
106+
state <= `START_BIT;
107107
end
108-
end else if (|sampleCount) begin
108+
end else if (|sample_count) begin
109109
// bit did not remain low while waiting till 7 -
110110
// remain in IDLE state
111-
err <= 1'b1;
111+
err <= 1'b1;
112112
end
113113
end
114114

115115
`START_BIT: begin
116116
/*
117117
* Wait one full baud interval to the mid-point of first bit
118118
*/
119-
sampleCount <= sampleCount + 4'b1;
120-
if (&sampleCount) begin // reached 15
121-
receivedData <= { 7'b0, inSample };
122-
out <= 8'b0;
123-
bitIndex <= 3'b1;
124-
state <= `DATA_BITS;
119+
sample_count <= sample_count + 4'b1;
120+
if (&sample_count) begin // reached 15
121+
received_data <= { 7'b0, in_sample };
122+
out <= 8'b0;
123+
bit_index <= 3'b1;
124+
state <= `DATA_BITS;
125125
end
126126
end
127127

128128
`DATA_BITS: begin
129129
/*
130130
* Take 8 baud intervals to receive serial data
131131
*/
132-
if (&sampleCount) begin // save one bit of received data
133-
sampleCount <= 4'b0;
134-
receivedData[bitIndex] <= inSample;
135-
if (&bitIndex) begin
136-
bitIndex <= 3'b0;
137-
state <= `STOP_BIT;
132+
if (&sample_count) begin // save one bit of received data
133+
sample_count <= 4'b0;
134+
received_data[bit_index] <= in_sample;
135+
if (&bit_index) begin
136+
bit_index <= 3'b0;
137+
state <= `STOP_BIT;
138138
end else begin
139-
bitIndex <= bitIndex + 3'b1;
139+
bit_index <= bit_index + 3'b1;
140140
end
141141
end else begin
142-
sampleCount <= sampleCount + 4'b1;
142+
sample_count <= sample_count + 4'b1;
143143
end
144144
end
145145

@@ -156,35 +156,35 @@ always @(posedge clk) begin
156156
* precisely in reality, accept the transition to handling the
157157
* next start bit any time after the stop bit mid-point
158158
*/
159-
inHoldReg <= { inHoldReg[2:0], inSample };
159+
in_hold_reg <= { in_hold_reg[2:0], in_sample };
160160

161-
sampleCount <= sampleCount + 4'b1;
162-
if (sampleCount[3]) begin // reached 8 to 15
161+
sample_count <= sample_count + 4'b1;
162+
if (sample_count[3]) begin // reached 8 to 15
163163
// in the second half of the baud interval
164-
if (!inSample) begin
164+
if (!in_sample) begin
165165
// accept that transmission has completed only if the stop
166166
// signal held for a time of >= 4 rx clocks before it
167167
// changed to a start signal
168-
if (&inHoldReg) begin
168+
if (&in_hold_reg) begin
169169
// can accept the transmitted data and output it
170-
done <= 1'b1;
171-
out <= receivedData;
172-
validCount <= sampleCount;
173-
sampleCount <= 4'b0;
174-
state <= `IDLE;
170+
done <= 1'b1;
171+
out <= received_data;
172+
valid_count <= sample_count;
173+
sample_count <= 4'b0;
174+
state <= `IDLE;
175175
end else begin
176176
// bit did not go high or remain high while waiting
177177
// till 8 - signal {err} for this transmit
178-
err <= 1'b1;
179-
sampleCount <= 4'b0;
180-
state <= `READY;
178+
err <= 1'b1;
179+
sample_count <= 4'b0;
180+
state <= `READY;
181181
end
182-
end else if (&sampleCount) begin // reached 15
182+
end else if (&sample_count) begin // reached 15
183183
// can accept the transmitted data and output it
184-
done <= 1'b1;
185-
out <= receivedData;
186-
sampleCount <= 4'b0;
187-
state <= `READY;
184+
done <= 1'b1;
185+
out <= received_data;
186+
sample_count <= 4'b0;
187+
state <= `READY;
188188
end
189189
end
190190
end
@@ -194,11 +194,11 @@ always @(posedge clk) begin
194194
* Wait one full bit cycle to sustain the {out} data, the
195195
* {done} signal or the {err} signal
196196
*/
197-
sampleCount <= sampleCount + 4'b1;
198-
if (&sampleCount[3:1]) begin // reached 14 -
197+
sample_count <= sample_count + 4'b1;
198+
if (&sample_count[3:1]) begin // reached 14 -
199199
// additional tick 15 comes from transitting the READY state
200200
// to the RESET state
201-
state <= `RESET;
201+
state <= `RESET;
202202
end
203203
end
204204

‎Uart8Transmitter.v

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -49,9 +49,9 @@ module Uart8Transmitter #(
4949
output reg out // tx line
5050
);
5151

52-
reg [2:0] state = `RESET;
53-
reg [7:0] inData = 8'b0; // storage for the data to transmit serially
54-
reg [2:0] bitIndex = 3'b0; // index for 8-bit data
52+
reg [2:0] state = `RESET;
53+
reg [7:0] in_data = 8'b0; // storage for the data to transmit serially
54+
reg [2:0] bit_index = 3'b0; // index for 8-bit data
5555

5656
always @(posedge clk) begin
5757
if (!en) begin
@@ -70,37 +70,37 @@ always @(posedge clk) begin
7070

7171
`IDLE: begin
7272
if (start) begin
73-
inData <= in; // register the input data
74-
state <= `START_BIT;
73+
in_data <= in; // register the input data
74+
state <= `START_BIT;
7575
end
7676
end
7777

7878
`START_BIT: begin
79-
busy <= 1'b1;
80-
done <= 1'b0;
81-
out <= 1'b0; // send the space output, aka start bit (low)
82-
bitIndex <= 3'b0;
83-
state <= `DATA_BITS;
79+
busy <= 1'b1;
80+
done <= 1'b0;
81+
out <= 1'b0; // send the space output, aka start bit (low)
82+
bit_index <= 3'b0;
83+
state <= `DATA_BITS;
8484
end
8585

8686
`DATA_BITS: begin // take 8 clock cycles for data bits to be sent
87-
out <= inData[bitIndex];
88-
if (&bitIndex) begin
89-
bitIndex <= 3'b0;
90-
state <= `STOP_BIT;
87+
out <= in_data[bit_index];
88+
if (&bit_index) begin
89+
bit_index <= 3'b0;
90+
state <= `STOP_BIT;
9191
end else begin
92-
bitIndex <= bitIndex + 1'b1;
92+
bit_index <= bit_index + 1'b1;
9393
end
9494
end
9595

9696
`STOP_BIT: begin
97-
done <= 1'b1; // signal transmission stop (one clock cycle)
98-
out <= 1'b1; // transition to the mark state output (high)
97+
done <= 1'b1; // signal transmission stop (one clock cycle)
98+
out <= 1'b1; // transition to the mark state output (high)
9999
if (TURBO_FRAMES && start) begin
100-
inData <= in; // register the input data
101-
state <= `START_BIT; // go straight to transmit
100+
in_data <= in; // register the input data
101+
state <= `START_BIT; // go straight to transmit
102102
end else begin
103-
state <= `RESET; // keep mark state (high) for one extra cycle
103+
state <= `RESET; // keep mark state (high) for one extra cycle
104104
end
105105
end
106106

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