Merge branch 'master' into feat_more_error_handling

Author: IAmMarcelJung

.gitignore

@@ -1 +1,2 @@
 demo/
+**/__pycache__

docs/source/fabric_definition.rst

@@ -266,7 +266,7 @@ specifying:
      EAST,       NULL,        4,        0,        E4e,              N    # N is used for illustration only 
      WEST,       W4b,         -4,       0,        NULL,             N    # N is used for illustration only 
  
-  The ``NULL`` port entry for the EAST source_name and the WEST destination_name will prevent FABulous from creating the corresponding tile port names. Moreover, the ``NULL`` port entries also will tell FABulous to connect *all* wires or the corresponding entry, including the nested ones, to the switch matrix. This allows the implementation of the shown U-turn routing scheme for termination but also any other more sophisticated termination scheme. 
+  The ``NULL`` port entry for the EAST source_name and the WEST destination_name will prevent FABulous from creating the corresponding tile port names. Moreover, the ``NULL`` port entries also will tell FABulous to connect *all* wires of the corresponding entry, including the nested ones, to the switch matrix. This allows the implementation of the shown U-turn routing scheme for termination but also any other more sophisticated termination scheme. 
 
   For instance, in the FlexBex project, a FABulous eFPGA was coupled with the Ibex RISC V core for custom instruction set extensions (where the eFPGA fabric operates logically in parallel to the ALU) as shown in the following figure:
 

docs/source/simulation/simulation.rst

@@ -1,49 +1,13 @@
 Simulation setup
 ================
 
-A simulation example can be found under ``$FAB_ROOT/fabric_files/fabric_icarus_example/``. This has been tested using the open source Icarus Verillog simulator.
-
-To setup the simulation enviroment, an eFPGA top module to instantiate the fabric and the `configuration module`_ are required, as in the example ``eFPGA_v2_top_sky130_sim.v``
-
-.. code-block:: verilog
-        
-        module eFPGA_top (I_top, T_top, O_top, A_config_C, B_config_C, CLK, SelfWriteStrobe, SelfWriteData, Rx, ComActive, ReceiveLED, s_clk, s_data);
-        ...
-        Config Config_inst (...);
-        //All Frame data register modules
-        ...
-        //All Frame select modules
-        ...
-        eFPGA Inst_eFPGA(
-        .Tile_X0Y1_A_I_top(I_top[23]),
-        .Tile_X0Y1_B_I_top(I_top[22]),
-        .Tile_X0Y2_A_I_top(I_top[21]),
-        .Tile_X0Y2_B_I_top(I_top[20]),
-        .Tile_X0Y3_A_I_top(I_top[19]),
-        .Tile_X0Y3_B_I_top(I_top[18]),
-        .Tile_X0Y4_A_I_top(I_top[17]),
-        .Tile_X0Y4_B_I_top(I_top[16]),
-        .Tile_X0Y5_A_I_top(I_top[15]),
-        .Tile_X0Y5_B_I_top(I_top[14]),
-        .Tile_X0Y6_A_I_top(I_top[13]),
-        .Tile_X0Y6_B_I_top(I_top[12]),
-        .Tile_X0Y7_A_I_top(I_top[11]),
-        .Tile_X0Y7_B_I_top(I_top[10]),
-        .Tile_X0Y8_A_I_top(I_top[9]),
-        .Tile_X0Y8_B_I_top(I_top[8]),
-        .Tile_X0Y9_A_I_top(I_top[7]),
-        .Tile_X0Y9_B_I_top(I_top[6]),
-        .Tile_X0Y10_A_I_top(I_top[5]),
-        .Tile_X0Y10_B_I_top(I_top[4]),
-        .Tile_X0Y11_A_I_top(I_top[3]),
-        .Tile_X0Y11_B_I_top(I_top[2]),
-        .Tile_X0Y12_A_I_top(I_top[1]),
-        .Tile_X0Y12_B_I_top(I_top[0]),
-        ...
-        );
-        endmodule
-
-Next, you can assign the input signals to ``O_top`` and the output signals to ``I_top`` under the ``fabulous_tb.v`` testbench. IO mappings are fixed for the top-level user design in the ``test_design/io_wrapper.v``. You will need to modify the number and position of bel mappings in this file if you have changed the height of the fabric from the default of 14 (2 IOs per tile give 28 IO total).
+The following series of commands can be used to easily run a simulation with a test bitstream loaded, using Icarus Verilog:
+
+.. code-block:: console
+
+        cd demo/Test
+        ./build_test_design.sh
+        ./run_simulation.sh
 
 FABulous comes with 3 different simulation methods _`configuration module`,
 

fabric_generator/model_generation_npnr.py

@@ -10,9 +10,9 @@ def genNextpnrModel(fabric: Fabric):
     belStr = []
     belv2Str = []
     belStr.append(
-        f"# BEL descriptions: bottom left corner Tile_X0Y0, top right Tile_X{fabric.numberOfColumns}Y{fabric.numberOfRows}")
+        f"# BEL descriptions: top left corner Tile_X0Y0, bottom right Tile_X{fabric.numberOfColumns}Y{fabric.numberOfRows}")
     belv2Str.append(
-        f"# BEL descriptions: bottom left corner Tile_X0Y0, top right Tile_X{fabric.numberOfColumns}Y{fabric.numberOfRows}")
+        f"# BEL descriptions: top left corner Tile_X0Y0, bottom right Tile_X{fabric.numberOfColumns}Y{fabric.numberOfRows}")
     constrainStr = []
 
     for y, row in enumerate(fabric.tile):