Develop MCS-51 IAP concept

[TG9541]

Like 8051forth, CamelForth 8051, Payne's 8051 Forth the original 8051-eForth requires a "dual mapped RAM" (i.e., addressable as XRAM or ROM). Modern MCS-51 IP cores in very-low-cost µCs and SoCs are "pure Harvard archetecture" and can't do that. Most of them lack an external bus feature. If they have it, like the CH559 it may be limited to XDATA RAM access.

Some possible approaches are:

• limitation to non-interactive use cases
• interactive use with a temporary dictionary in RAM (words can't use assembler code)
• interactive use with RAM as a "construction area" and copying to Flash ROM

Discuss and document possible solutions.