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[FEATURE] Add simulation-time width assertions to SV interfaces #128

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amykyta3 opened this issue Dec 20, 2024 · 0 comments
Open

[FEATURE] Add simulation-time width assertions to SV interfaces #128

amykyta3 opened this issue Dec 20, 2024 · 0 comments
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feature request New feature or request

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@amykyta3
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To guard against possible mis-parameterized interfaces, add simulation assertions to validate bus widths of CPUIF inputs.

  • Use $bits to compare interface data and address widths are compatible
  • Allow oversized address width
  • Require exact data width
  • Wrap with a ifndef SYNTHESIS guard
@amykyta3 amykyta3 added the feature request New feature or request label Dec 20, 2024
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