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amykyta3amykyta3
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Fixup test bitswap. mypy
1 parent 11d9f65 commit e0295ae

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7 files changed

+43
-34
lines changed

7 files changed

+43
-34
lines changed

‎src/peakrdl_regblock/entry_points.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,7 @@ def _get_name_from_dist(dist: 'Distribution') -> str:
4040
return dist.metadata["Name"]
4141

4242
else: # pragma: no cover
43-
import pkg_resources # type: ignore
43+
import pkg_resources
4444

4545
def _get_entry_points(group_name: str) -> List[Tuple['EntryPoint', 'Distribution']]:
4646
eps = []

‎src/peakrdl_regblock/field_logic/sw_onread.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@
88
from systemrdl.node import FieldNode
99

1010
class _OnRead(NextStateConditional):
11-
onreadtype = None
11+
onreadtype = None # type: OnReadType
1212
def is_match(self, field: 'FieldNode') -> bool:
1313
return field.get_property('onread') == self.onreadtype
1414

‎src/peakrdl_regblock/field_logic/sw_onwrite.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@
1010
# TODO: implement sw=w1 "write once" fields
1111

1212
class _OnWrite(NextStateConditional):
13-
onwritetype = None
13+
onwritetype = None # type: OnWriteType
1414
def is_match(self, field: 'FieldNode') -> bool:
1515
return field.is_sw_writable and field.get_property('onwrite') == self.onwritetype
1616

‎src/peakrdl_regblock/forloop_generator.py

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
from typing import TYPE_CHECKING, Optional, List, Union
22
import textwrap
33

4-
from systemrdl.walker import RDLListener, RDLWalker
4+
from systemrdl.walker import RDLListener, RDLWalker, WalkerAction
55

66
if TYPE_CHECKING:
77
from systemrdl.node import AddressableNode, Node
@@ -81,16 +81,18 @@ def get_content(self, node: 'Node') -> Optional[str]:
8181
walker.walk(node, self, skip_top=True)
8282
return self.finish()
8383

84-
def enter_AddressableComponent(self, node: 'AddressableNode') -> None:
84+
def enter_AddressableComponent(self, node: 'AddressableNode') -> Optional[WalkerAction]:
8585
if not node.is_array:
86-
return
86+
return None
8787

8888
for dim in node.array_dimensions:
8989
self.push_loop(dim)
90+
return None
9091

91-
def exit_AddressableComponent(self, node: 'AddressableNode') -> None:
92+
def exit_AddressableComponent(self, node: 'AddressableNode') -> Optional[WalkerAction]:
9293
if not node.is_array:
93-
return
94+
return None
9495

9596
for _ in node.array_dimensions:
9697
self.pop_loop()
98+
return None

‎src/peakrdl_regblock/hwif/generators.py

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -72,13 +72,13 @@ def _add_external_block_members(self, node: 'AddressableNode') -> None:
7272
self.add_member("rd_data", self.hwif.ds.cpuif_data_width)
7373
self.add_member("wr_ack")
7474

75-
def enter_Addrmap(self, node: 'AddrmapNode') -> None:
75+
def enter_Addrmap(self, node: 'AddrmapNode') -> Optional[WalkerAction]:
7676
super().enter_Addrmap(node)
7777
assert node.external
7878
self._add_external_block_members(node)
7979
return WalkerAction.SkipDescendants
8080

81-
def enter_Regfile(self, node: 'RegfileNode') -> None:
81+
def enter_Regfile(self, node: 'RegfileNode') -> Optional[WalkerAction]:
8282
super().enter_Regfile(node)
8383
if node.external:
8484
self._add_external_block_members(node)
@@ -137,7 +137,7 @@ def add_external_reg_rd_data(self, node: 'RegNode', width: int, n_subwords: int)
137137
# Multiple sub-words. Cannot generate a struct
138138
self.add_member("rd_data", width)
139139

140-
def enter_Field(self, node: 'FieldNode') -> None:
140+
def enter_Field(self, node: 'FieldNode') -> Optional[WalkerAction]:
141141
type_name = self.get_typdef_name(node)
142142
self.push_struct(type_name, kwf(node.inst_name))
143143

@@ -175,7 +175,7 @@ def enter_Field(self, node: 'FieldNode') -> None:
175175
# Implies a corresponding decrvalue input
176176
self.add_member('decrvalue', width)
177177

178-
def exit_Field(self, node: 'FieldNode') -> None:
178+
def exit_Field(self, node: 'FieldNode') -> Optional[WalkerAction]:
179179
self.pop_struct()
180180

181181

@@ -199,13 +199,13 @@ def _add_external_block_members(self, node: 'AddressableNode') -> None:
199199
self.add_member("wr_data", self.hwif.ds.cpuif_data_width)
200200
self.add_member("wr_biten", self.hwif.ds.cpuif_data_width)
201201

202-
def enter_Addrmap(self, node: 'AddrmapNode') -> None:
202+
def enter_Addrmap(self, node: 'AddrmapNode') -> Optional[WalkerAction]:
203203
super().enter_Addrmap(node)
204204
assert node.external
205205
self._add_external_block_members(node)
206206
return WalkerAction.SkipDescendants
207207

208-
def enter_Regfile(self, node: 'RegfileNode') -> None:
208+
def enter_Regfile(self, node: 'RegfileNode') -> Optional[WalkerAction]:
209209
super().enter_Regfile(node)
210210
if node.external:
211211
self._add_external_block_members(node)

‎src/peakrdl_regblock/struct_generator.py

Lines changed: 19 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
import textwrap
33
from collections import OrderedDict
44

5-
from systemrdl.walker import RDLListener, RDLWalker
5+
from systemrdl.walker import RDLListener, RDLWalker, WalkerAction
66

77
from .identifier_filter import kw_filter as kwf
88

@@ -140,31 +140,31 @@ def get_struct(self, node: 'Node', type_name: str) -> Optional[str]:
140140
return self.finish()
141141

142142

143-
def enter_Addrmap(self, node: 'AddrmapNode') -> None:
143+
def enter_Addrmap(self, node: 'AddrmapNode') -> Optional[WalkerAction]:
144144
self.push_struct(kwf(node.inst_name), node.array_dimensions)
145145

146-
def exit_Addrmap(self, node: 'AddrmapNode') -> None:
146+
def exit_Addrmap(self, node: 'AddrmapNode') -> Optional[WalkerAction]:
147147
self.pop_struct()
148148

149-
def enter_Regfile(self, node: 'RegfileNode') -> None:
149+
def enter_Regfile(self, node: 'RegfileNode') -> Optional[WalkerAction]:
150150
self.push_struct(kwf(node.inst_name), node.array_dimensions)
151151

152-
def exit_Regfile(self, node: 'RegfileNode') -> None:
152+
def exit_Regfile(self, node: 'RegfileNode') -> Optional[WalkerAction]:
153153
self.pop_struct()
154154

155-
def enter_Mem(self, node: 'MemNode') -> None:
155+
def enter_Mem(self, node: 'MemNode') -> Optional[WalkerAction]:
156156
self.push_struct(kwf(node.inst_name), node.array_dimensions)
157157

158-
def exit_Mem(self, node: 'MemNode') -> None:
158+
def exit_Mem(self, node: 'MemNode') -> Optional[WalkerAction]:
159159
self.pop_struct()
160160

161-
def enter_Reg(self, node: 'RegNode') -> None:
161+
def enter_Reg(self, node: 'RegNode') -> Optional[WalkerAction]:
162162
self.push_struct(kwf(node.inst_name), node.array_dimensions)
163163

164-
def exit_Reg(self, node: 'RegNode') -> None:
164+
def exit_Reg(self, node: 'RegNode') -> Optional[WalkerAction]:
165165
self.pop_struct()
166166

167-
def enter_Field(self, node: 'FieldNode') -> None:
167+
def enter_Field(self, node: 'FieldNode') -> Optional[WalkerAction]:
168168
self.add_member(kwf(node.inst_name), node.width)
169169

170170
#-------------------------------------------------------------------------------
@@ -228,33 +228,33 @@ def get_struct(self, node: 'Node', type_name: str) -> Optional[str]:
228228

229229
return self.finish()
230230

231-
def enter_Addrmap(self, node: 'AddrmapNode') -> None:
231+
def enter_Addrmap(self, node: 'AddrmapNode') -> Optional[WalkerAction]:
232232
type_name = self.get_typdef_name(node)
233233
self.push_struct(type_name, kwf(node.inst_name), node.array_dimensions)
234234

235-
def exit_Addrmap(self, node: 'AddrmapNode') -> None:
235+
def exit_Addrmap(self, node: 'AddrmapNode') -> Optional[WalkerAction]:
236236
self.pop_struct()
237237

238-
def enter_Regfile(self, node: 'RegfileNode') -> None:
238+
def enter_Regfile(self, node: 'RegfileNode') -> Optional[WalkerAction]:
239239
type_name = self.get_typdef_name(node)
240240
self.push_struct(type_name, kwf(node.inst_name), node.array_dimensions)
241241

242-
def exit_Regfile(self, node: 'RegfileNode') -> None:
242+
def exit_Regfile(self, node: 'RegfileNode') -> Optional[WalkerAction]:
243243
self.pop_struct()
244244

245-
def enter_Mem(self, node: 'MemNode') -> None:
245+
def enter_Mem(self, node: 'MemNode') -> Optional[WalkerAction]:
246246
type_name = self.get_typdef_name(node)
247247
self.push_struct(type_name, kwf(node.inst_name), node.array_dimensions)
248248

249-
def exit_Mem(self, node: 'MemNode') -> None:
249+
def exit_Mem(self, node: 'MemNode') -> Optional[WalkerAction]:
250250
self.pop_struct()
251251

252-
def enter_Reg(self, node: 'RegNode') -> None:
252+
def enter_Reg(self, node: 'RegNode') -> Optional[WalkerAction]:
253253
type_name = self.get_typdef_name(node)
254254
self.push_struct(type_name, kwf(node.inst_name), node.array_dimensions)
255255

256-
def exit_Reg(self, node: 'RegNode') -> None:
256+
def exit_Reg(self, node: 'RegNode') -> Optional[WalkerAction]:
257257
self.pop_struct()
258258

259-
def enter_Field(self, node: 'FieldNode') -> None:
259+
def enter_Field(self, node: 'FieldNode') -> Optional[WalkerAction]:
260260
self.add_member(kwf(node.inst_name), node.width)

‎tests/lib/tb_base.sv

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,14 @@ module tb;
33
timeunit 10ps;
44
timeprecision 1ps;
55

6-
`define bitswap(x) ($bits(x))'({<<{x}})
6+
class bitswap_cls #(W=1);
7+
static function logic [W-1:0] bitswap(logic [W-1:0] x);
8+
logic [W-1:0] result;
9+
result = {<<{x}};
10+
return result;
11+
endfunction
12+
endclass
13+
`define bitswap(x) (bitswap_cls#($bits(x))::bitswap(x))
714

815
logic rst = '1;
916
logic clk = '0;

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