From 6d7bd9516632a3523fa68aa8996b03c2cb73a4d1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E6=A2=81=E6=A3=AE=20Liang=20Sen?= Date: Sun, 8 Oct 2023 09:55:44 +0800 Subject: [PATCH] Update README.md --- README.md | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/README.md b/README.md index 63da847b491..ce67d199c51 100644 --- a/README.md +++ b/README.md @@ -90,15 +90,15 @@ make idea ### Run with simulator * Install [Verilator](https://verilator.org/guide/latest/), the open-source Verilog simulator. -* Run `make emu` to build the C++ simulator `./build/emu` with Verilator. -* Refer to `./build/emu --help` for run-time arguments of the simulator. +* Run `make emu_rtl` to build the C++ simulator `./sim/emu/comp/emu` with Verilator. +* Refer to `./sim/emu/comp/emu --help` for run-time arguments of the simulator. * Refer to `Makefile` and `verilator.mk` for more information. Example: ```bash -make emu CONFIG=MinimalConfig EMU_THREADS=2 -j10 -./build/emu -b 0 -e 0 -i ./ready-to-run/coremark-2-iteration.bin --diff ./ready-to-run/riscv64-nemu-interpreter-so +make emu_rtl -j32 +make emu_rtl-run RUN_BIN=coremark-3-iteration.bin ``` ## Troubleshooting Guide @@ -107,12 +107,13 @@ make emu CONFIG=MinimalConfig EMU_THREADS=2 -j10 ## Acknowledgement -In the development of XiangShan, some sub-modules from the open-source community are employed. All relevant usage is listed below. +In the development of XiangShan, some components from the open-source community are employed. All relevant usage is listed below. -| Sub-module | Source | Detail | -| ------------------ | ------------------------------------------------------------ | ------------------------------------------------------------ | -| L2 Cache/LLC | [Sifive block-inclusivecache](https://github.com/ucb-bar/block-inclusivecache-sifive) | Our new L2/L3 design are inspired by Sifive's `block-inclusivecache`. | -| Diplomacy/TileLink | [Rocket-chip](https://github.com/chipsalliance/rocket-chip) | We reused the Diplomacy framework and TileLink utility that exist in rocket-chip to negotiate bus. | +| Sub-module | Source | Detail | +|----------------------|---------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------| +| L2 Cache/LLC | [Sifive block-inclusivecache](https://github.com/ucb-bar/block-inclusivecache-sifive) | Our new L2/L3 design are inspired by Sifive's `block-inclusivecache`. | +| Diplomacy/TileLink | [Rocket-chip](https://github.com/chipsalliance/rocket-chip) | We reused the Diplomacy framework and TileLink utility that exist in rocket-chip to negotiate bus. | +| Vector Function Unit | [riscv-vector](https://github.com/IntelLabs/riscv-vector) | We reused vector function units in Intel's VPU| We are grateful for the support of the open-source community and encourage other open-source projects to reuse our code within the scope of the [license](LICENSE).