ZJIT: Don't leave gaps on the native stack when saving register for CCalls

[XrXr]

LIR uses CPush to preserve values around C calls, which on A64 is a STP X1, X1, [SP, #-16]!, using 16 bytes per 8 byte value.

ruby/zjit/src/backend/lir.rs

Lines 1605 to 1613 in 2f151e7

	// Save live registers
	for &(reg, _) in saved_regs.iter() {
	asm.cpush(Opnd::Reg(reg));
	pool.dealloc_opnd(&Opnd::Reg(reg));
	}
	// On x86_64, maintain 16-byte stack alignment
	if cfg!(target_arch = "x86_64") && saved_regs.len() % 2 == 1 {
	asm.cpush(Opnd::Reg(saved_regs.last().unwrap().0));
	}

Addressing this might involve adding a new CPushPair LIR instruction because of the distance between this cross platform code and the A64 backend, where STP can be directly emitted.