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sths34pf80_reg.c
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/**
******************************************************************************
* @file sths34pf80_reg.c
* @author Sensors Software Solution Team
* @brief STHS34PF80 driver file
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2021 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
#include "sths34pf80_reg.h"
/*
* Prototypes of routines used only throughout this driver and not exported
* outside as APIs
*/
typedef struct
{
uint8_t int_pulsed : 1;
uint8_t comp_type : 1;
uint8_t sel_abs : 1;
} sths34pf80_algo_config_t;
static int32_t sths34pf80_reset_algo_bit_set(const stmdev_ctx_t *ctx);
static int32_t sths34pf80_algo_config_get(const stmdev_ctx_t *ctx, sths34pf80_algo_config_t *val);
static int32_t sths34pf80_algo_config_set(const stmdev_ctx_t *ctx, sths34pf80_algo_config_t val);
static int32_t sths34pf80_safe_power_down(const stmdev_ctx_t *ctx, sths34pf80_ctrl1_t *ctrl1);
static int32_t sths34pf80_odr_safe_set(const stmdev_ctx_t *ctx,
sths34pf80_ctrl1_t *ctrl1,
uint8_t odr_new);
/**
* @defgroup STHS34PF80
* @brief This file provides a set of functions needed to drive the
* sths34pf80 enhanced inertial module.
* @{
*
*/
/**
* @defgroup Interfaces functions
* @brief This section provide a set of functions used to read and
* write a generic register of the device.
* MANDATORY: return 0 -> no Error.
* @{
*
*/
#ifndef __weak
#define __weak __attribute__((weak))
#endif /* __weak */
/**
* @brief Read generic device register
*
* @param ctx communication interface handler.(ptr)
* @param reg first register address to read.
* @param data buffer for data read.(ptr)
* @param len number of consecutive register to read.
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t __weak sths34pf80_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
uint8_t *data,
uint16_t len)
{
int32_t ret;
if (ctx == NULL)
{
return -1;
}
ret = ctx->read_reg(ctx->handle, reg, data, len);
return ret;
}
/**
* @brief Write generic device register
*
* @param ctx communication interface handler.(ptr)
* @param reg first register address to write.
* @param data the buffer contains data to be written.(ptr)
* @param len number of consecutive register to write.
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t __weak sths34pf80_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
uint8_t *data,
uint16_t len)
{
int32_t ret;
if (ctx == NULL)
{
return -1;
}
ret = ctx->write_reg(ctx->handle, reg, data, len);
return ret;
}
/**
* @}
*
*/
/**
* @defgroup Common
* @brief Common
* @{/
*
*/
/**
* @brief Device ID.[get]
*
* @param ctx read / write interface definitions
* @param val Device ID.
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t sths34pf80_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val)
{
int32_t ret;
ret = sths34pf80_read_reg(ctx, STHS34PF80_WHO_AM_I, val, 1);
return ret;
}
/**
* @brief Select number of averages for object temperature.[set]
*
* @param ctx read / write interface definitions
* @param val AVG_TMOS_2, AVG_TMOS_8, AVG_TMOS_32, AVG_TMOS_128, AVG_TMOS_256, AVG_TMOS_512, AVG_TMOS_1024, AVG_TMOS_2048,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t sths34pf80_avg_tobject_num_set(const stmdev_ctx_t *ctx, sths34pf80_avg_tobject_num_t val)
{
sths34pf80_avg_trim_t avg_trim;
int32_t ret;
ret = sths34pf80_read_reg(ctx, STHS34PF80_AVG_TRIM, (uint8_t *)&avg_trim, 1);
if (ret == 0)
{
avg_trim.avg_tmos = ((uint8_t)val & 0x7U);
ret = sths34pf80_write_reg(ctx, STHS34PF80_AVG_TRIM, (uint8_t *)&avg_trim, 1);
}
return ret;
}
/**
* @brief Select number of averages for object temperature.[get]
*
* @param ctx read / write interface definitions
* @param val AVG_TMOS_2, AVG_TMOS_8, AVG_TMOS_32, AVG_TMOS_128, AVG_TMOS_256, AVG_TMOS_512, AVG_TMOS_1024, AVG_TMOS_2048,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t sths34pf80_avg_tobject_num_get(const stmdev_ctx_t *ctx, sths34pf80_avg_tobject_num_t *val)
{
sths34pf80_avg_trim_t avg_trim;
int32_t ret;
ret = sths34pf80_read_reg(ctx, STHS34PF80_AVG_TRIM, (uint8_t *)&avg_trim, 1);
switch (avg_trim.avg_tmos)
{
case STHS34PF80_AVG_TMOS_2:
*val = STHS34PF80_AVG_TMOS_2;
break;
case STHS34PF80_AVG_TMOS_8:
*val = STHS34PF80_AVG_TMOS_8;
break;
case STHS34PF80_AVG_TMOS_32:
*val = STHS34PF80_AVG_TMOS_32;
break;
case STHS34PF80_AVG_TMOS_128:
*val = STHS34PF80_AVG_TMOS_128;
break;
case STHS34PF80_AVG_TMOS_256:
*val = STHS34PF80_AVG_TMOS_256;
break;
case STHS34PF80_AVG_TMOS_512:
*val = STHS34PF80_AVG_TMOS_512;
break;
case STHS34PF80_AVG_TMOS_1024:
*val = STHS34PF80_AVG_TMOS_1024;
break;
case STHS34PF80_AVG_TMOS_2048:
*val = STHS34PF80_AVG_TMOS_2048;
break;
default:
*val = STHS34PF80_AVG_TMOS_2;
break;
}
return ret;
}
/**
* @brief Select number of averages for ambient temperature.[set]
*
* @param ctx read / write interface definitions
* @param val AVG_T_8, AVG_T_4, AVG_T_2, AVG_T_1,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t sths34pf80_avg_tambient_num_set(const stmdev_ctx_t *ctx, sths34pf80_avg_tambient_num_t val)
{
sths34pf80_avg_trim_t avg_trim;
int32_t ret;
ret = sths34pf80_read_reg(ctx, STHS34PF80_AVG_TRIM, (uint8_t *)&avg_trim, 1);
if (ret == 0)
{
avg_trim.avg_t = ((uint8_t)val & 0x3U);
ret = sths34pf80_write_reg(ctx, STHS34PF80_AVG_TRIM, (uint8_t *)&avg_trim, 1);
}
return ret;
}
/**
* @brief Select number of averages for ambient temperature.[get]
*
* @param ctx read / write interface definitions
* @param val AVG_T_8, AVG_T_4, AVG_T_2, AVG_T_1,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t sths34pf80_avg_tambient_num_get(const stmdev_ctx_t *ctx, sths34pf80_avg_tambient_num_t *val)
{
sths34pf80_avg_trim_t avg_trim;
int32_t ret;
ret = sths34pf80_read_reg(ctx, STHS34PF80_AVG_TRIM, (uint8_t *)&avg_trim, 1);
switch (avg_trim.avg_t)
{
case STHS34PF80_AVG_T_8:
*val = STHS34PF80_AVG_T_8;
break;
case STHS34PF80_AVG_T_4:
*val = STHS34PF80_AVG_T_4;
break;
case STHS34PF80_AVG_T_2:
*val = STHS34PF80_AVG_T_2;
break;
case STHS34PF80_AVG_T_1:
*val = STHS34PF80_AVG_T_1;
break;
default:
*val = STHS34PF80_AVG_T_8;
break;
}
return ret;
}
/**
* @brief temperature range.[set]
*
* @param ctx read / write interface definitions
* @param val range: GAIN_WIDE_MODE, GAIN_DEFAULT_MODE
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t sths34pf80_gain_mode_set(const stmdev_ctx_t *ctx, sths34pf80_gain_mode_t val)
{
sths34pf80_ctrl0_t ctrl0;
int32_t ret;
ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL0, (uint8_t *)&ctrl0, 1);
if (ret == 0)
{
ctrl0.gain = (uint8_t)val;
ret = sths34pf80_write_reg(ctx, STHS34PF80_CTRL0, (uint8_t *)&ctrl0, 1);
}
return ret;
}
/**
* @brief temperature range.[get]
*
* @param ctx read / write interface definitions
* @param val range: GAIN_WIDE_MODE, GAIN_DEFAULT_MODE
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t sths34pf80_gain_mode_get(const stmdev_ctx_t *ctx, sths34pf80_gain_mode_t *val)
{
sths34pf80_ctrl0_t ctrl0;
int32_t ret;
ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL0, (uint8_t *)&ctrl0, 1);
switch (ctrl0.gain)
{
case STHS34PF80_GAIN_WIDE_MODE:
*val = STHS34PF80_GAIN_WIDE_MODE;
break;
case STHS34PF80_GAIN_DEFAULT_MODE:
*val = STHS34PF80_GAIN_DEFAULT_MODE;
break;
default:
*val = STHS34PF80_GAIN_DEFAULT_MODE;
break;
}
return ret;
}
/**
* @brief sensitivity data.[set]
*
* @param ctx read / write interface definitions
* @param val IN: desired sensitivity value
* OUT: rounded sensitivity value
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t sths34pf80_tobject_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t *val)
{
sths34pf80_sens_data_t data;
int32_t ret;
data.sens = (*val >= 2048U) ?
(*val - 2048U + 8U) / 16U :
(*val - 2048U - 8U) / 16U;
ret = sths34pf80_write_reg(ctx, STHS34PF80_SENS_DATA, (uint8_t *)&data, 1);
*val = (int8_t)data.sens * 16U + 2048U;
return ret;
}
/**
* @brief sensitivity data.[get]
*
* @param ctx read / write interface definitions
* @param val rounded sensitivity value
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t sths34pf80_tobject_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val)
{
sths34pf80_sens_data_t data;
int32_t ret;
ret = sths34pf80_read_reg(ctx, STHS34PF80_SENS_DATA, (uint8_t *)&data, 1);
*val = (int8_t)data.sens * 16 + 2048;
return ret;
}
/**
* @brief Enter to power-down in a safe way
*
* @param ctx read / write interface definitions
* @param ctrl1 Pointer to CTRL1 register
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
static int32_t sths34pf80_safe_power_down(const stmdev_ctx_t *ctx, sths34pf80_ctrl1_t *ctrl1)
{
sths34pf80_func_status_t func_status;
sths34pf80_drdy_status_t status;
int32_t ret;
/* if sensor is already in power-down then do nothing */
if (ctrl1->odr == 0U)
{
return 0;
}
/* reset the DRDY bit */
ret = sths34pf80_read_reg(ctx, STHS34PF80_FUNC_STATUS, (uint8_t *)&func_status, 1);
/* wait DRDY bit go to '1'. Maximum wait may be up to 4 sec (0.25 Hz) */
uint16_t retry = 0U;
do
{
ret += sths34pf80_drdy_status_get(ctx, &status);
ctx->mdelay(1);
} while (status.drdy == 0U && retry++ < 4000U);
if (ret != 0 || retry >= 4000U)
{
return -1;
};
/* perform power-down */
ctrl1->odr = 0U;
ret += sths34pf80_write_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)ctrl1, 1);
/* reset the DRDY bit */
ret += sths34pf80_read_reg(ctx, STHS34PF80_FUNC_STATUS, (uint8_t *)&func_status, 1);
return ret;
}
/**
* @brief Change odr in a safe way
*
* @param ctx read / write interface definitions
* @param ctrl1 Pointer to CTRL1 register
* @param odr_new Value of new odr to be set
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
static int32_t sths34pf80_odr_safe_set(const stmdev_ctx_t *ctx,
sths34pf80_ctrl1_t *ctrl1,
uint8_t odr_new)
{
int32_t ret;
/* perform power-down transition in a safe way. */
ret = sths34pf80_safe_power_down(ctx, ctrl1);
if (odr_new > 0U)
{
/*
* Do a clean reset algo procedure everytime odr is changed to an
* operative state.
*/
ret += sths34pf80_reset_algo_bit_set(ctx);
/* set new odr */
ctrl1->odr = (odr_new & 0xfU);
ret += sths34pf80_write_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)ctrl1, 1);
}
return ret;
}
/**
* @brief Selects the tmos odr.[set]
*
* @param ctx read / write interface definitions
* @param val ODR_OFF, ODR_AT_0Hz25, ODR_AT_0Hz50, ODR_1Hz, ODR_2Hz, ODR_4Hz, ODR_8Hz, ODR_15Hz, ODR_30Hz,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t sths34pf80_odr_set(const stmdev_ctx_t *ctx, sths34pf80_odr_t val)
{
sths34pf80_ctrl1_t ctrl1;
sths34pf80_avg_trim_t avg_trim;
sths34pf80_odr_t max_odr = STHS34PF80_ODR_AT_30Hz;
int32_t ret;
ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1);
if (ret == 0)
{
ret = sths34pf80_read_reg(ctx, STHS34PF80_AVG_TRIM, (uint8_t *)&avg_trim, 1);
switch (avg_trim.avg_tmos)
{
default:
case STHS34PF80_AVG_TMOS_2:
case STHS34PF80_AVG_TMOS_8:
case STHS34PF80_AVG_TMOS_32:
max_odr = STHS34PF80_ODR_AT_30Hz;
break;
case STHS34PF80_AVG_TMOS_128:
max_odr = STHS34PF80_ODR_AT_8Hz;
break;
case STHS34PF80_AVG_TMOS_256:
max_odr = STHS34PF80_ODR_AT_4Hz;
break;
case STHS34PF80_AVG_TMOS_512:
max_odr = STHS34PF80_ODR_AT_2Hz;
break;
case STHS34PF80_AVG_TMOS_1024:
max_odr = STHS34PF80_ODR_AT_1Hz;
break;
case STHS34PF80_AVG_TMOS_2048:
max_odr = STHS34PF80_ODR_AT_0Hz50;
break;
}
}
if (ret == 0)
{
if (val > max_odr)
{
return -1;
}
ret = sths34pf80_odr_safe_set(ctx, &ctrl1, (uint8_t)val);
}
return ret;
}
/**
* @brief Selects the tmos odr.[get]
*
* @param ctx read / write interface definitions
* @param val ODR_OFF, ODR_AT_0Hz25, ODR_AT_0Hz50, ODR_1Hz, ODR_2Hz, ODR_4Hz, ODR_8Hz, ODR_15Hz, ODR_30Hz,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t sths34pf80_odr_get(const stmdev_ctx_t *ctx, sths34pf80_odr_t *val)
{
sths34pf80_ctrl1_t ctrl1;
int32_t ret;
ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1);
switch (ctrl1.odr)
{
case STHS34PF80_ODR_OFF:
*val = STHS34PF80_ODR_OFF;
break;
case STHS34PF80_ODR_AT_0Hz25:
*val = STHS34PF80_ODR_AT_0Hz25;
break;
case STHS34PF80_ODR_AT_0Hz50:
*val = STHS34PF80_ODR_AT_0Hz50;
break;
case STHS34PF80_ODR_AT_1Hz:
*val = STHS34PF80_ODR_AT_1Hz;
break;
case STHS34PF80_ODR_AT_2Hz:
*val = STHS34PF80_ODR_AT_2Hz;
break;
case STHS34PF80_ODR_AT_4Hz:
*val = STHS34PF80_ODR_AT_4Hz;
break;
case STHS34PF80_ODR_AT_8Hz:
*val = STHS34PF80_ODR_AT_8Hz;
break;
case STHS34PF80_ODR_AT_15Hz:
*val = STHS34PF80_ODR_AT_15Hz;
break;
case STHS34PF80_ODR_AT_30Hz:
*val = STHS34PF80_ODR_AT_30Hz;
break;
default:
*val = STHS34PF80_ODR_OFF;
break;
}
return ret;
}
/**
* @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [set]
*
* @param ctx read / write interface definitions
* @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read).
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t sths34pf80_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val)
{
sths34pf80_ctrl1_t ctrl1;
int32_t ret;
ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1);
if (ret == 0)
{
ctrl1.bdu = val;
ret = sths34pf80_write_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1);
}
return ret;
}
/**
* @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [get]
*
* @param ctx read / write interface definitions
* @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read).
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t sths34pf80_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val)
{
sths34pf80_ctrl1_t ctrl1;
int32_t ret;
ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1);
*val = ctrl1.bdu;
return ret;
}
/**
* @brief Selects data output mode.[set]
*
* @param ctx read / write interface definitions
* @param val IDLE_MODE, ONE_SHOT
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t sths34pf80_one_shot_set(const stmdev_ctx_t *ctx, sths34pf80_one_shot_t val)
{
sths34pf80_ctrl2_t ctrl2;
int32_t ret;
ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL2, (uint8_t *)&ctrl2, 1);
if (ret == 0)
{
ctrl2.one_shot = ((uint8_t)val & 0x1U);
ret = sths34pf80_write_reg(ctx, STHS34PF80_CTRL2, (uint8_t *)&ctrl2, 1);
}
return ret;
}
/**
* @brief Selects data output mode.[get]
*
* @param ctx read / write interface definitions
* @param val IDLE_MODE, ONE_SHOT
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t sths34pf80_one_shot_get(const stmdev_ctx_t *ctx, sths34pf80_one_shot_t *val)
{
sths34pf80_ctrl2_t ctrl2;
int32_t ret;
ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL2, (uint8_t *)&ctrl2, 1);
switch (ctrl2.one_shot)
{
case STHS34PF80_IDLE_MODE:
*val = STHS34PF80_IDLE_MODE;
break;
case STHS34PF80_ONE_SHOT:
*val = STHS34PF80_ONE_SHOT;
break;
default:
*val = STHS34PF80_IDLE_MODE;
break;
}
return ret;
}
/**
* @brief Change memory bank.[set]
*
* @param ctx read / write interface definitions
* @param val MAIN_MEM_BANK, EMBED_FUNC_MEM_BANK, SENSOR_HUB_MEM_BANK, STRED_MEM_BANK,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t sths34pf80_mem_bank_set(const stmdev_ctx_t *ctx, sths34pf80_mem_bank_t val)
{
sths34pf80_ctrl2_t ctrl2;
int32_t ret;
ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL2, (uint8_t *)&ctrl2, 1);
if (ret == 0)
{
ctrl2.func_cfg_access = ((uint8_t)val & 0x1U);
ret = sths34pf80_write_reg(ctx, STHS34PF80_CTRL2, (uint8_t *)&ctrl2, 1);
}
return ret;
}
/**
* @brief Change memory bank.[get]
*
* @param ctx read / write interface definitions
* @param val MAIN_MEM_BANK, EMBED_FUNC_MEM_BANK, SENSOR_HUB_MEM_BANK, STRED_MEM_BANK,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t sths34pf80_mem_bank_get(const stmdev_ctx_t *ctx, sths34pf80_mem_bank_t *val)
{
sths34pf80_ctrl2_t ctrl2;
int32_t ret;
ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL2, (uint8_t *)&ctrl2, 1);
switch (ctrl2.func_cfg_access)
{
case STHS34PF80_MAIN_MEM_BANK:
*val = STHS34PF80_MAIN_MEM_BANK;
break;
case STHS34PF80_EMBED_FUNC_MEM_BANK:
*val = STHS34PF80_EMBED_FUNC_MEM_BANK;
break;
default:
*val = STHS34PF80_MAIN_MEM_BANK;
break;
}
return ret;
}
/**
* @brief Global reset of the device.[set]
*
* @param ctx read / write interface definitions
* @param val READY, RESTORE_CTRL_REGS,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t sths34pf80_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
{
sths34pf80_ctrl2_t ctrl2;
int32_t ret;
ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL2, (uint8_t *)&ctrl2, 1);
if (ret == 0)
{
ctrl2.boot = val;
ret = sths34pf80_write_reg(ctx, STHS34PF80_CTRL2, (uint8_t *)&ctrl2, 1);
}
return ret;
}
/**
* @brief Global reset of the device.[get]
*
* @param ctx read / write interface definitions
* @param val READY, RESTORE_CTRL_REGS,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t sths34pf80_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
{
sths34pf80_ctrl2_t ctrl2;
int32_t ret;
ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL2, (uint8_t *)&ctrl2, 1);
*val = ctrl2.boot;
return ret;
}
/**
* @brief status of drdy.[get]
*
* @param ctx read / write interface definitions
* @param val status of drdy bit (TAMB, TOBJ, TAMB_SHOCK, TPRESENCE, TMOTION).
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t sths34pf80_drdy_status_get(const stmdev_ctx_t *ctx, sths34pf80_drdy_status_t *val)
{
sths34pf80_status_t status;
int32_t ret;
ret = sths34pf80_read_reg(ctx, STHS34PF80_STATUS, (uint8_t *)&status, 1);
val->drdy = status.drdy;
return ret;
}
/**
* @brief status of internal functions.[get]
*
* @param ctx read / write interface definitions
* @param val status of internal functions.
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t sths34pf80_func_status_get(const stmdev_ctx_t *ctx, sths34pf80_func_status_t *val)
{
sths34pf80_func_status_t func_status;
int32_t ret;
ret = sths34pf80_read_reg(ctx, STHS34PF80_FUNC_STATUS, (uint8_t *)&func_status, 1);
val->tamb_shock_flag = func_status.tamb_shock_flag;
val->mot_flag = func_status.mot_flag;
val->pres_flag = func_status.pres_flag;
return ret;
}
/**
* @brief Object temperature output register.[get]
*
* @param ctx read / write interface definitions
* @param val Object temperature output register.
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t sths34pf80_tobject_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
{
uint8_t buff[2];
int32_t ret;
ret = sths34pf80_read_reg(ctx, STHS34PF80_TOBJECT_L, &buff[0], 2);
*val = (int16_t)buff[1];
*val = (*val * 256) + (int16_t)buff[0];
return ret;
}
/**
* @brief Ambient temperature output register.[get]
*
* @param ctx read / write interface definitions
* @param val Ambient temperature output register.
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t sths34pf80_tambient_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
{
uint8_t buff[2];
int32_t ret;
ret = sths34pf80_read_reg(ctx, STHS34PF80_TAMBIENT_L, &buff[0], 2);
*val = (int16_t)buff[1];
*val = (*val * 256) + (int16_t)buff[0];
return ret;
}
/**
* @brief Object compensation output register.[get]
*
* @param ctx read / write interface definitions
* @param val Object compensation output register.
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t sths34pf80_tobj_comp_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
{
uint8_t buff[2];
int32_t ret;
ret = sths34pf80_read_reg(ctx, STHS34PF80_TOBJ_COMP_L, &buff[0], 2);
*val = (int16_t)buff[1];
*val = (*val * 256) + (int16_t)buff[0];
return ret;
}
/**
* @brief Presence algo data output register.[get]
*
* @param ctx read / write interface definitions
* @param val Presence algo data output register.
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t sths34pf80_tpresence_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
{
uint8_t buff[2];
int32_t ret;
ret = sths34pf80_read_reg(ctx, STHS34PF80_TPRESENCE_L, &buff[0], 2);
*val = (int16_t)buff[1];
*val = (*val * 256) + (int16_t)buff[0];
return ret;
}
/**
* @brief Motion algo data output register.[get]
*
* @param ctx read / write interface definitions
* @param val Motion algo data output register.
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t sths34pf80_tmotion_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
{
uint8_t buff[2];
int32_t ret;
ret = sths34pf80_read_reg(ctx, STHS34PF80_TMOTION_L, &buff[0], 2);
*val = (int16_t)buff[1];
*val = (*val * 256) + (int16_t)buff[0];
return ret;
}
/**
* @brief Temperature ambient shock algo data output register.[get]
*
* @param ctx read / write interface definitions
* @param val Temperature ambient shock algo data output register.
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t sths34pf80_tamb_shock_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
{
uint8_t buff[2];
int32_t ret;
ret = sths34pf80_read_reg(ctx, STHS34PF80_TAMB_SHOCK_L, &buff[0], 2);
*val = (int16_t)buff[1];
*val = (*val * 256) + (int16_t)buff[0];
return ret;
}
/**
* @}
*
*/
/**
* @defgroup Filters
* @brief Filters
* @{/
*
*/
/**
* @brief low-pass filter configuration.[set]
*
* @param ctx read / write interface definitions
* @param val LPF_ODR_DIV_9, LPF_ODR_DIV_20, LPF_ODR_DIV_50, LPF_ODR_DIV_100, LPF_ODR_DIV_200, LPF_ODR_DIV_400, LPF_ODR_DIV_800,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t sths34pf80_lpf_m_bandwidth_set(const stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t val)
{
sths34pf80_lpf1_t lpf1;
int32_t ret;
ret = sths34pf80_read_reg(ctx, STHS34PF80_LPF1, (uint8_t *)&lpf1, 1);
if (ret == 0)
{
lpf1.lpf_m = ((uint8_t)val & 0x7U);
ret = sths34pf80_write_reg(ctx, STHS34PF80_LPF1, (uint8_t *)&lpf1, 1);
}
return ret;
}
/**
* @brief low-pass filter configuration.[get]
*
* @param ctx read / write interface definitions
* @param val LPF_ODR_DIV_9, LPF_ODR_DIV_20, LPF_ODR_DIV_50, LPF_ODR_DIV_100, LPF_ODR_DIV_200, LPF_ODR_DIV_400, LPF_ODR_DIV_800,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t sths34pf80_lpf_m_bandwidth_get(const stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t *val)
{
sths34pf80_lpf1_t lpf1;
int32_t ret;