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Copy pathSingle_Cycle_RISC_Processor.sta.rpt
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Single_Cycle_RISC_Processor.sta.rpt
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TimeQuest Timing Analyzer report for Single_Cycle_RISC_Processor
Sun Dec 15 22:39:11 2024
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. TimeQuest Timing Analyzer Summary
3. Parallel Compilation
4. SDC File List
5. Clocks
6. Slow 1200mV 85C Model Fmax Summary
7. Timing Closure Recommendations
8. Slow 1200mV 85C Model Setup Summary
9. Slow 1200mV 85C Model Hold Summary
10. Slow 1200mV 85C Model Recovery Summary
11. Slow 1200mV 85C Model Removal Summary
12. Slow 1200mV 85C Model Minimum Pulse Width Summary
13. Slow 1200mV 85C Model Setup: 'CLOCK_50'
14. Slow 1200mV 85C Model Hold: 'CLOCK_50'
15. Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50'
16. Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK2_50'
17. Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK3_50'
18. Setup Times
19. Hold Times
20. Clock to Output Times
21. Minimum Clock to Output Times
22. Slow 1200mV 85C Model Metastability Report
23. Slow 1200mV 0C Model Fmax Summary
24. Slow 1200mV 0C Model Setup Summary
25. Slow 1200mV 0C Model Hold Summary
26. Slow 1200mV 0C Model Recovery Summary
27. Slow 1200mV 0C Model Removal Summary
28. Slow 1200mV 0C Model Minimum Pulse Width Summary
29. Slow 1200mV 0C Model Setup: 'CLOCK_50'
30. Slow 1200mV 0C Model Hold: 'CLOCK_50'
31. Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'
32. Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK2_50'
33. Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK3_50'
34. Setup Times
35. Hold Times
36. Clock to Output Times
37. Minimum Clock to Output Times
38. Slow 1200mV 0C Model Metastability Report
39. Fast 1200mV 0C Model Setup Summary
40. Fast 1200mV 0C Model Hold Summary
41. Fast 1200mV 0C Model Recovery Summary
42. Fast 1200mV 0C Model Removal Summary
43. Fast 1200mV 0C Model Minimum Pulse Width Summary
44. Fast 1200mV 0C Model Setup: 'CLOCK_50'
45. Fast 1200mV 0C Model Hold: 'CLOCK_50'
46. Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'
47. Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK2_50'
48. Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK3_50'
49. Setup Times
50. Hold Times
51. Clock to Output Times
52. Minimum Clock to Output Times
53. Fast 1200mV 0C Model Metastability Report
54. Multicorner Timing Analysis Summary
55. Setup Times
56. Hold Times
57. Clock to Output Times
58. Minimum Clock to Output Times
59. Board Trace Model Assignments
60. Input Transition Times
61. Signal Integrity Metrics (Slow 1200mv 0c Model)
62. Signal Integrity Metrics (Slow 1200mv 85c Model)
63. Signal Integrity Metrics (Fast 1200mv 0c Model)
64. Setup Transfers
65. Hold Transfers
66. Report TCCS
67. Report RSKM
68. Unconstrained Paths
69. TimeQuest Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary ;
+--------------------+----------------------------------------------------+
; Quartus II Version ; Version 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
; Revision Name ; Single_Cycle_RISC_Processor ;
; Device Family ; Cyclone IV E ;
; Device Name ; EP4CE115F29C7 ;
; Timing Models ; Final ;
; Delay Model ; Combined ;
; Rise/Fall Delays ; Enabled ;
+--------------------+----------------------------------------------------+
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation ;
+----------------------------+--------+
; Processors ; Number ;
+----------------------------+--------+
; Number detected on machine ; 8 ;
; Maximum allowed ; 1 ;
+----------------------------+--------+
+---------------------------------------------------------------------+
; SDC File List ;
+---------------------------------+--------+--------------------------+
; SDC File Path ; Status ; Read at ;
+---------------------------------+--------+--------------------------+
; Single_Cycle_RISC_Processor.sdc ; OK ; Sun Dec 15 22:39:06 2024 ;
+---------------------------------+--------+--------------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks ;
+------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------------+
; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
+------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------------+
; CLOCK2_50 ; Base ; 20.000 ; 50.0 MHz ; 0.000 ; 10.000 ; ; ; ; ; ; ; ; ; ; ; { CLOCK2_50 } ;
; CLOCK3_50 ; Base ; 20.000 ; 50.0 MHz ; 0.000 ; 10.000 ; ; ; ; ; ; ; ; ; ; ; { CLOCK3_50 } ;
; CLOCK_50 ; Base ; 20.000 ; 50.0 MHz ; 0.000 ; 10.000 ; ; ; ; ; ; ; ; ; ; ; { CLOCK_50 } ;
+------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------------+
+--------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary ;
+------------+-----------------+------------+------+
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
+------------+-----------------+------------+------+
; 111.59 MHz ; 111.59 MHz ; CLOCK_50 ; ;
+------------+-----------------+------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.
+-------------------------------------+
; Slow 1200mV 85C Model Setup Summary ;
+----------+--------+-----------------+
; Clock ; Slack ; End Point TNS ;
+----------+--------+-----------------+
; CLOCK_50 ; 11.039 ; 0.000 ;
+----------+--------+-----------------+
+------------------------------------+
; Slow 1200mV 85C Model Hold Summary ;
+----------+-------+-----------------+
; Clock ; Slack ; End Point TNS ;
+----------+-------+-----------------+
; CLOCK_50 ; 0.401 ; 0.000 ;
+----------+-------+-----------------+
------------------------------------------
; Slow 1200mV 85C Model Recovery Summary ;
------------------------------------------
No paths to report.
-----------------------------------------
; Slow 1200mV 85C Model Removal Summary ;
-----------------------------------------
No paths to report.
+---------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
+-----------+--------+------------------------------+
; Clock ; Slack ; End Point TNS ;
+-----------+--------+------------------------------+
; CLOCK_50 ; 9.644 ; 0.000 ;
; CLOCK2_50 ; 16.000 ; 0.000 ;
; CLOCK3_50 ; 16.000 ; 0.000 ;
+-----------+--------+------------------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'CLOCK_50' ;
+--------+-----------------------------------------------------------------------+------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------+------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 11.039 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.095 ; 8.864 ;
; 11.651 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.095 ; 8.252 ;
; 11.808 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[22] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.111 ; 8.079 ;
; 11.847 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[26] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.081 ; 8.070 ;
; 11.887 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[28] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.084 ; 8.027 ;
; 11.920 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.099 ; 7.979 ;
; 12.136 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.119 ; 7.743 ;
; 12.150 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|current_reg_value[28] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.084 ; 7.764 ;
; 12.159 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[17] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.077 ; 7.762 ;
; 12.257 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.119 ; 7.622 ;
; 12.263 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.081 ; 7.654 ;
; 12.376 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.083 ; 7.539 ;
; 12.390 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[26] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.081 ; 7.527 ;
; 12.404 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[25] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.077 ; 7.517 ;
; 12.406 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|current_reg_value[20] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.079 ; 7.513 ;
; 12.434 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[25] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.077 ; 7.487 ;
; 12.437 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[21] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 7.487 ;
; 12.459 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[27] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.082 ; 7.457 ;
; 12.483 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[24] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.119 ; 7.396 ;
; 12.642 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.083 ; 7.273 ;
; 12.685 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[24] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.119 ; 7.194 ;
; 12.696 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[27] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.082 ; 7.220 ;
; 12.719 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[21] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 7.205 ;
; 12.746 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[20] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.079 ; 7.173 ;
; 12.761 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[28] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.084 ; 7.153 ;
; 12.762 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|current_reg_value[21] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 7.162 ;
; 12.778 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[19] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.082 ; 7.138 ;
; 12.783 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.081 ; 7.134 ;
; 12.819 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[31] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.079 ; 7.100 ;
; 12.828 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.093 ; 7.077 ;
; 12.869 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[28] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.084 ; 7.045 ;
; 12.886 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|current_reg_value[27] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.082 ; 7.030 ;
; 12.900 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|current_reg_value[26] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.081 ; 7.017 ;
; 12.904 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.096 ; 6.998 ;
; 12.922 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[26] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.081 ; 6.995 ;
; 12.940 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[19] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.082 ; 6.976 ;
; 12.947 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|current_reg_value[17] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.077 ; 6.974 ;
; 12.959 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[22] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.111 ; 6.928 ;
; 12.963 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[21] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 6.961 ;
; 12.970 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|current_reg_value[19] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.082 ; 6.946 ;
; 12.979 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.093 ; 6.926 ;
; 12.981 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.082 ; 6.935 ;
; 12.999 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|current_reg_value[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.081 ; 6.918 ;
; 13.017 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[22] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.111 ; 6.870 ;
; 13.050 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[29] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 6.874 ;
; 13.050 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[17] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.077 ; 6.871 ;
; 13.081 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|current_reg_value[31] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.079 ; 6.838 ;
; 13.090 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[16] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.081 ; 6.827 ;
; 13.137 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[31] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.079 ; 6.782 ;
; 13.165 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.098 ; 6.735 ;
; 13.187 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[29] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 6.737 ;
; 13.199 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[29] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 6.725 ;
; 13.201 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.077 ; 6.720 ;
; 13.203 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.095 ; 6.700 ;
; 13.224 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[19] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.082 ; 6.692 ;
; 13.226 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|current_reg_value[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.081 ; 6.691 ;
; 13.237 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[17] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.077 ; 6.684 ;
; 13.275 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|current_reg_value[30] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.081 ; 6.642 ;
; 13.281 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[30] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.081 ; 6.636 ;
; 13.316 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.094 ; 6.588 ;
; 13.341 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|current_reg_value[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.093 ; 6.564 ;
; 13.347 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.093 ; 6.558 ;
; 13.353 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.082 ; 6.563 ;
; 13.357 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|current_reg_value[24] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.119 ; 6.522 ;
; 13.362 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[31] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.079 ; 6.557 ;
; 13.377 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.099 ; 6.522 ;
; 13.425 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[24] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.119 ; 6.454 ;
; 13.429 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[20] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.079 ; 6.490 ;
; 13.437 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.099 ; 6.462 ;
; 13.439 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|current_reg_value[22] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.111 ; 6.448 ;
; 13.445 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|current_reg_value[29] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 6.479 ;
; 13.464 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[16] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.081 ; 6.453 ;
; 13.499 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.084 ; 6.415 ;
; 13.499 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[27] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.082 ; 6.417 ;
; 13.514 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[23] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.079 ; 6.405 ;
; 13.560 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.081 ; 6.357 ;
; 13.594 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.081 ; 6.323 ;
; 13.617 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.081 ; 6.300 ;
; 13.625 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.096 ; 6.277 ;
; 13.629 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.081 ; 6.288 ;
; 13.634 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[30] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.081 ; 6.283 ;
; 13.647 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.098 ; 6.253 ;
; 13.651 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[20] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.079 ; 6.268 ;
; 13.693 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|current_reg_value[25] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.077 ; 6.228 ;
; 13.717 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[23] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.079 ; 6.202 ;
; 13.736 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|current_reg_value[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.099 ; 6.163 ;
; 13.742 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[23] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.079 ; 6.177 ;
; 13.783 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|current_reg_value[16] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.081 ; 6.134 ;
; 13.818 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|current_reg_value[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.084 ; 6.096 ;
; 13.835 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[30] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.081 ; 6.082 ;
; 13.838 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.081 ; 6.079 ;
; 13.879 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.095 ; 6.024 ;
; 13.893 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[25] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.077 ; 6.028 ;
; 13.946 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|current_reg_value[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.077 ; 5.975 ;
; 13.969 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.094 ; 5.935 ;
; 13.988 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.082 ; 5.928 ;
; 13.993 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.077 ; 5.928 ;
; 13.994 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[16] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.081 ; 5.923 ;
; 14.082 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|current_reg_value[23] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.079 ; 5.837 ;
; 14.114 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|current_reg_value[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.095 ; 5.789 ;
+--------+-----------------------------------------------------------------------+------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'CLOCK_50' ;
+-------+----------------------------------------------------------------------------------+----------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------------------------------+----------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.401 ; receiver:uart_Rx|sample[0] ; receiver:uart_Rx|sample[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 0.669 ;
; 0.401 ; receiver:uart_Rx|sample[1] ; receiver:uart_Rx|sample[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 0.669 ;
; 0.401 ; receiver:uart_Rx|sample[3] ; receiver:uart_Rx|sample[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 0.669 ;
; 0.401 ; receiver:uart_Rx|sample[2] ; receiver:uart_Rx|sample[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 0.669 ;
; 0.402 ; processor:processor_u|register_file:register_file_inst|byte_counter[1] ; processor:processor_u|register_file:register_file_inst|byte_counter[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.669 ;
; 0.402 ; processor:processor_u|register_file:register_file_inst|byte_counter[0] ; processor:processor_u|register_file:register_file_inst|byte_counter[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.669 ;
; 0.402 ; processor:processor_u|register_file:register_file_inst|current_state.OUTPUT_BYTE ; processor:processor_u|register_file:register_file_inst|current_state.OUTPUT_BYTE ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.669 ;
; 0.402 ; processor:processor_u|register_file:register_file_inst|Ready_Byte ; processor:processor_u|register_file:register_file_inst|Ready_Byte ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.669 ;
; 0.402 ; transmitter:uart_Tx|state.TX_STATE_IDLE ; transmitter:uart_Tx|state.TX_STATE_IDLE ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.669 ;
; 0.402 ; transmitter:uart_Tx|bit_pos[2] ; transmitter:uart_Tx|bit_pos[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.669 ;
; 0.402 ; transmitter:uart_Tx|bit_pos[0] ; transmitter:uart_Tx|bit_pos[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.669 ;
; 0.402 ; transmitter:uart_Tx|bit_pos[1] ; transmitter:uart_Tx|bit_pos[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.669 ;
; 0.402 ; transmitter:uart_Tx|state.TX_STATE_START ; transmitter:uart_Tx|state.TX_STATE_START ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.669 ;
; 0.402 ; transmitter:uart_Tx|state.TX_STATE_STOP ; transmitter:uart_Tx|state.TX_STATE_STOP ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.669 ;
; 0.402 ; receiver:uart_Rx|state.RX_STATE_DATA ; receiver:uart_Rx|state.RX_STATE_DATA ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.669 ;
; 0.402 ; receiver:uart_Rx|bit_pos[3] ; receiver:uart_Rx|bit_pos[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.669 ;
; 0.402 ; receiver:uart_Rx|bit_pos[2] ; receiver:uart_Rx|bit_pos[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.669 ;
; 0.402 ; receiver:uart_Rx|bit_pos[1] ; receiver:uart_Rx|bit_pos[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.669 ;
; 0.403 ; receiver:uart_Rx|scratch[7] ; receiver:uart_Rx|scratch[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.669 ;
; 0.403 ; receiver:uart_Rx|scratch[1] ; receiver:uart_Rx|scratch[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.669 ;
; 0.403 ; receiver:uart_Rx|scratch[6] ; receiver:uart_Rx|scratch[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.669 ;
; 0.403 ; receiver:uart_Rx|scratch[3] ; receiver:uart_Rx|scratch[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.669 ;
; 0.403 ; receiver:uart_Rx|scratch[0] ; receiver:uart_Rx|scratch[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.669 ;
; 0.403 ; receiver:uart_Rx|scratch[5] ; receiver:uart_Rx|scratch[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.669 ;
; 0.403 ; receiver:uart_Rx|scratch[4] ; receiver:uart_Rx|scratch[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.669 ;
; 0.403 ; receiver:uart_Rx|scratch[2] ; receiver:uart_Rx|scratch[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.669 ;
; 0.406 ; baudrate:uart_baud|rx_acc[4] ; baudrate:uart_baud|rx_acc[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 0.674 ;
; 0.407 ; processor:processor_u|register_file:register_file_inst|current_state.BYTE_SENT ; processor:processor_u|register_file:register_file_inst|current_state.BYTE_SENT ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.674 ;
; 0.407 ; baudrate:uart_baud|tx_acc[1] ; baudrate:uart_baud|tx_acc[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.674 ;
; 0.407 ; receiver:uart_Rx|bit_pos[0] ; receiver:uart_Rx|bit_pos[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.674 ;
; 0.429 ; receiver:uart_Rx|scratch[4] ; receiver:uart_Rx|data_out[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.695 ;
; 0.430 ; receiver:uart_Rx|scratch[7] ; receiver:uart_Rx|data_out[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.696 ;
; 0.435 ; transmitter:uart_Tx|state.TX_STATE_START ; transmitter:uart_Tx|state.TX_STATE_DATA ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.702 ;
; 0.440 ; receiver:uart_Rx|ready ; receiver:uart_Rx|ready ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.043 ; 0.669 ;
; 0.446 ; processor:processor_u|register_file:register_file_inst|current_state.OUTPUT_BYTE ; processor:processor_u|register_file:register_file_inst|Ready_Byte ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.713 ;
; 0.461 ; baudrate:uart_baud|rx_acc[4] ; baudrate:uart_baud|rx_acc[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 0.729 ;
; 0.467 ; baudrate:uart_baud|rx_acc[4] ; baudrate:uart_baud|rx_acc[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 0.735 ;
; 0.468 ; processor:processor_u|register_file:register_file_inst|current_state.BYTE_SENT ; processor:processor_u|register_file:register_file_inst|current_state.REG_SENT ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.735 ;
; 0.475 ; processor:processor_u|register_file:register_file_inst|current_state.SEND_BYTE ; processor:processor_u|register_file:register_file_inst|current_state.BYTE_SENT ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.742 ;
; 0.499 ; receiver:uart_Rx|bit_pos[1] ; receiver:uart_Rx|bit_pos[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.766 ;
; 0.569 ; processor:processor_u|register_file:register_file_inst|current_state.IDLE ; processor:processor_u|register_file:register_file_inst|current_state.OUTPUT_REG ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.836 ;
; 0.589 ; processor:processor_u|register_file:register_file_inst|byte_counter[0] ; processor:processor_u|register_file:register_file_inst|current_state.REG_SENT ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.856 ;
; 0.596 ; processor:processor_u|register_file:register_file_inst|dout[2] ; transmitter:uart_Tx|data[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.863 ;
; 0.597 ; processor:processor_u|register_file:register_file_inst|dout[1] ; transmitter:uart_Tx|data[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.864 ;
; 0.603 ; transmitter:uart_Tx|state.TX_STATE_STOP ; transmitter:uart_Tx|state.TX_STATE_IDLE ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.870 ;
; 0.605 ; baudrate:uart_baud|tx_acc[1] ; baudrate:uart_baud|tx_acc[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.872 ;
; 0.605 ; baudrate:uart_baud|tx_acc[1] ; baudrate:uart_baud|tx_acc[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.872 ;
; 0.618 ; receiver:uart_Rx|bit_pos[0] ; receiver:uart_Rx|bit_pos[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.885 ;
; 0.619 ; receiver:uart_Rx|bit_pos[0] ; receiver:uart_Rx|bit_pos[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.886 ;
; 0.629 ; receiver:uart_Rx|state.RX_STATE_STOP ; receiver:uart_Rx|state.Ready_clearing ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.896 ;
; 0.642 ; baudrate:uart_baud|tx_acc[6] ; baudrate:uart_baud|tx_acc[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.909 ;
; 0.644 ; transmitter:uart_Tx|state.TX_STATE_DATA ; transmitter:uart_Tx|state.TX_STATE_STOP ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.911 ;
; 0.646 ; baudrate:uart_baud|tx_acc[2] ; baudrate:uart_baud|tx_acc[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.913 ;
; 0.646 ; baudrate:uart_baud|rx_acc[1] ; baudrate:uart_baud|rx_acc[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 0.914 ;
; 0.663 ; processor:processor_u|register_file:register_file_inst|incrementer[4] ; processor:processor_u|register_file:register_file_inst|incrementer[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.930 ;
; 0.674 ; processor:processor_u|register_file:register_file_inst|current_state.REG_SENT ; processor:processor_u|register_file:register_file_inst|current_state.OUTPUT_REG ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.941 ;
; 0.674 ; baudrate:uart_baud|rx_acc[0] ; baudrate:uart_baud|rx_acc[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 0.942 ;
; 0.675 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.942 ;
; 0.676 ; processor:processor_u|register_file:register_file_inst|current_state.BYTE_SENT ; processor:processor_u|register_file:register_file_inst|byte_counter[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.943 ;
; 0.676 ; receiver:uart_Rx|state.RX_STATE_DATA ; receiver:uart_Rx|bit_pos[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.943 ;
; 0.679 ; processor:processor_u|register_file:register_file_inst|current_state.REG_SENT ; processor:processor_u|register_file:register_file_inst|byte_counter[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.946 ;
; 0.685 ; processor:processor_u|register_file:register_file_inst|current_state.SEND_BYTE ; processor:processor_u|register_file:register_file_inst|Ready_Byte ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.952 ;
; 0.686 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.953 ;
; 0.688 ; transmitter:uart_Tx|state.TX_STATE_STOP ; transmitter:uart_Tx|state.TX_STATE_DATA ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.955 ;
; 0.690 ; receiver:uart_Rx|state.Ready_clearing ; receiver:uart_Rx|state.RX_STATE_START ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.957 ;
; 0.697 ; processor:processor_u|register_file:register_file_inst|current_state.BYTE_SENT ; processor:processor_u|register_file:register_file_inst|current_state.SEND_BYTE ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.964 ;
; 0.700 ; processor:processor_u|register_file:register_file_inst|current_state.SEND_BYTE ; processor:processor_u|register_file:register_file_inst|dout[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 0.968 ;
; 0.701 ; processor:processor_u|register_file:register_file_inst|current_state.SEND_BYTE ; processor:processor_u|register_file:register_file_inst|dout[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 0.969 ;
; 0.701 ; processor:processor_u|register_file:register_file_inst|byte_counter[1] ; processor:processor_u|register_file:register_file_inst|current_state.REG_SENT ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.968 ;
; 0.703 ; processor:processor_u|register_file:register_file_inst|current_state.SEND_BYTE ; processor:processor_u|register_file:register_file_inst|dout[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 0.971 ;
; 0.703 ; processor:processor_u|register_file:register_file_inst|current_state.SEND_BYTE ; processor:processor_u|register_file:register_file_inst|dout[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 0.971 ;
; 0.703 ; processor:processor_u|register_file:register_file_inst|current_state.SEND_BYTE ; processor:processor_u|register_file:register_file_inst|dout[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 0.971 ;
; 0.704 ; processor:processor_u|register_file:register_file_inst|current_state.SEND_BYTE ; processor:processor_u|register_file:register_file_inst|dout[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 0.972 ;
; 0.708 ; receiver:uart_Rx|bit_pos[2] ; receiver:uart_Rx|bit_pos[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.975 ;
; 0.714 ; receiver:uart_Rx|bit_pos[1] ; receiver:uart_Rx|bit_pos[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.981 ;
; 0.726 ; processor:processor_u|register_file:register_file_inst|current_state.OUTPUT_BYTE ; processor:processor_u|register_file:register_file_inst|current_state.SEND_BYTE ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.993 ;
; 0.733 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.000 ;
; 0.749 ; baudrate:uart_baud|tx_acc[1] ; baudrate:uart_baud|tx_acc[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.016 ;
; 0.749 ; baudrate:uart_baud|tx_acc[1] ; baudrate:uart_baud|tx_acc[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.016 ;
; 0.751 ; baudrate:uart_baud|tx_acc[1] ; baudrate:uart_baud|tx_acc[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.018 ;
; 0.756 ; receiver:uart_Rx|state.RX_STATE_DATA ; receiver:uart_Rx|bit_pos[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.023 ;
; 0.756 ; receiver:uart_Rx|state.RX_STATE_DATA ; receiver:uart_Rx|bit_pos[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.023 ;
; 0.756 ; receiver:uart_Rx|state.RX_STATE_DATA ; receiver:uart_Rx|bit_pos[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.023 ;
; 0.765 ; processor:processor_u|register_file:register_file_inst|dout[0] ; transmitter:uart_Tx|data[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.032 ;
; 0.767 ; processor:processor_u|register_file:register_file_inst|dout[4] ; transmitter:uart_Tx|data[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.034 ;
; 0.795 ; baudrate:uart_baud|rx_acc[1] ; baudrate:uart_baud|rx_acc[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.063 ;
; 0.799 ; processor:processor_u|register_file:register_file_inst|dout[3] ; transmitter:uart_Tx|data[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.066 ;
; 0.801 ; processor:processor_u|register_file:register_file_inst|dout[7] ; transmitter:uart_Tx|data[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.068 ;
; 0.803 ; processor:processor_u|register_file:register_file_inst|dout[5] ; transmitter:uart_Tx|data[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.070 ;
; 0.806 ; baudrate:uart_baud|tx_acc[3] ; baudrate:uart_baud|tx_acc[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.073 ;
; 0.817 ; receiver:uart_Rx|sample[0] ; receiver:uart_Rx|sample[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.085 ;
; 0.818 ; receiver:uart_Rx|sample[3] ; receiver:uart_Rx|sample[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.086 ;
; 0.822 ; processor:processor_u|register_file:register_file_inst|current_state.SEND_BYTE ; processor:processor_u|register_file:register_file_inst|current_state.SEND_BYTE ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.089 ;
; 0.837 ; receiver:uart_Rx|bit_pos[0] ; receiver:uart_Rx|bit_pos[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.104 ;
; 0.843 ; processor:processor_u|register_file:register_file_inst|current_state.SEND_BYTE ; processor:processor_u|register_file:register_file_inst|current_state.IDLE ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.110 ;
; 0.843 ; processor:processor_u|register_file:register_file_inst|current_state.SEND_BYTE ; processor:processor_u|register_file:register_file_inst|byte_counter[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.110 ;
; 0.843 ; processor:processor_u|register_file:register_file_inst|current_state.SEND_BYTE ; processor:processor_u|register_file:register_file_inst|byte_counter[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.110 ;
; 0.851 ; processor:processor_u|register_file:register_file_inst|current_state.REG_SENT ; processor:processor_u|register_file:register_file_inst|byte_counter[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.118 ;
; 0.860 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.127 ;
; 0.880 ; transmitter:uart_Tx|state.TX_STATE_DATA ; transmitter:uart_Tx|bit_pos[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.146 ;
+-------+----------------------------------------------------------------------------------+----------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50' ;
+-------+--------------+----------------+-----------------+----------+------------+----------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
+-------+--------------+----------------+-----------------+----------+------------+----------------------------------------------------------------------------------+
; 9.644 ; 9.832 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|ready ;
; 9.673 ; 9.861 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|scratch[0] ;
; 9.673 ; 9.861 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|scratch[1] ;
; 9.673 ; 9.861 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|scratch[2] ;
; 9.673 ; 9.861 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|scratch[3] ;
; 9.673 ; 9.861 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|scratch[5] ;
; 9.673 ; 9.861 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|scratch[6] ;
; 9.675 ; 9.863 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|data_out[0] ;
; 9.675 ; 9.863 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|data_out[1] ;
; 9.675 ; 9.863 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|data_out[2] ;
; 9.675 ; 9.863 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|data_out[3] ;
; 9.675 ; 9.863 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|data_out[4] ;
; 9.675 ; 9.863 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|data_out[5] ;
; 9.675 ; 9.863 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|data_out[6] ;
; 9.675 ; 9.863 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|data_out[7] ;
; 9.675 ; 9.863 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|scratch[4] ;
; 9.675 ; 9.863 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|scratch[7] ;
; 9.680 ; 9.868 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[22] ;
; 9.681 ; 9.869 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[14] ;
; 9.681 ; 9.869 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[24] ;
; 9.682 ; 9.870 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[8] ;
; 9.683 ; 9.871 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[12] ;
; 9.683 ; 9.871 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[17] ;
; 9.683 ; 9.871 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[1] ;
; 9.683 ; 9.871 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[20] ;
; 9.683 ; 9.871 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[21] ;
; 9.683 ; 9.871 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[23] ;
; 9.683 ; 9.871 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[25] ;
; 9.683 ; 9.871 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[29] ;
; 9.683 ; 9.871 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[2] ;
; 9.683 ; 9.871 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[31] ;
; 9.683 ; 9.871 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[7] ;
; 9.683 ; 9.871 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|state.RX_STATE_START ;
; 9.683 ; 9.871 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|state.RX_STATE_STOP ;
; 9.683 ; 9.871 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|state.Ready_clearing ;
; 9.683 ; 9.871 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; transmitter:uart_Tx|Tx ;
; 9.683 ; 9.871 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; transmitter:uart_Tx|bit_pos[0] ;
; 9.683 ; 9.871 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; transmitter:uart_Tx|bit_pos[1] ;
; 9.683 ; 9.871 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; transmitter:uart_Tx|bit_pos[2] ;
; 9.683 ; 9.871 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; transmitter:uart_Tx|data[0] ;
; 9.683 ; 9.871 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; transmitter:uart_Tx|data[1] ;
; 9.683 ; 9.871 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; transmitter:uart_Tx|data[2] ;
; 9.683 ; 9.871 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; transmitter:uart_Tx|data[3] ;
; 9.683 ; 9.871 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; transmitter:uart_Tx|data[4] ;
; 9.683 ; 9.871 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; transmitter:uart_Tx|data[5] ;
; 9.683 ; 9.871 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; transmitter:uart_Tx|data[6] ;
; 9.683 ; 9.871 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; transmitter:uart_Tx|data[7] ;
; 9.683 ; 9.871 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; transmitter:uart_Tx|state.TX_STATE_DATA ;
; 9.683 ; 9.871 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; transmitter:uart_Tx|state.TX_STATE_IDLE ;
; 9.683 ; 9.871 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; transmitter:uart_Tx|state.TX_STATE_START ;
; 9.683 ; 9.871 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; transmitter:uart_Tx|state.TX_STATE_STOP ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; baudrate:uart_baud|rx_acc[0] ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; baudrate:uart_baud|rx_acc[1] ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; baudrate:uart_baud|rx_acc[2] ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; baudrate:uart_baud|rx_acc[3] ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; baudrate:uart_baud|rx_acc[4] ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; baudrate:uart_baud|tx_acc[0] ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; baudrate:uart_baud|tx_acc[1] ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; baudrate:uart_baud|tx_acc[2] ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; baudrate:uart_baud|tx_acc[3] ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; baudrate:uart_baud|tx_acc[4] ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; baudrate:uart_baud|tx_acc[5] ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; baudrate:uart_baud|tx_acc[6] ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; baudrate:uart_baud|tx_acc[7] ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; baudrate:uart_baud|tx_acc[8] ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|Ready_Byte ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|byte_counter[0] ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|byte_counter[1] ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[0] ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[10] ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[13] ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[15] ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[16] ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[18] ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[26] ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[28] ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[30] ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[4] ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[5] ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[6] ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[9] ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_state.BYTE_SENT ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_state.IDLE ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_state.OUTPUT_BYTE ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_state.OUTPUT_REG ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_state.REG_SENT ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_state.SEND_BYTE ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|dout[0] ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|dout[1] ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|dout[2] ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|dout[3] ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|dout[4] ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|dout[5] ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|dout[6] ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|dout[7] ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|bit_pos[0] ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|bit_pos[1] ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|bit_pos[2] ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|bit_pos[3] ;
; 9.684 ; 9.872 ; 0.188 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|sample[0] ;
+-------+--------------+----------------+-----------------+----------+------------+----------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK2_50' ;
+--------+--------------+----------------+-----------+-----------+------------+-----------+
; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
+--------+--------------+----------------+-----------+-----------+------------+-----------+
; 16.000 ; 20.000 ; 4.000 ; Port Rate ; CLOCK2_50 ; Rise ; CLOCK2_50 ;
+--------+--------------+----------------+-----------+-----------+------------+-----------+
+-----------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK3_50' ;
+--------+--------------+----------------+-----------+-----------+------------+-----------+
; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
+--------+--------------+----------------+-----------+-----------+------------+-----------+
; 16.000 ; 20.000 ; 4.000 ; Port Rate ; CLOCK3_50 ; Rise ; CLOCK3_50 ;
+--------+--------------+----------------+-----------+-----------+------------+-----------+
+-----------------------------------------------------------------------+
; Setup Times ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; EX_IO[*] ; CLOCK_50 ; 6.335 ; 6.976 ; Rise ; CLOCK_50 ;
; EX_IO[1] ; CLOCK_50 ; 6.335 ; 6.976 ; Rise ; CLOCK_50 ;
; KEY[*] ; CLOCK_50 ; 5.746 ; 6.361 ; Rise ; CLOCK_50 ;
; KEY[2] ; CLOCK_50 ; 5.746 ; 6.361 ; Rise ; CLOCK_50 ;
+-----------+------------+-------+-------+------------+-----------------+
+-------------------------------------------------------------------------+
; Hold Times ;
+-----------+------------+--------+--------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+--------+--------+------------+-----------------+
; EX_IO[*] ; CLOCK_50 ; -2.076 ; -2.638 ; Rise ; CLOCK_50 ;
; EX_IO[1] ; CLOCK_50 ; -2.076 ; -2.638 ; Rise ; CLOCK_50 ;
; KEY[*] ; CLOCK_50 ; -1.629 ; -2.139 ; Rise ; CLOCK_50 ;
; KEY[2] ; CLOCK_50 ; -1.629 ; -2.139 ; Rise ; CLOCK_50 ;
+-----------+------------+--------+--------+------------+-----------------+
+-------------------------------------------------------------------------+
; Clock to Output Times ;
+-----------+------------+--------+--------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+--------+--------+------------+-----------------+
; EX_IO[*] ; CLOCK_50 ; 12.896 ; 13.167 ; Rise ; CLOCK_50 ;
; EX_IO[0] ; CLOCK_50 ; 12.896 ; 13.167 ; Rise ; CLOCK_50 ;
+-----------+------------+--------+--------+------------+-----------------+
+-------------------------------------------------------------------------+
; Minimum Clock to Output Times ;
+-----------+------------+--------+--------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+--------+--------+------------+-----------------+
; EX_IO[*] ; CLOCK_50 ; 12.417 ; 12.681 ; Rise ; CLOCK_50 ;
; EX_IO[0] ; CLOCK_50 ; 12.417 ; 12.681 ; Rise ; CLOCK_50 ;
+-----------+------------+--------+--------+------------+-----------------+
----------------------------------------------
; Slow 1200mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.
+--------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary ;
+------------+-----------------+------------+------+
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
+------------+-----------------+------------+------+
; 122.01 MHz ; 122.01 MHz ; CLOCK_50 ; ;
+------------+-----------------+------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+------------------------------------+
; Slow 1200mV 0C Model Setup Summary ;
+----------+--------+----------------+
; Clock ; Slack ; End Point TNS ;
+----------+--------+----------------+
; CLOCK_50 ; 11.804 ; 0.000 ;
+----------+--------+----------------+
+-----------------------------------+
; Slow 1200mV 0C Model Hold Summary ;
+----------+-------+----------------+
; Clock ; Slack ; End Point TNS ;
+----------+-------+----------------+
; CLOCK_50 ; 0.353 ; 0.000 ;
+----------+-------+----------------+
-----------------------------------------
; Slow 1200mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.
----------------------------------------
; Slow 1200mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.
+--------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
+-----------+--------+-----------------------------+
; Clock ; Slack ; End Point TNS ;
+-----------+--------+-----------------------------+
; CLOCK_50 ; 9.634 ; 0.000 ;
; CLOCK2_50 ; 16.000 ; 0.000 ;
; CLOCK3_50 ; 16.000 ; 0.000 ;
+-----------+--------+-----------------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'CLOCK_50' ;
+--------+-----------------------------------------------------------------------+------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------+------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 11.804 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.086 ; 8.109 ;
; 12.418 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[22] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.099 ; 7.482 ;
; 12.421 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.086 ; 7.492 ;
; 12.433 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[26] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.072 ; 7.494 ;
; 12.495 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[28] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.076 ; 7.428 ;
; 12.505 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.092 ; 7.402 ;
; 12.659 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.107 ; 7.233 ;
; 12.733 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[17] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.068 ; 7.198 ;
; 12.763 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|current_reg_value[28] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.076 ; 7.160 ;
; 12.813 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.073 ; 7.113 ;
; 12.858 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[14] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.107 ; 7.034 ;
; 12.928 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[26] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.072 ; 6.999 ;
; 12.930 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.073 ; 6.996 ;
; 12.934 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[25] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.068 ; 6.997 ;
; 12.961 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|current_reg_value[20] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.070 ; 6.968 ;
; 13.006 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[24] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.107 ; 6.886 ;
; 13.013 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[25] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.068 ; 6.918 ;
; 13.065 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[21] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.065 ; 6.869 ;
; 13.091 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[27] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 6.834 ;
; 13.200 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[8] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.073 ; 6.726 ;
; 13.289 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.072 ; 6.638 ;
; 13.303 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[21] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.065 ; 6.631 ;
; 13.313 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[19] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 6.612 ;
; 13.322 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[24] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.107 ; 6.570 ;
; 13.323 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[20] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.070 ; 6.606 ;
; 13.326 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[27] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 6.599 ;
; 13.340 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|current_reg_value[21] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.065 ; 6.594 ;
; 13.373 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[31] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.069 ; 6.557 ;
; 13.413 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.085 ; 6.501 ;
; 13.413 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[26] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.072 ; 6.514 ;
; 13.417 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[28] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.076 ; 6.506 ;
; 13.419 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|current_reg_value[27] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 6.506 ;
; 13.430 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[19] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 6.495 ;
; 13.451 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|current_reg_value[26] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.072 ; 6.476 ;
; 13.468 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[22] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.099 ; 6.432 ;
; 13.481 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.087 ; 6.431 ;
; 13.481 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[28] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.076 ; 6.442 ;
; 13.482 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[22] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.099 ; 6.418 ;
; 13.483 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[21] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.065 ; 6.451 ;
; 13.513 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|current_reg_value[17] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.068 ; 6.418 ;
; 13.535 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[17] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.068 ; 6.396 ;
; 13.547 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|current_reg_value[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.073 ; 6.379 ;
; 13.549 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.085 ; 6.365 ;
; 13.554 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 6.371 ;
; 13.577 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[16] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.073 ; 6.349 ;
; 13.603 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|current_reg_value[19] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 6.322 ;
; 13.609 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[29] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.065 ; 6.325 ;
; 13.633 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[31] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.069 ; 6.297 ;
; 13.639 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|current_reg_value[31] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.069 ; 6.291 ;
; 13.678 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[29] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.065 ; 6.256 ;
; 13.692 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[17] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.068 ; 6.239 ;
; 13.701 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[29] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.065 ; 6.233 ;
; 13.724 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.091 ; 6.184 ;
; 13.727 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.068 ; 6.204 ;
; 13.757 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[19] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 6.168 ;
; 13.765 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[30] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.073 ; 6.161 ;
; 13.781 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[2] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.086 ; 6.132 ;
; 13.808 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|current_reg_value[30] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.073 ; 6.118 ;
; 13.809 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|current_reg_value[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.073 ; 6.117 ;
; 13.820 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.087 ; 6.092 ;
; 13.864 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.085 ; 6.050 ;
; 13.894 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[31] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.069 ; 6.036 ;
; 13.899 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|current_reg_value[24] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.107 ; 5.993 ;
; 13.904 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 6.021 ;
; 13.920 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[24] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.107 ; 5.972 ;
; 13.922 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|current_reg_value[7] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.085 ; 5.992 ;
; 13.927 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[16] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.073 ; 5.999 ;
; 13.932 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|current_reg_value[22] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.099 ; 5.968 ;
; 13.945 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.092 ; 5.962 ;
; 13.962 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.092 ; 5.945 ;
; 13.968 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[20] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.070 ; 5.961 ;
; 13.991 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[27] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 5.934 ;
; 14.012 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.073 ; 5.914 ;
; 14.050 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.076 ; 5.873 ;
; 14.073 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|current_reg_value[29] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.065 ; 5.861 ;
; 14.098 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.073 ; 5.828 ;
; 14.103 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[6] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.073 ; 5.823 ;
; 14.112 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[23] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.069 ; 5.818 ;
; 14.137 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[0] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.073 ; 5.789 ;
; 14.143 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[9] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.087 ; 5.769 ;
; 14.147 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[30] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.073 ; 5.779 ;
; 14.165 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[11] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.091 ; 5.743 ;
; 14.173 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[20] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.070 ; 5.756 ;
; 14.223 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|current_reg_value[13] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.092 ; 5.684 ;
; 14.246 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|current_reg_value[23] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.069 ; 5.684 ;
; 14.268 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[23] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.069 ; 5.662 ;
; 14.277 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|current_reg_value[25] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.068 ; 5.654 ;
; 14.301 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|current_reg_value[16] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.073 ; 5.625 ;
; 14.335 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[10] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.072 ; 5.592 ;
; 14.356 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[30] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.073 ; 5.570 ;
; 14.375 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|current_reg_value[4] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.076 ; 5.548 ;
; 14.391 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.086 ; 5.522 ;
; 14.411 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[25] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.068 ; 5.520 ;
; 14.431 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|current_reg_value[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.068 ; 5.500 ;
; 14.448 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|current_reg_value[15] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.087 ; 5.464 ;
; 14.466 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[3] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.074 ; 5.459 ;
; 14.480 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[1] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.068 ; 5.451 ;
; 14.531 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|current_reg_value[16] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.073 ; 5.395 ;
; 14.621 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|current_reg_value[12] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.086 ; 5.292 ;
; 14.633 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|current_reg_value[23] ; CLOCK_50 ; CLOCK_50 ; 20.000 ; -0.069 ; 5.297 ;
+--------+-----------------------------------------------------------------------+------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'CLOCK_50' ;
+-------+----------------------------------------------------------------------------------+----------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------------------------------+----------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.353 ; transmitter:uart_Tx|state.TX_STATE_IDLE ; transmitter:uart_Tx|state.TX_STATE_IDLE ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.597 ;
; 0.353 ; transmitter:uart_Tx|state.TX_STATE_START ; transmitter:uart_Tx|state.TX_STATE_START ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.597 ;
; 0.353 ; transmitter:uart_Tx|state.TX_STATE_STOP ; transmitter:uart_Tx|state.TX_STATE_STOP ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.597 ;
; 0.353 ; receiver:uart_Rx|sample[0] ; receiver:uart_Rx|sample[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.597 ;
; 0.353 ; receiver:uart_Rx|sample[1] ; receiver:uart_Rx|sample[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.597 ;
; 0.353 ; receiver:uart_Rx|sample[3] ; receiver:uart_Rx|sample[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.597 ;
; 0.353 ; receiver:uart_Rx|sample[2] ; receiver:uart_Rx|sample[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.597 ;
; 0.354 ; processor:processor_u|register_file:register_file_inst|byte_counter[1] ; processor:processor_u|register_file:register_file_inst|byte_counter[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.597 ;
; 0.354 ; processor:processor_u|register_file:register_file_inst|byte_counter[0] ; processor:processor_u|register_file:register_file_inst|byte_counter[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.597 ;
; 0.354 ; processor:processor_u|register_file:register_file_inst|current_state.OUTPUT_BYTE ; processor:processor_u|register_file:register_file_inst|current_state.OUTPUT_BYTE ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.597 ;
; 0.354 ; processor:processor_u|register_file:register_file_inst|Ready_Byte ; processor:processor_u|register_file:register_file_inst|Ready_Byte ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.597 ;
; 0.354 ; transmitter:uart_Tx|bit_pos[2] ; transmitter:uart_Tx|bit_pos[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.597 ;
; 0.354 ; transmitter:uart_Tx|bit_pos[0] ; transmitter:uart_Tx|bit_pos[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.597 ;
; 0.354 ; transmitter:uart_Tx|bit_pos[1] ; transmitter:uart_Tx|bit_pos[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.597 ;
; 0.354 ; receiver:uart_Rx|scratch[1] ; receiver:uart_Rx|scratch[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.597 ;
; 0.354 ; receiver:uart_Rx|scratch[6] ; receiver:uart_Rx|scratch[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.597 ;
; 0.354 ; receiver:uart_Rx|scratch[3] ; receiver:uart_Rx|scratch[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.597 ;
; 0.354 ; receiver:uart_Rx|scratch[0] ; receiver:uart_Rx|scratch[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.597 ;
; 0.354 ; receiver:uart_Rx|scratch[5] ; receiver:uart_Rx|scratch[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.597 ;
; 0.354 ; receiver:uart_Rx|scratch[2] ; receiver:uart_Rx|scratch[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.597 ;
; 0.354 ; receiver:uart_Rx|state.RX_STATE_DATA ; receiver:uart_Rx|state.RX_STATE_DATA ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.597 ;
; 0.354 ; receiver:uart_Rx|bit_pos[3] ; receiver:uart_Rx|bit_pos[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.597 ;
; 0.354 ; receiver:uart_Rx|bit_pos[2] ; receiver:uart_Rx|bit_pos[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.597 ;
; 0.354 ; receiver:uart_Rx|bit_pos[1] ; receiver:uart_Rx|bit_pos[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.597 ;
; 0.355 ; receiver:uart_Rx|scratch[7] ; receiver:uart_Rx|scratch[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.071 ; 0.597 ;
; 0.355 ; receiver:uart_Rx|scratch[4] ; receiver:uart_Rx|scratch[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.071 ; 0.597 ;
; 0.364 ; baudrate:uart_baud|tx_acc[1] ; baudrate:uart_baud|tx_acc[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.608 ;
; 0.364 ; baudrate:uart_baud|rx_acc[4] ; baudrate:uart_baud|rx_acc[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.608 ;
; 0.365 ; processor:processor_u|register_file:register_file_inst|current_state.BYTE_SENT ; processor:processor_u|register_file:register_file_inst|current_state.BYTE_SENT ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.608 ;
; 0.365 ; receiver:uart_Rx|bit_pos[0] ; receiver:uart_Rx|bit_pos[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.608 ;
; 0.387 ; receiver:uart_Rx|ready ; receiver:uart_Rx|ready ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 0.597 ;
; 0.396 ; receiver:uart_Rx|scratch[4] ; receiver:uart_Rx|data_out[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.071 ; 0.638 ;
; 0.397 ; receiver:uart_Rx|scratch[7] ; receiver:uart_Rx|data_out[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.071 ; 0.639 ;
; 0.402 ; transmitter:uart_Tx|state.TX_STATE_START ; transmitter:uart_Tx|state.TX_STATE_DATA ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.646 ;
; 0.411 ; processor:processor_u|register_file:register_file_inst|current_state.OUTPUT_BYTE ; processor:processor_u|register_file:register_file_inst|Ready_Byte ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.654 ;
; 0.417 ; baudrate:uart_baud|rx_acc[4] ; baudrate:uart_baud|rx_acc[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.661 ;
; 0.422 ; baudrate:uart_baud|rx_acc[4] ; baudrate:uart_baud|rx_acc[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.666 ;
; 0.434 ; processor:processor_u|register_file:register_file_inst|current_state.BYTE_SENT ; processor:processor_u|register_file:register_file_inst|current_state.REG_SENT ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.677 ;
; 0.437 ; processor:processor_u|register_file:register_file_inst|current_state.SEND_BYTE ; processor:processor_u|register_file:register_file_inst|current_state.BYTE_SENT ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.680 ;
; 0.452 ; receiver:uart_Rx|bit_pos[1] ; receiver:uart_Rx|bit_pos[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.695 ;
; 0.516 ; processor:processor_u|register_file:register_file_inst|current_state.IDLE ; processor:processor_u|register_file:register_file_inst|current_state.OUTPUT_REG ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.759 ;
; 0.540 ; processor:processor_u|register_file:register_file_inst|byte_counter[0] ; processor:processor_u|register_file:register_file_inst|current_state.REG_SENT ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.783 ;
; 0.546 ; baudrate:uart_baud|tx_acc[1] ; baudrate:uart_baud|tx_acc[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.790 ;
; 0.546 ; baudrate:uart_baud|tx_acc[1] ; baudrate:uart_baud|tx_acc[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.790 ;
; 0.550 ; processor:processor_u|register_file:register_file_inst|dout[2] ; transmitter:uart_Tx|data[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.794 ;
; 0.551 ; processor:processor_u|register_file:register_file_inst|dout[1] ; transmitter:uart_Tx|data[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.795 ;
; 0.559 ; transmitter:uart_Tx|state.TX_STATE_STOP ; transmitter:uart_Tx|state.TX_STATE_IDLE ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.803 ;
; 0.574 ; receiver:uart_Rx|state.RX_STATE_STOP ; receiver:uart_Rx|state.Ready_clearing ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.818 ;
; 0.574 ; receiver:uart_Rx|bit_pos[0] ; receiver:uart_Rx|bit_pos[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.817 ;
; 0.576 ; receiver:uart_Rx|bit_pos[0] ; receiver:uart_Rx|bit_pos[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.819 ;
; 0.584 ; baudrate:uart_baud|tx_acc[6] ; baudrate:uart_baud|tx_acc[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.828 ;
; 0.590 ; baudrate:uart_baud|tx_acc[2] ; baudrate:uart_baud|tx_acc[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.834 ;
; 0.590 ; baudrate:uart_baud|rx_acc[1] ; baudrate:uart_baud|rx_acc[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.834 ;
; 0.593 ; transmitter:uart_Tx|state.TX_STATE_DATA ; transmitter:uart_Tx|state.TX_STATE_STOP ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.837 ;
; 0.606 ; processor:processor_u|register_file:register_file_inst|incrementer[4] ; processor:processor_u|register_file:register_file_inst|incrementer[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.850 ;
; 0.616 ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; processor:processor_u|register_file:register_file_inst|incrementer[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.860 ;
; 0.616 ; processor:processor_u|register_file:register_file_inst|current_state.REG_SENT ; processor:processor_u|register_file:register_file_inst|current_state.OUTPUT_REG ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.859 ;
; 0.616 ; baudrate:uart_baud|rx_acc[0] ; baudrate:uart_baud|rx_acc[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.860 ;
; 0.617 ; receiver:uart_Rx|state.RX_STATE_DATA ; receiver:uart_Rx|bit_pos[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.860 ;
; 0.619 ; processor:processor_u|register_file:register_file_inst|current_state.BYTE_SENT ; processor:processor_u|register_file:register_file_inst|byte_counter[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.862 ;
; 0.620 ; processor:processor_u|register_file:register_file_inst|current_state.REG_SENT ; processor:processor_u|register_file:register_file_inst|byte_counter[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.863 ;
; 0.626 ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; processor:processor_u|register_file:register_file_inst|incrementer[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.870 ;
; 0.627 ; processor:processor_u|register_file:register_file_inst|current_state.SEND_BYTE ; processor:processor_u|register_file:register_file_inst|Ready_Byte ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.870 ;
; 0.630 ; transmitter:uart_Tx|state.TX_STATE_STOP ; transmitter:uart_Tx|state.TX_STATE_DATA ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.874 ;
; 0.631 ; receiver:uart_Rx|state.Ready_clearing ; receiver:uart_Rx|state.RX_STATE_START ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.875 ;
; 0.638 ; processor:processor_u|register_file:register_file_inst|current_state.BYTE_SENT ; processor:processor_u|register_file:register_file_inst|current_state.SEND_BYTE ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.881 ;
; 0.639 ; processor:processor_u|register_file:register_file_inst|byte_counter[1] ; processor:processor_u|register_file:register_file_inst|current_state.REG_SENT ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.882 ;
; 0.647 ; receiver:uart_Rx|bit_pos[2] ; receiver:uart_Rx|bit_pos[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.890 ;
; 0.652 ; receiver:uart_Rx|bit_pos[1] ; receiver:uart_Rx|bit_pos[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.895 ;
; 0.655 ; processor:processor_u|register_file:register_file_inst|current_state.SEND_BYTE ; processor:processor_u|register_file:register_file_inst|dout[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.899 ;
; 0.657 ; processor:processor_u|register_file:register_file_inst|current_state.SEND_BYTE ; processor:processor_u|register_file:register_file_inst|dout[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.901 ;
; 0.659 ; processor:processor_u|register_file:register_file_inst|current_state.SEND_BYTE ; processor:processor_u|register_file:register_file_inst|dout[6] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.903 ;
; 0.659 ; processor:processor_u|register_file:register_file_inst|current_state.SEND_BYTE ; processor:processor_u|register_file:register_file_inst|dout[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.903 ;
; 0.659 ; processor:processor_u|register_file:register_file_inst|current_state.SEND_BYTE ; processor:processor_u|register_file:register_file_inst|dout[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.903 ;
; 0.660 ; processor:processor_u|register_file:register_file_inst|current_state.SEND_BYTE ; processor:processor_u|register_file:register_file_inst|dout[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.904 ;
; 0.666 ; processor:processor_u|register_file:register_file_inst|current_state.OUTPUT_BYTE ; processor:processor_u|register_file:register_file_inst|current_state.SEND_BYTE ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.909 ;
; 0.667 ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; processor:processor_u|register_file:register_file_inst|incrementer[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.911 ;
; 0.678 ; baudrate:uart_baud|tx_acc[1] ; baudrate:uart_baud|tx_acc[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.922 ;
; 0.678 ; baudrate:uart_baud|tx_acc[1] ; baudrate:uart_baud|tx_acc[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.922 ;
; 0.680 ; baudrate:uart_baud|tx_acc[1] ; baudrate:uart_baud|tx_acc[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.924 ;
; 0.709 ; receiver:uart_Rx|state.RX_STATE_DATA ; receiver:uart_Rx|bit_pos[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.952 ;
; 0.709 ; receiver:uart_Rx|state.RX_STATE_DATA ; receiver:uart_Rx|bit_pos[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.952 ;
; 0.709 ; receiver:uart_Rx|state.RX_STATE_DATA ; receiver:uart_Rx|bit_pos[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.952 ;
; 0.711 ; processor:processor_u|register_file:register_file_inst|dout[0] ; transmitter:uart_Tx|data[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.955 ;
; 0.714 ; processor:processor_u|register_file:register_file_inst|dout[4] ; transmitter:uart_Tx|data[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.958 ;
; 0.728 ; baudrate:uart_baud|rx_acc[1] ; baudrate:uart_baud|rx_acc[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.972 ;
; 0.737 ; receiver:uart_Rx|sample[0] ; receiver:uart_Rx|sample[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.981 ;
; 0.738 ; receiver:uart_Rx|sample[3] ; receiver:uart_Rx|sample[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.982 ;
; 0.745 ; processor:processor_u|register_file:register_file_inst|dout[3] ; transmitter:uart_Tx|data[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.989 ;
; 0.747 ; processor:processor_u|register_file:register_file_inst|dout[7] ; transmitter:uart_Tx|data[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.991 ;
; 0.748 ; baudrate:uart_baud|tx_acc[3] ; baudrate:uart_baud|tx_acc[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.992 ;
; 0.749 ; processor:processor_u|register_file:register_file_inst|dout[5] ; transmitter:uart_Tx|data[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 0.993 ;
; 0.760 ; processor:processor_u|register_file:register_file_inst|current_state.SEND_BYTE ; processor:processor_u|register_file:register_file_inst|current_state.SEND_BYTE ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.003 ;
; 0.766 ; processor:processor_u|register_file:register_file_inst|current_state.SEND_BYTE ; processor:processor_u|register_file:register_file_inst|current_state.IDLE ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.009 ;
; 0.766 ; processor:processor_u|register_file:register_file_inst|current_state.SEND_BYTE ; processor:processor_u|register_file:register_file_inst|byte_counter[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.009 ;
; 0.766 ; processor:processor_u|register_file:register_file_inst|current_state.SEND_BYTE ; processor:processor_u|register_file:register_file_inst|byte_counter[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.009 ;
; 0.778 ; receiver:uart_Rx|bit_pos[0] ; receiver:uart_Rx|bit_pos[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.021 ;
; 0.786 ; processor:processor_u|register_file:register_file_inst|current_state.REG_SENT ; processor:processor_u|register_file:register_file_inst|byte_counter[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.029 ;
; 0.794 ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; processor:processor_u|register_file:register_file_inst|incrementer[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 1.038 ;
; 0.816 ; transmitter:uart_Tx|state.TX_STATE_DATA ; transmitter:uart_Tx|bit_pos[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.059 ;
+-------+----------------------------------------------------------------------------------+----------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' ;
+-------+--------------+----------------+-----------------+----------+------------+----------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
+-------+--------------+----------------+-----------------+----------+------------+----------------------------------------------------------------------------------+
; 9.634 ; 9.820 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|ready ;
; 9.686 ; 9.872 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|data_out[0] ;
; 9.686 ; 9.872 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|data_out[1] ;
; 9.686 ; 9.872 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|data_out[2] ;
; 9.686 ; 9.872 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|data_out[3] ;
; 9.686 ; 9.872 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|data_out[4] ;
; 9.686 ; 9.872 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|data_out[5] ;
; 9.686 ; 9.872 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|data_out[6] ;
; 9.686 ; 9.872 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|data_out[7] ;
; 9.686 ; 9.872 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|scratch[4] ;
; 9.686 ; 9.872 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|scratch[7] ;
; 9.687 ; 9.873 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|scratch[0] ;
; 9.687 ; 9.873 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|scratch[1] ;
; 9.687 ; 9.873 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|scratch[2] ;
; 9.687 ; 9.873 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|scratch[3] ;
; 9.687 ; 9.873 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|scratch[5] ;
; 9.687 ; 9.873 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|scratch[6] ;
; 9.690 ; 9.876 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|sample[0] ;
; 9.690 ; 9.876 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|sample[1] ;
; 9.690 ; 9.876 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|sample[2] ;
; 9.690 ; 9.876 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|sample[3] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; baudrate:uart_baud|rx_acc[0] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; baudrate:uart_baud|rx_acc[1] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; baudrate:uart_baud|rx_acc[2] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; baudrate:uart_baud|rx_acc[3] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; baudrate:uart_baud|rx_acc[4] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|Ready_Byte ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|byte_counter[0] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|byte_counter[1] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[11] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[12] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[13] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[14] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[15] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[17] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[1] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[20] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[21] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[22] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[23] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[24] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[25] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[29] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[2] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[31] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[5] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[7] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[8] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[9] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_state.BYTE_SENT ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_state.IDLE ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_state.OUTPUT_BYTE ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_state.OUTPUT_REG ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_state.REG_SENT ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_state.SEND_BYTE ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|dout[0] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|dout[1] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|dout[2] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|dout[3] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|dout[4] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|dout[5] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|dout[6] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|dout[7] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|incrementer[0] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|incrementer[1] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|incrementer[2] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|incrementer[3] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|incrementer[4] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|bit_pos[0] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|bit_pos[1] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|bit_pos[2] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|bit_pos[3] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|state.RX_STATE_DATA ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|state.RX_STATE_START ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|state.RX_STATE_STOP ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; receiver:uart_Rx|state.Ready_clearing ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; transmitter:uart_Tx|Tx ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; transmitter:uart_Tx|data[6] ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; transmitter:uart_Tx|state.TX_STATE_DATA ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; transmitter:uart_Tx|state.TX_STATE_IDLE ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; transmitter:uart_Tx|state.TX_STATE_START ;
; 9.691 ; 9.877 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; transmitter:uart_Tx|state.TX_STATE_STOP ;
; 9.692 ; 9.878 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; baudrate:uart_baud|tx_acc[0] ;
; 9.692 ; 9.878 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; baudrate:uart_baud|tx_acc[1] ;
; 9.692 ; 9.878 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; baudrate:uart_baud|tx_acc[2] ;
; 9.692 ; 9.878 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; baudrate:uart_baud|tx_acc[3] ;
; 9.692 ; 9.878 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; baudrate:uart_baud|tx_acc[4] ;
; 9.692 ; 9.878 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; baudrate:uart_baud|tx_acc[5] ;
; 9.692 ; 9.878 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; baudrate:uart_baud|tx_acc[6] ;
; 9.692 ; 9.878 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; baudrate:uart_baud|tx_acc[7] ;
; 9.692 ; 9.878 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; baudrate:uart_baud|tx_acc[8] ;
; 9.692 ; 9.878 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[0] ;
; 9.692 ; 9.878 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[10] ;
; 9.692 ; 9.878 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[16] ;
; 9.692 ; 9.878 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[18] ;
; 9.692 ; 9.878 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[19] ;
; 9.692 ; 9.878 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[26] ;
; 9.692 ; 9.878 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[27] ;
; 9.692 ; 9.878 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[28] ;
; 9.692 ; 9.878 ; 0.186 ; Low Pulse Width ; CLOCK_50 ; Rise ; processor:processor_u|register_file:register_file_inst|current_reg_value[30] ;
+-------+--------------+----------------+-----------------+----------+------------+----------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK2_50' ;
+--------+--------------+----------------+-----------+-----------+------------+-----------+
; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
+--------+--------------+----------------+-----------+-----------+------------+-----------+
; 16.000 ; 20.000 ; 4.000 ; Port Rate ; CLOCK2_50 ; Rise ; CLOCK2_50 ;
+--------+--------------+----------------+-----------+-----------+------------+-----------+
+-----------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK3_50' ;
+--------+--------------+----------------+-----------+-----------+------------+-----------+
; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
+--------+--------------+----------------+-----------+-----------+------------+-----------+
; 16.000 ; 20.000 ; 4.000 ; Port Rate ; CLOCK3_50 ; Rise ; CLOCK3_50 ;
+--------+--------------+----------------+-----------+-----------+------------+-----------+
+-----------------------------------------------------------------------+
; Setup Times ;
+-----------+------------+-------+-------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+-----------------+
; EX_IO[*] ; CLOCK_50 ; 5.707 ; 6.260 ; Rise ; CLOCK_50 ;
; EX_IO[1] ; CLOCK_50 ; 5.707 ; 6.260 ; Rise ; CLOCK_50 ;
; KEY[*] ; CLOCK_50 ; 5.139 ; 5.713 ; Rise ; CLOCK_50 ;
; KEY[2] ; CLOCK_50 ; 5.139 ; 5.713 ; Rise ; CLOCK_50 ;
+-----------+------------+-------+-------+------------+-----------------+
+-------------------------------------------------------------------------+
; Hold Times ;
+-----------+------------+--------+--------+------------+-----------------+