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Single_Cycle_RISC_Processor.eda.rpt
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EDA Netlist Writer report for Single_Cycle_RISC_Processor
Sun Dec 15 22:39:24 2024
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. EDA Netlist Writer Summary
3. Simulation Settings
4. Simulation Generated Files
5. EDA Netlist Writer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------+
; EDA Netlist Writer Summary ;
+---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Sun Dec 15 22:39:24 2024 ;
; Revision Name ; Single_Cycle_RISC_Processor ;
; Top-level Entity Name ; Single_Cycle_RISC_Processor ;
; Family ; Cyclone IV E ;
; Simulation Files Creation ; Successful ;
+---------------------------+---------------------------------------+
+-------------------------------------------------------------------------------------------------------------------------------+
; Simulation Settings ;
+---------------------------------------------------------------------------------------------------+---------------------------+
; Option ; Setting ;
+---------------------------------------------------------------------------------------------------+---------------------------+
; Tool Name ; ModelSim-Altera (Verilog) ;
; Generate netlist for functional simulation only ; Off ;
; Time scale ; 1 ps ;
; Truncate long hierarchy paths ; Off ;
; Map illegal HDL characters ; Off ;
; Flatten buses into individual nodes ; Off ;
; Maintain hierarchy ; Off ;
; Bring out device-wide set/reset signals as ports ; Off ;
; Enable glitch filtering ; Off ;
; Do not write top level VHDL entity ; Off ;
; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
; Architecture name in VHDL output netlist ; structure ;
; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
; Generate third-party EDA tool command script for gate-level simulation ; Off ;
+---------------------------------------------------------------------------------------------------+---------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------+
; Simulation Generated Files ;
+------------------------------------------------------------------------------------------------------------------------------------------+
; Generated Files ;
+------------------------------------------------------------------------------------------------------------------------------------------+
; D:/FPGA_Projects/RV32I_Processor/Pipelined-Processor-In-DE2-115/simulation/modelsim/Single_Cycle_RISC_Processor_7_1200mv_85c_slow.vo ;
; D:/FPGA_Projects/RV32I_Processor/Pipelined-Processor-In-DE2-115/simulation/modelsim/Single_Cycle_RISC_Processor_7_1200mv_0c_slow.vo ;
; D:/FPGA_Projects/RV32I_Processor/Pipelined-Processor-In-DE2-115/simulation/modelsim/Single_Cycle_RISC_Processor_min_1200mv_0c_fast.vo ;
; D:/FPGA_Projects/RV32I_Processor/Pipelined-Processor-In-DE2-115/simulation/modelsim/Single_Cycle_RISC_Processor.vo ;
; D:/FPGA_Projects/RV32I_Processor/Pipelined-Processor-In-DE2-115/simulation/modelsim/Single_Cycle_RISC_Processor_7_1200mv_85c_v_slow.sdo ;
; D:/FPGA_Projects/RV32I_Processor/Pipelined-Processor-In-DE2-115/simulation/modelsim/Single_Cycle_RISC_Processor_7_1200mv_0c_v_slow.sdo ;
; D:/FPGA_Projects/RV32I_Processor/Pipelined-Processor-In-DE2-115/simulation/modelsim/Single_Cycle_RISC_Processor_min_1200mv_0c_v_fast.sdo ;
; D:/FPGA_Projects/RV32I_Processor/Pipelined-Processor-In-DE2-115/simulation/modelsim/Single_Cycle_RISC_Processor_v.sdo ;
+------------------------------------------------------------------------------------------------------------------------------------------+
+-----------------------------+
; EDA Netlist Writer Messages ;
+-----------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit EDA Netlist Writer
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Info: Processing started: Sun Dec 15 22:39:14 2024
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off Single_Cycle_RISC_Processor -c Single_Cycle_RISC_Processor
Info (204019): Generated file Single_Cycle_RISC_Processor_7_1200mv_85c_slow.vo in folder "D:/FPGA_Projects/RV32I_Processor/Pipelined-Processor-In-DE2-115/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file Single_Cycle_RISC_Processor_7_1200mv_0c_slow.vo in folder "D:/FPGA_Projects/RV32I_Processor/Pipelined-Processor-In-DE2-115/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file Single_Cycle_RISC_Processor_min_1200mv_0c_fast.vo in folder "D:/FPGA_Projects/RV32I_Processor/Pipelined-Processor-In-DE2-115/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file Single_Cycle_RISC_Processor.vo in folder "D:/FPGA_Projects/RV32I_Processor/Pipelined-Processor-In-DE2-115/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file Single_Cycle_RISC_Processor_7_1200mv_85c_v_slow.sdo in folder "D:/FPGA_Projects/RV32I_Processor/Pipelined-Processor-In-DE2-115/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file Single_Cycle_RISC_Processor_7_1200mv_0c_v_slow.sdo in folder "D:/FPGA_Projects/RV32I_Processor/Pipelined-Processor-In-DE2-115/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file Single_Cycle_RISC_Processor_min_1200mv_0c_v_fast.sdo in folder "D:/FPGA_Projects/RV32I_Processor/Pipelined-Processor-In-DE2-115/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file Single_Cycle_RISC_Processor_v.sdo in folder "D:/FPGA_Projects/RV32I_Processor/Pipelined-Processor-In-DE2-115/simulation/modelsim/" for EDA simulation tool
Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 4631 megabytes
Info: Processing ended: Sun Dec 15 22:39:25 2024
Info: Elapsed time: 00:00:11
Info: Total CPU time (on all processors): 00:00:09