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Copy pathSingle_Cycle_RISC_Processor.asm.rpt
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Single_Cycle_RISC_Processor.asm.rpt
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Assembler report for Single_Cycle_RISC_Processor
Sun Dec 15 22:39:02 2024
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: D:/FPGA_Projects/RV32I_Processor/Pipelined-Processor-In-DE2-115/Single_Cycle_RISC_Processor.sof
6. Assembler Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Sun Dec 15 22:39:02 2024 ;
; Revision Name ; Single_Cycle_RISC_Processor ;
; Top-level Entity Name ; Single_Cycle_RISC_Processor ;
; Family ; Cyclone IV E ;
; Device ; EP4CE115F29C7 ;
+-----------------------+---------------------------------------+
+--------------------------------------------------------------------------------------------------------+
; Assembler Settings ;
+-----------------------------------------------------------------------------+----------+---------------+
; Option ; Setting ; Default Value ;
+-----------------------------------------------------------------------------+----------+---------------+
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Generate compressed bitstreams ; On ; On ;
; Compression mode ; Off ; Off ;
; Clock source for configuration device ; Internal ; Internal ;
; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ;
; Divide clock frequency by ; 1 ; 1 ;
; Auto user code ; On ; On ;
; Use configuration device ; Off ; Off ;
; Configuration device ; Auto ; Auto ;
; Configuration device auto user code ; Off ; Off ;
; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ;
; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ;
; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ;
; Hexadecimal Output File start address ; 0 ; 0 ;
; Hexadecimal Output File count direction ; Up ; Up ;
; Release clears before tri-states ; Off ; Off ;
; Auto-restart configuration after error ; On ; On ;
; Enable OCT_DONE ; Off ; Off ;
; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ;
; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ;
+-----------------------------------------------------------------------------+----------+---------------+
+-------------------------------------------------------------------------------------------------+
; Assembler Generated Files ;
+-------------------------------------------------------------------------------------------------+
; File Name ;
+-------------------------------------------------------------------------------------------------+
; D:/FPGA_Projects/RV32I_Processor/Pipelined-Processor-In-DE2-115/Single_Cycle_RISC_Processor.sof ;
+-------------------------------------------------------------------------------------------------+
+---------------------------------------------------------------------------------------------------------------------------+
; Assembler Device Options: D:/FPGA_Projects/RV32I_Processor/Pipelined-Processor-In-DE2-115/Single_Cycle_RISC_Processor.sof ;
+----------------+----------------------------------------------------------------------------------------------------------+
; Option ; Setting ;
+----------------+----------------------------------------------------------------------------------------------------------+
; Device ; EP4CE115F29C7 ;
; JTAG usercode ; 0x00A3B0AD ;
; Checksum ; 0x00A3B0AD ;
+----------------+----------------------------------------------------------------------------------------------------------+
+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit Assembler
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Info: Processing started: Sun Dec 15 22:38:55 2024
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off Single_Cycle_RISC_Processor -c Single_Cycle_RISC_Processor
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 4619 megabytes
Info: Processing ended: Sun Dec 15 22:39:02 2024
Info: Elapsed time: 00:00:07
Info: Total CPU time (on all processors): 00:00:05