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emu65816.c
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emu65816.c
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#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <stdbool.h>
// Comment out this #define if compiling on a Big Endian System/CPU
#define __EMU_LITTLE_ENDIAN
#include "emu65816_library.h"
// Initalizes the CPU struct
void cpuInit(cpuState* CPU, uint8_t* memory, uint32_t memSize, uint32_t ioAddress, uint32_t ioSize, uint8_t (*ioRead)(uint32_t), void (*ioWrite)(uint32_t, uint8_t)){
CPU->wai = false;
CPU->stp = false;
MEM = memory;
CPU->io_read = ioRead;
CPU->io_write = ioWrite;
IOB = ioAddress;
IOS = ioSize;
MES = memSize;
INT = 0;
DBG = false;
A.w = 0;
X.w = 0;
Y.w = 0;
PC.bl = readMem(CPU, VECT_E_RES);
PC.bh = readMem(CPU, VECT_E_RES + 1);
SP.w = 0x01FD;
DP.w = 0;
PB = 0;
DB = 0;
EF = true; // Emulation Mode
// printf("CPU starting execution at 0x%04X (read from Reset vector at: 0x%04X)\n", PC.w, VECT_E_RES);
writeSR(CPU, SR_INIT);
}
// Executes instructions for a set amount of cycles
// Returns how many Cycles it didn't use, value is negative if it used more Cycles than requested
int32_t cpuExecute(cpuState* CPU, int32_t cycles){
int32_t cycleRem = cycles;
uint8_t opcode;
bool _pre_debug = DBG;
cint32_t tmp0, tmp1, tmp2, tmp3;
// If a STP instruction was executed, exit immediately
if (CPU->stp) return 0;
// If a WAI instruction was executed but no interrupt was issued, exit immediately
if (CPU->wai) return cycleRem;
// Handle Hardware Interrupts (IRQ, NMI, ABT)
if(INT){
if (EF){ // Emulation
pushStack(CPU, PC.bh);
pushStack(CPU, PC.bl);
pushStack(CPU, readSR(CPU) | SR_INT);
setD(false);
setI(true);
PC.bl = readMem(CPU, interruptTableE[INT]);
PC.bh = readMem(CPU, interruptTableE[INT] + 1);
PB = 0;
}else{ // Native
pushStack(CPU, PB);
pushStack(CPU, PC.bh);
pushStack(CPU, PC.bl);
pushStack(CPU, readSR(CPU));
setD(false);
setI(true);
PC.bl = readMem(CPU, interruptTableN[INT]);
PC.bh = readMem(CPU, interruptTableN[INT] + 1);
PB = 0;
}
INT = 0;
}
next:
// Clear the high Bytes of X and Y when XF=1, in case they were changed somehow
if (XF){
X.bh = 0;
Y.bh = 0;
}
// Update the Upper Byte of the SP when EF=1, in case it got changed somehow
if (EF) SP.bh = 1;
// Fetch an Opcode
opcode = fetch(CPU);
// Decode it
// Run the correct operation
// Subtract the amount of Cycles spend from the total
// If the total reaches or supasses 0, get the difference and return it
// Otherwise execute another Instruction
dbg_printf("Executing Instruction (0x%02X at 0x%02X%04X): ", opcode, PB, PC.w - 1);
//dbg_printf("\"%s\"", inst_names[opcode]);
switch(opcode){
// Jumps ----------------------------------------------------------------- //
// Absolute
case OP_JMP_A:
tmp0.bl = fetch(CPU);
tmp0.bm = fetch(CPU);
PC.w = tmp0.wl;
dbg_printf("JMP $%04X", PC.w);
break;
// Absolute Indirect
case OP_JMP_AI:
tmp0.bl = fetch(CPU);
tmp0.bm = fetch(CPU);
PC.bl = readMem(CPU, 0x0000FFFF & (tmp0.wl));
PC.bh = readMem(CPU, 0x0000FFFF & (tmp0.wl + 1));
dbg_printf("JMP ($%04X) (Value: $%04X)", tmp0.wl, PC.w);
break;
// Absolute X Indirect
case OP_JMP_AXI:
tmp0.bl = fetch(CPU);
tmp0.bm = fetch(CPU);
PC.bl = readMem(CPU, 0x00FFFFFF & ((PB << 16U) | (((uint32_t)tmp0.wl + X.w) & 0x0000FFFF)));
PC.bh = readMem(CPU, 0x00FFFFFF & ((PB << 16U) | (((uint32_t)tmp0.wl + X.w + 1) & 0x0000FFFF)));
dbg_printf("JMP ($%04X,X) (Target: $%06X, Value: $%04X)", tmp0.wl, 0x00FFFFFF & ((PB << 16U) | (((uint32_t)tmp0.wl + X.w) & 0x0000FFFF)), PC.w);
break;
// Absolute Indirect Long
case OP_JML_AI:
tmp0.bl = fetch(CPU);
tmp0.bm = fetch(CPU);
PC.bl = readMem(CPU, 0x0000FFFF & (tmp0.wl));
PC.bh = readMem(CPU, 0x0000FFFF & (tmp0.wl + 1));
PB = readMem(CPU, 0x0000FFFF & (tmp0.wl + 2));
dbg_printf("JML ($%04X) (Value: $%02X%04X)", tmp0.wl, PB, PC.w);
break;
// Absolute Long
case OP_JML_AL:
tmp0.bl = fetch(CPU);
tmp0.bm = fetch(CPU);
tmp0.bh = fetch(CPU);
PC.w = tmp0.wl;
PB = tmp0.bh;
dbg_printf("JML $%02X%04X", PB, PC.w);
break;
// Absolute
case OP_JSR_A:
tmp0.bl = fetch(CPU);
pushStack(CPU, PC.bh);
pushStack(CPU, PC.bl); // Push the PC before fetching the 2nd Operand
tmp0.bm = fetch(CPU);
PC.w = tmp0.wl;
dbg_printf("JSR $%04X ------------------------------------------------", PC.w);
break;
// Absolute X Indirect
case OP_JSR_AXI:
tmp0.bl = fetch(CPU);
pushStack(CPU, PC.bh);
pushStack(CPU, PC.bl); // Push the PC before fetching the 2nd Operand
tmp0.bm = fetch(CPU);
PC.bl = readMem(CPU, 0x00FFFFFF & ((PB << 16U) | (((uint32_t)tmp0.wl + X.w) & 0x0000FFFF)));
PC.bh = readMem(CPU, 0x00FFFFFF & ((PB << 16U) | (((uint32_t)tmp0.wl + X.w + 1) & 0x0000FFFF)));
dbg_printf("JSR ($%04X,X) (Target: $%06X, Value: $%04X)", tmp0.wl, (tmp0.wl + X.w) & 0x0000FFFF, PC.w);
break;
// Absolute Long
case OP_JSL_AL:
tmp3.bl = EF; // Save the E Flag
tmp0.bl = fetch(CPU);
tmp0.bm = fetch(CPU);
setE(false); // Then Clear it
pushStack(CPU, PB);
pushStack(CPU, PC.bh);
pushStack(CPU, PC.bl); // Push the PC before fetching the 3rd Operand
setE(tmp3.bl); // And afterwards restore it again
tmp0.bh = fetch(CPU);
PC.w = tmp0.wl;
PB = tmp0.bh;
dbg_printf("JSL $%02X%04X ----------------------------------------------", PB, PC.w);
break;
// Returns --------------------------------------------------------------- //
// From Subroutine
case OP_RTS:
tmp0.bl = pullStack(CPU);
tmp0.bm = pullStack(CPU);
PC.w = tmp0.wl + 1;
dbg_printf("RTS (Target: $%02X%04X)", PB, PC.w);
break;
// From Long Subroutine
case OP_RTL:
tmp3.bl = EF; // Save the E Flag
setE(false); // Then Clear it
tmp0.bl = pullStack(CPU);
tmp0.bm = pullStack(CPU);
PC.w = tmp0.wl + 1;
PB = pullStack(CPU);
setE(tmp3.bl); // And afterwards restore it again
dbg_printf("RTL (Target: $%02X%04X)", PB, PC.w);
break;
// From Interrupt
case OP_RTI:
if (EF){ // Emulation
writeSR(CPU, pullStack(CPU) | SR_BRK);
PC.bl = pullStack(CPU);
PC.bh = pullStack(CPU);
}else{ // Native
writeSR(CPU, pullStack(CPU));
PC.bl = pullStack(CPU);
PC.bh = pullStack(CPU);
PB = pullStack(CPU);
}
dbg_printf("RTI (Target: $%02X%04X)", PB, PC.w);
break;
// Branches -------------------------------------------------------------- //
// Branch on Carry Clear/Set
case OP_BCS_R:
case OP_BCC_R:
tmp0.bl = fetch(CPU); // Relative Offset
if (opcode & 0b00100000){
dbg_printf("BCS (Target: $%02X%04X, ", PB, PC.w + tmp0.sbl);
}else{
dbg_printf("BCC (Target: $%02X%04X, ", PB, PC.w + tmp0.sbl);
}
if (!CF == !(opcode & 0b00100000)){ // If bit 5 of the opcode is the same as the Flag to check, take the branch
PC.w += tmp0.sbl;
dbg_printf("Taken)");
}else{
dbg_printf("Not Taken)");
}
break;
// Branch on Zero Clear/Set
case OP_BEQ_R:
case OP_BNE_R:
tmp0.bl = fetch(CPU); // Relative Offset
if (opcode & 0b00100000){
dbg_printf("BEQ (Target: $%02X%04X, ", PB, PC.w + tmp0.sbl);
}else{
dbg_printf("BNE (Target: $%02X%04X, ", PB, PC.w + tmp0.sbl);
}
if (!ZF == !(opcode & 0b00100000)){ // If bit 5 of the opcode is the same as the Flag to check, take the branch
PC.w += tmp0.sbl;
dbg_printf("Taken)");
}else{
dbg_printf("Not Taken)");
}
break;
// Branch on Interrupt Clear/Set
case OP_BMI_R:
case OP_BPL_R:
tmp0.bl = fetch(CPU); // Relative Offset
if (opcode & 0b00100000){
dbg_printf("BMI (Target: $%02X%04X, ", PB, PC.w + tmp0.sbl);
}else{
dbg_printf("BPL (Target: $%02X%04X, ", PB, PC.w + tmp0.sbl);
}
if (!NF == !(opcode & 0b00100000)){ // If bit 5 of the opcode is the same as the Flag to check, take the branch
PC.w += tmp0.sbl;
dbg_printf("Taken)");
}else{
dbg_printf("Not Taken)");
}
break;
// Branch on Overflow Clear/Set
case OP_BVS_R:
case OP_BVC_R:
tmp0.bl = fetch(CPU); // Relative Offset
if (opcode & 0b00100000){
dbg_printf("BVS (Target: $%02X%04X, ", PB, PC.w + tmp0.sbl);
}else{
dbg_printf("BVC (Target: $%02X%04X, ", PB, PC.w + tmp0.sbl);
}
if (!VF == !(opcode & 0b00100000)){ // If bit 5 of the opcode is the same as the Flag to check, take the branch
PC.w += tmp0.sbl;
dbg_printf("Taken)");
}else{
dbg_printf("Not Taken)");
}
break;
// Unconditional Branches
case OP_BRA_R:
tmp0.bl = fetch(CPU); // Relative Offset
PC.w += tmp0.sbl;
dbg_printf("BRA (Target: $%02X%04X)", PB, PC.w);
break;
case OP_BRL_R:
tmp0.bl = fetch(CPU);
tmp0.bm = fetch(CPU); // 16-bit Relative Offset
PC.w += tmp0.swl;
dbg_printf("BRA (Target: $%02X%04X)", PB, PC.w);
break;
// Stack Operations ------------------------------------------------------ //
// 16 bit Pushes
// Immediate
case OP_PEA_IM:
tmp3.bl = EF; // Save the E Flag
tmp0.bl = fetch(CPU);
tmp0.bm = fetch(CPU);
setE(false); // Then Clear it
pushStack(CPU, tmp0.bm);
pushStack(CPU, tmp0.bl);
setE(tmp3.bl); // And afterwards restore it again
dbg_printf("PEA #$%04X", tmp0.wl);
break;
// Direct Page
case OP_PEI_DP:
tmp3.bl = EF; // Save the E Flag
tmp0.bl = fetch(CPU);
tmp1.bl = readDP(CPU, tmp0.bl);
tmp1.bm = readDP(CPU, tmp0.bl + 1);
setE(false); // Then Clear it
pushStack(CPU, tmp1.bm);
pushStack(CPU, tmp1.bl);
setE(tmp3.bl); // And afterwards restore it again
dbg_printf("PEI $%02X (Target: $%06X, Value: $%04X)", tmp0.bl, addrDP(CPU, tmp0.bl), tmp1.wl);
break;
// Immediate
case OP_PER_IM:
tmp3.bl = EF; // Save the E Flag
tmp0.bl = fetch(CPU);
tmp0.bm = fetch(CPU);
tmp1.wl = tmp0.wl;
tmp1.wl += PC.w; // Add the Address of the next Instruction before pushing to the Stack
setE(false); // Then Clear it
pushStack(CPU, tmp1.bm);
pushStack(CPU, tmp1.bl);
setE(tmp3.bl); // And afterwards restore it again
dbg_printf("PER #$%04X (Value: $%04X)", tmp0.wl, tmp1.wl);
break;
// Push Registers
case OP_PHB:
pushStack(CPU, DB);
dbg_printf("PHB (Target: $%06X, Value: $%02X)", addrStack(CPU, -1), DB);
break;
case OP_PHD:
tmp3.bl = EF; // Save the E Flag
setE(false); // Then Clear it
pushStack(CPU, DP.bh);
pushStack(CPU, DP.bl);
setE(tmp3.bl); // And afterwards restore it again
dbg_printf("PHD (Target: $%06X, Value: $%02X)", addrStack(CPU, -1), DP.w);
break;
case OP_PHK:
pushStack(CPU, PB);
dbg_printf("PHK (Target: $%06X, Value: $%02X)", addrStack(CPU, -1), PB);
break;
case OP_PHP:
if (EF){ // Emulation
pushStack(CPU, readSR(CPU) | SR_BRK);
dbg_printf("PHP (Target: $%06X, Value: $%02X)", addrStack(CPU, -1), readSR(CPU) | SR_BRK);
}else{ // Native
pushStack(CPU, readSR(CPU));
dbg_printf("PHP (Target: $%06X, Value: $%02X)", addrStack(CPU, -1), readSR(CPU));
}
break;
case OP_PHA:
if (!MF) pushStack(CPU, A.bh);
pushStack(CPU, A.bl);
if (MF){
dbg_printf("PHA (Target: $%06X, Value: $%02X)", addrStack(CPU, -1), A.bl);
}else{
dbg_printf("PHA (Target: $%06X, Value: $%04X)", addrStack(CPU, -1), A.w);
}
break;
case OP_PHX:
if (!XF) pushStack(CPU, X.bh);
pushStack(CPU, X.bl);
if (XF){
dbg_printf("PHX (Target: $%06X, Value: $%02X)", addrStack(CPU, -1), X.bl);
}else{
dbg_printf("PHX (Target: $%06X, Value: $%04X)", addrStack(CPU, -1), X.w);
}
break;
case OP_PHY:
if (!XF) pushStack(CPU, Y.bh);
pushStack(CPU, Y.bl);
if (XF){
dbg_printf("PHY (Target: $%06X, Value: $%02X)", addrStack(CPU, -1), Y.bl);
}else{
dbg_printf("PHY (Target: $%06X, Value: $%04X)", addrStack(CPU, -1), Y.w);
}
break;
// Pull Registers
case OP_PLB:
DB = pullStack(CPU);
setNZ(CPU, true, DB);
dbg_printf("PLB (Target: $%06X, Value: $%02X)", addrStack(CPU, -1), DB);
break;
case OP_PLD:
tmp3.bl = EF; // Save the E Flag
setE(false); // Then Clear it
DP.bl = pullStack(CPU);
DP.bh = pullStack(CPU);
setE(tmp3.bl); // And afterwards restore it again
setNZ(CPU, false, DP.w);
dbg_printf("PLD (Target: $%06X, Value: $%02X)", addrStack(CPU, -1), DP.w);
break;
case OP_PLP:
if (EF){ // Emulation
writeSR(CPU, pullStack(CPU) | SR_BRK);
}else{
writeSR(CPU, pullStack(CPU));
}
dbg_printf("PLP (Target: $%06X, Value: $%02X)", addrStack(CPU, -1), readSR(CPU));
break;
case OP_PLA:
A.bl = pullStack(CPU);
if (!MF) A.bh = pullStack(CPU);
setNZ(CPU, MF, A.w);
if (MF){
dbg_printf("PLA (Target: $%06X, Value: $%02X)", addrStack(CPU, -1), A.bl);
}else{
dbg_printf("PLA (Target: $%06X, Value: $%04X)", addrStack(CPU, -1), A.w);
}
break;
case OP_PLX:
X.bl = pullStack(CPU);
if (!XF) X.bh = pullStack(CPU);
setNZ(CPU, XF, X.w);
if (XF){
dbg_printf("PLX (Target: $%06X, Value: $%02X)", addrStack(CPU, -1), X.bl);
}else{
dbg_printf("PLX (Target: $%06X, Value: $%04X)", addrStack(CPU, -1), X.w);
}
break;
case OP_PLY:
Y.bl = pullStack(CPU);
if (!XF) Y.bh = pullStack(CPU);
setNZ(CPU, XF, Y.w);
if (XF){
dbg_printf("PLY (Target: $%06X, Value: $%02X)", addrStack(CPU, -1), Y.bl);
}else{
dbg_printf("PLY (Target: $%06X, Value: $%04X)", addrStack(CPU, -1), Y.w);
}
break;
// Load/Store Accumulator ------------------------------------------------ //
// Load
// Immediate
case OP_LDA_IM:
A.bl = fetch(CPU);
if (!MF) A.bh = fetch(CPU);
setNZ(CPU, MF, A.w);
if (MF){
dbg_printf("LDA #$%02X", A.bl);
}else{
dbg_printf("LDA #$%04X", A.w);
}
break;
// Absolute
case OP_LDA_A:
tmp0.bl = fetch(CPU);
tmp0.bm = fetch(CPU);
A.bl = readAbs(CPU, tmp0.wl);
if (!MF) A.bh = readAbs(CPU, tmp0.wl + 1);
setNZ(CPU, MF, A.w);
if (MF){
dbg_printf("LDA $%04X (Target: $%06X, Value: $%02X)", tmp0.wl, addrAbs(CPU, tmp0.wl), A.bl);
}else{
dbg_printf("LDA $%04X (Target: $%06X, Value: $%04X)", tmp0.wl, addrAbs(CPU, tmp0.wl), A.w);
}
break;
// Absolute X
case OP_LDA_AX:
tmp0.bl = fetch(CPU);
tmp0.bm = fetch(CPU);
A.bl = readAbs(CPU, tmp0.wl + X.w);
if (!MF) A.bh = readAbs(CPU, tmp0.wl + X.w + 1);
setNZ(CPU, MF, A.w);
if (MF){
dbg_printf("LDA $%04X,X (Target: $%06X, Value: $%02X)", tmp0.wl, addrAbs(CPU, tmp0.wl + X.w), A.bl);
}else{
dbg_printf("LDA $%04X,X (Target: $%06X, Value: $%04X)", tmp0.wl, addrAbs(CPU, tmp0.wl + X.w), A.w);
}
break;
// Absolute Y
case OP_LDA_AY:
tmp0.bl = fetch(CPU);
tmp0.bm = fetch(CPU);
A.bl = readAbs(CPU, tmp0.wl + Y.w);
if (!MF) A.bh = readAbs(CPU, tmp0.wl + Y.w + 1);
setNZ(CPU, MF, A.w);
if (MF){
dbg_printf("LDA $%04X,Y (Target: $%06X, Value: $%02X)", tmp0.wl, addrAbs(CPU, tmp0.wl + Y.w), A.bl);
}else{
dbg_printf("LDA $%04X,Y (Target: $%06X, Value: $%04X)", tmp0.wl, addrAbs(CPU, tmp0.wl + Y.w), A.w);
}
break;
// Absolute Long
case OP_LDA_AL:
tmp0.bl = fetch(CPU);
tmp0.bm = fetch(CPU);
tmp0.bh = fetch(CPU);
tmp0.bx = 0;
A.bl = readMem(CPU, tmp0.l);
if (!MF) A.bh = readMem(CPU, tmp0.l + 1);
setNZ(CPU, MF, A.w);
if (MF){
dbg_printf("LDA $%06X (Value: $%02X)", tmp0.l, A.bl);
}else{
dbg_printf("LDA $%06X (Value: $%04X)", tmp0.l, A.w);
}
break;
// Absolute Long X
case OP_LDA_ALX:
tmp0.bl = fetch(CPU);
tmp0.bm = fetch(CPU);
tmp0.bh = fetch(CPU);
tmp0.bx = 0;
A.bl = readMem(CPU, tmp0.l + X.w);
if (!MF) A.bh = readMem(CPU, tmp0.l + X.w + 1);
setNZ(CPU, MF, A.w);
if (MF){
dbg_printf("LDA $%06X,X (Target: $%06X, Value: $%02X)", tmp0.l, tmp0.l + X.w, A.bl);
}else{
dbg_printf("LDA $%06X,X (Target: $%06X, Value: $%04X)", tmp0.l, tmp0.l + X.w, A.w);
}
break;
// Direct Page
case OP_LDA_DP:
tmp0.bl = fetch(CPU);
A.bl = readDP(CPU, tmp0.bl);
if (!MF) A.bh = readDP(CPU, tmp0.bl + 1);
setNZ(CPU, MF, A.w);
if (MF){
dbg_printf("LDA $%02X (Target: $%06X, Value: $%02X)", tmp0.bl, addrDP(CPU, tmp0.bl), A.bl);
}else{
dbg_printf("LDA $%02X (Target: $%06X, Value: $%04X)", tmp0.bl, addrDP(CPU, tmp0.bl), A.w);
}
break;
// Direct Page X
case OP_LDA_DPX:
tmp0.bl = fetch(CPU);
A.bl = readDP(CPU, tmp0.bl + X.w);
if (!MF) A.bh = readDP(CPU, tmp0.bl + X.w + 1);
setNZ(CPU, MF, A.w);
if (MF){
dbg_printf("LDA $%02X,X (Target: $%06X, Value: $%02X)", tmp0.bl, addrDP(CPU, tmp0.bl + X.w), A.bl);
}else{
dbg_printf("LDA $%02X,X (Target: $%06X, Value: $%04X)", tmp0.bl, addrDP(CPU, tmp0.bl + X.w), A.w);
}
break;
// Direct Page Indirect
case OP_LDA_DPI:
tmp0.bl = fetch(CPU);
tmp1.bl = readDP(CPU, tmp0.bl);
tmp1.bm = readDP(CPU, tmp0.bl + 1);
A.bl = readAbs(CPU, tmp1.wl);
if (!MF) A.bh = readAbs(CPU, tmp1.wl + 1);
setNZ(CPU, MF, A.w);
if (MF){
dbg_printf("LDA ($%02X) (Target: $%06X, Value: $%02X)", tmp0.bl, addrAbs(CPU, tmp1.wl), A.bl);
}else{
dbg_printf("LDA ($%02X) (Target: $%06X, Value: $%04X)", tmp0.bl, addrAbs(CPU, tmp1.wl), A.w);
}
break;
// Direct Page X Indirect
case OP_LDA_DPXI:
tmp0.bl = fetch(CPU);
tmp1.bl = readDP(CPU, tmp0.bl + X.w);
tmp1.bm = readDP(CPU, tmp0.bl + X.w + 1);
A.bl = readAbs(CPU, tmp1.wl);
if (!MF) A.bh = readAbs(CPU, tmp1.wl + 1);
setNZ(CPU, MF, A.w);
if (MF){
dbg_printf("LDA ($%02X,X) (Target: $%06X, Value: $%02X)", tmp0.bl, addrAbs(CPU, tmp1.wl), A.bl);
}else{
dbg_printf("LDA ($%02X,X) (Target: $%06X, Value: $%04X)", tmp0.bl, addrAbs(CPU, tmp1.wl), A.w);
}
break;
// Direct Page Indirect Y
case OP_LDA_DPIY:
tmp0.bl = fetch(CPU);
tmp1.bl = readDP(CPU, tmp0.bl);
tmp1.bm = readDP(CPU, tmp0.bl + 1);
A.bl = readAbs(CPU, tmp1.wl + Y.w);
if (!MF) A.bh = readAbs(CPU, tmp1.wl + Y.w + 1);
setNZ(CPU, MF, A.w);
if (MF){
dbg_printf("LDA ($%02X),Y (Target: $%06X, Value: $%02X)", tmp0.bl, addrAbs(CPU, tmp1.wl + Y.w), A.bl);
}else{
dbg_printf("LDA ($%02X),Y (Target: $%06X, Value: $%04X)", tmp0.bl, addrAbs(CPU, tmp1.wl + Y.w), A.w);
}
break;
// Direct Page Indirect Long
case OP_LDA_DPIL:
tmp0.bl = fetch(CPU);
tmp1.bl = readDP(CPU, tmp0.bl);
tmp1.bm = readDP(CPU, tmp0.bl + 1);
tmp1.bh = readDP(CPU, tmp0.bl + 2);
tmp1.bx = 0;
A.bl = readMem(CPU, tmp1.l);
if (!MF) A.bh = readMem(CPU, tmp1.l + 1);
setNZ(CPU, MF, A.w);
if (MF){
dbg_printf("LDA [$%02X] (Target: $%06X, Value: $%02X)", tmp0.bl, tmp1.l, A.bl);
}else{
dbg_printf("LDA [$%02X] (Target: $%06X, Value: $%04X)", tmp0.bl, tmp1.l, A.w);
}
break;
// Direct Page Indirect Long Y
case OP_LDA_DPILY:
tmp0.bl = fetch(CPU);
tmp1.bl = readDP(CPU, tmp0.bl);
tmp1.bm = readDP(CPU, tmp0.bl + 1);
tmp1.bh = readDP(CPU, tmp0.bl + 2);
tmp1.bx = 0;
A.bl = readMem(CPU, tmp1.l + Y.w);
if (!MF) A.bh = readMem(CPU, tmp1.l + Y.w + 1);
setNZ(CPU, MF, A.w);
if (MF){
dbg_printf("LDA [$%02X],Y (Target: $%06X, Value: $%02X)", tmp0.bl, tmp1.l + Y.w, A.bl);
}else{
dbg_printf("LDA [$%02X],Y (Target: $%06X, Value: $%04X)", tmp0.bl, tmp1.l + Y.w, A.w);
}
break;
// Stack
case OP_LDA_S:
tmp3.bl = EF; // Save the E Flag
tmp0.bl = fetch(CPU);
setE(false); // Then Clear it
A.bl = readStack(CPU, tmp0.bl);
if (!MF) A.bh = readStack(CPU, tmp0.bl + 1);
setE(tmp3.bl); // And afterwards restore it again
setNZ(CPU, MF, A.w);
if (MF){
dbg_printf("LDA %u,S (Target: $%06X, Value: $%02X)", tmp0.bl, addrStack(CPU, tmp0.bl), A.bl);
}else{
dbg_printf("LDA %u,S (Target: $%06X, Value: $%04X)", tmp0.bl, addrStack(CPU, tmp0.bl), A.w);
}
break;
// Stack Indirect Y
case OP_LDA_SIY:
tmp3.bl = EF; // Save the E Flag
tmp0.bl = fetch(CPU);
setE(false); // Then Clear it
tmp1.bl = readStack(CPU, tmp0.bl);
tmp1.bm = readStack(CPU, tmp0.bl + 1);
setE(tmp3.bl); // And afterwards restore it again
A.bl = readAbs(CPU, tmp1.wl + Y.w);
if (!MF) A.bh = readAbs(CPU, tmp1.wl + Y.w + 1);
setNZ(CPU, MF, A.w);
if (MF){
dbg_printf("LDA (%u,S),Y (Target: $%06X, Value: $%02X)", tmp0.bl, addrAbs(CPU, tmp1.wl + Y.w), A.bl);
}else{
dbg_printf("LDA (%u,S),Y (Target: $%06X, Value: $%04X)", tmp0.bl, addrAbs(CPU, tmp1.wl + Y.w), A.w);
}
break;
// Store
// Absolute
case OP_STA_A:
tmp0.bl = fetch(CPU);
tmp0.bm = fetch(CPU);
writeAbs(CPU, tmp0.wl, A.bl);
if (!MF) writeAbs(CPU, tmp0.wl + 1, A.bh);
if (MF){
dbg_printf("STA $%04X (Target: $%06X, Value: $%02X)", tmp0.wl, addrAbs(CPU, tmp0.wl), A.bl);
}else{
dbg_printf("STA $%04X (Target: $%06X, Value: $%04X)", tmp0.wl, addrAbs(CPU, tmp0.wl), A.w);
}
break;
// Absolute X
case OP_STA_AX:
tmp0.bl = fetch(CPU);
tmp0.bm = fetch(CPU);
writeAbs(CPU, tmp0.wl + X.w, A.bl);
if (!MF) writeAbs(CPU, tmp0.wl + X.w + 1, A.bh);
if (MF){
dbg_printf("STA $%04X,X (Target: $%06X, Value: $%02X)", tmp0.wl, addrAbs(CPU, tmp0.wl + X.w), A.bl);
}else{
dbg_printf("STA $%04X,X (Target: $%06X, Value: $%04X)", tmp0.wl, addrAbs(CPU, tmp0.wl + X.w), A.w);
}
break;
// Absolute Y
case OP_STA_AY:
tmp0.bl = fetch(CPU);
tmp0.bm = fetch(CPU);
writeAbs(CPU, tmp0.wl + Y.w, A.bl);
if (!MF) writeAbs(CPU, tmp0.wl + Y.w + 1, A.bh);
if (MF){
dbg_printf("STA $%04X,Y (Target: $%06X, Value: $%02X)", tmp0.wl, addrAbs(CPU, tmp0.wl + Y.w), A.bl);
}else{
dbg_printf("STA $%04X,Y (Target: $%06X, Value: $%04X)", tmp0.wl, addrAbs(CPU, tmp0.wl + Y.w), A.w);
}
break;
// Absolute Long
case OP_STA_AL:
tmp0.bl = fetch(CPU);
tmp0.bm = fetch(CPU);
tmp0.bh = fetch(CPU);
tmp0.bx = 0;
writeMem(CPU, tmp0.l, A.bl);
if (!MF) writeMem(CPU, tmp0.l + 1, A.bh);
if (MF){
dbg_printf("STA $%06X (Value: $%02X)", tmp0.l, A.bl);
}else{
dbg_printf("STA $%06X (Value: $%04X)", tmp0.l, A.w);
}
break;
// Absolute Long X
case OP_STA_ALX:
tmp0.bl = fetch(CPU);
tmp0.bm = fetch(CPU);
tmp0.bh = fetch(CPU);
tmp0.bx = 0;
writeMem(CPU, tmp0.l + X.w, A.bl);
if (!MF) writeMem(CPU, tmp0.l + X.w + 1, A.bh);
if (MF){
dbg_printf("STA $%06X,X (Target: $%06X, Value: $%02X)", tmp0.l, tmp0.l + X.w, A.bl);
}else{
dbg_printf("STA $%06X,X (Target: $%06X, Value: $%04X)", tmp0.l, tmp0.l + X.w, A.w);
}
break;
// Direct Page
case OP_STA_DP:
tmp0.bl = fetch(CPU);
writeDP(CPU, tmp0.bl, A.bl);
if (!MF) writeDP(CPU, tmp0.bl + 1, A.bh);
if (MF){
dbg_printf("STA $%02X (Target: $%06X, Value: $%02X)", tmp0.bl, addrDP(CPU, tmp0.bl), A.bl);
}else{
dbg_printf("STA $%02X (Target: $%06X, Value: $%04X)", tmp0.bl, addrDP(CPU, tmp0.bl), A.w);
}
break;
// Direct Page X
case OP_STA_DPX:
tmp0.bl = fetch(CPU);
writeDP(CPU, tmp0.bl + X.w, A.bl);
if (!MF) writeDP(CPU, tmp0.bl + X.w + 1, A.bh);
if (MF){
dbg_printf("STA $%02X,X (Target: $%06X, Value: $%02X)", tmp0.bl, addrDP(CPU, tmp0.bl + X.w), A.bl);
}else{
dbg_printf("STA $%02X,X (Target: $%06X, Value: $%04X)", tmp0.bl, addrDP(CPU, tmp0.bl + X.w), A.w);
}
break;
// Direct Page Indirect
case OP_STA_DPI:
tmp0.bl = fetch(CPU);
tmp1.bl = readDP(CPU, tmp0.bl);
tmp1.bm = readDP(CPU, tmp0.bl + 1);
writeAbs(CPU, tmp1.wl, A.bl);
if (!MF) writeAbs(CPU, tmp1.wl + 1, A.bh);
if (MF){
dbg_printf("STA ($%02X) (Target: $%06X, Value: $%02X)", tmp0.bl, addrAbs(CPU, tmp1.wl), A.bl);
}else{
dbg_printf("STA ($%02X) (Target: $%06X, Value: $%04X)", tmp0.bl, addrAbs(CPU, tmp1.wl), A.w);
}
break;
// Direct Page X Indirect
case OP_STA_DPXI:
tmp0.bl = fetch(CPU);
tmp1.bl = readDP(CPU, tmp0.bl + X.w);
tmp1.bm = readDP(CPU, tmp0.bl + X.w + 1);
writeAbs(CPU, tmp1.wl, A.bl);
if (!MF) writeAbs(CPU, tmp1.wl + 1, A.bh);
if (MF){
dbg_printf("STA ($%02X,X) (Target: $%06X, Value: $%02X)", tmp0.bl, addrAbs(CPU, tmp1.wl), A.bl);
}else{
dbg_printf("STA ($%02X,X) (Target: $%06X, Value: $%04X)", tmp0.bl, addrAbs(CPU, tmp1.wl), A.w);
}
break;
// Direct Page Indirect Y
case OP_STA_DPIY:
tmp0.bl = fetch(CPU);
tmp1.bl = readDP(CPU, tmp0.bl);
tmp1.bm = readDP(CPU, tmp0.bl + 1);
writeAbs(CPU, tmp1.wl + Y.w, A.bl);
if (!MF) writeAbs(CPU, tmp1.wl + Y.w + 1, A.bh);
if (MF){
dbg_printf("STA ($%02X),Y (Target: $%06X, Value: $%02X)", tmp0.bl, addrAbs(CPU, tmp1.wl + Y.w), A.bl);
}else{
dbg_printf("STA ($%02X),Y (Target: $%06X, Value: $%04X)", tmp0.bl, addrAbs(CPU, tmp1.wl + Y.w), A.w);
}
break;
// Direct Page Indirect Long
case OP_STA_DPIL:
tmp0.bl = fetch(CPU);
tmp1.bl = readDP(CPU, tmp0.bl);
tmp1.bm = readDP(CPU, tmp0.bl + 1);
tmp1.bh = readDP(CPU, tmp0.bl + 2);
tmp1.bx = 0;
writeMem(CPU, tmp1.l, A.bl);
if (!MF) writeMem(CPU, tmp1.l + 1, A.bh);
if (MF){
dbg_printf("STA [$%02X] (Target: $%06X, Value: $%02X)", tmp0.bl, tmp1.l, A.bl);
}else{
dbg_printf("STA [$%02X] (Target: $%06X, Value: $%04X)", tmp0.bl, tmp1.l, A.w);
}
break;
// Direct Page Indirect Long Y
case OP_STA_DPILY:
tmp0.bl = fetch(CPU);
tmp1.bl = readDP(CPU, tmp0.bl);
tmp1.bm = readDP(CPU, tmp0.bl + 1);
tmp1.bh = readDP(CPU, tmp0.bl + 2);
tmp1.bx = 0;
writeMem(CPU, tmp1.l + Y.w, A.bl);
if (!MF) writeMem(CPU, tmp1.l + Y.w + 1, A.bh);
if (MF){
dbg_printf("STA [$%02X],Y (Target: $%06X, Value: $%02X)", tmp0.bl, tmp1.l + Y.w, A.bl);
}else{
dbg_printf("STA [$%02X],Y (Target: $%06X, Value: $%04X)", tmp0.bl, tmp1.l + Y.w, A.w);
}
break;
// Stack
case OP_STA_S:
tmp3.bl = EF; // Save the E Flag
setE(false); // Then Clear it
tmp0.bl = fetch(CPU);
writeStack(CPU, tmp0.bl, A.bl);
if (!MF) writeStack(CPU, tmp0.bl + 1, A.bh);
setE(tmp3.bl); // And afterwards restore it again
if (MF){
dbg_printf("STA %u,S (Target: $%06X, Value: $%02X)", tmp0.bl, addrStack(CPU, tmp0.bl), A.bl);
}else{
dbg_printf("STA %u,S (Target: $%06X, Value: $%04X)", tmp0.bl, addrStack(CPU, tmp0.bl), A.w);
}
break;
// Stack Indirect Y
case OP_STA_SIY:
tmp3.bl = EF; // Save the E Flag
tmp0.bl = fetch(CPU);
setE(false); // Then Clear it
tmp1.bl = readStack(CPU, tmp0.bl);
tmp1.bm = readStack(CPU, tmp0.bl + 1);
setE(tmp3.bl); // And afterwards restore it again
writeAbs(CPU, tmp1.wl + Y.w, A.bl);
if (!MF) writeAbs(CPU, tmp1.wl + Y.w + 1, A.bh);
if (MF){
dbg_printf("STA (%u,S),Y (Target: $%06X, Value: $%02X)", tmp0.bl, tmp1.wl + Y.w, A.bl);
}else{
dbg_printf("STA (%u,S),Y (Target: $%06X, Value: $%04X)", tmp0.bl, tmp1.wl + Y.w, A.w);
}
break;
// Load/Store X ---------------------------------------------------------- //
// Immediate
case OP_LDX_IM:
X.bl = fetch(CPU);
if (!XF) X.bh = fetch(CPU);
setNZ(CPU, XF, X.w);
if (XF){
dbg_printf("LDX #$%02X", X.bl);
}else{
dbg_printf("LDX #$%04X", X.w);
}
break;
// Absolute
case OP_LDX_A:
tmp0.bl = fetch(CPU);
tmp0.bm = fetch(CPU);
X.bl = readAbs(CPU, tmp0.wl);
if (!XF) X.bh = readAbs(CPU, tmp0.wl + 1);
setNZ(CPU, XF, X.w);
if (XF){
dbg_printf("LDX $%04X (Target: $%06X, Value: $%02X)", tmp0.wl, addrAbs(CPU, tmp0.wl), X.bl);
}else{
dbg_printf("LDX $%04X (Target: $%06X, Value: $%04X)", tmp0.wl, addrAbs(CPU, tmp0.wl), X.w);
}
break;
// Absolute Y
case OP_LDX_AY:
tmp0.bl = fetch(CPU);
tmp0.bm = fetch(CPU);
X.bl = readAbs(CPU, tmp0.wl + Y.w);
if (!XF) X.bh = readAbs(CPU, tmp0.wl + Y.w + 1);
setNZ(CPU, XF, X.w);
if (XF){
dbg_printf("LDX $%04X,Y (Target: $%06X, Value: $%02X)", tmp0.wl, addrAbs(CPU, tmp0.wl + Y.w), X.bl);
}else{
dbg_printf("LDX $%04X,Y (Target: $%06X, Value: $%04X)", tmp0.wl, addrAbs(CPU, tmp0.wl + Y.w), X.w);
}
break;
// Direct Page
case OP_LDX_DP:
tmp0.bl = fetch(CPU);
X.bl = readDP(CPU, tmp0.bl);
if (!XF) X.bh = readDP(CPU, tmp0.bl + 1);
setNZ(CPU, XF, X.w);
if (XF){
dbg_printf("LDX $%02X (Target: $%06X, Value: $%02X)", tmp0.bl, addrDP(CPU, tmp0.bl), X.bl);
}else{