diff --git a/COMPARATOR_16BIT.v b/COMPARATOR_16BIT.v
new file mode 100644
index 0000000..eb95c2f
--- /dev/null
+++ b/COMPARATOR_16BIT.v
@@ -0,0 +1,32 @@
+/* Generated by Yosys 0.29+11 (git sha1 acfdc5cc4, clang 10.0.0-4ubuntu1 -fPIC -Os) */
+
+module COMPARATOR_16BIT(clk, din, sel, comp_val, pwm_o);
+  wire _0_;
+  wire _1_;
+  wire _2_;
+  wire _3_;
+  wire _4_;
+  wire _5_;
+  wire _6_;
+  reg _7_;
+  input clk;
+  wire clk;
+  input [15:0] comp_val;
+  wire [15:0] comp_val;
+  input [15:0] din;
+  wire [15:0] din;
+  output pwm_o;
+  wire pwm_o;
+  input sel;
+  wire sel;
+  assign _4_ = _3_ ? 1'h1 : 1'h0;
+  assign _5_ = sel ? _4_ : _7_;
+  assign _6_ = _0_ ? _2_ : _5_;
+  always @(posedge clk)
+    _7_ <= _6_;
+  assign _0_ = ~ sel;
+  assign _1_ = din >= comp_val;
+  assign _2_ = _1_ ? 1'h0 : 1'h1;
+  assign _3_ = din <= comp_val;
+  assign pwm_o = _7_;
+endmodule
diff --git a/COUNTER_16BIT.v b/COUNTER_16BIT.v
new file mode 100644
index 0000000..c199fc9
--- /dev/null
+++ b/COUNTER_16BIT.v
@@ -0,0 +1,44 @@
+/* Generated by Yosys 0.29+11 (git sha1 acfdc5cc4, clang 10.0.0-4ubuntu1 -fPIC -Os) */
+
+module COUNTER_16BIT(clk, en, rst, overflow, dout, ndout);
+  wire [31:0] _0_;
+  reg _1_;
+  wire _2_;
+  wire _3_;
+  wire [15:0] _4_;
+  wire [15:0] _5_;
+  reg [15:0] _6_ = 16'h0000;
+  wire _7_;
+  wire _8_;
+  wire _9_;
+  input clk;
+  wire clk;
+  wire [15:0] cnt_reg;
+  output [15:0] dout;
+  wire [15:0] dout;
+  input en;
+  wire en;
+  output [15:0] ndout;
+  wire [15:0] ndout;
+  output overflow;
+  wire overflow;
+  input rst;
+  wire rst;
+  assign _2_ = { 16'h0000, cnt_reg } == 32'd0;
+  assign _3_ = _2_ ? 1'h1 : 1'h0;
+  assign _4_ = ~ cnt_reg;
+  assign _5_ = en ? _0_[15:0] : cnt_reg;
+  always @(posedge clk, posedge rst)
+    if (rst) _6_ <= 16'h0000;
+    else _6_ <= _5_;
+  assign _7_ = ~ rst;
+  assign _8_ = en & _7_;
+  assign _9_ = _8_ ? _3_ : _1_;
+  always @(posedge clk)
+    _1_ <= _9_;
+  assign _0_ = { 16'h0000, cnt_reg } + 32'd1;
+  assign cnt_reg = _6_;
+  assign overflow = _1_;
+  assign dout = cnt_reg;
+  assign ndout = _4_;
+endmodule
diff --git a/FREQCOUNT_CORE_V4.v b/FREQCOUNT_CORE_V4.v
new file mode 100644
index 0000000..2c86967
--- /dev/null
+++ b/FREQCOUNT_CORE_V4.v
@@ -0,0 +1,122 @@
+/* Generated by Yosys 0.29+11 (git sha1 acfdc5cc4, clang 10.0.0-4ubuntu1 -fPIC -Os) */
+
+module FREQCOUNT_CORE_V4(clk, rst, en, cnt_clk, int_ack, interval_time, \int , freq);
+  wire _00_;
+  wire _01_;
+  wire [31:0] _02_;
+  wire _03_;
+  wire _04_;
+  wire _05_;
+  wire [3:0] _06_;
+  reg [3:0] _07_;
+  wire _08_;
+  reg _09_;
+  wire _10_;
+  wire _11_;
+  wire _12_;
+  wire _13_;
+  reg _14_;
+  wire [26:0] _15_;
+  reg [26:0] _16_ = 27'h0000000;
+  wire _17_;
+  reg _18_;
+  wire [31:0] _19_;
+  reg [31:0] _20_;
+  wire _21_;
+  wire [31:0] _22_;
+  wire _23_;
+  wire [31:0] _24_;
+  reg [31:0] _25_;
+  wire [26:0] _26_;
+  wire _27_;
+  wire _28_;
+  wire [26:0] _29_;
+  wire _30_;
+  wire _31_;
+  input clk;
+  wire clk;
+  input cnt_clk;
+  wire cnt_clk;
+  wire cnt_en;
+  wire [31:0] cnt_reg;
+  wire cnt_rst;
+  input en;
+  wire en;
+  wire [3:0] flipflop_delay;
+  output [31:0] freq;
+  wire [31:0] freq;
+  output \int ;
+  wire \int ;
+  input int_ack;
+  wire int_ack;
+  wire interrupt;
+  wire [26:0] interval;
+  input [31:0] interval_time;
+  wire [31:0] interval_time;
+  input rst;
+  wire rst;
+  assign _22_ = { 5'h00, interval } + 32'd1;
+  assign _26_ = _11_ ? interval : _22_[26:0];
+  assign _27_ = _11_ ? 1'h1 : interrupt;
+  assign _28_ = int_ack ? 1'h1 : 1'h0;
+  assign _29_ = int_ack ? 27'h0000000 : _26_;
+  assign _30_ = int_ack ? 1'h0 : _27_;
+  assign _31_ = cnt_rst | rst;
+  assign _01_ = en & cnt_en;
+  assign _02_ = cnt_reg + 32'd1;
+  assign _00_ = en & _11_;
+  assign _03_ = flipflop_delay[3:1] == 3'h0;
+  assign _04_ = flipflop_delay[3:1] == 3'h7;
+  function [0:0] \58 ;
+    input [0:0] a;
+    input [1:0] b;
+    input [1:0] s;
+    (* parallel_case *)
+    casez (s)
+      2'b?1:
+        \58  = b[0:0];
+      2'b1?:
+        \58  = b[1:1];
+      default:
+        \58  = a;
+    endcase
+  endfunction
+  assign _05_ = \58 (cnt_en, 2'h1, { _04_, _03_ });
+  assign _06_ = en ? { flipflop_delay[2:0], interrupt } : flipflop_delay;
+  always @(posedge cnt_clk)
+    _07_ <= _06_;
+  assign _08_ = en ? _05_ : cnt_en;
+  always @(posedge cnt_clk)
+    _09_ <= _08_;
+  assign _10_ = ~ rst;
+  assign _12_ = en & _10_;
+  assign _13_ = _12_ ? _28_ : cnt_rst;
+  always @(posedge clk)
+    _14_ <= _13_;
+  assign _11_ = { 5'h00, interval } == interval_time;
+  assign _15_ = en ? _29_ : interval;
+  always @(posedge clk, posedge rst)
+    if (rst) _16_ <= 27'h0000000;
+    else _16_ <= _15_;
+  assign _17_ = en ? _30_ : interrupt;
+  always @(posedge clk, posedge rst)
+    if (rst) _18_ <= 1'h0;
+    else _18_ <= _17_;
+  assign _19_ = _01_ ? _02_ : cnt_reg;
+  always @(posedge cnt_clk, posedge _31_)
+    if (_31_) _20_ <= 32'd0;
+    else _20_ <= _19_;
+  assign _21_ = ~ rst;
+  assign _23_ = _00_ & _21_;
+  assign _24_ = _23_ ? cnt_reg : _25_;
+  always @(posedge clk)
+    _25_ <= _24_;
+  assign flipflop_delay = _07_;
+  assign cnt_en = _09_;
+  assign cnt_rst = _14_;
+  assign interval = _16_;
+  assign interrupt = _18_;
+  assign cnt_reg = _20_;
+  assign \int  = interrupt;
+  assign freq = _25_;
+endmodule
diff --git a/PWM_CORE_LAT_V17.v b/PWM_CORE_LAT_V17.v
new file mode 100644
index 0000000..ccf1c03
--- /dev/null
+++ b/PWM_CORE_LAT_V17.v
@@ -0,0 +1,73 @@
+/* Generated by Yosys 0.29+11 (git sha1 acfdc5cc4, clang 10.0.0-4ubuntu1 -fPIC -Os) */
+
+module PWM_CORE_LAT_V17(clk, rst, en, pwm_reg_a, pwm_reg_b, pwm_out_1, pwm_out_2);
+  wire [15:0] _0_;
+  wire [15:0] _1_;
+  wire _2_;
+  wire [15:0] _3_;
+  wire [15:0] _4_;
+  wire _5_;
+  wire _6_;
+  input clk;
+  wire clk;
+  wire counter_overflow;
+  input en;
+  wire en;
+  wire [15:0] n_counter_val;
+  wire [15:0] p_counter_val;
+  output pwm_out_1;
+  wire pwm_out_1;
+  output pwm_out_2;
+  wire pwm_out_2;
+  input [15:0] pwm_reg_a;
+  wire [15:0] pwm_reg_a;
+  input [15:0] pwm_reg_b;
+  wire [15:0] pwm_reg_b;
+  wire [15:0] reg_a_out;
+  wire [15:0] reg_b_out;
+  input rst;
+  wire rst;
+  COUNTER_16BIT counter (
+    .clk(clk),
+    .dout(_3_),
+    .en(en),
+    .ndout(_4_),
+    .overflow(_2_),
+    .rst(rst)
+  );
+  COMPARATOR_16BIT n_comparator (
+    .clk(clk),
+    .comp_val(reg_b_out),
+    .din(n_counter_val),
+    .pwm_o(_6_),
+    .sel(1'h1)
+  );
+  COMPARATOR_16BIT p_comparator (
+    .clk(clk),
+    .comp_val(reg_a_out),
+    .din(p_counter_val),
+    .pwm_o(_5_),
+    .sel(1'h0)
+  );
+  REGISTER_16BIT reg_a (
+    .clk(clk),
+    .din(pwm_reg_a),
+    .dout(_0_),
+    .en(counter_overflow),
+    .rst(rst)
+  );
+  REGISTER_16BIT reg_b (
+    .clk(clk),
+    .din(pwm_reg_b),
+    .dout(_1_),
+    .en(counter_overflow),
+    .rst(rst)
+  );
+  assign n_counter_val = _4_;
+  assign p_counter_val = _3_;
+  assign reg_a_out = _0_;
+  assign reg_b_out = _1_;
+  assign counter_overflow = _2_;
+  assign pwm_out_1 = _5_;
+  assign pwm_out_2 = _6_;
+endmodule
diff --git a/REGISTER_16BIT.v b/REGISTER_16BIT.v
new file mode 100644
index 0000000..548a413
--- /dev/null
+++ b/REGISTER_16BIT.v
@@ -0,0 +1,23 @@
+/* Generated by Yosys 0.29+11 (git sha1 acfdc5cc4, clang 10.0.0-4ubuntu1 -fPIC -Os) */
+
+module REGISTER_16BIT(clk, rst, en, din, dout);
+  wire [15:0] _0_;
+  reg [15:0] _1_;
+  input clk;
+  wire clk;
+  input [15:0] din;
+  wire [15:0] din;
+  output [15:0] dout;
+  wire [15:0] dout;
+  input en;
+  wire en;
+  wire [15:0] \reg ;
+  input rst;
+  wire rst;
+  always @(posedge clk, posedge rst)
+    if (rst) _1_ <= 16'h0000;
+    else _1_ <= _0_;
+  assign _0_ = en ? din : \reg ;
+  assign \reg  = _1_;
+  assign dout = \reg ;
+endmodule
diff --git a/SPI_SLAVE_TOPDESIGN.v b/SPI_SLAVE_TOPDESIGN.v
new file mode 100644
index 0000000..a018990
--- /dev/null
+++ b/SPI_SLAVE_TOPDESIGN.v
@@ -0,0 +1,775 @@
+/* Generated by Yosys 0.29+11 (git sha1 acfdc5cc4, clang 10.0.0-4ubuntu1 -fPIC -Os) */
+
+module bionic_eye_spi_slave(CLK, SCK, CS, MOSI, FREQ_IN, MISO, PWM_OUT_1, PWM_OUT_2);
+  wire _000_;
+  wire _001_;
+  wire _002_;
+  wire _003_;
+  wire _004_;
+  wire [31:0] _005_;
+  wire [1:0] _006_;
+  wire [7:0] _007_;
+  wire [7:0] _008_;
+  wire _009_;
+  wire _010_;
+  wire _011_;
+  wire _012_;
+  wire _013_;
+  wire _014_;
+  wire _015_;
+  wire [31:0] _016_;
+  wire [1:0] _017_;
+  wire [7:0] _018_;
+  wire [7:0] _019_;
+  wire _020_;
+  wire _021_;
+  wire _022_;
+  wire [31:0] _023_;
+  wire _024_;
+  wire _025_;
+  wire _026_;
+  wire [31:0] _027_;
+  wire _028_;
+  wire [7:0] _029_;
+  wire [7:0] _030_;
+  wire _031_;
+  wire _032_;
+  wire _033_;
+  wire [2:0] _034_;
+  wire _035_;
+  wire _036_;
+  wire _037_;
+  wire _038_;
+  wire _039_;
+  wire _040_;
+  wire _041_;
+  wire _042_;
+  wire _043_;
+  wire [2:0] _044_;
+  wire _045_;
+  wire _046_;
+  wire [2:0] _047_;
+  wire _048_;
+  reg _049_ = 1'h0;
+  reg _050_ = 1'h0;
+  reg _051_ = 1'h0;
+  reg _052_ = 1'h0;
+  reg _053_ = 1'h0;
+  reg _054_ = 1'h0;
+  reg [2:0] _055_ = 3'h0;
+  wire _056_;
+  wire [1:0] _057_;
+  reg [1:0] _058_ = 2'h0;
+  reg [7:0] _059_;
+  wire [7:0] _060_;
+  reg [7:0] _061_;
+  reg [7:0] _062_ = 8'h00;
+  wire _063_;
+  reg _064_ = 1'h0;
+  wire _065_;
+  reg _066_ = 1'h0;
+  wire _067_;
+  wire _068_;
+  reg _069_ = 1'h0;
+  wire _070_;
+  reg _071_ = 1'h0;
+  wire _072_;
+  reg _073_ = 1'h0;
+  wire [15:0] _074_;
+  reg [15:0] _075_ = 16'h0000;
+  reg _076_ = 1'h0;
+  reg [2:0] _077_ = 3'h0;
+  wire _078_;
+  reg _079_ = 1'h0;
+  wire [31:0] _080_;
+  reg [31:0] _081_ = 32'd0;
+  wire _082_;
+  wire _083_;
+  wire _084_;
+  wire [2:0] _085_;
+  wire [7:0] _086_;
+  wire _087_;
+  wire _088_;
+  wire _089_;
+  wire _090_;
+  wire _091_;
+  wire _092_;
+  wire _093_;
+  wire [7:0] _094_;
+  wire _095_;
+  wire [7:0] _096_;
+  wire [31:0] _097_;
+  wire _098_;
+  wire _099_;
+  wire _100_;
+  wire [7:0] _101_;
+  wire _102_;
+  wire _103_;
+  wire [31:0] _104_;
+  wire _105_;
+  wire [31:0] _106_;
+  wire _107_;
+  wire _108_;
+  wire _109_;
+  wire _110_;
+  wire _111_;
+  wire [7:0] _112_;
+  wire [7:0] _113_;
+  wire [7:0] _114_;
+  wire [7:0] _115_;
+  wire [31:0] _116_;
+  wire _117_;
+  wire _118_;
+  wire _119_;
+  wire _120_;
+  wire [1:0] _121_;
+  wire _122_;
+  wire _123_;
+  wire _124_;
+  wire _125_;
+  wire _126_;
+  wire _127_;
+  wire _128_;
+  wire _129_;
+  wire [1:0] _130_;
+  wire [7:0] _131_;
+  wire _132_;
+  wire _133_;
+  wire [1:0] _134_;
+  wire [7:0] _135_;
+  wire _136_;
+  wire _137_;
+  wire [1:0] _138_;
+  wire [2:0] _139_;
+  wire [7:0] _140_;
+  wire _141_;
+  wire _142_;
+  wire _143_;
+  wire _144_;
+  wire _145_;
+  wire [1:0] _146_;
+  wire [7:0] _147_;
+  wire _148_;
+  wire _149_;
+  wire _150_;
+  wire _151_;
+  wire _152_;
+  wire _153_;
+  wire _154_;
+  wire [31:0] _155_;
+  wire [1:0] _156_;
+  wire [7:0] _157_;
+  wire _158_;
+  wire _159_;
+  wire _160_;
+  wire _161_;
+  wire _162_;
+  wire _163_;
+  wire _164_;
+  wire [31:0] _165_;
+  wire [1:0] _166_;
+  wire [7:0] _167_;
+  wire [7:0] _168_;
+  wire _169_;
+  wire _170_;
+  wire _171_;
+  input CLK;
+  wire CLK;
+  input CS;
+  wire CS;
+  input FREQ_IN;
+  wire FREQ_IN;
+  output MISO;
+  wire MISO;
+  input MOSI;
+  wire MOSI;
+  output PWM_OUT_1;
+  wire PWM_OUT_1;
+  output PWM_OUT_2;
+  wire PWM_OUT_2;
+  input SCK;
+  wire SCK;
+  wire cs_latched;
+  wire cs_old;
+  wire [31:0] freq_cnt;
+  wire freq_gen_int;
+  wire [2:0] int_ack_pulse;
+  wire interrupt;
+  wire interrupt_ack;
+  wire [31:0] interval_time;
+  wire [7:0] miso_reg;
+  wire mosi_latched;
+  wire [7:0] mosi_reg;
+  wire [2:0] msg_bit_index;
+  wire [1:0] msg_cnt;
+  wire [15:0] pwm_reg;
+  wire r_freq_cmd;
+  wire r_pwm_cmd;
+  wire sck_latched;
+  wire sck_old;
+  wire spi_done;
+  wire [7:0] status_reg;
+  wire w_freq_cmd;
+  wire w_pwm_cmd;
+  wire w_status_cmd;
+  function [0:0] \101 ;
+    input [0:0] a;
+    input [2:0] b;
+    input [2:0] s;
+    (* parallel_case *)
+    casez (s)
+      3'b??1:
+        \101  = b[0:0];
+      3'b?1?:
+        \101  = b[1:1];
+      3'b1??:
+        \101  = b[2:2];
+      default:
+        \101  = a;
+    endcase
+  endfunction
+  assign _103_ = \101 (freq_gen_int, { 1'h1, freq_gen_int, freq_gen_int }, { _100_, _099_, _098_ });
+  assign _104_ = { 30'h00000000, msg_cnt } - 32'd1;
+  assign _105_ = msg_cnt == 2'h3;
+  assign _107_ = msg_cnt == 2'h2;
+  assign _108_ = msg_cnt == 2'h1;
+  assign _109_ = msg_cnt == 2'h0;
+  function [0:0] \116 ;
+    input [0:0] a;
+    input [3:0] b;
+    input [3:0] s;
+    (* parallel_case *)
+    casez (s)
+      4'b???1:
+        \116  = b[0:0];
+      4'b??1?:
+        \116  = b[1:1];
+      4'b?1??:
+        \116  = b[2:2];
+      4'b1???:
+        \116  = b[3:3];
+      default:
+        \116  = a;
+    endcase
+  endfunction
+  assign _110_ = \116 (w_freq_cmd, { 1'h0, w_freq_cmd, w_freq_cmd, w_freq_cmd }, { _109_, _108_, _107_, _105_ });
+  function [0:0] \118 ;
+    input [0:0] a;
+    input [3:0] b;
+    input [3:0] s;
+    (* parallel_case *)
+    casez (s)
+      4'b???1:
+        \118  = b[0:0];
+      4'b??1?:
+        \118  = b[1:1];
+      4'b?1??:
+        \118  = b[2:2];
+      4'b1???:
+        \118  = b[3:3];
+      default:
+        \118  = a;
+    endcase
+  endfunction
+  assign _111_ = \118 (freq_gen_int, { 1'h1, freq_gen_int, freq_gen_int, freq_gen_int }, { _109_, _108_, _107_, _105_ });
+  function [7:0] \120 ;
+    input [7:0] a;
+    input [31:0] b;
+    input [3:0] s;
+    (* parallel_case *)
+    casez (s)
+      4'b???1:
+        \120  = b[7:0];
+      4'b??1?:
+        \120  = b[15:8];
+      4'b?1??:
+        \120  = b[23:16];
+      4'b1???:
+        \120  = b[31:24];
+      default:
+        \120  = a;
+    endcase
+  endfunction
+  assign _112_ = \120 (interval_time[7:0], { mosi_reg, interval_time[7:0], interval_time[7:0], interval_time[7:0] }, { _109_, _108_, _107_, _105_ });
+  function [7:0] \122 ;
+    input [7:0] a;
+    input [31:0] b;
+    input [3:0] s;
+    (* parallel_case *)
+    casez (s)
+      4'b???1:
+        \122  = b[7:0];
+      4'b??1?:
+        \122  = b[15:8];
+      4'b?1??:
+        \122  = b[23:16];
+      4'b1???:
+        \122  = b[31:24];
+      default:
+        \122  = a;
+    endcase
+  endfunction
+  assign _113_ = \122 (interval_time[15:8], { interval_time[15:8], mosi_reg, interval_time[15:8], interval_time[15:8] }, { _109_, _108_, _107_, _105_ });
+  function [7:0] \124 ;
+    input [7:0] a;
+    input [31:0] b;
+    input [3:0] s;
+    (* parallel_case *)
+    casez (s)
+      4'b???1:
+        \124  = b[7:0];
+      4'b??1?:
+        \124  = b[15:8];
+      4'b?1??:
+        \124  = b[23:16];
+      4'b1???:
+        \124  = b[31:24];
+      default:
+        \124  = a;
+    endcase
+  endfunction
+  assign _114_ = \124 (interval_time[23:16], { interval_time[23:16], interval_time[23:16], mosi_reg, interval_time[23:16] }, { _109_, _108_, _107_, _105_ });
+  function [7:0] \126 ;
+    input [7:0] a;
+    input [31:0] b;
+    input [3:0] s;
+    (* parallel_case *)
+    casez (s)
+      4'b???1:
+        \126  = b[7:0];
+      4'b??1?:
+        \126  = b[15:8];
+      4'b?1??:
+        \126  = b[23:16];
+      4'b1???:
+        \126  = b[31:24];
+      default:
+        \126  = a;
+    endcase
+  endfunction
+  assign _115_ = \126 (interval_time[31:24], { interval_time[31:24], interval_time[31:24], interval_time[31:24], mosi_reg }, { _109_, _108_, _107_, _105_ });
+  assign _116_ = { 30'h00000000, msg_cnt } - 32'd1;
+  assign _118_ = mosi_reg[6:0] == 7'h01;
+  assign _119_ = mosi_reg[6:0] == 7'h02;
+  assign _120_ = mosi_reg[6:0] == 7'h03;
+  function [1:0] \142 ;
+    input [1:0] a;
+    input [5:0] b;
+    input [2:0] s;
+    (* parallel_case *)
+    casez (s)
+      3'b??1:
+        \142  = b[1:0];
+      3'b?1?:
+        \142  = b[3:2];
+      3'b1??:
+        \142  = b[5:4];
+      default:
+        \142  = a;
+    endcase
+  endfunction
+  assign _121_ = \142 (msg_cnt, { 4'hd, msg_cnt }, { _120_, _119_, _118_ });
+  function [0:0] \144 ;
+    input [0:0] a;
+    input [2:0] b;
+    input [2:0] s;
+    (* parallel_case *)
+    casez (s)
+      3'b??1:
+        \144  = b[0:0];
+      3'b?1?:
+        \144  = b[1:1];
+      3'b1??:
+        \144  = b[2:2];
+      default:
+        \144  = a;
+    endcase
+  endfunction
+  assign _122_ = \144 (w_status_cmd, { w_status_cmd, w_status_cmd, 1'h1 }, { _120_, _119_, _118_ });
+  function [0:0] \146 ;
+    input [0:0] a;
+    input [2:0] b;
+    input [2:0] s;
+    (* parallel_case *)
+    casez (s)
+      3'b??1:
+        \146  = b[0:0];
+      3'b?1?:
+        \146  = b[1:1];
+      3'b1??:
+        \146  = b[2:2];
+      default:
+        \146  = a;
+    endcase
+  endfunction
+  assign _123_ = \146 (w_pwm_cmd, { w_pwm_cmd, 1'h1, w_pwm_cmd }, { _120_, _119_, _118_ });
+  function [0:0] \148 ;
+    input [0:0] a;
+    input [2:0] b;
+    input [2:0] s;
+    (* parallel_case *)
+    casez (s)
+      3'b??1:
+        \148  = b[0:0];
+      3'b?1?:
+        \148  = b[1:1];
+      3'b1??:
+        \148  = b[2:2];
+      default:
+        \148  = a;
+    endcase
+  endfunction
+  assign _124_ = \148 (w_freq_cmd, { 1'h1, w_freq_cmd, w_freq_cmd }, { _120_, _119_, _118_ });
+  assign _125_ = ~ mosi_reg[7];
+  assign _126_ = mosi_reg[6:0] == 7'h01;
+  assign _127_ = mosi_reg[6:0] == 7'h02;
+  assign _129_ = mosi_reg[6:0] == 7'h03;
+  function [1:0] \162 ;
+    input [1:0] a;
+    input [5:0] b;
+    input [2:0] s;
+    (* parallel_case *)
+    casez (s)
+      3'b??1:
+        \162  = b[1:0];
+      3'b?1?:
+        \162  = b[3:2];
+      3'b1??:
+        \162  = b[5:4];
+      default:
+        \162  = a;
+    endcase
+  endfunction
+  assign _130_ = \162 (msg_cnt, { 2'h2, msg_cnt, msg_cnt }, { _129_, _127_, _126_ });
+  function [7:0] \163 ;
+    input [7:0] a;
+    input [23:0] b;
+    input [2:0] s;
+    (* parallel_case *)
+    casez (s)
+      3'b??1:
+        \163  = b[7:0];
+      3'b?1?:
+        \163  = b[15:8];
+      3'b1??:
+        \163  = b[23:16];
+      default:
+        \163  = a;
+    endcase
+  endfunction
+  assign _131_ = \163 (_086_, { freq_cnt[31:24], pwm_reg[15:8], status_reg }, { _129_, _127_, _126_ });
+  function [0:0] \165 ;
+    input [0:0] a;
+    input [2:0] b;
+    input [2:0] s;
+    (* parallel_case *)
+    casez (s)
+      3'b??1:
+        \165  = b[0:0];
+      3'b?1?:
+        \165  = b[1:1];
+      3'b1??:
+        \165  = b[2:2];
+      default:
+        \165  = a;
+    endcase
+  endfunction
+  assign _132_ = \165 (r_pwm_cmd, { r_pwm_cmd, 1'h1, r_pwm_cmd }, { _129_, _127_, _126_ });
+  function [0:0] \167 ;
+    input [0:0] a;
+    input [2:0] b;
+    input [2:0] s;
+    (* parallel_case *)
+    casez (s)
+      3'b??1:
+        \167  = b[0:0];
+      3'b?1?:
+        \167  = b[1:1];
+      3'b1??:
+        \167  = b[2:2];
+      default:
+        \167  = a;
+    endcase
+  endfunction
+  assign _133_ = \167 (r_freq_cmd, { 1'h1, r_freq_cmd, r_freq_cmd }, { _129_, _127_, _126_ });
+  assign _134_ = _125_ ? _130_ : msg_cnt;
+  assign _135_ = _125_ ? _131_ : _086_;
+  assign _136_ = _125_ ? _132_ : r_pwm_cmd;
+  assign _137_ = _125_ ? _133_ : r_freq_cmd;
+  assign _138_ = mosi_reg[7] ? _121_ : _134_;
+  assign _140_ = mosi_reg[7] ? _086_ : _135_;
+  assign _141_ = mosi_reg[7] ? _122_ : w_status_cmd;
+  assign _142_ = mosi_reg[7] ? _123_ : w_pwm_cmd;
+  assign _143_ = mosi_reg[7] ? r_pwm_cmd : _136_;
+  assign _144_ = mosi_reg[7] ? r_freq_cmd : _137_;
+  assign _145_ = mosi_reg[7] ? _124_ : w_freq_cmd;
+  assign _146_ = w_freq_cmd ? _116_[1:0] : _138_;
+  assign _147_ = w_freq_cmd ? _086_ : _140_;
+  assign _148_ = w_freq_cmd ? w_status_cmd : _141_;
+  assign _149_ = w_freq_cmd ? w_pwm_cmd : _142_;
+  assign _151_ = w_freq_cmd ? r_pwm_cmd : _143_;
+  assign _152_ = w_freq_cmd ? r_freq_cmd : _144_;
+  assign _153_ = w_freq_cmd ? _110_ : _145_;
+  assign _154_ = w_freq_cmd ? _111_ : freq_gen_int;
+  assign _155_ = w_freq_cmd ? { _115_, _114_, _113_, _112_ } : interval_time;
+  assign _156_ = r_freq_cmd ? _104_[1:0] : _146_;
+  assign _157_ = r_freq_cmd ? _101_ : _147_;
+  assign _158_ = r_freq_cmd ? w_status_cmd : _148_;
+  assign _159_ = r_freq_cmd ? w_pwm_cmd : _149_;
+  assign _160_ = r_freq_cmd ? r_pwm_cmd : _151_;
+  assign _162_ = r_freq_cmd ? _102_ : _152_;
+  assign _163_ = r_freq_cmd ? w_freq_cmd : _153_;
+  assign _164_ = r_freq_cmd ? _103_ : _154_;
+  assign _165_ = r_freq_cmd ? interval_time : _155_;
+  assign _166_ = w_status_cmd ? msg_cnt : _156_;
+  assign _167_ = w_status_cmd ? _086_ : _157_;
+  assign _168_ = w_status_cmd ? mosi_reg : { status_reg[7:5], interrupt, status_reg[3:0] };
+  assign _169_ = w_status_cmd ? 1'h0 : _158_;
+  assign _170_ = w_status_cmd ? w_pwm_cmd : _159_;
+  assign _171_ = w_status_cmd ? r_pwm_cmd : _160_;
+  assign _002_ = w_status_cmd ? r_freq_cmd : _162_;
+  assign _003_ = w_status_cmd ? w_freq_cmd : _163_;
+  assign _004_ = w_status_cmd ? freq_gen_int : _164_;
+  assign _005_ = w_status_cmd ? interval_time : _165_;
+  assign _006_ = r_pwm_cmd ? msg_cnt : _166_;
+  assign _007_ = r_pwm_cmd ? pwm_reg[7:0] : _167_;
+  assign _008_ = r_pwm_cmd ? { status_reg[7:5], interrupt, status_reg[3:0] } : _168_;
+  assign _009_ = r_pwm_cmd ? w_status_cmd : _169_;
+  assign _010_ = r_pwm_cmd ? w_pwm_cmd : _170_;
+  assign _011_ = r_pwm_cmd ? 1'h0 : _171_;
+  assign _013_ = r_pwm_cmd ? r_freq_cmd : _002_;
+  assign _014_ = r_pwm_cmd ? w_freq_cmd : _003_;
+  assign _015_ = r_pwm_cmd ? freq_gen_int : _004_;
+  assign _016_ = r_pwm_cmd ? interval_time : _005_;
+  assign _017_ = w_pwm_cmd ? _097_[1:0] : _006_;
+  assign _018_ = w_pwm_cmd ? _086_ : _007_;
+  assign _019_ = w_pwm_cmd ? { status_reg[7:5], interrupt, status_reg[3:0] } : _008_;
+  assign _020_ = w_pwm_cmd ? w_status_cmd : _009_;
+  assign _021_ = w_pwm_cmd ? _093_ : _010_;
+  assign _022_ = w_pwm_cmd ? r_pwm_cmd : _011_;
+  assign _024_ = w_pwm_cmd ? r_freq_cmd : _013_;
+  assign _025_ = w_pwm_cmd ? w_freq_cmd : _014_;
+  assign _026_ = w_pwm_cmd ? freq_gen_int : _015_;
+  assign _027_ = w_pwm_cmd ? interval_time : _016_;
+  assign _028_ = spi_done ? 1'h0 : _087_;
+  assign _029_ = spi_done ? _018_ : _086_;
+  assign _030_ = spi_done ? _019_ : { status_reg[7:5], interrupt, status_reg[3:0] };
+  assign _031_ = spi_done & w_pwm_cmd;
+  assign _032_ = spi_done ? _026_ : freq_gen_int;
+  assign _033_ = ~ status_reg[3];
+  assign _035_ = _033_ & freq_gen_int;
+  assign _036_ = int_ack_pulse == 3'h7;
+  assign _037_ = _036_ ? 1'h0 : 1'h1;
+  assign _038_ = _048_ ? 1'h0 : _032_;
+  assign _039_ = int_ack_pulse == 3'h7;
+  assign _040_ = int_ack_pulse == 3'h0;
+  assign _041_ = _040_ ? 1'h0 : interrupt_ack;
+  assign _042_ = _039_ ? 1'h1 : _041_;
+  assign _043_ = status_reg[3] ? _042_ : interrupt_ack;
+  assign _044_ = status_reg[3] ? { int_ack_pulse[1:0], interrupt } : int_ack_pulse;
+  assign _046_ = _035_ ? _037_ : _043_;
+  assign _047_ = _035_ ? { int_ack_pulse[1:0], interrupt_ack } : _044_;
+  assign _048_ = _035_ & _036_;
+  always @(posedge CLK)
+    _049_ <= SCK;
+  always @(posedge CLK)
+    _050_ <= sck_latched;
+  always @(posedge CLK)
+    _051_ <= CS;
+  always @(posedge CLK)
+    _052_ <= cs_latched;
+  always @(posedge CLK)
+    _053_ <= MOSI;
+  always @(posedge CLK)
+    _054_ <= _028_;
+  always @(posedge CLK)
+    _055_ <= _085_;
+  assign _057_ = spi_done ? _017_ : msg_cnt;
+  always @(posedge CLK)
+    _058_ <= _057_;
+  always @(posedge CLK)
+    _059_ <= _029_;
+  assign _060_ = _090_ ? { mosi_reg[6:0], mosi_latched } : mosi_reg;
+  always @(posedge CLK)
+    _061_ <= _060_;
+  always @(posedge CLK)
+    _062_ <= _030_;
+  assign _063_ = spi_done ? _020_ : w_status_cmd;
+  always @(posedge CLK)
+    _064_ <= _063_;
+  assign _065_ = spi_done ? _021_ : w_pwm_cmd;
+  always @(posedge CLK)
+    _066_ <= _065_;
+  assign _068_ = spi_done ? _022_ : r_pwm_cmd;
+  always @(posedge CLK)
+    _069_ <= _068_;
+  assign _070_ = spi_done ? _024_ : r_freq_cmd;
+  always @(posedge CLK)
+    _071_ <= _070_;
+  assign _072_ = spi_done ? _025_ : w_freq_cmd;
+  always @(posedge CLK)
+    _073_ <= _072_;
+  assign _074_ = _031_ ? { _096_, _094_ } : pwm_reg;
+  always @(posedge CLK)
+    _075_ <= _074_;
+  always @(posedge CLK)
+    _076_ <= _046_;
+  always @(posedge CLK)
+    _077_ <= _047_;
+  always @(posedge CLK)
+    _079_ <= _038_;
+  assign _080_ = spi_done ? _027_ : interval_time;
+  always @(posedge CLK)
+    _081_ <= _080_;
+  assign _117_ = ~ cs_latched;
+  assign _128_ = _117_ & cs_old;
+  assign _139_ = _128_ ? 3'h7 : msg_bit_index;
+  assign _150_ = ~ cs_latched;
+  assign _161_ = ~ sck_old;
+  assign _001_ = sck_latched & _161_;
+  assign _012_ = { 29'h00000000, msg_bit_index } == 32'd0;
+  assign _023_ = { 29'h00000000, msg_bit_index } - 32'd1;
+  assign _034_ = _012_ ? 3'h7 : _023_[2:0];
+  assign _045_ = ~ sck_latched;
+  assign _056_ = _045_ & sck_old;
+  assign _067_ = { 29'h00000000, msg_bit_index } == 32'd7;
+  assign _078_ = _082_ ? 1'h1 : spi_done;
+  assign _082_ = _056_ & _067_;
+  assign _083_ = _001_ ? spi_done : _078_;
+  assign _085_ = _088_ ? _034_ : _139_;
+  assign _086_ = _089_ ? { miso_reg[6:0], 1'h0 } : miso_reg;
+  assign _087_ = _150_ ? _083_ : spi_done;
+  assign _088_ = _150_ & _001_;
+  assign _089_ = _150_ & _001_;
+  assign _090_ = _150_ & _001_;
+  assign _091_ = msg_cnt == 2'h1;
+  assign _092_ = msg_cnt == 2'h0;
+  function [0:0] \77 ;
+    input [0:0] a;
+    input [1:0] b;
+    input [1:0] s;
+    (* parallel_case *)
+    casez (s)
+      2'b?1:
+        \77  = b[0:0];
+      2'b1?:
+        \77  = b[1:1];
+      default:
+        \77  = a;
+    endcase
+  endfunction
+  assign _093_ = \77 (w_pwm_cmd, { 1'h0, w_pwm_cmd }, { _092_, _091_ });
+  function [7:0] \79 ;
+    input [7:0] a;
+    input [15:0] b;
+    input [1:0] s;
+    (* parallel_case *)
+    casez (s)
+      2'b?1:
+        \79  = b[7:0];
+      2'b1?:
+        \79  = b[15:8];
+      default:
+        \79  = a;
+    endcase
+  endfunction
+  assign _094_ = \79 (pwm_reg[7:0], { mosi_reg, pwm_reg[7:0] }, { _092_, _091_ });
+  function [7:0] \81 ;
+    input [7:0] a;
+    input [15:0] b;
+    input [1:0] s;
+    (* parallel_case *)
+    casez (s)
+      2'b?1:
+        \81  = b[7:0];
+      2'b1?:
+        \81  = b[15:8];
+      default:
+        \81  = a;
+    endcase
+  endfunction
+  assign _096_ = \81 (pwm_reg[15:8], { pwm_reg[15:8], mosi_reg }, { _092_, _091_ });
+  assign _097_ = { 30'h00000000, msg_cnt } - 32'd1;
+  assign _098_ = msg_cnt == 2'h2;
+  assign _099_ = msg_cnt == 2'h1;
+  assign _100_ = msg_cnt == 2'h0;
+  function [7:0] \97 ;
+    input [7:0] a;
+    input [23:0] b;
+    input [2:0] s;
+    (* parallel_case *)
+    casez (s)
+      3'b??1:
+        \97  = b[7:0];
+      3'b?1?:
+        \97  = b[15:8];
+      3'b1??:
+        \97  = b[23:16];
+      default:
+        \97  = a;
+    endcase
+  endfunction
+  assign _101_ = \97 (_086_, { freq_cnt[7:0], freq_cnt[15:8], freq_cnt[23:16] }, { _100_, _099_, _098_ });
+  function [0:0] \99 ;
+    input [0:0] a;
+    input [2:0] b;
+    input [2:0] s;
+    (* parallel_case *)
+    casez (s)
+      3'b??1:
+        \99  = b[0:0];
+      3'b?1?:
+        \99  = b[1:1];
+      3'b1??:
+        \99  = b[2:2];
+      default:
+        \99  = a;
+    endcase
+  endfunction
+  assign _102_ = \99 (r_freq_cmd, { 1'h0, r_freq_cmd, r_freq_cmd }, { _100_, _099_, _098_ });
+  FREQCOUNT_CORE_V4 freq_core (
+    .clk(CLK),
+    .cnt_clk(FREQ_IN),
+    .en(status_reg[5]),
+    .freq(_106_),
+    .\int (_095_),
+    .int_ack(interrupt_ack),
+    .interval_time(interval_time),
+    .rst(status_reg[7])
+  );
+  PWM_CORE_LAT_V17 pwm_core (
+    .clk(CLK),
+    .en(status_reg[6]),
+    .pwm_out_1(_000_),
+    .pwm_out_2(_084_),
+    .pwm_reg_a(pwm_reg),
+    .pwm_reg_b(pwm_reg),
+    .rst(status_reg[7])
+  );
+  assign sck_latched = _049_;
+  assign sck_old = _050_;
+  assign cs_latched = _051_;
+  assign cs_old = _052_;
+  assign mosi_latched = _053_;
+  assign spi_done = _054_;
+  assign msg_bit_index = _055_;
+  assign msg_cnt = _058_;
+  assign miso_reg = _059_;
+  assign mosi_reg = _061_;
+  assign status_reg = _062_;
+  assign w_status_cmd = _064_;
+  assign w_pwm_cmd = _066_;
+  assign r_pwm_cmd = _069_;
+  assign r_freq_cmd = _071_;
+  assign w_freq_cmd = _073_;
+  assign pwm_reg = _075_;
+  assign freq_cnt = _106_;
+  assign interrupt = _095_;
+  assign interrupt_ack = _076_;
+  assign int_ack_pulse = _077_;
+  assign freq_gen_int = _079_;
+  assign interval_time = _081_;
+  assign MISO = miso_reg[7];
+  assign PWM_OUT_1 = _000_;
+  assign PWM_OUT_2 = _084_;
+endmodule
diff --git a/convert.sh b/convert.sh
new file mode 100755
index 0000000..e14e6ac
--- /dev/null
+++ b/convert.sh
@@ -0,0 +1,6 @@
+yosys -qm ghdl -p 'ghdl -fsynopsys COMPARATOR_16BIT.vhd -e COMPARATOR_16BIT; write_verilog COMPARATOR_16BIT.v'
+yosys -qm ghdl -p 'ghdl -fsynopsys COUNTER_16BIT.vhd -e COUNTER_16BIT; write_verilog COUNTER_16BIT.v'
+yosys -qm ghdl -p 'ghdl -fsynopsys FREQCOUNT_CORE_V4.vhd --ieee=synopsys -e FREQCOUNT_CORE_V4; write_verilog FREQCOUNT_CORE_V4.v'
+yosys -qm ghdl -p 'ghdl -fsynopsys PWM_CORE_LAT_V17.vhd -e PWM_CORE_LAT_V17; write_verilog PWM_CORE_LAT_V17.v'
+yosys -qm ghdl -p 'ghdl -fsynopsys REGISTER_16BIT.vhd -e REGISTER_16BIT; write_verilog REGISTER_16BIT.v'
+yosys -qm ghdl -p 'ghdl -fsynopsys SPI_SLAVE_TOPDESIGN.vhd -e bionic_eye_spi_slave ; write_verilog SPI_SLAVE_TOPDESIGN.v'