From 7c59164928de1eca635108aa016a41c06c93998c Mon Sep 17 00:00:00 2001
From: jueshiwenli <275626310@qq.com>
Date: Tue, 21 Jan 2025 17:33:22 +0800
Subject: [PATCH] cpu-o3: changge store misaligned warn to DPRINTF

many warning of Store misaligned because of Error path

Change-Id: I6dc10ec27b5ed15178d0f1442895e50a883e56b1
---
 src/cpu/o3/lsq.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/cpu/o3/lsq.cc b/src/cpu/o3/lsq.cc
index 93116eb4bd..17749d8fb6 100644
--- a/src/cpu/o3/lsq.cc
+++ b/src/cpu/o3/lsq.cc
@@ -1035,7 +1035,7 @@ LSQ::pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
     inst->effSize = size;
 
     if (!isLoad && !inst->isVector() && size > 1 && addr % size != 0) {
-        warn( "Store misaligned: size: %u, Addr: %#lx, code: %d\n", size,
+         DPRINTF(LSQ, "Store misaligned: size: %u, Addr: %#lx, code: %d\n", size,
             addr, RiscvISA::ExceptionCode::STORE_ADDR_MISALIGNED);
         return std::make_shared<RiscvISA::AddressFault>(request->mainReq()->getVaddr(),
             request->mainReq()->getgPaddr(),