From 511caf6a03e3ecfe123dda5319227c950f2bef90 Mon Sep 17 00:00:00 2001
From: jueshiwenli <275626310@qq.com>
Date: Tue, 21 Jan 2025 17:36:11 +0800
Subject: [PATCH] arch-riscv: Fix bugs of h-ptw

Change-Id: I8789d663029a46e14aa887f15082345bd7adbeec
---
 src/arch/riscv/pagetable_walker.cc | 13 +++++++++----
 src/arch/riscv/tlb.cc              |  2 --
 2 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/src/arch/riscv/pagetable_walker.cc b/src/arch/riscv/pagetable_walker.cc
index 3dfdd65a0e..b010e6ec04 100644
--- a/src/arch/riscv/pagetable_walker.cc
+++ b/src/arch/riscv/pagetable_walker.cc
@@ -706,6 +706,8 @@ Walker::WalkerState::twoStageStepWalk(PacketPtr &write)
                         }
 
                         else if (l2_level == 1) {
+                            inl2Entry.index =
+                                (gPaddr >> (LEVEL_BITS + PageShift + L2TLB_BLK_OFFSET)) & (walker->tlb->L2TLB_L2_MASK);
                             walker->tlb->L2TLBInsert(inl2Entry.gpaddr, inl2Entry, l2_level, L_L2sp2, l2_i, false,
                                                      gstage);
                         }  // hit level =1
@@ -917,11 +919,14 @@ Walker::WalkerState::twoStageWalk(PacketPtr &write)
                                 inl2Entry.pte = l2pte;
                                 inl2Entry.paddr = l2pte.ppn;
                                 if (l2_level == 0) {
-                                    inl2Entry.index =
-                                        (gPaddr >> (L2TLB_BLK_OFFSET + PageShift)) & walker->tlb->L2TLB_L3_MASK;
+                                    inl2Entry.index = (inl2Entry.vaddr >> (L2TLB_BLK_OFFSET + PageShift)) &
+                                                      walker->tlb->L2TLB_L3_MASK;
                                     walker->tlb->L2TLBInsert(inl2Entry.vaddr, inl2Entry, l2_level, L_L2L3, l2_i, false,
                                                              vsstage);
                                 } else if (l2_level == 1) {
+                                    inl2Entry.index =
+                                        (inl2Entry.vaddr >> (LEVEL_BITS + PageShift + L2TLB_BLK_OFFSET)) &
+                                        walker->tlb->L2TLB_L2_MASK;
                                     walker->tlb->L2TLBInsert(inl2Entry.vaddr, inl2Entry, l2_level, L_L2sp2, l2_i,
                                                              false, vsstage);
                                 } else if (l2_level == 2) {
@@ -1020,7 +1025,7 @@ Walker::WalkerState::twoStageWalk(PacketPtr &write)
                                 walker->tlb->L2TLBInsert(inl2Entry.vaddr, inl2Entry, l2_level, L_L2L1, l2_i, false,
                                                          vsstage);
                             } else if (l2_level == 1) {
-                                inl2Entry.index = (entry.vaddr >> (LEVEL_BITS + PageShift + L2TLB_BLK_OFFSET)) &
+                                inl2Entry.index = (inl2Entry.vaddr>> (LEVEL_BITS + PageShift + L2TLB_BLK_OFFSET)) &
                                                   (walker->tlb->L2TLB_L2_MASK);
                                 walker->tlb->L2TLBInsert(inl2Entry.vaddr, inl2Entry, l2_level, L_L2L2, l2_i, false,
                                                          vsstage);
@@ -1242,7 +1247,7 @@ Walker::WalkerState::stepWalk(PacketPtr &write)
                                                      direct);
                         }
                         if (l2_level == 1) {
-                            inl2Entry.index = (entry.vaddr >> (LEVEL_BITS + PageShift + L2TLB_BLK_OFFSET)) &
+                            inl2Entry.index = (inl2Entry.vaddr >> (LEVEL_BITS + PageShift + L2TLB_BLK_OFFSET)) &
                                               (walker->tlb->L2TLB_L2_MASK);
                             walker->tlb->L2TLBInsert(inl2Entry.vaddr, inl2Entry, l2_level, L_L2L2, l2_i, false,
                                                      direct);
diff --git a/src/arch/riscv/tlb.cc b/src/arch/riscv/tlb.cc
index 1dbb9bc41b..f0ef32be60 100644
--- a/src/arch/riscv/tlb.cc
+++ b/src/arch/riscv/tlb.cc
@@ -1984,8 +1984,6 @@ TLB::translate(const RequestPtr &req, ThreadContext *tc,
             req->setFlags(Request::PHYSICAL);
 
         Fault fault;
-        if (req->getVaddr() == 0)
-            warn("notice vaddr == 0 pc %lx \n", req->getPC());
 
         if (req->getFlags() & Request::PHYSICAL) {
             req->setTwoStageState(false, 0, 0);