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Move pla into decode
1 parent 1916f3a commit 7e8c22b

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2 files changed

+80
-131
lines changed

2 files changed

+80
-131
lines changed

‎src/main/scala/rocket/ABLU.scala‎

Lines changed: 57 additions & 113 deletions
Original file line numberDiff line numberDiff line change
@@ -10,62 +10,62 @@ import freechips.rocketchip.tile.CoreModule
1010

1111
object ABLU extends ALUFN
1212
{
13-
override val SZ_ALU_FN = 6
14-
override def FN_X = BitPat("b??????")
15-
override def FN_ADD = 0.U(SZ_ALU_FN.W)
16-
override def FN_SL = 1.U(SZ_ALU_FN.W)
17-
override def FN_SEQ = 2.U(SZ_ALU_FN.W)
18-
override def FN_SNE = 3.U(SZ_ALU_FN.W)
19-
override def FN_XOR = 4.U(SZ_ALU_FN.W)
20-
override def FN_SR = 5.U(SZ_ALU_FN.W)
21-
override def FN_OR = 6.U(SZ_ALU_FN.W)
22-
override def FN_AND = 7.U(SZ_ALU_FN.W)
23-
override def FN_SUB = 10.U(SZ_ALU_FN.W)
24-
override def FN_SRA = 11.U(SZ_ALU_FN.W)
25-
override def FN_SLT = 12.U(SZ_ALU_FN.W)
26-
override def FN_SGE = 13.U(SZ_ALU_FN.W)
27-
override def FN_SLTU = 14.U(SZ_ALU_FN.W)
28-
override def FN_SGEU = 15.U(SZ_ALU_FN.W)
13+
override val SZ_ALU_FN = 39
14+
override def FN_X = BitPat("b??_???_????_????_????__????__??_????_????_????_????")
15+
override def FN_ADD = "b00_000_0000_0000_0000__0001__00_0000_0000_0000_0001".U(SZ_ALU_FN.W)
16+
override def FN_SL = "b00_000_0000_1100_0000__0001__00_0000_0000_0000_0010".U(SZ_ALU_FN.W)
17+
override def FN_SEQ = "b00_100_0000_0000_0000__0001__00_0000_0000_0100_0000".U(SZ_ALU_FN.W)
18+
override def FN_SNE = "b00_110_0000_0000_0000__0001__00_0000_0000_0100_0000".U(SZ_ALU_FN.W)
19+
override def FN_XOR = "b00_000_0000_0000_0000__0001__00_0000_0000_0000_1000".U(SZ_ALU_FN.W)
20+
override def FN_SR = "b00_000_0000_0000_0000__0001__00_0000_0000_0000_0010".U(SZ_ALU_FN.W)
21+
override def FN_OR = "b00_000_0000_0000_0000__0001__00_0000_0000_0001_0000".U(SZ_ALU_FN.W)
22+
override def FN_AND = "b00_000_0000_0000_0000__0001__00_0000_0000_0000_0100".U(SZ_ALU_FN.W)
23+
override def FN_SUB = "b00_000_0000_0000_0011__0001__00_0000_0000_0000_0001".U(SZ_ALU_FN.W)
24+
override def FN_SRA = "b00_000_0000_0001_0000__0001__00_0000_0000_0000_0010".U(SZ_ALU_FN.W)
25+
override def FN_SLT = "b00_000_0000_0000_0011__0001__00_0000_0000_0100_0000".U(SZ_ALU_FN.W)
26+
override def FN_SGE = "b00_010_0000_0000_0011__0001__00_0000_0000_0100_0000".U(SZ_ALU_FN.W)
27+
override def FN_SLTU = "b00_001_0000_0000_0011__0001__00_0000_0000_0100_0000".U(SZ_ALU_FN.W)
28+
override def FN_SGEU = "b00_011_0000_0000_0011__0001__00_0000_0000_0100_0000".U(SZ_ALU_FN.W)
2929

3030
// from Zb
3131
// Zba: UW is encoded here becuase it is DW_64
32-
override def FN_ADDUW = 16.U(SZ_ALU_FN.W)
33-
override def FN_SLLIUW = 17.U(SZ_ALU_FN.W)
34-
override def FN_SH1ADD = 18.U(SZ_ALU_FN.W)
35-
override def FN_SH1ADDUW = 19.U(SZ_ALU_FN.W)
36-
override def FN_SH2ADD = 20.U(SZ_ALU_FN.W)
37-
override def FN_SH2ADDUW = 21.U(SZ_ALU_FN.W)
38-
override def FN_SH3ADD = 22.U(SZ_ALU_FN.W)
39-
override def FN_SH3ADDUW = 23.U(SZ_ALU_FN.W)
32+
override def FN_ADDUW = "b00_000_0000_0000_1000__0001__00_0000_0000_0000_0001".U(SZ_ALU_FN.W)
33+
override def FN_SLLIUW = "b00_000_0000_1100_1000__0001__00_0000_0000_0000_0010".U(SZ_ALU_FN.W)
34+
override def FN_SH1ADD = "b00_000_0000_0000_0000__0010__00_0000_0000_0000_0001".U(SZ_ALU_FN.W)
35+
override def FN_SH1ADDUW = "b00_000_0000_0000_1000__0010__00_0000_0000_0000_0001".U(SZ_ALU_FN.W)
36+
override def FN_SH2ADD = "b00_000_0000_0000_0000__0100__00_0000_0000_0000_0001".U(SZ_ALU_FN.W)
37+
override def FN_SH2ADDUW = "b00_000_0000_0000_1000__0100__00_0000_0000_0000_0001".U(SZ_ALU_FN.W)
38+
override def FN_SH3ADD = "b00_000_0000_0000_0000__1000__00_0000_0000_0000_0001".U(SZ_ALU_FN.W)
39+
override def FN_SH3ADDUW = "b00_000_0000_0000_1000__1000__00_0000_0000_0000_0001".U(SZ_ALU_FN.W)
4040
// Zbb
41-
override def FN_ROR = 24.U(SZ_ALU_FN.W)
42-
override def FN_ROL = 25.U(SZ_ALU_FN.W)
43-
override def FN_ANDN = 26.U(SZ_ALU_FN.W)
44-
override def FN_ORN = 27.U(SZ_ALU_FN.W)
45-
override def FN_XNOR = 28.U(SZ_ALU_FN.W)
46-
override def FN_REV8 = 29.U(SZ_ALU_FN.W)
47-
override def FN_ORCB = 30.U(SZ_ALU_FN.W)
48-
override def FN_SEXTB = 31.U(SZ_ALU_FN.W)
49-
override def FN_SEXTH = 32.U(SZ_ALU_FN.W)
50-
override def FN_ZEXTH = 33.U(SZ_ALU_FN.W)
51-
override def FN_MAX = 34.U(SZ_ALU_FN.W)
52-
override def FN_MAXU = 35.U(SZ_ALU_FN.W)
53-
override def FN_MIN = 36.U(SZ_ALU_FN.W)
54-
override def FN_MINU = 37.U(SZ_ALU_FN.W)
55-
override def FN_CPOP = 38.U(SZ_ALU_FN.W)
56-
override def FN_CLZ = 39.U(SZ_ALU_FN.W)
57-
override def FN_CTZ = 40.U(SZ_ALU_FN.W)
41+
override def FN_ROR = "b00_000_0000_0010_0000__0001__00_0000_0000_0000_0010".U(SZ_ALU_FN.W)
42+
override def FN_ROL = "b00_000_0000_1110_0000__0001__00_0000_0000_0000_0010".U(SZ_ALU_FN.W)
43+
override def FN_ANDN = "b00_000_0000_0000_0010__0001__00_0000_0000_0000_0100".U(SZ_ALU_FN.W)
44+
override def FN_ORN = "b00_000_0000_0000_0010__0001__00_0000_0000_0001_0000".U(SZ_ALU_FN.W)
45+
override def FN_XNOR = "b00_000_0000_0000_0010__0001__00_0000_0000_0000_1000".U(SZ_ALU_FN.W)
46+
override def FN_REV8 = "b00_000_0000_0000_0000__0001__00_0001_0000_0000_0000".U(SZ_ALU_FN.W)
47+
override def FN_ORCB = "b10_000_0000_0000_0000__0001__00_0010_0000_0000_0000".U(SZ_ALU_FN.W)
48+
override def FN_SEXTB = "b00_000_0000_0000_0000__0001__00_0000_1000_0000_0000".U(SZ_ALU_FN.W)
49+
override def FN_SEXTH = "b01_000_0000_0000_0000__0001__00_0000_0100_0000_0000".U(SZ_ALU_FN.W)
50+
override def FN_ZEXTH = "b00_000_0000_0000_0000__0001__00_0000_0100_0000_0000".U(SZ_ALU_FN.W)
51+
override def FN_MAX = "b00_000_0000_0000_0011__0001__00_0000_0000_1000_0000".U(SZ_ALU_FN.W)
52+
override def FN_MAXU = "b00_001_0000_0000_0011__0001__00_0000_0000_1000_0000".U(SZ_ALU_FN.W)
53+
override def FN_MIN = "b00_010_0000_0000_0011__0001__00_0000_0000_1000_0000".U(SZ_ALU_FN.W)
54+
override def FN_MINU = "b00_011_0000_0000_0011__0001__00_0000_0000_1000_0000".U(SZ_ALU_FN.W)
55+
override def FN_CPOP = "b00_000_0000_0000_0000__0001__00_0000_0001_0000_0000".U(SZ_ALU_FN.W)
56+
override def FN_CLZ = "b00_000_1101_1110_0000__0001__00_0000_0010_0000_0000".U(SZ_ALU_FN.W)
57+
override def FN_CTZ = "b00_000_1101_0000_0000__0001__00_0000_0010_0000_0000".U(SZ_ALU_FN.W)
5858
// Zbs
59-
override def FN_BCLR = 41.U(SZ_ALU_FN.W)
60-
override def FN_BEXT = 42.U(SZ_ALU_FN.W)
61-
override def FN_BINV = 43.U(SZ_ALU_FN.W)
62-
override def FN_BSET = 44.U(SZ_ALU_FN.W)
59+
override def FN_BCLR = "b00_000_1110_1000_0100__0001__00_0000_0000_0000_0100".U(SZ_ALU_FN.W)
60+
override def FN_BEXT = "b00_000_1000_1000_0100__0001__00_0000_0000_0010_0000".U(SZ_ALU_FN.W)
61+
override def FN_BINV = "b00_000_1000_1000_0100__0001__00_0000_0000_0000_1000".U(SZ_ALU_FN.W)
62+
override def FN_BSET = "b00_000_1000_1000_0100__0001__00_0000_0000_0001_0000".U(SZ_ALU_FN.W)
6363
// Zbk
64-
override def FN_BREV8 = 45.U(SZ_ALU_FN.W)
65-
override def FN_PACK = 46.U(SZ_ALU_FN.W)
66-
override def FN_PACKH = 47.U(SZ_ALU_FN.W)
67-
override def FN_ZIP = 48.U(SZ_ALU_FN.W)
68-
override def FN_UNZIP = 49.U(SZ_ALU_FN.W)
64+
override def FN_BREV8 = "b00_000_0000_0000_0000__0001__00_0010_0000_0000_0000".U(SZ_ALU_FN.W)
65+
override def FN_PACK = "b00_000_0000_0000_0000__0001__00_0100_0000_0000_0000".U(SZ_ALU_FN.W)
66+
override def FN_PACKH = "b00_000_0000_0000_0000__0001__00_1000_0000_0000_0000".U(SZ_ALU_FN.W)
67+
override def FN_ZIP = "b00_000_0000_0000_0000__0001__01_0000_0000_0000_0000".U(SZ_ALU_FN.W)
68+
override def FN_UNZIP = "b00_000_0000_0000_0000__0001__10_0000_0000_0000_0000".U(SZ_ALU_FN.W)
6969

7070
override def FN_DIV = FN_XOR
7171
override def FN_DIVU = FN_SR
@@ -81,70 +81,14 @@ object ABLU extends ALUFN
8181
import ABLU._
8282

8383
class ABLU(implicit p: Parameters) extends CoreModule()(p) with HasALUIO {
84-
val (pla_in, pla_out) = pla(Seq(
85-
// ctrl signals, shxadd1H out1H
86-
(BitPat("b000000"),BitPat("b00_000_0000_0000_0000 0001 00_0000_0000_0000_0001")),//FN_ADD
87-
(BitPat("b000001"),BitPat("b00_000_0000_1100_0000 0001 00_0000_0000_0000_0010")),//FN_SL
88-
(BitPat("b000010"),BitPat("b00_100_0000_0000_0000 0001 00_0000_0000_0100_0000")),//FN_SEQ
89-
(BitPat("b000011"),BitPat("b00_110_0000_0000_0000 0001 00_0000_0000_0100_0000")),//FN_SNE
90-
(BitPat("b000100"),BitPat("b00_000_0000_0000_0000 0001 00_0000_0000_0000_1000")),//FN_XOR
91-
(BitPat("b000101"),BitPat("b00_000_0000_0000_0000 0001 00_0000_0000_0000_0010")),//FN_SR
92-
(BitPat("b000110"),BitPat("b00_000_0000_0000_0000 0001 00_0000_0000_0001_0000")),//FN_OR
93-
(BitPat("b000111"),BitPat("b00_000_0000_0000_0000 0001 00_0000_0000_0000_0100")),//FN_AND
94-
(BitPat("b001000"),BitPat("b00_000_0000_0000_0000 0000 00_0000_0000_0000_0000")),//UNUSED
95-
(BitPat("b001001"),BitPat("b00_000_0000_0000_0000 0000 00_0000_0000_0000_0000")),//UNUSED
96-
(BitPat("b001010"),BitPat("b00_000_0000_0000_0011 0001 00_0000_0000_0000_0001")),//FN_SUB
97-
(BitPat("b001011"),BitPat("b00_000_0000_0001_0000 0001 00_0000_0000_0000_0010")),//FN_SRA
98-
(BitPat("b001100"),BitPat("b00_000_0000_0000_0011 0001 00_0000_0000_0100_0000")),//FN_SLT
99-
(BitPat("b001101"),BitPat("b00_010_0000_0000_0011 0001 00_0000_0000_0100_0000")),//FN_SGE
100-
(BitPat("b001110"),BitPat("b00_001_0000_0000_0011 0001 00_0000_0000_0100_0000")),//FN_SLTU
101-
(BitPat("b001111"),BitPat("b00_011_0000_0000_0011 0001 00_0000_0000_0100_0000")),//FN_SGEU
102-
// Zb
103-
(BitPat("b010000"),BitPat("b00_000_0000_0000_1000 0001 00_0000_0000_0000_0001")),//FN_ADDUW
104-
(BitPat("b010001"),BitPat("b00_000_0000_1100_1000 0001 00_0000_0000_0000_0010")),//FN_SLLIUW
105-
(BitPat("b010010"),BitPat("b00_000_0000_0000_0000 0010 00_0000_0000_0000_0001")),//FN_SH1ADD
106-
(BitPat("b010011"),BitPat("b00_000_0000_0000_1000 0010 00_0000_0000_0000_0001")),//FN_SH1ADDUW
107-
(BitPat("b010100"),BitPat("b00_000_0000_0000_0000 0100 00_0000_0000_0000_0001")),//FN_SH2ADD
108-
(BitPat("b010101"),BitPat("b00_000_0000_0000_1000 0100 00_0000_0000_0000_0001")),//FN_SH2ADDUW
109-
(BitPat("b010110"),BitPat("b00_000_0000_0000_0000 1000 00_0000_0000_0000_0001")),//FN_SH3ADD
110-
(BitPat("b010111"),BitPat("b00_000_0000_0000_1000 1000 00_0000_0000_0000_0001")),//FN_SH3ADDUW
111-
(BitPat("b011000"),BitPat("b00_000_0000_0010_0000 0001 00_0000_0000_0000_0010")),//FN_ROR
112-
(BitPat("b011001"),BitPat("b00_000_0000_1110_0000 0001 00_0000_0000_0000_0010")),//FN_ROL
113-
(BitPat("b011010"),BitPat("b00_000_0000_0000_0010 0001 00_0000_0000_0000_0100")),//FN_ANDN
114-
(BitPat("b011011"),BitPat("b00_000_0000_0000_0010 0001 00_0000_0000_0001_0000")),//FN_ORN
115-
(BitPat("b011100"),BitPat("b00_000_0000_0000_0010 0001 00_0000_0000_0000_1000")),//FN_XNOR
116-
(BitPat("b011101"),BitPat("b00_000_0000_0000_0000 0001 00_0001_0000_0000_0000")),//FN_REV8
117-
(BitPat("b011110"),BitPat("b10_000_0000_0000_0000 0001 00_0010_0000_0000_0000")),//FN_ORCB
118-
(BitPat("b011111"),BitPat("b00_000_0000_0000_0000 0001 00_0000_1000_0000_0000")),//FN_SEXTB
119-
(BitPat("b100000"),BitPat("b01_000_0000_0000_0000 0001 00_0000_0100_0000_0000")),//FN_SEXTH
120-
(BitPat("b100001"),BitPat("b00_000_0000_0000_0000 0001 00_0000_0100_0000_0000")),//FN_ZEXTH
121-
(BitPat("b100010"),BitPat("b00_000_0000_0000_0011 0001 00_0000_0000_1000_0000")),//FN_MAX
122-
(BitPat("b100011"),BitPat("b00_001_0000_0000_0011 0001 00_0000_0000_1000_0000")),//FN_MAXU
123-
(BitPat("b100100"),BitPat("b00_010_0000_0000_0011 0001 00_0000_0000_1000_0000")),//FN_MIN
124-
(BitPat("b100101"),BitPat("b00_011_0000_0000_0011 0001 00_0000_0000_1000_0000")),//FN_MINU
125-
(BitPat("b100110"),BitPat("b00_000_0000_0000_0000 0001 00_0000_0001_0000_0000")),//FN_CPOP
126-
(BitPat("b100111"),BitPat("b00_000_1101_1110_0000 0001 00_0000_0010_0000_0000")),//FN_CLZ
127-
(BitPat("b101000"),BitPat("b00_000_1101_0000_0000 0001 00_0000_0010_0000_0000")),//FN_CTZ
128-
(BitPat("b101001"),BitPat("b00_000_1110_1000_0100 0001 00_0000_0000_0000_0100")),//FN_BCLR
129-
(BitPat("b101010"),BitPat("b00_000_1000_1000_0100 0001 00_0000_0000_0010_0000")),//FN_BEXT
130-
(BitPat("b101011"),BitPat("b00_000_1000_1000_0100 0001 00_0000_0000_0000_1000")),//FN_BINV
131-
(BitPat("b101100"),BitPat("b00_000_1000_1000_0100 0001 00_0000_0000_0001_0000")),//FN_BSET
132-
(BitPat("b101101"),BitPat("b00_000_0000_0000_0000 0001 00_0010_0000_0000_0000")),//FN_BREV8
133-
(BitPat("b101110"),BitPat("b00_000_0000_0000_0000 0001 00_0100_0000_0000_0000")),//FN_PACK
134-
(BitPat("b101111"),BitPat("b00_000_0000_0000_0000 0001 00_1000_0000_0000_0000")),//FN_PACKH
135-
(BitPat("b110000"),BitPat("b00_000_0000_0000_0000 0001 01_0000_0000_0000_0000")),//FN_ZIP
136-
(BitPat("b110001"),BitPat("b00_000_0000_0000_0000 0001 10_0000_0000_0000_0000")),//FN_UNZIP
137-
))
138-
139-
pla_in := io.fn
14084
// note that it is inverted
141-
val isSub :: isIn2Inv :: isZBS :: isUW :: Nil = pla_out(25,22).asBools
142-
val isSRA :: isRotate :: isLeft :: isLeftZBS :: Nil = pla_out(29,26).asBools
143-
val isCZ :: isBCLR :: isCZBCLR :: isCZZBS :: Nil = pla_out(33,30).asBools
144-
val isUnsigned :: isInverted :: isSEQSNE :: Nil = pla_out(36,34).asBools
145-
val isSEXT :: isORC :: Nil = pla_out(38,37).asBools
146-
val shxadd1H = pla_out(21,18) // 4 bit
147-
val out1H = pla_out(17,0)
85+
val isSub :: isIn2Inv :: isZBS :: isUW :: Nil = io.fn(25,22).asBools
86+
val isSRA :: isRotate :: isLeft :: isLeftZBS :: Nil = io.fn(29,26).asBools
87+
val isCZ :: isBCLR :: isCZBCLR :: isCZZBS :: Nil = io.fn(33,30).asBools
88+
val isUnsigned :: isInverted :: isSEQSNE :: Nil = io.fn(36,34).asBools
89+
val isSEXT :: isORC :: Nil = io.fn(38,37).asBools
90+
val shxadd1H = io.fn(21,18) // 4 bit
91+
val out1H = io.fn(17,0)
14892

14993
// process input
15094
// used by SUB, ANDN, ORN, XNOR

‎src/main/scala/rocket/Multiplier.scala‎

Lines changed: 23 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -7,10 +7,13 @@ import chisel3._
77
import chisel3.util.{Cat, log2Up, log2Ceil, log2Floor, Log2, Decoupled, Enum, Fill, Valid, Pipe}
88
import Chisel.ImplicitConversions._
99
import freechips.rocketchip.util._
10-
import ALU._
10+
import freechips.rocketchip.config.Parameters
11+
import freechips.rocketchip.tile.HasCoreParameters
1112

12-
class MultiplierReq(dataBits: Int, tagBits: Int) extends Bundle {
13-
val fn = Bits(SZ_ALU_FN.W)
13+
class MultiplierReq(dataBits: Int, tagBits: Int)(implicit val p: Parameters) extends Bundle with HasCoreParameters {
14+
val alu = if (usingABLU) ABLU else ALU
15+
16+
val fn = Bits(alu.SZ_ALU_FN.W)
1417
val dw = Bits(SZ_DW.W)
1518
val in1 = Bits(dataBits.W)
1619
val in2 = Bits(dataBits.W)
@@ -22,7 +25,7 @@ class MultiplierResp(dataBits: Int, tagBits: Int) extends Bundle {
2225
val tag = UInt(tagBits.W)
2326
}
2427

25-
class MultiplierIO(val dataBits: Int, val tagBits: Int) extends Bundle {
28+
class MultiplierIO(val dataBits: Int, val tagBits: Int)(implicit val p: Parameters) extends Bundle {
2629
val req = Flipped(Decoupled(new MultiplierReq(dataBits, tagBits)))
2730
val kill = Input(Bool())
2831
val resp = Decoupled(new MultiplierResp(dataBits, tagBits))
@@ -36,7 +39,7 @@ case class MulDivParams(
3639
divEarlyOutGranularity: Int = 1
3740
)
3841

39-
class MulDiv(cfg: MulDivParams, width: Int, nXpr: Int = 32) extends Module {
42+
class MulDiv(cfg: MulDivParams, width: Int, nXpr: Int = 32)(implicit val p: Parameters) extends Module with HasCoreParameters {
4043
private def minDivLatency = (cfg.divUnroll > 0).option(if (cfg.divEarlyOut) 3 else 1 + w/cfg.divUnroll)
4144
private def minMulLatency = (cfg.mulUnroll > 0).option(if (cfg.mulEarlyOut) 2 else w/cfg.mulUnroll)
4245
def minLatency: Int = (minDivLatency ++ minMulLatency).min
@@ -59,16 +62,17 @@ class MulDiv(cfg: MulDivParams, width: Int, nXpr: Int = 32) extends Module {
5962
val divisor = Reg(Bits((w+1).W)) // div only needs w bits
6063
val remainder = Reg(Bits((2*mulw+2).W)) // div only needs 2*w+1 bits
6164

65+
val alu = if (usingABLU) ABLU else ALU
6266
val mulDecode = List(
63-
FN_MUL -> List(Y, N, X, X),
64-
FN_MULH -> List(Y, Y, Y, Y),
65-
FN_MULHU -> List(Y, Y, N, N),
66-
FN_MULHSU -> List(Y, Y, Y, N))
67+
alu.FN_MUL -> List(Y, N, X, X),
68+
alu.FN_MULH -> List(Y, Y, Y, Y),
69+
alu.FN_MULHU -> List(Y, Y, N, N),
70+
alu.FN_MULHSU -> List(Y, Y, Y, N))
6771
val divDecode = List(
68-
FN_DIV -> List(N, N, Y, Y),
69-
FN_REM -> List(N, Y, Y, Y),
70-
FN_DIVU -> List(N, N, N, N),
71-
FN_REMU -> List(N, Y, N, N))
72+
alu.FN_DIV -> List(N, N, Y, Y),
73+
alu.FN_REM -> List(N, Y, Y, Y),
74+
alu.FN_DIVU -> List(N, N, N, N),
75+
alu.FN_REMU -> List(N, Y, N, N))
7276
val cmdMul :: cmdHi :: lhsSigned :: rhsSigned :: Nil =
7377
DecodeLogic(io.req.bits.fn, List(X, X, X, X),
7478
(if (cfg.divUnroll != 0) divDecode else Nil) ++ (if (cfg.mulUnroll != 0) mulDecode else Nil)).map(_.asBool)
@@ -181,19 +185,20 @@ class MulDiv(cfg: MulDivParams, width: Int, nXpr: Int = 32) extends Module {
181185
io.req.ready := state === s_ready
182186
}
183187

184-
class PipelinedMultiplier(width: Int, latency: Int, nXpr: Int = 32) extends Module with ShouldBeRetimed {
188+
class PipelinedMultiplier(width: Int, latency: Int, nXpr: Int = 32)(implicit val p: Parameters) extends Module with ShouldBeRetimed with HasCoreParameters {
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val io = IO(new Bundle {
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val req = Flipped(Valid(new MultiplierReq(width, log2Ceil(nXpr))))
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val resp = Valid(new MultiplierResp(width, log2Ceil(nXpr)))
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})
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190194
val in = Pipe(io.req)
191195

196+
val alu = if (usingABLU) ABLU else ALU
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val decode = List(
193-
FN_MUL -> List(N, X, X),
194-
FN_MULH -> List(Y, Y, Y),
195-
FN_MULHU -> List(Y, N, N),
196-
FN_MULHSU -> List(Y, Y, N))
198+
alu.FN_MUL -> List(N, X, X),
199+
alu.FN_MULH -> List(Y, Y, Y),
200+
alu.FN_MULHU -> List(Y, N, N),
201+
alu.FN_MULHSU -> List(Y, Y, N))
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val cmdHi :: lhsSigned :: rhsSigned :: Nil =
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DecodeLogic(in.bits.fn, List(X, X, X), decode).map(_.asBool)
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val cmdHalf = (width > 32).B && in.bits.dw === DW_32

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