Baseline: boot protocol upload benchmark (hi3516ev300)

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Boot Protocol Upload Benchmark

Baseline Results (commit ec8bd22)

Measured on hi3516ev300 with FTDI FT232R USB-UART adapter at 115200 baud.
3 consecutive runs, power-cycle between each.

Stage	Size	Time	Speed
Handshake	—	10–15s	varies with power-cycle timing
DDR step	64 bytes	0.05s	—
SPL	24,576 bytes	2.33s	10,548 B/s
U-Boot / Agent	211,607 bytes	22.17s	9,545 B/s
Total upload (after handshake)	236,183 bytes	24.55s	9,620 B/s

Upload time after handshake: <0.1s variance across 3 runs.
Total wall time including handshake: 35–39s.

How to Reproduce

# Requires: hi3516ev300 board with boot mode pin set to serial download
# Serial adapter connected to UART0

PORT=/dev/uart-IVG85HG50PYA-S  # or /dev/serial/by-id/usb-FTDI_...

uv run python3 -c "
import asyncio, time, sys
sys.path.insert(0, 'src')

async def main():
    from defib.profiles.loader import load_profile
    from defib.protocol.hisilicon_standard import HiSiliconStandard
    from defib.transport.serial import SerialTransport
    from defib.recovery.events import ProgressEvent
    from defib.firmware import get_cached_path

    profile = load_profile('hi3516ev300')
    fw = get_cached_path('hi3516ev300').read_bytes()

    print('*** POWER-CYCLE NOW ***', flush=True)
    transport = await SerialTransport.create('$PORT')
    protocol = HiSiliconStandard()
    protocol.set_profile(profile)

    t0 = time.time()
    def on_progress(e: ProgressEvent):
        if e.message: print(f'  [{time.time()-t0:.2f}s] {e.message}', flush=True)

    hs = await protocol.handshake(transport, on_progress)
    result = await protocol.send_firmware(transport, fw, on_progress)
    elapsed = time.time() - t0
    print(f'Total: {elapsed:.2f}s ({len(fw)/elapsed:.0f} B/s)')
    await transport.close()

asyncio.run(main())
"

Regression Criteria

• Upload time after handshake should be <30s for 236,183 bytes at 115200 baud
• SPL stage should complete in <3s
• Zero retries, zero CRC errors
• Consistent across 3 consecutive runs (<1s variance)

Environment

• SoC: hi3516ev300 (Cortex-A7, DDR3)
• Adapter: FTDI FT232R USB-UART
• Baud: 115200 (bootrom fixed)
• Protocol: HiSilicon standard (DDR step → SPL → U-Boot)
• Host: Linux, Python 3.14, pyserial