diff --git a/src/main/scala/utils/FlushableQueue.scala b/src/main/scala/utils/FlushableQueue.scala
index 1e1380fe..be7707e4 100644
--- a/src/main/scala/utils/FlushableQueue.scala
+++ b/src/main/scala/utils/FlushableQueue.scala
@@ -30,6 +30,8 @@ class FlushableQueue[T <: Data](gen: T, val entries: Int,
   private val full = ptr_match && maybe_full
   private val do_enq = WireInit(io.enq.fire)
   private val do_deq = WireInit(io.deq.fire)
+//Unable enter quene when reset or flush
+  private val not_enq = RegInit(true.B)
 
   when (do_enq) {
     ram(enq_ptr.value) := io.enq.bits
@@ -43,7 +45,7 @@ class FlushableQueue[T <: Data](gen: T, val entries: Int,
   }
 
   io.deq.valid := !empty
-  io.enq.ready := !full
+  io.enq.ready := !full & !not_enq
   io.deq.bits := ram(deq_ptr.value)
 
   if (flow) {
@@ -65,6 +67,11 @@ class FlushableQueue[T <: Data](gen: T, val entries: Int,
       deq_ptr.value := 0.U
     }
     maybe_full := false.B
+    not_enq := true.B
+  }
+  
+  when (!io.flush){
+    not_enq := false.B //add
   }
 
   private val ptr_diff = enq_ptr.value - deq_ptr.value
diff --git a/src/main/scala/utils/SRAMTemplate.scala b/src/main/scala/utils/SRAMTemplate.scala
index a2a2b899..f23b9cc4 100644
--- a/src/main/scala/utils/SRAMTemplate.scala
+++ b/src/main/scala/utils/SRAMTemplate.scala
@@ -74,17 +74,23 @@ class SRAMTemplate[T <: Data](gen: T, set: Int, way: Int = 1,
 
   val wordType = UInt(gen.getWidth.W)
   val array = SyncReadMem(set, Vec(way, wordType))
-  val (resetState, resetSet) = (WireInit(false.B), WireInit(0.U))
+  val (resetState, resetSet) = (RegInit(false.B), WireInit(0.U))
 
   if (shouldReset) {
     val _resetState = RegInit(true.B)
-    val (_resetSet, resetFinish) = Counter(_resetState, set)
-    when (resetFinish) { _resetState := false.B }
+    val (_resetSet, resetFinish) = Counter(resetState, set)
+    when (resetFinish) { _resetState := false.B;resetState := false.B }
 
-    resetState := _resetState
     resetSet := _resetSet
+
+    withReset(reset.asBool){
+        when(!reset.asBool) {
+            resetState := _resetState
+      }
   }
 
+}
+
   val (ren, wen) = (io.r.req.valid, io.w.req.valid || resetState)
   val realRen = (if (singlePort) ren && !wen else ren)