FAIL ( Check reg_stim.log file!!!! )

[harshgondaliya]

Hi all,

I am constantly getting the below-mentioned error when I run the following step:
./tools/scripts/nf_test.py sim --major switch --minor default
I am using a ternary match table in my P4 code. Till 32 table entries, the Check Registers step passes. But, for anything above 32 table entries, it gives me the below-mentioned error. AFAIK, 4096 TCAM entries are allowed in SDNet 2018.1.1 but still, it is limiting me at 32 table entries.

Can someone please help me in this regard?

loading libsume..
Reconciliation of nf_interface_0_log.axi with nf_interface_0_expected.axi
	PASS (0 packets expected, 0 packets received)

Reconciliation of dma_0_log.axi with dma_0_expected.axi
	PASS (0 packets expected, 0 packets received)

Reconciliation of nf_interface_2_log.axi with nf_interface_2_expected.axi
	PASS (0 packets expected, 0 packets received)

Reconciliation of nf_interface_3_log.axi with nf_interface_3_expected.axi
	PASS (0 packets expected, 0 packets received)

Reconciliation of nf_interface_1_log.axi with nf_interface_1_expected.axi
nf_interface_1_log.axi: 4: #1: warning: meta length (64) disagrees with actual length (72)
	PASS (1 packets expected, 1 packets received)

/home/fpga/harsh-gondaliya/P4-NetFPGA/tools/scripts/nf_sim_registers_axi_logs.py
Check registers
	FAIL ( Check reg_stim.log file!!!! )

Attachment:
reg_stim.log file

[salvatorg]

The SDNet compiler might permit it but the question is if this is supported by the target platform, i.e., Virtex-7. It is mentioned in the documentation of the CAM IPs v1.1 that there is a tradeoff between depth/width. It might be worth to check it. My guess is that you can have deep CAM with few bits as width or shallow with large entries (large width size).