From b5bf85a8e3eb2516b9abca4d1becaf1172d62822 Mon Sep 17 00:00:00 2001 From: Andy Ritger Date: Tue, 17 Oct 2023 09:25:29 -0700 Subject: [PATCH] 545.23.06 --- CHANGELOG.md | 12 + README.md | 20 +- kernel-open/Kbuild | 19 +- kernel-open/common/inc/nv-chardev-numbers.h | 43 + kernel-open/common/inc/nv-ioctl-numa.h | 10 +- .../inc/nv-kthread-q-os.h} | 47 +- kernel-open/common/inc/nv-kthread-q.h | 50 +- kernel-open/common/inc/nv-linux.h | 43 +- kernel-open/common/inc/nv-pgprot.h | 7 + kernel-open/common/inc/nv-proto.h | 6 +- kernel-open/common/inc/nv.h | 20 +- .../common/inc/nv_speculation_barrier.h | 2 +- kernel-open/common/inc/nv_uvm_types.h | 19 +- kernel-open/common/inc/nvkms-api-types.h | 79 +- kernel-open/common/inc/nvkms-kapi.h | 301 +- kernel-open/common/inc/os-interface.h | 10 +- kernel-open/conftest.sh | 775 +- kernel-open/nvidia-drm/nv-kthread-q.c | 334 + .../nvidia-drm/nvidia-dma-fence-helper.h | 37 +- .../nvidia-drm/nvidia-dma-resv-helper.h | 14 + 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.../src/kernel/gpu/bus/third_party_p2p.c | 12 +- .../src/kernel/gpu/bus/third_party_p2p_ctrl.c | 1 + src/nvidia/src/kernel/gpu/ccu/kernel_ccu.c | 5 +- .../src/kernel/gpu/ccu/kernel_ccu_api.c | 26 +- .../gpu/ce/arch/ampere/kernel_ce_ga100.c | 2 +- .../gpu/ce/arch/hopper/kernel_ce_gh100.c | 181 +- src/nvidia/src/kernel/gpu/ce/kernel_ce.c | 12 +- .../src/kernel/gpu/ce/kernel_ce_shared.c | 6 +- .../kernel/gpu/conf_compute/conf_compute.c | 23 +- .../gpu/conf_compute/conf_compute_api.c | 6 +- src/nvidia/src/kernel/gpu/deferred_api.c | 32 +- src/nvidia/src/kernel/gpu/device.c | 91 +- src/nvidia/src/kernel/gpu/device_ctrl.c | 2 +- src/nvidia/src/kernel/gpu/device_share.c | 5 +- .../kernel/gpu/disp/arch/v02/kern_disp_0207.c | 24 +- .../kernel/gpu/disp/arch/v03/kern_disp_0300.c | 19 + .../kernel/gpu/disp/disp_common_ctrl_acpi.c | 11 +- .../gpu/disp/disp_common_kern_ctrl_minimal.c | 27 +- .../inst_mem/arch/v03/disp_inst_mem_0300.c | 3 +- .../kernel/gpu/disp/inst_mem/disp_inst_mem.c | 7 +- .../kernel/gpu/disp/vblank_callback/vblank.c | 31 +- .../disp/vblank_callback/vblank_callback.c | 8 +- src/nvidia/src/kernel/gpu/eng_state.c | 24 +- .../arch/kepler/kern_gsync_p2060.c | 34 +- .../src/kernel/gpu/external_device/gsync.c | 22 +- .../external_device/kern_external_device.c | 1 + .../src/kernel/gpu/falcon/kernel_falcon.c | 30 +- .../kernel/gpu/falcon/kernel_falcon_ctrl.c | 4 +- .../gpu/fifo/arch/hopper/kernel_fifo_gh100.c | 1 + .../fifo/arch/maxwell/kernel_channel_gm107.c | 5 +- .../gpu/fifo/arch/maxwell/kernel_fifo_gm107.c | 56 +- .../arch/volta/kernel_channel_group_gv100.c | 3 +- .../src/kernel/gpu/fifo/kernel_channel.c | 119 +- src/nvidia/src/kernel/gpu/fifo/kernel_fifo.c | 64 +- .../src/kernel/gpu/fifo/kernel_sched_mgr.c | 4 +- src/nvidia/src/kernel/gpu/fifo/usermode_api.c | 67 +- .../kernel/gpu/fifo/uvm_channel_retainer.c | 17 +- .../gpu/fsp/arch/hopper/kern_fsp_gh100.c | 22 +- src/nvidia/src/kernel/gpu/fsp/kern_fsp.c | 10 +- src/nvidia/src/kernel/gpu/gpu.c | 440 +- src/nvidia/src/kernel/gpu/gpu_engine_type.c | 7 +- src/nvidia/src/kernel/gpu/gpu_fabric_probe.c | 70 +- src/nvidia/src/kernel/gpu/gpu_gspclient.c | 7 +- src/nvidia/src/kernel/gpu/gpu_registry.c | 25 +- src/nvidia/src/kernel/gpu/gpu_resource.c | 22 +- src/nvidia/src/kernel/gpu/gpu_rmapi.c | 123 +- src/nvidia/src/kernel/gpu/gpu_suspend.c | 1 + .../src/kernel/gpu/gpu_user_shared_data.c | 206 +- .../kernel/gpu/gr/arch/ampere/kgrmgr_ga100.c | 48 + .../gpu/gr/arch/maxwell/kgraphics_gm200.c | 30 +- .../gpu/gr/arch/pascal/kgraphics_gp100.c | 9 +- .../gpu/gr/arch/turing/kgraphics_tu102.c | 7 +- .../src/kernel/gpu/gr/fecs_event_list.c | 127 +- .../src/kernel/gpu/gr/kernel_graphics.c | 74 +- .../kernel/gpu/gr/kernel_graphics_context.c | 124 +- .../kernel/gpu/gr/kernel_graphics_manager.c | 144 +- .../kernel/gpu/gr/kernel_graphics_object.c | 20 +- .../gpu/gr/kernel_sm_debugger_session.c | 17 +- .../gpu/gr/kernel_sm_debugger_session_ctrl.c | 9 +- .../gpu/gsp/arch/ampere/kernel_gsp_ga102.c | 21 +- .../gpu/gsp/arch/hopper/kernel_gsp_gh100.c | 4 +- .../gpu/gsp/arch/turing/kernel_gsp_tu102.c | 35 +- src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c | 255 +- .../src/kernel/gpu/gsp/kernel_gsp_booter.c | 5 +- .../src/kernel/gpu/gsp/kernel_gsp_fwsec.c | 9 +- .../src/kernel/gpu/gsp/message_queue_cpu.c | 8 +- .../gpu/hwpm/profiler_v2/kern_profiler_v2.c | 12 +- .../hwpm/profiler_v2/kern_profiler_v2_ctrl.c | 3 +- src/nvidia/src/kernel/gpu/intr/intr.c | 68 +- src/nvidia/src/kernel/gpu/kern_gpu_power.c | 51 +- .../gpu/mem_mgr/arch/ampere/mem_mgr_ga100.c | 17 +- .../gpu/mem_mgr/arch/maxwell/fbsr_gm107.c | 63 +- .../mem_mgr/arch/maxwell/mem_mgr_cmn_gm107.c | 110 + .../gpu/mem_mgr/arch/maxwell/mem_mgr_gm107.c | 133 +- .../mem_mgr/arch/maxwell/mem_utils_gm107.c | 256 +- .../arch/maxwell/virt_mem_allocator_gm107.c | 40 +- .../mem_mgr/arch/pascal/mem_mgr_scrub_gp100.c | 92 +- src/nvidia/src/kernel/gpu/mem_mgr/ce_utils.c | 42 +- .../src/kernel/gpu/mem_mgr/channel_utils.c | 140 +- .../src/kernel/gpu/mem_mgr/context_dma.c | 17 +- src/nvidia/src/kernel/gpu/mem_mgr/dma.c | 10 +- src/nvidia/src/kernel/gpu/mem_mgr/fbsr.c | 15 +- src/nvidia/src/kernel/gpu/mem_mgr/heap.c | 74 +- src/nvidia/src/kernel/gpu/mem_mgr/mem_ctrl.c | 28 +- src/nvidia/src/kernel/gpu/mem_mgr/mem_desc.c | 313 +- src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c | 355 +- .../src/kernel/gpu/mem_mgr/mem_mgr_ctrl.c | 5 +- .../kernel/gpu/mem_mgr/mem_mgr_gsp_client.c | 17 +- .../src/kernel/gpu/mem_mgr/mem_mgr_pwr_mgmt.c | 54 +- .../src/kernel/gpu/mem_mgr/mem_mgr_regions.c | 1 - src/nvidia/src/kernel/gpu/mem_mgr/mem_scrub.c | 2 +- src/nvidia/src/kernel/gpu/mem_mgr/mem_utils.c | 163 +- .../kernel/gpu/mem_mgr/method_notification.c | 36 +- .../gpu/mem_mgr/phys_mem_allocator/numa.c | 55 +- .../phys_mem_allocator/phys_mem_allocator.c | 4 +- .../phys_mem_allocator_util.c | 64 +- src/nvidia/src/kernel/gpu/mem_mgr/sem_surf.c | 6 +- .../src/kernel/gpu/mem_mgr/vaspace_api.c | 108 +- .../mem_sys/arch/ampere/kern_mem_sys_ga100.c | 5 +- .../mem_sys/arch/hopper/kern_mem_sys_gh100.c | 25 +- .../mem_sys/arch/maxwell/kern_mem_sys_gm107.c | 8 +- .../src/kernel/gpu/mem_sys/kern_mem_sys.c | 79 +- .../kernel/gpu/mem_sys/kern_mem_sys_ctrl.c | 84 +- .../mig_mgr/compute_instance_subscription.c | 9 +- .../gpu/mig_mgr/gpu_instance_subscription.c | 57 +- .../kernel/gpu/mig_mgr/kernel_mig_manager.c | 642 +- .../gpu/mmu/arch/ampere/kern_gmmu_ga100.c | 10 +- .../gpu/mmu/arch/hopper/kern_gmmu_gh100.c | 5 +- .../gpu/mmu/arch/maxwell/kern_gmmu_gm107.c | 2 +- src/nvidia/src/kernel/gpu/mmu/bar2_walk.c | 6 +- src/nvidia/src/kernel/gpu/mmu/gmmu_trace.c | 6 +- src/nvidia/src/kernel/gpu/mmu/gmmu_walk.c | 9 +- src/nvidia/src/kernel/gpu/mmu/kern_gmmu.c | 22 +- src/nvidia/src/kernel/gpu/mmu/uvm_sw.c | 7 - .../kernel/gpu/nvdec/kernel_nvdec_engdesc.c | 2 +- .../nvlink/arch/hopper/kernel_nvlink_gh100.c | 22 +- .../nvlink/arch/pascal/kernel_nvlink_gp100.c | 25 + .../src/kernel/gpu/nvlink/common_nvlinkapi.c | 13 +- .../src/kernel/gpu/nvlink/kernel_nvlink.c | 77 +- .../kernel/gpu/nvlink/kernel_nvlinkcorelib.c | 95 +- .../gpu/nvlink/kernel_nvlinkcorelibcallback.c | 7 +- .../gpu/nvlink/kernel_nvlinkcorelibtrain.c | 12 +- .../gpu/nvlink/kernel_nvlinkoverrides.c | 10 + .../src/kernel/gpu/ofa/kernel_ofa_engdesc.c | 110 + .../kernel/gpu/perf/kern_perf_gpuboostsync.c | 1 + .../src/kernel/gpu/perf/kern_perf_pwr.c | 5 +- src/nvidia/src/kernel/gpu/pmu/kern_pmu.c | 34 + src/nvidia/src/kernel/gpu/rc/kernel_rc.c | 7 + .../src/kernel/gpu/rc/kernel_rc_callback.c | 36 +- .../kernel/gpu/rc/kernel_rc_notification.c | 26 +- .../src/kernel/gpu/rc/kernel_rc_watchdog.c | 1 + .../gpu/sec2/arch/hopper/kernel_sec2_gh100.c | 4 +- .../kernel/gpu/spdm/arch/hopper/spdm_gh100.c | 4 +- .../src/kernel/gpu/subdevice/generic_engine.c | 10 + .../src/kernel/gpu/subdevice/subdevice.c | 39 +- .../subdevice/subdevice_ctrl_event_kernel.c | 2 +- .../gpu/subdevice/subdevice_ctrl_gpu_kernel.c | 29 +- .../subdevice/subdevice_ctrl_timer_kernel.c | 2 +- src/nvidia/src/kernel/gpu/timed_semaphore.c | 16 +- src/nvidia/src/kernel/gpu/timer/timer.c | 27 +- .../src/kernel/gpu/uvm/arch/volta/uvm_gv100.c | 5 +- .../kernel/gpu/video/kernel_video_engine.c | 183 + src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c | 356 +- src/nvidia/src/kernel/mem_mgr/console_mem.c | 7 - src/nvidia/src/kernel/mem_mgr/ctx_buf_pool.c | 6 +- src/nvidia/src/kernel/mem_mgr/egm_mem.c | 6 +- .../src/kernel/mem_mgr/fabric_vaspace.c | 19 +- src/nvidia/src/kernel/mem_mgr/gpu_vaspace.c | 68 +- src/nvidia/src/kernel/mem_mgr/mem.c | 25 +- src/nvidia/src/kernel/mem_mgr/mem_fabric.c | 44 +- src/nvidia/src/kernel/mem_mgr/mem_list.c | 31 +- .../src/kernel/mem_mgr/mem_multicast_fabric.c | 639 +- src/nvidia/src/kernel/mem_mgr/os_desc_mem.c | 2 +- src/nvidia/src/kernel/mem_mgr/phys_mem.c | 98 +- src/nvidia/src/kernel/mem_mgr/system_mem.c | 44 +- src/nvidia/src/kernel/mem_mgr/vaspace.c | 84 +- src/nvidia/src/kernel/mem_mgr/video_mem.c | 82 +- src/nvidia/src/kernel/mem_mgr/virtual_mem.c | 47 +- src/nvidia/src/kernel/os/os_init.c | 22 - src/nvidia/src/kernel/os/os_stubs.c | 116 +- .../src/kernel/platform/chipset/chipset.c | 5 +- .../kernel/platform/chipset/chipset_info.c | 11 +- .../kernel/platform/chipset/chipset_pcie.c | 44 +- src/nvidia/src/kernel/platform/cpu.c | 22 +- .../src/kernel/platform/nbsi/nbsi_getv.c | 4 +- .../src/kernel/platform/nbsi/nbsi_init.c | 74 +- src/nvidia/src/kernel/platform/p2p/p2p_caps.c | 53 +- .../platform/platform_request_handler.c | 39 +- .../platform/platform_request_handler_ctrl.c | 11 +- src/nvidia/src/kernel/platform/sli/sli.c | 24 +- src/nvidia/src/kernel/power/gpu_boost_mgr.c | 3 + src/nvidia/src/kernel/rmapi/alloc_free.c | 148 +- src/nvidia/src/kernel/rmapi/client.c | 43 +- src/nvidia/src/kernel/rmapi/client_resource.c | 59 +- src/nvidia/src/kernel/rmapi/control.c | 31 +- .../src/kernel/rmapi/embedded_param_copy.c | 2 +- src/nvidia/src/kernel/rmapi/event.c | 6 +- .../src/kernel/rmapi/event_notification.c | 10 +- src/nvidia/src/kernel/rmapi/mapping.c | 20 +- src/nvidia/src/kernel/rmapi/mapping_cpu.c | 35 +- src/nvidia/src/kernel/rmapi/nv_gpu_ops.c | 324 +- .../src/kernel/rmapi/resource_desc_flags.h | 38 +- src/nvidia/src/kernel/rmapi/resource_list.h | 22 +- src/nvidia/src/kernel/rmapi/rmapi.c | 237 +- src/nvidia/src/kernel/rmapi/sharing.c | 35 +- .../kernel/virtualization/common_vgpu_mgr.c | 6 +- .../virtualization/hypervisor/hypervisor.c | 3 +- src/nvidia/src/libraries/containers/list.c | 11 +- src/nvidia/src/libraries/containers/map.c | 14 +- src/nvidia/src/libraries/containers/vector.c | 27 +- .../eventbuffer/eventbufferproducer.c | 28 +- src/nvidia/src/libraries/mmu/mmu_walk.c | 302 +- .../src/libraries/mmu/mmu_walk_private.h | 57 +- .../src/libraries/nvbitvector/nvbitvector.c | 84 +- src/nvidia/src/libraries/nvoc/src/runtime.c | 8 +- .../libraries/nvport/memory/memory_tracking.c | 4 +- .../src/libraries/resserv/src/rs_server.c | 29 +- src/nvidia/src/libraries/utils/nvassert.c | 37 +- src/nvidia/srcs.mk | 7 + utils.mk | 15 + version.mk | 2 +- 917 files changed, 132395 insertions(+), 109930 deletions(-) create mode 100644 kernel-open/common/inc/nv-chardev-numbers.h rename kernel-open/{nvidia/nv-frontend.h => common/inc/nv-kthread-q-os.h} (54%) create mode 100644 kernel-open/nvidia-drm/nv-kthread-q.c create mode 100644 kernel-open/nvidia-uvm/uvm_processors.c delete mode 100644 kernel-open/nvidia/nv-frontend.c create mode 100644 src/common/inc/swref/published/ampere/ga102/dev_nv_pcfg_xve_regmap.h create mode 100644 src/common/inc/swref/published/disp/v02_04/dev_disp.h create mode 100644 src/common/inc/swref/published/disp/v05_01/dev_disp.h create mode 100644 src/common/inc/swref/published/maxwell/gm107/dev_nv_pcfg_xve1_addendum.h create mode 100644 src/common/inc/swref/published/maxwell/gm107/dev_nv_pcfg_xve_addendum.h create mode 100644 src/common/inc/swref/published/pascal/gp100/dev_ctxsw_prog.h create mode 100644 src/common/inc/swref/published/turing/tu102/dev_ctxsw_prog.h create mode 100644 src/common/inc/swref/published/turing/tu102/dev_nv_pcfg_xve_regmap.h create mode 100644 src/common/modeset/timing/nvt_ovt.c create mode 100644 src/common/nvlink/kernel/nvlink/interface/nvlink_kern_device_mgmt_entry.c create mode 100644 src/common/sdk/nvidia/inc/class/cl00e0.h create mode 100644 src/common/sdk/nvidia/inc/class/cl90cdvideo.h rename src/{nvidia/inc/kernel/os/os_fixed_mode_timings_props.h => common/sdk/nvidia/inc/class/cl90e7.h} (65%) create mode 100644 src/common/sdk/nvidia/inc/ctrl/ctrl00de.h create mode 100644 src/common/sdk/nvidia/inc/ctrl/ctrl90e7.h create mode 100644 src/nvidia-modeset/include/nvkms-ctxdma.h create mode 100644 src/nvidia-modeset/include/nvkms-evo3.h create mode 100644 src/nvidia-modeset/src/nvkms-ctxdma.c create mode 100644 src/nvidia/arch/nvalloc/unix/include/nv-chardev-numbers.h rename src/nvidia/arch/nvalloc/unix/include/{nv-ioctl-nvlog.h => nv-ioctl-lockless-diag.h} (92%) create mode 100644 src/nvidia/arch/nvalloc/unix/include/nv-ioctl-numa.h create mode 100644 src/nvidia/generated/g_kernel_video_engine_nvoc.c create mode 100644 src/nvidia/generated/g_kernel_video_engine_nvoc.h create mode 100644 src/nvidia/inc/kernel/gpu/fifo/engine_info.h create mode 100644 src/nvidia/inc/kernel/gpu/video/kernel_video_engine.h create mode 100644 src/nvidia/inc/kernel/gpuvideo/video_event.h create mode 100644 src/nvidia/inc/libraries/utils/nvprintf_level.h create mode 100644 src/nvidia/src/kernel/gpu/bif/arch/ampere/kernel_bif_ga102.c create mode 100644 src/nvidia/src/kernel/gpu/gr/arch/ampere/kgrmgr_ga100.c create mode 100644 src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_cmn_gm107.c create mode 100644 src/nvidia/src/kernel/gpu/ofa/kernel_ofa_engdesc.c create mode 100644 src/nvidia/src/kernel/gpu/video/kernel_video_engine.c diff --git a/CHANGELOG.md b/CHANGELOG.md index 886cef2ab2..101ee02c5b 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,5 +1,17 @@ # Changelog +## Release 545 Entries + +### [545.23.06] 2023-10-17 + +#### Fixed + +- Fix always-false conditional, [#493](https://github.com/NVIDIA/open-gpu-kernel-modules/pull/493) by @meme8383 + +#### Added + +- Added beta-quality support for GeForce and Workstation GPUs. Please see the "Open Linux Kernel Modules" chapter in the NVIDIA GPU driver end user README for details. + ## Release 535 Entries ### [535.113.01] 2023-09-21 diff --git a/README.md b/README.md index 0191813fa3..fc94273542 100644 --- a/README.md +++ b/README.md @@ -1,7 +1,7 @@ # NVIDIA Linux Open GPU Kernel Module Source This is the source release of the NVIDIA Linux open GPU kernel modules, -version 535.113.01. +version 545.23.06. ## How to Build @@ -17,7 +17,7 @@ as root: Note that the kernel modules built here must be used with GSP firmware and user-space NVIDIA GPU driver components from a corresponding -535.113.01 driver release. This can be achieved by installing +545.23.06 driver release. This can be achieved by installing the NVIDIA GPU driver from the .run file using the `--no-kernel-modules` option. E.g., @@ -179,16 +179,16 @@ software applications. ## Compatible GPUs -The open-gpu-kernel-modules can be used on any Turing or later GPU -(see the table below). However, in the 535.113.01 release, -GeForce and Workstation support is still considered alpha-quality. +The NVIDIA open kernel modules can be used on any Turing or later GPU +(see the table below). However, in the __DRIVER_VERION__ release, GeForce and +Workstation support is considered to be Beta quality. The open kernel modules +are suitable for broad usage, and NVIDIA requests feedback on any issues +encountered specific to them. -To enable use of the open kernel modules on GeForce and Workstation GPUs, -set the "NVreg_OpenRmEnableUnsupportedGpus" nvidia.ko kernel module -parameter to 1. For more details, see the NVIDIA GPU driver end user -README here: +For details on feature support and limitations, see the NVIDIA GPU driver +end user README here: -https://us.download.nvidia.com/XFree86/Linux-x86_64/535.113.01/README/kernel_open.html +https://us.download.nvidia.com/XFree86/Linux-x86_64/545.23.06/README/kernel_open.html In the below table, if three IDs are listed, the first is the PCI Device ID, the second is the PCI Subsystem Vendor ID, and the third is the PCI diff --git a/kernel-open/Kbuild b/kernel-open/Kbuild index 4489ec3b30..75a9ab165f 100644 --- a/kernel-open/Kbuild +++ b/kernel-open/Kbuild @@ -72,12 +72,24 @@ EXTRA_CFLAGS += -I$(src)/common/inc EXTRA_CFLAGS += -I$(src) EXTRA_CFLAGS += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-error -Wno-format-extra-args EXTRA_CFLAGS += -D__KERNEL__ -DMODULE -DNVRM -EXTRA_CFLAGS += -DNV_VERSION_STRING=\"535.113.01\" +EXTRA_CFLAGS += -DNV_VERSION_STRING=\"545.23.06\" ifneq ($(SYSSRCHOST1X),) EXTRA_CFLAGS += -I$(SYSSRCHOST1X) endif +# Some Android kernels prohibit driver use of filesystem functions like +# filp_open() and kernel_read(). Disable the NV_FILESYSTEM_ACCESS_AVAILABLE +# functionality that uses those functions when building for Android. + +PLATFORM_IS_ANDROID ?= 0 + +ifeq ($(PLATFORM_IS_ANDROID),1) + EXTRA_CFLAGS += -DNV_FILESYSTEM_ACCESS_AVAILABLE=0 +else + EXTRA_CFLAGS += -DNV_FILESYSTEM_ACCESS_AVAILABLE=1 +endif + EXTRA_CFLAGS += -Wno-unused-function ifneq ($(NV_BUILD_TYPE),debug) @@ -92,7 +104,6 @@ endif ifeq ($(NV_BUILD_TYPE),debug) EXTRA_CFLAGS += -g - EXTRA_CFLAGS += $(call cc-option,-gsplit-dwarf,) endif EXTRA_CFLAGS += -ffreestanding @@ -214,6 +225,7 @@ $(obj)/conftest/patches.h: $(NV_CONFTEST_SCRIPT) NV_HEADER_PRESENCE_TESTS = \ asm/system.h \ drm/drmP.h \ + drm/drm_aperture.h \ drm/drm_auth.h \ drm/drm_gem.h \ drm/drm_crtc.h \ @@ -224,6 +236,7 @@ NV_HEADER_PRESENCE_TESTS = \ drm/drm_encoder.h \ drm/drm_atomic_uapi.h \ drm/drm_drv.h \ + drm/drm_fbdev_generic.h \ drm/drm_framebuffer.h \ drm/drm_connector.h \ drm/drm_probe_helper.h \ @@ -257,6 +270,7 @@ NV_HEADER_PRESENCE_TESTS = \ linux/sched/task_stack.h \ xen/ioemu.h \ linux/fence.h \ + linux/dma-fence.h \ linux/dma-resv.h \ soc/tegra/chip-id.h \ soc/tegra/fuse.h \ @@ -302,6 +316,7 @@ NV_HEADER_PRESENCE_TESTS = \ linux/mdev.h \ soc/tegra/bpmp-abi.h \ soc/tegra/bpmp.h \ + linux/sync_file.h \ linux/cc_platform.h \ asm/cpufeature.h diff --git a/kernel-open/common/inc/nv-chardev-numbers.h b/kernel-open/common/inc/nv-chardev-numbers.h new file mode 100644 index 0000000000..54ca547e08 --- /dev/null +++ b/kernel-open/common/inc/nv-chardev-numbers.h @@ -0,0 +1,43 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _NV_CHARDEV_NUMBERS_H_ +#define _NV_CHARDEV_NUMBERS_H_ + +// NVIDIA's reserved major character device number (Linux). +#define NV_MAJOR_DEVICE_NUMBER 195 + +// Minor numbers 0 to 247 reserved for regular devices +#define NV_MINOR_DEVICE_NUMBER_REGULAR_MAX 247 + +// Minor numbers 248 to 253 currently unused + +// Minor number 254 reserved for the modeset device (provided by NVKMS) +#define NV_MINOR_DEVICE_NUMBER_MODESET_DEVICE 254 + +// Minor number 255 reserved for the control device +#define NV_MINOR_DEVICE_NUMBER_CONTROL_DEVICE 255 + +#endif // _NV_CHARDEV_NUMBERS_H_ + diff --git a/kernel-open/common/inc/nv-ioctl-numa.h b/kernel-open/common/inc/nv-ioctl-numa.h index 1d456ec953..0af52675d5 100644 --- a/kernel-open/common/inc/nv-ioctl-numa.h +++ b/kernel-open/common/inc/nv-ioctl-numa.h @@ -25,14 +25,12 @@ #ifndef NV_IOCTL_NUMA_H #define NV_IOCTL_NUMA_H -#if defined(NV_LINUX) - #include -#if defined(NV_KERNEL_INTERFACE_LAYER) - +#if defined(NV_KERNEL_INTERFACE_LAYER) && defined(NV_LINUX) #include - +#elif defined (NV_KERNEL_INTERFACE_LAYER) && defined(NV_BSD) +#include #else #include @@ -81,5 +79,3 @@ typedef struct nv_ioctl_set_numa_status #define NV_IOCTL_NUMA_STATUS_OFFLINE_FAILED 6 #endif - -#endif diff --git a/kernel-open/nvidia/nv-frontend.h b/kernel-open/common/inc/nv-kthread-q-os.h similarity index 54% rename from kernel-open/nvidia/nv-frontend.h rename to kernel-open/common/inc/nv-kthread-q-os.h index 1ce72a0b00..3ab3f5623d 100644 --- a/kernel-open/nvidia/nv-frontend.h +++ b/kernel-open/common/inc/nv-kthread-q-os.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2012-2013 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2016 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,27 +21,42 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef _NV_FRONTEND_H_ -#define _NV_FRONTEND_H_ +#ifndef __NV_KTHREAD_QUEUE_OS_H__ +#define __NV_KTHREAD_QUEUE_OS_H__ -#include "nvtypes.h" -#include "nv-linux.h" -#include "nv-register-module.h" +#include // atomic_t +#include // list +#include // task_struct +#include // NUMA_NO_NODE +#include -#define NV_MAX_MODULE_INSTANCES 8 +#include "conftest.h" -#define NV_FRONTEND_MINOR_NUMBER(x) minor((x)->i_rdev) +struct nv_kthread_q +{ + struct list_head q_list_head; + spinlock_t q_lock; -#define NV_FRONTEND_CONTROL_DEVICE_MINOR_MAX 255 -#define NV_FRONTEND_CONTROL_DEVICE_MINOR_MIN (NV_FRONTEND_CONTROL_DEVICE_MINOR_MAX - \ - NV_MAX_MODULE_INSTANCES) + // This is a counting semaphore. It gets incremented and decremented + // exactly once for each item that is added to the queue. + struct semaphore q_sem; + atomic_t main_loop_should_exit; -#define NV_FRONTEND_IS_CONTROL_DEVICE(x) ((x <= NV_FRONTEND_CONTROL_DEVICE_MINOR_MAX) && \ - (x > NV_FRONTEND_CONTROL_DEVICE_MINOR_MIN)) + struct task_struct *q_kthread; +}; -int nvidia_frontend_add_device(nvidia_module_t *, nv_linux_state_t *); -int nvidia_frontend_remove_device(nvidia_module_t *, nv_linux_state_t *); +struct nv_kthread_q_item +{ + struct list_head q_list_node; + nv_q_func_t function_to_run; + void *function_args; +}; -extern nvidia_module_t *nv_minor_num_table[]; + +#ifndef NUMA_NO_NODE +#define NUMA_NO_NODE (-1) +#endif + +#define NV_KTHREAD_NO_NODE NUMA_NO_NODE #endif diff --git a/kernel-open/common/inc/nv-kthread-q.h b/kernel-open/common/inc/nv-kthread-q.h index 0b364d7cc9..a278ca57dc 100644 --- a/kernel-open/common/inc/nv-kthread-q.h +++ b/kernel-open/common/inc/nv-kthread-q.h @@ -24,13 +24,14 @@ #ifndef __NV_KTHREAD_QUEUE_H__ #define __NV_KTHREAD_QUEUE_H__ -#include // atomic_t -#include // list -#include // task_struct -#include // NUMA_NO_NODE -#include +struct nv_kthread_q; +struct nv_kthread_q_item; +typedef struct nv_kthread_q nv_kthread_q_t; +typedef struct nv_kthread_q_item nv_kthread_q_item_t; + +typedef void (*nv_q_func_t)(void *args); -#include "conftest.h" +#include "nv-kthread-q-os.h" //////////////////////////////////////////////////////////////////////////////// // nv_kthread_q: @@ -85,38 +86,6 @@ // //////////////////////////////////////////////////////////////////////////////// -typedef struct nv_kthread_q nv_kthread_q_t; -typedef struct nv_kthread_q_item nv_kthread_q_item_t; - -typedef void (*nv_q_func_t)(void *args); - -struct nv_kthread_q -{ - struct list_head q_list_head; - spinlock_t q_lock; - - // This is a counting semaphore. It gets incremented and decremented - // exactly once for each item that is added to the queue. - struct semaphore q_sem; - atomic_t main_loop_should_exit; - - struct task_struct *q_kthread; -}; - -struct nv_kthread_q_item -{ - struct list_head q_list_node; - nv_q_func_t function_to_run; - void *function_args; -}; - - -#ifndef NUMA_NO_NODE -#define NUMA_NO_NODE (-1) -#endif - -#define NV_KTHREAD_NO_NODE NUMA_NO_NODE - // // The queue must not be used before calling this routine. // @@ -155,10 +124,7 @@ int nv_kthread_q_init_on_node(nv_kthread_q_t *q, // This routine is the same as nv_kthread_q_init_on_node() with the exception // that the queue stack will be allocated on the NUMA node of the caller. // -static inline int nv_kthread_q_init(nv_kthread_q_t *q, const char *qname) -{ - return nv_kthread_q_init_on_node(q, qname, NV_KTHREAD_NO_NODE); -} +int nv_kthread_q_init(nv_kthread_q_t *q, const char *qname); // // The caller is responsible for stopping all queues, by calling this routine diff --git a/kernel-open/common/inc/nv-linux.h b/kernel-open/common/inc/nv-linux.h index fd6f99d161..d46d1123ee 100644 --- a/kernel-open/common/inc/nv-linux.h +++ b/kernel-open/common/inc/nv-linux.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2001-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -248,7 +248,7 @@ NV_STATUS nvos_forward_error_to_cray(struct pci_dev *, NvU32, #undef NV_SET_PAGES_UC_PRESENT #endif -#if !defined(NVCPU_AARCH64) && !defined(NVCPU_PPC64LE) +#if !defined(NVCPU_AARCH64) && !defined(NVCPU_PPC64LE) && !defined(NVCPU_RISCV64) #if !defined(NV_SET_MEMORY_UC_PRESENT) && !defined(NV_SET_PAGES_UC_PRESENT) #error "This driver requires the ability to change memory types!" #endif @@ -430,6 +430,11 @@ extern NvBool nvos_is_chipset_io_coherent(void); #define CACHE_FLUSH() asm volatile("sync; \n" \ "isync; \n" ::: "memory") #define WRITE_COMBINE_FLUSH() CACHE_FLUSH() +#elif defined(NVCPU_RISCV64) +#define CACHE_FLUSH() mb() +#define WRITE_COMBINE_FLUSH() CACHE_FLUSH() +#else +#error "CACHE_FLUSH() and WRITE_COMBINE_FLUSH() need to be defined for this architecture." #endif typedef enum @@ -440,7 +445,7 @@ typedef enum NV_MEMORY_TYPE_DEVICE_MMIO, /* All kinds of MMIO referred by NVRM e.g. BARs and MCFG of device */ } nv_memory_type_t; -#if defined(NVCPU_AARCH64) || defined(NVCPU_PPC64LE) +#if defined(NVCPU_AARCH64) || defined(NVCPU_PPC64LE) || defined(NVCPU_RISCV64) #define NV_ALLOW_WRITE_COMBINING(mt) 1 #elif defined(NVCPU_X86_64) #if defined(NV_ENABLE_PAT_SUPPORT) @@ -753,7 +758,6 @@ static inline dma_addr_t nv_phys_to_dma(struct device *dev, NvU64 pa) #define NV_VMA_FILE(vma) ((vma)->vm_file) #define NV_DEVICE_MINOR_NUMBER(x) minor((x)->i_rdev) -#define NV_CONTROL_DEVICE_MINOR 255 #define NV_PCI_DISABLE_DEVICE(pci_dev) \ { \ @@ -1646,20 +1650,11 @@ typedef struct nvidia_event nv_event_t event; } nvidia_event_t; -typedef enum -{ - NV_FOPS_STACK_INDEX_MMAP, - NV_FOPS_STACK_INDEX_IOCTL, - NV_FOPS_STACK_INDEX_COUNT -} nvidia_entry_point_index_t; - typedef struct { nv_file_private_t nvfp; nvidia_stack_t *sp; - nvidia_stack_t *fops_sp[NV_FOPS_STACK_INDEX_COUNT]; - struct semaphore fops_sp_lock[NV_FOPS_STACK_INDEX_COUNT]; nv_alloc_t *free_list; void *nvptr; nvidia_event_t *event_data_head, *event_data_tail; @@ -1689,28 +1684,6 @@ static inline nv_linux_file_private_t *nv_get_nvlfp_from_nvfp(nv_file_private_t #define NV_STATE_PTR(nvl) &(((nv_linux_state_t *)(nvl))->nv_state) -static inline nvidia_stack_t *nv_nvlfp_get_sp(nv_linux_file_private_t *nvlfp, nvidia_entry_point_index_t which) -{ -#if defined(NVCPU_X86_64) - if (rm_is_altstack_in_use()) - { - down(&nvlfp->fops_sp_lock[which]); - return nvlfp->fops_sp[which]; - } -#endif - return NULL; -} - -static inline void nv_nvlfp_put_sp(nv_linux_file_private_t *nvlfp, nvidia_entry_point_index_t which) -{ -#if defined(NVCPU_X86_64) - if (rm_is_altstack_in_use()) - { - up(&nvlfp->fops_sp_lock[which]); - } -#endif -} - #define NV_ATOMIC_READ(data) atomic_read(&(data)) #define NV_ATOMIC_SET(data,val) atomic_set(&(data), (val)) #define NV_ATOMIC_INC(data) atomic_inc(&(data)) diff --git a/kernel-open/common/inc/nv-pgprot.h b/kernel-open/common/inc/nv-pgprot.h index 581e97f3ae..5054997c65 100644 --- a/kernel-open/common/inc/nv-pgprot.h +++ b/kernel-open/common/inc/nv-pgprot.h @@ -119,6 +119,13 @@ static inline pgprot_t pgprot_modify_writecombine(pgprot_t old_prot) #define NV_PGPROT_WRITE_COMBINED(old_prot) old_prot #define NV_PGPROT_READ_ONLY(old_prot) \ __pgprot(pgprot_val((old_prot)) & ~NV_PAGE_RW) +#elif defined(NVCPU_RISCV64) +#define NV_PGPROT_WRITE_COMBINED_DEVICE(old_prot) \ + pgprot_writecombine(old_prot) +/* Don't attempt to mark sysmem pages as write combined on riscv */ +#define NV_PGPROT_WRITE_COMBINED(old_prot) old_prot +#define NV_PGPROT_READ_ONLY(old_prot) \ + __pgprot(pgprot_val((old_prot)) & ~_PAGE_WRITE) #else /* Writecombine is not supported */ #undef NV_PGPROT_WRITE_COMBINED_DEVICE(old_prot) diff --git a/kernel-open/common/inc/nv-proto.h b/kernel-open/common/inc/nv-proto.h index 815107d259..580d12a5cd 100644 --- a/kernel-open/common/inc/nv-proto.h +++ b/kernel-open/common/inc/nv-proto.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -25,10 +25,8 @@ #define _NV_PROTO_H_ #include "nv-pci.h" -#include "nv-register-module.h" extern const char *nv_device_name; -extern nvidia_module_t nv_fops; void nv_acpi_register_notifier (nv_linux_state_t *); void nv_acpi_unregister_notifier (nv_linux_state_t *); @@ -86,7 +84,7 @@ void nv_shutdown_adapter(nvidia_stack_t *, nv_state_t *, nv_linux_state void nv_dev_free_stacks(nv_linux_state_t *); NvBool nv_lock_init_locks(nvidia_stack_t *, nv_state_t *); void nv_lock_destroy_locks(nvidia_stack_t *, nv_state_t *); -void nv_linux_add_device_locked(nv_linux_state_t *); +int nv_linux_add_device_locked(nv_linux_state_t *); void nv_linux_remove_device_locked(nv_linux_state_t *); NvBool nv_acpi_power_resource_method_present(struct pci_dev *); diff --git a/kernel-open/common/inc/nv.h b/kernel-open/common/inc/nv.h index 44a1515e39..f3f32ee88b 100644 --- a/kernel-open/common/inc/nv.h +++ b/kernel-open/common/inc/nv.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -42,6 +42,7 @@ #include #include #include +#include #include extern nv_cap_t *nvidia_caps_root; @@ -50,9 +51,6 @@ extern const NvBool nv_is_rm_firmware_supported_os; #include -/* NVIDIA's reserved major character device number (Linux). */ -#define NV_MAJOR_DEVICE_NUMBER 195 - #define GPU_UUID_LEN (16) /* @@ -478,8 +476,6 @@ typedef struct nv_state_t /* Bool to check if dma-buf is supported */ NvBool dma_buf_supported; - NvBool printed_openrm_enable_unsupported_gpus_error; - /* Check if NVPCF DSM function is implemented under NVPCF or GPU device scope */ NvBool nvpcf_dsm_in_gpu_scope; @@ -505,6 +501,7 @@ struct nv_file_private_t NvHandle *handles; NvU16 maxHandles; NvU32 deviceInstance; + NvU32 gpuInstanceId; NvU8 metadata[64]; nv_file_private_t *ctl_nvfp; @@ -765,7 +762,7 @@ nv_state_t* NV_API_CALL nv_get_ctl_state (void); void NV_API_CALL nv_set_dma_address_size (nv_state_t *, NvU32 ); NV_STATUS NV_API_CALL nv_alias_pages (nv_state_t *, NvU32, NvU32, NvU32, NvU64, NvU64 *, void **); -NV_STATUS NV_API_CALL nv_alloc_pages (nv_state_t *, NvU32, NvBool, NvU32, NvBool, NvBool, NvS32, NvU64 *, void **); +NV_STATUS NV_API_CALL nv_alloc_pages (nv_state_t *, NvU32, NvU64, NvBool, NvU32, NvBool, NvBool, NvS32, NvU64 *, void **); NV_STATUS NV_API_CALL nv_free_pages (nv_state_t *, NvU32, NvBool, NvU32, void *); NV_STATUS NV_API_CALL nv_register_user_pages (nv_state_t *, NvU64, NvU64 *, void *, void **); @@ -981,7 +978,7 @@ NV_STATUS NV_API_CALL rm_dma_buf_dup_mem_handle (nvidia_stack_t *, nv_state_t void NV_API_CALL rm_dma_buf_undup_mem_handle(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle); NV_STATUS NV_API_CALL rm_dma_buf_map_mem_handle (nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvU64, NvU64, void *, nv_phys_addr_range_t **, NvU32 *); void NV_API_CALL rm_dma_buf_unmap_mem_handle(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvU64, nv_phys_addr_range_t **, NvU32); -NV_STATUS NV_API_CALL rm_dma_buf_get_client_and_device(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle *, NvHandle *, NvHandle *, void **, NvBool *); +NV_STATUS NV_API_CALL rm_dma_buf_get_client_and_device(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvHandle *, NvHandle *, NvHandle *, void **, NvBool *); void NV_API_CALL rm_dma_buf_put_client_and_device(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvHandle, void *); NV_STATUS NV_API_CALL rm_log_gpu_crash (nv_stack_t *, nv_state_t *); @@ -993,7 +990,7 @@ NvBool NV_API_CALL rm_gpu_need_4k_page_isolation(nv_state_t *); NvBool NV_API_CALL rm_is_chipset_io_coherent(nv_stack_t *); NvBool NV_API_CALL rm_init_event_locks(nvidia_stack_t *, nv_state_t *); void NV_API_CALL rm_destroy_event_locks(nvidia_stack_t *, nv_state_t *); -NV_STATUS NV_API_CALL rm_get_gpu_numa_info(nvidia_stack_t *, nv_state_t *, NvS32 *, NvU64 *, NvU64 *, NvU64 *, NvU32 *); +NV_STATUS NV_API_CALL rm_get_gpu_numa_info(nvidia_stack_t *, nv_state_t *, nv_ioctl_numa_info_t *); NV_STATUS NV_API_CALL rm_gpu_numa_online(nvidia_stack_t *, nv_state_t *); NV_STATUS NV_API_CALL rm_gpu_numa_offline(nvidia_stack_t *, nv_state_t *); NvBool NV_API_CALL rm_is_device_sequestered(nvidia_stack_t *, nv_state_t *); @@ -1008,7 +1005,7 @@ void NV_API_CALL rm_cleanup_dynamic_power_management(nvidia_stack_t *, nv_ void NV_API_CALL rm_enable_dynamic_power_management(nvidia_stack_t *, nv_state_t *); NV_STATUS NV_API_CALL rm_ref_dynamic_power(nvidia_stack_t *, nv_state_t *, nv_dynamic_power_mode_t); void NV_API_CALL rm_unref_dynamic_power(nvidia_stack_t *, nv_state_t *, nv_dynamic_power_mode_t); -NV_STATUS NV_API_CALL rm_transition_dynamic_power(nvidia_stack_t *, nv_state_t *, NvBool); +NV_STATUS NV_API_CALL rm_transition_dynamic_power(nvidia_stack_t *, nv_state_t *, NvBool, NvBool *); const char* NV_API_CALL rm_get_vidmem_power_status(nvidia_stack_t *, nv_state_t *); const char* NV_API_CALL rm_get_dynamic_power_management_status(nvidia_stack_t *, nv_state_t *); const char* NV_API_CALL rm_get_gpu_gcx_support(nvidia_stack_t *, nv_state_t *, NvBool); @@ -1023,7 +1020,8 @@ NV_STATUS NV_API_CALL nv_vgpu_create_request(nvidia_stack_t *, nv_state_t *, c NV_STATUS NV_API_CALL nv_vgpu_delete(nvidia_stack_t *, const NvU8 *, NvU16); NV_STATUS NV_API_CALL nv_vgpu_get_type_ids(nvidia_stack_t *, nv_state_t *, NvU32 *, NvU32 *, NvBool, NvU8, NvBool); NV_STATUS NV_API_CALL nv_vgpu_get_type_info(nvidia_stack_t *, nv_state_t *, NvU32, char *, int, NvU8); -NV_STATUS NV_API_CALL nv_vgpu_get_bar_info(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU64 *, NvU32, void *); +NV_STATUS NV_API_CALL nv_vgpu_get_bar_info(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU64 *, NvU32, void *, NvBool *); +NV_STATUS NV_API_CALL nv_vgpu_get_hbm_info(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU64 *, NvU64 *); NV_STATUS NV_API_CALL nv_vgpu_start(nvidia_stack_t *, const NvU8 *, void *, NvS32 *, NvU8 *, NvU32); NV_STATUS NV_API_CALL nv_vgpu_get_sparse_mmap(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU64 **, NvU64 **, NvU32 *); NV_STATUS NV_API_CALL nv_vgpu_process_vf_info(nvidia_stack_t *, nv_state_t *, NvU8, NvU32, NvU8, NvU8, NvU8, NvBool, void *); diff --git a/kernel-open/common/inc/nv_speculation_barrier.h b/kernel-open/common/inc/nv_speculation_barrier.h index 20b32bdaf0..b78fbf0d3e 100644 --- a/kernel-open/common/inc/nv_speculation_barrier.h +++ b/kernel-open/common/inc/nv_speculation_barrier.h @@ -86,7 +86,7 @@ /* Not currently implemented for MSVC/ARM64. See bug 3366890. */ # define nv_speculation_barrier() # define speculation_barrier() nv_speculation_barrier() -#elif defined(NVCPU_NVRISCV64) && NVOS_IS_LIBOS +#elif defined(NVCPU_IS_RISCV64) # define nv_speculation_barrier() #else #error "Unknown compiler/chip family" diff --git a/kernel-open/common/inc/nv_uvm_types.h b/kernel-open/common/inc/nv_uvm_types.h index d4e935c084..4cdbf9db3a 100644 --- a/kernel-open/common/inc/nv_uvm_types.h +++ b/kernel-open/common/inc/nv_uvm_types.h @@ -104,6 +104,10 @@ typedef struct UvmGpuMemoryInfo_tag // Out: Set to TRUE, if the allocation is in sysmem. NvBool sysmem; + // Out: Set to TRUE, if this allocation is treated as EGM. + // sysmem is also TRUE when egm is TRUE. + NvBool egm; + // Out: Set to TRUE, if the allocation is a constructed // under a Device or Subdevice. // All permutations of sysmem and deviceDescendant are valid. @@ -125,6 +129,8 @@ typedef struct UvmGpuMemoryInfo_tag // Out: Uuid of the GPU to which the allocation belongs. // This is only valid if deviceDescendant is NV_TRUE. + // When egm is NV_TRUE, this is also the UUID of the GPU + // for which EGM is local. // Note: If the allocation is owned by a device in // an SLI group and the allocation is broadcast // across the SLI group, this UUID will be any one @@ -332,7 +338,7 @@ typedef struct UvmGpuPagingChannelAllocParams_tag // The max number of Copy Engines supported by a GPU. // The gpu ops build has a static assert that this is the correct number. -#define UVM_COPY_ENGINE_COUNT_MAX 10 +#define UVM_COPY_ENGINE_COUNT_MAX 64 typedef struct { @@ -566,11 +572,8 @@ typedef struct UvmPlatformInfo_tag // Out: ATS (Address Translation Services) is supported NvBool atsSupported; - // Out: True if HW trusted execution, such as AMD's SEV-SNP or Intel's TDX, - // is enabled in the VM, indicating that Confidential Computing must be - // also enabled in the GPU(s); these two security features are either both - // enabled, or both disabled. - NvBool confComputingEnabled; + // Out: AMD SEV (Secure Encrypted Virtualization) is enabled + NvBool sevEnabled; } UvmPlatformInfo; typedef struct UvmGpuClientInfo_tag @@ -683,6 +686,10 @@ typedef struct UvmGpuInfo_tag // to NVSwitch peers. NvBool connectedToSwitch; NvU64 nvswitchMemoryWindowStart; + + // local EGM properties + NvBool egmEnabled; + NvU8 egmPeerId; } UvmGpuInfo; typedef struct UvmGpuFbInfo_tag diff --git a/kernel-open/common/inc/nvkms-api-types.h b/kernel-open/common/inc/nvkms-api-types.h index 7131b32b8a..f56195c193 100644 --- a/kernel-open/common/inc/nvkms-api-types.h +++ b/kernel-open/common/inc/nvkms-api-types.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -45,6 +45,11 @@ #define NVKMS_DEVICE_ID_TEGRA 0x0000ffff +#define NVKMS_MAX_SUPERFRAME_VIEWS 4 + +#define NVKMS_LOG2_LUT_ARRAY_SIZE 10 +#define NVKMS_LUT_ARRAY_SIZE (1 << NVKMS_LOG2_LUT_ARRAY_SIZE) + typedef NvU32 NvKmsDeviceHandle; typedef NvU32 NvKmsDispHandle; typedef NvU32 NvKmsConnectorHandle; @@ -179,6 +184,14 @@ enum NvKmsEventType { NVKMS_EVENT_TYPE_FLIP_OCCURRED, }; +enum NvKmsFlipResult { + NV_KMS_FLIP_RESULT_SUCCESS = 0, /* Success */ + NV_KMS_FLIP_RESULT_INVALID_PARAMS, /* Parameter validation failed */ + NV_KMS_FLIP_RESULT_IN_PROGRESS, /* Flip would fail because an outstanding + flip containing changes that cannot be + queued is in progress */ +}; + typedef enum { NV_EVO_SCALER_1TAP = 0, NV_EVO_SCALER_2TAPS = 1, @@ -221,6 +234,16 @@ struct NvKmsUsageBounds { } layer[NVKMS_MAX_LAYERS_PER_HEAD]; }; +/*! + * Per-component arrays of NvU16s describing the LUT; used for both the input + * LUT and output LUT. + */ +struct NvKmsLutRamps { + NvU16 red[NVKMS_LUT_ARRAY_SIZE]; /*! in */ + NvU16 green[NVKMS_LUT_ARRAY_SIZE]; /*! in */ + NvU16 blue[NVKMS_LUT_ARRAY_SIZE]; /*! in */ +}; + /* * A 3x4 row-major colorspace conversion matrix. * @@ -531,6 +554,18 @@ typedef struct { NvBool noncoherent; } NvKmsDispIOCoherencyModes; +enum NvKmsInputColorRange { + /* + * If DEFAULT is provided, driver will assume full range for RGB formats + * and limited range for YUV formats. + */ + NVKMS_INPUT_COLORRANGE_DEFAULT = 0, + + NVKMS_INPUT_COLORRANGE_LIMITED = 1, + + NVKMS_INPUT_COLORRANGE_FULL = 2, +}; + enum NvKmsInputColorSpace { /* Unknown colorspace; no de-gamma will be applied */ NVKMS_INPUT_COLORSPACE_NONE = 0, @@ -542,6 +577,12 @@ enum NvKmsInputColorSpace { NVKMS_INPUT_COLORSPACE_BT2100_PQ = 2, }; +enum NvKmsOutputColorimetry { + NVKMS_OUTPUT_COLORIMETRY_DEFAULT = 0, + + NVKMS_OUTPUT_COLORIMETRY_BT2100 = 1, +}; + enum NvKmsOutputTf { /* * NVKMS itself won't apply any OETF (clients are still @@ -552,6 +593,17 @@ enum NvKmsOutputTf { NVKMS_OUTPUT_TF_PQ = 2, }; +/*! + * EOTF Data Byte 1 as per CTA-861-G spec. + * This is expected to match exactly with the spec. + */ +enum NvKmsInfoFrameEOTF { + NVKMS_INFOFRAME_EOTF_SDR_GAMMA = 0, + NVKMS_INFOFRAME_EOTF_HDR_GAMMA = 1, + NVKMS_INFOFRAME_EOTF_ST2084 = 2, + NVKMS_INFOFRAME_EOTF_HLG = 3, +}; + /*! * HDR Static Metadata Type1 Descriptor as per CEA-861.3 spec. * This is expected to match exactly with the spec. @@ -605,4 +657,29 @@ struct NvKmsHDRStaticMetadata { NvU16 maxFALL; }; +/*! + * A superframe is made of two or more video streams that are combined in + * a specific way. A DP serializer (an external device connected to a Tegra + * ARM SOC over DP or HDMI) can receive a video stream comprising multiple + * videos combined into a single frame and then split it into multiple + * video streams. The following structure describes the number of views + * and dimensions of each view inside a superframe. + */ +struct NvKmsSuperframeInfo { + NvU8 numViews; + struct { + /* x offset inside superframe at which this view starts */ + NvU16 x; + + /* y offset inside superframe at which this view starts */ + NvU16 y; + + /* Horizontal active width in pixels for this view */ + NvU16 width; + + /* Vertical active height in lines for this view */ + NvU16 height; + } view[NVKMS_MAX_SUPERFRAME_VIEWS]; +}; + #endif /* NVKMS_API_TYPES_H */ diff --git a/kernel-open/common/inc/nvkms-kapi.h b/kernel-open/common/inc/nvkms-kapi.h index cf0c2a5902..c487b4b786 100644 --- a/kernel-open/common/inc/nvkms-kapi.h +++ b/kernel-open/common/inc/nvkms-kapi.h @@ -49,6 +49,8 @@ struct NvKmsKapiDevice; struct NvKmsKapiMemory; struct NvKmsKapiSurface; struct NvKmsKapiChannelEvent; +struct NvKmsKapiSemaphoreSurface; +struct NvKmsKapiSemaphoreSurfaceCallback; typedef NvU32 NvKmsKapiConnector; typedef NvU32 NvKmsKapiDisplay; @@ -67,6 +69,14 @@ typedef NvU32 NvKmsKapiDisplay; */ typedef void NvKmsChannelEventProc(void *dataPtr, NvU32 dataU32); +/* + * Note: Same as above, this function must not call back into NVKMS-KAPI, nor + * directly into RM. Doing so could cause deadlocks given the notification + * function will most likely be called from within RM's interrupt handler + * callchain. + */ +typedef void NvKmsSemaphoreSurfaceCallbackProc(void *pData); + /** @} */ /** @@ -126,6 +136,11 @@ struct NvKmsKapiDeviceResourcesInfo { NvU32 validCursorCompositionModes; NvU64 supportedCursorSurfaceMemoryFormats; + struct { + NvU64 maxSubmittedOffset; + NvU64 stride; + } semsurf; + struct { NvU16 validRRTransforms; NvU32 validCompositionModes; @@ -218,8 +233,10 @@ struct NvKmsKapiLayerConfig { struct NvKmsRRParams rrParams; struct NvKmsKapiSyncpt syncptParams; - struct NvKmsHDRStaticMetadata hdrMetadata; - NvBool hdrMetadataSpecified; + struct { + struct NvKmsHDRStaticMetadata val; + NvBool enabled; + } hdrMetadata; enum NvKmsOutputTf tf; @@ -233,16 +250,21 @@ struct NvKmsKapiLayerConfig { NvU16 dstWidth, dstHeight; enum NvKmsInputColorSpace inputColorSpace; + struct NvKmsCscMatrix csc; + NvBool cscUseMain; }; struct NvKmsKapiLayerRequestedConfig { struct NvKmsKapiLayerConfig config; struct { - NvBool surfaceChanged : 1; - NvBool srcXYChanged : 1; - NvBool srcWHChanged : 1; - NvBool dstXYChanged : 1; - NvBool dstWHChanged : 1; + NvBool surfaceChanged : 1; + NvBool srcXYChanged : 1; + NvBool srcWHChanged : 1; + NvBool dstXYChanged : 1; + NvBool dstWHChanged : 1; + NvBool cscChanged : 1; + NvBool tfChanged : 1; + NvBool hdrMetadataChanged : 1; } flags; }; @@ -286,14 +308,41 @@ struct NvKmsKapiHeadModeSetConfig { struct NvKmsKapiDisplayMode mode; NvBool vrrEnabled; + + struct { + NvBool enabled; + enum NvKmsInfoFrameEOTF eotf; + struct NvKmsHDRStaticMetadata staticMetadata; + } hdrInfoFrame; + + enum NvKmsOutputColorimetry colorimetry; + + struct { + struct { + NvBool specified; + NvU32 depth; + NvU32 start; + NvU32 end; + struct NvKmsLutRamps *pRamps; + } input; + + struct { + NvBool specified; + NvBool enabled; + struct NvKmsLutRamps *pRamps; + } output; + } lut; }; struct NvKmsKapiHeadRequestedConfig { struct NvKmsKapiHeadModeSetConfig modeSetConfig; struct { - NvBool activeChanged : 1; - NvBool displaysChanged : 1; - NvBool modeChanged : 1; + NvBool activeChanged : 1; + NvBool displaysChanged : 1; + NvBool modeChanged : 1; + NvBool hdrInfoFrameChanged : 1; + NvBool colorimetryChanged : 1; + NvBool lutChanged : 1; } flags; struct NvKmsKapiCursorRequestedConfig cursorRequestedConfig; @@ -318,6 +367,7 @@ struct NvKmsKapiHeadReplyConfig { }; struct NvKmsKapiModeSetReplyConfig { + enum NvKmsFlipResult flipResult; struct NvKmsKapiHeadReplyConfig headReplyConfig[NVKMS_KAPI_MAX_HEADS]; }; @@ -434,6 +484,12 @@ enum NvKmsKapiAllocationType { NVKMS_KAPI_ALLOCATION_TYPE_OFFSCREEN = 2, }; +typedef enum NvKmsKapiRegisterWaiterResultRec { + NVKMS_KAPI_REG_WAITER_FAILED, + NVKMS_KAPI_REG_WAITER_SUCCESS, + NVKMS_KAPI_REG_WAITER_ALREADY_SIGNALLED, +} NvKmsKapiRegisterWaiterResult; + struct NvKmsKapiFunctionsTable { /*! @@ -519,8 +575,8 @@ struct NvKmsKapiFunctionsTable { ); /*! - * Revoke permissions previously granted. Only one (dispIndex, head, - * display) is currently supported. + * Revoke modeset permissions previously granted. Only one (dispIndex, + * head, display) is currently supported. * * \param [in] device A device returned by allocateDevice(). * @@ -537,6 +593,34 @@ struct NvKmsKapiFunctionsTable { NvKmsKapiDisplay display ); + /*! + * Grant modeset sub-owner permissions to fd. This is used by clients to + * convert drm 'master' permissions into nvkms sub-owner permission. + * + * \param [in] fd fd from opening /dev/nvidia-modeset. + * + * \param [in] device A device returned by allocateDevice(). + * + * \return NV_TRUE on success, NV_FALSE on failure. + */ + NvBool (*grantSubOwnership) + ( + NvS32 fd, + struct NvKmsKapiDevice *device + ); + + /*! + * Revoke sub-owner permissions previously granted. + * + * \param [in] device A device returned by allocateDevice(). + * + * \return NV_TRUE on success, NV_FALSE on failure. + */ + NvBool (*revokeSubOwnership) + ( + struct NvKmsKapiDevice *device + ); + /*! * Registers for notification, via * NvKmsKapiAllocateDeviceParams::eventCallback, of the events specified @@ -1122,6 +1206,199 @@ struct NvKmsKapiFunctionsTable { NvP64 dmaBuf, NvU32 limit); + /*! + * Import a semaphore surface allocated elsewhere to NVKMS and return a + * handle to the new object. + * + * \param [in] device A device allocated using allocateDevice(). + * + * \param [in] nvKmsParamsUser Userspace pointer to driver-specific + * parameters describing the semaphore + * surface being imported. + * + * \param [in] nvKmsParamsSize Size of the driver-specific parameter + * struct. + * + * \param [out] pSemaphoreMap Returns a CPU mapping of the semaphore + * surface's semaphore memory to the client. + * + * \param [out] pMaxSubmittedMap Returns a CPU mapping of the semaphore + * surface's semaphore memory to the client. + * + * \return struct NvKmsKapiSemaphoreSurface* on success, NULL on failure. + */ + struct NvKmsKapiSemaphoreSurface* (*importSemaphoreSurface) + ( + struct NvKmsKapiDevice *device, + NvU64 nvKmsParamsUser, + NvU64 nvKmsParamsSize, + void **pSemaphoreMap, + void **pMaxSubmittedMap + ); + + /*! + * Free an imported semaphore surface. + * + * \param [in] device The device passed to + * importSemaphoreSurface() when creating + * semaphoreSurface. + * + * \param [in] semaphoreSurface A semaphore surface returned by + * importSemaphoreSurface(). + */ + void (*freeSemaphoreSurface) + ( + struct NvKmsKapiDevice *device, + struct NvKmsKapiSemaphoreSurface *semaphoreSurface + ); + + /*! + * Register a callback to be called when a semaphore reaches a value. + * + * The callback will be called when the semaphore at index in + * semaphoreSurface reaches the value wait_value. The callback will + * be called at most once and is automatically unregistered when called. + * It may also be unregistered (i.e., cancelled) explicitly using the + * unregisterSemaphoreSurfaceCallback() function. To avoid leaking the + * memory used to track the registered callback, callers must ensure one + * of these methods of unregistration is used for every successful + * callback registration that returns a non-NULL pCallbackHandle. + * + * \param [in] device The device passed to + * importSemaphoreSurface() when creating + * semaphoreSurface. + * + * \param [in] semaphoreSurface A semaphore surface returned by + * importSemaphoreSurface(). + * + * \param [in] pCallback A pointer to the function to call when + * the specified value is reached. NULL + * means no callback. + * + * \param [in] pData Arbitrary data to be passed back to the + * callback as its sole parameter. + * + * \param [in] index The index of the semaphore within + * semaphoreSurface. + * + * \param [in] wait_value The value the semaphore must reach or + * exceed before the callback is called. + * + * \param [in] new_value The value the semaphore will be set to + * when it reaches or exceeds . + * 0 means do not update the value. + * + * \param [out] pCallbackHandle On success, the value pointed to will + * contain an opaque handle to the + * registered callback that may be used to + * cancel it if needed. Unused if pCallback + * is NULL. + * + * \return NVKMS_KAPI_REG_WAITER_SUCCESS if the waiter was registered or if + * no callback was requested and the semaphore at has + * already reached or exceeded + * + * NVKMS_KAPI_REG_WAITER_ALREADY_SIGNALLED if a callback was + * requested and the semaphore at has already reached or + * exceeded + * + * NVKMS_KAPI_REG_WAITER_FAILED if waiter registration failed. + */ + NvKmsKapiRegisterWaiterResult + (*registerSemaphoreSurfaceCallback) + ( + struct NvKmsKapiDevice *device, + struct NvKmsKapiSemaphoreSurface *semaphoreSurface, + NvKmsSemaphoreSurfaceCallbackProc *pCallback, + void *pData, + NvU64 index, + NvU64 wait_value, + NvU64 new_value, + struct NvKmsKapiSemaphoreSurfaceCallback **pCallbackHandle + ); + + /*! + * Unregister a callback registered via registerSemaphoreSurfaceCallback() + * + * If the callback has not yet been called, this function will cancel the + * callback and free its associated resources. + * + * Note this function treats the callback handle as a pointer. While this + * function does not dereference that pointer itself, the underlying call + * to RM does within a properly guarded critical section that first ensures + * it is not in the process of being used within a callback. This means + * the callstack must take into consideration that pointers are not in + * general unique handles if they may have been freed, since a subsequent + * malloc could return the same pointer value at that point. This callchain + * avoids that by leveraging the behavior of the underlying RM APIs: + * + * 1) A callback handle is referenced relative to its corresponding + * (semaphore surface, index, wait_value) tuple here and within RM. It + * is not a valid handle outside of that scope. + * + * 2) A callback can not be registered against an already-reached value + * for a given semaphore surface index. + * + * 3) A given callback handle can not be registered twice against the same + * (semaphore surface, index, wait_value) tuple, so unregistration will + * never race with registration at the RM level, and would only race at + * a higher level if used incorrectly. Since this is kernel code, we + * can safely assume there won't be malicious clients purposely misuing + * the API, but the burden is placed on the caller to ensure its usage + * does not lead to races at higher levels. + * + * These factors considered together ensure any valid registered handle is + * either still in the relevant waiter list and refers to the same event/ + * callback as when it was registered, or has been removed from the list + * as part of a critical section that also destroys the list itself and + * makes future lookups in that list impossible, and hence eliminates the + * chance of comparing a stale handle with a new handle of the same value + * as part of a lookup. + * + * \param [in] device The device passed to + * importSemaphoreSurface() when creating + * semaphoreSurface. + * + * \param [in] semaphoreSurface The semaphore surface passed to + * registerSemaphoreSurfaceCallback() when + * registering the callback. + * + * \param [in] index The index passed to + * registerSemaphoreSurfaceCallback() when + * registering the callback. + * + * \param [in] wait_value The wait_value passed to + * registerSemaphoreSurfaceCallback() when + * registering the callback. + * + * \param [in] callbackHandle The callback handle returned by + * registerSemaphoreSurfaceCallback(). + */ + NvBool + (*unregisterSemaphoreSurfaceCallback) + ( + struct NvKmsKapiDevice *device, + struct NvKmsKapiSemaphoreSurface *semaphoreSurface, + NvU64 index, + NvU64 wait_value, + struct NvKmsKapiSemaphoreSurfaceCallback *callbackHandle + ); + + /*! + * Update the value of a semaphore surface from the CPU. + * + * Update the semaphore value at the specified index from the CPU, then + * wake up any pending CPU waiters associated with that index that are + * waiting on it reaching a value <= the new value. + */ + NvBool + (*setSemaphoreSurfaceValue) + ( + struct NvKmsKapiDevice *device, + struct NvKmsKapiSemaphoreSurface *semaphoreSurface, + NvU64 index, + NvU64 new_value + ); }; /** @} */ diff --git a/kernel-open/common/inc/os-interface.h b/kernel-open/common/inc/os-interface.h index 5249e124e5..ffbf4e1f5a 100644 --- a/kernel-open/common/inc/os-interface.h +++ b/kernel-open/common/inc/os-interface.h @@ -162,7 +162,7 @@ NvBool NV_API_CALL os_is_vgx_hyper (void); NV_STATUS NV_API_CALL os_inject_vgx_msi (NvU16, NvU64, NvU32); NvBool NV_API_CALL os_is_grid_supported (void); NvU32 NV_API_CALL os_get_grid_csp_support (void); -void NV_API_CALL os_get_screen_info (NvU64 *, NvU16 *, NvU16 *, NvU16 *, NvU16 *, NvU64, NvU64); +void NV_API_CALL os_get_screen_info (NvU64 *, NvU32 *, NvU32 *, NvU32 *, NvU32 *, NvU64, NvU64); void NV_API_CALL os_bug_check (NvU32, const char *); NV_STATUS NV_API_CALL os_lock_user_pages (void *, NvU64, void **, NvU32); NV_STATUS NV_API_CALL os_lookup_user_io_memory (void *, NvU64, NvU64 **, void**); @@ -230,12 +230,14 @@ extern NvBool os_dma_buf_enabled; * --------------------------------------------------------------------------- */ -#define NV_DBG_INFO 0x0 -#define NV_DBG_SETUP 0x1 -#define NV_DBG_USERERRORS 0x2 +#define NV_DBG_INFO 0x1 +#define NV_DBG_SETUP 0x2 #define NV_DBG_WARNINGS 0x3 #define NV_DBG_ERRORS 0x4 +#define NV_DBG_HW_ERRORS 0x5 +#define NV_DBG_FATAL 0x6 +#define NV_DBG_FORCE_LEVEL(level) ((level) | (1 << 8)) void NV_API_CALL out_string(const char *str); int NV_API_CALL nv_printf(NvU32 debuglevel, const char *printf_format, ...); diff --git a/kernel-open/conftest.sh b/kernel-open/conftest.sh index 99b9e38952..f36e1f4d14 100755 --- a/kernel-open/conftest.sh +++ b/kernel-open/conftest.sh @@ -316,7 +316,7 @@ export_symbol_present_conftest() { SYMBOL="$1" TAB=' ' - if grep -e "${TAB}${SYMBOL}${TAB}.*${TAB}EXPORT_SYMBOL.*\$" \ + if grep -e "${TAB}${SYMBOL}${TAB}.*${TAB}EXPORT_SYMBOL\(_GPL\)\?\s*\$" \ "$OUTPUT/Module.symvers" >/dev/null 2>&1; then echo "#define NV_IS_EXPORT_SYMBOL_PRESENT_$SYMBOL 1" | append_conftest "symbols" @@ -337,7 +337,7 @@ export_symbol_gpl_conftest() { SYMBOL="$1" TAB=' ' - if grep -e "${TAB}${SYMBOL}${TAB}.*${TAB}EXPORT_\(UNUSED_\)*SYMBOL_GPL\$" \ + if grep -e "${TAB}${SYMBOL}${TAB}.*${TAB}EXPORT_\(UNUSED_\)*SYMBOL_GPL\s*\$" \ "$OUTPUT/Module.symvers" >/dev/null 2>&1; then echo "#define NV_IS_EXPORT_SYMBOL_GPL_$SYMBOL 1" | append_conftest "symbols" @@ -549,10 +549,8 @@ compile_test() { # Determine if the set_pages_array_uc() function is present. # It does not exist on all architectures. # - # set_pages_array_uc() was added by commit - # 0f3507555f6fa4acbc85a646d6e8766230db38fc ("x86, CPA: Add - # set_pages_arrayuc and set_pages_array_wb") in v2.6.30-rc1 (Thu Mar - # 19 14:51:15 2009) + # Added by commit 0f3507555f6f ("x86, CPA: Add set_pages_arrayuc + # and set_pages_array_wb") in v2.6.30. # CODE=" #include @@ -597,8 +595,8 @@ compile_test() { # # Added by commit 3c299dc22635 ("PCI: add # pci_get_domain_bus_and_slot function") in 2.6.33 but aarch64 - # support was added by commit d1e6dc91b532 - # ("arm64: Add architectural support for PCI") in 3.18-rc1 + # support was added by commit d1e6dc91b532 ("arm64: Add + # architectural support for PCI") in 3.18. # CODE=" #include @@ -1242,26 +1240,6 @@ compile_test() { compile_check_conftest "$CODE" "NV_VFIO_DEVICE_GFX_PLANE_INFO_PRESENT" "" "types" ;; - vfio_device_migration_has_start_pfn) - # - # Determine if the 'vfio_device_migration_info' structure has - # a 'start_pfn' field. - # - # This member was present in proposed interface for vGPU Migration - # ("[PATCH v3 0/5] Add migration support for VFIO device ") - # https://lists.gnu.org/archive/html/qemu-devel/2019-02/msg05176.html - # which is not present in upstreamed commit a8a24f3f6e38 (vfio: UAPI - # for migration interface for device state) in v5.8 (2020-05-29) - # - CODE=" - #include - int conftest_vfio_device_migration_has_start_pfn(void) { - return offsetof(struct vfio_device_migration_info, start_pfn); - }" - - compile_check_conftest "$CODE" "NV_VFIO_DEVICE_MIGRATION_HAS_START_PFN" "" "types" - ;; - vfio_uninit_group_dev) # # Determine if vfio_uninit_group_dev() function is present or not. @@ -1411,9 +1389,8 @@ compile_test() { # # Determine if the pde_data() function is present. # - # The commit c28198889c15 removed the function - # 'PDE_DATA()', and replaced it with 'pde_data()' - # ("proc: remove PDE_DATA() completely") in v5.17-rc1. + # PDE_DATA() was replaced with pde_data() by commit 359745d78351 + # ("proc: remove PDE_DATA() completely") in v5.17. # CODE=" #include @@ -1554,8 +1531,8 @@ compile_test() { # based implementation") in v4.5 # # Commit 0a0f0d8be76d ("dma-mapping: split ") - # in v5.10-rc1 (2020-09-22), moved get_dma_ops() function - # prototype from to . + # in v5.10 moved get_dma_ops() function prototype from + # to . # CODE=" #if defined(NV_LINUX_DMA_MAP_OPS_H_PRESENT) @@ -1725,9 +1702,8 @@ compile_test() { kernel_write_has_pointer_pos_arg) # - # Determine the pos argument type, which was changed by - # commit e13ec939e96b1 (fs: fix kernel_write prototype) on - # 9/1/2017. + # Determine the pos argument type, which was changed by commit + # e13ec939e96b ("fs: fix kernel_write prototype") in v4.14. # echo "$CONFTEST_PREAMBLE #include @@ -1750,9 +1726,8 @@ compile_test() { kernel_read_has_pointer_pos_arg) # - # Determine the pos argument type, which was changed by - # commit bdd1d2d3d251c (fs: fix kernel_read prototype) on - # 9/1/2017. + # Determine the pos argument type, which was changed by commit + # bdd1d2d3d251 ("fs: fix kernel_read prototype") in v4.14. # echo "$CONFTEST_PREAMBLE #include @@ -1777,8 +1752,8 @@ compile_test() { # # Determine if vm_insert_pfn_prot function is present # - # Added by commit 1745cbc5d0de ("mm: Add vm_insert_pfn_prot()") in - # v3.16.59 + # Added by commit 1745cbc5d0de ("mm: Add vm_insert_pfn_prot()") + # in v4.6. # # Removed by commit f5e6d1d5f8f3 ("mm: introduce # vmf_insert_pfn_prot()") in v4.20. @@ -1995,7 +1970,7 @@ compile_test() { # attached drivers") in v3.14 (2013-12-11) # # The commit 57bb1ee60340 ("drm: Compile out legacy chunks from - # struct drm_device") compiles out the legacy chunks like + # struct drm_device") in v5.11 compiles out the legacy chunks like # drm_driver::legacy_dev_list. # CODE=" @@ -2018,14 +1993,14 @@ compile_test() { # # Determine if jiffies_to_timespec() is present # - # removed by commit 751addac78b6 - # ("y2038: remove obsolete jiffies conversion functions") - # in v5.6-rc1 (2019-12-13). - CODE=" - #include - void conftest_jiffies_to_timespec(void){ - jiffies_to_timespec(); - }" + # Removed by commit 751addac78b6 ("y2038: remove obsolete jiffies + # conversion functions") in v5.6. + # + CODE=" + #include + void conftest_jiffies_to_timespec(void){ + jiffies_to_timespec(); + }" compile_check_conftest "$CODE" "NV_JIFFIES_TO_TIMESPEC_PRESENT" "" "functions" ;; @@ -2035,14 +2010,21 @@ compile_test() { # drm_universal_plane_init() # drm_crtc_init_with_planes() # drm_encoder_init() - # have a 'name' argument, which was added by these commits: - # drm_universal_plane_init: 2015-12-09 b0b3b7951114315d65398c27648705ca1c322faa - # drm_crtc_init_with_planes: 2015-12-09 f98828769c8838f526703ef180b3088a714af2f9 - # drm_encoder_init: 2015-12-09 13a3d91f17a5f7ed2acd275d18b6acfdb131fb15 + # have a 'name' argument. + # + # drm_universal_plane_init was updated by commit b0b3b7951114 + # ("drm: Pass 'name' to drm_universal_plane_init()") in v4.5. + # + # drm_crtc_init_with_planes was updated by commit f98828769c88 + # ("drm: Pass 'name' to drm_crtc_init_with_planes()") in v4.5. # - # Additionally determine whether drm_universal_plane_init() has a - # 'format_modifiers' argument, which was added by: - # 2017-07-23 e6fc3b68558e4c6d8d160b5daf2511b99afa8814 + # drm_encoder_init was updated by commit 13a3d91f17a5 ("drm: Pass + # 'name' to drm_encoder_init()") in v4.5. + # + # Additionally, determine whether drm_universal_plane_init() has + # a 'format_modifiers' argument, which was added by commit + # e6fc3b68558e ("drm: Plumb modifiers through plane init") in + # v4.14. # CODE=" #if defined(NV_DRM_DRMP_H_PRESENT) @@ -2239,7 +2221,7 @@ compile_test() { # correction properties") in v4.6 (2016-03-08). # # Removed by commit f8ed34ac7b45 ("drm: drm_helper_crtc_enable_color_mgmt() - # => drm_crtc_enable_color_mgmt()") in v4.8-rc1 (2016-06-07). + # => drm_crtc_enable_color_mgmt()") in v4.8. # CODE=" #include @@ -2257,11 +2239,11 @@ compile_test() { # present. # # Added by commit f8ed34ac7b45 ("drm: drm_helper_crtc_enable_color_mgmt() - # => drm_crtc_enable_color_mgmt()") in v4.8-rc1 (2016-06-07), replacing + # => drm_crtc_enable_color_mgmt()") in v4.8, replacing # drm_helper_crtc_enable_color_mgmt(). # # Moved to drm_color_mgmt.[ch] by commit f1e2f66ce2d9 ("drm: Extract - # drm_color_mgmt.[hc]") in v4.9-rc1 (2016-09-22) + # drm_color_mgmt.[hc]") in v4.9. # CODE=" #if defined(NV_DRM_DRM_CRTC_H_PRESENT) @@ -2288,8 +2270,7 @@ compile_test() { # Accidentally moved to drm_atomic_state_helper.[ch] by commit # 9ef8a9dc4b21 ("drm: Extract drm_atomic_state_helper.[ch]") # and moved back to drm_atomic_helper.[ch] by commit 1d8224e790c7 - # ("drm: Fix up drm_atomic_state_helper.[hc] extraction") in - # v5.0-rc1 + # ("drm: Fix up drm_atomic_state_helper.[hc] extraction") in v5.0. # # Removed by commit 6ca2ab8086af ("drm: automatic legacy gamma # support") in v5.12 (2020-12-15) @@ -2353,8 +2334,8 @@ compile_test() { # # Added by commit 210647af897a ("PCI: Rename pci_remove_bus_device # to pci_stop_and_remove_bus_device") in v3.4 (2012-02-25) but - # aarch64 support was added by commit d1e6dc91b532 - # ("arm64: Add architectural support for PCI") in v3.18-rc1. + # aarch64 support was added by commit d1e6dc91b532 ("arm64: Add + # architectural support for PCI") in v3.18. # CODE=" #include @@ -2451,8 +2432,8 @@ compile_test() { # # Determine if the 'pci_dev' data type has a 'ats_enabled' member. # - # Added by commit d544d75ac96aa ("PCI: Embed ATS info directly - # into struct pci_dev") in v4.3-rc1 (2015-08-14) + # Added by commit d544d75ac96a ("PCI: Embed ATS info directly + # into struct pci_dev") in v4.3. # CODE=" #include @@ -2483,9 +2464,9 @@ compile_test() { # commit 768ae309a961 ("mm: replace get_user_pages() write/force # parameters with gup_flags") in v4.9 (2016-10-13) # - # Removed vmas parameter from get_user_pages() by commit 7bbf9c8c99 + # Removed vmas parameter from get_user_pages() by commit 54d020692b34 # ("mm/gup: remove unused vmas parameter from get_user_pages()") - # in linux-next, expected in v6.5-rc1 + # in v6.5. # # linux-4.4.168 cherry-picked commit 768ae309a961 without # c12d2da56d0e which is covered in Conftest #3. @@ -2653,11 +2634,11 @@ compile_test() { # # get_user_pages_remote() removed 'tsk' parameter by # commit 64019a2e467a ("mm/gup: remove task_struct pointer for - # all gup code") in v5.9-rc1 (2020-08-11). + # all gup code") in v5.9. # # Removed vmas parameter from get_user_pages_remote() by commit - # a4bde14d549 ("mm/gup: remove vmas parameter from get_user_pages_remote()") - # in linux-next, expected in v6.5-rc1 + # ca5e863233e8 ("mm/gup: remove vmas parameter from + # get_user_pages_remote()") in v6.5. # # @@ -2856,15 +2837,14 @@ compile_test() { # # Determine if the function pin_user_pages() is present. # Presence of pin_user_pages() also implies the presence of - # unpin-user_page(). Both were added in the v5.6-rc1 + # unpin-user_page(). # - # pin_user_pages() was added by commit eddb1c228f7951d399240 - # ("mm/gup: introduce pin_user_pages*() and FOLL_PIN") in - # v5.6-rc1 (2020-01-30) + # pin_user_pages() was added by commit eddb1c228f79 ("mm/gup: + # introduce pin_user_pages*() and FOLL_PIN") in v5.6. # # Removed vmas parameter from pin_user_pages() by commit - # 40896a02751("mm/gup: remove vmas parameter from pin_user_pages()") - # in linux-next, expected in v6.5-rc1 + # 4c630f307455 ("mm/gup: remove vmas parameter from + # pin_user_pages()") in v6.5. set_pin_user_pages_defines () { if [ "$1" = "" ]; then @@ -2929,13 +2909,13 @@ compile_test() { # ("mm/gup: introduce pin_user_pages*() and FOLL_PIN") # in v5.6 (2020-01-30) - # pin_user_pages_remote() removed 'tsk' parameter by - # commit 64019a2e467a ("mm/gup: remove task_struct pointer for - # all gup code") in v5.9-rc1 (2020-08-11). + # pin_user_pages_remote() removed 'tsk' parameter by commit + # 64019a2e467a ("mm/gup: remove task_struct pointer for all gup + # code") in v5.9. # # Removed unused vmas parameter from pin_user_pages_remote() by - # commit 83bcc2e132 ("mm/gup: remove unused vmas parameter from - # pin_user_pages_remote()") in linux-next, expected in v6.5-rc1 + # commit 0b295316b3a9 ("mm/gup: remove unused vmas parameter from + # pin_user_pages_remote()") in v6.5. # # This function sets the NV_PIN_USER_PAGES_REMOTE_* macros as per @@ -3098,8 +3078,8 @@ compile_test() { # # Determine if enable_apicv boolean is exported by kernel. # - # Added by commit fdf513e37a3bd ("KVM: x86: Use common 'enable_apicv' - # variable for both APICv and AVIC") + # Added by commit fdf513e37a3b ("KVM: x86: Use common + # 'enable_apicv' variable for both APICv and AVIC") in v5.14. # CODE=" $CONFTEST_PREAMBLE @@ -4027,9 +4007,8 @@ compile_test() { # Determine if drm_connector_attach_vrr_capable_property and # drm_connector_set_vrr_capable_property is present # - # Added by commit ba1b0f6c73d4ea1390f0d5381f715ffa20c75f09 ("drm: - # Add vrr_capable property to the drm connector") in v5.0-rc1 - # (2018-11-28) + # Added by commit ba1b0f6c73d4 ("drm: Add vrr_capable property to + # the drm connector") in v5.0. # CODE=" #if defined(NV_DRM_DRM_CONNECTOR_H_PRESENT) @@ -4339,16 +4318,21 @@ compile_test() { # with the logic of "functions" the presence of # *either*_alpha_property or _blend_mode_property would be enough # to cause NV_DRM_ALPHA_BLENDING_AVAILABLE to be defined. + + # drm_plane_create_alpha_property was added by commit + # ae0e28265e21 ("drm/blend: Add a generic alpha property") in + # v4.18. + # + # drm_plane_create_blend_mode_property was added by commit + # a5ec8332d428 ("drm: Add per-plane pixel blend mode property") + # in v4.20. # CODE=" #if defined(NV_DRM_DRM_BLEND_H_PRESENT) #include #endif void conftest_drm_alpha_blending_available(void) { - /* 2018-04-11 ae0e28265e216dad11d4cbde42fc15e92919af78 */ (void)drm_plane_create_alpha_property; - - /* 2018-08-23 a5ec8332d4280500544e316f76c04a7adc02ce03 */ (void)drm_plane_create_blend_mode_property; }" @@ -4359,10 +4343,10 @@ compile_test() { # # Determine if the DRM subsystem supports rotation. # - # drm_plane_create_rotation_property() was added on 2016-09-26 by - # d138dd3c0c70979215f3184cf36f95875e37932e (drm: Add support for - # optional per-plane rotation property) in linux kernel. Presence - # of it is sufficient to say that DRM subsystem support rotation. + # drm_plane_create_rotation_property() was added by commit + # d138dd3c0c70 ("drm: Add support for optional per-plane rotation + # property") in v4.10. Presence of it is sufficient to say that + # DRM subsystem support rotation. # CODE=" #if defined(NV_DRM_DRM_BLEND_H_PRESENT) @@ -4381,8 +4365,8 @@ compile_test() { # # The DRIVER_PRIME flag was added by commit 3248877ea179 (drm: # base prime/dma-buf support (v5)) in v3.4 (2011-11-25) and is - # removed by commit 0424fdaf883a (drm/prime: Actually remove - # DRIVER_PRIME everywhere) on 2019-06-17. + # removed by commit 0424fdaf883a ("drm/prime: Actually remove + # DRIVER_PRIME everywhere") in v5.4. # # DRIVER_PRIME definition moved from drmP.h to drm_drv.h by # commit 85e634bce01a (drm: Extract drm_drv.h) in v4.10 @@ -4415,10 +4399,10 @@ compile_test() { # # drm_connector_for_each_possible_encoder() is added by commit # 83aefbb887b5 (drm: Add drm_connector_for_each_possible_encoder()) - # in v4.19. The definition and prorotype is changed to take only - # two arguments connector and encoder, by commit 62afb4ad425a - # (drm/connector: Allow max possible encoders to attach to a - # connector) in v5.5rc1. + # in v4.19. The definition and prototype is changed to take only + # two arguments connector and encoder by commit 62afb4ad425a + # ("drm/connector: Allow max possible encoders to attach to a + # connector") in v5.5. # echo "$CONFTEST_PREAMBLE #if defined(NV_DRM_DRMP_H_PRESENT) @@ -4468,6 +4452,24 @@ compile_test() { compile_check_conftest "$CODE" "NV_MMU_NOTIFIER_OPS_HAS_INVALIDATE_RANGE" "" "types" ;; + mmu_notifier_ops_arch_invalidate_secondary_tlbs) + # + # Determine if the mmu_notifier_ops struct has the + # 'arch_invalidate_secondary_tlbs' member. + # + # struct mmu_notifier_ops.invalidate_range was renamed to + # arch_invalidate_secondary_tlbs by commit 1af5a8109904 + # ("mmu_notifiers: rename invalidate_range notifier") due to be + # added in v6.6 + CODE=" + #include + int conftest_mmu_notifier_ops_arch_invalidate_secondary_tlbs(void) { + return offsetof(struct mmu_notifier_ops, arch_invalidate_secondary_tlbs); + }" + + compile_check_conftest "$CODE" "NV_MMU_NOTIFIER_OPS_HAS_ARCH_INVALIDATE_SECONDARY_TLBS" "" "types" + ;; + drm_format_num_planes) # # Determine if drm_format_num_planes() function is present. @@ -4523,8 +4525,8 @@ compile_test() { # # Determine if the 'struct proc_ops' type is present. # - # Added by commit d56c0d45f0e2 ("proc: decouple proc from VFS with - # "struct proc_ops"") in 5.6-rc1 + # Added by commit d56c0d45f0e2 ("proc: decouple proc from VFS + # with "struct proc_ops"") in v5.6. # CODE=" #include @@ -4582,8 +4584,8 @@ compile_test() { # Determine if 'drm_crtc_state' structure has a # 'vrr_enabled' field. # - # Added by commit 1398958cfd8d331342d657d37151791dd7256b40 ("drm: - # Add vrr_enabled property to drm CRTC") in v5.0-rc1 (2018-11-28) + # Added by commit 1398958cfd8d ("drm: Add vrr_enabled property to + # drm CRTC") in v5.0. # CODE=" #if defined(NV_DRM_DRM_CRTC_H_PRESENT) @@ -4604,11 +4606,11 @@ compile_test() { # Added by commit fb7fcc96a86cf ("timekeeping: Standardize on # ktime_get_*() naming") in 4.18 (2018-04-27) # - CODE=" - #include - void conftest_ktime_get_raw_ts64(void){ - ktime_get_raw_ts64(); - }" + CODE=" + #include + void conftest_ktime_get_raw_ts64(void){ + ktime_get_raw_ts64(); + }" compile_check_conftest "$CODE" "NV_KTIME_GET_RAW_TS64_PRESENT" "" "functions" ;; @@ -4619,11 +4621,11 @@ compile_test() { # Added by commit d6d29896c665d ("timekeeping: Provide timespec64 # based interfaces") in 3.17 (2014-07-16) # - CODE=" - #include - void conftest_ktime_get_real_ts64(void){ - ktime_get_real_ts64(); - }" + CODE=" + #include + void conftest_ktime_get_real_ts64(void){ + ktime_get_real_ts64(); + }" compile_check_conftest "$CODE" "NV_KTIME_GET_REAL_TS64_PRESENT" "" "functions" ;; @@ -4643,8 +4645,9 @@ compile_test() { # -the "modifier[]" member of the AddFB2 ioctl's parameter # structure. # - # All these were added by commit e3eb3250d84e (drm: add support for - # tiled/compressed/etc modifier in addfb2) in 4.1-rc1 (2015-02-05). + # All these were added by commit e3eb3250d84e ("drm: add support + # for tiled/compressed/etc modifier in addfb2") in v4.1. + # CODE=" #include #include @@ -4664,11 +4667,11 @@ compile_test() { # Added by commit 361a3bf00582 ("time64: Add time64.h header and # define struct timespec64") in 3.17 (2014-07-16) # - CODE=" - #include + CODE=" + #include - struct timespec64 ts64; - " + struct timespec64 ts64; + " compile_check_conftest "$CODE" "NV_TIMESPEC64_PRESENT" "" "types" ;; @@ -4680,15 +4683,15 @@ compile_test() { # The third argument to __vmalloc, page protection # 'pgprot_t prot', was removed by commit 88dca4ca5a93 # (mm: remove the pgprot argument to __vmalloc) - # in v5.8-rc1 (2020-06-01). - CODE=" - #include - - void conftest_vmalloc_has_pgprot_t_arg(void) { - pgprot_t prot; - (void)__vmalloc(0, 0, prot); - }" + # in v5.8. + # + CODE=" + #include + void conftest_vmalloc_has_pgprot_t_arg(void) { + pgprot_t prot; + (void)__vmalloc(0, 0, prot); + }" compile_check_conftest "$CODE" "NV_VMALLOC_HAS_PGPROT_T_ARG" "" "types" ;; @@ -4699,7 +4702,8 @@ compile_test() { # # Kernel commit da1c55f1b272 ("mmap locking API: rename mmap_sem # to mmap_lock") replaced the field 'mmap_sem' by 'mmap_lock' - # in v5.8-rc1 (2020-06-08). + # in v5.8. + # CODE=" #include @@ -4789,9 +4793,9 @@ compile_test() { ;; pci_enable_atomic_ops_to_root) - # pci_enable_atomic_ops_to_root was added by - # commit 430a23689dea ("PCI: Add pci_enable_atomic_ops_to_root()") - # in v4.16-rc1 (2018-01-05) + # + # pci_enable_atomic_ops_to_root was added by commit 430a23689dea + # ("PCI: Add pci_enable_atomic_ops_to_root()") in v4.16. # CODE=" #include @@ -4808,11 +4812,11 @@ compile_test() { # Added by commit a7c3e901a46ff54c016d040847eda598a9e3e653 ("mm: # introduce kv[mz]alloc helpers") in v4.12 (2017-05-08). # - CODE=" - #include - void conftest_kvmalloc(void){ - kvmalloc(); - }" + CODE=" + #include + void conftest_kvmalloc(void){ + kvmalloc(); + }" compile_check_conftest "$CODE" "NV_KVMALLOC_PRESENT" "" "functions" ;; @@ -4821,12 +4825,11 @@ compile_test() { # # Determine if the function drm_gem_object_put_unlocked() is present. # - # In v5.9-rc1, commit 2f4dd13d4bb8 ("drm/gem: add - # drm_gem_object_put helper") removes drm_gem_object_put_unlocked() - # function and replace its definition by transient macro. Commit - # ab15d56e27be ("drm: remove transient - # drm_gem_object_put_unlocked()") finally removes - # drm_gem_object_put_unlocked() macro. + # Replaced with a transient macro by commit 2f4dd13d4bb8 ("drm/gem: + # add drm_gem_object_put helper") in v5.9. + # + # Finally removed by commit ab15d56e27be ("drm: remove transient + # drm_gem_object_put_unlocked()") in v5.9. # CODE=" #if defined(NV_DRM_DRMP_H_PRESENT) @@ -4849,7 +4852,7 @@ compile_test() { # field. # # Removed by commit 0425662fdf05 ("drm: Nuke mode->vrefresh") in - # v5.9-rc1. + # v5.9. # CODE=" #include @@ -4867,7 +4870,7 @@ compile_test() { # Determine if drm_driver::master_set() returns integer value # # Changed to void by commit 907f53200f98 ("drm: vmwgfx: remove - # drm_driver::master_set() return type") in v5.9-rc1. + # drm_driver::master_set() return type") in v5.9. # CODE=" #if defined(NV_DRM_DRMP_H_PRESENT) @@ -4893,7 +4896,7 @@ compile_test() { # function pointer. # # drm_driver::gem_free_object is removed by commit 1a9458aeb8eb - # ("drm: remove drm_driver::gem_free_object") in v5.9-rc1. + # ("drm: remove drm_driver::gem_free_object") in v5.9. # CODE=" #if defined(NV_DRM_DRMP_H_PRESENT) @@ -4916,7 +4919,7 @@ compile_test() { # Determine if vga_tryget() is present # # vga_tryget() was removed by commit f369bc3f9096 ("vgaarb: mark - # vga_tryget static") in v5.9-rc1 (2020-08-01). + # vga_tryget static") in v5.9. # CODE=" #include @@ -4933,7 +4936,7 @@ compile_test() { # # pci_channel_state was removed by commit 16d79cd4e23b ("PCI: Use # 'pci_channel_state_t' instead of 'enum pci_channel_state'") in - # v5.9-rc1 (2020-07-02). + # v5.9. # CODE=" #include @@ -4949,7 +4952,8 @@ compile_test() { # Determine if 'cc_platform_has()' is present. # # Added by commit aa5a461171f9 ("x86/sev: Add an x86 version of - # cc_platform_has()") in v5.15.3 (2021-10-04) + # cc_platform_has()") in v5.16. + # CODE=" #if defined(NV_LINUX_CC_PLATFORM_H_PRESENT) #include @@ -4966,8 +4970,9 @@ compile_test() { # # Determine if drm_prime_pages_to_sg() has 'dev' argument. # - # drm_prime_pages_to_sg() is updated to take 'dev' argument by commit - # 707d561f77b5 ("drm: allow limiting the scatter list size."). + # drm_prime_pages_to_sg() is updated to take 'dev' argument by + # commit 707d561f77b5 ("drm: allow limiting the scatter list + # size.") in v5.10. # CODE=" #if defined(NV_DRM_DRMP_H_PRESENT) @@ -4991,9 +4996,9 @@ compile_test() { # Determine if drm_driver structure has the GEM and PRIME callback # function pointers. # - # The GEM and PRIME callback are removed from drm_driver - # structure, by commit d693def4fd1c ("drm: Remove obsolete GEM and - # PRIME callbacks from struct drm_driver"). + # The GEM and PRIME callbacks are removed from drm_driver + # structure by commit d693def4fd1c ("drm: Remove obsolete GEM and + # PRIME callbacks from struct drm_driver") in v5.11. # CODE=" #if defined(NV_DRM_DRMP_H_PRESENT) @@ -5022,8 +5027,8 @@ compile_test() { # Determine if drm_crtc_helper_funcs::atomic_check takes 'state' # argument of 'struct drm_atomic_state' type. # - # The commit 29b77ad7b9ca ("drm/atomic: Pass the full state to CRTC - # atomic_check") passed the full atomic state to + # Commit 29b77ad7b9ca ("drm/atomic: Pass the full state to CRTC + # atomic_check") in v5.11 passed the full atomic state to # drm_crtc_helper_funcs::atomic_check() # # To test the signature of drm_crtc_helper_funcs::atomic_check(), @@ -5059,9 +5064,9 @@ compile_test() { # Determine if drm_gem_object_funcs::vmap takes 'map' # argument of 'struct dma_buf_map' type. # - # The commit 49a3f51dfeee ("drm/gem: Use struct dma_buf_map in GEM - # vmap ops and convert GEM backends") update - # drm_gem_object_funcs::vmap to take 'map' argument. + # drm_gem_object_funcs::vmap is updated to take 'map' argument by + # commit 49a3f51dfeee ("drm/gem: Use struct dma_buf_map in GEM + # vmap ops and convert GEM backends") in v5.11. # CODE=" #include @@ -5078,7 +5083,7 @@ compile_test() { # Determine if seq_read_iter() is present # # seq_read_iter() was added by commit d4d50710a8b4 ("seq_file: - # add seq_read_iter") in v5.10-rc1 (2020-11-04). + # add seq_read_iter") in v5.10. # CODE=" #include @@ -5096,7 +5101,7 @@ compile_test() { # # The commit 07f4f97d7b4b ("vga_switcheroo: Use device link for HDA # controller") has moved 'PCI_CLASS_MULTIMEDIA_HD_AUDIO' macro from - # to in v4.17-rc1 (2018-03-03). + # to in v4.17. # CODE=" #include @@ -5114,6 +5119,9 @@ compile_test() { # unsafe_follow_pfn() was added by commit 69bacee7f9ad # ("mm: Add unsafe_follow_pfn") in v5.13-rc1. # + # Note: this commit never made it to the linux kernel, so + # unsafe_follow_pfn() never existed. + # CODE=" #include void conftest_unsafe_follow_pfn(void) { @@ -5128,8 +5136,8 @@ compile_test() { # Determine if drm_plane_helper_funcs::atomic_check takes 'state' # argument of 'struct drm_atomic_state' type. # - # The commit 7c11b99a8e58 ("drm/atomic: Pass the full state to - # planes atomic_check") passed the full atomic state to + # Commit 7c11b99a8e58 ("drm/atomic: Pass the full state to planes + # atomic_check") in v5.13 passes the full atomic state to # drm_plane_helper_funcs::atomic_check() # # To test the signature of drm_plane_helper_funcs::atomic_check(), @@ -5193,7 +5201,7 @@ compile_test() { # Determine if the add_memory_driver_managed function is present # # Added by commit 7b7b27214bba ("mm/memory_hotplug: introduce - # add_memory_driver_managed()") in v5.8-rc1 (2020-06-05) + # add_memory_driver_managed()") in v5.8. # CODE=" #include @@ -5208,8 +5216,8 @@ compile_test() { # # Check if add_memory_driver_managed() has mhp_flags arg. # - # Added by commit b6117199787c ("mm/memory_hotplug: prepare passing flags to - # add_memory() and friends") in v5.10-rc1 (2020-10-16) + # Added by commit b6117199787c ("mm/memory_hotplug: prepare + # passing flags to add_memory() and friends") in v5.10. # CODE=" #include @@ -5226,8 +5234,8 @@ compile_test() { # # Check if remove_memory() has nid parameter. # - # Removed by commit e1c158e4956612e7 ("mm/memory_hotplug: remove nid - # parameter from remove_memory() and friends") in v5.15-rc1 (2021-09-09) + # Removed by commit e1c158e49566 ("mm/memory_hotplug: remove nid + # parameter from remove_memory() and friends") in v5.15. # CODE=" #include @@ -5242,8 +5250,8 @@ compile_test() { # # Determine if the offline_and_remove_memory function is present. # - # Added by commit 08b3acd7a68fc179 ("mm/memory_hotplug: Introduce - # offline_and_remove_memory()") in v5.8-rc1 (2020-06-05) + # Added by commit 08b3acd7a68f ("mm/memory_hotplug: Introduce + # offline_and_remove_memory()") in v5.8. # CODE=" #include @@ -5258,8 +5266,8 @@ compile_test() { # # Determine if the device_property_read_u64 function is present # - # Added by commit b31384fa5de37a1 ("Driver core: Unified device - # properties interface for platform firmware") in v3.19-rc1 (2014-11-05) + # Added by commit b31384fa5de3 ("Driver core: Unified device + # properties interface for platform firmware") in v3.19. # CODE=" #include @@ -5274,8 +5282,12 @@ compile_test() { # # Determine if of_property_count_elems_of_size is present # - # Added by commit 1df09bcof (" Move OF property and graph API from - # base.c to property.c" + # Added by commit ad54a0cfbeb4 ("of: add functions to count + # number of elements in a property") in v3.15. + # + # Moved from base.c to property.c by commit 1df09bc66f9b ("of: + # Move OF property and graph API from base.c to property.c") in + # v4.13. # # Test if linux/of.h header file inclusion is successful or not, # depending on that check, for of_property_count_elems_of_size @@ -5306,8 +5318,12 @@ compile_test() { # # Determine if of_property_read_variable_u8_array is present # - # Added by commit 1df09bcof (" Move OF property and graph API from - # base.c to property.c" + # Added by commit a67e9472da42 ("of: Add array read functions + # with min/max size limits") in v4.9. + # + # Moved from base.c to property.c by commit 1df09bc66f9b ("of: + # Move OF property and graph API from base.c to property.c") in + # v4.13. # # Test if linux/of.h header file inclusion is successful or not, # depending on that, check for of_property_read_variable_u8_array @@ -5338,8 +5354,15 @@ compile_test() { # # Determine if of_property_read_variable_u32_array is present # - # Added by commit 1df09bcof (" Move OF property and graph API from - # base.c to property.c" + # Added by commit a67e9472da42 ("of: Add array read functions + # with min/max size limits") in v4.9. + # + # Moved from base.c to property.c by commit 1df09bc66f9b ("of: + # Move OF property and graph API from base.c to property.c") in + # v4.13. + # + # Note: this can probably be combined with the + # of_property_read_variable_u8_array conftest above. # # Test if linux/of.h header file inclusion is successful or not, # depending on that, check for of_property_read_variable_u32_array @@ -5370,8 +5393,8 @@ compile_test() { # # Determine if devm_of_platform_populate() function is present # - # Added by commit 38b0b21of (add devm_ functions for populate and - # depopulate") + # Added by commit 38b0b219fbe8 ("of: add devm_ functions for + # populate and depopulate") in v4.12. # CODE=" #if defined(NV_LINUX_OF_PLATFORM_H_PRESENT) @@ -5389,8 +5412,13 @@ compile_test() { # # Determine if of_dma_configure() function is present # - # Added by commit 591c1eeof ("configure the platform device - # dma parameters") + # Added by commit 591c1ee465ce ("of: configure the platform + # device dma parameters") in v3.16. However, it was a static, + # non-exported function at that time. + # + # It was moved from platform.c to device.c and made public by + # commit 1f5c69aa51f9 ("of: Move of_dma_configure() to device.c + # to help re-use") in v4.1. # CODE=" #if defined(NV_LINUX_OF_DEVICE_H_PRESENT) @@ -5409,8 +5437,8 @@ compile_test() { # # Determine if icc_get() function is present # - # Added by commit 11f1cec ("interconnect: Add generic on-chip - # interconnect API") + # Added by commit 11f1ceca7031 ("interconnect: Add generic + # on-chip interconnect API") in v5.1. # CODE=" #if defined(NV_LINUX_INTERCONNECT_H_PRESENT) @@ -5429,8 +5457,8 @@ compile_test() { # # Determine if icc_set_bw() function is present # - # Added by commit 11f1cec ("interconnect: Add generic on-chip - # interconnect API") + # Added by commit 11f1ceca7031 ("interconnect: Add generic + # on-chip interconnect API") in v5.1. # CODE=" #if defined(NV_LINUX_INTERCONNECT_H_PRESENT) @@ -5449,8 +5477,8 @@ compile_test() { # # Determine if icc_put() function is present # - # Added by commit 11f1cec ("interconnect: Add generic on-chip - # interconnect API") + # Added by commit 11f1ceca7031 ("interconnect: Add generic + # on-chip interconnect API") in v5.1. # CODE=" #if defined(NV_LINUX_INTERCONNECT_H_PRESENT) @@ -5469,7 +5497,8 @@ compile_test() { # # Determine if i2c_new_client_device() function is present # - # Added by commit 390fd04i2c ("remove deprecated i2c_new_device API") + # Added by commit 390fd0475af5 ("i2c: remove deprecated + # i2c_new_device API") in v5.8. # CODE=" #include @@ -5486,7 +5515,8 @@ compile_test() { # # Determine if i2c_unregister_device() function is present # - # Added by commit 9c1600ei2c ("Add i2c_board_info and i2c_new_device()") + # Added by commit 9c1600eda42e ("i2c: Add i2c_board_info and + # i2c_new_device()") in v2.6.22. # CODE=" #include @@ -5503,8 +5533,8 @@ compile_test() { # # Determine if of_get_named_gpio() function is present # - # Added by commit a6b0919 ("of/gpio: Add new method for getting gpios - # under different property names") + # Added by commit a6b0919140b4 ("of/gpio: Add new method for + # getting gpios under different property names") in v3.1. # CODE=" #if defined(NV_LINUX_OF_GPIO_H_PRESENT) @@ -5523,7 +5553,8 @@ compile_test() { # # Determine if devm_gpio_request_one() function is present # - # Added by commit 09d71ff (gpiolib: Implement devm_gpio_request_one()") + # Added by commit 09d71ff19404 ("gpiolib: Implement + # devm_gpio_request_one()") in v3.5. # CODE=" #if defined(NV_LINUX_GPIO_H_PRESENT) @@ -5542,7 +5573,8 @@ compile_test() { # # Determine if gpio_direction_input() function is present # - # Added by commit c7caf86 (gpio: remove gpio_ensure_requested()") + # Added by commit c7caf86823c7 ("gpio: remove + # gpio_ensure_requested()") in v3.17. # CODE=" #if defined(NV_LINUX_GPIO_H_PRESENT) @@ -5561,7 +5593,8 @@ compile_test() { # # Determine if gpio_direction_output() function is present # - # Added by commit c7caf86 (gpio: remove gpio_ensure_requested()") + # Added by commit c7caf86823c7 ("gpio: remove + # gpio_ensure_requested()") in v3.17. # CODE=" #if defined(NV_LINUX_GPIO_H_PRESENT) @@ -5580,8 +5613,8 @@ compile_test() { # # Determine if gpio_get_value() function is present # - # Added by commit 7563bbf ("gpiolib/arches: Centralise bolierplate - # asm/gpio.h") + # Added by commit 7563bbf89d06 ("gpiolib/arches: Centralise + # bolierplate asm/gpio.h") in v3.5. # CODE=" #if defined(NV_LINUX_GPIO_H_PRESENT) @@ -5600,8 +5633,8 @@ compile_test() { # # Determine if gpio_set_value() function is present # - # Added by commit 7563bbf ("gpiolib/arches: Centralise bolierplate - # asm/gpio.h") + # Added by commit 7563bbf89d06 ("gpiolib/arches: Centralise + # bolierplate asm/gpio.h") in v3.5. # CODE=" #if defined(NV_LINUX_GPIO_H_PRESENT) @@ -5620,8 +5653,8 @@ compile_test() { # # Determine if gpio_to_irq() function is present # - # Added by commit 7563bbf ("gpiolib/arches: Centralise bolierplate - # asm/gpio.h") + # Added by commit 7563bbf89d06 ("gpiolib/arches: Centralise + # bolierplate asm/gpio.h") in v3.5. # CODE=" #if defined(NV_LINUX_GPIO_H_PRESENT) @@ -5636,14 +5669,29 @@ compile_test() { compile_check_conftest "$CODE" "NV_GPIO_TO_IRQ_PRESENT" "" "functions" ;; + migrate_vma_setup) + # + # Determine if migrate_vma_setup() function is present + # + # Added by commit a7d1f22bb74f ("mm: turn migrate_vma upside + # down") in v5.4. + # + CODE=" + #include + int conftest_migrate_vma_setup(void) { + migrate_vma_setup(); + }" + + compile_check_conftest "$CODE" "NV_MIGRATE_VMA_SETUP_PRESENT" "" "functions" + ;; + migrate_vma_added_flags) # # Determine if migrate_vma structure has flags # - # flags were added to struct migrate_vma by commit - # 5143192cd410c4fc83be09a2e73423765aee072b ("mm/migrate: add a flags - # parameter to_migrate_vma) in v5.9. - # (2020-07-28). + # Added by commit 5143192cd410 ("mm/migrate: add a flags + # parameter to migrate_vma") in v5.9. + # CODE=" #include int conftest_migrate_vma_added_flags(void) { @@ -5658,7 +5706,7 @@ compile_test() { # Determine if the 'drm_device' structure has a 'pdev' field. # # Removed by commit b347e04452ff ("drm: Remove pdev field from - # struct drm_device") in v5.14-rc1. + # struct drm_device") in v5.14. # CODE=" #if defined(NV_DRM_DRMP_H_PRESENT) @@ -5712,9 +5760,9 @@ compile_test() { # # Determine if ioasid_get() function is present # - # ioasid_get() function was added by commit - # cb4789b0d19ff231ce9f73376a023341300aed96 (iommu/ioasid: Add ioasidreferences) in v5.11. - # (2020-11-23). + # Added by commit cb4789b0d19f ("iommu/ioasid: Add ioasid + # references") in v5.11. + # CODE=" #if defined(NV_LINUX_IOASID_H_PRESENT) #include @@ -5751,9 +5799,8 @@ compile_test() { # # Determine if the 'drm_crtc_state' structure has 'no_vblank'. # - # drm_crtc_state::no_vblank was added by commit b25c60af7a877 - # ("drm/crtc: Add a generic infrastructure to fake VBLANK events") - # in 4.18.0-rc3 (2018-07-03). + # Added by commit b25c60af7a87 ("drm/crtc: Add a generic + # infrastructure to fake VBLANK events") in v4.19. # CODE=" #include @@ -5773,7 +5820,7 @@ compile_test() { # an 'allow_fb_modifiers' field in the 'drm_mode_config' structure, # is added by commit e3eb3250d84e ("drm: add support for # tiled/compressed/etc modifier in addfb2") in v4.1, and removed by - # commit 3d082157a242 ("drm: remove allow_fb_modifiers") in v5.18-rc1. + # commit 3d082157a242 ("drm: remove allow_fb_modifiers") in v5.18. # # The 'struct drm_mode_config' definition, is moved to # drm_mode_config.h file by commit 28575f165d36 ("drm: Extract @@ -5811,9 +5858,8 @@ compile_test() { # # Determine if drm_mode.h has 'hdr_output_metadata' structure. # - # struct hdr_output_metadata was added by commit fbb5d0353c62d - # ("drm: Add HDR source metadata property") in 5.1.0-rc5 - # (2019-05-16) + # Added by commit fbb5d0353c62 ("drm: Add HDR source metadata + # property") in v5.3. # CODE=" #include @@ -5840,9 +5886,8 @@ compile_test() { # # Determine if the platform_irq_count() function is present # - # platform_irq_count was added by commit - # 4b83555d5098e73cf2c5ca7f86c17ca0ba3b968e ("driver-core: platform: Add platform_irq_count()") - # in 4.5-rc1 (2016-01-07) + # Added by commit 4b83555d5098 ("driver-core: platform: Add + # platform_irq_count()") in v4.5. # CODE=" #include @@ -5856,7 +5901,8 @@ compile_test() { # # Determine if devm_clk_bulk_get_all() function is present # - # Added by commit f08c2e286 ("clk: add managed version of clk_bulk_get_all") + # Added by commit f08c2e2865f6 ("clk: add managed version of + # clk_bulk_get_all") in v4.20. # CODE=" #if defined(NV_LINUX_CLK_H_PRESENT) @@ -5923,7 +5969,7 @@ compile_test() { # dma_resv_add_excl_fence() and dma_resv_add_shared_fence() were # removed and replaced with dma_resv_add_fence() by commit # 73511edf8b19 ("dma-buf: specify usage while adding fences to - # dma_resv obj v7") in linux-next, expected in v5.19-rc1. + # dma_resv obj v7") in v5.19. # CODE=" #if defined(NV_LINUX_DMA_RESV_H_PRESENT) @@ -5943,7 +5989,7 @@ compile_test() { # dma_resv_reserve_shared() was removed and replaced with # dma_resv_reserve_fences() by commit c8d4c18bfbc4 # ("dma-buf/drivers: make reserving a shared slot mandatory v4") in - # linux-next, expected in v5.19-rc1. + # v5.19. # CODE=" #if defined(NV_LINUX_DMA_RESV_H_PRESENT) @@ -5963,8 +6009,7 @@ compile_test() { # # reservation_object_reserve_shared() function prototype was updated # to take 'num_fences' argument by commit ca05359f1e64 ("dma-buf: - # allow reserving more than one shared fence slot") in v4.21-rc1 - # (2018-12-14). + # allow reserving more than one shared fence slot") in v5.0. # CODE=" #include @@ -5981,9 +6026,8 @@ compile_test() { # # Determine if the __get_task_ioprio() function is present. # - # __get_task_ioprio was added by commit 893e5d32d583 - # ("block: Generalize get_current_ioprio() for any task") for - # v5.20 linux-next (2022-06-23). + # Added by commit 893e5d32d583 ("block: Generalize + # get_current_ioprio() for any task") in v6.0. # CODE=" #include @@ -5998,9 +6042,8 @@ compile_test() { # # Determine if 'num_registered_fb' variable is present. # - # 'num_registered_fb' was removed by commit 5727dcfd8486 - # ("fbdev: Make registered_fb[] private to fbmem.c") for - # v5.20 linux-next (2022-07-27). + # Removed by commit 5727dcfd8486 ("fbdev: Make registered_fb[] + # private to fbmem.c") in v6.1. # CODE=" #include @@ -6146,9 +6189,8 @@ compile_test() { # # Determine if 'struct drm_connector' has an 'override_edid' member. # - # Removed by commit 90b575f52c6ab ("drm/edid: detach debugfs EDID - # override from EDID property update") in linux-next, expected in - # v6.2-rc1. + # Removed by commit 90b575f52c6a ("drm/edid: detach debugfs EDID + # override from EDID property update") in v6.2. # CODE=" #if defined(NV_DRM_DRM_CRTC_H_PRESENT) @@ -6190,10 +6232,9 @@ compile_test() { # Determine if the 'vm_area_struct' structure has # const 'vm_flags'. # - # A union of '__vm_flags' and 'const vm_flags' was added - # by commit bc292ab00f6c ("mm: introduce vma->vm_flags - # wrapper functions") in mm-stable branch (2023-02-09) - # of the akpm/mm maintainer tree. + # A union of '__vm_flags' and 'const vm_flags' was added by + # commit bc292ab00f6c ("mm: introduce vma->vm_flags wrapper + # functions") in v6.3. # CODE=" #include @@ -6209,8 +6250,8 @@ compile_test() { # Determine if the 'drm_driver' structure has a 'dumb_destroy' # function pointer. # - # Removed by commit 96a7b60f6ddb2 ("drm: remove dumb_destroy - # callback") in v6.3 linux-next (2023-02-10). + # Removed by commit 96a7b60f6ddb ("drm: remove dumb_destroy + # callback") in v6.4. # CODE=" #if defined(NV_DRM_DRMP_H_PRESENT) @@ -6232,9 +6273,8 @@ compile_test() { # # Check if memory_failure() has trapno parameter. # - # trapno argument was removed by commit - # 83b57531c58f4173d1c0d0b2c0bc88c853c32ea5 ("mm/memory_failure: - # Remove unused trapno from memory_failure") in v4.15.0 (2017-7-9) + # Removed by commit 83b57531c58f ("mm/memory_failure: Remove + # unused trapno from memory_failure") in v4.16. # CODE=" #include @@ -6251,9 +6291,8 @@ compile_test() { # # Check if memory_failure() flag MF_SW_SIMULATED is defined. # - # MF_SW_SIMULATED was added by commit - # 67f22ba7750f940bcd7e1b12720896c505c2d63f ("mm/hwpoison: - # fix unpoison_memory()") in v5.19.0-rc2 (2022-6-16) + # Added by commit 67f22ba7750f ("mm/memory-failure: disable + # unpoison once hw error happens") in v5.19. # CODE=" #include @@ -6264,6 +6303,186 @@ compile_test() { compile_check_conftest "$CODE" "NV_MEMORY_FAILURE_MF_SW_SIMULATED_DEFINED" "" "types" ;; + sync_file_get_fence) + # + # Determine if sync_file_get_fence() function is present + # + # Added by commit 972526a40932 ("dma-buf/sync_file: add + # sync_file_get_fence()") in v4.9. + # + CODE=" + #if defined(NV_LINUX_SYNC_FILE_H_PRESENT) + #include + #endif + void conftest_sync_file_get_fence(void) + { + sync_file_get_fence(); + }" + + compile_check_conftest "$CODE" "NV_SYNC_FILE_GET_FENCE_PRESENT" "" "functions" + ;; + + dma_fence_set_error) + # + # Determine if dma_fence_set_error() function is present + # + # Added by commit a009e975da5c ("dma-fence: Introduce + # drm_fence_set_error() helper") in v4.11. + # + CODE=" + #if defined(NV_LINUX_DMA_FENCE_H_PRESENT) + #include + #endif + void conftest_dma_fence_set_error(void) + { + dma_fence_set_error(); + }" + + compile_check_conftest "$CODE" "NV_DMA_FENCE_SET_ERROR_PRESENT" "" "functions" + ;; + + fence_set_error) + # + # Determine if fence_set_error() function is present + # + # fence_set_error is a different name for dma_fence_set_error + # present in kernels where commit a009e975da5c ("dma-fence: + # Introduce drm_fence_set_error() helper") from v4.11 was + # backported, but commit f54d1867005c ("dma-buf: Rename struct fence + # to dma_fence") from v4.10 was not. In particular, Tegra v4.9 + # kernels, such as commit f5e0724e76c2 ("dma-fence: Introduce + # drm_fence_set_error() helper") in NVIDIA Linux for Tegra (L4T) r31 + # and r32 kernels in the L4T kernel repo + # git://nv-tegra.nvidia.com/linux-4.9.git, contain this function. + # + CODE=" + #if defined(NV_LINUX_FENCE_H_PRESENT) + #include + #endif + void conftest_fence_set_error(void) + { + fence_set_error(); + }" + + compile_check_conftest "$CODE" "NV_FENCE_SET_ERROR_PRESENT" "" "functions" + ;; + + fence_ops_use_64bit_seqno) + # + # Determine if dma_fence_ops has the use_64bit_seqno member + # + # 64-bit fence seqno support was actually added by commit + # b312d8ca3a7c ("dma-buf: make fence sequence numbers 64 bit v2") + # in v5.1, but the field to explicitly declare support for it + # didn't get added until commit 5e498abf1485 ("dma-buf: + # explicitely note that dma-fence-chains use 64bit seqno") in + # v5.2. Since it is currently trivial to work around the lack of + # native 64-bit seqno in our driver, we'll use the work-around path + # for kernels prior to v5.2 to avoid further ifdefing of the code. + # + CODE=" + #if defined(NV_LINUX_DMA_FENCE_H_PRESENT) + #include + #endif + int conftest_fence_ops(void) + { + return offsetof(struct dma_fence_ops, use_64bit_seqno); + }" + + compile_check_conftest "$CODE" "NV_DMA_FENCE_OPS_HAS_USE_64BIT_SEQNO" "" "types" + ;; + + drm_fbdev_generic_setup) + # + # Determine whether drm_fbdev_generic_setup is present. + # + # Added by commit 9060d7f49376 ("drm/fb-helper: Finish the + # generic fbdev emulation") in v4.19. + # + CODE=" + #include + #if defined(NV_DRM_DRM_FBDEV_GENERIC_H_PRESENT) + #include + #endif + void conftest_drm_fbdev_generic_setup(void) { + drm_fbdev_generic_setup(); + }" + + compile_check_conftest "$CODE" "NV_DRM_FBDEV_GENERIC_SETUP_PRESENT" "" "functions" + ;; + + drm_aperture_remove_conflicting_pci_framebuffers) + # + # Determine whether drm_aperture_remove_conflicting_pci_framebuffers is present. + # + # Added by commit 2916059147ea ("drm/aperture: Add infrastructure + # for aperture ownership") in v5.14. + # + CODE=" + #if defined(NV_DRM_DRM_APERTURE_H_PRESENT) + #include + #endif + void conftest_drm_aperture_remove_conflicting_pci_framebuffers(void) { + drm_aperture_remove_conflicting_pci_framebuffers(); + }" + + compile_check_conftest "$CODE" "NV_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PRESENT" "" "functions" + ;; + + drm_aperture_remove_conflicting_pci_framebuffers_has_driver_arg) + # + # Determine whether drm_aperture_remove_conflicting_pci_framebuffers + # takes a struct drm_driver * as its second argument. + # + # Prior to commit 97c9bfe3f6605d41eb8f1206e6e0f62b31ba15d6, the + # second argument was a char * pointer to the driver's name. + # + # To test if drm_aperture_remove_conflicting_pci_framebuffers() has + # a req_driver argument, define a function with the expected + # signature and then define the corresponding function + # implementation with the expected signature. Successful compilation + # indicates that this function has the expected signature. + # + # This change occurred in commit 97c9bfe3f660 ("drm/aperture: Pass + # DRM driver structure instead of driver name") in v5.15 + # (2021-06-29). + # + CODE=" + #if defined(NV_DRM_DRM_DRV_H_PRESENT) + #include + #endif + #if defined(NV_DRM_DRM_APERTURE_H_PRESENT) + #include + #endif + typeof(drm_aperture_remove_conflicting_pci_framebuffers) conftest_drm_aperture_remove_conflicting_pci_framebuffers; + int conftest_drm_aperture_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, + const struct drm_driver *req_driver) + { + return 0; + }" + + compile_check_conftest "$CODE" "NV_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_HAS_DRIVER_ARG" "" "types" + ;; + + find_next_bit_wrap) + # Determine if 'find_next_bit_wrap' is defined. + # + # The function was added by commit 6cc18331a987 ("lib/find_bit: + # add find_next{,_and}_bit_wrap") in v6.1-rc1 (2022-09-19). + # + # Ideally, we would want to be able to include linux/find.h. + # However, linux/find.h does not allow direct inclusion. Rather + # it has to be included through linux/bitmap.h. + # + CODE=" + #include + void conftest_find_next_bit_wrap(void) { + (void)find_next_bit_wrap(); + }" + + compile_check_conftest "$CODE" "NV_FIND_NEXT_BIT_WRAP_PRESENT" "" "functions" + ;; + crypto) # # Determine if we support various crypto functions. @@ -6342,6 +6561,29 @@ compile_test() { compile_check_conftest "$CODE" "NV_MPOL_PREFERRED_MANY_PRESENT" "" "types" ;; + drm_connector_attach_hdr_output_metadata_property) + # + # Determine if the function + # drm_connector_attach_hdr_output_metadata_property() is present. + # + # Added by commit e057b52c1d90 ("drm/connector: Create a helper to + # attach the hdr_output_metadata property") in v5.14. + # + CODE=" + #if defined(NV_DRM_DRM_CRTC_H_PRESENT) + #include + #endif + #if defined(NV_DRM_DRM_CONNECTOR_H_PRESENT) + #include + #endif + + void conftest_drm_connector_attach_hdr_output_metadata_property(void) { + drm_connector_attach_hdr_output_metadata_property(); + }" + + compile_check_conftest "$CODE" "NV_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY_PRESENT" "" "functions" + ;; + mmu_interval_notifier) # # Determine if mmu_interval_notifier struct is present or not @@ -6357,11 +6599,48 @@ compile_test() { compile_check_conftest "$CODE" "NV_MMU_INTERVAL_NOTIFIER" "" "types" ;; + drm_mode_create_dp_colorspace_property_has_supported_colorspaces_arg) + # Determine if drm_mode_create_dp_colorspace_property() takes the + # 'supported_colorspaces' argument. + # + # The 'u32 supported_colorspaces' argument was added to + # drm_mode_create_dp_colorspace_property() by linux-next commit + # c265f340eaa8 ("drm/connector: Allow drivers to pass list of + # supported colorspaces"). + # + # To test if drm_mode_create_dp_colorspace_property() has the + # 'supported_colorspaces' argument, declare a function prototype + # with typeof drm_mode_create_dp_colorspace_property and then + # define the corresponding function implementation with the + # expected signature. Successful compilation indicates that + # drm_mode_create_dp_colorspace_property() has the + # 'supported_colorspaces' argument. + # + CODE=" + #if defined(NV_DRM_DRM_CRTC_H_PRESENT) + #include + #endif + #if defined(NV_DRM_DRM_CONNECTOR_H_PRESENT) + #include + #endif + + typeof(drm_mode_create_dp_colorspace_property) conftest_drm_mode_create_dp_colorspace_property_has_supported_colorspaces_arg; + int conftest_drm_mode_create_dp_colorspace_property_has_supported_colorspaces_arg(struct drm_connector *connector, + u32 supported_colorspaces) + { + return 0; + }" + + compile_check_conftest "$CODE" "NV_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY_HAS_SUPPORTED_COLORSPACES_ARG" "" "types" + ;; + # When adding a new conftest entry, please use the correct format for - # specifying the relevant upstream Linux kernel commit. + # specifying the relevant upstream Linux kernel commit. Please + # avoid specifying -rc kernels, and only use SHAs that actually exist + # in the upstream Linux kernel git repository. # - # was added|removed|etc by commit (" (). + # Added|Removed|etc by commit (". *) # Unknown test name given diff --git a/kernel-open/nvidia-drm/nv-kthread-q.c b/kernel-open/nvidia-drm/nv-kthread-q.c new file mode 100644 index 0000000000..c3b5570557 --- /dev/null +++ b/kernel-open/nvidia-drm/nv-kthread-q.c @@ -0,0 +1,334 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nv-kthread-q.h" +#include "nv-list-helpers.h" + +#include +#include +#include +#include +#include + +#if defined(NV_LINUX_BUG_H_PRESENT) + #include +#else + #include +#endif + +// Today's implementation is a little simpler and more limited than the +// API description allows for in nv-kthread-q.h. Details include: +// +// 1. Each nv_kthread_q instance is a first-in, first-out queue. +// +// 2. Each nv_kthread_q instance is serviced by exactly one kthread. +// +// You can create any number of queues, each of which gets its own +// named kernel thread (kthread). You can then insert arbitrary functions +// into the queue, and those functions will be run in the context of the +// queue's kthread. + +#ifndef WARN + // Only *really* old kernels (2.6.9) end up here. Just use a simple printk + // to implement this, because such kernels won't be supported much longer. + #define WARN(condition, format...) ({ \ + int __ret_warn_on = !!(condition); \ + if (unlikely(__ret_warn_on)) \ + printk(KERN_ERR format); \ + unlikely(__ret_warn_on); \ + }) +#endif + +#define NVQ_WARN(fmt, ...) \ + do { \ + if (in_interrupt()) { \ + WARN(1, "nv_kthread_q: [in interrupt]: " fmt, \ + ##__VA_ARGS__); \ + } \ + else { \ + WARN(1, "nv_kthread_q: task: %s: " fmt, \ + current->comm, \ + ##__VA_ARGS__); \ + } \ + } while (0) + +static int _main_loop(void *args) +{ + nv_kthread_q_t *q = (nv_kthread_q_t *)args; + nv_kthread_q_item_t *q_item = NULL; + unsigned long flags; + + while (1) { + // Normally this thread is never interrupted. However, + // down_interruptible (instead of down) is called here, + // in order to avoid being classified as a potentially + // hung task, by the kernel watchdog. + while (down_interruptible(&q->q_sem)) + NVQ_WARN("Interrupted during semaphore wait\n"); + + if (atomic_read(&q->main_loop_should_exit)) + break; + + spin_lock_irqsave(&q->q_lock, flags); + + // The q_sem semaphore prevents us from getting here unless there is + // at least one item in the list, so an empty list indicates a bug. + if (unlikely(list_empty(&q->q_list_head))) { + spin_unlock_irqrestore(&q->q_lock, flags); + NVQ_WARN("_main_loop: Empty queue: q: 0x%p\n", q); + continue; + } + + // Consume one item from the queue + q_item = list_first_entry(&q->q_list_head, + nv_kthread_q_item_t, + q_list_node); + + list_del_init(&q_item->q_list_node); + + spin_unlock_irqrestore(&q->q_lock, flags); + + // Run the item + q_item->function_to_run(q_item->function_args); + + // Make debugging a little simpler by clearing this between runs: + q_item = NULL; + } + + while (!kthread_should_stop()) + schedule(); + + return 0; +} + +void nv_kthread_q_stop(nv_kthread_q_t *q) +{ + // check if queue has been properly initialized + if (unlikely(!q->q_kthread)) + return; + + nv_kthread_q_flush(q); + + // If this assertion fires, then a caller likely either broke the API rules, + // by adding items after calling nv_kthread_q_stop, or possibly messed up + // with inadequate flushing of self-rescheduling q_items. + if (unlikely(!list_empty(&q->q_list_head))) + NVQ_WARN("list not empty after flushing\n"); + + if (likely(!atomic_read(&q->main_loop_should_exit))) { + + atomic_set(&q->main_loop_should_exit, 1); + + // Wake up the kthread so that it can see that it needs to stop: + up(&q->q_sem); + + kthread_stop(q->q_kthread); + q->q_kthread = NULL; + } +} + +// When CONFIG_VMAP_STACK is defined, the kernel thread stack allocator used by +// kthread_create_on_node relies on a 2 entry, per-core cache to minimize +// vmalloc invocations. The cache is NUMA-unaware, so when there is a hit, the +// stack location ends up being a function of the core assigned to the current +// thread, instead of being a function of the specified NUMA node. The cache was +// added to the kernel in commit ac496bf48d97f2503eaa353996a4dd5e4383eaf0 +// ("fork: Optimize task creation by caching two thread stacks per CPU if +// CONFIG_VMAP_STACK=y") +// +// To work around the problematic cache, we create up to three kernel threads +// -If the first thread's stack is resident on the preferred node, return this +// thread. +// -Otherwise, create a second thread. If its stack is resident on the +// preferred node, stop the first thread and return this one. +// -Otherwise, create a third thread. The stack allocator does not find a +// cached stack, and so falls back to vmalloc, which takes the NUMA hint into +// consideration. The first two threads are then stopped. +// +// When CONFIG_VMAP_STACK is not defined, the first kernel thread is returned. +// +// This function is never invoked when there is no NUMA preference (preferred +// node is NUMA_NO_NODE). +static struct task_struct *thread_create_on_node(int (*threadfn)(void *data), + nv_kthread_q_t *q, + int preferred_node, + const char *q_name) +{ + + unsigned i, j; + const static unsigned attempts = 3; + struct task_struct *thread[3]; + + for (i = 0;; i++) { + struct page *stack; + + thread[i] = kthread_create_on_node(threadfn, q, preferred_node, q_name); + + if (unlikely(IS_ERR(thread[i]))) { + + // Instead of failing, pick the previous thread, even if its + // stack is not allocated on the preferred node. + if (i > 0) + i--; + + break; + } + + // vmalloc is not used to allocate the stack, so simply return the + // thread, even if its stack may not be allocated on the preferred node + if (!is_vmalloc_addr(thread[i]->stack)) + break; + + // Ran out of attempts - return thread even if its stack may not be + // allocated on the preferred node + if ((i == (attempts - 1))) + break; + + // Get the NUMA node where the first page of the stack is resident. If + // it is the preferred node, select this thread. + stack = vmalloc_to_page(thread[i]->stack); + if (page_to_nid(stack) == preferred_node) + break; + } + + for (j = i; j > 0; j--) + kthread_stop(thread[j - 1]); + + return thread[i]; +} + +int nv_kthread_q_init_on_node(nv_kthread_q_t *q, const char *q_name, int preferred_node) +{ + memset(q, 0, sizeof(*q)); + + INIT_LIST_HEAD(&q->q_list_head); + spin_lock_init(&q->q_lock); + sema_init(&q->q_sem, 0); + + if (preferred_node == NV_KTHREAD_NO_NODE) { + q->q_kthread = kthread_create(_main_loop, q, q_name); + } + else { + q->q_kthread = thread_create_on_node(_main_loop, q, preferred_node, q_name); + } + + if (IS_ERR(q->q_kthread)) { + int err = PTR_ERR(q->q_kthread); + + // Clear q_kthread before returning so that nv_kthread_q_stop() can be + // safely called on it making error handling easier. + q->q_kthread = NULL; + + return err; + } + + wake_up_process(q->q_kthread); + + return 0; +} + +int nv_kthread_q_init(nv_kthread_q_t *q, const char *qname) +{ + return nv_kthread_q_init_on_node(q, qname, NV_KTHREAD_NO_NODE); +} + +// Returns true (non-zero) if the item was actually scheduled, and false if the +// item was already pending in a queue. +static int _raw_q_schedule(nv_kthread_q_t *q, nv_kthread_q_item_t *q_item) +{ + unsigned long flags; + int ret = 1; + + spin_lock_irqsave(&q->q_lock, flags); + + if (likely(list_empty(&q_item->q_list_node))) + list_add_tail(&q_item->q_list_node, &q->q_list_head); + else + ret = 0; + + spin_unlock_irqrestore(&q->q_lock, flags); + + if (likely(ret)) + up(&q->q_sem); + + return ret; +} + +void nv_kthread_q_item_init(nv_kthread_q_item_t *q_item, + nv_q_func_t function_to_run, + void *function_args) +{ + INIT_LIST_HEAD(&q_item->q_list_node); + q_item->function_to_run = function_to_run; + q_item->function_args = function_args; +} + +// Returns true (non-zero) if the q_item got scheduled, false otherwise. +int nv_kthread_q_schedule_q_item(nv_kthread_q_t *q, + nv_kthread_q_item_t *q_item) +{ + if (unlikely(atomic_read(&q->main_loop_should_exit))) { + NVQ_WARN("Not allowed: nv_kthread_q_schedule_q_item was " + "called with a non-alive q: 0x%p\n", q); + return 0; + } + + return _raw_q_schedule(q, q_item); +} + +static void _q_flush_function(void *args) +{ + struct completion *completion = (struct completion *)args; + complete(completion); +} + + +static void _raw_q_flush(nv_kthread_q_t *q) +{ + nv_kthread_q_item_t q_item; + DECLARE_COMPLETION_ONSTACK(completion); + + nv_kthread_q_item_init(&q_item, _q_flush_function, &completion); + + _raw_q_schedule(q, &q_item); + + // Wait for the flush item to run. Once it has run, then all of the + // previously queued items in front of it will have run, so that means + // the flush is complete. + wait_for_completion(&completion); +} + +void nv_kthread_q_flush(nv_kthread_q_t *q) +{ + if (unlikely(atomic_read(&q->main_loop_should_exit))) { + NVQ_WARN("Not allowed: nv_kthread_q_flush was called after " + "nv_kthread_q_stop. q: 0x%p\n", q); + return; + } + + // This 2x flush is not a typing mistake. The queue really does have to be + // flushed twice, in order to take care of the case of a q_item that + // reschedules itself. + _raw_q_flush(q); + _raw_q_flush(q); +} diff --git a/kernel-open/nvidia-drm/nvidia-dma-fence-helper.h b/kernel-open/nvidia-drm/nvidia-dma-fence-helper.h index a09ab7678a..731f6a794b 100644 --- a/kernel-open/nvidia-drm/nvidia-dma-fence-helper.h +++ b/kernel-open/nvidia-drm/nvidia-dma-fence-helper.h @@ -43,9 +43,13 @@ #if defined(NV_LINUX_FENCE_H_PRESENT) typedef struct fence nv_dma_fence_t; typedef struct fence_ops nv_dma_fence_ops_t; +typedef struct fence_cb nv_dma_fence_cb_t; +typedef fence_func_t nv_dma_fence_func_t; #else typedef struct dma_fence nv_dma_fence_t; typedef struct dma_fence_ops nv_dma_fence_ops_t; +typedef struct dma_fence_cb nv_dma_fence_cb_t; +typedef dma_fence_func_t nv_dma_fence_func_t; #endif #if defined(NV_LINUX_FENCE_H_PRESENT) @@ -97,6 +101,14 @@ static inline int nv_dma_fence_signal(nv_dma_fence_t *fence) { #endif } +static inline int nv_dma_fence_signal_locked(nv_dma_fence_t *fence) { +#if defined(NV_LINUX_FENCE_H_PRESENT) + return fence_signal_locked(fence); +#else + return dma_fence_signal_locked(fence); +#endif +} + static inline u64 nv_dma_fence_context_alloc(unsigned num) { #if defined(NV_LINUX_FENCE_H_PRESENT) return fence_context_alloc(num); @@ -108,7 +120,7 @@ static inline u64 nv_dma_fence_context_alloc(unsigned num) { static inline void nv_dma_fence_init(nv_dma_fence_t *fence, const nv_dma_fence_ops_t *ops, - spinlock_t *lock, u64 context, unsigned seqno) { + spinlock_t *lock, u64 context, uint64_t seqno) { #if defined(NV_LINUX_FENCE_H_PRESENT) fence_init(fence, ops, lock, context, seqno); #else @@ -116,6 +128,29 @@ nv_dma_fence_init(nv_dma_fence_t *fence, #endif } +static inline void +nv_dma_fence_set_error(nv_dma_fence_t *fence, + int error) { +#if defined(NV_DMA_FENCE_SET_ERROR_PRESENT) + return dma_fence_set_error(fence, error); +#elif defined(NV_FENCE_SET_ERROR_PRESENT) + return fence_set_error(fence, error); +#else + fence->status = error; +#endif +} + +static inline int +nv_dma_fence_add_callback(nv_dma_fence_t *fence, + nv_dma_fence_cb_t *cb, + nv_dma_fence_func_t func) { +#if defined(NV_LINUX_FENCE_H_PRESENT) + return fence_add_callback(fence, cb, func); +#else + return dma_fence_add_callback(fence, cb, func); +#endif +} + #endif /* defined(NV_DRM_FENCE_AVAILABLE) */ #endif /* __NVIDIA_DMA_FENCE_HELPER_H__ */ diff --git a/kernel-open/nvidia-drm/nvidia-dma-resv-helper.h b/kernel-open/nvidia-drm/nvidia-dma-resv-helper.h index b520b260a4..43a30b8c2a 100644 --- a/kernel-open/nvidia-drm/nvidia-dma-resv-helper.h +++ b/kernel-open/nvidia-drm/nvidia-dma-resv-helper.h @@ -121,6 +121,20 @@ static inline void nv_dma_resv_add_excl_fence(nv_dma_resv_t *obj, #endif } +static inline void nv_dma_resv_add_shared_fence(nv_dma_resv_t *obj, + nv_dma_fence_t *fence) +{ +#if defined(NV_LINUX_DMA_RESV_H_PRESENT) +#if defined(NV_DMA_RESV_ADD_FENCE_PRESENT) + dma_resv_add_fence(obj, fence, DMA_RESV_USAGE_READ); +#else + dma_resv_add_shared_fence(obj, fence); +#endif +#else + reservation_object_add_shared_fence(obj, fence); +#endif +} + #endif /* defined(NV_DRM_FENCE_AVAILABLE) */ #endif /* __NVIDIA_DMA_RESV_HELPER_H__ */ diff --git a/kernel-open/nvidia-drm/nvidia-drm-conftest.h b/kernel-open/nvidia-drm/nvidia-drm-conftest.h index bed8d81265..fd389f1099 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-conftest.h +++ b/kernel-open/nvidia-drm/nvidia-drm-conftest.h @@ -61,4 +61,15 @@ #undef NV_DRM_FENCE_AVAILABLE #endif +/* + * We can support color management if either drm_helper_crtc_enable_color_mgmt() + * or drm_crtc_enable_color_mgmt() exist. + */ +#if defined(NV_DRM_HELPER_CRTC_ENABLE_COLOR_MGMT_PRESENT) || \ + defined(NV_DRM_CRTC_ENABLE_COLOR_MGMT_PRESENT) +#define NV_DRM_COLOR_MGMT_AVAILABLE +#else +#undef NV_DRM_COLOR_MGMT_AVAILABLE +#endif + #endif /* defined(__NVIDIA_DRM_CONFTEST_H__) */ diff --git a/kernel-open/nvidia-drm/nvidia-drm-connector.c b/kernel-open/nvidia-drm/nvidia-drm-connector.c index 18965cf7b8..4d2e11262d 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-connector.c +++ b/kernel-open/nvidia-drm/nvidia-drm-connector.c @@ -349,10 +349,125 @@ nv_drm_connector_best_encoder(struct drm_connector *connector) return NULL; } +#if defined(NV_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY_HAS_SUPPORTED_COLORSPACES_ARG) +static const NvU32 __nv_drm_connector_supported_colorspaces = + BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) | + BIT(DRM_MODE_COLORIMETRY_BT2020_YCC); +#endif + +#if defined(NV_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY_PRESENT) +static int +__nv_drm_connector_atomic_check(struct drm_connector *connector, + struct drm_atomic_state *state) +{ + struct drm_connector_state *new_connector_state = + drm_atomic_get_new_connector_state(state, connector); + struct drm_connector_state *old_connector_state = + drm_atomic_get_old_connector_state(state, connector); + struct nv_drm_device *nv_dev = to_nv_device(connector->dev); + + struct drm_crtc *crtc = new_connector_state->crtc; + struct drm_crtc_state *crtc_state; + struct nv_drm_crtc_state *nv_crtc_state; + struct NvKmsKapiHeadRequestedConfig *req_config; + + if (!crtc) { + return 0; + } + + crtc_state = drm_atomic_get_new_crtc_state(state, crtc); + nv_crtc_state = to_nv_crtc_state(crtc_state); + req_config = &nv_crtc_state->req_config; + + /* + * Override metadata for the entire head instead of allowing NVKMS to derive + * it from the layers' metadata. + * + * This is the metadata that will sent to the display, and if applicable, + * layers will be tone mapped to this metadata rather than that of the + * display. + */ + req_config->flags.hdrInfoFrameChanged = + !drm_connector_atomic_hdr_metadata_equal(old_connector_state, + new_connector_state); + if (new_connector_state->hdr_output_metadata && + new_connector_state->hdr_output_metadata->data) { + + /* + * Note that HDMI definitions are used here even though we might not + * be using HDMI. While that seems odd, it is consistent with + * upstream behavior. + */ + + struct hdr_output_metadata *hdr_metadata = + new_connector_state->hdr_output_metadata->data; + struct hdr_metadata_infoframe *info_frame = + &hdr_metadata->hdmi_metadata_type1; + unsigned int i; + + if (hdr_metadata->metadata_type != HDMI_STATIC_METADATA_TYPE1) { + return -EINVAL; + } + + for (i = 0; i < ARRAY_SIZE(info_frame->display_primaries); i++) { + req_config->modeSetConfig.hdrInfoFrame.staticMetadata.displayPrimaries[i].x = + info_frame->display_primaries[i].x; + req_config->modeSetConfig.hdrInfoFrame.staticMetadata.displayPrimaries[i].y = + info_frame->display_primaries[i].y; + } + + req_config->modeSetConfig.hdrInfoFrame.staticMetadata.whitePoint.x = + info_frame->white_point.x; + req_config->modeSetConfig.hdrInfoFrame.staticMetadata.whitePoint.y = + info_frame->white_point.y; + req_config->modeSetConfig.hdrInfoFrame.staticMetadata.maxDisplayMasteringLuminance = + info_frame->max_display_mastering_luminance; + req_config->modeSetConfig.hdrInfoFrame.staticMetadata.minDisplayMasteringLuminance = + info_frame->min_display_mastering_luminance; + req_config->modeSetConfig.hdrInfoFrame.staticMetadata.maxCLL = + info_frame->max_cll; + req_config->modeSetConfig.hdrInfoFrame.staticMetadata.maxFALL = + info_frame->max_fall; + + req_config->modeSetConfig.hdrInfoFrame.eotf = info_frame->eotf; + + req_config->modeSetConfig.hdrInfoFrame.enabled = NV_TRUE; + } else { + req_config->modeSetConfig.hdrInfoFrame.enabled = NV_FALSE; + } + + req_config->flags.colorimetryChanged = + (old_connector_state->colorspace != new_connector_state->colorspace); + // When adding a case here, also add to __nv_drm_connector_supported_colorspaces + switch (new_connector_state->colorspace) { + case DRM_MODE_COLORIMETRY_DEFAULT: + req_config->modeSetConfig.colorimetry = + NVKMS_OUTPUT_COLORIMETRY_DEFAULT; + break; + case DRM_MODE_COLORIMETRY_BT2020_RGB: + case DRM_MODE_COLORIMETRY_BT2020_YCC: + // Ignore RGB/YCC + // See https://patchwork.freedesktop.org/patch/525496/?series=111865&rev=4 + req_config->modeSetConfig.colorimetry = + NVKMS_OUTPUT_COLORIMETRY_BT2100; + break; + default: + // XXX HDR TODO: Add support for more color spaces + NV_DRM_DEV_LOG_ERR(nv_dev, "Unsupported color space"); + return -EINVAL; + } + + return 0; +} +#endif /* defined(NV_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY_PRESENT) */ + static const struct drm_connector_helper_funcs nv_connector_helper_funcs = { .get_modes = nv_drm_connector_get_modes, .mode_valid = nv_drm_connector_mode_valid, .best_encoder = nv_drm_connector_best_encoder, +#if defined(NV_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY_PRESENT) + .atomic_check = __nv_drm_connector_atomic_check, +#endif }; static struct drm_connector* @@ -405,6 +520,32 @@ nv_drm_connector_new(struct drm_device *dev, DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; } +#if defined(NV_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY_PRESENT) + if (nv_connector->type == NVKMS_CONNECTOR_TYPE_HDMI) { +#if defined(NV_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY_HAS_SUPPORTED_COLORSPACES_ARG) + if (drm_mode_create_hdmi_colorspace_property( + &nv_connector->base, + __nv_drm_connector_supported_colorspaces) == 0) { +#else + if (drm_mode_create_hdmi_colorspace_property(&nv_connector->base) == 0) { +#endif + drm_connector_attach_colorspace_property(&nv_connector->base); + } + drm_connector_attach_hdr_output_metadata_property(&nv_connector->base); + } else if (nv_connector->type == NVKMS_CONNECTOR_TYPE_DP) { +#if defined(NV_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY_HAS_SUPPORTED_COLORSPACES_ARG) + if (drm_mode_create_dp_colorspace_property( + &nv_connector->base, + __nv_drm_connector_supported_colorspaces) == 0) { +#else + if (drm_mode_create_dp_colorspace_property(&nv_connector->base) == 0) { +#endif + drm_connector_attach_colorspace_property(&nv_connector->base); + } + drm_connector_attach_hdr_output_metadata_property(&nv_connector->base); + } +#endif /* defined(NV_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY_PRESENT) */ + /* Register connector with DRM subsystem */ ret = drm_connector_register(&nv_connector->base); diff --git a/kernel-open/nvidia-drm/nvidia-drm-crtc.c b/kernel-open/nvidia-drm/nvidia-drm-crtc.c index 333387a155..8a12da70ba 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-crtc.c +++ b/kernel-open/nvidia-drm/nvidia-drm-crtc.c @@ -48,6 +48,11 @@ #include #endif +#if defined(NV_DRM_DRM_COLOR_MGMT_H_PRESENT) +#include +#endif + + #if defined(NV_DRM_HAS_HDR_OUTPUT_METADATA) static int nv_drm_atomic_replace_property_blob_from_id(struct drm_device *dev, @@ -399,27 +404,25 @@ plane_req_config_update(struct drm_plane *plane, } for (i = 0; i < ARRAY_SIZE(info_frame->display_primaries); i ++) { - req_config->config.hdrMetadata.displayPrimaries[i].x = + req_config->config.hdrMetadata.val.displayPrimaries[i].x = info_frame->display_primaries[i].x; - req_config->config.hdrMetadata.displayPrimaries[i].y = + req_config->config.hdrMetadata.val.displayPrimaries[i].y = info_frame->display_primaries[i].y; } - req_config->config.hdrMetadata.whitePoint.x = + req_config->config.hdrMetadata.val.whitePoint.x = info_frame->white_point.x; - req_config->config.hdrMetadata.whitePoint.y = + req_config->config.hdrMetadata.val.whitePoint.y = info_frame->white_point.y; - req_config->config.hdrMetadata.maxDisplayMasteringLuminance = + req_config->config.hdrMetadata.val.maxDisplayMasteringLuminance = info_frame->max_display_mastering_luminance; - req_config->config.hdrMetadata.minDisplayMasteringLuminance = + req_config->config.hdrMetadata.val.minDisplayMasteringLuminance = info_frame->min_display_mastering_luminance; - req_config->config.hdrMetadata.maxCLL = + req_config->config.hdrMetadata.val.maxCLL = info_frame->max_cll; - req_config->config.hdrMetadata.maxFALL = + req_config->config.hdrMetadata.val.maxFALL = info_frame->max_fall; - req_config->config.hdrMetadataSpecified = true; - switch (info_frame->eotf) { case HDMI_EOTF_SMPTE_ST2084: req_config->config.tf = NVKMS_OUTPUT_TF_PQ; @@ -432,10 +435,21 @@ plane_req_config_update(struct drm_plane *plane, NV_DRM_DEV_LOG_ERR(nv_dev, "Unsupported EOTF"); return -1; } + + req_config->config.hdrMetadata.enabled = true; } else { - req_config->config.hdrMetadataSpecified = false; + req_config->config.hdrMetadata.enabled = false; req_config->config.tf = NVKMS_OUTPUT_TF_NONE; } + + req_config->flags.hdrMetadataChanged = + ((old_config.hdrMetadata.enabled != + req_config->config.hdrMetadata.enabled) || + memcmp(&old_config.hdrMetadata.val, + &req_config->config.hdrMetadata.val, + sizeof(struct NvKmsHDRStaticMetadata))); + + req_config->flags.tfChanged = (old_config.tf != req_config->config.tf); #endif /* @@ -692,9 +706,11 @@ static inline void __nv_drm_plane_atomic_destroy_state( #endif #if defined(NV_DRM_HAS_HDR_OUTPUT_METADATA) - struct nv_drm_plane_state *nv_drm_plane_state = - to_nv_drm_plane_state(state); - drm_property_blob_put(nv_drm_plane_state->hdr_output_metadata); + { + struct nv_drm_plane_state *nv_drm_plane_state = + to_nv_drm_plane_state(state); + drm_property_blob_put(nv_drm_plane_state->hdr_output_metadata); + } #endif } @@ -800,6 +816,9 @@ nv_drm_atomic_crtc_duplicate_state(struct drm_crtc *crtc) &(to_nv_crtc_state(crtc->state)->req_config), &nv_state->req_config); + nv_state->ilut_ramps = NULL; + nv_state->olut_ramps = NULL; + return &nv_state->base; } @@ -823,6 +842,9 @@ static void nv_drm_atomic_crtc_destroy_state(struct drm_crtc *crtc, __nv_drm_atomic_helper_crtc_destroy_state(crtc, &nv_state->base); + nv_drm_free(nv_state->ilut_ramps); + nv_drm_free(nv_state->olut_ramps); + nv_drm_free(nv_state); } @@ -833,6 +855,9 @@ static struct drm_crtc_funcs nv_crtc_funcs = { .destroy = nv_drm_crtc_destroy, .atomic_duplicate_state = nv_drm_atomic_crtc_duplicate_state, .atomic_destroy_state = nv_drm_atomic_crtc_destroy_state, +#if defined(NV_DRM_ATOMIC_HELPER_LEGACY_GAMMA_SET_PRESENT) + .gamma_set = drm_atomic_helper_legacy_gamma_set, +#endif }; /* @@ -866,6 +891,198 @@ static int head_modeset_config_attach_connector( return 0; } +#if defined(NV_DRM_COLOR_MGMT_AVAILABLE) +static int color_mgmt_config_copy_lut(struct NvKmsLutRamps *nvkms_lut, + struct drm_color_lut *drm_lut, + uint64_t lut_len) +{ + uint64_t i = 0; + if (lut_len != NVKMS_LUT_ARRAY_SIZE) { + return -EINVAL; + } + + /* + * Both NvKms and drm LUT values are 16-bit linear values. NvKms LUT ramps + * are in arrays in a single struct while drm LUT ramps are an array of + * structs. + */ + for (i = 0; i < lut_len; i++) { + nvkms_lut->red[i] = drm_lut[i].red; + nvkms_lut->green[i] = drm_lut[i].green; + nvkms_lut->blue[i] = drm_lut[i].blue; + } + return 0; +} + +static void color_mgmt_config_ctm_to_csc(struct NvKmsCscMatrix *nvkms_csc, + struct drm_color_ctm *drm_ctm) +{ + int y; + + /* CTM is a 3x3 matrix while ours is 3x4. Zero out the last column. */ + nvkms_csc->m[0][3] = nvkms_csc->m[1][3] = nvkms_csc->m[2][3] = 0; + + for (y = 0; y < 3; y++) { + int x; + + for (x = 0; x < 3; x++) { + /* + * Values in the CTM are encoded in S31.32 sign-magnitude fixed- + * point format, while NvKms CSC values are signed 2's-complement + * S15.16 (Ssign-extend12-3.16?) fixed-point format. + */ + NvU64 ctmVal = drm_ctm->matrix[y*3 + x]; + NvU64 signBit = ctmVal & (1ULL << 63); + NvU64 magnitude = ctmVal & ~signBit; + + /* + * Drop the low 16 bits of the fractional part and the high 17 bits + * of the integral part. Drop 17 bits to avoid corner cases where + * the highest resulting bit is a 1, causing the `cscVal = -cscVal` + * line to result in a positive number. + */ + NvS32 cscVal = (magnitude >> 16) & ((1ULL << 31) - 1); + if (signBit) { + cscVal = -cscVal; + } + + nvkms_csc->m[y][x] = cscVal; + } + } +} + +static int color_mgmt_config_set(struct nv_drm_crtc_state *nv_crtc_state, + struct NvKmsKapiHeadRequestedConfig *req_config) +{ + struct NvKmsKapiHeadModeSetConfig *modeset_config = + &req_config->modeSetConfig; + struct drm_crtc_state *crtc_state = &nv_crtc_state->base; + int ret = 0; + + struct drm_color_lut *degamma_lut = NULL; + struct drm_color_ctm *ctm = NULL; + struct drm_color_lut *gamma_lut = NULL; + uint64_t degamma_len = 0; + uint64_t gamma_len = 0; + + int i; + struct drm_plane *plane; + struct drm_plane_state *plane_state; + + /* + * According to the comment in the Linux kernel's + * drivers/gpu/drm/drm_color_mgmt.c, if any of these properties are NULL, + * that LUT or CTM needs to be changed to a linear LUT or identity matrix + * respectively. + */ + + req_config->flags.lutChanged = NV_TRUE; + if (crtc_state->degamma_lut) { + nv_crtc_state->ilut_ramps = nv_drm_calloc(1, sizeof(*nv_crtc_state->ilut_ramps)); + if (!nv_crtc_state->ilut_ramps) { + ret = -ENOMEM; + goto fail; + } + + degamma_lut = (struct drm_color_lut *)crtc_state->degamma_lut->data; + degamma_len = crtc_state->degamma_lut->length / + sizeof(struct drm_color_lut); + + if ((ret = color_mgmt_config_copy_lut(nv_crtc_state->ilut_ramps, + degamma_lut, + degamma_len)) != 0) { + goto fail; + } + + modeset_config->lut.input.specified = NV_TRUE; + modeset_config->lut.input.depth = 30; /* specify the full LUT */ + modeset_config->lut.input.start = 0; + modeset_config->lut.input.end = degamma_len - 1; + modeset_config->lut.input.pRamps = nv_crtc_state->ilut_ramps; + } else { + /* setting input.end to 0 is equivalent to disabling the LUT, which + * should be equivalent to a linear LUT */ + modeset_config->lut.input.specified = NV_TRUE; + modeset_config->lut.input.depth = 30; /* specify the full LUT */ + modeset_config->lut.input.start = 0; + modeset_config->lut.input.end = 0; + modeset_config->lut.input.pRamps = NULL; + } + + nv_drm_for_each_new_plane_in_state(crtc_state->state, plane, + plane_state, i) { + struct nv_drm_plane *nv_plane = to_nv_plane(plane); + uint32_t layer = nv_plane->layer_idx; + struct NvKmsKapiLayerRequestedConfig *layer_config; + + if (layer == NVKMS_KAPI_LAYER_INVALID_IDX || plane_state->crtc != crtc_state->crtc) { + continue; + } + layer_config = &req_config->layerRequestedConfig[layer]; + + if (layer == NVKMS_KAPI_LAYER_PRIMARY_IDX && crtc_state->ctm) { + ctm = (struct drm_color_ctm *)crtc_state->ctm->data; + + color_mgmt_config_ctm_to_csc(&layer_config->config.csc, ctm); + layer_config->config.cscUseMain = NV_FALSE; + } else { + /* When crtc_state->ctm is unset, this also sets the main layer to + * the identity matrix. + */ + layer_config->config.csc = NVKMS_IDENTITY_CSC_MATRIX; + } + layer_config->flags.cscChanged = NV_TRUE; + } + + if (crtc_state->gamma_lut) { + nv_crtc_state->olut_ramps = nv_drm_calloc(1, sizeof(*nv_crtc_state->olut_ramps)); + if (!nv_crtc_state->olut_ramps) { + ret = -ENOMEM; + goto fail; + } + + gamma_lut = (struct drm_color_lut *)crtc_state->gamma_lut->data; + gamma_len = crtc_state->gamma_lut->length / + sizeof(struct drm_color_lut); + + if ((ret = color_mgmt_config_copy_lut(nv_crtc_state->olut_ramps, + gamma_lut, + gamma_len)) != 0) { + goto fail; + } + + modeset_config->lut.output.specified = NV_TRUE; + modeset_config->lut.output.enabled = NV_TRUE; + modeset_config->lut.output.pRamps = nv_crtc_state->olut_ramps; + } else { + /* disabling the output LUT should be equivalent to setting a linear + * LUT */ + modeset_config->lut.output.specified = NV_TRUE; + modeset_config->lut.output.enabled = NV_FALSE; + modeset_config->lut.output.pRamps = NULL; + } + + return 0; + +fail: + /* free allocated state */ + nv_drm_free(nv_crtc_state->ilut_ramps); + nv_drm_free(nv_crtc_state->olut_ramps); + + /* remove dangling pointers */ + nv_crtc_state->ilut_ramps = NULL; + nv_crtc_state->olut_ramps = NULL; + modeset_config->lut.input.pRamps = NULL; + modeset_config->lut.output.pRamps = NULL; + + /* prevent attempts at reading NULLs */ + modeset_config->lut.input.specified = NV_FALSE; + modeset_config->lut.output.specified = NV_FALSE; + + return ret; +} +#endif /* NV_DRM_COLOR_MGMT_AVAILABLE */ + /** * nv_drm_crtc_atomic_check() can fail after it has modified * the 'nv_drm_crtc_state::req_config', that is fine because 'nv_drm_crtc_state' @@ -887,6 +1104,9 @@ static int nv_drm_crtc_atomic_check(struct drm_crtc *crtc, struct NvKmsKapiHeadRequestedConfig *req_config = &nv_crtc_state->req_config; int ret = 0; +#if defined(NV_DRM_COLOR_MGMT_AVAILABLE) + struct nv_drm_device *nv_dev = to_nv_device(crtc_state->crtc->dev); +#endif if (crtc_state->mode_changed) { drm_mode_to_nvkms_display_mode(&crtc_state->mode, @@ -925,6 +1145,25 @@ static int nv_drm_crtc_atomic_check(struct drm_crtc *crtc, req_config->flags.activeChanged = NV_TRUE; } +#if defined(NV_DRM_CRTC_STATE_HAS_VRR_ENABLED) + req_config->modeSetConfig.vrrEnabled = crtc_state->vrr_enabled; +#endif + +#if defined(NV_DRM_COLOR_MGMT_AVAILABLE) + if (nv_dev->drmMasterChangedSinceLastAtomicCommit && + (crtc_state->degamma_lut || + crtc_state->ctm || + crtc_state->gamma_lut)) { + + crtc_state->color_mgmt_changed = NV_TRUE; + } + if (crtc_state->color_mgmt_changed) { + if ((ret = color_mgmt_config_set(nv_crtc_state, req_config)) != 0) { + return ret; + } + } +#endif + return ret; } @@ -1156,6 +1395,8 @@ nv_drm_plane_create(struct drm_device *dev, plane, validLayerRRTransforms); + nv_drm_free(formats); + return plane; failed_plane_init: @@ -1220,6 +1461,22 @@ static struct drm_crtc *__nv_drm_crtc_create(struct nv_drm_device *nv_dev, drm_crtc_helper_add(&nv_crtc->base, &nv_crtc_helper_funcs); +#if defined(NV_DRM_COLOR_MGMT_AVAILABLE) +#if defined(NV_DRM_CRTC_ENABLE_COLOR_MGMT_PRESENT) + drm_crtc_enable_color_mgmt(&nv_crtc->base, NVKMS_LUT_ARRAY_SIZE, true, + NVKMS_LUT_ARRAY_SIZE); +#else + drm_helper_crtc_enable_color_mgmt(&nv_crtc->base, NVKMS_LUT_ARRAY_SIZE, + NVKMS_LUT_ARRAY_SIZE); +#endif + ret = drm_mode_crtc_set_gamma_size(&nv_crtc->base, NVKMS_LUT_ARRAY_SIZE); + if (ret != 0) { + NV_DRM_DEV_LOG_WARN( + nv_dev, + "Failed to initialize legacy gamma support for head %u", head); + } +#endif + return &nv_crtc->base; failed_init_crtc: @@ -1328,10 +1585,16 @@ static void NvKmsKapiCrcsToDrm(const struct NvKmsKapiCrcs *crcs, { drmCrcs->outputCrc32.value = crcs->outputCrc32.value; drmCrcs->outputCrc32.supported = crcs->outputCrc32.supported; + drmCrcs->outputCrc32.__pad0 = 0; + drmCrcs->outputCrc32.__pad1 = 0; drmCrcs->rasterGeneratorCrc32.value = crcs->rasterGeneratorCrc32.value; drmCrcs->rasterGeneratorCrc32.supported = crcs->rasterGeneratorCrc32.supported; + drmCrcs->rasterGeneratorCrc32.__pad0 = 0; + drmCrcs->rasterGeneratorCrc32.__pad1 = 0; drmCrcs->compositorCrc32.value = crcs->compositorCrc32.value; drmCrcs->compositorCrc32.supported = crcs->compositorCrc32.supported; + drmCrcs->compositorCrc32.__pad0 = 0; + drmCrcs->compositorCrc32.__pad1 = 0; } int nv_drm_get_crtc_crc32_v2_ioctl(struct drm_device *dev, diff --git a/kernel-open/nvidia-drm/nvidia-drm-crtc.h b/kernel-open/nvidia-drm/nvidia-drm-crtc.h index 2562e87c69..56ec671510 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-crtc.h +++ b/kernel-open/nvidia-drm/nvidia-drm-crtc.h @@ -129,6 +129,9 @@ struct nv_drm_crtc_state { */ struct NvKmsKapiHeadRequestedConfig req_config; + struct NvKmsLutRamps *ilut_ramps; + struct NvKmsLutRamps *olut_ramps; + /** * @nv_flip: * diff --git a/kernel-open/nvidia-drm/nvidia-drm-drv.c b/kernel-open/nvidia-drm/nvidia-drm-drv.c index 6c68d82421..554c51a1e7 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-drv.c +++ b/kernel-open/nvidia-drm/nvidia-drm-drv.c @@ -44,6 +44,10 @@ #include #endif +#if defined(NV_DRM_DRM_ATOMIC_UAPI_H_PRESENT) +#include +#endif + #if defined(NV_DRM_DRM_VBLANK_H_PRESENT) #include #endif @@ -60,6 +64,15 @@ #include #endif +#if defined(NV_DRM_FBDEV_GENERIC_AVAILABLE) +#include +#include +#endif + +#if defined(NV_DRM_DRM_FBDEV_GENERIC_H_PRESENT) +#include +#endif + #include /* @@ -84,6 +97,11 @@ #include #endif +static int nv_drm_revoke_modeset_permission(struct drm_device *dev, + struct drm_file *filep, + NvU32 dpyId); +static int nv_drm_revoke_sub_ownership(struct drm_device *dev); + static struct nv_drm_device *dev_list = NULL; static const char* nv_get_input_colorspace_name( @@ -460,6 +478,11 @@ static int nv_drm_load(struct drm_device *dev, unsigned long flags) nv_dev->supportsSyncpts = resInfo.caps.supportsSyncpts; + nv_dev->semsurf_stride = resInfo.caps.semsurf.stride; + + nv_dev->semsurf_max_submitted_offset = + resInfo.caps.semsurf.maxSubmittedOffset; + #if defined(NV_DRM_FORMAT_MODIFIERS_PRESENT) gen = nv_dev->pageKindGeneration; kind = nv_dev->genericPageKind; @@ -546,6 +569,8 @@ static void __nv_drm_unload(struct drm_device *dev) mutex_lock(&nv_dev->lock); + WARN_ON(nv_dev->subOwnershipGranted); + /* Disable event handling */ atomic_set(&nv_dev->enable_event_handling, false); @@ -595,9 +620,15 @@ static int __nv_drm_master_set(struct drm_device *dev, { struct nv_drm_device *nv_dev = to_nv_device(dev); - if (!nvKms->grabOwnership(nv_dev->pDevice)) { + /* + * If this device is driving a framebuffer, then nvidia-drm already has + * modeset ownership. Otherwise, grab ownership now. + */ + if (!nv_dev->hasFramebufferConsole && + !nvKms->grabOwnership(nv_dev->pDevice)) { return -EINVAL; } + nv_dev->drmMasterChangedSinceLastAtomicCommit = NV_TRUE; return 0; } @@ -631,6 +662,9 @@ void nv_drm_master_drop(struct drm_device *dev, struct drm_file *file_priv) struct nv_drm_device *nv_dev = to_nv_device(dev); int err; + nv_drm_revoke_modeset_permission(dev, file_priv, 0); + nv_drm_revoke_sub_ownership(dev); + /* * After dropping nvkms modeset onwership, it is not guaranteed that * drm and nvkms modeset state will remain in sync. Therefore, disable @@ -655,7 +689,9 @@ void nv_drm_master_drop(struct drm_device *dev, struct drm_file *file_priv) drm_modeset_unlock_all(dev); - nvKms->releaseOwnership(nv_dev->pDevice); + if (!nv_dev->hasFramebufferConsole) { + nvKms->releaseOwnership(nv_dev->pDevice); + } } #endif /* NV_DRM_ATOMIC_MODESET_AVAILABLE */ @@ -693,15 +729,24 @@ static int nv_drm_get_dev_info_ioctl(struct drm_device *dev, params->gpu_id = nv_dev->gpu_info.gpu_id; params->primary_index = dev->primary->index; + params->generic_page_kind = 0; + params->page_kind_generation = 0; + params->sector_layout = 0; + params->supports_sync_fd = false; + params->supports_semsurf = false; + #if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE) params->generic_page_kind = nv_dev->genericPageKind; params->page_kind_generation = nv_dev->pageKindGeneration; params->sector_layout = nv_dev->sectorLayout; -#else - params->generic_page_kind = 0; - params->page_kind_generation = 0; - params->sector_layout = 0; -#endif + /* Semaphore surfaces are only supported if the modeset = 1 parameter is set */ + if ((nv_dev->pDevice) != NULL && (nv_dev->semsurf_stride != 0)) { + params->supports_semsurf = true; +#if defined(NV_SYNC_FILE_GET_FENCE_PRESENT) + params->supports_sync_fd = true; +#endif /* defined(NV_SYNC_FILE_GET_FENCE_PRESENT) */ + } +#endif /* defined(NV_DRM_ATOMIC_MODESET_AVAILABLE) */ return 0; } @@ -833,10 +878,10 @@ static NvU32 nv_drm_get_head_bit_from_connector(struct drm_connector *connector) return 0; } -static int nv_drm_grant_permission_ioctl(struct drm_device *dev, void *data, - struct drm_file *filep) +static int nv_drm_grant_modeset_permission(struct drm_device *dev, + struct drm_nvidia_grant_permissions_params *params, + struct drm_file *filep) { - struct drm_nvidia_grant_permissions_params *params = data; struct nv_drm_device *nv_dev = to_nv_device(dev); struct nv_drm_connector *target_nv_connector = NULL; struct nv_drm_crtc *target_nv_crtc = NULL; @@ -958,26 +1003,102 @@ static int nv_drm_grant_permission_ioctl(struct drm_device *dev, void *data, return ret; } -static bool nv_drm_revoke_connector(struct nv_drm_device *nv_dev, - struct nv_drm_connector *nv_connector) +static int nv_drm_grant_sub_ownership(struct drm_device *dev, + struct drm_nvidia_grant_permissions_params *params) { - bool ret = true; + int ret = -EINVAL; + struct nv_drm_device *nv_dev = to_nv_device(dev); + struct drm_modeset_acquire_ctx *pctx; +#if NV_DRM_MODESET_LOCK_ALL_END_ARGUMENT_COUNT == 3 + struct drm_modeset_acquire_ctx ctx; + DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE, + ret); + pctx = &ctx; +#else + mutex_lock(&dev->mode_config.mutex); + pctx = dev->mode_config.acquire_ctx; +#endif + + if (nv_dev->subOwnershipGranted || + !nvKms->grantSubOwnership(params->fd, nv_dev->pDevice)) { + goto done; + } + + /* + * When creating an ownership grant, shut down all heads and disable flip + * notifications. + */ + ret = nv_drm_atomic_helper_disable_all(dev, pctx); + if (ret != 0) { + NV_DRM_DEV_LOG_ERR( + nv_dev, + "nv_drm_atomic_helper_disable_all failed with error code %d!", + ret); + } + + atomic_set(&nv_dev->enable_event_handling, false); + nv_dev->subOwnershipGranted = NV_TRUE; + + ret = 0; + +done: +#if NV_DRM_MODESET_LOCK_ALL_END_ARGUMENT_COUNT == 3 + DRM_MODESET_LOCK_ALL_END(dev, ctx, ret); +#else + mutex_unlock(&dev->mode_config.mutex); +#endif + return 0; +} + +static int nv_drm_grant_permission_ioctl(struct drm_device *dev, void *data, + struct drm_file *filep) +{ + struct drm_nvidia_grant_permissions_params *params = data; + + if (params->type == NV_DRM_PERMISSIONS_TYPE_MODESET) { + return nv_drm_grant_modeset_permission(dev, params, filep); + } else if (params->type == NV_DRM_PERMISSIONS_TYPE_SUB_OWNER) { + return nv_drm_grant_sub_ownership(dev, params); + } + + return -EINVAL; +} + +static int +nv_drm_atomic_disable_connector(struct drm_atomic_state *state, + struct nv_drm_connector *nv_connector) +{ + struct drm_crtc_state *crtc_state; + struct drm_connector_state *connector_state; + int ret = 0; + if (nv_connector->modeset_permission_crtc) { - if (nv_connector->nv_detected_encoder) { - ret = nvKms->revokePermissions( - nv_dev->pDevice, nv_connector->modeset_permission_crtc->head, - nv_connector->nv_detected_encoder->hDisplay); + crtc_state = drm_atomic_get_crtc_state( + state, &nv_connector->modeset_permission_crtc->base); + if (!crtc_state) { + return -EINVAL; + } + + crtc_state->active = false; + ret = drm_atomic_set_mode_prop_for_crtc(crtc_state, NULL); + if (ret < 0) { + return ret; } - nv_connector->modeset_permission_crtc->modeset_permission_filep = NULL; - nv_connector->modeset_permission_crtc = NULL; } - nv_connector->modeset_permission_filep = NULL; - return ret; + + connector_state = drm_atomic_get_connector_state(state, &nv_connector->base); + if (!connector_state) { + return -EINVAL; + } + + return drm_atomic_set_crtc_for_connector(connector_state, NULL); } -static int nv_drm_revoke_permission(struct drm_device *dev, - struct drm_file *filep, NvU32 dpyId) +static int nv_drm_revoke_modeset_permission(struct drm_device *dev, + struct drm_file *filep, NvU32 dpyId) { + struct drm_modeset_acquire_ctx *pctx; + struct drm_atomic_state *state; struct drm_connector *connector; struct drm_crtc *crtc; int ret = 0; @@ -988,10 +1109,19 @@ static int nv_drm_revoke_permission(struct drm_device *dev, struct drm_modeset_acquire_ctx ctx; DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE, ret); + pctx = &ctx; #else mutex_lock(&dev->mode_config.mutex); + pctx = dev->mode_config.acquire_ctx; #endif + state = drm_atomic_state_alloc(dev); + if (!state) { + ret = -ENOMEM; + goto done; + } + state->acquire_ctx = pctx; + /* * If dpyId is set, only revoke those specific resources. Otherwise, * it is from closing the file so revoke all resources for that filep. @@ -1003,10 +1133,13 @@ static int nv_drm_revoke_permission(struct drm_device *dev, struct nv_drm_connector *nv_connector = to_nv_connector(connector); if (nv_connector->modeset_permission_filep == filep && (!dpyId || nv_drm_connector_is_dpy_id(connector, dpyId))) { - if (!nv_drm_connector_revoke_permissions(dev, nv_connector)) { - ret = -EINVAL; - // Continue trying to revoke as much as possible. + ret = nv_drm_atomic_disable_connector(state, nv_connector); + if (ret < 0) { + goto done; } + + // Continue trying to revoke as much as possible. + nv_drm_connector_revoke_permissions(dev, nv_connector); } } #if defined(NV_DRM_CONNECTOR_LIST_ITER_PRESENT) @@ -1020,6 +1153,25 @@ static int nv_drm_revoke_permission(struct drm_device *dev, } } + ret = drm_atomic_commit(state); +done: +#if defined(NV_DRM_ATOMIC_STATE_REF_COUNTING_PRESENT) + drm_atomic_state_put(state); +#else + if (ret != 0) { + drm_atomic_state_free(state); + } else { + /* + * In case of success, drm_atomic_commit() takes care to cleanup and + * free @state. + * + * Comment placed above drm_atomic_commit() says: The caller must not + * free or in any other way access @state. If the function fails then + * the caller must clean up @state itself. + */ + } +#endif + #if NV_DRM_MODESET_LOCK_ALL_END_ARGUMENT_COUNT == 3 DRM_MODESET_LOCK_ALL_END(dev, ctx, ret); #else @@ -1029,14 +1181,55 @@ static int nv_drm_revoke_permission(struct drm_device *dev, return ret; } +static int nv_drm_revoke_sub_ownership(struct drm_device *dev) +{ + int ret = -EINVAL; + struct nv_drm_device *nv_dev = to_nv_device(dev); +#if NV_DRM_MODESET_LOCK_ALL_END_ARGUMENT_COUNT == 3 + struct drm_modeset_acquire_ctx ctx; + DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE, + ret); +#else + mutex_lock(&dev->mode_config.mutex); +#endif + + if (!nv_dev->subOwnershipGranted) { + goto done; + } + + if (!nvKms->revokeSubOwnership(nv_dev->pDevice)) { + NV_DRM_DEV_LOG_ERR(nv_dev, "Failed to revoke sub-ownership from NVKMS"); + goto done; + } + + nv_dev->subOwnershipGranted = NV_FALSE; + atomic_set(&nv_dev->enable_event_handling, true); + ret = 0; + +done: +#if NV_DRM_MODESET_LOCK_ALL_END_ARGUMENT_COUNT == 3 + DRM_MODESET_LOCK_ALL_END(dev, ctx, ret); +#else + mutex_unlock(&dev->mode_config.mutex); +#endif + return ret; +} + static int nv_drm_revoke_permission_ioctl(struct drm_device *dev, void *data, struct drm_file *filep) { struct drm_nvidia_revoke_permissions_params *params = data; - if (!params->dpyId) { - return -EINVAL; + + if (params->type == NV_DRM_PERMISSIONS_TYPE_MODESET) { + if (!params->dpyId) { + return -EINVAL; + } + return nv_drm_revoke_modeset_permission(dev, filep, params->dpyId); + } else if (params->type == NV_DRM_PERMISSIONS_TYPE_SUB_OWNER) { + return nv_drm_revoke_sub_ownership(dev); } - return nv_drm_revoke_permission(dev, filep, params->dpyId); + + return -EINVAL; } static void nv_drm_postclose(struct drm_device *dev, struct drm_file *filep) @@ -1051,7 +1244,7 @@ static void nv_drm_postclose(struct drm_device *dev, struct drm_file *filep) dev->mode_config.num_connector > 0 && dev->mode_config.connector_list.next != NULL && dev->mode_config.connector_list.prev != NULL) { - nv_drm_revoke_permission(dev, filep, 0); + nv_drm_revoke_modeset_permission(dev, filep, 0); } } #endif /* NV_DRM_ATOMIC_MODESET_AVAILABLE */ @@ -1310,6 +1503,18 @@ static const struct drm_ioctl_desc nv_drm_ioctls[] = { DRM_IOCTL_DEF_DRV(NVIDIA_GEM_PRIME_FENCE_ATTACH, nv_drm_gem_prime_fence_attach_ioctl, DRM_RENDER_ALLOW|DRM_UNLOCKED), + DRM_IOCTL_DEF_DRV(NVIDIA_SEMSURF_FENCE_CTX_CREATE, + nv_drm_semsurf_fence_ctx_create_ioctl, + DRM_RENDER_ALLOW|DRM_UNLOCKED), + DRM_IOCTL_DEF_DRV(NVIDIA_SEMSURF_FENCE_CREATE, + nv_drm_semsurf_fence_create_ioctl, + DRM_RENDER_ALLOW|DRM_UNLOCKED), + DRM_IOCTL_DEF_DRV(NVIDIA_SEMSURF_FENCE_WAIT, + nv_drm_semsurf_fence_wait_ioctl, + DRM_RENDER_ALLOW|DRM_UNLOCKED), + DRM_IOCTL_DEF_DRV(NVIDIA_SEMSURF_FENCE_ATTACH, + nv_drm_semsurf_fence_attach_ioctl, + DRM_RENDER_ALLOW|DRM_UNLOCKED), #endif DRM_IOCTL_DEF_DRV(NVIDIA_GET_CLIENT_CAPABILITY, @@ -1513,6 +1718,30 @@ static void nv_drm_register_drm_device(const nv_gpu_info_t *gpu_info) goto failed_drm_register; } +#if defined(NV_DRM_FBDEV_GENERIC_AVAILABLE) + if (nv_drm_fbdev_module_param && + drm_core_check_feature(dev, DRIVER_MODESET)) { + + if (!nvKms->grabOwnership(nv_dev->pDevice)) { + NV_DRM_DEV_LOG_ERR(nv_dev, "Failed to grab NVKMS modeset ownership"); + goto failed_grab_ownership; + } + + if (device->bus == &pci_bus_type) { + struct pci_dev *pdev = to_pci_dev(device); + +#if defined(NV_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_HAS_DRIVER_ARG) + drm_aperture_remove_conflicting_pci_framebuffers(pdev, &nv_drm_driver); +#else + drm_aperture_remove_conflicting_pci_framebuffers(pdev, nv_drm_driver.name); +#endif + } + drm_fbdev_generic_setup(dev, 32); + + nv_dev->hasFramebufferConsole = NV_TRUE; + } +#endif /* defined(NV_DRM_FBDEV_GENERIC_AVAILABLE) */ + /* Add NVIDIA-DRM device into list */ nv_dev->next = dev_list; @@ -1520,6 +1749,12 @@ static void nv_drm_register_drm_device(const nv_gpu_info_t *gpu_info) return; /* Success */ +#if defined(NV_DRM_FBDEV_GENERIC_AVAILABLE) +failed_grab_ownership: + + drm_dev_unregister(dev); +#endif + failed_drm_register: nv_drm_dev_free(dev); @@ -1582,9 +1817,16 @@ void nv_drm_remove_devices(void) { while (dev_list != NULL) { struct nv_drm_device *next = dev_list->next; + struct drm_device *dev = dev_list->dev; - drm_dev_unregister(dev_list->dev); - nv_drm_dev_free(dev_list->dev); +#if defined(NV_DRM_FBDEV_GENERIC_AVAILABLE) + if (dev_list->hasFramebufferConsole) { + drm_atomic_helper_shutdown(dev); + nvKms->releaseOwnership(dev_list->pDevice); + } +#endif + drm_dev_unregister(dev); + nv_drm_dev_free(dev); nv_drm_free(dev_list); diff --git a/kernel-open/nvidia-drm/nvidia-drm-fence.c b/kernel-open/nvidia-drm/nvidia-drm-fence.c index 97dfff8d74..23298ad12c 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-fence.c +++ b/kernel-open/nvidia-drm/nvidia-drm-fence.c @@ -38,6 +38,8 @@ #include "nvidia-dma-fence-helper.h" +#define NV_DRM_SEMAPHORE_SURFACE_FENCE_MAX_TIMEOUT_MS 5000 + struct nv_drm_fence_context; struct nv_drm_fence_context_ops { @@ -45,17 +47,19 @@ struct nv_drm_fence_context_ops { }; struct nv_drm_fence_context { + struct nv_drm_gem_object base; + const struct nv_drm_fence_context_ops *ops; struct nv_drm_device *nv_dev; - uint32_t context; + uint64_t context; + + NvU64 fenceSemIndex; /* Index into semaphore surface */ }; struct nv_drm_prime_fence_context { struct nv_drm_fence_context base; - NvU64 fenceSemIndex; /* Index into semaphore surface */ - /* Mapped semaphore surface */ struct NvKmsKapiMemory *pSemSurface; NvU32 *pLinearAddress; @@ -181,7 +185,7 @@ static void nv_drm_gem_prime_fence_event /* Index into surface with 16 byte stride */ unsigned int seqno = *((nv_fence_context->pLinearAddress) + - (nv_fence_context->fenceSemIndex * 4)); + (nv_fence_context->base.fenceSemIndex * 4)); if (nv_fence->base.seqno > seqno) { /* @@ -199,8 +203,8 @@ static void nv_drm_gem_prime_fence_event } static inline struct nv_drm_prime_fence_context* -to_prime_fence_context(struct nv_drm_fence_context *nv_fence_context) { - return (struct nv_drm_prime_fence_context *)nv_fence_context; +to_nv_prime_fence_context(struct nv_drm_fence_context *nv_fence_context) { + return container_of(nv_fence_context, struct nv_drm_prime_fence_context, base); } static void __nv_drm_prime_fence_context_destroy( @@ -208,7 +212,7 @@ static void __nv_drm_prime_fence_context_destroy( { struct nv_drm_device *nv_dev = nv_fence_context->nv_dev; struct nv_drm_prime_fence_context *nv_prime_fence_context = - to_prime_fence_context(nv_fence_context); + to_nv_prime_fence_context(nv_fence_context); /* * Free channel event before destroying the fence context, otherwise event @@ -293,9 +297,9 @@ __nv_drm_prime_fence_context_new( .base.ops = &nv_drm_prime_fence_context_ops, .base.nv_dev = nv_dev, .base.context = nv_dma_fence_context_alloc(1), + .base.fenceSemIndex = p->index, .pSemSurface = pSemSurface, .pLinearAddress = pLinearAddress, - .fenceSemIndex = p->index, }; INIT_LIST_HEAD(&nv_prime_fence_context->pending); @@ -391,47 +395,37 @@ int nv_drm_fence_supported_ioctl(struct drm_device *dev, return nv_dev->pDevice ? 0 : -EINVAL; } -struct nv_drm_gem_fence_context { - struct nv_drm_gem_object base; - struct nv_drm_fence_context *nv_fence_context; -}; - -static inline struct nv_drm_gem_fence_context *to_gem_fence_context( +static inline struct nv_drm_fence_context *to_nv_fence_context( struct nv_drm_gem_object *nv_gem) { if (nv_gem != NULL) { - return container_of(nv_gem, struct nv_drm_gem_fence_context, base); + return container_of(nv_gem, struct nv_drm_fence_context, base); } return NULL; } /* - * Tear down of the 'struct nv_drm_gem_fence_context' object is not expected + * Tear down of the 'struct nv_drm_fence_context' object is not expected * to be happen from any worker thread, if that happen it causes dead-lock * because tear down sequence calls to flush all existing * worker thread. */ static void -__nv_drm_gem_fence_context_free(struct nv_drm_gem_object *nv_gem) +__nv_drm_fence_context_gem_free(struct nv_drm_gem_object *nv_gem) { - struct nv_drm_gem_fence_context *nv_gem_fence_context = - to_gem_fence_context(nv_gem); - struct nv_drm_fence_context *nv_fence_context = - nv_gem_fence_context->nv_fence_context; + struct nv_drm_fence_context *nv_fence_context = to_nv_fence_context(nv_gem); nv_fence_context->ops->destroy(nv_fence_context); - - nv_drm_free(nv_gem_fence_context); } -const struct nv_drm_gem_object_funcs nv_gem_fence_context_ops = { - .free = __nv_drm_gem_fence_context_free, +const struct nv_drm_gem_object_funcs nv_fence_context_gem_ops = { + .free = __nv_drm_fence_context_gem_free, }; static inline -struct nv_drm_gem_fence_context * -__nv_drm_gem_object_fence_context_lookup( +struct nv_drm_fence_context * +__nv_drm_fence_context_lookup( struct drm_device *dev, struct drm_file *filp, u32 handle) @@ -439,43 +433,31 @@ __nv_drm_gem_object_fence_context_lookup( struct nv_drm_gem_object *nv_gem = nv_drm_gem_object_lookup(dev, filp, handle); - if (nv_gem != NULL && nv_gem->ops != &nv_gem_fence_context_ops) { + if (nv_gem != NULL && nv_gem->ops != &nv_fence_context_gem_ops) { nv_drm_gem_object_unreference_unlocked(nv_gem); return NULL; } - return to_gem_fence_context(nv_gem); + return to_nv_fence_context(nv_gem); } static int -__nv_drm_gem_fence_context_create(struct drm_device *dev, - struct nv_drm_fence_context *nv_fence_context, - u32 *handle, - struct drm_file *filep) +__nv_drm_fence_context_gem_init(struct drm_device *dev, + struct nv_drm_fence_context *nv_fence_context, + u32 *handle, + struct drm_file *filep) { struct nv_drm_device *nv_dev = to_nv_device(dev); - struct nv_drm_gem_fence_context *nv_gem_fence_context = NULL; - - if ((nv_gem_fence_context = nv_drm_calloc( - 1, - sizeof(struct nv_drm_gem_fence_context))) == NULL) { - goto done; - } - - nv_gem_fence_context->nv_fence_context = nv_fence_context; nv_drm_gem_object_init(nv_dev, - &nv_gem_fence_context->base, - &nv_gem_fence_context_ops, + &nv_fence_context->base, + &nv_fence_context_gem_ops, 0 /* size */, NULL /* pMemory */); return nv_drm_gem_handle_create_drop_reference(filep, - &nv_gem_fence_context->base, + &nv_fence_context->base, handle); - -done: - return -ENOMEM; } int nv_drm_prime_fence_context_create_ioctl(struct drm_device *dev, @@ -491,10 +473,10 @@ int nv_drm_prime_fence_context_create_ioctl(struct drm_device *dev, goto done; } - err = __nv_drm_gem_fence_context_create(dev, - &nv_prime_fence_context->base, - &p->handle, - filep); + err = __nv_drm_fence_context_gem_init(dev, + &nv_prime_fence_context->base, + &p->handle, + filep); if (err) { __nv_drm_prime_fence_context_destroy(&nv_prime_fence_context->base); } @@ -505,6 +487,31 @@ int nv_drm_prime_fence_context_create_ioctl(struct drm_device *dev, return -ENOMEM; } +static int __nv_drm_gem_attach_fence(struct nv_drm_gem_object *nv_gem, + nv_dma_fence_t *fence, + bool shared) +{ + nv_dma_resv_t *resv = nv_drm_gem_res_obj(nv_gem); + int ret; + + nv_dma_resv_lock(resv, NULL); + + ret = nv_dma_resv_reserve_fences(resv, 1, shared); + if (ret == 0) { + if (shared) { + nv_dma_resv_add_shared_fence(resv, fence); + } else { + nv_dma_resv_add_excl_fence(resv, fence); + } + } else { + NV_DRM_LOG_ERR("Failed to reserve fence. Error code: %d", ret); + } + + nv_dma_resv_unlock(resv); + + return ret; +} + int nv_drm_gem_prime_fence_attach_ioctl(struct drm_device *dev, void *data, struct drm_file *filep) { @@ -513,10 +520,13 @@ int nv_drm_gem_prime_fence_attach_ioctl(struct drm_device *dev, struct drm_nvidia_gem_prime_fence_attach_params *p = data; struct nv_drm_gem_object *nv_gem; - struct nv_drm_gem_fence_context *nv_gem_fence_context; - + struct nv_drm_fence_context *nv_fence_context; nv_dma_fence_t *fence; - nv_dma_resv_t *resv; + + if (p->__pad != 0) { + NV_DRM_DEV_LOG_ERR(nv_dev, "Padding fields must be zeroed"); + goto done; + } nv_gem = nv_drm_gem_object_lookup(nv_dev->dev, filep, p->handle); @@ -529,7 +539,7 @@ int nv_drm_gem_prime_fence_attach_ioctl(struct drm_device *dev, goto done; } - if((nv_gem_fence_context = __nv_drm_gem_object_fence_context_lookup( + if((nv_fence_context = __nv_drm_fence_context_lookup( nv_dev->dev, filep, p->fence_context_handle)) == NULL) { @@ -542,7 +552,7 @@ int nv_drm_gem_prime_fence_attach_ioctl(struct drm_device *dev, goto fence_context_lookup_failed; } - if (nv_gem_fence_context->nv_fence_context->ops != + if (nv_fence_context->ops != &nv_drm_prime_fence_context_ops) { NV_DRM_DEV_LOG_ERR( @@ -554,7 +564,7 @@ int nv_drm_gem_prime_fence_attach_ioctl(struct drm_device *dev, } fence = __nv_drm_prime_fence_context_create_fence( - to_prime_fence_context(nv_gem_fence_context->nv_fence_context), + to_nv_prime_fence_context(nv_fence_context), p->sem_thresh); if (IS_ERR(fence)) { @@ -567,31 +577,1235 @@ int nv_drm_gem_prime_fence_attach_ioctl(struct drm_device *dev, goto fence_context_create_fence_failed; } - resv = nv_drm_gem_res_obj(nv_gem); + ret = __nv_drm_gem_attach_fence(nv_gem, fence, true /* exclusive */); - nv_dma_resv_lock(resv, NULL); + nv_dma_fence_put(fence); - ret = nv_dma_resv_reserve_fences(resv, 1, false); - if (ret == 0) { - nv_dma_resv_add_excl_fence(resv, fence); +fence_context_create_fence_failed: + nv_drm_gem_object_unreference_unlocked(&nv_fence_context->base); + +fence_context_lookup_failed: + nv_drm_gem_object_unreference_unlocked(nv_gem); + +done: + return ret; +} + +struct nv_drm_semsurf_fence { + nv_dma_fence_t base; + spinlock_t lock; + + /* + * When unsignaled, node in the associated fence context's pending fence + * list. The list holds a reference to the fence + */ + struct list_head pending_node; + +#if !defined(NV_DMA_FENCE_OPS_HAS_USE_64BIT_SEQNO) + /* 64-bit version of base.seqno on kernels with 32-bit fence seqno */ + NvU64 wait_value; +#endif + + /* + * Raw absolute kernel time (time domain and scale are treated as opaque) + * when this fence times out. + */ + unsigned long timeout; +}; + +struct nv_drm_semsurf_fence_callback { + struct nv_drm_semsurf_fence_ctx *ctx; + nv_drm_work work; + NvU64 wait_value; +}; + +struct nv_drm_sync_fd_wait_data { + nv_dma_fence_cb_t dma_fence_cb; + struct nv_drm_semsurf_fence_ctx *ctx; + nv_drm_work work; /* Deferred second half of fence wait callback */ + + /* Could use a lockless list data structure here instead */ + struct list_head pending_node; + + NvU64 pre_wait_value; + NvU64 post_wait_value; +}; + +struct nv_drm_semsurf_fence_ctx { + struct nv_drm_fence_context base; + + /* The NVKMS KAPI reference to the context's semaphore surface */ + struct NvKmsKapiSemaphoreSurface *pSemSurface; + + /* CPU mapping of the semaphore slot values */ + union { + volatile void *pVoid; + volatile NvU32 *p32; + volatile NvU64 *p64; + } pSemMapping; + volatile NvU64 *pMaxSubmittedMapping; + + /* work thread for fence timeouts and waits */ + nv_drm_workthread worker; + + /* Timeout timer and associated workthread work */ + nv_drm_timer timer; + nv_drm_work timeout_work; + + /* Protects access to everything below */ + spinlock_t lock; + + /* List of pending fences which are not yet signaled */ + struct list_head pending_fences; + + /* List of pending fence wait operations */ + struct list_head pending_waits; + + /* + * Tracking data for the single in-flight callback associated with this + * context. Either both pointers will be valid, or both will be NULL. + * + * Note it is not safe to dereference these values outside of the context + * lock unless it is certain the associated callback is not yet active, + * or has been canceled. Their memory is owned by the callback itself as + * soon as it is registered. Subtly, this means these variables can not + * be used as output parameters to the function that registers the callback. + */ + struct { + struct nv_drm_semsurf_fence_callback *local; + struct NvKmsKapiSemaphoreSurfaceCallback *nvKms; + } callback; + + /* + * Wait value associated with either the above or a being-registered + * callback. May differ from callback->local->wait_value if it is the + * latter. Zero if no callback is currently needed. + */ + NvU64 current_wait_value; +}; + +static inline struct nv_drm_semsurf_fence_ctx* +to_semsurf_fence_ctx( + struct nv_drm_fence_context *nv_fence_context +) +{ + return container_of(nv_fence_context, + struct nv_drm_semsurf_fence_ctx, + base); +} + +static inline NvU64 +__nv_drm_get_semsurf_fence_seqno(const struct nv_drm_semsurf_fence *nv_fence) +{ +#if defined(NV_DMA_FENCE_OPS_HAS_USE_64BIT_SEQNO) + return nv_fence->base.seqno; +#else + return nv_fence->wait_value; +#endif +} + +#ifndef READ_ONCE +#define READ_ONCE(x) ACCESS_ONCE(x) +#endif + +static inline NvU64 +__nv_drm_get_semsurf_ctx_seqno(struct nv_drm_semsurf_fence_ctx *ctx) +{ + NvU64 semVal; + + if (ctx->pMaxSubmittedMapping) { + /* 32-bit GPU semaphores */ + NvU64 maxSubmitted = READ_ONCE(*ctx->pMaxSubmittedMapping); + + /* + * Must happen after the max submitted read! See + * NvTimeSemFermiGetPayload() for full details. + */ + semVal = READ_ONCE(*ctx->pSemMapping.p32); + + if ((maxSubmitted & 0xFFFFFFFFull) < semVal) { + maxSubmitted -= 0x100000000ull; + } + + semVal |= (maxSubmitted & 0xffffffff00000000ull); } else { + /* 64-bit GPU semaphores */ + semVal = READ_ONCE(*ctx->pSemMapping.p64); + } + + return semVal; +} + +static void +__nv_drm_semsurf_force_complete_pending(struct nv_drm_semsurf_fence_ctx *ctx) +{ + unsigned long flags; + + /* + * No locks are needed for the pending_fences list. This code runs after all + * other possible references to the fence context have been removed. The + * fences have their own individual locks to protect themselves. + */ + while (!list_empty(&ctx->pending_fences)) { + struct nv_drm_semsurf_fence *nv_fence = list_first_entry( + &ctx->pending_fences, + typeof(*nv_fence), + pending_node); + nv_dma_fence_t *fence = &nv_fence->base; + + list_del(&nv_fence->pending_node); + + nv_dma_fence_set_error(fence, -ETIMEDOUT); + nv_dma_fence_signal(fence); + + /* Remove the pending list's reference */ + nv_dma_fence_put(fence); + } + + /* + * The pending waits are also referenced by the fences they are waiting on, + * but those fences are guaranteed to complete in finite time. Just keep the + * the context alive until they do so. + */ + spin_lock_irqsave(&ctx->lock, flags); + while (!list_empty(&ctx->pending_waits)) { + spin_unlock_irqrestore(&ctx->lock, flags); + nv_drm_yield(); + spin_lock_irqsave(&ctx->lock, flags); + } + spin_unlock_irqrestore(&ctx->lock, flags); +} + +/* Forward declaration */ +static void +__nv_drm_semsurf_ctx_reg_callbacks(struct nv_drm_semsurf_fence_ctx *ctx); + +static void +__nv_drm_semsurf_ctx_fence_callback_work(void *data) +{ + struct nv_drm_semsurf_fence_callback *callback = data; + + __nv_drm_semsurf_ctx_reg_callbacks(callback->ctx); + + nv_drm_free(callback); +} + +static struct nv_drm_semsurf_fence_callback* +__nv_drm_semsurf_new_callback(struct nv_drm_semsurf_fence_ctx *ctx) +{ + struct nv_drm_semsurf_fence_callback *newCallback = + nv_drm_calloc(1, sizeof(*newCallback)); + + if (!newCallback) { + return NULL; + } + + newCallback->ctx = ctx; + nv_drm_workthread_work_init(&newCallback->work, + __nv_drm_semsurf_ctx_fence_callback_work, + newCallback); + + return newCallback; +} + +static void +__nv_drm_semsurf_ctx_process_completed(struct nv_drm_semsurf_fence_ctx *ctx, + NvU64 *newWaitValueOut, + unsigned long *newTimeoutOut) +{ + struct list_head finished; + struct list_head timed_out; + struct nv_drm_semsurf_fence *nv_fence; + nv_dma_fence_t *fence; + NvU64 currentSeqno = __nv_drm_get_semsurf_ctx_seqno(ctx); + NvU64 fenceSeqno = 0; + unsigned long flags; + unsigned long fenceTimeout = 0; + unsigned long now = nv_drm_timer_now(); + + INIT_LIST_HEAD(&finished); + INIT_LIST_HEAD(&timed_out); + + spin_lock_irqsave(&ctx->lock, flags); + + while (!list_empty(&ctx->pending_fences)) { + nv_fence = list_first_entry(&ctx->pending_fences, + typeof(*nv_fence), + pending_node); + + fenceSeqno = __nv_drm_get_semsurf_fence_seqno(nv_fence); + fenceTimeout = nv_fence->timeout; + + if (fenceSeqno <= currentSeqno) { + list_move_tail(&nv_fence->pending_node, &finished); + } else if (fenceTimeout <= now) { + list_move_tail(&nv_fence->pending_node, &timed_out); + } else { + break; + } + } + + /* + * If the caller passes non-NULL newWaitValueOut and newTimeoutOut + * parameters, it establishes a contract. If the returned values are + * non-zero, the caller must attempt to register a callback associated with + * the new wait value and reset the context's timer to the specified + * timeout. + */ + if (newWaitValueOut && newTimeoutOut) { + if (list_empty(&ctx->pending_fences)) { + /* No pending fences, so no waiter is needed. */ + ctx->current_wait_value = fenceSeqno = 0; + fenceTimeout = 0; + } else if (fenceSeqno == ctx->current_wait_value) { + /* + * The context already has a waiter registered, or in the process of + * being registered, for this fence. Indicate to the caller no new + * waiter registration is needed, and leave the ctx state alone. + */ + fenceSeqno = 0; + fenceTimeout = 0; + } else { + /* A new waiter must be registered. Prep the context */ + ctx->current_wait_value = fenceSeqno; + } + + *newWaitValueOut = fenceSeqno; + *newTimeoutOut = fenceTimeout; + } + + spin_unlock_irqrestore(&ctx->lock, flags); + + while (!list_empty(&finished)) { + nv_fence = list_first_entry(&finished, typeof(*nv_fence), pending_node); + list_del_init(&nv_fence->pending_node); + fence = &nv_fence->base; + nv_dma_fence_signal(fence); + nv_dma_fence_put(fence); /* Drops the pending list's reference */ + } + + while (!list_empty(&timed_out)) { + nv_fence = list_first_entry(&timed_out, typeof(*nv_fence), + pending_node); + list_del_init(&nv_fence->pending_node); + fence = &nv_fence->base; + nv_dma_fence_set_error(fence, -ETIMEDOUT); + nv_dma_fence_signal(fence); + nv_dma_fence_put(fence); /* Drops the pending list's reference */ + } +} + +static void +__nv_drm_semsurf_ctx_callback(void *data) +{ + struct nv_drm_semsurf_fence_callback *callback = data; + struct nv_drm_semsurf_fence_ctx *ctx = callback->ctx; + unsigned long flags; + + spin_lock_irqsave(&ctx->lock, flags); + /* If this was the context's currently registered callback, clear it. */ + if (ctx->callback.local == callback) { + ctx->callback.local = NULL; + ctx->callback.nvKms = NULL; + } + /* If storing of this callback may have been pending, prevent it. */ + if (ctx->current_wait_value == callback->wait_value) { + ctx->current_wait_value = 0; + } + spin_unlock_irqrestore(&ctx->lock, flags); + + /* + * This is redundant with the __nv_drm_semsurf_ctx_reg_callbacks() call from + * __nv_drm_semsurf_ctx_fence_callback_work(), which will be called by the + * work enqueued below, but calling it here as well allows unblocking + * waiters with less latency. + */ + __nv_drm_semsurf_ctx_process_completed(ctx, NULL, NULL); + + if (!nv_drm_workthread_add_work(&ctx->worker, &callback->work)) { + /* + * The context is shutting down. It will force-signal all fences when + * doing so, so there's no need for any more callback handling. + */ + nv_drm_free(callback); + } +} + +/* + * Take spin lock, attempt to stash newNvKmsCallback/newCallback in ctx. + * If current_wait_value in fence context != new_wait_value, we raced with + * someone registering a newer waiter. Release spin lock, and unregister our + * waiter. It isn't needed anymore. + */ +static bool +__nv_drm_semsurf_ctx_store_callback( + struct nv_drm_semsurf_fence_ctx *ctx, + NvU64 new_wait_value, + struct NvKmsKapiSemaphoreSurfaceCallback *newNvKmsCallback, + struct nv_drm_semsurf_fence_callback *newCallback) +{ + struct nv_drm_device *nv_dev = ctx->base.nv_dev; + struct NvKmsKapiSemaphoreSurfaceCallback *oldNvKmsCallback; + struct nv_drm_semsurf_fence_callback *oldCallback = NULL; + NvU64 oldWaitValue; + unsigned long flags; + bool installed = false; + + spin_lock_irqsave(&ctx->lock, flags); + if (ctx->current_wait_value == new_wait_value) { + oldCallback = ctx->callback.local; + oldNvKmsCallback = ctx->callback.nvKms; + oldWaitValue = oldCallback ? oldCallback->wait_value : 0; + ctx->callback.local = newCallback; + ctx->callback.nvKms = newNvKmsCallback; + installed = true; + } + spin_unlock_irqrestore(&ctx->lock, flags); + + if (oldCallback) { + if (nvKms->unregisterSemaphoreSurfaceCallback(nv_dev->pDevice, + ctx->pSemSurface, + ctx->base.fenceSemIndex, + oldWaitValue, + oldNvKmsCallback)) { + /* + * The old callback was successfully canceled, and its NVKMS and RM + * resources have been freed. Free its local tracking data. + */ + nv_drm_free(oldCallback); + } else { + /* + * The new callback is already running. It will do no harm, and free + * itself. + */ + } + } + + return installed; +} + +/* + * Processes completed fences and registers an RM callback and a timeout timer + * for the next incomplete fence, if any. To avoid calling in to RM while + * holding a spinlock, this is done in a loop until the state settles. + * + * Can NOT be called from in an atomic context/interrupt handler. + */ +static void +__nv_drm_semsurf_ctx_reg_callbacks(struct nv_drm_semsurf_fence_ctx *ctx) + +{ + struct nv_drm_device *nv_dev = ctx->base.nv_dev; + struct nv_drm_semsurf_fence_callback *newCallback = + __nv_drm_semsurf_new_callback(ctx); + struct NvKmsKapiSemaphoreSurfaceCallback *newNvKmsCallback; + NvU64 newWaitValue; + unsigned long newTimeout; + NvKmsKapiRegisterWaiterResult kapiRet; + + if (!newCallback) { NV_DRM_DEV_LOG_ERR( nv_dev, - "Failed to reserve fence. Error code: %d", ret); + "Failed to allocate new fence signal callback data"); + return; } - nv_dma_resv_unlock(resv); + do { + /* + * Process any completed or timed out fences. This returns the wait + * value and timeout of the first remaining pending fence, or 0/0 + * if no pending fences remain. It will also tag the context as + * waiting for the value returned. + */ + __nv_drm_semsurf_ctx_process_completed(ctx, + &newWaitValue, + &newTimeout); + + if (newWaitValue == 0) { + /* No fences remain, so no callback is needed. */ + nv_drm_free(newCallback); + newCallback = NULL; + return; + } - /* dma_resv_add_excl_fence takes its own reference to the fence. */ - nv_dma_fence_put(fence); + newCallback->wait_value = newWaitValue; + + /* + * Attempt to register a callback for the remaining fences. Note this + * code may be running concurrently in multiple places, attempting to + * register a callback for the same value, a value greater than + * newWaitValue if more fences have since completed, or a value less + * than newWaitValue if new fences have been created tracking lower + * values than the previously lowest pending one. Hence, even if this + * registration succeeds, the callback may be discarded + */ + kapiRet = + nvKms->registerSemaphoreSurfaceCallback(nv_dev->pDevice, + ctx->pSemSurface, + __nv_drm_semsurf_ctx_callback, + newCallback, + ctx->base.fenceSemIndex, + newWaitValue, + 0, + &newNvKmsCallback); + } while (kapiRet == NVKMS_KAPI_REG_WAITER_ALREADY_SIGNALLED); + + /* Can't deref newCallback at this point unless kapiRet indicates failure */ + + if (kapiRet != NVKMS_KAPI_REG_WAITER_SUCCESS) { + /* + * This is expected if another thread concurrently registered a callback + * for the same value, which is fine. That thread's callback will do the + * same work this thread's would have. Clean this one up and return. + * + * Another possibility is that an allocation or some other low-level + * operation that can spuriously fail has caused this failure, or of + * course a bug resulting in invalid usage of the + * registerSemaphoreSurfaceCallback() API. There is no good way to + * handle such failures, so the fence timeout will be relied upon to + * guarantee forward progress in those cases. + */ + nv_drm_free(newCallback); + return; + } -fence_context_create_fence_failed: - nv_drm_gem_object_unreference_unlocked(&nv_gem_fence_context->base); + nv_drm_mod_timer(&ctx->timer, newTimeout); + + if (!__nv_drm_semsurf_ctx_store_callback(ctx, + newWaitValue, + newNvKmsCallback, + newCallback)) { + /* + * Another thread registered a callback for a different value before + * this thread's callback could be stored in the context, or the + * callback is already running. That's OK. One of the following is true: + * + * -A new fence with a lower value has been registered, and the callback + * associated with that fence is now active and associated with the + * context. + * + * -This fence has already completed, and a new callback associated with + * a higher value has been registered and associated with the context. + * This lower-value callback is no longer needed, as any fences + * associated with it must have been marked completed before + * registering the higher-value callback. + * + * -The callback started running and cleared ctx->current_wait_value + * before the callback could be stored in the context. Work to signal + * the fence is now pending. + * + * Hence, it is safe to request cancellation of the callback and free + * the associated data if cancellation succeeds. + */ + if (nvKms->unregisterSemaphoreSurfaceCallback(nv_dev->pDevice, + ctx->pSemSurface, + ctx->base.fenceSemIndex, + newWaitValue, + newNvKmsCallback)) { + /* RM callback successfully canceled. Free local tracking data */ + nv_drm_free(newCallback); + } + } +} -fence_context_lookup_failed: - nv_drm_gem_object_unreference_unlocked(nv_gem); +static void __nv_drm_semsurf_fence_ctx_destroy( + struct nv_drm_fence_context *nv_fence_context) +{ + struct nv_drm_device *nv_dev = nv_fence_context->nv_dev; + struct nv_drm_semsurf_fence_ctx *ctx = + to_semsurf_fence_ctx(nv_fence_context); + struct NvKmsKapiSemaphoreSurfaceCallback *pendingNvKmsCallback; + NvU64 pendingWaitValue; + unsigned long flags; + + /* + * The workthread must be shut down before the timer is stopped to ensure + * the timer does not queue work that restarts itself. + */ + nv_drm_workthread_shutdown(&ctx->worker); + + nv_drm_del_timer_sync(&ctx->timer); + + /* + * The semaphore surface could still be sending callbacks, so it is still + * not safe to dereference the ctx->callback pointers. However, + * unregistering a callback via its handle is safe, as that code in NVKMS + * takes care to avoid dereferencing the handle until it knows the callback + * has been canceled in RM. This unregistration must be done to ensure the + * callback data is not leaked in NVKMS if it is still pending, as freeing + * the semaphore surface only cleans up RM's callback data. + */ + spin_lock_irqsave(&ctx->lock, flags); + pendingNvKmsCallback = ctx->callback.nvKms; + pendingWaitValue = ctx->callback.local ? + ctx->callback.local->wait_value : 0; + spin_unlock_irqrestore(&ctx->lock, flags); + + if (pendingNvKmsCallback) { + WARN_ON(pendingWaitValue == 0); + nvKms->unregisterSemaphoreSurfaceCallback(nv_dev->pDevice, + ctx->pSemSurface, + ctx->base.fenceSemIndex, + pendingWaitValue, + pendingNvKmsCallback); + } + + nvKms->freeSemaphoreSurface(nv_dev->pDevice, ctx->pSemSurface); + + /* + * Now that the semaphore surface, the timer, and the workthread are gone: + * + * -No more RM/NVKMS callbacks will arrive, nor are any in progress. Freeing + * the semaphore surface cancels all its callbacks associated with this + * instance of it, and idles any pending callbacks. + * + * -No more timer callbacks will arrive, nor are any in flight. + * + * -The workthread has been idled and is no longer running. + * + * Further, given the destructor is running, no other references to the + * fence context exist, so this code can assume no concurrent access to the + * fence context's data will happen from here on out. + */ + + if (ctx->callback.local) { + nv_drm_free(ctx->callback.local); + ctx->callback.local = NULL; + ctx->callback.nvKms = NULL; + } + + __nv_drm_semsurf_force_complete_pending(ctx); + + nv_drm_free(nv_fence_context); +} + +static void +__nv_drm_semsurf_ctx_timeout_work(void *data) +{ + struct nv_drm_semsurf_fence_ctx *ctx = data; + + __nv_drm_semsurf_ctx_reg_callbacks(ctx); +} + +static void +__nv_drm_semsurf_ctx_timeout_callback(nv_drm_timer *timer) +{ + struct nv_drm_semsurf_fence_ctx *ctx = + container_of(timer, typeof(*ctx), timer); + + /* + * Schedule work to register new waiter & timer on a worker thread. + * + * It does not matter if this fails. There are two possible failure cases: + * + * - ctx->timeout_work is already scheduled. That existing scheduled work + * will do at least as much as work scheduled right now and executed + * immediately, which is sufficient. + * + * - The context is shutting down. In this case, all fences will be force- + * signalled, so no further callbacks or timeouts are needed. + * + * Note this work may schedule a new timeout timer. To ensure that doesn't + * happen while context shutdown is shutting down and idling the timer, the + * the worker thread must be shut down before the timer is stopped. + */ + nv_drm_workthread_add_work(&ctx->worker, &ctx->timeout_work); +} + +static struct nv_drm_fence_context_ops +nv_drm_semsurf_fence_ctx_ops = { + .destroy = __nv_drm_semsurf_fence_ctx_destroy, +}; + +static struct nv_drm_semsurf_fence_ctx* +__nv_drm_semsurf_fence_ctx_new( + struct nv_drm_device *nv_dev, + struct drm_nvidia_semsurf_fence_ctx_create_params *p +) +{ + struct nv_drm_semsurf_fence_ctx *ctx; + struct NvKmsKapiSemaphoreSurface *pSemSurface; + uint8_t *semMapping; + uint8_t *maxSubmittedMapping; + char worker_name[20+16+1]; /* strlen(nvidia-drm/timeline-) + 16 for %llx + NUL */ + + pSemSurface = nvKms->importSemaphoreSurface(nv_dev->pDevice, + p->nvkms_params_ptr, + p->nvkms_params_size, + (void **)&semMapping, + (void **)&maxSubmittedMapping); + if (!pSemSurface) { + NV_DRM_DEV_LOG_ERR( + nv_dev, + "Failed to import semaphore surface"); + + goto failed; + } + + /* + * Allocate a fence context object and initialize it. + */ + + if ((ctx = nv_drm_calloc(1, sizeof(*ctx))) == NULL) { + goto failed_alloc_fence_context; + } + + semMapping += (p->index * nv_dev->semsurf_stride); + if (maxSubmittedMapping) { + maxSubmittedMapping += (p->index * nv_dev->semsurf_stride) + + nv_dev->semsurf_max_submitted_offset; + } + + /* + * nv_dma_fence_context_alloc() cannot fail, so we do not need + * to check a return value. + */ + + *ctx = (struct nv_drm_semsurf_fence_ctx) { + .base.ops = &nv_drm_semsurf_fence_ctx_ops, + .base.nv_dev = nv_dev, + .base.context = nv_dma_fence_context_alloc(1), + .base.fenceSemIndex = p->index, + .pSemSurface = pSemSurface, + .pSemMapping.pVoid = semMapping, + .pMaxSubmittedMapping = (volatile NvU64 *)maxSubmittedMapping, + .callback.local = NULL, + .callback.nvKms = NULL, + .current_wait_value = 0, + }; + + spin_lock_init(&ctx->lock); + INIT_LIST_HEAD(&ctx->pending_fences); + INIT_LIST_HEAD(&ctx->pending_waits); + + sprintf(worker_name, "nvidia-drm/timeline-%llx", + (long long unsigned)ctx->base.context); + if (!nv_drm_workthread_init(&ctx->worker, worker_name)) { + goto failed_alloc_worker; + } + + nv_drm_workthread_work_init(&ctx->timeout_work, + __nv_drm_semsurf_ctx_timeout_work, + ctx); + + nv_drm_timer_setup(&ctx->timer, __nv_drm_semsurf_ctx_timeout_callback); + + return ctx; + +failed_alloc_worker: + nv_drm_free(ctx); + +failed_alloc_fence_context: + nvKms->freeSemaphoreSurface(nv_dev->pDevice, pSemSurface); + +failed: + return NULL; + +} + +int nv_drm_semsurf_fence_ctx_create_ioctl(struct drm_device *dev, + void *data, + struct drm_file *filep) +{ + struct nv_drm_device *nv_dev = to_nv_device(dev); + struct drm_nvidia_semsurf_fence_ctx_create_params *p = data; + struct nv_drm_semsurf_fence_ctx *ctx; + int err; + + if (p->__pad != 0) { + NV_DRM_DEV_LOG_ERR(nv_dev, "Padding fields must be zeroed"); + return -EINVAL; + } + + ctx = __nv_drm_semsurf_fence_ctx_new(nv_dev, p); + + if (!ctx) { + return -ENOMEM; + } + + err = __nv_drm_fence_context_gem_init(dev, &ctx->base, &p->handle, filep); + + if (err) { + __nv_drm_semsurf_fence_ctx_destroy(&ctx->base); + } + + return err; +} + +static inline struct nv_drm_semsurf_fence* +to_nv_drm_semsurf_fence(nv_dma_fence_t *fence) +{ + return container_of(fence, struct nv_drm_semsurf_fence, base); +} + +static const char* +__nv_drm_semsurf_fence_op_get_timeline_name(nv_dma_fence_t *fence) +{ + return "nvidia.semaphore_surface"; +} + +static bool +__nv_drm_semsurf_fence_op_enable_signaling(nv_dma_fence_t *fence) +{ + // DO NOTHING - Could defer RM callback registration until this point + return true; +} + +static void +__nv_drm_semsurf_fence_op_release(nv_dma_fence_t *fence) +{ + struct nv_drm_semsurf_fence *nv_fence = + to_nv_drm_semsurf_fence(fence); + + nv_drm_free(nv_fence); +} + +static const nv_dma_fence_ops_t nv_drm_semsurf_fence_ops = { + .get_driver_name = nv_drm_gem_fence_op_get_driver_name, + .get_timeline_name = __nv_drm_semsurf_fence_op_get_timeline_name, + .enable_signaling = __nv_drm_semsurf_fence_op_enable_signaling, + .release = __nv_drm_semsurf_fence_op_release, + .wait = nv_dma_fence_default_wait, +#if defined(NV_DMA_FENCE_OPS_HAS_USE_64BIT_SEQNO) + .use_64bit_seqno = true, +#endif +}; + +/* + * Completes fence initialization, places a new reference to the fence in the + * context's pending fence list, and updates/registers any RM callbacks and + * timeout timers if necessary. + * + * Can NOT be called from in an atomic context/interrupt handler. + */ +static void +__nv_drm_semsurf_ctx_add_pending(struct nv_drm_semsurf_fence_ctx *ctx, + struct nv_drm_semsurf_fence *nv_fence, + NvU64 timeoutMS) +{ + struct list_head *pending; + unsigned long flags; + + if (timeoutMS > NV_DRM_SEMAPHORE_SURFACE_FENCE_MAX_TIMEOUT_MS) { + timeoutMS = NV_DRM_SEMAPHORE_SURFACE_FENCE_MAX_TIMEOUT_MS; + } + + /* Add a reference to the fence for the list */ + nv_dma_fence_get(&nv_fence->base); + INIT_LIST_HEAD(&nv_fence->pending_node); + + nv_fence->timeout = nv_drm_timeout_from_ms(timeoutMS); + + spin_lock_irqsave(&ctx->lock, flags); + + list_for_each(pending, &ctx->pending_fences) { + struct nv_drm_semsurf_fence *pending_fence = + list_entry(pending, typeof(*pending_fence), pending_node); + if (__nv_drm_get_semsurf_fence_seqno(pending_fence) > + __nv_drm_get_semsurf_fence_seqno(nv_fence)) { + /* Inserts 'nv_fence->pending_node' before 'pending' */ + list_add_tail(&nv_fence->pending_node, pending); + break; + } + } + + if (list_empty(&nv_fence->pending_node)) { + /* + * Inserts 'fence->pending_node' at the end of 'ctx->pending_fences', + * or as the head if the list is empty + */ + list_add_tail(&nv_fence->pending_node, &ctx->pending_fences); + } + + /* Fence is live starting... now! */ + spin_unlock_irqrestore(&ctx->lock, flags); + + /* Register new wait and timeout callbacks, if necessary */ + __nv_drm_semsurf_ctx_reg_callbacks(ctx); +} + +static nv_dma_fence_t *__nv_drm_semsurf_fence_ctx_create_fence( + struct nv_drm_device *nv_dev, + struct nv_drm_semsurf_fence_ctx *ctx, + NvU64 wait_value, + NvU64 timeout_value_ms) +{ + struct nv_drm_semsurf_fence *nv_fence; + nv_dma_fence_t *fence; + int ret = 0; + + if (timeout_value_ms == 0 || + timeout_value_ms > NV_DRM_SEMAPHORE_SURFACE_FENCE_MAX_TIMEOUT_MS) { + timeout_value_ms = NV_DRM_SEMAPHORE_SURFACE_FENCE_MAX_TIMEOUT_MS; + } + + if ((nv_fence = nv_drm_calloc(1, sizeof(*nv_fence))) == NULL) { + ret = -ENOMEM; + goto out; + } + + fence = &nv_fence->base; + spin_lock_init(&nv_fence->lock); +#if !defined(NV_DMA_FENCE_OPS_HAS_USE_64BIT_SEQNO) + nv_fence->wait_value = wait_value; +#endif + + /* Initializes the fence with one reference (for the caller) */ + nv_dma_fence_init(fence, &nv_drm_semsurf_fence_ops, + &nv_fence->lock, + ctx->base.context, wait_value); + + __nv_drm_semsurf_ctx_add_pending(ctx, nv_fence, timeout_value_ms); + +out: + /* Returned fence has one reference reserved for the caller. */ + return ret != 0 ? ERR_PTR(ret) : &nv_fence->base; +} + +int nv_drm_semsurf_fence_create_ioctl(struct drm_device *dev, + void *data, + struct drm_file *filep) +{ + struct nv_drm_device *nv_dev = to_nv_device(dev); + struct drm_nvidia_semsurf_fence_create_params *p = data; + struct nv_drm_fence_context *nv_fence_context; + nv_dma_fence_t *fence; + int ret = -EINVAL; + int fd; + + if (p->__pad != 0) { + NV_DRM_DEV_LOG_ERR(nv_dev, "Padding fields must be zeroed"); + goto done; + } + + if ((nv_fence_context = __nv_drm_fence_context_lookup( + nv_dev->dev, + filep, + p->fence_context_handle)) == NULL) { + NV_DRM_DEV_LOG_ERR( + nv_dev, + "Failed to lookup gem object for fence context: 0x%08x", + p->fence_context_handle); + + goto done; + } + + if (nv_fence_context->ops != &nv_drm_semsurf_fence_ctx_ops) { + NV_DRM_DEV_LOG_ERR( + nv_dev, + "Wrong fence context type: 0x%08x", + p->fence_context_handle); + + goto fence_context_create_fence_failed; + } + + fence = __nv_drm_semsurf_fence_ctx_create_fence( + nv_dev, + to_semsurf_fence_ctx(nv_fence_context), + p->wait_value, + p->timeout_value_ms); + + if (IS_ERR(fence)) { + ret = PTR_ERR(fence); + + NV_DRM_DEV_LOG_ERR( + nv_dev, + "Failed to allocate fence: 0x%08x", p->fence_context_handle); + + goto fence_context_create_fence_failed; + } + + if ((fd = nv_drm_create_sync_file(fence)) < 0) { + ret = fd; + + NV_DRM_DEV_LOG_ERR( + nv_dev, + "Failed to create sync file from fence on ctx 0x%08x", + p->fence_context_handle); + + goto fence_context_create_sync_failed; + } + + p->fd = fd; + ret = 0; + +fence_context_create_sync_failed: + /* + * Release this function's reference to the fence. If successful, the sync + * FD will still hold a reference, and the pending list (if the fence hasn't + * already been signaled) will also retain a reference. + */ + nv_dma_fence_put(fence); + +fence_context_create_fence_failed: + nv_drm_gem_object_unreference_unlocked(&nv_fence_context->base); + +done: + return ret; +} + +static void +__nv_drm_semsurf_free_wait_data(struct nv_drm_sync_fd_wait_data *wait_data) +{ + struct nv_drm_semsurf_fence_ctx *ctx = wait_data->ctx; + unsigned long flags; + + spin_lock_irqsave(&ctx->lock, flags); + list_del(&wait_data->pending_node); + spin_unlock_irqrestore(&ctx->lock, flags); + + nv_drm_free(wait_data); +} + +static void +__nv_drm_semsurf_wait_fence_work_cb +( + void *arg +) +{ + struct nv_drm_sync_fd_wait_data *wait_data = arg; + struct nv_drm_semsurf_fence_ctx *ctx = wait_data->ctx; + struct nv_drm_device *nv_dev = ctx->base.nv_dev; + NvKmsKapiRegisterWaiterResult ret; + + /* + * Note this command applies "newValue" immediately if the semaphore has + * already reached "waitValue." It only returns NVKMS_KAPI_ALREADY_SIGNALLED + * if a separate notification was requested as well. + */ + ret = nvKms->registerSemaphoreSurfaceCallback(nv_dev->pDevice, + ctx->pSemSurface, + NULL, + NULL, + ctx->base.fenceSemIndex, + wait_data->pre_wait_value, + wait_data->post_wait_value, + NULL); + + if (ret != NVKMS_KAPI_REG_WAITER_SUCCESS) { + NV_DRM_DEV_LOG_ERR(nv_dev, + "Failed to register auto-value-update on pre-wait value for sync FD semaphore surface"); + } + + __nv_drm_semsurf_free_wait_data(wait_data); +} + +static void +__nv_drm_semsurf_wait_fence_cb +( + nv_dma_fence_t *fence, + nv_dma_fence_cb_t *cb +) +{ + struct nv_drm_sync_fd_wait_data *wait_data = + container_of(cb, typeof(*wait_data), dma_fence_cb); + struct nv_drm_semsurf_fence_ctx *ctx = wait_data->ctx; + + /* + * Defer registering the wait with RM to a worker thread, since + * this function may be called in interrupt context, which + * could mean arriving here directly from RM's top/bottom half + * handler when the fence being waited on came from an RM-managed GPU. + */ + if (!nv_drm_workthread_add_work(&ctx->worker, &wait_data->work)) { + /* + * The context is shutting down. RM would likely just drop + * the wait anyway as part of that, so do nothing. Either the + * client is exiting uncleanly, or it is a bug in the client + * in that it didn't consume its wait before destroying the + * fence context used to instantiate it. + */ + __nv_drm_semsurf_free_wait_data(wait_data); + } + + /* Don't need to reference the fence anymore, just the fence context. */ + nv_dma_fence_put(fence); +} + +int nv_drm_semsurf_fence_wait_ioctl(struct drm_device *dev, + void *data, + struct drm_file *filep) +{ + struct nv_drm_device *nv_dev = to_nv_device(dev); + struct drm_nvidia_semsurf_fence_wait_params *p = data; + struct nv_drm_fence_context *nv_fence_context; + struct nv_drm_semsurf_fence_ctx *ctx; + struct nv_drm_sync_fd_wait_data *wait_data = NULL; + nv_dma_fence_t *fence; + unsigned long flags; + int ret = -EINVAL; + + if (p->pre_wait_value >= p->post_wait_value) { + NV_DRM_DEV_LOG_ERR( + nv_dev, + "Non-monotonic wait values specified to fence wait: 0x%llu, 0x%llu", + p->pre_wait_value, p->post_wait_value); + goto done; + } + + if ((nv_fence_context = __nv_drm_fence_context_lookup( + nv_dev->dev, + filep, + p->fence_context_handle)) == NULL) { + NV_DRM_DEV_LOG_ERR( + nv_dev, + "Failed to lookup gem object for fence context: 0x%08x", + p->fence_context_handle); + + goto done; + } + + if (nv_fence_context->ops != &nv_drm_semsurf_fence_ctx_ops) { + NV_DRM_DEV_LOG_ERR( + nv_dev, + "Wrong fence context type: 0x%08x", + p->fence_context_handle); + + goto fence_context_sync_lookup_failed; + } + + ctx = to_semsurf_fence_ctx(nv_fence_context); + + wait_data = nv_drm_calloc(1, sizeof(*wait_data)); + + if (!wait_data) { + NV_DRM_DEV_LOG_ERR( + nv_dev, + "Failed to allocate callback data for sync FD wait: %d", p->fd); + + goto fence_context_sync_lookup_failed; + } + + fence = nv_drm_sync_file_get_fence(p->fd); + + if (!fence) { + NV_DRM_DEV_LOG_ERR( + nv_dev, + "Attempt to wait on invalid sync FD: %d", p->fd); + + goto fence_context_sync_lookup_failed; + } + + wait_data->ctx = ctx; + wait_data->pre_wait_value = p->pre_wait_value; + wait_data->post_wait_value = p->post_wait_value; + nv_drm_workthread_work_init(&wait_data->work, + __nv_drm_semsurf_wait_fence_work_cb, + wait_data); + + spin_lock_irqsave(&ctx->lock, flags); + list_add(&wait_data->pending_node, &ctx->pending_waits); + spin_unlock_irqrestore(&ctx->lock, flags); + + ret = nv_dma_fence_add_callback(fence, + &wait_data->dma_fence_cb, + __nv_drm_semsurf_wait_fence_cb); + + if (ret) { + if (ret == -ENOENT) { + /* The fence is already signaled */ + } else { + NV_DRM_LOG_ERR( + "Failed to add dma_fence callback. Signaling early!"); + /* Proceed as if the fence wait succeeded */ + } + + /* Execute second half of wait immediately, avoiding the worker thread */ + nv_dma_fence_put(fence); + __nv_drm_semsurf_wait_fence_work_cb(wait_data); + } + + ret = 0; + +fence_context_sync_lookup_failed: + if (ret && wait_data) { + /* + * Do not use __nv_drm_semsurf_free_wait_data() here, as the wait_data + * has not been added to the pending list yet. + */ + nv_drm_free(wait_data); + } + + nv_drm_gem_object_unreference_unlocked(&nv_fence_context->base); + +done: + return 0; +} + +int nv_drm_semsurf_fence_attach_ioctl(struct drm_device *dev, + void *data, + struct drm_file *filep) +{ + struct nv_drm_device *nv_dev = to_nv_device(dev); + struct drm_nvidia_semsurf_fence_attach_params *p = data; + struct nv_drm_gem_object *nv_gem = NULL; + struct nv_drm_fence_context *nv_fence_context = NULL; + nv_dma_fence_t *fence; + int ret = -EINVAL; + + nv_gem = nv_drm_gem_object_lookup(nv_dev->dev, filep, p->handle); + + if (!nv_gem) { + NV_DRM_DEV_LOG_ERR( + nv_dev, + "Failed to lookup gem object for fence attach: 0x%08x", + p->handle); + + goto done; + } + + nv_fence_context = __nv_drm_fence_context_lookup( + nv_dev->dev, + filep, + p->fence_context_handle); + + if (!nv_fence_context) { + NV_DRM_DEV_LOG_ERR( + nv_dev, + "Failed to lookup gem object for fence context: 0x%08x", + p->fence_context_handle); + + goto done; + } + + if (nv_fence_context->ops != &nv_drm_semsurf_fence_ctx_ops) { + NV_DRM_DEV_LOG_ERR( + nv_dev, + "Wrong fence context type: 0x%08x", + p->fence_context_handle); + + goto done; + } + + fence = __nv_drm_semsurf_fence_ctx_create_fence( + nv_dev, + to_semsurf_fence_ctx(nv_fence_context), + p->wait_value, + p->timeout_value_ms); + + if (IS_ERR(fence)) { + ret = PTR_ERR(fence); + + NV_DRM_DEV_LOG_ERR( + nv_dev, + "Failed to allocate fence: 0x%08x", p->handle); + + goto done; + } + + ret = __nv_drm_gem_attach_fence(nv_gem, fence, p->shared); + + nv_dma_fence_put(fence); + +done: + if (nv_fence_context) { + nv_drm_gem_object_unreference_unlocked(&nv_fence_context->base); + } + + if (nv_gem) { + nv_drm_gem_object_unreference_unlocked(nv_gem); + } -done: return ret; } diff --git a/kernel-open/nvidia-drm/nvidia-drm-fence.h b/kernel-open/nvidia-drm/nvidia-drm-fence.h index 10689e1db2..188ad20a8c 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-fence.h +++ b/kernel-open/nvidia-drm/nvidia-drm-fence.h @@ -41,6 +41,22 @@ int nv_drm_prime_fence_context_create_ioctl(struct drm_device *dev, int nv_drm_gem_prime_fence_attach_ioctl(struct drm_device *dev, void *data, struct drm_file *filep); +int nv_drm_semsurf_fence_ctx_create_ioctl(struct drm_device *dev, + void *data, + struct drm_file *filep); + +int nv_drm_semsurf_fence_create_ioctl(struct drm_device *dev, + void *data, + struct drm_file *filep); + +int nv_drm_semsurf_fence_wait_ioctl(struct drm_device *dev, + void *data, + struct drm_file *filep); + +int nv_drm_semsurf_fence_attach_ioctl(struct drm_device *dev, + void *data, + struct drm_file *filep); + #endif /* NV_DRM_FENCE_AVAILABLE */ #endif /* NV_DRM_AVAILABLE */ diff --git a/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.c b/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.c index 5d04713ce7..7d66c432ec 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.c +++ b/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.c @@ -465,7 +465,7 @@ int nv_drm_gem_alloc_nvkms_memory_ioctl(struct drm_device *dev, goto failed; } - if (p->__pad != 0) { + if ((p->__pad0 != 0) || (p->__pad1 != 0)) { ret = -EINVAL; NV_DRM_DEV_LOG_ERR(nv_dev, "non-zero value in padding field"); goto failed; diff --git a/kernel-open/nvidia-drm/nvidia-drm-gem.h b/kernel-open/nvidia-drm/nvidia-drm-gem.h index 70974e0f0d..d918479a16 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-gem.h +++ b/kernel-open/nvidia-drm/nvidia-drm-gem.h @@ -95,6 +95,16 @@ static inline struct nv_drm_gem_object *to_nv_gem_object( * 3e70fd160cf0b1945225eaa08dd2cb8544f21cb8 (2018-11-15). */ +static inline void +nv_drm_gem_object_reference(struct nv_drm_gem_object *nv_gem) +{ +#if defined(NV_DRM_GEM_OBJECT_GET_PRESENT) + drm_gem_object_get(&nv_gem->base); +#else + drm_gem_object_reference(&nv_gem->base); +#endif +} + static inline void nv_drm_gem_object_unreference_unlocked(struct nv_drm_gem_object *nv_gem) { diff --git a/kernel-open/nvidia-drm/nvidia-drm-helper.h b/kernel-open/nvidia-drm/nvidia-drm-helper.h index 85a5d2e9cc..6bb966059e 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-helper.h +++ b/kernel-open/nvidia-drm/nvidia-drm-helper.h @@ -306,6 +306,36 @@ int nv_drm_atomic_helper_disable_all(struct drm_device *dev, for_each_plane_in_state(__state, plane, plane_state, __i) #endif +/* + * for_each_new_plane_in_state() was added by kernel commit + * 581e49fe6b411f407102a7f2377648849e0fa37f which was Signed-off-by: + * Maarten Lankhorst + * Daniel Vetter + * + * This commit also added the old_state and new_state pointers to + * __drm_planes_state. Because of this, the best that can be done on kernel + * versions without this macro is for_each_plane_in_state. + */ + +/** + * nv_drm_for_each_new_plane_in_state - iterate over all planes in an atomic update + * @__state: &struct drm_atomic_state pointer + * @plane: &struct drm_plane iteration cursor + * @new_plane_state: &struct drm_plane_state iteration cursor for the new state + * @__i: int iteration cursor, for macro-internal use + * + * This iterates over all planes in an atomic update, tracking only the new + * state. This is useful in enable functions, where we need the new state the + * hardware should be in when the atomic commit operation has completed. + */ +#if !defined(for_each_new_plane_in_state) +#define nv_drm_for_each_new_plane_in_state(__state, plane, new_plane_state, __i) \ + nv_drm_for_each_plane_in_state(__state, plane, new_plane_state, __i) +#else +#define nv_drm_for_each_new_plane_in_state(__state, plane, new_plane_state, __i) \ + for_each_new_plane_in_state(__state, plane, new_plane_state, __i) +#endif + static inline struct drm_connector * nv_drm_connector_lookup(struct drm_device *dev, struct drm_file *filep, uint32_t id) diff --git a/kernel-open/nvidia-drm/nvidia-drm-ioctl.h b/kernel-open/nvidia-drm/nvidia-drm-ioctl.h index 1d0e738591..d1e7a07803 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-ioctl.h +++ b/kernel-open/nvidia-drm/nvidia-drm-ioctl.h @@ -48,6 +48,10 @@ #define DRM_NVIDIA_GET_CONNECTOR_ID_FOR_DPY_ID 0x11 #define DRM_NVIDIA_GRANT_PERMISSIONS 0x12 #define DRM_NVIDIA_REVOKE_PERMISSIONS 0x13 +#define DRM_NVIDIA_SEMSURF_FENCE_CTX_CREATE 0x14 +#define DRM_NVIDIA_SEMSURF_FENCE_CREATE 0x15 +#define DRM_NVIDIA_SEMSURF_FENCE_WAIT 0x16 +#define DRM_NVIDIA_SEMSURF_FENCE_ATTACH 0x17 #define DRM_IOCTL_NVIDIA_GEM_IMPORT_NVKMS_MEMORY \ DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_IMPORT_NVKMS_MEMORY), \ @@ -133,6 +137,26 @@ DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_REVOKE_PERMISSIONS), \ struct drm_nvidia_revoke_permissions_params) +#define DRM_IOCTL_NVIDIA_SEMSURF_FENCE_CTX_CREATE \ + DRM_IOWR((DRM_COMMAND_BASE + \ + DRM_NVIDIA_SEMSURF_FENCE_CTX_CREATE), \ + struct drm_nvidia_semsurf_fence_ctx_create_params) + +#define DRM_IOCTL_NVIDIA_SEMSURF_FENCE_CREATE \ + DRM_IOWR((DRM_COMMAND_BASE + \ + DRM_NVIDIA_SEMSURF_FENCE_CREATE), \ + struct drm_nvidia_semsurf_fence_create_params) + +#define DRM_IOCTL_NVIDIA_SEMSURF_FENCE_WAIT \ + DRM_IOW((DRM_COMMAND_BASE + \ + DRM_NVIDIA_SEMSURF_FENCE_WAIT), \ + struct drm_nvidia_semsurf_fence_wait_params) + +#define DRM_IOCTL_NVIDIA_SEMSURF_FENCE_ATTACH \ + DRM_IOW((DRM_COMMAND_BASE + \ + DRM_NVIDIA_SEMSURF_FENCE_ATTACH), \ + struct drm_nvidia_semsurf_fence_attach_params) + struct drm_nvidia_gem_import_nvkms_memory_params { uint64_t mem_size; /* IN */ @@ -158,6 +182,8 @@ struct drm_nvidia_get_dev_info_params { uint32_t generic_page_kind; /* OUT */ uint32_t page_kind_generation; /* OUT */ uint32_t sector_layout; /* OUT */ + uint32_t supports_sync_fd; /* OUT */ + uint32_t supports_semsurf; /* OUT */ }; struct drm_nvidia_prime_fence_context_create_params { @@ -179,6 +205,7 @@ struct drm_nvidia_gem_prime_fence_attach_params { uint32_t handle; /* IN GEM handle to attach fence to */ uint32_t fence_context_handle; /* IN GEM handle to fence context on which fence is run on */ uint32_t sem_thresh; /* IN Semaphore value to reach before signal */ + uint32_t __pad; }; struct drm_nvidia_get_client_capability_params { @@ -190,6 +217,8 @@ struct drm_nvidia_get_client_capability_params { struct drm_nvidia_crtc_crc32 { uint32_t value; /* Read value, undefined if supported is false */ uint8_t supported; /* Supported boolean, true if readable by hardware */ + uint8_t __pad0; + uint16_t __pad1; }; struct drm_nvidia_crtc_crc32_v2_out { @@ -229,10 +258,11 @@ struct drm_nvidia_gem_alloc_nvkms_memory_params { uint32_t handle; /* OUT */ uint8_t block_linear; /* IN */ uint8_t compressible; /* IN/OUT */ - uint16_t __pad; + uint16_t __pad0; uint64_t memory_size; /* IN */ uint32_t flags; /* IN */ + uint32_t __pad1; }; struct drm_nvidia_gem_export_dmabuf_memory_params { @@ -266,13 +296,90 @@ struct drm_nvidia_get_connector_id_for_dpy_id_params { uint32_t connectorId; /* OUT */ }; +enum drm_nvidia_permissions_type { + NV_DRM_PERMISSIONS_TYPE_MODESET = 2, + NV_DRM_PERMISSIONS_TYPE_SUB_OWNER = 3 +}; + struct drm_nvidia_grant_permissions_params { int32_t fd; /* IN */ uint32_t dpyId; /* IN */ + uint32_t type; /* IN */ }; struct drm_nvidia_revoke_permissions_params { uint32_t dpyId; /* IN */ + uint32_t type; /* IN */ +}; + +struct drm_nvidia_semsurf_fence_ctx_create_params { + uint64_t index; /* IN Index of the desired semaphore in the + * fence context's semaphore surface */ + + /* Params for importing userspace semaphore surface */ + uint64_t nvkms_params_ptr; /* IN */ + uint64_t nvkms_params_size; /* IN */ + + uint32_t handle; /* OUT GEM handle to fence context */ + uint32_t __pad; +}; + +struct drm_nvidia_semsurf_fence_create_params { + uint32_t fence_context_handle; /* IN GEM handle to fence context on which + * fence is run on */ + + uint32_t timeout_value_ms; /* IN Timeout value in ms for the fence + * after which the fence will be signaled + * with its error status set to -ETIMEDOUT. + * Default timeout value is 5000ms */ + + uint64_t wait_value; /* IN Semaphore value to reach before signal */ + + int32_t fd; /* OUT sync FD object representing the + * semaphore at the specified index reaching + * a value >= wait_value */ + uint32_t __pad; +}; + +/* + * Note there is no provision for timeouts in this ioctl. The kernel + * documentation asserts timeouts should be handled by fence producers, and + * that waiters should not second-guess their logic, as it is producers rather + * than consumers that have better information when it comes to determining a + * reasonable timeout for a given workload. + */ +struct drm_nvidia_semsurf_fence_wait_params { + uint32_t fence_context_handle; /* IN GEM handle to fence context which will + * be used to wait on the sync FD. Need not + * be the fence context used to create the + * sync FD. */ + + int32_t fd; /* IN sync FD object to wait on */ + + uint64_t pre_wait_value; /* IN Wait for the semaphore represented by + * fence_context to reach this value before + * waiting for the sync file. */ + + uint64_t post_wait_value; /* IN Signal the semaphore represented by + * fence_context to this value after waiting + * for the sync file */ +}; + +struct drm_nvidia_semsurf_fence_attach_params { + uint32_t handle; /* IN GEM handle of buffer */ + + uint32_t fence_context_handle; /* IN GEM handle of fence context */ + + uint32_t timeout_value_ms; /* IN Timeout value in ms for the fence + * after which the fence will be signaled + * with its error status set to -ETIMEDOUT. + * Default timeout value is 5000ms */ + + uint32_t shared; /* IN If true, fence will reserve shared + * access to the buffer, otherwise it will + * reserve exclusive access */ + + uint64_t wait_value; /* IN Semaphore value to reach before signal */ }; #endif /* _UAPI_NVIDIA_DRM_IOCTL_H_ */ diff --git a/kernel-open/nvidia-drm/nvidia-drm-linux.c b/kernel-open/nvidia-drm/nvidia-drm-linux.c index 8cd9cbb260..17daa88b78 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-linux.c +++ b/kernel-open/nvidia-drm/nvidia-drm-linux.c @@ -35,7 +35,13 @@ #include #endif +#if defined(NV_LINUX_SYNC_FILE_H_PRESENT) +#include +#include +#endif + #include +#include #include "nv-mm.h" @@ -45,6 +51,14 @@ MODULE_PARM_DESC( bool nv_drm_modeset_module_param = false; module_param_named(modeset, nv_drm_modeset_module_param, bool, 0400); +#if defined(NV_DRM_FBDEV_GENERIC_AVAILABLE) +MODULE_PARM_DESC( + fbdev, + "Create a framebuffer device (1 = enable, 0 = disable (default)) (EXPERIMENTAL)"); +bool nv_drm_fbdev_module_param = false; +module_param_named(fbdev, nv_drm_fbdev_module_param, bool, 0400); +#endif + void *nv_drm_calloc(size_t nmemb, size_t size) { size_t total_size = nmemb * size; @@ -81,14 +95,10 @@ char *nv_drm_asprintf(const char *fmt, ...) #if defined(NVCPU_X86) || defined(NVCPU_X86_64) #define WRITE_COMBINE_FLUSH() asm volatile("sfence":::"memory") -#elif defined(NVCPU_FAMILY_ARM) - #if defined(NVCPU_ARM) - #define WRITE_COMBINE_FLUSH() { dsb(); outer_sync(); } - #elif defined(NVCPU_AARCH64) - #define WRITE_COMBINE_FLUSH() mb() - #endif #elif defined(NVCPU_PPC64LE) #define WRITE_COMBINE_FLUSH() asm volatile("sync":::"memory") +#else + #define WRITE_COMBINE_FLUSH() mb() #endif void nv_drm_write_combine_flush(void) @@ -160,6 +170,122 @@ void nv_drm_vunmap(void *address) vunmap(address); } +bool nv_drm_workthread_init(nv_drm_workthread *worker, const char *name) +{ + worker->shutting_down = false; + if (nv_kthread_q_init(&worker->q, name)) { + return false; + } + + spin_lock_init(&worker->lock); + + return true; +} + +void nv_drm_workthread_shutdown(nv_drm_workthread *worker) +{ + unsigned long flags; + + spin_lock_irqsave(&worker->lock, flags); + worker->shutting_down = true; + spin_unlock_irqrestore(&worker->lock, flags); + + nv_kthread_q_stop(&worker->q); +} + +void nv_drm_workthread_work_init(nv_drm_work *work, + void (*callback)(void *), + void *arg) +{ + nv_kthread_q_item_init(work, callback, arg); +} + +int nv_drm_workthread_add_work(nv_drm_workthread *worker, nv_drm_work *work) +{ + unsigned long flags; + int ret = 0; + + spin_lock_irqsave(&worker->lock, flags); + if (!worker->shutting_down) { + ret = nv_kthread_q_schedule_q_item(&worker->q, work); + } + spin_unlock_irqrestore(&worker->lock, flags); + + return ret; +} + +void nv_drm_timer_setup(nv_drm_timer *timer, void (*callback)(nv_drm_timer *nv_drm_timer)) +{ + nv_timer_setup(timer, callback); +} + +void nv_drm_mod_timer(nv_drm_timer *timer, unsigned long timeout_native) +{ + mod_timer(&timer->kernel_timer, timeout_native); +} + +unsigned long nv_drm_timer_now(void) +{ + return jiffies; +} + +unsigned long nv_drm_timeout_from_ms(NvU64 relative_timeout_ms) +{ + return jiffies + msecs_to_jiffies(relative_timeout_ms); +} + +bool nv_drm_del_timer_sync(nv_drm_timer *timer) +{ + if (del_timer_sync(&timer->kernel_timer)) { + return true; + } else { + return false; + } +} + +#if defined(NV_DRM_FENCE_AVAILABLE) +int nv_drm_create_sync_file(nv_dma_fence_t *fence) +{ +#if defined(NV_LINUX_SYNC_FILE_H_PRESENT) + struct sync_file *sync; + int fd = get_unused_fd_flags(O_CLOEXEC); + + if (fd < 0) { + return fd; + } + + /* sync_file_create() generates its own reference to the fence */ + sync = sync_file_create(fence); + + if (IS_ERR(sync)) { + put_unused_fd(fd); + return PTR_ERR(sync); + } + + fd_install(fd, sync->file); + + return fd; +#else /* defined(NV_LINUX_SYNC_FILE_H_PRESENT) */ + return -EINVAL; +#endif /* defined(NV_LINUX_SYNC_FILE_H_PRESENT) */ +} + +nv_dma_fence_t *nv_drm_sync_file_get_fence(int fd) +{ +#if defined(NV_SYNC_FILE_GET_FENCE_PRESENT) + return sync_file_get_fence(fd); +#else /* defined(NV_SYNC_FILE_GET_FENCE_PRESENT) */ + return NULL; +#endif /* defined(NV_SYNC_FILE_GET_FENCE_PRESENT) */ +} +#endif /* defined(NV_DRM_FENCE_AVAILABLE) */ + +void nv_drm_yield(void) +{ + set_current_state(TASK_INTERRUPTIBLE); + schedule_timeout(1); +} + #endif /* NV_DRM_AVAILABLE */ /************************************************************************* diff --git a/kernel-open/nvidia-drm/nvidia-drm-modeset.c b/kernel-open/nvidia-drm/nvidia-drm-modeset.c index 4b601b0853..85ea28778f 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-modeset.c +++ b/kernel-open/nvidia-drm/nvidia-drm-modeset.c @@ -237,6 +237,14 @@ nv_drm_atomic_apply_modeset_config(struct drm_device *dev, int i; int ret; + /* + * If sub-owner permission was granted to another NVKMS client, disallow + * modesets through the DRM interface. + */ + if (nv_dev->subOwnershipGranted) { + return -EINVAL; + } + memset(requested_config, 0, sizeof(*requested_config)); /* Loop over affected crtcs and construct NvKmsKapiRequestedModeSetConfig */ @@ -274,9 +282,6 @@ nv_drm_atomic_apply_modeset_config(struct drm_device *dev, nv_new_crtc_state->nv_flip = NULL; } -#if defined(NV_DRM_CRTC_STATE_HAS_VRR_ENABLED) - requested_config->headRequestedConfig[nv_crtc->head].modeSetConfig.vrrEnabled = new_crtc_state->vrr_enabled; -#endif } } @@ -292,7 +297,9 @@ nv_drm_atomic_apply_modeset_config(struct drm_device *dev, requested_config, &reply_config, commit)) { - return -EINVAL; + if (commit || reply_config.flipResult != NV_KMS_FLIP_RESULT_IN_PROGRESS) { + return -EINVAL; + } } if (commit && nv_dev->supportsSyncpts) { @@ -388,42 +395,56 @@ int nv_drm_atomic_commit(struct drm_device *dev, struct nv_drm_device *nv_dev = to_nv_device(dev); /* - * drm_mode_config_funcs::atomic_commit() mandates to return -EBUSY - * for nonblocking commit if previous updates (commit tasks/flip event) are - * pending. In case of blocking commits it mandates to wait for previous - * updates to complete. + * XXX: drm_mode_config_funcs::atomic_commit() mandates to return -EBUSY + * for nonblocking commit if the commit would need to wait for previous + * updates (commit tasks/flip event) to complete. In case of blocking + * commits it mandates to wait for previous updates to complete. However, + * the kernel DRM-KMS documentation does explicitly allow maintaining a + * queue of outstanding commits. + * + * Our system already implements such a queue, but due to + * bug 4054608, it is currently not used. */ - if (nonblock) { - nv_drm_for_each_crtc_in_state(state, crtc, crtc_state, i) { - struct nv_drm_crtc *nv_crtc = to_nv_crtc(crtc); + nv_drm_for_each_crtc_in_state(state, crtc, crtc_state, i) { + struct nv_drm_crtc *nv_crtc = to_nv_crtc(crtc); - /* - * Here you aren't required to hold nv_drm_crtc::flip_list_lock - * because: - * - * The core DRM driver acquires lock for all affected crtcs before - * calling into ->commit() hook, therefore it is not possible for - * other threads to call into ->commit() hook affecting same crtcs - * and enqueue flip objects into flip_list - - * - * nv_drm_atomic_commit_internal() - * |-> nv_drm_atomic_apply_modeset_config(commit=true) - * |-> nv_drm_crtc_enqueue_flip() - * - * Only possibility is list_empty check races with code path - * dequeuing flip object - - * - * __nv_drm_handle_flip_event() - * |-> nv_drm_crtc_dequeue_flip() - * - * But this race condition can't lead list_empty() to return - * incorrect result. nv_drm_crtc_dequeue_flip() in the middle of - * updating the list could not trick us into thinking the list is - * empty when it isn't. - */ + /* + * Here you aren't required to hold nv_drm_crtc::flip_list_lock + * because: + * + * The core DRM driver acquires lock for all affected crtcs before + * calling into ->commit() hook, therefore it is not possible for + * other threads to call into ->commit() hook affecting same crtcs + * and enqueue flip objects into flip_list - + * + * nv_drm_atomic_commit_internal() + * |-> nv_drm_atomic_apply_modeset_config(commit=true) + * |-> nv_drm_crtc_enqueue_flip() + * + * Only possibility is list_empty check races with code path + * dequeuing flip object - + * + * __nv_drm_handle_flip_event() + * |-> nv_drm_crtc_dequeue_flip() + * + * But this race condition can't lead list_empty() to return + * incorrect result. nv_drm_crtc_dequeue_flip() in the middle of + * updating the list could not trick us into thinking the list is + * empty when it isn't. + */ + if (nonblock) { if (!list_empty(&nv_crtc->flip_list)) { return -EBUSY; } + } else { + if (wait_event_timeout( + nv_dev->flip_event_wq, + list_empty(&nv_crtc->flip_list), + 3 * HZ /* 3 second */) == 0) { + NV_DRM_DEV_LOG_ERR( + nv_dev, + "Flip event timeout on head %u", nv_crtc->head); + } } } @@ -467,6 +488,7 @@ int nv_drm_atomic_commit(struct drm_device *dev, goto done; } + nv_dev->drmMasterChangedSinceLastAtomicCommit = NV_FALSE; nv_drm_for_each_crtc_in_state(state, crtc, crtc_state, i) { struct nv_drm_crtc *nv_crtc = to_nv_crtc(crtc); diff --git a/kernel-open/nvidia-drm/nvidia-drm-os-interface.h b/kernel-open/nvidia-drm/nvidia-drm-os-interface.h index ac527528a5..51c7a7fda3 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-os-interface.h +++ b/kernel-open/nvidia-drm/nvidia-drm-os-interface.h @@ -29,10 +29,47 @@ #if defined(NV_DRM_AVAILABLE) +#if defined(NV_DRM_FENCE_AVAILABLE) +#include "nvidia-dma-fence-helper.h" +#endif + +#if defined(NV_LINUX) +#include "nv-kthread-q.h" +#include "linux/spinlock.h" + +typedef struct nv_drm_workthread { + spinlock_t lock; + struct nv_kthread_q q; + bool shutting_down; +} nv_drm_workthread; + +typedef nv_kthread_q_item_t nv_drm_work; + +#else /* defined(NV_LINUX) */ +#error "Need to define deferred work primitives for this OS" +#endif /* else defined(NV_LINUX) */ + +#if defined(NV_LINUX) +#include "nv-timer.h" + +typedef struct nv_timer nv_drm_timer; + +#else /* defined(NV_LINUX) */ +#error "Need to define kernel timer callback primitives for this OS" +#endif /* else defined(NV_LINUX) */ + +#if defined(NV_DRM_FBDEV_GENERIC_SETUP_PRESENT) && defined(NV_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PRESENT) +#define NV_DRM_FBDEV_GENERIC_AVAILABLE +#endif + struct page; /* Set to true when the atomic modeset feature is enabled. */ extern bool nv_drm_modeset_module_param; +#if defined(NV_DRM_FBDEV_GENERIC_AVAILABLE) +/* Set to true when the nvidia-drm driver should install a framebuffer device */ +extern bool nv_drm_fbdev_module_param; +#endif void *nv_drm_calloc(size_t nmemb, size_t size); @@ -51,6 +88,37 @@ void *nv_drm_vmap(struct page **pages, unsigned long pages_count); void nv_drm_vunmap(void *address); -#endif +bool nv_drm_workthread_init(nv_drm_workthread *worker, const char *name); + +/* Can be called concurrently with nv_drm_workthread_add_work() */ +void nv_drm_workthread_shutdown(nv_drm_workthread *worker); + +void nv_drm_workthread_work_init(nv_drm_work *work, + void (*callback)(void *), + void *arg); + +/* Can be called concurrently with nv_drm_workthread_shutdown() */ +int nv_drm_workthread_add_work(nv_drm_workthread *worker, nv_drm_work *work); + +void nv_drm_timer_setup(nv_drm_timer *timer, + void (*callback)(nv_drm_timer *nv_drm_timer)); + +void nv_drm_mod_timer(nv_drm_timer *timer, unsigned long relative_timeout_ms); + +bool nv_drm_del_timer_sync(nv_drm_timer *timer); + +unsigned long nv_drm_timer_now(void); + +unsigned long nv_drm_timeout_from_ms(NvU64 relative_timeout_ms); + +#if defined(NV_DRM_FENCE_AVAILABLE) +int nv_drm_create_sync_file(nv_dma_fence_t *fence); + +nv_dma_fence_t *nv_drm_sync_file_get_fence(int fd); +#endif /* defined(NV_DRM_FENCE_AVAILABLE) */ + +void nv_drm_yield(void); + +#endif /* defined(NV_DRM_AVAILABLE) */ #endif /* __NVIDIA_DRM_OS_INTERFACE_H__ */ diff --git a/kernel-open/nvidia-drm/nvidia-drm-priv.h b/kernel-open/nvidia-drm/nvidia-drm-priv.h index 91b7b4f219..253155f6d4 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-priv.h +++ b/kernel-open/nvidia-drm/nvidia-drm-priv.h @@ -46,12 +46,33 @@ #define NV_DRM_LOG_ERR(__fmt, ...) \ DRM_ERROR("[nvidia-drm] " __fmt "\n", ##__VA_ARGS__) +/* + * DRM_WARN() was added in v4.9 by kernel commit + * 30b0da8d556e65ff935a56cd82c05ba0516d3e4a + * + * Before this commit, only DRM_INFO and DRM_ERROR were defined and + * DRM_INFO(fmt, ...) was defined as + * printk(KERN_INFO "[" DRM_NAME "] " fmt, ##__VA_ARGS__). So, if + * DRM_WARN is undefined this defines NV_DRM_LOG_WARN following the + * same pattern as DRM_INFO. + */ +#ifdef DRM_WARN +#define NV_DRM_LOG_WARN(__fmt, ...) \ + DRM_WARN("[nvidia-drm] " __fmt "\n", ##__VA_ARGS__) +#else +#define NV_DRM_LOG_WARN(__fmt, ...) \ + printk(KERN_WARNING "[" DRM_NAME "] [nvidia-drm] " __fmt "\n", ##__VA_ARGS__) +#endif + #define NV_DRM_LOG_INFO(__fmt, ...) \ DRM_INFO("[nvidia-drm] " __fmt "\n", ##__VA_ARGS__) #define NV_DRM_DEV_LOG_INFO(__dev, __fmt, ...) \ NV_DRM_LOG_INFO("[GPU ID 0x%08x] " __fmt, __dev->gpu_info.gpu_id, ##__VA_ARGS__) +#define NV_DRM_DEV_LOG_WARN(__dev, __fmt, ...) \ + NV_DRM_LOG_WARN("[GPU ID 0x%08x] " __fmt, __dev->gpu_info.gpu_id, ##__VA_ARGS__) + #define NV_DRM_DEV_LOG_ERR(__dev, __fmt, ...) \ NV_DRM_LOG_ERR("[GPU ID 0x%08x] " __fmt, __dev->gpu_info.gpu_id, ##__VA_ARGS__) @@ -117,9 +138,26 @@ struct nv_drm_device { #endif +#if defined(NV_DRM_FENCE_AVAILABLE) + NvU64 semsurf_stride; + NvU64 semsurf_max_submitted_offset; +#endif + NvBool hasVideoMemory; NvBool supportsSyncpts; + NvBool subOwnershipGranted; + NvBool hasFramebufferConsole; + + /** + * @drmMasterChangedSinceLastAtomicCommit: + * + * This flag is set in nv_drm_master_set and reset after a completed atomic + * commit. It is used to restore or recommit state that is lost by the + * NvKms modeset owner change, such as the CRTC color management + * properties. + */ + NvBool drmMasterChangedSinceLastAtomicCommit; struct drm_property *nv_out_fence_property; struct drm_property *nv_input_colorspace_property; diff --git a/kernel-open/nvidia-drm/nvidia-drm.Kbuild b/kernel-open/nvidia-drm/nvidia-drm.Kbuild index a4ea2d4798..b8cc5e23d6 100644 --- a/kernel-open/nvidia-drm/nvidia-drm.Kbuild +++ b/kernel-open/nvidia-drm/nvidia-drm.Kbuild @@ -19,6 +19,7 @@ NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-modeset.c NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-fence.c NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-linux.c NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-helper.c +NVIDIA_DRM_SOURCES += nvidia-drm/nv-kthread-q.c NVIDIA_DRM_SOURCES += nvidia-drm/nv-pci-table.c NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-gem-nvkms-memory.c NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-gem-user-memory.c @@ -79,6 +80,17 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_rotation_available NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_vma_offset_exact_lookup_locked NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_gem_object_put_unlocked NV_CONFTEST_FUNCTION_COMPILE_TESTS += nvhost_dma_fence_unpack +NV_CONFTEST_FUNCTION_COMPILE_TESTS += list_is_first +NV_CONFTEST_FUNCTION_COMPILE_TESTS += timer_setup +NV_CONFTEST_FUNCTION_COMPILE_TESTS += dma_fence_set_error +NV_CONFTEST_FUNCTION_COMPILE_TESTS += fence_set_error +NV_CONFTEST_FUNCTION_COMPILE_TESTS += sync_file_get_fence +NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_aperture_remove_conflicting_pci_framebuffers +NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_fbdev_generic_setup +NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_connector_attach_hdr_output_metadata_property +NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_helper_crtc_enable_color_mgmt +NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_crtc_enable_color_mgmt +NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_atomic_helper_legacy_gamma_set NV_CONFTEST_TYPE_COMPILE_TESTS += drm_bus_present NV_CONFTEST_TYPE_COMPILE_TESTS += drm_bus_has_bus_type @@ -133,3 +145,6 @@ NV_CONFTEST_TYPE_COMPILE_TESTS += drm_connector_lookup NV_CONFTEST_TYPE_COMPILE_TESTS += drm_connector_put NV_CONFTEST_TYPE_COMPILE_TESTS += vm_area_struct_has_const_vm_flags NV_CONFTEST_TYPE_COMPILE_TESTS += drm_driver_has_dumb_destroy +NV_CONFTEST_TYPE_COMPILE_TESTS += fence_ops_use_64bit_seqno +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_aperture_remove_conflicting_pci_framebuffers_has_driver_arg +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_mode_create_dp_colorspace_property_has_supported_colorspaces_arg diff --git a/kernel-open/nvidia-modeset/nv-kthread-q.c b/kernel-open/nvidia-modeset/nv-kthread-q.c index 2098f27a70..c3b5570557 100644 --- a/kernel-open/nvidia-modeset/nv-kthread-q.c +++ b/kernel-open/nvidia-modeset/nv-kthread-q.c @@ -247,6 +247,11 @@ int nv_kthread_q_init_on_node(nv_kthread_q_t *q, const char *q_name, int preferr return 0; } +int nv_kthread_q_init(nv_kthread_q_t *q, const char *qname) +{ + return nv_kthread_q_init_on_node(q, qname, NV_KTHREAD_NO_NODE); +} + // Returns true (non-zero) if the item was actually scheduled, and false if the // item was already pending in a queue. static int _raw_q_schedule(nv_kthread_q_t *q, nv_kthread_q_item_t *q_item) diff --git a/kernel-open/nvidia-modeset/nvidia-modeset-linux.c b/kernel-open/nvidia-modeset/nvidia-modeset-linux.c index d4d1d26837..4fa576c6d2 100644 --- a/kernel-open/nvidia-modeset/nvidia-modeset-linux.c +++ b/kernel-open/nvidia-modeset/nvidia-modeset-linux.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-21 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -65,9 +65,15 @@ static bool output_rounding_fix = true; module_param_named(output_rounding_fix, output_rounding_fix, bool, 0400); +static bool disable_hdmi_frl = false; +module_param_named(disable_hdmi_frl, disable_hdmi_frl, bool, 0400); + static bool disable_vrr_memclk_switch = false; module_param_named(disable_vrr_memclk_switch, disable_vrr_memclk_switch, bool, 0400); +static bool hdmi_deepcolor = false; +module_param_named(hdmi_deepcolor, hdmi_deepcolor, bool, 0400); + /* These parameters are used for fault injection tests. Normally the defaults * should be used. */ MODULE_PARM_DESC(fail_malloc, "Fail the Nth call to nvkms_alloc"); @@ -78,6 +84,7 @@ MODULE_PARM_DESC(malloc_verbose, "Report information about malloc calls on modul static bool malloc_verbose = false; module_param_named(malloc_verbose, malloc_verbose, bool, 0400); +#if NVKMS_CONFIG_FILE_SUPPORTED /* This parameter is used to find the dpy override conf file */ #define NVKMS_CONF_FILE_SPECIFIED (nvkms_conf != NULL) @@ -86,6 +93,7 @@ MODULE_PARM_DESC(config_file, "(default: disabled)"); static char *nvkms_conf = NULL; module_param_named(config_file, nvkms_conf, charp, 0400); +#endif static atomic_t nvkms_alloc_called_count; @@ -94,11 +102,21 @@ NvBool nvkms_output_rounding_fix(void) return output_rounding_fix; } +NvBool nvkms_disable_hdmi_frl(void) +{ + return disable_hdmi_frl; +} + NvBool nvkms_disable_vrr_memclk_switch(void) { return disable_vrr_memclk_switch; } +NvBool nvkms_hdmi_deepcolor(void) +{ + return hdmi_deepcolor; +} + #define NVKMS_SYNCPT_STUBS_NEEDED /************************************************************************* @@ -335,7 +353,7 @@ NvU64 nvkms_get_usec(void) struct timespec64 ts; NvU64 ns; - ktime_get_real_ts64(&ts); + ktime_get_raw_ts64(&ts); ns = timespec64_to_ns(&ts); return ns / 1000; @@ -1382,6 +1400,7 @@ static void nvkms_proc_exit(void) /************************************************************************* * NVKMS Config File Read ************************************************************************/ +#if NVKMS_CONFIG_FILE_SUPPORTED static NvBool nvkms_fs_mounted(void) { return current->fs != NULL; @@ -1489,6 +1508,11 @@ static void nvkms_read_config_file_locked(void) nvkms_free(buffer, buf_size); } +#else +static void nvkms_read_config_file_locked(void) +{ +} +#endif /************************************************************************* * NVKMS KAPI functions diff --git a/kernel-open/nvidia-modeset/nvidia-modeset-os-interface.h b/kernel-open/nvidia-modeset/nvidia-modeset-os-interface.h index 16b89c1ca2..9f1a2f5428 100644 --- a/kernel-open/nvidia-modeset/nvidia-modeset-os-interface.h +++ b/kernel-open/nvidia-modeset/nvidia-modeset-os-interface.h @@ -97,8 +97,9 @@ typedef struct { } NvKmsSyncPtOpParams; NvBool nvkms_output_rounding_fix(void); - +NvBool nvkms_disable_hdmi_frl(void); NvBool nvkms_disable_vrr_memclk_switch(void); +NvBool nvkms_hdmi_deepcolor(void); void nvkms_call_rm (void *ops); void* nvkms_alloc (size_t size, diff --git a/kernel-open/nvidia-modeset/nvidia-modeset.Kbuild b/kernel-open/nvidia-modeset/nvidia-modeset.Kbuild index ebf3f048b2..e50d42d710 100644 --- a/kernel-open/nvidia-modeset/nvidia-modeset.Kbuild +++ b/kernel-open/nvidia-modeset/nvidia-modeset.Kbuild @@ -58,6 +58,18 @@ nvidia-modeset-y += $(NVIDIA_MODESET_BINARY_OBJECT_O) NVIDIA_MODESET_CFLAGS += -I$(src)/nvidia-modeset NVIDIA_MODESET_CFLAGS += -UDEBUG -U_DEBUG -DNDEBUG -DNV_BUILD_MODULE_INSTANCES=0 +# Some Android kernels prohibit driver use of filesystem functions like +# filp_open() and kernel_read(). Disable the NVKMS_CONFIG_FILE_SUPPORTED +# functionality that uses those functions when building for Android. + +PLATFORM_IS_ANDROID ?= 0 + +ifeq ($(PLATFORM_IS_ANDROID),1) + NVIDIA_MODESET_CFLAGS += -DNVKMS_CONFIG_FILE_SUPPORTED=0 +else + NVIDIA_MODESET_CFLAGS += -DNVKMS_CONFIG_FILE_SUPPORTED=1 +endif + $(call ASSIGN_PER_OBJ_CFLAGS, $(NVIDIA_MODESET_OBJECTS), $(NVIDIA_MODESET_CFLAGS)) diff --git a/kernel-open/nvidia-modeset/nvkms.h b/kernel-open/nvidia-modeset/nvkms.h index e770341b89..b64fbb098e 100644 --- a/kernel-open/nvidia-modeset/nvkms.h +++ b/kernel-open/nvidia-modeset/nvkms.h @@ -66,6 +66,8 @@ enum NvKmsClientType { NVKMS_CLIENT_KERNEL_SPACE, }; +struct NvKmsPerOpenDev; + NvBool nvKmsIoctl( void *pOpenVoid, NvU32 cmd, @@ -104,4 +106,6 @@ NvBool nvKmsKapiGetFunctionsTableInternal NvBool nvKmsGetBacklight(NvU32 display_id, void *drv_priv, NvU32 *brightness); NvBool nvKmsSetBacklight(NvU32 display_id, void *drv_priv, NvU32 brightness); +NvBool nvKmsOpenDevHasSubOwnerPermissionOrBetter(const struct NvKmsPerOpenDev *pOpenDev); + #endif /* __NV_KMS_H__ */ diff --git a/kernel-open/nvidia-peermem/nvidia-peermem.c b/kernel-open/nvidia-peermem/nvidia-peermem.c index a20f7d1dd8..e1d5f37494 100644 --- a/kernel-open/nvidia-peermem/nvidia-peermem.c +++ b/kernel-open/nvidia-peermem/nvidia-peermem.c @@ -249,8 +249,8 @@ static int nv_dma_map(struct sg_table *sg_head, void *context, nv_mem_context->sg_allocated = 1; for_each_sg(sg_head->sgl, sg, nv_mem_context->npages, i) { sg_set_page(sg, NULL, nv_mem_context->page_size, 0); - sg->dma_address = dma_mapping->dma_addresses[i]; - sg->dma_length = nv_mem_context->page_size; + sg_dma_address(sg) = dma_mapping->dma_addresses[i]; + sg_dma_len(sg) = nv_mem_context->page_size; } nv_mem_context->sg_head = *sg_head; *nmap = nv_mem_context->npages; @@ -304,8 +304,13 @@ static void nv_mem_put_pages_common(int nc, return; if (nc) { +#ifdef NVIDIA_P2P_CAP_GET_PAGES_PERSISTENT_API ret = nvidia_p2p_put_pages_persistent(nv_mem_context->page_virt_start, nv_mem_context->page_table, 0); +#else + ret = nvidia_p2p_put_pages(0, 0, nv_mem_context->page_virt_start, + nv_mem_context->page_table); +#endif } else { ret = nvidia_p2p_put_pages(0, 0, nv_mem_context->page_virt_start, nv_mem_context->page_table); @@ -412,9 +417,15 @@ static int nv_mem_get_pages_nc(unsigned long addr, nv_mem_context->core_context = core_context; nv_mem_context->page_size = GPU_PAGE_SIZE; +#ifdef NVIDIA_P2P_CAP_GET_PAGES_PERSISTENT_API ret = nvidia_p2p_get_pages_persistent(nv_mem_context->page_virt_start, nv_mem_context->mapped_size, &nv_mem_context->page_table, 0); +#else + ret = nvidia_p2p_get_pages(0, 0, nv_mem_context->page_virt_start, nv_mem_context->mapped_size, + &nv_mem_context->page_table, NULL, NULL); +#endif + if (ret < 0) { peer_err("error %d while calling nvidia_p2p_get_pages() with NULL callback\n", ret); return ret; @@ -459,8 +470,6 @@ static int __init nv_mem_client_init(void) } #if defined (NV_MLNX_IB_PEER_MEM_SYMBOLS_PRESENT) - int status = 0; - // off by one, to leave space for the trailing '1' which is flagging // the new client type BUG_ON(strlen(DRV_NAME) > IB_PEER_MEMORY_NAME_MAX-1); @@ -489,7 +498,7 @@ static int __init nv_mem_client_init(void) &mem_invalidate_callback); if (!reg_handle) { peer_err("nv_mem_client_init -- error while registering traditional client\n"); - status = -EINVAL; + rc = -EINVAL; goto out; } @@ -499,12 +508,12 @@ static int __init nv_mem_client_init(void) reg_handle_nc = ib_register_peer_memory_client(&nv_mem_client_nc, NULL); if (!reg_handle_nc) { peer_err("nv_mem_client_init -- error while registering nc client\n"); - status = -EINVAL; + rc = -EINVAL; goto out; } out: - if (status) { + if (rc) { if (reg_handle) { ib_unregister_peer_memory_client(reg_handle); reg_handle = NULL; @@ -516,7 +525,7 @@ static int __init nv_mem_client_init(void) } } - return status; + return rc; #else return -EINVAL; #endif diff --git a/kernel-open/nvidia-uvm/clc365.h b/kernel-open/nvidia-uvm/clc365.h index 82c6cce11c..807238c2f5 100644 --- a/kernel-open/nvidia-uvm/clc365.h +++ b/kernel-open/nvidia-uvm/clc365.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2022 NVIDIA Corporation + Copyright (c) 2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to diff --git a/kernel-open/nvidia-uvm/clc369.h b/kernel-open/nvidia-uvm/clc369.h index 49b01d9012..37473f8883 100644 --- a/kernel-open/nvidia-uvm/clc369.h +++ b/kernel-open/nvidia-uvm/clc369.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2022 NVIDIA Corporation + Copyright (c) 2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to diff --git a/kernel-open/nvidia-uvm/nv-kthread-q.c b/kernel-open/nvidia-uvm/nv-kthread-q.c index 2098f27a70..c3b5570557 100644 --- a/kernel-open/nvidia-uvm/nv-kthread-q.c +++ b/kernel-open/nvidia-uvm/nv-kthread-q.c @@ -247,6 +247,11 @@ int nv_kthread_q_init_on_node(nv_kthread_q_t *q, const char *q_name, int preferr return 0; } +int nv_kthread_q_init(nv_kthread_q_t *q, const char *qname) +{ + return nv_kthread_q_init_on_node(q, qname, NV_KTHREAD_NO_NODE); +} + // Returns true (non-zero) if the item was actually scheduled, and false if the // item was already pending in a queue. static int _raw_q_schedule(nv_kthread_q_t *q, nv_kthread_q_item_t *q_item) diff --git a/kernel-open/nvidia-uvm/nvidia-uvm-sources.Kbuild b/kernel-open/nvidia-uvm/nvidia-uvm-sources.Kbuild index b051989267..b9ab77bc2c 100644 --- a/kernel-open/nvidia-uvm/nvidia-uvm-sources.Kbuild +++ b/kernel-open/nvidia-uvm/nvidia-uvm-sources.Kbuild @@ -27,6 +27,7 @@ NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_rm_mem.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_channel.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_lock.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_hal.c +NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_processors.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_range_tree.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_rb_tree.c NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_range_allocator.c diff --git a/kernel-open/nvidia-uvm/nvidia-uvm.Kbuild b/kernel-open/nvidia-uvm/nvidia-uvm.Kbuild index 9c4d04ced1..8da0c7efe9 100644 --- a/kernel-open/nvidia-uvm/nvidia-uvm.Kbuild +++ b/kernel-open/nvidia-uvm/nvidia-uvm.Kbuild @@ -82,10 +82,12 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += set_pages_uc NV_CONFTEST_FUNCTION_COMPILE_TESTS += ktime_get_raw_ts64 NV_CONFTEST_FUNCTION_COMPILE_TESTS += ioasid_get NV_CONFTEST_FUNCTION_COMPILE_TESTS += mm_pasid_drop +NV_CONFTEST_FUNCTION_COMPILE_TESTS += migrate_vma_setup NV_CONFTEST_FUNCTION_COMPILE_TESTS += mmget_not_zero NV_CONFTEST_FUNCTION_COMPILE_TESTS += mmgrab NV_CONFTEST_FUNCTION_COMPILE_TESTS += iommu_sva_bind_device_has_drvdata_arg NV_CONFTEST_FUNCTION_COMPILE_TESTS += vm_fault_to_errno +NV_CONFTEST_FUNCTION_COMPILE_TESTS += find_next_bit_wrap NV_CONFTEST_TYPE_COMPILE_TESTS += backing_dev_info NV_CONFTEST_TYPE_COMPILE_TESTS += mm_context_t @@ -99,6 +101,7 @@ NV_CONFTEST_TYPE_COMPILE_TESTS += kmem_cache_has_kobj_remove_work NV_CONFTEST_TYPE_COMPILE_TESTS += sysfs_slab_unlink NV_CONFTEST_TYPE_COMPILE_TESTS += vm_fault_t NV_CONFTEST_TYPE_COMPILE_TESTS += mmu_notifier_ops_invalidate_range +NV_CONFTEST_TYPE_COMPILE_TESTS += mmu_notifier_ops_arch_invalidate_secondary_tlbs NV_CONFTEST_TYPE_COMPILE_TESTS += proc_ops NV_CONFTEST_TYPE_COMPILE_TESTS += timespec64 NV_CONFTEST_TYPE_COMPILE_TESTS += mm_has_mmap_lock @@ -113,4 +116,3 @@ NV_CONFTEST_TYPE_COMPILE_TESTS += mpol_preferred_many_present NV_CONFTEST_TYPE_COMPILE_TESTS += mmu_interval_notifier NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_int_active_memcg -NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_migrate_vma_setup diff --git a/kernel-open/nvidia-uvm/nvstatus.c b/kernel-open/nvidia-uvm/nvstatus.c index e377dd9f9b..92c5d7af8f 100644 --- a/kernel-open/nvidia-uvm/nvstatus.c +++ b/kernel-open/nvidia-uvm/nvstatus.c @@ -24,11 +24,11 @@ #include "nvstatus.h" #if !defined(NV_PRINTF_STRING_SECTION) -#if defined(NVRM) && NVCPU_IS_RISCV64 +#if defined(NVRM) && NVOS_IS_LIBOS #define NV_PRINTF_STRING_SECTION __attribute__ ((section (".logging"))) -#else // defined(NVRM) && NVCPU_IS_RISCV64 +#else // defined(NVRM) && NVOS_IS_LIBOS #define NV_PRINTF_STRING_SECTION -#endif // defined(NVRM) && NVCPU_IS_RISCV64 +#endif // defined(NVRM) && NVOS_IS_LIBOS #endif // !defined(NV_PRINTF_STRING_SECTION) /* diff --git a/kernel-open/nvidia-uvm/uvm.c b/kernel-open/nvidia-uvm/uvm.c index a74ad154b3..6f95f17cb4 100644 --- a/kernel-open/nvidia-uvm/uvm.c +++ b/kernel-open/nvidia-uvm/uvm.c @@ -571,7 +571,6 @@ static void uvm_vm_open_managed_entry(struct vm_area_struct *vma) static void uvm_vm_close_managed(struct vm_area_struct *vma) { uvm_va_space_t *va_space = uvm_va_space_get(vma->vm_file); - uvm_processor_id_t gpu_id; bool make_zombie = false; if (current->mm != NULL) @@ -606,12 +605,6 @@ static void uvm_vm_close_managed(struct vm_area_struct *vma) uvm_destroy_vma_managed(vma, make_zombie); - // Notify GPU address spaces that the fault buffer needs to be flushed to - // avoid finding stale entries that can be attributed to new VA ranges - // reallocated at the same address. - for_each_gpu_id_in_mask(gpu_id, &va_space->registered_gpu_va_spaces) { - uvm_processor_mask_set_atomic(&va_space->needs_fault_buffer_flush, gpu_id); - } uvm_va_space_up_write(va_space); if (current->mm != NULL) diff --git a/kernel-open/nvidia-uvm/uvm.h b/kernel-open/nvidia-uvm/uvm.h index 8177b9797d..c1b54b9ed6 100644 --- a/kernel-open/nvidia-uvm/uvm.h +++ b/kernel-open/nvidia-uvm/uvm.h @@ -216,6 +216,10 @@ NV_STATUS UvmDeinitialize(void); // Note that it is not required to release VA ranges that were reserved with // UvmReserveVa(). // +// This is useful for per-process checkpoint and restore, where kernel-mode +// state needs to be reconfigured to match the expectations of a pre-existing +// user-mode process. +// // UvmReopen() closes the open file returned by UvmGetFileDescriptor() and // replaces it with a new open file with the same name. // diff --git a/kernel-open/nvidia-uvm/uvm_ats_faults.c b/kernel-open/nvidia-uvm/uvm_ats_faults.c index 99f5db2928..88f654f198 100644 --- a/kernel-open/nvidia-uvm/uvm_ats_faults.c +++ b/kernel-open/nvidia-uvm/uvm_ats_faults.c @@ -114,6 +114,8 @@ static void flush_tlb_write_faults(uvm_gpu_va_space_t *gpu_va_space, { uvm_ats_fault_invalidate_t *ats_invalidate; + uvm_ats_smmu_invalidate_tlbs(gpu_va_space, addr, size); + if (client_type == UVM_FAULT_CLIENT_TYPE_GPC) ats_invalidate = &gpu_va_space->gpu->parent->fault_buffer_info.replayable.ats_invalidate; else @@ -588,4 +590,3 @@ NV_STATUS uvm_ats_invalidate_tlbs(uvm_gpu_va_space_t *gpu_va_space, return status; } - diff --git a/kernel-open/nvidia-uvm/uvm_ats_sva.c b/kernel-open/nvidia-uvm/uvm_ats_sva.c index f9753d2c1a..5cfcb3e766 100644 --- a/kernel-open/nvidia-uvm/uvm_ats_sva.c +++ b/kernel-open/nvidia-uvm/uvm_ats_sva.c @@ -29,8 +29,12 @@ #include "uvm_va_space.h" #include "uvm_va_space_mm.h" +#include #include #include +#include +#include +#include // linux/sched/mm.h is needed for mmget_not_zero and mmput to get the mm // reference required for the iommu_sva_bind_device() call. This header is not @@ -46,17 +50,271 @@ #define UVM_IOMMU_SVA_BIND_DEVICE(dev, mm) iommu_sva_bind_device(dev, mm) #endif +// Base address of SMMU CMDQ-V for GSMMU0. +#define SMMU_CMDQV_BASE_ADDR(smmu_base) (smmu_base + 0x200000) +#define SMMU_CMDQV_BASE_LEN 0x00830000 + +// CMDQV configuration is done by firmware but we check status here. +#define SMMU_CMDQV_CONFIG 0x0 +#define SMMU_CMDQV_CONFIG_CMDQV_EN BIT(0) + +// Used to map a particular VCMDQ to a VINTF. +#define SMMU_CMDQV_CMDQ_ALLOC_MAP(vcmdq_id) (0x200 + 0x4 * (vcmdq_id)) +#define SMMU_CMDQV_CMDQ_ALLOC_MAP_ALLOC BIT(0) + +// Shift for the field containing the index of the virtual interface +// owning the VCMDQ. +#define SMMU_CMDQV_CMDQ_ALLOC_MAP_VIRT_INTF_INDX_SHIFT 15 + +// Base address for the VINTF registers. +#define SMMU_VINTF_BASE_ADDR(cmdqv_base_addr, vintf_id) (cmdqv_base_addr + 0x1000 + 0x100 * (vintf_id)) + +// Virtual interface (VINTF) configuration registers. The WAR only +// works on baremetal so we need to configure ourselves as the +// hypervisor owner. +#define SMMU_VINTF_CONFIG 0x0 +#define SMMU_VINTF_CONFIG_ENABLE BIT(0) +#define SMMU_VINTF_CONFIG_HYP_OWN BIT(17) + +#define SMMU_VINTF_STATUS 0x0 +#define SMMU_VINTF_STATUS_ENABLED BIT(0) + +// Caclulates the base address for a particular VCMDQ instance. +#define SMMU_VCMDQ_BASE_ADDR(cmdqv_base_addr, vcmdq_id) (cmdqv_base_addr + 0x10000 + 0x80 * (vcmdq_id)) + +// SMMU command queue consumer index register. Updated by SMMU +// when commands are consumed. +#define SMMU_VCMDQ_CONS 0x0 + +// SMMU command queue producer index register. Updated by UVM when +// commands are added to the queue. +#define SMMU_VCMDQ_PROD 0x4 + +// Configuration register used to enable a VCMDQ. +#define SMMU_VCMDQ_CONFIG 0x8 +#define SMMU_VCMDQ_CONFIG_ENABLE BIT(0) + +// Status register used to check the VCMDQ is enabled. +#define SMMU_VCMDQ_STATUS 0xc +#define SMMU_VCMDQ_STATUS_ENABLED BIT(0) + +// Base address offset for the VCMDQ registers. +#define SMMU_VCMDQ_CMDQ_BASE 0x10000 + +// Size of the command queue. Each command is 8 bytes and we can't +// have a command queue greater than one page. +#define SMMU_VCMDQ_CMDQ_BASE_LOG2SIZE 9 +#define SMMU_VCMDQ_CMDQ_ENTRIES (1UL << SMMU_VCMDQ_CMDQ_BASE_LOG2SIZE) + +// We always use VINTF63 for the WAR +#define VINTF 63 +static void smmu_vintf_write32(void __iomem *smmu_cmdqv_base, int reg, NvU32 val) +{ + iowrite32(val, SMMU_VINTF_BASE_ADDR(smmu_cmdqv_base, VINTF) + reg); +} + +static NvU32 smmu_vintf_read32(void __iomem *smmu_cmdqv_base, int reg) +{ + return ioread32(SMMU_VINTF_BASE_ADDR(smmu_cmdqv_base, VINTF) + reg); +} + +// We always use VCMDQ127 for the WAR +#define VCMDQ 127 +void smmu_vcmdq_write32(void __iomem *smmu_cmdqv_base, int reg, NvU32 val) +{ + iowrite32(val, SMMU_VCMDQ_BASE_ADDR(smmu_cmdqv_base, VCMDQ) + reg); +} + +NvU32 smmu_vcmdq_read32(void __iomem *smmu_cmdqv_base, int reg) +{ + return ioread32(SMMU_VCMDQ_BASE_ADDR(smmu_cmdqv_base, VCMDQ) + reg); +} + +static void smmu_vcmdq_write64(void __iomem *smmu_cmdqv_base, int reg, NvU64 val) +{ + iowrite64(val, SMMU_VCMDQ_BASE_ADDR(smmu_cmdqv_base, VCMDQ) + reg); +} + +// Fix for Bug 4130089: [GH180][r535] WAR for kernel not issuing SMMU +// TLB invalidates on read-only to read-write upgrades +static NV_STATUS uvm_ats_smmu_war_init(uvm_parent_gpu_t *parent_gpu) +{ + uvm_spin_loop_t spin; + NV_STATUS status; + unsigned long cmdqv_config; + void __iomem *smmu_cmdqv_base; + struct acpi_iort_node *node; + struct acpi_iort_smmu_v3 *iort_smmu; + + node = *(struct acpi_iort_node **) dev_get_platdata(parent_gpu->pci_dev->dev.iommu->iommu_dev->dev->parent); + iort_smmu = (struct acpi_iort_smmu_v3 *) node->node_data; + + smmu_cmdqv_base = ioremap(SMMU_CMDQV_BASE_ADDR(iort_smmu->base_address), SMMU_CMDQV_BASE_LEN); + if (!smmu_cmdqv_base) + return NV_ERR_NO_MEMORY; + + parent_gpu->smmu_war.smmu_cmdqv_base = smmu_cmdqv_base; + cmdqv_config = ioread32(smmu_cmdqv_base + SMMU_CMDQV_CONFIG); + if (!(cmdqv_config & SMMU_CMDQV_CONFIG_CMDQV_EN)) { + status = NV_ERR_OBJECT_NOT_FOUND; + goto out; + } + + // Allocate SMMU CMDQ pages for WAR + parent_gpu->smmu_war.smmu_cmdq = alloc_page(NV_UVM_GFP_FLAGS | __GFP_ZERO); + if (!parent_gpu->smmu_war.smmu_cmdq) { + status = NV_ERR_NO_MEMORY; + goto out; + } + + // Initialise VINTF for the WAR + smmu_vintf_write32(smmu_cmdqv_base, SMMU_VINTF_CONFIG, SMMU_VINTF_CONFIG_ENABLE | SMMU_VINTF_CONFIG_HYP_OWN); + UVM_SPIN_WHILE(!(smmu_vintf_read32(smmu_cmdqv_base, SMMU_VINTF_STATUS) & SMMU_VINTF_STATUS_ENABLED), &spin); + + // Allocate VCMDQ to VINTF + iowrite32((VINTF << SMMU_CMDQV_CMDQ_ALLOC_MAP_VIRT_INTF_INDX_SHIFT) | SMMU_CMDQV_CMDQ_ALLOC_MAP_ALLOC, + smmu_cmdqv_base + SMMU_CMDQV_CMDQ_ALLOC_MAP(VCMDQ)); + + BUILD_BUG_ON((SMMU_VCMDQ_CMDQ_BASE_LOG2SIZE + 3) > PAGE_SHIFT); + smmu_vcmdq_write64(smmu_cmdqv_base, SMMU_VCMDQ_CMDQ_BASE, + page_to_phys(parent_gpu->smmu_war.smmu_cmdq) | SMMU_VCMDQ_CMDQ_BASE_LOG2SIZE); + smmu_vcmdq_write32(smmu_cmdqv_base, SMMU_VCMDQ_CONS, 0); + smmu_vcmdq_write32(smmu_cmdqv_base, SMMU_VCMDQ_PROD, 0); + smmu_vcmdq_write32(smmu_cmdqv_base, SMMU_VCMDQ_CONFIG, SMMU_VCMDQ_CONFIG_ENABLE); + UVM_SPIN_WHILE(!(smmu_vcmdq_read32(smmu_cmdqv_base, SMMU_VCMDQ_STATUS) & SMMU_VCMDQ_STATUS_ENABLED), &spin); + + uvm_mutex_init(&parent_gpu->smmu_war.smmu_lock, UVM_LOCK_ORDER_LEAF); + parent_gpu->smmu_war.smmu_prod = 0; + parent_gpu->smmu_war.smmu_cons = 0; + + return NV_OK; + +out: + iounmap(parent_gpu->smmu_war.smmu_cmdqv_base); + parent_gpu->smmu_war.smmu_cmdqv_base = NULL; + + return status; +} + +static void uvm_ats_smmu_war_deinit(uvm_parent_gpu_t *parent_gpu) +{ + void __iomem *smmu_cmdqv_base = parent_gpu->smmu_war.smmu_cmdqv_base; + NvU32 cmdq_alloc_map; + + if (parent_gpu->smmu_war.smmu_cmdqv_base) { + smmu_vcmdq_write32(smmu_cmdqv_base, SMMU_VCMDQ_CONFIG, 0); + cmdq_alloc_map = ioread32(smmu_cmdqv_base + SMMU_CMDQV_CMDQ_ALLOC_MAP(VCMDQ)); + iowrite32(cmdq_alloc_map & SMMU_CMDQV_CMDQ_ALLOC_MAP_ALLOC, smmu_cmdqv_base + SMMU_CMDQV_CMDQ_ALLOC_MAP(VCMDQ)); + smmu_vintf_write32(smmu_cmdqv_base, SMMU_VINTF_CONFIG, 0); + } + + if (parent_gpu->smmu_war.smmu_cmdq) + __free_page(parent_gpu->smmu_war.smmu_cmdq); + + if (parent_gpu->smmu_war.smmu_cmdqv_base) + iounmap(parent_gpu->smmu_war.smmu_cmdqv_base); +} + +// The SMMU on ARM64 can run under different translation regimes depending on +// what features the OS and CPU variant support. The CPU for GH180 supports +// virtualisation extensions and starts the kernel at EL2 meaning SMMU operates +// under the NS-EL2-E2H translation regime. Therefore we need to use the +// TLBI_EL2_* commands which invalidate TLB entries created under this +// translation regime. +#define CMDQ_OP_TLBI_EL2_ASID 0x21; +#define CMDQ_OP_TLBI_EL2_VA 0x22; +#define CMDQ_OP_CMD_SYNC 0x46 + +// Use the same maximum as used for MAX_TLBI_OPS in the upstream +// kernel. +#define UVM_MAX_TLBI_OPS (1UL << (PAGE_SHIFT - 3)) + +#if UVM_ATS_SMMU_WAR_REQUIRED() +void uvm_ats_smmu_invalidate_tlbs(uvm_gpu_va_space_t *gpu_va_space, NvU64 addr, size_t size) +{ + struct mm_struct *mm = gpu_va_space->va_space->va_space_mm.mm; + uvm_parent_gpu_t *parent_gpu = gpu_va_space->gpu->parent; + struct { + NvU64 low; + NvU64 high; + } *vcmdq; + unsigned long vcmdq_prod; + NvU64 end; + uvm_spin_loop_t spin; + NvU16 asid; + + if (!parent_gpu->smmu_war.smmu_cmdqv_base) + return; + + asid = arm64_mm_context_get(mm); + vcmdq = kmap(parent_gpu->smmu_war.smmu_cmdq); + uvm_mutex_lock(&parent_gpu->smmu_war.smmu_lock); + vcmdq_prod = parent_gpu->smmu_war.smmu_prod; + + // Our queue management is very simple. The mutex prevents multiple + // producers writing to the queue and all our commands require waiting for + // the queue to drain so we know it's empty. If we can't fit enough commands + // in the queue we just invalidate the whole ASID. + // + // The command queue is a cirular buffer with the MSB representing a wrap + // bit that must toggle on each wrap. See the SMMU architecture + // specification for more details. + // + // SMMU_VCMDQ_CMDQ_ENTRIES - 1 because we need to leave space for the + // CMD_SYNC. + if ((size >> PAGE_SHIFT) > min(UVM_MAX_TLBI_OPS, SMMU_VCMDQ_CMDQ_ENTRIES - 1)) { + vcmdq[vcmdq_prod % SMMU_VCMDQ_CMDQ_ENTRIES].low = CMDQ_OP_TLBI_EL2_ASID; + vcmdq[vcmdq_prod % SMMU_VCMDQ_CMDQ_ENTRIES].low |= (NvU64) asid << 48; + vcmdq[vcmdq_prod % SMMU_VCMDQ_CMDQ_ENTRIES].high = 0; + vcmdq_prod++; + } + else { + for (end = addr + size; addr < end; addr += PAGE_SIZE) { + vcmdq[vcmdq_prod % SMMU_VCMDQ_CMDQ_ENTRIES].low = CMDQ_OP_TLBI_EL2_VA; + vcmdq[vcmdq_prod % SMMU_VCMDQ_CMDQ_ENTRIES].low |= (NvU64) asid << 48; + vcmdq[vcmdq_prod % SMMU_VCMDQ_CMDQ_ENTRIES].high = addr & ~((1UL << 12) - 1); + vcmdq_prod++; + } + } + + vcmdq[vcmdq_prod % SMMU_VCMDQ_CMDQ_ENTRIES].low = CMDQ_OP_CMD_SYNC; + vcmdq[vcmdq_prod % SMMU_VCMDQ_CMDQ_ENTRIES].high = 0x0; + vcmdq_prod++; + + // MSB is the wrap bit + vcmdq_prod &= (1UL << (SMMU_VCMDQ_CMDQ_BASE_LOG2SIZE + 1)) - 1; + parent_gpu->smmu_war.smmu_prod = vcmdq_prod; + smmu_vcmdq_write32(parent_gpu->smmu_war.smmu_cmdqv_base, SMMU_VCMDQ_PROD, parent_gpu->smmu_war.smmu_prod); + + UVM_SPIN_WHILE( + (smmu_vcmdq_read32(parent_gpu->smmu_war.smmu_cmdqv_base, SMMU_VCMDQ_CONS) & GENMASK(19, 0)) != vcmdq_prod, + &spin); + + uvm_mutex_unlock(&parent_gpu->smmu_war.smmu_lock); + kunmap(parent_gpu->smmu_war.smmu_cmdq); + arm64_mm_context_put(mm); +} +#endif + NV_STATUS uvm_ats_sva_add_gpu(uvm_parent_gpu_t *parent_gpu) { int ret; ret = iommu_dev_enable_feature(&parent_gpu->pci_dev->dev, IOMMU_DEV_FEAT_SVA); + if (ret) + return errno_to_nv_status(ret); - return errno_to_nv_status(ret); + if (UVM_ATS_SMMU_WAR_REQUIRED()) + return uvm_ats_smmu_war_init(parent_gpu); + else + return NV_OK; } void uvm_ats_sva_remove_gpu(uvm_parent_gpu_t *parent_gpu) { + if (UVM_ATS_SMMU_WAR_REQUIRED()) + uvm_ats_smmu_war_deinit(parent_gpu); + iommu_dev_disable_feature(&parent_gpu->pci_dev->dev, IOMMU_DEV_FEAT_SVA); } diff --git a/kernel-open/nvidia-uvm/uvm_ats_sva.h b/kernel-open/nvidia-uvm/uvm_ats_sva.h index 7aecde30ea..1466c6e472 100644 --- a/kernel-open/nvidia-uvm/uvm_ats_sva.h +++ b/kernel-open/nvidia-uvm/uvm_ats_sva.h @@ -53,6 +53,17 @@ #define UVM_ATS_SVA_SUPPORTED() 0 #endif +// If NV_ARCH_INVALIDATE_SECONDARY_TLBS is defined it means the upstream fix is +// in place so no need for the WAR from Bug 4130089: [GH180][r535] WAR for +// kernel not issuing SMMU TLB invalidates on read-only +#if defined(NV_ARCH_INVALIDATE_SECONDARY_TLBS) + #define UVM_ATS_SMMU_WAR_REQUIRED() 0 +#elif NVCPU_IS_AARCH64 + #define UVM_ATS_SMMU_WAR_REQUIRED() 1 +#else + #define UVM_ATS_SMMU_WAR_REQUIRED() 0 +#endif + typedef struct { int placeholder; @@ -81,6 +92,17 @@ typedef struct // LOCKING: None void uvm_ats_sva_unregister_gpu_va_space(uvm_gpu_va_space_t *gpu_va_space); + + // Fix for Bug 4130089: [GH180][r535] WAR for kernel not issuing SMMU + // TLB invalidates on read-only to read-write upgrades + #if UVM_ATS_SMMU_WAR_REQUIRED() + void uvm_ats_smmu_invalidate_tlbs(uvm_gpu_va_space_t *gpu_va_space, NvU64 addr, size_t size); + #else + static void uvm_ats_smmu_invalidate_tlbs(uvm_gpu_va_space_t *gpu_va_space, NvU64 addr, size_t size) + { + + } + #endif #else static NV_STATUS uvm_ats_sva_add_gpu(uvm_parent_gpu_t *parent_gpu) { @@ -111,6 +133,11 @@ typedef struct { } + + static void uvm_ats_smmu_invalidate_tlbs(uvm_gpu_va_space_t *gpu_va_space, NvU64 addr, size_t size) + { + + } #endif // UVM_ATS_SVA_SUPPORTED #endif // __UVM_ATS_SVA_H__ diff --git a/kernel-open/nvidia-uvm/uvm_channel.c b/kernel-open/nvidia-uvm/uvm_channel.c index 8a17484f01..5474e8a466 100644 --- a/kernel-open/nvidia-uvm/uvm_channel.c +++ b/kernel-open/nvidia-uvm/uvm_channel.c @@ -2683,7 +2683,7 @@ static void init_channel_manager_conf(uvm_channel_manager_t *manager) // caches vidmem (and sysmem), we place GPFIFO and GPPUT on sysmem to avoid // cache thrash. The memory access latency is reduced, despite the required // access through the bus, because no cache coherence message is exchanged. - if (uvm_gpu_is_coherent(gpu->parent)) { + if (uvm_parent_gpu_is_coherent(gpu->parent)) { manager->conf.gpfifo_loc = UVM_BUFFER_LOCATION_SYS; // On GPUs with limited ESCHED addressing range, e.g., Volta on P9, RM diff --git a/kernel-open/nvidia-uvm/uvm_common.c b/kernel-open/nvidia-uvm/uvm_common.c index cc39f430df..1a4910e296 100644 --- a/kernel-open/nvidia-uvm/uvm_common.c +++ b/kernel-open/nvidia-uvm/uvm_common.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2013-2021 NVIDIA Corporation + Copyright (c) 2013-2023 NVIDIA Corporation This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License @@ -233,18 +233,6 @@ unsigned uvm_get_stale_thread_id(void) return (unsigned)task_pid_vnr(current); } -// -// A simple security rule for allowing access to UVM user space memory: if you -// are the same user as the owner of the memory, or if you are root, then you -// are granted access. The idea is to allow debuggers and profilers to work, but -// without opening up any security holes. -// -NvBool uvm_user_id_security_check(uid_t euidTarget) -{ - return (NV_CURRENT_EUID() == euidTarget) || - (UVM_ROOT_UID == euidTarget); -} - void on_uvm_test_fail(void) { (void)NULL; diff --git a/kernel-open/nvidia-uvm/uvm_common.h b/kernel-open/nvidia-uvm/uvm_common.h index 7631c2610c..cfc58b6fb1 100644 --- a/kernel-open/nvidia-uvm/uvm_common.h +++ b/kernel-open/nvidia-uvm/uvm_common.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2013-2021 NVIDIA Corporation + Copyright (c) 2013-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -282,9 +282,6 @@ static inline void kmem_cache_destroy_safe(struct kmem_cache **ppCache) } } -static const uid_t UVM_ROOT_UID = 0; - - typedef struct { NvU64 start_time_ns; @@ -335,7 +332,6 @@ NV_STATUS errno_to_nv_status(int errnoCode); int nv_status_to_errno(NV_STATUS status); unsigned uvm_get_stale_process_id(void); unsigned uvm_get_stale_thread_id(void); -NvBool uvm_user_id_security_check(uid_t euidTarget); extern int uvm_enable_builtin_tests; diff --git a/kernel-open/nvidia-uvm/uvm_conf_computing.c b/kernel-open/nvidia-uvm/uvm_conf_computing.c index 34fe900437..4927948d90 100644 --- a/kernel-open/nvidia-uvm/uvm_conf_computing.c +++ b/kernel-open/nvidia-uvm/uvm_conf_computing.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2021-2023 NVIDIA Corporation + Copyright (c) 2021 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -54,26 +54,23 @@ bool uvm_conf_computing_mode_is_hcc(const uvm_gpu_t *gpu) return uvm_conf_computing_get_mode(gpu->parent) == UVM_GPU_CONF_COMPUTE_MODE_HCC; } -void uvm_conf_computing_check_parent_gpu(const uvm_parent_gpu_t *parent) +NV_STATUS uvm_conf_computing_init_parent_gpu(const uvm_parent_gpu_t *parent) { - uvm_gpu_t *first_gpu; + UvmGpuConfComputeMode cc, sys_cc; + uvm_gpu_t *first; uvm_assert_mutex_locked(&g_uvm_global.global_lock); - // The Confidential Computing state of the GPU should match that of the - // system. - UVM_ASSERT(uvm_conf_computing_mode_enabled_parent(parent) == g_uvm_global.conf_computing_enabled); - // TODO: Bug 2844714: since we have no routine to traverse parent GPUs, // find first child GPU and get its parent. - first_gpu = uvm_global_processor_mask_find_first_gpu(&g_uvm_global.retained_gpus); - if (first_gpu == NULL) - return; + first = uvm_global_processor_mask_find_first_gpu(&g_uvm_global.retained_gpus); + if (!first) + return NV_OK; + + sys_cc = uvm_conf_computing_get_mode(first->parent); + cc = uvm_conf_computing_get_mode(parent); - // All GPUs derive Confidential Computing status from their parent. By - // current policy all parent GPUs have identical Confidential Computing - // status. - UVM_ASSERT(uvm_conf_computing_get_mode(parent) == uvm_conf_computing_get_mode(first_gpu->parent)); + return cc == sys_cc ? NV_OK : NV_ERR_NOT_SUPPORTED; } static void dma_buffer_destroy_locked(uvm_conf_computing_dma_buffer_pool_t *dma_buffer_pool, diff --git a/kernel-open/nvidia-uvm/uvm_conf_computing.h b/kernel-open/nvidia-uvm/uvm_conf_computing.h index c06eafe51e..99b6d96276 100644 --- a/kernel-open/nvidia-uvm/uvm_conf_computing.h +++ b/kernel-open/nvidia-uvm/uvm_conf_computing.h @@ -60,8 +60,10 @@ // UVM_METHOD_SIZE * 2 * 10 = 80. #define UVM_CONF_COMPUTING_SIGN_BUF_MAX_SIZE 80 -void uvm_conf_computing_check_parent_gpu(const uvm_parent_gpu_t *parent); - +// All GPUs derive confidential computing status from their parent. +// By current policy all parent GPUs have identical confidential +// computing status. +NV_STATUS uvm_conf_computing_init_parent_gpu(const uvm_parent_gpu_t *parent); bool uvm_conf_computing_mode_enabled_parent(const uvm_parent_gpu_t *parent); bool uvm_conf_computing_mode_enabled(const uvm_gpu_t *gpu); bool uvm_conf_computing_mode_is_hcc(const uvm_gpu_t *gpu); diff --git a/kernel-open/nvidia-uvm/uvm_global.c b/kernel-open/nvidia-uvm/uvm_global.c index c38010adc7..42af70ef71 100644 --- a/kernel-open/nvidia-uvm/uvm_global.c +++ b/kernel-open/nvidia-uvm/uvm_global.c @@ -71,6 +71,11 @@ static void uvm_unregister_callbacks(void) } } +static void sev_init(const UvmPlatformInfo *platform_info) +{ + g_uvm_global.sev_enabled = platform_info->sevEnabled; +} + NV_STATUS uvm_global_init(void) { NV_STATUS status; @@ -119,7 +124,8 @@ NV_STATUS uvm_global_init(void) uvm_ats_init(&platform_info); g_uvm_global.num_simulated_devices = 0; - g_uvm_global.conf_computing_enabled = platform_info.confComputingEnabled; + + sev_init(&platform_info); status = uvm_gpu_init(); if (status != NV_OK) { diff --git a/kernel-open/nvidia-uvm/uvm_global.h b/kernel-open/nvidia-uvm/uvm_global.h index 808d06ca4f..8c92bbc067 100644 --- a/kernel-open/nvidia-uvm/uvm_global.h +++ b/kernel-open/nvidia-uvm/uvm_global.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2023 NVIDIA Corporation + Copyright (c) 2015-2021 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -143,16 +143,11 @@ struct uvm_global_struct struct page *page; } unload_state; - // True if the VM has AMD's SEV, or equivalent HW security extensions such - // as Intel's TDX, enabled. The flag is always false on the host. - // - // This value moves in tandem with that of Confidential Computing in the - // GPU(s) in all supported configurations, so it is used as a proxy for the - // Confidential Computing state. - // - // This field is set once during global initialization (uvm_global_init), - // and can be read afterwards without acquiring any locks. - bool conf_computing_enabled; + // AMD Secure Encrypted Virtualization (SEV) status. True if VM has SEV + // enabled. This field is set once during global initialization + // (uvm_global_init), and can be read afterwards without acquiring any + // locks. + bool sev_enabled; }; // Initialize global uvm state @@ -238,10 +233,8 @@ static uvm_gpu_t *uvm_gpu_get_by_processor_id(uvm_processor_id_t id) return gpu; } -static uvmGpuSessionHandle uvm_gpu_session_handle(uvm_gpu_t *gpu) +static uvmGpuSessionHandle uvm_global_session_handle(void) { - if (gpu->parent->smc.enabled) - return gpu->smc.rm_session_handle; return g_uvm_global.rm_session_handle; } diff --git a/kernel-open/nvidia-uvm/uvm_gpu.c b/kernel-open/nvidia-uvm/uvm_gpu.c index 6e4551b187..0967281b3c 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu.c +++ b/kernel-open/nvidia-uvm/uvm_gpu.c @@ -99,8 +99,8 @@ static void fill_gpu_info(uvm_parent_gpu_t *parent_gpu, const UvmGpuInfo *gpu_in parent_gpu->system_bus.link_rate_mbyte_per_s = gpu_info->sysmemLinkRateMBps; if (gpu_info->systemMemoryWindowSize > 0) { - // memory_window_end is inclusive but uvm_gpu_is_coherent() checks - // memory_window_end > memory_window_start as its condition. + // memory_window_end is inclusive but uvm_parent_gpu_is_coherent() + // checks memory_window_end > memory_window_start as its condition. UVM_ASSERT(gpu_info->systemMemoryWindowSize > 1); parent_gpu->system_bus.memory_window_start = gpu_info->systemMemoryWindowStart; parent_gpu->system_bus.memory_window_end = gpu_info->systemMemoryWindowStart + @@ -136,12 +136,12 @@ static NV_STATUS get_gpu_caps(uvm_gpu_t *gpu) return status; if (gpu_caps.numaEnabled) { - UVM_ASSERT(uvm_gpu_is_coherent(gpu->parent)); + UVM_ASSERT(uvm_parent_gpu_is_coherent(gpu->parent)); gpu->mem_info.numa.enabled = true; gpu->mem_info.numa.node_id = gpu_caps.numaNodeId; } else { - UVM_ASSERT(!uvm_gpu_is_coherent(gpu->parent)); + UVM_ASSERT(!uvm_parent_gpu_is_coherent(gpu->parent)); } return NV_OK; @@ -1089,7 +1089,7 @@ static NV_STATUS init_parent_gpu(uvm_parent_gpu_t *parent_gpu, { NV_STATUS status; - status = uvm_rm_locked_call(nvUvmInterfaceDeviceCreate(g_uvm_global.rm_session_handle, + status = uvm_rm_locked_call(nvUvmInterfaceDeviceCreate(uvm_global_session_handle(), gpu_info, gpu_uuid, &parent_gpu->rm_device, @@ -1099,7 +1099,12 @@ static NV_STATUS init_parent_gpu(uvm_parent_gpu_t *parent_gpu, return status; } - uvm_conf_computing_check_parent_gpu(parent_gpu); + status = uvm_conf_computing_init_parent_gpu(parent_gpu); + if (status != NV_OK) { + UVM_ERR_PRINT("Confidential computing: %s, GPU %s\n", + nvstatusToString(status), parent_gpu->name); + return status; + } parent_gpu->pci_dev = gpu_platform_info->pci_dev; parent_gpu->closest_cpu_numa_node = dev_to_node(&parent_gpu->pci_dev->dev); @@ -1161,19 +1166,8 @@ static NV_STATUS init_gpu(uvm_gpu_t *gpu, const UvmGpuInfo *gpu_info) { NV_STATUS status; - // Presently, an RM client can only subscribe to a single partition per - // GPU. Therefore, UVM needs to create several RM clients. For simplicity, - // and since P2P is not supported when SMC partitions are created, we - // create a client (session) per GPU partition. if (gpu->parent->smc.enabled) { - UvmPlatformInfo platform_info; - status = uvm_rm_locked_call(nvUvmInterfaceSessionCreate(&gpu->smc.rm_session_handle, &platform_info)); - if (status != NV_OK) { - UVM_ERR_PRINT("Creating RM session failed: %s\n", nvstatusToString(status)); - return status; - } - - status = uvm_rm_locked_call(nvUvmInterfaceDeviceCreate(uvm_gpu_session_handle(gpu), + status = uvm_rm_locked_call(nvUvmInterfaceDeviceCreate(uvm_global_session_handle(), gpu_info, uvm_gpu_uuid(gpu), &gpu->smc.rm_device, @@ -1543,9 +1537,6 @@ static void deinit_gpu(uvm_gpu_t *gpu) if (gpu->parent->smc.enabled) { if (gpu->smc.rm_device != 0) uvm_rm_locked_call_void(nvUvmInterfaceDeviceDestroy(gpu->smc.rm_device)); - - if (gpu->smc.rm_session_handle != 0) - uvm_rm_locked_call_void(nvUvmInterfaceSessionDestroy(gpu->smc.rm_session_handle)); } gpu->magic = 0; @@ -2575,7 +2566,7 @@ static void disable_peer_access(uvm_gpu_t *gpu0, uvm_gpu_t *gpu1) uvm_mmu_destroy_peer_identity_mappings(gpu0, gpu1); uvm_mmu_destroy_peer_identity_mappings(gpu1, gpu0); - uvm_rm_locked_call_void(nvUvmInterfaceP2pObjectDestroy(uvm_gpu_session_handle(gpu0), p2p_handle)); + uvm_rm_locked_call_void(nvUvmInterfaceP2pObjectDestroy(uvm_global_session_handle(), p2p_handle)); UVM_ASSERT(uvm_gpu_get(gpu0->global_id) == gpu0); UVM_ASSERT(uvm_gpu_get(gpu1->global_id) == gpu1); @@ -2701,9 +2692,9 @@ uvm_processor_id_t uvm_gpu_get_processor_id_by_address(uvm_gpu_t *gpu, uvm_gpu_p return id; } -uvm_gpu_peer_t *uvm_gpu_index_peer_caps(const uvm_gpu_id_t gpu_id1, const uvm_gpu_id_t gpu_id2) +uvm_gpu_peer_t *uvm_gpu_index_peer_caps(const uvm_gpu_id_t gpu_id0, const uvm_gpu_id_t gpu_id1) { - NvU32 table_index = uvm_gpu_peer_table_index(gpu_id1, gpu_id2); + NvU32 table_index = uvm_gpu_peer_table_index(gpu_id0, gpu_id1); return &g_uvm_global.peers[table_index]; } diff --git a/kernel-open/nvidia-uvm/uvm_gpu.h b/kernel-open/nvidia-uvm/uvm_gpu.h index 8e13f6fe4e..03c9a0ba8b 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu.h +++ b/kernel-open/nvidia-uvm/uvm_gpu.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -167,7 +167,7 @@ struct uvm_service_block_context_struct } per_processor_masks[UVM_ID_MAX_PROCESSORS]; // State used by the VA block routines called by the servicing routine - uvm_va_block_context_t block_context; + uvm_va_block_context_t *block_context; // Prefetch state hint uvm_perf_prefetch_hint_t prefetch_hint; @@ -263,7 +263,10 @@ struct uvm_fault_service_batch_context_struct NvU32 num_coalesced_faults; - bool has_fatal_faults; + // One of the VA spaces in this batch which had fatal faults. If NULL, no + // faults were fatal. More than one VA space could have fatal faults, but we + // pick one to be the target of the cancel sequence. + uvm_va_space_t *fatal_va_space; bool has_throttled_faults; @@ -825,8 +828,6 @@ struct uvm_gpu_struct { NvU32 swizz_id; - uvmGpuSessionHandle rm_session_handle; - // RM device handle used in many of the UVM/RM APIs. // // Do not read this field directly, use uvm_gpu_device_handle instead. @@ -1162,6 +1163,16 @@ struct uvm_parent_gpu_struct NvU64 memory_window_start; NvU64 memory_window_end; } system_bus; + + // WAR to issue ATS TLB invalidation commands ourselves. + struct + { + uvm_mutex_t smmu_lock; + struct page *smmu_cmdq; + void __iomem *smmu_cmdqv_base; + unsigned long smmu_prod; + unsigned long smmu_cons; + } smmu_war; }; static const char *uvm_gpu_name(uvm_gpu_t *gpu) @@ -1336,7 +1347,7 @@ static NvU64 uvm_gpu_retained_count(uvm_gpu_t *gpu) void uvm_parent_gpu_kref_put(uvm_parent_gpu_t *gpu); // Calculates peer table index using GPU ids. -NvU32 uvm_gpu_peer_table_index(uvm_gpu_id_t gpu_id1, uvm_gpu_id_t gpu_id2); +NvU32 uvm_gpu_peer_table_index(const uvm_gpu_id_t gpu_id0, const uvm_gpu_id_t gpu_id1); // Either retains an existing PCIe peer entry or creates a new one. In both // cases the two GPUs are also each retained. @@ -1355,7 +1366,7 @@ uvm_aperture_t uvm_gpu_peer_aperture(uvm_gpu_t *local_gpu, uvm_gpu_t *remote_gpu uvm_processor_id_t uvm_gpu_get_processor_id_by_address(uvm_gpu_t *gpu, uvm_gpu_phys_address_t addr); // Get the P2P capabilities between the gpus with the given indexes -uvm_gpu_peer_t *uvm_gpu_index_peer_caps(uvm_gpu_id_t gpu_id1, uvm_gpu_id_t gpu_id2); +uvm_gpu_peer_t *uvm_gpu_index_peer_caps(const uvm_gpu_id_t gpu_id0, const uvm_gpu_id_t gpu_id1); // Get the P2P capabilities between the given gpus static uvm_gpu_peer_t *uvm_gpu_peer_caps(const uvm_gpu_t *gpu0, const uvm_gpu_t *gpu1) @@ -1363,10 +1374,10 @@ static uvm_gpu_peer_t *uvm_gpu_peer_caps(const uvm_gpu_t *gpu0, const uvm_gpu_t return uvm_gpu_index_peer_caps(gpu0->id, gpu1->id); } -static bool uvm_gpus_are_nvswitch_connected(uvm_gpu_t *gpu1, uvm_gpu_t *gpu2) +static bool uvm_gpus_are_nvswitch_connected(const uvm_gpu_t *gpu0, const uvm_gpu_t *gpu1) { - if (gpu1->parent->nvswitch_info.is_nvswitch_connected && gpu2->parent->nvswitch_info.is_nvswitch_connected) { - UVM_ASSERT(uvm_gpu_peer_caps(gpu1, gpu2)->link_type >= UVM_GPU_LINK_NVLINK_2); + if (gpu0->parent->nvswitch_info.is_nvswitch_connected && gpu1->parent->nvswitch_info.is_nvswitch_connected) { + UVM_ASSERT(uvm_gpu_peer_caps(gpu0, gpu1)->link_type >= UVM_GPU_LINK_NVLINK_2); return true; } @@ -1511,7 +1522,7 @@ bool uvm_gpu_can_address_kernel(uvm_gpu_t *gpu, NvU64 addr, NvU64 size); // addresses. NvU64 uvm_parent_gpu_canonical_address(uvm_parent_gpu_t *parent_gpu, NvU64 addr); -static bool uvm_gpu_is_coherent(const uvm_parent_gpu_t *parent_gpu) +static bool uvm_parent_gpu_is_coherent(const uvm_parent_gpu_t *parent_gpu) { return parent_gpu->system_bus.memory_window_end > parent_gpu->system_bus.memory_window_start; } diff --git a/kernel-open/nvidia-uvm/uvm_gpu_access_counters.c b/kernel-open/nvidia-uvm/uvm_gpu_access_counters.c index b3d3a3d3e9..e0d40a2ce8 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu_access_counters.c +++ b/kernel-open/nvidia-uvm/uvm_gpu_access_counters.c @@ -985,7 +985,7 @@ static NV_STATUS service_va_block_locked(uvm_processor_id_t processor, return NV_OK; if (uvm_processor_mask_test(&va_block->resident, processor)) - residency_mask = uvm_va_block_resident_mask_get(va_block, processor); + residency_mask = uvm_va_block_resident_mask_get(va_block, processor, NUMA_NO_NODE); else residency_mask = NULL; @@ -1036,8 +1036,8 @@ static NV_STATUS service_va_block_locked(uvm_processor_id_t processor, // If the underlying VMA is gone, skip HMM migrations. if (uvm_va_block_is_hmm(va_block)) { - status = uvm_hmm_find_vma(service_context->block_context.mm, - &service_context->block_context.hmm.vma, + status = uvm_hmm_find_vma(service_context->block_context->mm, + &service_context->block_context->hmm.vma, address); if (status == NV_ERR_INVALID_ADDRESS) continue; @@ -1048,7 +1048,7 @@ static NV_STATUS service_va_block_locked(uvm_processor_id_t processor, policy = uvm_va_policy_get(va_block, address); new_residency = uvm_va_block_select_residency(va_block, - &service_context->block_context, + service_context->block_context, page_index, processor, uvm_fault_access_type_mask_bit(UVM_FAULT_ACCESS_TYPE_PREFETCH), @@ -1083,7 +1083,7 @@ static NV_STATUS service_va_block_locked(uvm_processor_id_t processor, // Remove pages that are already resident in the destination processors for_each_id_in_mask(id, &update_processors) { bool migrate_pages; - uvm_page_mask_t *residency_mask = uvm_va_block_resident_mask_get(va_block, id); + uvm_page_mask_t *residency_mask = uvm_va_block_resident_mask_get(va_block, id, NUMA_NO_NODE); UVM_ASSERT(residency_mask); migrate_pages = uvm_page_mask_andnot(&service_context->per_processor_masks[uvm_id_value(id)].new_residency, @@ -1101,9 +1101,9 @@ static NV_STATUS service_va_block_locked(uvm_processor_id_t processor, if (uvm_va_block_is_hmm(va_block)) { status = NV_ERR_INVALID_ADDRESS; - if (service_context->block_context.mm) { + if (service_context->block_context->mm) { status = uvm_hmm_find_policy_vma_and_outer(va_block, - &service_context->block_context.hmm.vma, + &service_context->block_context->hmm.vma, first_page_index, &policy, &outer); @@ -1206,7 +1206,7 @@ static NV_STATUS service_phys_single_va_block(uvm_gpu_t *gpu, service_context->operation = UVM_SERVICE_OPERATION_ACCESS_COUNTERS; service_context->num_retries = 0; - service_context->block_context.mm = mm; + service_context->block_context->mm = mm; if (uvm_va_block_is_hmm(va_block)) { uvm_hmm_service_context_init(service_context); diff --git a/kernel-open/nvidia-uvm/uvm_gpu_isr.c b/kernel-open/nvidia-uvm/uvm_gpu_isr.c index 1b3770ada0..33e7142d21 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu_isr.c +++ b/kernel-open/nvidia-uvm/uvm_gpu_isr.c @@ -292,6 +292,7 @@ NV_STATUS uvm_gpu_init_isr(uvm_parent_gpu_t *parent_gpu) { NV_STATUS status = NV_OK; char kthread_name[TASK_COMM_LEN + 1]; + uvm_va_block_context_t *block_context; if (parent_gpu->replayable_faults_supported) { status = uvm_gpu_fault_buffer_init(parent_gpu); @@ -311,6 +312,12 @@ NV_STATUS uvm_gpu_init_isr(uvm_parent_gpu_t *parent_gpu) if (!parent_gpu->isr.replayable_faults.stats.cpu_exec_count) return NV_ERR_NO_MEMORY; + block_context = uvm_va_block_context_alloc(NULL); + if (!block_context) + return NV_ERR_NO_MEMORY; + + parent_gpu->fault_buffer_info.replayable.block_service_context.block_context = block_context; + parent_gpu->isr.replayable_faults.handling = true; snprintf(kthread_name, sizeof(kthread_name), "UVM GPU%u BH", uvm_id_value(parent_gpu->id)); @@ -333,6 +340,12 @@ NV_STATUS uvm_gpu_init_isr(uvm_parent_gpu_t *parent_gpu) if (!parent_gpu->isr.non_replayable_faults.stats.cpu_exec_count) return NV_ERR_NO_MEMORY; + block_context = uvm_va_block_context_alloc(NULL); + if (!block_context) + return NV_ERR_NO_MEMORY; + + parent_gpu->fault_buffer_info.non_replayable.block_service_context.block_context = block_context; + parent_gpu->isr.non_replayable_faults.handling = true; snprintf(kthread_name, sizeof(kthread_name), "UVM GPU%u KC", uvm_id_value(parent_gpu->id)); @@ -356,6 +369,13 @@ NV_STATUS uvm_gpu_init_isr(uvm_parent_gpu_t *parent_gpu) return status; } + block_context = uvm_va_block_context_alloc(NULL); + if (!block_context) + return NV_ERR_NO_MEMORY; + + parent_gpu->access_counter_buffer_info.batch_service_context.block_service_context.block_context = + block_context; + nv_kthread_q_item_init(&parent_gpu->isr.access_counters.bottom_half_q_item, access_counters_isr_bottom_half_entry, parent_gpu); @@ -410,6 +430,8 @@ void uvm_gpu_disable_isr(uvm_parent_gpu_t *parent_gpu) void uvm_gpu_deinit_isr(uvm_parent_gpu_t *parent_gpu) { + uvm_va_block_context_t *block_context; + // Return ownership to RM: if (parent_gpu->isr.replayable_faults.was_handling) { // No user threads could have anything left on @@ -439,8 +461,18 @@ void uvm_gpu_deinit_isr(uvm_parent_gpu_t *parent_gpu) // It is safe to deinitialize access counters even if they have not been // successfully initialized. uvm_gpu_deinit_access_counters(parent_gpu); + block_context = + parent_gpu->access_counter_buffer_info.batch_service_context.block_service_context.block_context; + uvm_va_block_context_free(block_context); + } + + if (parent_gpu->non_replayable_faults_supported) { + block_context = parent_gpu->fault_buffer_info.non_replayable.block_service_context.block_context; + uvm_va_block_context_free(block_context); } + block_context = parent_gpu->fault_buffer_info.replayable.block_service_context.block_context; + uvm_va_block_context_free(block_context); uvm_kvfree(parent_gpu->isr.replayable_faults.stats.cpu_exec_count); uvm_kvfree(parent_gpu->isr.non_replayable_faults.stats.cpu_exec_count); uvm_kvfree(parent_gpu->isr.access_counters.stats.cpu_exec_count); diff --git a/kernel-open/nvidia-uvm/uvm_gpu_non_replayable_faults.c b/kernel-open/nvidia-uvm/uvm_gpu_non_replayable_faults.c index 3ba2cde206..2f3d10f1e9 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu_non_replayable_faults.c +++ b/kernel-open/nvidia-uvm/uvm_gpu_non_replayable_faults.c @@ -370,7 +370,7 @@ static NV_STATUS service_managed_fault_in_block_locked(uvm_gpu_t *gpu, // Check logical permissions status = uvm_va_block_check_logical_permissions(va_block, - &service_context->block_context, + service_context->block_context, gpu->id, uvm_va_block_cpu_page_index(va_block, fault_entry->fault_address), @@ -393,7 +393,7 @@ static NV_STATUS service_managed_fault_in_block_locked(uvm_gpu_t *gpu, // Compute new residency and update the masks new_residency = uvm_va_block_select_residency(va_block, - &service_context->block_context, + service_context->block_context, page_index, gpu->id, fault_entry->access_type_mask, @@ -629,7 +629,7 @@ static NV_STATUS service_fault(uvm_gpu_t *gpu, uvm_fault_buffer_entry_t *fault_e uvm_gpu_va_space_t *gpu_va_space; uvm_non_replayable_fault_buffer_info_t *non_replayable_faults = &gpu->parent->fault_buffer_info.non_replayable; uvm_va_block_context_t *va_block_context = - &gpu->parent->fault_buffer_info.non_replayable.block_service_context.block_context; + gpu->parent->fault_buffer_info.non_replayable.block_service_context.block_context; status = uvm_gpu_fault_entry_to_va_space(gpu, fault_entry, &va_space); if (status != NV_OK) { @@ -655,7 +655,7 @@ static NV_STATUS service_fault(uvm_gpu_t *gpu, uvm_fault_buffer_entry_t *fault_e // to remain valid until we release. If no mm is registered, we // can only service managed faults, not ATS/HMM faults. mm = uvm_va_space_mm_retain_lock(va_space); - va_block_context->mm = mm; + uvm_va_block_context_init(va_block_context, mm); uvm_va_space_down_read(va_space); diff --git a/kernel-open/nvidia-uvm/uvm_gpu_replayable_faults.c b/kernel-open/nvidia-uvm/uvm_gpu_replayable_faults.c index 63642e8f37..5b8a6d57f3 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu_replayable_faults.c +++ b/kernel-open/nvidia-uvm/uvm_gpu_replayable_faults.c @@ -1180,7 +1180,11 @@ static void mark_fault_fatal(uvm_fault_service_batch_context_t *batch_context, fault_entry->replayable.cancel_va_mode = cancel_va_mode; utlb->has_fatal_faults = true; - batch_context->has_fatal_faults = true; + + if (!batch_context->fatal_va_space) { + UVM_ASSERT(fault_entry->va_space); + batch_context->fatal_va_space = fault_entry->va_space; + } } static void fault_entry_duplicate_flags(uvm_fault_service_batch_context_t *batch_context, @@ -1230,7 +1234,7 @@ static uvm_fault_access_type_t check_fault_access_permissions(uvm_gpu_t *gpu, UvmEventFatalReason fatal_reason; uvm_fault_cancel_va_mode_t cancel_va_mode; uvm_fault_access_type_t ret = UVM_FAULT_ACCESS_TYPE_COUNT; - uvm_va_block_context_t *va_block_context = &service_block_context->block_context; + uvm_va_block_context_t *va_block_context = service_block_context->block_context; perm_status = uvm_va_block_check_logical_permissions(va_block, va_block_context, @@ -1345,7 +1349,7 @@ static NV_STATUS service_fault_batch_block_locked(uvm_gpu_t *gpu, if (uvm_va_block_is_hmm(va_block)) { policy = uvm_hmm_find_policy_end(va_block, - block_context->block_context.hmm.vma, + block_context->block_context->hmm.vma, ordered_fault_cache[first_fault_index]->fault_address, &end); } @@ -1469,7 +1473,7 @@ static NV_STATUS service_fault_batch_block_locked(uvm_gpu_t *gpu, // Compute new residency and update the masks new_residency = uvm_va_block_select_residency(va_block, - &block_context->block_context, + block_context->block_context, page_index, gpu->id, service_access_type_mask, @@ -1511,8 +1515,8 @@ static NV_STATUS service_fault_batch_block_locked(uvm_gpu_t *gpu, ++block_context->num_retries; - if (status == NV_OK && batch_context->has_fatal_faults) - status = uvm_va_block_set_cancel(va_block, &block_context->block_context, gpu); + if (status == NV_OK && batch_context->fatal_va_space) + status = uvm_va_block_set_cancel(va_block, block_context->block_context, gpu); return status; } @@ -1860,7 +1864,7 @@ static NV_STATUS service_fault_batch_dispatch(uvm_va_space_t *va_space, uvm_va_block_t *va_block; uvm_gpu_t *gpu = gpu_va_space->gpu; uvm_va_block_context_t *va_block_context = - &gpu->parent->fault_buffer_info.replayable.block_service_context.block_context; + gpu->parent->fault_buffer_info.replayable.block_service_context.block_context; uvm_fault_buffer_entry_t *current_entry = batch_context->ordered_fault_cache[fault_index]; struct mm_struct *mm = va_block_context->mm; NvU64 fault_address = current_entry->fault_address; @@ -1937,14 +1941,198 @@ static NV_STATUS service_fault_batch_dispatch(uvm_va_space_t *va_space, return status; } +// Called when a fault in the batch has been marked fatal. Flush the buffer +// under the VA and mmap locks to remove any potential stale fatal faults, then +// service all new faults for just that VA space and cancel those which are +// fatal. Faults in other VA spaces are replayed when done and will be processed +// when normal fault servicing resumes. +static NV_STATUS service_fault_batch_for_cancel(uvm_gpu_t *gpu, uvm_fault_service_batch_context_t *batch_context) +{ + NV_STATUS status = NV_OK; + NvU32 i; + uvm_va_space_t *va_space = batch_context->fatal_va_space; + uvm_gpu_va_space_t *gpu_va_space = NULL; + struct mm_struct *mm; + uvm_replayable_fault_buffer_info_t *replayable_faults = &gpu->parent->fault_buffer_info.replayable; + uvm_service_block_context_t *service_context = &gpu->parent->fault_buffer_info.replayable.block_service_context; + uvm_va_block_context_t *va_block_context = service_context->block_context; + + UVM_ASSERT(gpu->parent->replayable_faults_supported); + UVM_ASSERT(va_space); + + // Perform the flush and re-fetch while holding the mmap_lock and the + // VA space lock. This avoids stale faults because it prevents any vma + // modifications (mmap, munmap, mprotect) from happening between the time HW + // takes the fault and we cancel it. + mm = uvm_va_space_mm_retain_lock(va_space); + uvm_va_block_context_init(va_block_context, mm); + uvm_va_space_down_read(va_space); + + // We saw fatal faults in this VA space before. Flush while holding + // mmap_lock to make sure those faults come back (aren't stale). + // + // We need to wait until all old fault messages have arrived before + // flushing, hence UVM_GPU_BUFFER_FLUSH_MODE_WAIT_UPDATE_PUT. + status = fault_buffer_flush_locked(gpu, + UVM_GPU_BUFFER_FLUSH_MODE_WAIT_UPDATE_PUT, + UVM_FAULT_REPLAY_TYPE_START, + batch_context); + if (status != NV_OK) + goto done; + + // Wait for the flush's replay to finish to give the legitimate faults a + // chance to show up in the buffer again. + status = uvm_tracker_wait(&replayable_faults->replay_tracker); + if (status != NV_OK) + goto done; + + // We expect all replayed faults to have arrived in the buffer so we can re- + // service them. The replay-and-wait sequence above will ensure they're all + // in the HW buffer. When GSP owns the HW buffer, we also have to wait for + // GSP to copy all available faults from the HW buffer into the shadow + // buffer. + // + // TODO: Bug 2533557: This flush does not actually guarantee that GSP will + // copy over all faults. + status = hw_fault_buffer_flush_locked(gpu->parent); + if (status != NV_OK) + goto done; + + // If there is no GPU VA space for the GPU, ignore all faults in the VA + // space. This can happen if the GPU VA space has been destroyed since we + // unlocked the VA space in service_fault_batch. That means the fatal faults + // are stale, because unregistering the GPU VA space requires preempting the + // context and detaching all channels in that VA space. Restart fault + // servicing from the top. + gpu_va_space = uvm_gpu_va_space_get_by_parent_gpu(va_space, gpu->parent); + if (!gpu_va_space) + goto done; + + // Re-parse the new faults + batch_context->num_invalid_prefetch_faults = 0; + batch_context->num_duplicate_faults = 0; + batch_context->num_replays = 0; + batch_context->fatal_va_space = NULL; + batch_context->has_throttled_faults = false; + + status = fetch_fault_buffer_entries(gpu, batch_context, FAULT_FETCH_MODE_ALL); + if (status != NV_OK) + goto done; + + // No more faults left. Either the previously-seen fatal entry was stale, or + // RM killed the context underneath us. + if (batch_context->num_cached_faults == 0) + goto done; + + ++batch_context->batch_id; + + status = preprocess_fault_batch(gpu, batch_context); + if (status != NV_OK) { + if (status == NV_WARN_MORE_PROCESSING_REQUIRED) { + // Another flush happened due to stale faults or a context-fatal + // error. The previously-seen fatal fault might not exist anymore, + // so restart fault servicing from the top. + status = NV_OK; + } + + goto done; + } + + // Search for the target VA space + for (i = 0; i < batch_context->num_coalesced_faults; i++) { + uvm_fault_buffer_entry_t *current_entry = batch_context->ordered_fault_cache[i]; + UVM_ASSERT(current_entry->va_space); + if (current_entry->va_space == va_space) + break; + } + + while (i < batch_context->num_coalesced_faults) { + uvm_fault_buffer_entry_t *current_entry = batch_context->ordered_fault_cache[i]; + + if (current_entry->va_space != va_space) + break; + + // service_fault_batch_dispatch() doesn't expect unserviceable faults. + // Just cancel them directly. + if (current_entry->is_fatal) { + status = cancel_fault_precise_va(gpu, current_entry, UVM_FAULT_CANCEL_VA_MODE_ALL); + if (status != NV_OK) + break; + + ++i; + } + else { + uvm_ats_fault_invalidate_t *ats_invalidate = &gpu->parent->fault_buffer_info.replayable.ats_invalidate; + NvU32 block_faults; + + ats_invalidate->write_faults_in_batch = false; + uvm_hmm_service_context_init(service_context); + + // Service all the faults that we can. We only really need to search + // for fatal faults, but attempting to service all is the easiest + // way to do that. + status = service_fault_batch_dispatch(va_space, gpu_va_space, batch_context, i, &block_faults, false); + if (status != NV_OK) { + // TODO: Bug 3900733: clean up locking in service_fault_batch(). + // We need to drop lock and retry. That means flushing and + // starting over. + if (status == NV_WARN_MORE_PROCESSING_REQUIRED) + status = NV_OK; + + break; + } + + // Invalidate TLBs before cancel to ensure that fatal faults don't + // get stuck in HW behind non-fatal faults to the same line. + status = uvm_ats_invalidate_tlbs(gpu_va_space, ats_invalidate, &batch_context->tracker); + if (status != NV_OK) + break; + + while (block_faults-- > 0) { + current_entry = batch_context->ordered_fault_cache[i]; + if (current_entry->is_fatal) { + status = cancel_fault_precise_va(gpu, current_entry, current_entry->replayable.cancel_va_mode); + if (status != NV_OK) + break; + } + + ++i; + } + } + } + +done: + uvm_va_space_up_read(va_space); + uvm_va_space_mm_release_unlock(va_space, mm); + + if (status == NV_OK) { + // There are two reasons to flush the fault buffer here. + // + // 1) Functional. We need to replay both the serviced non-fatal faults + // and the skipped faults in other VA spaces. The former need to be + // restarted and the latter need to be replayed so the normal fault + // service mechanism can fetch and process them. + // + // 2) Performance. After cancelling the fatal faults, a flush removes + // any potential duplicated fault that may have been added while + // processing the faults in this batch. This flush also avoids doing + // unnecessary processing after the fatal faults have been cancelled, + // so all the rest are unlikely to remain after a replay because the + // context is probably in the process of dying. + status = fault_buffer_flush_locked(gpu, + UVM_GPU_BUFFER_FLUSH_MODE_UPDATE_PUT, + UVM_FAULT_REPLAY_TYPE_START, + batch_context); + } + + return status; +} // Scan the ordered view of faults and group them by different va_blocks // (managed faults) and service faults for each va_block, in batch. // Service non-managed faults one at a time as they are encountered during the // scan. // -// This function returns NV_WARN_MORE_PROCESSING_REQUIRED if the fault buffer -// was flushed because the needs_fault_buffer_flush flag was set on some GPU VA -// space +// Fatal faults are marked for later processing by the caller. static NV_STATUS service_fault_batch(uvm_gpu_t *gpu, fault_service_mode_t service_mode, uvm_fault_service_batch_context_t *batch_context) @@ -1959,7 +2147,7 @@ static NV_STATUS service_fault_batch(uvm_gpu_t *gpu, gpu->parent->fault_buffer_info.replayable.replay_policy == UVM_PERF_FAULT_REPLAY_POLICY_BLOCK; uvm_service_block_context_t *service_context = &gpu->parent->fault_buffer_info.replayable.block_service_context; - uvm_va_block_context_t *va_block_context = &service_context->block_context; + uvm_va_block_context_t *va_block_context = service_context->block_context; UVM_ASSERT(gpu->parent->replayable_faults_supported); @@ -1995,41 +2183,28 @@ static NV_STATUS service_fault_batch(uvm_gpu_t *gpu, // to remain valid until we release. If no mm is registered, we // can only service managed faults, not ATS/HMM faults. mm = uvm_va_space_mm_retain_lock(va_space); - va_block_context->mm = mm; + uvm_va_block_context_init(va_block_context, mm); uvm_va_space_down_read(va_space); - gpu_va_space = uvm_gpu_va_space_get_by_parent_gpu(va_space, gpu->parent); - if (uvm_processor_mask_test_and_clear_atomic(&va_space->needs_fault_buffer_flush, gpu->id)) { - status = fault_buffer_flush_locked(gpu, - UVM_GPU_BUFFER_FLUSH_MODE_WAIT_UPDATE_PUT, - UVM_FAULT_REPLAY_TYPE_START, - batch_context); - if (status == NV_OK) - status = NV_WARN_MORE_PROCESSING_REQUIRED; - - break; - } - - // The case where there is no valid GPU VA space for the GPU in this - // VA space is handled next } // Some faults could be already fatal if they cannot be handled by // the UVM driver if (current_entry->is_fatal) { ++i; - batch_context->has_fatal_faults = true; + if (!batch_context->fatal_va_space) + batch_context->fatal_va_space = va_space; + utlb->has_fatal_faults = true; UVM_ASSERT(utlb->num_pending_faults > 0); continue; } - if (!uvm_processor_mask_test(&va_space->registered_gpu_va_spaces, gpu->parent->id)) { + if (!gpu_va_space) { // If there is no GPU VA space for the GPU, ignore the fault. This // can happen if a GPU VA space is destroyed without explicitly - // freeing all memory ranges (destroying the VA range triggers a - // flush of the fault buffer) and there are stale entries in the + // freeing all memory ranges and there are stale entries in the // buffer that got fixed by the servicing in a previous batch. ++i; continue; @@ -2057,7 +2232,7 @@ static NV_STATUS service_fault_batch(uvm_gpu_t *gpu, i += block_faults; // Don't issue replays in cancel mode - if (replay_per_va_block && !batch_context->has_fatal_faults) { + if (replay_per_va_block && !batch_context->fatal_va_space) { status = push_replay_on_gpu(gpu, UVM_FAULT_REPLAY_TYPE_START, batch_context); if (status != NV_OK) goto fail; @@ -2069,8 +2244,6 @@ static NV_STATUS service_fault_batch(uvm_gpu_t *gpu, } } - // Only clobber status if invalidate_status != NV_OK, since status may also - // contain NV_WARN_MORE_PROCESSING_REQUIRED. if (va_space != NULL) { NV_STATUS invalidate_status = uvm_ats_invalidate_tlbs(gpu_va_space, ats_invalidate, &batch_context->tracker); if (invalidate_status != NV_OK) @@ -2278,64 +2451,6 @@ static NvU32 is_fatal_fault_in_buffer(uvm_fault_service_batch_context_t *batch_c return false; } -// Cancel just the faults flagged as fatal in the given fault service batch -// context. -static NV_STATUS cancel_faults_precise_va(uvm_gpu_t *gpu, uvm_fault_service_batch_context_t *batch_context) -{ - NV_STATUS status = NV_OK; - NV_STATUS fault_status; - uvm_va_space_t *va_space = NULL; - NvU32 i; - - UVM_ASSERT(gpu->parent->fault_cancel_va_supported); - - for (i = 0; i < batch_context->num_coalesced_faults; ++i) { - uvm_fault_buffer_entry_t *current_entry = batch_context->ordered_fault_cache[i]; - - UVM_ASSERT(current_entry->va_space); - - if (current_entry->va_space != va_space) { - // Fault on a different va_space, drop the lock of the old one... - if (va_space != NULL) - uvm_va_space_up_read(va_space); - - va_space = current_entry->va_space; - - // ... and take the lock of the new one - uvm_va_space_down_read(va_space); - - // We don't need to check whether a buffer flush is required - // (due to VA range destruction). Once a fault is flagged as fatal - // we need to cancel it, even if its VA range no longer exists. - } - - // See the comment for the same check in cancel_faults_all - if (!uvm_processor_mask_test(&va_space->registered_gpu_va_spaces, gpu->parent->id)) - continue; - - if (current_entry->is_fatal) { - status = cancel_fault_precise_va(gpu, current_entry, current_entry->replayable.cancel_va_mode); - if (status != NV_OK) - break; - } - } - - if (va_space != NULL) - uvm_va_space_up_read(va_space); - - // See the comment on flushing in cancel_faults_all - fault_status = fault_buffer_flush_locked(gpu, - UVM_GPU_BUFFER_FLUSH_MODE_UPDATE_PUT, - UVM_FAULT_REPLAY_TYPE_START, - batch_context); - - // We report the first encountered error. - if (status == NV_OK) - status = fault_status; - - return status; -} - // Cancel all faults in the given fault service batch context, even those not // marked as fatal. static NV_STATUS cancel_faults_all(uvm_gpu_t *gpu, @@ -2344,56 +2459,51 @@ static NV_STATUS cancel_faults_all(uvm_gpu_t *gpu, { NV_STATUS status = NV_OK; NV_STATUS fault_status; - uvm_va_space_t *va_space = NULL; - NvU32 i; + NvU32 i = 0; UVM_ASSERT(gpu->parent->fault_cancel_va_supported); UVM_ASSERT(reason != UvmEventFatalReasonInvalid); - for (i = 0; i < batch_context->num_coalesced_faults; ++i) { + while (i < batch_context->num_coalesced_faults && status == NV_OK) { uvm_fault_buffer_entry_t *current_entry = batch_context->ordered_fault_cache[i]; - uvm_fault_cancel_va_mode_t cancel_va_mode; + uvm_va_space_t *va_space = current_entry->va_space; + bool skip_va_space; - UVM_ASSERT(current_entry->va_space); + UVM_ASSERT(va_space); - if (current_entry->va_space != va_space) { - // Fault on a different va_space, drop the lock of the old one... - if (va_space != NULL) - uvm_va_space_up_read(va_space); + uvm_va_space_down_read(va_space); - va_space = current_entry->va_space; + // If there is no GPU VA space for the GPU, ignore all faults in + // that VA space. This can happen if the GPU VA space has been + // destroyed since we unlocked the VA space in service_fault_batch. + // Ignoring the fault avoids targetting a PDB that might have been + // reused by another process. + skip_va_space = !uvm_gpu_va_space_get_by_parent_gpu(va_space, gpu->parent); - // ... and take the lock of the new one - uvm_va_space_down_read(va_space); - } + for (; + i < batch_context->num_coalesced_faults && current_entry->va_space == va_space; + current_entry = batch_context->ordered_fault_cache[++i]) { + uvm_fault_cancel_va_mode_t cancel_va_mode; - if (!uvm_processor_mask_test(&va_space->registered_gpu_va_spaces, gpu->parent->id)) { - // If there is no GPU VA space for the GPU, ignore the fault. - // This can happen if the GPU VA did not exist in - // service_fault_batch(), or it was destroyed since then. - // This is to avoid targetting a PDB that might have been reused - // by another process. - continue; - } + if (skip_va_space) + continue; - // If the fault was already marked fatal, use its reason and cancel - // mode. Otherwise use the provided reason. - if (current_entry->is_fatal) { - UVM_ASSERT(current_entry->fatal_reason != UvmEventFatalReasonInvalid); - cancel_va_mode = current_entry->replayable.cancel_va_mode; - } - else { - current_entry->fatal_reason = reason; - cancel_va_mode = UVM_FAULT_CANCEL_VA_MODE_ALL; - } + if (current_entry->is_fatal) { + UVM_ASSERT(current_entry->fatal_reason != UvmEventFatalReasonInvalid); + cancel_va_mode = current_entry->replayable.cancel_va_mode; + } + else { + current_entry->fatal_reason = reason; + cancel_va_mode = UVM_FAULT_CANCEL_VA_MODE_ALL; + } - status = cancel_fault_precise_va(gpu, current_entry, cancel_va_mode); - if (status != NV_OK) - break; - } + status = cancel_fault_precise_va(gpu, current_entry, cancel_va_mode); + if (status != NV_OK) + break; + } - if (va_space != NULL) uvm_va_space_up_read(va_space); + } // Because each cancel itself triggers a replay, there may be a large number // of new duplicated faults in the buffer after cancelling all the known @@ -2537,7 +2647,7 @@ static NV_STATUS cancel_faults_precise_tlb(uvm_gpu_t *gpu, uvm_fault_service_bat batch_context->num_invalid_prefetch_faults = 0; batch_context->num_replays = 0; - batch_context->has_fatal_faults = false; + batch_context->fatal_va_space = NULL; batch_context->has_throttled_faults = false; // 5) Fetch all faults from buffer @@ -2584,9 +2694,6 @@ static NV_STATUS cancel_faults_precise_tlb(uvm_gpu_t *gpu, uvm_fault_service_bat // 8) Service all non-fatal faults and mark all non-serviceable faults // as fatal status = service_fault_batch(gpu, FAULT_SERVICE_MODE_CANCEL, batch_context); - if (status == NV_WARN_MORE_PROCESSING_REQUIRED) - continue; - UVM_ASSERT(batch_context->num_replays == 0); if (status == NV_ERR_NO_MEMORY) continue; @@ -2594,7 +2701,7 @@ static NV_STATUS cancel_faults_precise_tlb(uvm_gpu_t *gpu, uvm_fault_service_bat break; // No more fatal faults left, we are done - if (!batch_context->has_fatal_faults) + if (!batch_context->fatal_va_space) break; // 9) Search for uTLBs that contain fatal faults and meet the @@ -2616,9 +2723,9 @@ static NV_STATUS cancel_faults_precise_tlb(uvm_gpu_t *gpu, uvm_fault_service_bat static NV_STATUS cancel_faults_precise(uvm_gpu_t *gpu, uvm_fault_service_batch_context_t *batch_context) { - UVM_ASSERT(batch_context->has_fatal_faults); + UVM_ASSERT(batch_context->fatal_va_space); if (gpu->parent->fault_cancel_va_supported) - return cancel_faults_precise_va(gpu, batch_context); + return service_fault_batch_for_cancel(gpu, batch_context); return cancel_faults_precise_tlb(gpu, batch_context); } @@ -2674,7 +2781,7 @@ void uvm_gpu_service_replayable_faults(uvm_gpu_t *gpu) batch_context->num_invalid_prefetch_faults = 0; batch_context->num_duplicate_faults = 0; batch_context->num_replays = 0; - batch_context->has_fatal_faults = false; + batch_context->fatal_va_space = NULL; batch_context->has_throttled_faults = false; status = fetch_fault_buffer_entries(gpu, batch_context, FAULT_FETCH_MODE_BATCH_READY); @@ -2702,9 +2809,6 @@ void uvm_gpu_service_replayable_faults(uvm_gpu_t *gpu) // was flushed num_replays += batch_context->num_replays; - if (status == NV_WARN_MORE_PROCESSING_REQUIRED) - continue; - enable_disable_prefetch_faults(gpu->parent, batch_context); if (status != NV_OK) { @@ -2718,10 +2822,17 @@ void uvm_gpu_service_replayable_faults(uvm_gpu_t *gpu) break; } - if (batch_context->has_fatal_faults) { + if (batch_context->fatal_va_space) { status = uvm_tracker_wait(&batch_context->tracker); - if (status == NV_OK) + if (status == NV_OK) { status = cancel_faults_precise(gpu, batch_context); + if (status == NV_OK) { + // Cancel handling should've issued at least one replay + UVM_ASSERT(batch_context->num_replays > 0); + ++num_batches; + continue; + } + } break; } diff --git a/kernel-open/nvidia-uvm/uvm_hal.c b/kernel-open/nvidia-uvm/uvm_hal.c index f1c781d901..eb59fb7e3d 100644 --- a/kernel-open/nvidia-uvm/uvm_hal.c +++ b/kernel-open/nvidia-uvm/uvm_hal.c @@ -794,7 +794,7 @@ uvm_membar_t uvm_hal_downgrade_membar_type(uvm_gpu_t *gpu, bool is_local_vidmem) // memory, including those from other processors like the CPU or peer GPUs, // must come through this GPU's L2. In all current architectures, MEMBAR_GPU // is sufficient to resolve ordering at the L2 level. - if (is_local_vidmem && !uvm_gpu_is_coherent(gpu->parent) && !uvm_downgrade_force_membar_sys) + if (is_local_vidmem && !uvm_parent_gpu_is_coherent(gpu->parent) && !uvm_downgrade_force_membar_sys) return UVM_MEMBAR_GPU; // If the mapped memory was remote, or if a coherence protocol can cache diff --git a/kernel-open/nvidia-uvm/uvm_hmm.c b/kernel-open/nvidia-uvm/uvm_hmm.c index 0d82314a46..5a3acf5409 100644 --- a/kernel-open/nvidia-uvm/uvm_hmm.c +++ b/kernel-open/nvidia-uvm/uvm_hmm.c @@ -60,6 +60,8 @@ module_param(uvm_disable_hmm, bool, 0444); #include "uvm_gpu.h" #include "uvm_pmm_gpu.h" #include "uvm_hal_types.h" +#include "uvm_push.h" +#include "uvm_hal.h" #include "uvm_va_block_types.h" #include "uvm_va_space_mm.h" #include "uvm_va_space.h" @@ -110,20 +112,7 @@ typedef struct bool uvm_hmm_is_enabled_system_wide(void) { - if (uvm_disable_hmm) - return false; - - if (g_uvm_global.ats.enabled) - return false; - - // Confidential Computing and HMM impose mutually exclusive constraints. In - // Confidential Computing the GPU can only access pages resident in vidmem, - // but in HMM pages may be required to be resident in sysmem: file backed - // VMAs, huge pages, etc. - if (g_uvm_global.conf_computing_enabled) - return false; - - return uvm_va_space_mm_enabled_system(); + return !uvm_disable_hmm && !g_uvm_global.ats.enabled && uvm_va_space_mm_enabled_system(); } bool uvm_hmm_is_enabled(uvm_va_space_t *va_space) @@ -140,6 +129,100 @@ static uvm_va_block_t *hmm_va_block_from_node(uvm_range_tree_node_t *node) return container_of(node, uvm_va_block_t, hmm.node); } +// Copies the contents of the source device-private page to the +// destination CPU page. This will invalidate mappings, so cannot be +// called while holding any va_block locks. +static NV_STATUS uvm_hmm_copy_devmem_page(struct page *dst_page, struct page *src_page, uvm_tracker_t *tracker) +{ + uvm_gpu_phys_address_t src_addr; + uvm_gpu_phys_address_t dst_addr; + uvm_gpu_chunk_t *gpu_chunk; + NvU64 dma_addr; + uvm_push_t push; + NV_STATUS status = NV_OK; + uvm_gpu_t *gpu; + + // Holding a reference on the device-private page ensures the gpu + // is already retained. This is because when a GPU is unregistered + // all device-private pages are migrated back to the CPU and freed + // before releasing the GPU. Therefore if we could get a reference + // to the page the GPU must be retained. + UVM_ASSERT(is_device_private_page(src_page) && page_count(src_page)); + gpu_chunk = uvm_pmm_devmem_page_to_chunk(src_page); + gpu = uvm_gpu_chunk_get_gpu(gpu_chunk); + status = uvm_mmu_chunk_map(gpu_chunk); + if (status != NV_OK) + return status; + + status = uvm_gpu_map_cpu_pages(gpu->parent, dst_page, PAGE_SIZE, &dma_addr); + if (status != NV_OK) + goto out_unmap_gpu; + + dst_addr = uvm_gpu_phys_address(UVM_APERTURE_SYS, dma_addr); + src_addr = uvm_gpu_phys_address(UVM_APERTURE_VID, gpu_chunk->address); + status = uvm_push_begin_acquire(gpu->channel_manager, + UVM_CHANNEL_TYPE_GPU_TO_CPU, + tracker, + &push, + "Copy for remote process fault"); + if (status != NV_OK) + goto out_unmap_cpu; + + gpu->parent->ce_hal->memcopy(&push, + uvm_gpu_address_copy(gpu, dst_addr), + uvm_gpu_address_copy(gpu, src_addr), + PAGE_SIZE); + uvm_push_end(&push); + status = uvm_tracker_add_push_safe(tracker, &push); + +out_unmap_cpu: + uvm_gpu_unmap_cpu_pages(gpu->parent, dma_addr, PAGE_SIZE); + +out_unmap_gpu: + uvm_mmu_chunk_unmap(gpu_chunk, NULL); + + return status; +} + +static NV_STATUS uvm_hmm_pmm_gpu_evict_pfn(unsigned long pfn) +{ + unsigned long src_pfn = 0; + unsigned long dst_pfn = 0; + struct page *dst_page; + NV_STATUS status = NV_OK; + int ret; + + ret = migrate_device_range(&src_pfn, pfn, 1); + if (ret) + return errno_to_nv_status(ret); + + if (src_pfn & MIGRATE_PFN_MIGRATE) { + uvm_tracker_t tracker = UVM_TRACKER_INIT(); + + dst_page = alloc_page(GFP_HIGHUSER_MOVABLE); + if (!dst_page) { + status = NV_ERR_NO_MEMORY; + goto out; + } + + lock_page(dst_page); + if (WARN_ON(uvm_hmm_copy_devmem_page(dst_page, migrate_pfn_to_page(src_pfn), &tracker) != NV_OK)) + memzero_page(dst_page, 0, PAGE_SIZE); + + dst_pfn = migrate_pfn(page_to_pfn(dst_page)); + migrate_device_pages(&src_pfn, &dst_pfn, 1); + uvm_tracker_wait_deinit(&tracker); + } + +out: + migrate_device_finalize(&src_pfn, &dst_pfn, 1); + + if (!(src_pfn & MIGRATE_PFN_MIGRATE)) + status = NV_ERR_BUSY_RETRY; + + return status; +} + void uvm_hmm_va_space_initialize(uvm_va_space_t *va_space) { uvm_hmm_va_space_t *hmm_va_space = &va_space->hmm; @@ -199,6 +282,9 @@ void uvm_hmm_unregister_gpu(uvm_va_space_t *va_space, uvm_gpu_t *gpu, struct mm_ { uvm_range_tree_node_t *node; uvm_va_block_t *va_block; + struct range range = gpu->pmm.devmem.pagemap.range; + unsigned long pfn; + bool retry; if (!uvm_hmm_is_enabled(va_space)) return; @@ -207,6 +293,29 @@ void uvm_hmm_unregister_gpu(uvm_va_space_t *va_space, uvm_gpu_t *gpu, struct mm_ uvm_assert_mmap_lock_locked(mm); uvm_assert_rwsem_locked_write(&va_space->lock); + // There could be pages with page->zone_device_data pointing to the va_space + // which may be about to be freed. Migrate those back to the CPU so we don't + // fault on them. Normally infinite retries are bad, but we don't have any + // option here. Device-private pages can't be pinned so migration should + // eventually succeed. Even if we did eventually bail out of the loop we'd + // just stall in memunmap_pages() anyway. + do { + retry = false; + + for (pfn = __phys_to_pfn(range.start); pfn <= __phys_to_pfn(range.end); pfn++) { + struct page *page = pfn_to_page(pfn); + + UVM_ASSERT(is_device_private_page(page)); + + // This check is racy because nothing stops the page being freed and + // even reused. That doesn't matter though - worst case the + // migration fails, we retry and find the va_space doesn't match. + if (page->zone_device_data == va_space) + if (uvm_hmm_pmm_gpu_evict_pfn(pfn) != NV_OK) + retry = true; + } + } while (retry); + uvm_range_tree_for_each(node, &va_space->hmm.blocks) { va_block = hmm_va_block_from_node(node); @@ -568,7 +677,7 @@ bool uvm_hmm_check_context_vma_is_valid(uvm_va_block_t *va_block, void uvm_hmm_service_context_init(uvm_service_block_context_t *service_context) { // TODO: Bug 4050579: Remove this when swap cached pages can be migrated. - service_context->block_context.hmm.swap_cached = false; + service_context->block_context->hmm.swap_cached = false; } NV_STATUS uvm_hmm_migrate_begin(uvm_va_block_t *va_block) @@ -631,47 +740,6 @@ static NV_STATUS hmm_migrate_range(uvm_va_block_t *va_block, return status; } -void uvm_hmm_evict_va_blocks(uvm_va_space_t *va_space) -{ - // We can't use uvm_va_space_mm_retain(), because the va_space_mm - // should already be dead by now. - struct mm_struct *mm = va_space->va_space_mm.mm; - uvm_hmm_va_space_t *hmm_va_space = &va_space->hmm; - uvm_range_tree_node_t *node, *next; - uvm_va_block_t *va_block; - uvm_va_block_context_t *block_context; - - uvm_down_read_mmap_lock(mm); - uvm_va_space_down_write(va_space); - - uvm_range_tree_for_each_safe(node, next, &hmm_va_space->blocks) { - uvm_va_block_region_t region; - struct vm_area_struct *vma; - - va_block = hmm_va_block_from_node(node); - block_context = uvm_va_space_block_context(va_space, mm); - uvm_hmm_migrate_begin_wait(va_block); - uvm_mutex_lock(&va_block->lock); - for_each_va_block_vma_region(va_block, mm, vma, ®ion) { - if (!uvm_hmm_vma_is_valid(vma, vma->vm_start, false)) - continue; - - block_context->hmm.vma = vma; - uvm_hmm_va_block_migrate_locked(va_block, - NULL, - block_context, - UVM_ID_CPU, - region, - UVM_MAKE_RESIDENT_CAUSE_API_MIGRATE); - } - uvm_mutex_unlock(&va_block->lock); - uvm_hmm_migrate_finish(va_block); - } - - uvm_va_space_up_write(va_space); - uvm_up_read_mmap_lock(mm); -} - NV_STATUS uvm_hmm_test_va_block_inject_split_error(uvm_va_space_t *va_space, NvU64 addr) { uvm_va_block_test_t *block_test; @@ -1476,40 +1544,59 @@ static NV_STATUS hmm_va_block_cpu_page_populate(uvm_va_block_t *va_block, return status; } - status = uvm_va_block_map_cpu_chunk_on_gpus(va_block, page_index); + status = uvm_va_block_map_cpu_chunk_on_gpus(va_block, chunk, page_index); if (status != NV_OK) { - uvm_cpu_chunk_remove_from_block(va_block, page_index); + uvm_cpu_chunk_remove_from_block(va_block, page_to_nid(page), page_index); uvm_cpu_chunk_free(chunk); } return status; } -static void hmm_va_block_cpu_page_unpopulate(uvm_va_block_t *va_block, - uvm_page_index_t page_index) +static void hmm_va_block_cpu_unpopulate_chunk(uvm_va_block_t *va_block, + uvm_cpu_chunk_t *chunk, + int chunk_nid, + uvm_page_index_t page_index) { - uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(va_block, page_index); - - UVM_ASSERT(uvm_va_block_is_hmm(va_block)); - if (!chunk) return; UVM_ASSERT(!uvm_processor_mask_test(&va_block->resident, UVM_ID_CPU) || - !uvm_page_mask_test(&va_block->cpu.resident, page_index)); + !uvm_va_block_cpu_is_page_resident_on(va_block, NUMA_NO_NODE, page_index)); + UVM_ASSERT(uvm_cpu_chunk_get_size(chunk) == PAGE_SIZE); - uvm_cpu_chunk_remove_from_block(va_block, page_index); + uvm_cpu_chunk_remove_from_block(va_block, chunk_nid, page_index); uvm_va_block_unmap_cpu_chunk_on_gpus(va_block, chunk, page_index); uvm_cpu_chunk_free(chunk); } +static void hmm_va_block_cpu_page_unpopulate(uvm_va_block_t *va_block, uvm_page_index_t page_index, struct page *page) +{ + uvm_cpu_chunk_t *chunk; + + UVM_ASSERT(uvm_va_block_is_hmm(va_block)); + + if (page) { + chunk = uvm_cpu_chunk_get_chunk_for_page(va_block, page_to_nid(page), page_index); + hmm_va_block_cpu_unpopulate_chunk(va_block, chunk, page_to_nid(page), page_index); + } + else { + int nid; + + for_each_possible_uvm_node(nid) { + chunk = uvm_cpu_chunk_get_chunk_for_page(va_block, nid, page_index); + hmm_va_block_cpu_unpopulate_chunk(va_block, chunk, nid, page_index); + } + } +} + static bool hmm_va_block_cpu_page_is_same(uvm_va_block_t *va_block, uvm_page_index_t page_index, struct page *page) { - struct page *old_page = uvm_cpu_chunk_get_cpu_page(va_block, page_index); + struct page *old_page = uvm_va_block_get_cpu_page(va_block, page_index); - UVM_ASSERT(uvm_cpu_chunk_is_hmm(uvm_cpu_chunk_get_chunk_for_page(va_block, page_index))); + UVM_ASSERT(uvm_cpu_chunk_is_hmm(uvm_cpu_chunk_get_chunk_for_page(va_block, page_to_nid(page), page_index))); return old_page == page; } @@ -1522,7 +1609,7 @@ static void clear_service_context_masks(uvm_service_block_context_t *service_con uvm_processor_id_t new_residency, uvm_page_index_t page_index) { - uvm_page_mask_clear(&service_context->block_context.caller_page_mask, page_index); + uvm_page_mask_clear(&service_context->block_context->caller_page_mask, page_index); uvm_page_mask_clear(&service_context->per_processor_masks[uvm_id_value(new_residency)].new_residency, page_index); @@ -1549,7 +1636,6 @@ static void cpu_mapping_set(uvm_va_block_t *va_block, uvm_page_index_t page_index) { uvm_processor_mask_set(&va_block->mapped, UVM_ID_CPU); - uvm_page_mask_set(&va_block->maybe_mapped_pages, page_index); uvm_page_mask_set(&va_block->cpu.pte_bits[UVM_PTE_BITS_CPU_READ], page_index); if (is_write) uvm_page_mask_set(&va_block->cpu.pte_bits[UVM_PTE_BITS_CPU_WRITE], page_index); @@ -1699,7 +1785,7 @@ static NV_STATUS sync_page_and_chunk_state(uvm_va_block_t *va_block, // migrate_vma_finalize() will release the reference so we should // clear our pointer to it. // TODO: Bug 3660922: Need to handle read duplication at some point. - hmm_va_block_cpu_page_unpopulate(va_block, page_index); + hmm_va_block_cpu_page_unpopulate(va_block, page_index, page); } } @@ -1725,7 +1811,7 @@ static void clean_up_non_migrating_page(uvm_va_block_t *va_block, else { UVM_ASSERT(page_ref_count(dst_page) == 1); - hmm_va_block_cpu_page_unpopulate(va_block, page_index); + hmm_va_block_cpu_page_unpopulate(va_block, page_index, dst_page); } unlock_page(dst_page); @@ -1760,7 +1846,7 @@ static void lock_block_cpu_page(uvm_va_block_t *va_block, unsigned long *dst_pfns, uvm_page_mask_t *same_devmem_page_mask) { - uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(va_block, page_index); + uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(va_block, page_to_nid(src_page), page_index); uvm_va_block_region_t chunk_region; struct page *dst_page; @@ -1786,7 +1872,7 @@ static void lock_block_cpu_page(uvm_va_block_t *va_block, // hmm_va_block_cpu_page_unpopulate() or block_kill(). If the page // does not migrate, it will be freed though. UVM_ASSERT(!uvm_processor_mask_test(&va_block->resident, UVM_ID_CPU) || - !uvm_page_mask_test(&va_block->cpu.resident, page_index)); + !uvm_va_block_cpu_is_page_resident_on(va_block, NUMA_NO_NODE, page_index)); UVM_ASSERT(chunk->type == UVM_CPU_CHUNK_TYPE_PHYSICAL); UVM_ASSERT(page_ref_count(dst_page) == 1); uvm_cpu_chunk_make_hmm(chunk); @@ -1934,7 +2020,7 @@ static NV_STATUS alloc_and_copy_to_cpu(uvm_va_block_t *va_block, } UVM_ASSERT(!uvm_processor_mask_test(&va_block->resident, UVM_ID_CPU) || - !uvm_page_mask_test(&va_block->cpu.resident, page_index)); + !uvm_va_block_cpu_is_page_resident_on(va_block, NUMA_NO_NODE, page_index)); // Allocate a user system memory page for the destination. // This is the typical case since Linux will free the source page when @@ -2012,8 +2098,8 @@ static NV_STATUS uvm_hmm_devmem_fault_alloc_and_copy(uvm_hmm_devmem_fault_contex service_context = devmem_fault_context->service_context; va_block_retry = devmem_fault_context->va_block_retry; va_block = devmem_fault_context->va_block; - src_pfns = service_context->block_context.hmm.src_pfns; - dst_pfns = service_context->block_context.hmm.dst_pfns; + src_pfns = service_context->block_context->hmm.src_pfns; + dst_pfns = service_context->block_context->hmm.dst_pfns; // Build the migration page mask. // Note that thrashing pinned pages and prefetch pages are already @@ -2022,7 +2108,7 @@ static NV_STATUS uvm_hmm_devmem_fault_alloc_and_copy(uvm_hmm_devmem_fault_contex uvm_page_mask_copy(page_mask, &service_context->per_processor_masks[UVM_ID_CPU_VALUE].new_residency); status = alloc_and_copy_to_cpu(va_block, - service_context->block_context.hmm.vma, + service_context->block_context->hmm.vma, src_pfns, dst_pfns, service_context->region, @@ -2057,8 +2143,8 @@ static NV_STATUS uvm_hmm_devmem_fault_finalize_and_map(uvm_hmm_devmem_fault_cont prefetch_hint = &service_context->prefetch_hint; va_block = devmem_fault_context->va_block; va_block_retry = devmem_fault_context->va_block_retry; - src_pfns = service_context->block_context.hmm.src_pfns; - dst_pfns = service_context->block_context.hmm.dst_pfns; + src_pfns = service_context->block_context->hmm.src_pfns; + dst_pfns = service_context->block_context->hmm.dst_pfns; region = service_context->region; page_mask = &devmem_fault_context->page_mask; @@ -2165,8 +2251,7 @@ static NV_STATUS populate_region(uvm_va_block_t *va_block, // Since we have a stable snapshot of the CPU pages, we can // update the residency and protection information. - uvm_processor_mask_set(&va_block->resident, UVM_ID_CPU); - uvm_page_mask_set(&va_block->cpu.resident, page_index); + uvm_va_block_cpu_set_resident_page(va_block, page_to_nid(page), page_index); cpu_mapping_set(va_block, pfns[page_index] & HMM_PFN_WRITE, page_index); } @@ -2253,7 +2338,7 @@ static void hmm_release_atomic_pages(uvm_va_block_t *va_block, uvm_page_index_t page_index; for_each_va_block_page_in_region(page_index, region) { - struct page *page = service_context->block_context.hmm.pages[page_index]; + struct page *page = service_context->block_context->hmm.pages[page_index]; if (!page) continue; @@ -2269,14 +2354,14 @@ static NV_STATUS hmm_block_atomic_fault_locked(uvm_processor_id_t processor_id, uvm_service_block_context_t *service_context) { uvm_va_block_region_t region = service_context->region; - struct page **pages = service_context->block_context.hmm.pages; + struct page **pages = service_context->block_context->hmm.pages; int npages; uvm_page_index_t page_index; uvm_make_resident_cause_t cause; NV_STATUS status; if (!uvm_processor_mask_test(&va_block->resident, UVM_ID_CPU) || - !uvm_page_mask_region_full(&va_block->cpu.resident, region)) { + !uvm_va_block_cpu_is_region_resident_on(va_block, NUMA_NO_NODE, region)) { // There is an atomic GPU fault. We need to make sure no pages are // GPU resident so that make_device_exclusive_range() doesn't call // migrate_to_ram() and cause a va_space lock recursion problem. @@ -2289,7 +2374,7 @@ static NV_STATUS hmm_block_atomic_fault_locked(uvm_processor_id_t processor_id, status = uvm_hmm_va_block_migrate_locked(va_block, va_block_retry, - &service_context->block_context, + service_context->block_context, UVM_ID_CPU, region, cause); @@ -2299,7 +2384,7 @@ static NV_STATUS hmm_block_atomic_fault_locked(uvm_processor_id_t processor_id, // make_device_exclusive_range() will try to call migrate_to_ram() // and deadlock with ourself if the data isn't CPU resident. if (!uvm_processor_mask_test(&va_block->resident, UVM_ID_CPU) || - !uvm_page_mask_region_full(&va_block->cpu.resident, region)) { + !uvm_va_block_cpu_is_region_resident_on(va_block, NUMA_NO_NODE, region)) { status = NV_WARN_MORE_PROCESSING_REQUIRED; goto done; } @@ -2309,7 +2394,7 @@ static NV_STATUS hmm_block_atomic_fault_locked(uvm_processor_id_t processor_id, // mmap() files so we check for that here and report a fatal fault. // Otherwise with the current Linux 6.1 make_device_exclusive_range(), // it doesn't make the page exclusive and we end up in an endless loop. - if (service_context->block_context.hmm.vma->vm_flags & VM_SHARED) { + if (service_context->block_context->hmm.vma->vm_flags & (VM_SHARED | VM_HUGETLB)) { status = NV_ERR_NOT_SUPPORTED; goto done; } @@ -2318,7 +2403,7 @@ static NV_STATUS hmm_block_atomic_fault_locked(uvm_processor_id_t processor_id, uvm_mutex_unlock(&va_block->lock); - npages = make_device_exclusive_range(service_context->block_context.mm, + npages = make_device_exclusive_range(service_context->block_context->mm, uvm_va_block_cpu_page_address(va_block, region.first), uvm_va_block_cpu_page_address(va_block, region.outer - 1) + PAGE_SIZE, pages + region.first, @@ -2356,15 +2441,13 @@ static NV_STATUS hmm_block_atomic_fault_locked(uvm_processor_id_t processor_id, if (uvm_page_mask_test(&va_block->cpu.allocated, page_index)) { UVM_ASSERT(hmm_va_block_cpu_page_is_same(va_block, page_index, page)); UVM_ASSERT(uvm_processor_mask_test(&va_block->resident, UVM_ID_CPU)); - UVM_ASSERT(uvm_page_mask_test(&va_block->cpu.resident, page_index)); + UVM_ASSERT(uvm_va_block_cpu_is_page_resident_on(va_block, NUMA_NO_NODE, page_index)); } else { NV_STATUS s = hmm_va_block_cpu_page_populate(va_block, page_index, page); - if (s == NV_OK) { - uvm_processor_mask_set(&va_block->resident, UVM_ID_CPU); - uvm_page_mask_set(&va_block->cpu.resident, page_index); - } + if (s == NV_OK) + uvm_va_block_cpu_set_resident_page(va_block, page_to_nid(page), page_index); } cpu_mapping_clear(va_block, page_index); @@ -2419,7 +2502,7 @@ static NV_STATUS hmm_block_cpu_fault_locked(uvm_processor_id_t processor_id, uvm_service_block_context_t *service_context) { uvm_va_block_region_t region = service_context->region; - struct migrate_vma *args = &service_context->block_context.hmm.migrate_vma_args; + struct migrate_vma *args = &service_context->block_context->hmm.migrate_vma_args; NV_STATUS status; int ret; uvm_hmm_devmem_fault_context_t fault_context = { @@ -2453,8 +2536,8 @@ static NV_STATUS hmm_block_cpu_fault_locked(uvm_processor_id_t processor_id, } status = hmm_make_resident_cpu(va_block, - service_context->block_context.hmm.vma, - service_context->block_context.hmm.src_pfns, + service_context->block_context->hmm.vma, + service_context->block_context->hmm.src_pfns, region, service_context->access_type, &fault_context.same_devmem_page_mask); @@ -2476,9 +2559,9 @@ static NV_STATUS hmm_block_cpu_fault_locked(uvm_processor_id_t processor_id, } } - args->vma = service_context->block_context.hmm.vma; - args->src = service_context->block_context.hmm.src_pfns + region.first; - args->dst = service_context->block_context.hmm.dst_pfns + region.first; + args->vma = service_context->block_context->hmm.vma; + args->src = service_context->block_context->hmm.src_pfns + region.first; + args->dst = service_context->block_context->hmm.dst_pfns + region.first; args->start = uvm_va_block_region_start(va_block, region); args->end = uvm_va_block_region_end(va_block, region) + 1; args->flags = MIGRATE_VMA_SELECT_DEVICE_PRIVATE; @@ -2558,7 +2641,7 @@ static NV_STATUS dmamap_src_sysmem_pages(uvm_va_block_t *va_block, // TODO: Bug 4050579: Remove this when swap cached pages can be // migrated. if (service_context) { - service_context->block_context.hmm.swap_cached = true; + service_context->block_context->hmm.swap_cached = true; break; } @@ -2574,7 +2657,7 @@ static NV_STATUS dmamap_src_sysmem_pages(uvm_va_block_t *va_block, if (uvm_page_mask_test(&va_block->cpu.allocated, page_index)) { UVM_ASSERT(hmm_va_block_cpu_page_is_same(va_block, page_index, src_page)); UVM_ASSERT(uvm_processor_mask_test(&va_block->resident, UVM_ID_CPU)); - UVM_ASSERT(uvm_page_mask_test(&va_block->cpu.resident, page_index)); + UVM_ASSERT(uvm_va_block_cpu_is_page_resident_on(va_block, NUMA_NO_NODE, page_index)); } else { status = hmm_va_block_cpu_page_populate(va_block, page_index, src_page); @@ -2588,8 +2671,7 @@ static NV_STATUS dmamap_src_sysmem_pages(uvm_va_block_t *va_block, // migrate_vma_setup() was able to isolate and lock the page; // therefore, it is CPU resident and not mapped. - uvm_processor_mask_set(&va_block->resident, UVM_ID_CPU); - uvm_page_mask_set(&va_block->cpu.resident, page_index); + uvm_va_block_cpu_set_resident_page(va_block, page_to_nid(src_page), page_index); } // The call to migrate_vma_setup() will have inserted a migration @@ -2604,7 +2686,7 @@ static NV_STATUS dmamap_src_sysmem_pages(uvm_va_block_t *va_block, if (uvm_page_mask_test(&va_block->cpu.allocated, page_index)) { UVM_ASSERT(!uvm_va_block_page_resident_processors_count(va_block, page_index)); - hmm_va_block_cpu_page_unpopulate(va_block, page_index); + hmm_va_block_cpu_page_unpopulate(va_block, page_index, NULL); } } @@ -2618,7 +2700,7 @@ static NV_STATUS dmamap_src_sysmem_pages(uvm_va_block_t *va_block, } if (uvm_page_mask_empty(page_mask) || - (service_context && service_context->block_context.hmm.swap_cached)) + (service_context && service_context->block_context->hmm.swap_cached)) status = NV_WARN_MORE_PROCESSING_REQUIRED; if (status != NV_OK) @@ -2649,8 +2731,8 @@ static NV_STATUS uvm_hmm_gpu_fault_alloc_and_copy(struct vm_area_struct *vma, service_context = uvm_hmm_gpu_fault_event->service_context; region = service_context->region; prefetch_hint = &service_context->prefetch_hint; - src_pfns = service_context->block_context.hmm.src_pfns; - dst_pfns = service_context->block_context.hmm.dst_pfns; + src_pfns = service_context->block_context->hmm.src_pfns; + dst_pfns = service_context->block_context->hmm.dst_pfns; // Build the migration mask. // Note that thrashing pinned pages are already accounted for in @@ -2708,8 +2790,8 @@ static NV_STATUS uvm_hmm_gpu_fault_finalize_and_map(uvm_hmm_gpu_fault_event_t *u va_block = uvm_hmm_gpu_fault_event->va_block; va_block_retry = uvm_hmm_gpu_fault_event->va_block_retry; service_context = uvm_hmm_gpu_fault_event->service_context; - src_pfns = service_context->block_context.hmm.src_pfns; - dst_pfns = service_context->block_context.hmm.dst_pfns; + src_pfns = service_context->block_context->hmm.src_pfns; + dst_pfns = service_context->block_context->hmm.dst_pfns; region = service_context->region; page_mask = &uvm_hmm_gpu_fault_event->page_mask; @@ -2752,11 +2834,11 @@ NV_STATUS uvm_hmm_va_block_service_locked(uvm_processor_id_t processor_id, uvm_va_block_retry_t *va_block_retry, uvm_service_block_context_t *service_context) { - struct mm_struct *mm = service_context->block_context.mm; - struct vm_area_struct *vma = service_context->block_context.hmm.vma; + struct mm_struct *mm = service_context->block_context->mm; + struct vm_area_struct *vma = service_context->block_context->hmm.vma; uvm_va_block_region_t region = service_context->region; uvm_hmm_gpu_fault_event_t uvm_hmm_gpu_fault_event; - struct migrate_vma *args = &service_context->block_context.hmm.migrate_vma_args; + struct migrate_vma *args = &service_context->block_context->hmm.migrate_vma_args; int ret; NV_STATUS status = NV_ERR_INVALID_ADDRESS; @@ -2780,8 +2862,8 @@ NV_STATUS uvm_hmm_va_block_service_locked(uvm_processor_id_t processor_id, uvm_hmm_gpu_fault_event.service_context = service_context; args->vma = vma; - args->src = service_context->block_context.hmm.src_pfns + region.first; - args->dst = service_context->block_context.hmm.dst_pfns + region.first; + args->src = service_context->block_context->hmm.src_pfns + region.first; + args->dst = service_context->block_context->hmm.dst_pfns + region.first; args->start = uvm_va_block_region_start(va_block, region); args->end = uvm_va_block_region_end(va_block, region) + 1; args->flags = MIGRATE_VMA_SELECT_DEVICE_PRIVATE | MIGRATE_VMA_SELECT_SYSTEM; @@ -2815,8 +2897,8 @@ NV_STATUS uvm_hmm_va_block_service_locked(uvm_processor_id_t processor_id, // since migrate_vma_setup() would have reported that information. // Try to make it resident in system memory and retry the migration. status = hmm_make_resident_cpu(va_block, - service_context->block_context.hmm.vma, - service_context->block_context.hmm.src_pfns, + service_context->block_context->hmm.vma, + service_context->block_context->hmm.src_pfns, region, service_context->access_type, NULL); @@ -2962,16 +3044,6 @@ static NV_STATUS uvm_hmm_migrate_finalize(uvm_hmm_migrate_event_t *uvm_hmm_migra &uvm_hmm_migrate_event->same_devmem_page_mask); } -static bool is_resident(uvm_va_block_t *va_block, - uvm_processor_id_t dest_id, - uvm_va_block_region_t region) -{ - if (!uvm_processor_mask_test(&va_block->resident, dest_id)) - return false; - - return uvm_page_mask_region_full(uvm_va_block_resident_mask_get(va_block, dest_id), region); -} - // Note that migrate_vma_*() doesn't handle asynchronous migrations so the // migration flag UVM_MIGRATE_FLAG_SKIP_CPU_MAP doesn't have an effect. // TODO: Bug 3900785: investigate ways to implement async migration. @@ -3063,9 +3135,7 @@ NV_STATUS uvm_hmm_va_block_migrate_locked(uvm_va_block_t *va_block, uvm_page_mask_init_from_region(page_mask, region, NULL); for_each_id_in_mask(id, &va_block->resident) { - if (!uvm_page_mask_andnot(page_mask, - page_mask, - uvm_va_block_resident_mask_get(va_block, id))) + if (!uvm_page_mask_andnot(page_mask, page_mask, uvm_va_block_resident_mask_get(va_block, id, NUMA_NO_NODE))) return NV_OK; } @@ -3193,6 +3263,7 @@ static NV_STATUS hmm_va_block_evict_chunks(uvm_va_block_t *va_block, uvm_page_mask_t *page_mask = &uvm_hmm_migrate_event.page_mask; const uvm_va_policy_t *policy; uvm_va_policy_node_t *node; + uvm_page_mask_t *cpu_resident_mask = uvm_va_block_resident_mask_get(va_block, UVM_ID_CPU, NUMA_NO_NODE); unsigned long npages; NV_STATUS status; @@ -3215,7 +3286,7 @@ static NV_STATUS hmm_va_block_evict_chunks(uvm_va_block_t *va_block, // Pages resident on the GPU should not have a resident page in system // memory. // TODO: Bug 3660922: Need to handle read duplication at some point. - UVM_ASSERT(uvm_page_mask_region_empty(&va_block->cpu.resident, region)); + UVM_ASSERT(uvm_page_mask_region_empty(cpu_resident_mask, region)); status = alloc_and_copy_to_cpu(va_block, NULL, @@ -3314,35 +3385,34 @@ NV_STATUS uvm_hmm_va_block_evict_pages_from_gpu(uvm_va_block_t *va_block, NULL); } -NV_STATUS uvm_hmm_pmm_gpu_evict_pfn(unsigned long pfn) +NV_STATUS uvm_hmm_remote_cpu_fault(struct vm_fault *vmf) { - unsigned long src_pfn = 0; - unsigned long dst_pfn = 0; - struct page *dst_page; NV_STATUS status = NV_OK; + unsigned long src_pfn; + unsigned long dst_pfn; + struct migrate_vma args; + struct page *src_page = vmf->page; + uvm_tracker_t tracker = UVM_TRACKER_INIT(); int ret; - ret = migrate_device_range(&src_pfn, pfn, 1); - if (ret) - return errno_to_nv_status(ret); + args.vma = vmf->vma; + args.src = &src_pfn; + args.dst = &dst_pfn; + args.start = nv_page_fault_va(vmf); + args.end = args.start + PAGE_SIZE; + args.pgmap_owner = &g_uvm_global; + args.flags = MIGRATE_VMA_SELECT_DEVICE_PRIVATE; + args.fault_page = src_page; + + // We don't call migrate_vma_setup_locked() here because we don't + // have a va_block and don't want to ignore invalidations. + ret = migrate_vma_setup(&args); + UVM_ASSERT(!ret); if (src_pfn & MIGRATE_PFN_MIGRATE) { - // All the code for copying a vidmem page to sysmem relies on - // having a va_block. However certain combinations of mremap() - // and fork() can result in device-private pages being mapped - // in a child process without a va_block. - // - // We don't expect the above to be a common occurance so for - // now we allocate a fresh zero page when evicting without a - // va_block. However this results in child processes losing - // data so make sure we warn about it. Ideally we would just - // not migrate and SIGBUS the child if it tries to access the - // page. However that would prevent unloading of the driver so - // we're stuck with this until we fix the problem. - // TODO: Bug 3902536: add code to migrate GPU memory without having a - // va_block. - WARN_ON(1); - dst_page = alloc_page(GFP_HIGHUSER_MOVABLE | __GFP_ZERO); + struct page *dst_page; + + dst_page = alloc_page(GFP_HIGHUSER_MOVABLE); if (!dst_page) { status = NV_ERR_NO_MEMORY; goto out; @@ -3351,11 +3421,15 @@ NV_STATUS uvm_hmm_pmm_gpu_evict_pfn(unsigned long pfn) lock_page(dst_page); dst_pfn = migrate_pfn(page_to_pfn(dst_page)); - migrate_device_pages(&src_pfn, &dst_pfn, 1); + status = uvm_hmm_copy_devmem_page(dst_page, src_page, &tracker); + if (status == NV_OK) + status = uvm_tracker_wait_deinit(&tracker); } + migrate_vma_pages(&args); + out: - migrate_device_finalize(&src_pfn, &dst_pfn, 1); + migrate_vma_finalize(&args); return status; } @@ -3606,4 +3680,3 @@ bool uvm_hmm_must_use_sysmem(uvm_va_block_t *va_block, } #endif // UVM_IS_CONFIG_HMM() - diff --git a/kernel-open/nvidia-uvm/uvm_hmm.h b/kernel-open/nvidia-uvm/uvm_hmm.h index 190ef94ece..9983c5dc98 100644 --- a/kernel-open/nvidia-uvm/uvm_hmm.h +++ b/kernel-open/nvidia-uvm/uvm_hmm.h @@ -307,10 +307,10 @@ typedef struct uvm_migrate_mode_t mode, uvm_tracker_t *out_tracker); - // Evicts all va_blocks in the va_space to the CPU. Unlike the - // other va_block eviction functions this is based on virtual - // address and therefore takes mmap_lock for read. - void uvm_hmm_evict_va_blocks(uvm_va_space_t *va_space); + // Handle a fault to a device-private page from a process other than the + // process which created the va_space that originally allocated the + // device-private page. + NV_STATUS uvm_hmm_remote_cpu_fault(struct vm_fault *vmf); // This sets the va_block_context->hmm.src_pfns[] to the ZONE_DEVICE private // PFN for the GPU chunk memory. @@ -343,14 +343,6 @@ typedef struct const uvm_page_mask_t *pages_to_evict, uvm_va_block_region_t region); - // Migrate a GPU device-private page to system memory. This is - // called to remove CPU page table references to device private - // struct pages for the given GPU after all other references in - // va_blocks have been released and the GPU is in the process of - // being removed/torn down. Note that there is no mm, VMA, - // va_block or any user channel activity on this GPU. - NV_STATUS uvm_hmm_pmm_gpu_evict_pfn(unsigned long pfn); - // This returns what would be the intersection of va_block start/end and // VMA start/end-1 for the given 'lookup_address' if // uvm_hmm_va_block_find_create() was called. @@ -592,8 +584,10 @@ typedef struct return NV_ERR_INVALID_ADDRESS; } - static void uvm_hmm_evict_va_blocks(uvm_va_space_t *va_space) + static NV_STATUS uvm_hmm_remote_cpu_fault(struct vm_fault *vmf) { + UVM_ASSERT(0); + return NV_ERR_INVALID_ADDRESS; } static NV_STATUS uvm_hmm_va_block_evict_chunk_prep(uvm_va_block_t *va_block, @@ -622,11 +616,6 @@ typedef struct return NV_OK; } - static NV_STATUS uvm_hmm_pmm_gpu_evict_pfn(unsigned long pfn) - { - return NV_OK; - } - static NV_STATUS uvm_hmm_va_block_range_bounds(uvm_va_space_t *va_space, struct mm_struct *mm, NvU64 lookup_address, diff --git a/kernel-open/nvidia-uvm/uvm_hopper.c b/kernel-open/nvidia-uvm/uvm_hopper.c index 2ae803d2cc..c2457d9af8 100644 --- a/kernel-open/nvidia-uvm/uvm_hopper.c +++ b/kernel-open/nvidia-uvm/uvm_hopper.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2020-2022 NVIDIA Corporation + Copyright (c) 2020-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -59,12 +59,12 @@ void uvm_hal_hopper_arch_init_properties(uvm_parent_gpu_t *parent_gpu) // Physical CE writes to vidmem are non-coherent with respect to the CPU on // GH180. - parent_gpu->ce_phys_vidmem_write_supported = !uvm_gpu_is_coherent(parent_gpu); + parent_gpu->ce_phys_vidmem_write_supported = !uvm_parent_gpu_is_coherent(parent_gpu); // TODO: Bug 4174553: [HGX-SkinnyJoe][GH180] channel errors discussion/debug // portion for the uvm tests became nonresponsive after // some time and then failed even after reboot - parent_gpu->peer_copy_mode = uvm_gpu_is_coherent(parent_gpu) ? + parent_gpu->peer_copy_mode = uvm_parent_gpu_is_coherent(parent_gpu) ? UVM_GPU_PEER_COPY_MODE_VIRTUAL : g_uvm_global.peer_copy_mode; // All GR context buffers may be mapped to 57b wide VAs. All "compute" units diff --git a/kernel-open/nvidia-uvm/uvm_hopper_mmu.c b/kernel-open/nvidia-uvm/uvm_hopper_mmu.c index 8f7b3da50f..092a7e2ba5 100644 --- a/kernel-open/nvidia-uvm/uvm_hopper_mmu.c +++ b/kernel-open/nvidia-uvm/uvm_hopper_mmu.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2020-2023 NVIDIA Corporation + Copyright (c) 2020-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -368,10 +368,7 @@ static NvU64 small_half_pde_hopper(uvm_mmu_page_table_alloc_t *phys_alloc) return pde_bits; } -static void make_pde_hopper(void *entry, - uvm_mmu_page_table_alloc_t **phys_allocs, - NvU32 depth, - uvm_page_directory_t *child_dir) +static void make_pde_hopper(void *entry, uvm_mmu_page_table_alloc_t **phys_allocs, NvU32 depth) { NvU32 entry_count = entries_per_index_hopper(depth); NvU64 *entry_bits = (NvU64 *)entry; diff --git a/kernel-open/nvidia-uvm/uvm_linux.h b/kernel-open/nvidia-uvm/uvm_linux.h index 96e20195d3..c7c7ccad6d 100644 --- a/kernel-open/nvidia-uvm/uvm_linux.h +++ b/kernel-open/nvidia-uvm/uvm_linux.h @@ -128,8 +128,9 @@ static inline const struct cpumask *uvm_cpumask_of_node(int node) // present if we see the callback. // // The callback was added in commit 0f0a327fa12cd55de5e7f8c05a70ac3d047f405e, -// v3.19 (2014-11-13). - #if defined(NV_MMU_NOTIFIER_OPS_HAS_INVALIDATE_RANGE) +// v3.19 (2014-11-13) and renamed in commit 1af5a8109904. + #if defined(NV_MMU_NOTIFIER_OPS_HAS_INVALIDATE_RANGE) || \ + defined(NV_MMU_NOTIFIER_OPS_HAS_ARCH_INVALIDATE_SECONDARY_TLBS) #define UVM_CAN_USE_MMU_NOTIFIERS() 1 #else #define UVM_CAN_USE_MMU_NOTIFIERS() 0 @@ -348,6 +349,47 @@ static inline NvU64 NV_GETTIME(void) (bit) = find_next_zero_bit((addr), (size), (bit) + 1)) #endif +#if !defined(NV_FIND_NEXT_BIT_WRAP_PRESENT) + static inline unsigned long find_next_bit_wrap(const unsigned long *addr, unsigned long size, unsigned long offset) + { + unsigned long bit = find_next_bit(addr, size, offset); + + if (bit < size) + return bit; + + bit = find_first_bit(addr, offset); + return bit < offset ? bit : size; + } +#endif + +// for_each_set_bit_wrap and __for_each_wrap were introduced in v6.1-rc1 +// by commit 4fe49b3b97c2640147c46519c2a6fdb06df34f5f +#if !defined(for_each_set_bit_wrap) +static inline unsigned long __for_each_wrap(const unsigned long *bitmap, + unsigned long size, + unsigned long start, + unsigned long n) +{ + unsigned long bit; + + if (n > start) { + bit = find_next_bit(bitmap, size, n); + if (bit < size) + return bit; + + n = 0; + } + + bit = find_next_bit(bitmap, start, n); + return bit < start ? bit : size; +} + +#define for_each_set_bit_wrap(bit, addr, size, start) \ + for ((bit) = find_next_bit_wrap((addr), (size), (start)); \ + (bit) < (size); \ + (bit) = __for_each_wrap((addr), (size), (start), (bit) + 1)) +#endif + // Added in 2.6.24 #ifndef ACCESS_ONCE #define ACCESS_ONCE(x) (*(volatile typeof(x) *)&(x)) @@ -579,4 +621,5 @@ static inline pgprot_t uvm_pgprot_decrypted(pgprot_t prot) #include #define page_to_virt(x) __va(PFN_PHYS(page_to_pfn(x))) #endif + #endif // _UVM_LINUX_H diff --git a/kernel-open/nvidia-uvm/uvm_map_external.c b/kernel-open/nvidia-uvm/uvm_map_external.c index 8399295172..a360328648 100644 --- a/kernel-open/nvidia-uvm/uvm_map_external.c +++ b/kernel-open/nvidia-uvm/uvm_map_external.c @@ -355,6 +355,7 @@ static uvm_membar_t va_range_downgrade_membar(uvm_va_range_t *va_range, uvm_ext_ if (!ext_gpu_map->mem_handle) return UVM_MEMBAR_GPU; + // EGM uses the same barriers as sysmem. return uvm_hal_downgrade_membar_type(ext_gpu_map->gpu, !ext_gpu_map->is_sysmem && ext_gpu_map->gpu == ext_gpu_map->owning_gpu); } @@ -633,6 +634,8 @@ static NV_STATUS set_ext_gpu_map_location(uvm_ext_gpu_map_t *ext_gpu_map, const UvmGpuMemoryInfo *mem_info) { uvm_gpu_t *owning_gpu; + if (mem_info->egm) + UVM_ASSERT(mem_info->sysmem); if (!mem_info->deviceDescendant && !mem_info->sysmem) { ext_gpu_map->owning_gpu = NULL; @@ -641,6 +644,7 @@ static NV_STATUS set_ext_gpu_map_location(uvm_ext_gpu_map_t *ext_gpu_map, } // This is a local or peer allocation, so the owning GPU must have been // registered. + // This also checks for if EGM owning GPU is registered. owning_gpu = uvm_va_space_get_gpu_by_uuid(va_space, &mem_info->uuid); if (!owning_gpu) return NV_ERR_INVALID_DEVICE; @@ -651,13 +655,10 @@ static NV_STATUS set_ext_gpu_map_location(uvm_ext_gpu_map_t *ext_gpu_map, // crashes when it's eventually freed. // TODO: Bug 1811006: Bug tracking the RM issue, its fix might change the // semantics of sysmem allocations. - if (mem_info->sysmem) { - ext_gpu_map->owning_gpu = owning_gpu; - ext_gpu_map->is_sysmem = true; - return NV_OK; - } - if (owning_gpu != mapping_gpu) { + // Check if peer access for peer memory is enabled. + // This path also handles EGM allocations. + if (owning_gpu != mapping_gpu && (!mem_info->sysmem || mem_info->egm)) { // TODO: Bug 1757136: In SLI, the returned UUID may be different but a // local mapping must be used. We need to query SLI groups to know // that. @@ -666,7 +667,9 @@ static NV_STATUS set_ext_gpu_map_location(uvm_ext_gpu_map_t *ext_gpu_map, } ext_gpu_map->owning_gpu = owning_gpu; - ext_gpu_map->is_sysmem = false; + ext_gpu_map->is_sysmem = mem_info->sysmem; + ext_gpu_map->is_egm = mem_info->egm; + return NV_OK; } @@ -719,6 +722,7 @@ static NV_STATUS uvm_ext_gpu_map_split(uvm_range_tree_t *tree, new->gpu = existing_map->gpu; new->owning_gpu = existing_map->owning_gpu; new->is_sysmem = existing_map->is_sysmem; + new->is_egm = existing_map->is_egm; // Initialize the new ext_gpu_map tracker as a copy of the existing_map tracker. // This way, any operations on any of the two ext_gpu_maps will be able to diff --git a/kernel-open/nvidia-uvm/uvm_maxwell_mmu.c b/kernel-open/nvidia-uvm/uvm_maxwell_mmu.c index 51e1d3130c..4f3e055529 100644 --- a/kernel-open/nvidia-uvm/uvm_maxwell_mmu.c +++ b/kernel-open/nvidia-uvm/uvm_maxwell_mmu.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2023 NVIDIA Corporation + Copyright (c) 2016-2021 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -106,10 +106,7 @@ static NvU64 small_half_pde_maxwell(uvm_mmu_page_table_alloc_t *phys_alloc) return pde_bits; } -static void make_pde_maxwell(void *entry, - uvm_mmu_page_table_alloc_t **phys_allocs, - NvU32 depth, - uvm_page_directory_t *child_dir) +static void make_pde_maxwell(void *entry, uvm_mmu_page_table_alloc_t **phys_allocs, NvU32 depth) { NvU64 pde_bits = 0; UVM_ASSERT(depth == 0); diff --git a/kernel-open/nvidia-uvm/uvm_mem.c b/kernel-open/nvidia-uvm/uvm_mem.c index 4d3cca6e7b..5ba285c4b6 100644 --- a/kernel-open/nvidia-uvm/uvm_mem.c +++ b/kernel-open/nvidia-uvm/uvm_mem.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2023 NVIDIA Corporation + Copyright (c) 2016-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -93,9 +93,8 @@ static bool sysmem_can_be_mapped_on_gpu(uvm_mem_t *sysmem) { UVM_ASSERT(uvm_mem_is_sysmem(sysmem)); - // In Confidential Computing, only unprotected memory can be mapped on the - // GPU - if (g_uvm_global.conf_computing_enabled) + // If SEV is enabled, only unprotected memory can be mapped + if (g_uvm_global.sev_enabled) return uvm_mem_is_sysmem_dma(sysmem); return true; @@ -738,7 +737,7 @@ static NV_STATUS mem_map_cpu_to_sysmem_kernel(uvm_mem_t *mem) pages[page_index] = mem_cpu_page(mem, page_index * PAGE_SIZE); } - if (g_uvm_global.conf_computing_enabled && uvm_mem_is_sysmem_dma(mem)) + if (g_uvm_global.sev_enabled && uvm_mem_is_sysmem_dma(mem)) prot = uvm_pgprot_decrypted(PAGE_KERNEL_NOENC); mem->kernel.cpu_addr = vmap(pages, num_pages, VM_MAP, prot); diff --git a/kernel-open/nvidia-uvm/uvm_mem_test.c b/kernel-open/nvidia-uvm/uvm_mem_test.c index 62cb9b20ff..0c7fd7a1eb 100644 --- a/kernel-open/nvidia-uvm/uvm_mem_test.c +++ b/kernel-open/nvidia-uvm/uvm_mem_test.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2023 NVIDIA Corporation + Copyright (c) 2016-2021 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -44,10 +44,10 @@ static NvU32 first_page_size(NvU32 page_sizes) static inline NV_STATUS __alloc_map_sysmem(NvU64 size, uvm_gpu_t *gpu, uvm_mem_t **sys_mem) { - if (g_uvm_global.conf_computing_enabled) + if (g_uvm_global.sev_enabled) return uvm_mem_alloc_sysmem_dma_and_map_cpu_kernel(size, gpu, current->mm, sys_mem); - - return uvm_mem_alloc_sysmem_and_map_cpu_kernel(size, current->mm, sys_mem); + else + return uvm_mem_alloc_sysmem_and_map_cpu_kernel(size, current->mm, sys_mem); } static NV_STATUS check_accessible_from_gpu(uvm_gpu_t *gpu, uvm_mem_t *mem) @@ -335,6 +335,9 @@ static NV_STATUS test_alloc_vidmem(uvm_gpu_t *gpu, NvU32 page_size, size_t size, static bool should_test_page_size(size_t alloc_size, NvU32 page_size) { + if (g_uvm_global.sev_enabled) + return false; + if (g_uvm_global.num_simulated_devices == 0) return true; diff --git a/kernel-open/nvidia-uvm/uvm_migrate.c b/kernel-open/nvidia-uvm/uvm_migrate.c index 63a7e06b00..1be4b1ddfa 100644 --- a/kernel-open/nvidia-uvm/uvm_migrate.c +++ b/kernel-open/nvidia-uvm/uvm_migrate.c @@ -130,9 +130,9 @@ static NV_STATUS block_migrate_map_unmapped_pages(uvm_va_block_t *va_block, NV_STATUS status = NV_OK; NV_STATUS tracker_status; - // Save the mask of unmapped pages because it will change after the + // Get the mask of unmapped pages because it will change after the // first map operation - uvm_page_mask_complement(&va_block_context->caller_page_mask, &va_block->maybe_mapped_pages); + uvm_va_block_unmapped_pages_get(va_block, region, &va_block_context->caller_page_mask); if (uvm_va_block_is_hmm(va_block) && !UVM_ID_IS_CPU(dest_id)) { // Do not map pages that are already resident on the CPU. This is in @@ -147,7 +147,7 @@ static NV_STATUS block_migrate_map_unmapped_pages(uvm_va_block_t *va_block, // such pages at all, when migrating. uvm_page_mask_andnot(&va_block_context->caller_page_mask, &va_block_context->caller_page_mask, - uvm_va_block_resident_mask_get(va_block, UVM_ID_CPU)); + uvm_va_block_resident_mask_get(va_block, UVM_ID_CPU, NUMA_NO_NODE)); } // Only map those pages that are not mapped anywhere else (likely due @@ -377,7 +377,7 @@ static bool va_block_should_do_cpu_preunmap(uvm_va_block_t *va_block, mapped_pages_cpu = uvm_va_block_map_mask_get(va_block, UVM_ID_CPU); if (uvm_processor_mask_test(&va_block->resident, dest_id)) { - const uvm_page_mask_t *resident_pages_dest = uvm_va_block_resident_mask_get(va_block, dest_id); + const uvm_page_mask_t *resident_pages_dest = uvm_va_block_resident_mask_get(va_block, dest_id, NUMA_NO_NODE); uvm_page_mask_t *do_not_unmap_pages = &va_block_context->scratch_page_mask; // TODO: Bug 1877578 diff --git a/kernel-open/nvidia-uvm/uvm_migrate_pageable.c b/kernel-open/nvidia-uvm/uvm_migrate_pageable.c index 44b5e857cc..e16053755c 100644 --- a/kernel-open/nvidia-uvm/uvm_migrate_pageable.c +++ b/kernel-open/nvidia-uvm/uvm_migrate_pageable.c @@ -672,14 +672,6 @@ static NV_STATUS nv_migrate_vma(struct migrate_vma *args, migrate_vma_state_t *s .finalize_and_map = uvm_migrate_vma_finalize_and_map_helper, }; - // WAR for Bug 4130089: [GH180][r535] WAR for kernel not issuing SMMU TLB - // invalidates on read-only to read-write upgrades - // - // This code path isn't used on GH180 but we need to maintain consistent - // behaviour on systems that do. - if (!vma_is_anonymous(args->vma)) - return NV_WARN_NOTHING_TO_DO; - ret = migrate_vma(&uvm_migrate_vma_ops, args->vma, args->start, args->end, args->src, args->dst, state); if (ret < 0) return errno_to_nv_status(ret); @@ -693,24 +685,6 @@ static NV_STATUS nv_migrate_vma(struct migrate_vma *args, migrate_vma_state_t *s if (ret < 0) return errno_to_nv_status(ret); - // TODO: Bug 2419180: support file-backed pages in migrate_vma, when - // support for it is added to the Linux kernel - // - // A side-effect of migrate_vma_setup() is it calls mmu notifiers even if a - // page can't be migrated (eg. because it's a non-anonymous mapping). We - // need this side-effect for SMMU on GH180 to ensure any cached read-only - // entries are flushed from SMMU on permission upgrade. - // - // TODO: Bug 4130089: [GH180][r535] WAR for kernel not issuing SMMU TLB - // invalidates on read-only to read-write upgrades - // - // The above WAR doesn't work for HugeTLBfs mappings because - // migrate_vma_setup() will fail in that case. - if (!vma_is_anonymous(args->vma)) { - migrate_vma_finalize(args); - return NV_WARN_NOTHING_TO_DO; - } - uvm_migrate_vma_alloc_and_copy(args, state); if (state->status == NV_OK) { migrate_vma_pages(args); @@ -884,13 +858,9 @@ static NV_STATUS migrate_pageable_vma(struct vm_area_struct *vma, start = max(start, vma->vm_start); outer = min(outer, vma->vm_end); - // migrate_vma only supports anonymous VMAs. We check for those after - // calling migrate_vma_setup() to workaround Bug 4130089. We need to check - // for HugeTLB VMAs here because migrate_vma_setup() will return a fatal - // error for those. - // TODO: Bug 4130089: [GH180][r535] WAR for kernel not issuing SMMU TLB - // invalidates on read-only to read-write upgrades - if (is_vm_hugetlb_page(vma)) + // TODO: Bug 2419180: support file-backed pages in migrate_vma, when + // support for it is added to the Linux kernel + if (!vma_is_anonymous(vma)) return NV_WARN_NOTHING_TO_DO; if (uvm_processor_mask_empty(&va_space->registered_gpus)) diff --git a/kernel-open/nvidia-uvm/uvm_migrate_pageable.h b/kernel-open/nvidia-uvm/uvm_migrate_pageable.h index 9b56bad355..41c01b2375 100644 --- a/kernel-open/nvidia-uvm/uvm_migrate_pageable.h +++ b/kernel-open/nvidia-uvm/uvm_migrate_pageable.h @@ -51,7 +51,7 @@ typedef struct #if defined(CONFIG_MIGRATE_VMA_HELPER) #define UVM_MIGRATE_VMA_SUPPORTED 1 #else -#if NV_IS_EXPORT_SYMBOL_PRESENT_migrate_vma_setup +#if defined(CONFIG_DEVICE_PRIVATE) && defined(NV_MIGRATE_VMA_SETUP_PRESENT) #define UVM_MIGRATE_VMA_SUPPORTED 1 #endif #endif diff --git a/kernel-open/nvidia-uvm/uvm_mmu.c b/kernel-open/nvidia-uvm/uvm_mmu.c index 2fff2c3a4d..e3d5e1b425 100644 --- a/kernel-open/nvidia-uvm/uvm_mmu.c +++ b/kernel-open/nvidia-uvm/uvm_mmu.c @@ -323,153 +323,37 @@ static void uvm_mmu_page_table_cpu_memset_16(uvm_gpu_t *gpu, uvm_mmu_page_table_cpu_unmap(gpu, phys_alloc); } -static void pde_fill_cpu(uvm_page_tree_t *tree, - uvm_page_directory_t *directory, - NvU32 start_index, - NvU32 pde_count, - uvm_mmu_page_table_alloc_t **phys_addr) +static void phys_mem_init(uvm_page_tree_t *tree, NvU32 page_size, uvm_page_directory_t *dir, uvm_push_t *push) { - NvU64 pde_data[2], entry_size; - NvU32 i; - - UVM_ASSERT(uvm_mmu_use_cpu(tree)); - - entry_size = tree->hal->entry_size(directory->depth); - UVM_ASSERT(sizeof(pde_data) >= entry_size); - - for (i = 0; i < pde_count; i++) { - tree->hal->make_pde(pde_data, phys_addr, directory->depth, directory->entries[start_index + i]); + NvU64 clear_bits[2]; + uvm_mmu_mode_hal_t *hal = tree->hal; - if (entry_size == sizeof(pde_data[0])) - uvm_mmu_page_table_cpu_memset_8(tree->gpu, &directory->phys_alloc, start_index + i, pde_data[0], 1); - else - uvm_mmu_page_table_cpu_memset_16(tree->gpu, &directory->phys_alloc, start_index + i, pde_data, 1); + if (dir->depth == tree->hal->page_table_depth(page_size)) { + *clear_bits = 0; // Invalid PTE } -} - -static void pde_fill_gpu(uvm_page_tree_t *tree, - uvm_page_directory_t *directory, - NvU32 start_index, - NvU32 pde_count, - uvm_mmu_page_table_alloc_t **phys_addr, - uvm_push_t *push) -{ - NvU64 pde_data[2], entry_size; - uvm_gpu_address_t pde_entry_addr = uvm_mmu_gpu_address(tree->gpu, directory->phys_alloc.addr); - NvU32 max_inline_entries; - uvm_push_flag_t push_membar_flag = UVM_PUSH_FLAG_COUNT; - uvm_gpu_address_t inline_data_addr; - uvm_push_inline_data_t inline_data; - NvU32 entry_count, i, j; - - UVM_ASSERT(!uvm_mmu_use_cpu(tree)); - - entry_size = tree->hal->entry_size(directory->depth); - UVM_ASSERT(sizeof(pde_data) >= entry_size); - - max_inline_entries = UVM_PUSH_INLINE_DATA_MAX_SIZE / entry_size; - - if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE)) - push_membar_flag = UVM_PUSH_FLAG_NEXT_MEMBAR_NONE; - else if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU)) - push_membar_flag = UVM_PUSH_FLAG_NEXT_MEMBAR_GPU; - - pde_entry_addr.address += start_index * entry_size; - - for (i = 0; i < pde_count;) { - // All but the first memory operation can be pipelined. We respect the - // caller's pipelining settings for the first push. - if (i != 0) - uvm_push_set_flag(push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED); - - entry_count = min(pde_count - i, max_inline_entries); - - // No membar is needed until the last memory operation. Otherwise, - // use caller's membar flag. - if ((i + entry_count) < pde_count) - uvm_push_set_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); - else if (push_membar_flag != UVM_PUSH_FLAG_COUNT) - uvm_push_set_flag(push, push_membar_flag); - - uvm_push_inline_data_begin(push, &inline_data); - for (j = 0; j < entry_count; j++) { - tree->hal->make_pde(pde_data, phys_addr, directory->depth, directory->entries[start_index + i + j]); - uvm_push_inline_data_add(&inline_data, pde_data, entry_size); - } - inline_data_addr = uvm_push_inline_data_end(&inline_data); - - tree->gpu->parent->ce_hal->memcopy(push, pde_entry_addr, inline_data_addr, entry_count * entry_size); + else { + // passing in NULL for the phys_allocs will mark the child entries as invalid + uvm_mmu_page_table_alloc_t *phys_allocs[2] = {NULL, NULL}; + hal->make_pde(clear_bits, phys_allocs, dir->depth); - i += entry_count; - pde_entry_addr.address += entry_size * entry_count; + // Make sure that using only clear_bits[0] will work + UVM_ASSERT(hal->entry_size(dir->depth) == sizeof(clear_bits[0]) || clear_bits[0] == clear_bits[1]); } -} - -// pde_fill() populates pde_count PDE entries (starting at start_index) with -// the same mapping, i.e., with the same physical address (phys_addr). -// pde_fill() is optimized for pde_count == 1, which is the common case. The -// map_remap() function is the only case where pde_count > 1, only used on GA100 -// GPUs for 512MB page size mappings. -static void pde_fill(uvm_page_tree_t *tree, - uvm_page_directory_t *directory, - NvU32 start_index, - NvU32 pde_count, - uvm_mmu_page_table_alloc_t **phys_addr, - uvm_push_t *push) -{ - UVM_ASSERT(start_index + pde_count <= uvm_mmu_page_tree_entries(tree, directory->depth, UVM_PAGE_SIZE_AGNOSTIC)); - if (push) - pde_fill_gpu(tree, directory, start_index, pde_count, phys_addr, push); - else - pde_fill_cpu(tree, directory, start_index, pde_count, phys_addr); -} - -static void phys_mem_init(uvm_page_tree_t *tree, NvU32 page_size, uvm_page_directory_t *dir, uvm_push_t *push) -{ - NvU32 entries_count = uvm_mmu_page_tree_entries(tree, dir->depth, page_size); - - // Passing in NULL for the phys_allocs will mark the child entries as - // invalid. - uvm_mmu_page_table_alloc_t *phys_allocs[2] = {NULL, NULL}; - - // Init with an invalid PTE or clean PDE. Only Maxwell PDEs can have more - // than 512 entries. We initialize them all with the same clean PDE. - // Additionally, only ATS systems may require clean PDEs bit settings based - // on the mapping VA. - if (dir->depth == tree->hal->page_table_depth(page_size) || (entries_count > 512 && !g_uvm_global.ats.enabled)) { - NvU64 clear_bits[2]; - - // If it is not a PTE, make a clean PDE. - if (dir->depth != tree->hal->page_table_depth(page_size)) { - tree->hal->make_pde(clear_bits, phys_allocs, dir->depth, dir->entries[0]); - - // Make sure that using only clear_bits[0] will work. - UVM_ASSERT(tree->hal->entry_size(dir->depth) == sizeof(clear_bits[0]) || clear_bits[0] == clear_bits[1]); - } - else { - *clear_bits = 0; - } - - // Initialize the memory to a reasonable value. - if (push) { - tree->gpu->parent->ce_hal->memset_8(push, - uvm_mmu_gpu_address(tree->gpu, dir->phys_alloc.addr), - *clear_bits, - dir->phys_alloc.size); - } - else { - uvm_mmu_page_table_cpu_memset_8(tree->gpu, - &dir->phys_alloc, - 0, + // initialize the memory to a reasonable value + if (push) { + tree->gpu->parent->ce_hal->memset_8(push, + uvm_mmu_gpu_address(tree->gpu, dir->phys_alloc.addr), *clear_bits, - dir->phys_alloc.size / sizeof(*clear_bits)); - } + dir->phys_alloc.size); } else { - pde_fill(tree, dir, 0, entries_count, phys_allocs, push); + uvm_mmu_page_table_cpu_memset_8(tree->gpu, + &dir->phys_alloc, + 0, + *clear_bits, + dir->phys_alloc.size / sizeof(*clear_bits)); } - } static uvm_page_directory_t *allocate_directory(uvm_page_tree_t *tree, @@ -483,10 +367,8 @@ static uvm_page_directory_t *allocate_directory(uvm_page_tree_t *tree, NvLength phys_alloc_size = hal->allocation_size(depth, page_size); uvm_page_directory_t *dir; - // The page tree doesn't cache PTEs so space is not allocated for entries - // that are always PTEs. - // 2M PTEs may later become PDEs so pass UVM_PAGE_SIZE_AGNOSTIC, not - // page_size. + // The page tree doesn't cache PTEs so space is not allocated for entries that are always PTEs. + // 2M PTEs may later become PDEs so pass UVM_PAGE_SIZE_AGNOSTIC, not page_size. if (depth == hal->page_table_depth(UVM_PAGE_SIZE_AGNOSTIC)) entry_count = 0; else @@ -527,6 +409,108 @@ static inline NvU32 index_to_entry(uvm_mmu_mode_hal_t *hal, NvU32 entry_index, N return hal->entries_per_index(depth) * entry_index + hal->entry_offset(depth, page_size); } +static void pde_fill_cpu(uvm_page_tree_t *tree, + NvU32 depth, + uvm_mmu_page_table_alloc_t *directory, + NvU32 start_index, + NvU32 pde_count, + uvm_mmu_page_table_alloc_t **phys_addr) +{ + NvU64 pde_data[2], entry_size; + + UVM_ASSERT(uvm_mmu_use_cpu(tree)); + entry_size = tree->hal->entry_size(depth); + UVM_ASSERT(sizeof(pde_data) >= entry_size); + + tree->hal->make_pde(pde_data, phys_addr, depth); + + if (entry_size == sizeof(pde_data[0])) + uvm_mmu_page_table_cpu_memset_8(tree->gpu, directory, start_index, pde_data[0], pde_count); + else + uvm_mmu_page_table_cpu_memset_16(tree->gpu, directory, start_index, pde_data, pde_count); +} + +static void pde_fill_gpu(uvm_page_tree_t *tree, + NvU32 depth, + uvm_mmu_page_table_alloc_t *directory, + NvU32 start_index, + NvU32 pde_count, + uvm_mmu_page_table_alloc_t **phys_addr, + uvm_push_t *push) +{ + NvU64 pde_data[2], entry_size; + uvm_gpu_address_t pde_entry_addr = uvm_mmu_gpu_address(tree->gpu, directory->addr); + + UVM_ASSERT(!uvm_mmu_use_cpu(tree)); + + entry_size = tree->hal->entry_size(depth); + UVM_ASSERT(sizeof(pde_data) >= entry_size); + + tree->hal->make_pde(pde_data, phys_addr, depth); + pde_entry_addr.address += start_index * entry_size; + + if (entry_size == sizeof(pde_data[0])) { + tree->gpu->parent->ce_hal->memset_8(push, pde_entry_addr, pde_data[0], sizeof(pde_data[0]) * pde_count); + } + else { + NvU32 max_inline_entries = UVM_PUSH_INLINE_DATA_MAX_SIZE / sizeof(pde_data); + uvm_gpu_address_t inline_data_addr; + uvm_push_inline_data_t inline_data; + uvm_push_flag_t push_membar_flag = UVM_PUSH_FLAG_COUNT; + NvU32 i; + + if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE)) + push_membar_flag = UVM_PUSH_FLAG_NEXT_MEMBAR_NONE; + else if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU)) + push_membar_flag = UVM_PUSH_FLAG_NEXT_MEMBAR_GPU; + + for (i = 0; i < pde_count;) { + NvU32 j; + NvU32 entry_count = min(pde_count - i, max_inline_entries); + + uvm_push_inline_data_begin(push, &inline_data); + for (j = 0; j < entry_count; j++) + uvm_push_inline_data_add(&inline_data, pde_data, sizeof(pde_data)); + inline_data_addr = uvm_push_inline_data_end(&inline_data); + + // All but the first memcopy can be pipelined. We respect the + // caller's pipelining settings for the first push. + if (i != 0) + uvm_push_set_flag(push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED); + + // No membar is needed until the last copy. Otherwise, use + // caller's membar flag. + if (i + entry_count < pde_count) + uvm_push_set_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); + else if (push_membar_flag != UVM_PUSH_FLAG_COUNT) + uvm_push_set_flag(push, push_membar_flag); + + tree->gpu->parent->ce_hal->memcopy(push, pde_entry_addr, inline_data_addr, entry_count * sizeof(pde_data)); + + i += entry_count; + pde_entry_addr.address += sizeof(pde_data) * entry_count; + } + } +} + +// pde_fill() populates pde_count PDE entries (starting at start_index) with +// the same mapping, i.e., with the same physical address (phys_addr). +static void pde_fill(uvm_page_tree_t *tree, + NvU32 depth, + uvm_mmu_page_table_alloc_t *directory, + NvU32 start_index, + NvU32 pde_count, + uvm_mmu_page_table_alloc_t **phys_addr, + uvm_push_t *push) +{ + UVM_ASSERT(start_index + pde_count <= uvm_mmu_page_tree_entries(tree, depth, UVM_PAGE_SIZE_AGNOSTIC)); + + if (push) + pde_fill_gpu(tree, depth, directory, start_index, pde_count, phys_addr, push); + else + pde_fill_cpu(tree, depth, directory, start_index, pde_count, phys_addr); +} + static uvm_page_directory_t *host_pde_write(uvm_page_directory_t *dir, uvm_page_directory_t *parent, NvU32 index_in_parent) @@ -556,7 +540,7 @@ static void pde_write(uvm_page_tree_t *tree, phys_allocs[i] = &entry->phys_alloc; } - pde_fill(tree, dir, entry_index, 1, phys_allocs, push); + pde_fill(tree, dir->depth, &dir->phys_alloc, entry_index, 1, phys_allocs, push); } static void host_pde_clear(uvm_page_tree_t *tree, uvm_page_directory_t *dir, NvU32 entry_index, NvU32 page_size) @@ -829,11 +813,8 @@ static NV_STATUS allocate_page_table(uvm_page_tree_t *tree, NvU32 page_size, uvm static void map_remap_deinit(uvm_page_tree_t *tree) { - if (tree->map_remap.pde0) { - phys_mem_deallocate(tree, &tree->map_remap.pde0->phys_alloc); - uvm_kvfree(tree->map_remap.pde0); - tree->map_remap.pde0 = NULL; - } + if (tree->map_remap.pde0.size) + phys_mem_deallocate(tree, &tree->map_remap.pde0); if (tree->map_remap.ptes_invalid_4k.size) phys_mem_deallocate(tree, &tree->map_remap.ptes_invalid_4k); @@ -858,16 +839,10 @@ static NV_STATUS map_remap_init(uvm_page_tree_t *tree) // PDE1-depth(512M) PTE. We first map it to the pde0 directory, then we // return the PTE for the get_ptes()'s caller. if (tree->hal->page_sizes() & UVM_PAGE_SIZE_512M) { - tree->map_remap.pde0 = allocate_directory(tree, - UVM_PAGE_SIZE_2M, - tree->hal->page_table_depth(UVM_PAGE_SIZE_2M), - UVM_PMM_ALLOC_FLAGS_EVICT); - if (tree->map_remap.pde0 == NULL) { - status = NV_ERR_NO_MEMORY; + status = allocate_page_table(tree, UVM_PAGE_SIZE_2M, &tree->map_remap.pde0); + if (status != NV_OK) goto error; - } } - status = page_tree_begin_acquire(tree, &tree->tracker, &push, "map remap init"); if (status != NV_OK) goto error; @@ -889,23 +864,22 @@ static NV_STATUS map_remap_init(uvm_page_tree_t *tree) uvm_mmu_page_table_alloc_t *phys_allocs[2] = {NULL, NULL}; NvU32 depth = tree->hal->page_table_depth(UVM_PAGE_SIZE_4K) - 1; size_t index_4k = tree->hal->entry_offset(depth, UVM_PAGE_SIZE_4K); - NvU32 pde0_entries = tree->map_remap.pde0->phys_alloc.size / tree->hal->entry_size(tree->map_remap.pde0->depth); + + // pde0 depth equals UVM_PAGE_SIZE_2M. + NvU32 pde0_depth = tree->hal->page_table_depth(UVM_PAGE_SIZE_2M); + NvU32 pde0_entries = tree->map_remap.pde0.size / tree->hal->entry_size(pde0_depth); // The big-page entry is NULL which makes it an invalid entry. phys_allocs[index_4k] = &tree->map_remap.ptes_invalid_4k; // By default CE operations include a MEMBAR_SYS. MEMBAR_GPU is // sufficient when pde0 is allocated in VIDMEM. - if (tree->map_remap.pde0->phys_alloc.addr.aperture == UVM_APERTURE_VID) + if (tree->map_remap.pde0.addr.aperture == UVM_APERTURE_VID) uvm_push_set_flag(&push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU); - // This is an orphan directory, make_pde() requires a directory to - // compute the VA. The UVM depth map_remap() operates on is not in the - // range make_pde() must operate. We only need to supply the fields used - // by make_pde() to not access invalid memory addresses. - pde_fill(tree, - tree->map_remap.pde0, + pde0_depth, + &tree->map_remap.pde0, 0, pde0_entries, (uvm_mmu_page_table_alloc_t **)&phys_allocs, @@ -932,10 +906,11 @@ static NV_STATUS map_remap_init(uvm_page_tree_t *tree) // --------------|-------------------------||----------------|---------------- // vidmem | - || vidmem | false // sysmem | - || sysmem | false -// default | || vidmem | true +// default | || vidmem | true (1) // default | vidmem || vidmem | false // default | sysmem || sysmem | false // +// (1) When SEV mode is enabled, the fallback path is disabled. // // In SR-IOV heavy the the page tree must be in vidmem, to prevent guest drivers // from updating GPU page tables without hypervisor knowledge. @@ -951,27 +926,28 @@ static NV_STATUS map_remap_init(uvm_page_tree_t *tree) // static void page_tree_set_location(uvm_page_tree_t *tree, uvm_aperture_t location) { + bool should_location_be_vidmem; UVM_ASSERT(tree->gpu != NULL); UVM_ASSERT_MSG((location == UVM_APERTURE_VID) || (location == UVM_APERTURE_SYS) || (location == UVM_APERTURE_DEFAULT), "Invalid location %s (%d)\n", uvm_aperture_string(location), (int)location); + should_location_be_vidmem = uvm_gpu_is_virt_mode_sriov_heavy(tree->gpu) + || uvm_conf_computing_mode_enabled(tree->gpu); + // The page tree of a "fake" GPU used during page tree testing can be in - // sysmem in scenarios where a "real" GPU must be in vidmem. Fake GPUs can - // be identified by having no channel manager. - if (tree->gpu->channel_manager != NULL) { - - if (uvm_gpu_is_virt_mode_sriov_heavy(tree->gpu)) - UVM_ASSERT(location == UVM_APERTURE_VID); - else if (uvm_conf_computing_mode_enabled(tree->gpu)) - UVM_ASSERT(location == UVM_APERTURE_VID); - } + // sysmem even if should_location_be_vidmem is true. A fake GPU can be + // identified by having no channel manager. + if ((tree->gpu->channel_manager != NULL) && should_location_be_vidmem) + UVM_ASSERT(location == UVM_APERTURE_VID); if (location == UVM_APERTURE_DEFAULT) { if (page_table_aperture == UVM_APERTURE_DEFAULT) { tree->location = UVM_APERTURE_VID; - tree->location_sys_fallback = true; + + // See the comment (1) above. + tree->location_sys_fallback = !g_uvm_global.sev_enabled; } else { tree->location = page_table_aperture; @@ -1358,9 +1334,10 @@ static NV_STATUS map_remap(uvm_page_tree_t *tree, NvU64 start, NvLength size, uv if (uvm_page_table_range_aperture(range) == UVM_APERTURE_VID) uvm_push_set_flag(&push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU); - phys_alloc[0] = &tree->map_remap.pde0->phys_alloc; + phys_alloc[0] = &tree->map_remap.pde0; pde_fill(tree, - range->table, + range->table->depth, + &range->table->phys_alloc, range->start_index, range->entry_count, (uvm_mmu_page_table_alloc_t **)&phys_alloc, diff --git a/kernel-open/nvidia-uvm/uvm_mmu.h b/kernel-open/nvidia-uvm/uvm_mmu.h index 2d4c78ee59..2f21b6ee78 100644 --- a/kernel-open/nvidia-uvm/uvm_mmu.h +++ b/kernel-open/nvidia-uvm/uvm_mmu.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2023 NVIDIA Corporation + Copyright (c) 2015-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -219,7 +219,7 @@ struct uvm_mmu_mode_hal_struct // point to two items for dual PDEs). // any of allocs are allowed to be NULL, in which case they are to be // treated as empty. - void (*make_pde)(void *entry, uvm_mmu_page_table_alloc_t **allocs, NvU32 depth, uvm_page_directory_t *child_dir); + void (*make_pde)(void *entry, uvm_mmu_page_table_alloc_t **allocs, NvU32 depth); // size of an entry in a directory/table. Generally either 8 or 16 bytes. // (in the case of Pascal dual PDEs) @@ -229,7 +229,7 @@ struct uvm_mmu_mode_hal_struct NvU32 (*entries_per_index)(NvU32 depth); // For dual PDEs, this is ether 1 or 0, depending on the page size. - // This is used to index the host copy only. GPU PDEs are always entirely + // This is used to index the host copy only. GPU PDEs are always entirely // re-written using make_pde. NvLength (*entry_offset)(NvU32 depth, NvU32 page_size); @@ -295,8 +295,9 @@ struct uvm_page_tree_struct // PDE0 where all big-page entries are invalid, and small-page entries // point to ptes_invalid_4k. - // pde0 is used on Pascal+ GPUs, i.e., they have the same PDE format. - uvm_page_directory_t *pde0; + // pde0 is only used on Pascal-Ampere, i.e., they have the same PDE + // format. + uvm_mmu_page_table_alloc_t pde0; } map_remap; // Tracker for all GPU operations on the tree @@ -364,32 +365,21 @@ void uvm_page_tree_deinit(uvm_page_tree_t *tree); // the same page size without an intervening put_ptes. To duplicate a subset of // an existing range or change the size of an existing range, use // uvm_page_table_range_get_upper() and/or uvm_page_table_range_shrink(). -NV_STATUS uvm_page_tree_get_ptes(uvm_page_tree_t *tree, - NvU32 page_size, - NvU64 start, - NvLength size, - uvm_pmm_alloc_flags_t pmm_flags, - uvm_page_table_range_t *range); +NV_STATUS uvm_page_tree_get_ptes(uvm_page_tree_t *tree, NvU32 page_size, NvU64 start, NvLength size, + uvm_pmm_alloc_flags_t pmm_flags, uvm_page_table_range_t *range); // Same as uvm_page_tree_get_ptes(), but doesn't synchronize the GPU work. // // All pending operations can be waited on with uvm_page_tree_wait(). -NV_STATUS uvm_page_tree_get_ptes_async(uvm_page_tree_t *tree, - NvU32 page_size, - NvU64 start, - NvLength size, - uvm_pmm_alloc_flags_t pmm_flags, - uvm_page_table_range_t *range); +NV_STATUS uvm_page_tree_get_ptes_async(uvm_page_tree_t *tree, NvU32 page_size, NvU64 start, NvLength size, + uvm_pmm_alloc_flags_t pmm_flags, uvm_page_table_range_t *range); // Returns a single-entry page table range for the addresses passed. // The size parameter must be a page size supported by this tree. // This is equivalent to calling uvm_page_tree_get_ptes() with size equal to // page_size. -NV_STATUS uvm_page_tree_get_entry(uvm_page_tree_t *tree, - NvU32 page_size, - NvU64 start, - uvm_pmm_alloc_flags_t pmm_flags, - uvm_page_table_range_t *single); +NV_STATUS uvm_page_tree_get_entry(uvm_page_tree_t *tree, NvU32 page_size, NvU64 start, + uvm_pmm_alloc_flags_t pmm_flags, uvm_page_table_range_t *single); // For a single-entry page table range, write the PDE (which could be a dual // PDE) to the GPU. @@ -488,8 +478,8 @@ NV_STATUS uvm_page_table_range_vec_create(uvm_page_tree_t *tree, // new_range_vec will contain the upper portion of range_vec, starting at // new_end + 1. // -// new_end + 1 is required to be within the address range of range_vec and be -// aligned to range_vec's page_size. +// new_end + 1 is required to be within the address range of range_vec and be aligned to +// range_vec's page_size. // // On failure, the original range vector is left unmodified. NV_STATUS uvm_page_table_range_vec_split_upper(uvm_page_table_range_vec_t *range_vec, @@ -511,22 +501,18 @@ void uvm_page_table_range_vec_destroy(uvm_page_table_range_vec_t *range_vec); // for each offset. // The caller_data pointer is what the caller passed in as caller_data to // uvm_page_table_range_vec_write_ptes(). -typedef NvU64 (*uvm_page_table_range_pte_maker_t)(uvm_page_table_range_vec_t *range_vec, - NvU64 offset, - void *caller_data); +typedef NvU64 (*uvm_page_table_range_pte_maker_t)(uvm_page_table_range_vec_t *range_vec, NvU64 offset, + void *caller_data); -// Write all PTEs covered by the range vector using the given PTE making -// function. +// Write all PTEs covered by the range vector using the given PTE making function. // // After writing all the PTEs a TLB invalidate operation is performed including // the passed in tlb_membar. // // See comments about uvm_page_table_range_pte_maker_t for details about the // PTE making callback. -NV_STATUS uvm_page_table_range_vec_write_ptes(uvm_page_table_range_vec_t *range_vec, - uvm_membar_t tlb_membar, - uvm_page_table_range_pte_maker_t pte_maker, - void *caller_data); +NV_STATUS uvm_page_table_range_vec_write_ptes(uvm_page_table_range_vec_t *range_vec, uvm_membar_t tlb_membar, + uvm_page_table_range_pte_maker_t pte_maker, void *caller_data); // Set all PTEs covered by the range vector to an empty PTE // @@ -650,9 +636,8 @@ static NvU64 uvm_page_table_range_size(uvm_page_table_range_t *range) // Get the physical address of the entry at entry_index within the range // (counted from range->start_index). -static uvm_gpu_phys_address_t uvm_page_table_range_entry_address(uvm_page_tree_t *tree, - uvm_page_table_range_t *range, - size_t entry_index) +static uvm_gpu_phys_address_t uvm_page_table_range_entry_address(uvm_page_tree_t *tree, uvm_page_table_range_t *range, + size_t entry_index) { NvU32 entry_size = uvm_mmu_pte_size(tree, range->page_size); uvm_gpu_phys_address_t entry = range->table->phys_alloc.addr; diff --git a/kernel-open/nvidia-uvm/uvm_page_tree_test.c b/kernel-open/nvidia-uvm/uvm_page_tree_test.c index 051076174d..a5710e582f 100644 --- a/kernel-open/nvidia-uvm/uvm_page_tree_test.c +++ b/kernel-open/nvidia-uvm/uvm_page_tree_test.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2023 NVIDIA Corporation + Copyright (c) 2015-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -146,15 +146,9 @@ static void fake_tlb_invals_disable(void) g_fake_tlb_invals_tracking_enabled = false; } -// Fake TLB invalidate VA that just saves off the parameters so that they can be -// verified later. -static void fake_tlb_invalidate_va(uvm_push_t *push, - uvm_gpu_phys_address_t pdb, - NvU32 depth, - NvU64 base, - NvU64 size, - NvU32 page_size, - uvm_membar_t membar) +// Fake TLB invalidate VA that just saves off the parameters so that they can be verified later +static void fake_tlb_invalidate_va(uvm_push_t *push, uvm_gpu_phys_address_t pdb, + NvU32 depth, NvU64 base, NvU64 size, NvU32 page_size, uvm_membar_t membar) { if (!g_fake_tlb_invals_tracking_enabled) return; @@ -216,8 +210,8 @@ static bool assert_and_reset_last_invalidate(NvU32 expected_depth, bool expected } if ((g_last_fake_inval->membar == UVM_MEMBAR_NONE) == expected_membar) { UVM_TEST_PRINT("Expected %s membar, got %s instead\n", - expected_membar ? "a" : "no", - uvm_membar_string(g_last_fake_inval->membar)); + expected_membar ? "a" : "no", + uvm_membar_string(g_last_fake_inval->membar)); result = false; } @@ -236,8 +230,7 @@ static bool assert_last_invalidate_all(NvU32 expected_depth, bool expected_memba } if (g_last_fake_inval->base != 0 || g_last_fake_inval->size != -1) { UVM_TEST_PRINT("Expected invalidate all but got range [0x%llx, 0x%llx) instead\n", - g_last_fake_inval->base, - g_last_fake_inval->base + g_last_fake_inval->size); + g_last_fake_inval->base, g_last_fake_inval->base + g_last_fake_inval->size); return false; } if (g_last_fake_inval->depth != expected_depth) { @@ -254,16 +247,15 @@ static bool assert_invalidate_range_specific(fake_tlb_invalidate_t *inval, UVM_ASSERT(g_fake_tlb_invals_tracking_enabled); if (g_fake_invals_count == 0) { - UVM_TEST_PRINT("Expected an invalidate for range [0x%llx, 0x%llx), but got none\n", base, base + size); + UVM_TEST_PRINT("Expected an invalidate for range [0x%llx, 0x%llx), but got none\n", + base, base + size); return false; } if ((inval->base != base || inval->size != size) && inval->base != 0 && inval->size != -1) { UVM_TEST_PRINT("Expected invalidate range [0x%llx, 0x%llx), but got range [0x%llx, 0x%llx) instead\n", - base, - base + size, - inval->base, - inval->base + inval->size); + base, base + size, + inval->base, inval->base + inval->size); return false; } if (inval->depth != expected_depth) { @@ -278,13 +270,7 @@ static bool assert_invalidate_range_specific(fake_tlb_invalidate_t *inval, return true; } -static bool assert_invalidate_range(NvU64 base, - NvU64 size, - NvU32 page_size, - bool allow_inval_all, - NvU32 range_depth, - NvU32 all_depth, - bool expected_membar) +static bool assert_invalidate_range(NvU64 base, NvU64 size, NvU32 page_size, bool allow_inval_all, NvU32 range_depth, NvU32 all_depth, bool expected_membar) { NvU32 i; @@ -502,6 +488,7 @@ static NV_STATUS alloc_adjacent_pde_64k_memory(uvm_gpu_t *gpu) return NV_OK; } + static NV_STATUS alloc_nearby_pde_64k_memory(uvm_gpu_t *gpu) { uvm_page_tree_t tree; @@ -855,7 +842,6 @@ static NV_STATUS get_two_free_apart(uvm_gpu_t *gpu) TEST_CHECK_RET(range2.entry_count == 256); TEST_CHECK_RET(range2.table->ref_count == 512); TEST_CHECK_RET(range1.table == range2.table); - // 4k page is second entry in a dual PDE TEST_CHECK_RET(range1.table == tree.root->entries[0]->entries[0]->entries[0]->entries[1]); TEST_CHECK_RET(range1.start_index == 256); @@ -885,7 +871,6 @@ static NV_STATUS get_overlapping_dual_pdes(uvm_gpu_t *gpu) MEM_NV_CHECK_RET(test_page_tree_get_ptes(&tree, UVM_PAGE_SIZE_64K, size, size, &range64k), NV_OK); TEST_CHECK_RET(range64k.entry_count == 16); TEST_CHECK_RET(range64k.table->ref_count == 16); - // 4k page is second entry in a dual PDE TEST_CHECK_RET(range64k.table == tree.root->entries[0]->entries[0]->entries[0]->entries[0]); TEST_CHECK_RET(range64k.start_index == 16); @@ -1045,13 +1030,10 @@ static NV_STATUS test_tlb_invalidates(uvm_gpu_t *gpu) // Depth 4 NvU64 extent_pte = UVM_PAGE_SIZE_2M; - // Depth 3 NvU64 extent_pde0 = extent_pte * (1ull << 8); - // Depth 2 NvU64 extent_pde1 = extent_pde0 * (1ull << 9); - // Depth 1 NvU64 extent_pde2 = extent_pde1 * (1ull << 9); @@ -1099,11 +1081,7 @@ static NV_STATUS test_tlb_invalidates(uvm_gpu_t *gpu) return status; } -static NV_STATUS test_tlb_batch_invalidates_case(uvm_page_tree_t *tree, - NvU64 base, - NvU64 size, - NvU32 min_page_size, - NvU32 max_page_size) +static NV_STATUS test_tlb_batch_invalidates_case(uvm_page_tree_t *tree, NvU64 base, NvU64 size, NvU32 min_page_size, NvU32 max_page_size) { NV_STATUS status = NV_OK; uvm_push_t push; @@ -1227,11 +1205,7 @@ static bool assert_range_vec_ptes(uvm_page_table_range_vec_t *range_vec, bool ex NvU64 expected_pte = expecting_cleared ? 0 : range_vec->size + offset; if (*pte != expected_pte) { UVM_TEST_PRINT("PTE is 0x%llx instead of 0x%llx for offset 0x%llx within range [0x%llx, 0x%llx)\n", - *pte, - expected_pte, - offset, - range_vec->start, - range_vec->size); + *pte, expected_pte, offset, range_vec->start, range_vec->size); return false; } offset += range_vec->page_size; @@ -1252,11 +1226,7 @@ static NV_STATUS test_range_vec_write_ptes(uvm_page_table_range_vec_t *range_vec TEST_CHECK_RET(data.status == NV_OK); TEST_CHECK_RET(data.count == range_vec->size / range_vec->page_size); TEST_CHECK_RET(assert_invalidate_range_specific(g_last_fake_inval, - range_vec->start, - range_vec->size, - range_vec->page_size, - page_table_depth, - membar != UVM_MEMBAR_NONE)); + range_vec->start, range_vec->size, range_vec->page_size, page_table_depth, membar != UVM_MEMBAR_NONE)); TEST_CHECK_RET(assert_range_vec_ptes(range_vec, false)); fake_tlb_invals_disable(); @@ -1279,11 +1249,7 @@ static NV_STATUS test_range_vec_clear_ptes(uvm_page_table_range_vec_t *range_vec return NV_OK; } -static NV_STATUS test_range_vec_create(uvm_page_tree_t *tree, - NvU64 start, - NvU64 size, - NvU32 page_size, - uvm_page_table_range_vec_t **range_vec_out) +static NV_STATUS test_range_vec_create(uvm_page_tree_t *tree, NvU64 start, NvU64 size, NvU32 page_size, uvm_page_table_range_vec_t **range_vec_out) { uvm_page_table_range_vec_t *range_vec; uvm_pmm_alloc_flags_t pmm_flags = UVM_PMM_ALLOC_FLAGS_EVICT; @@ -1586,17 +1552,17 @@ static NV_STATUS entry_test_maxwell(uvm_gpu_t *gpu) memset(phys_allocs, 0, sizeof(phys_allocs)); - hal->make_pde(&pde_bits, phys_allocs, 0, NULL); + hal->make_pde(&pde_bits, phys_allocs, 0); TEST_CHECK_RET(pde_bits == 0x0L); phys_allocs[0] = &alloc_sys; phys_allocs[1] = &alloc_vid; - hal->make_pde(&pde_bits, phys_allocs, 0, NULL); + hal->make_pde(&pde_bits, phys_allocs, 0); TEST_CHECK_RET(pde_bits == 0x1BBBBBBD99999992LL); phys_allocs[0] = &alloc_vid; phys_allocs[1] = &alloc_sys; - hal->make_pde(&pde_bits, phys_allocs, 0, NULL); + hal->make_pde(&pde_bits, phys_allocs, 0); TEST_CHECK_RET(pde_bits == 0x9999999E1BBBBBB1LL); for (j = 0; j <= 2; j++) { @@ -1666,7 +1632,6 @@ static NV_STATUS entry_test_pascal(uvm_gpu_t *gpu, entry_test_page_size_func ent uvm_mmu_page_table_alloc_t *phys_allocs[2] = {NULL, NULL}; uvm_mmu_page_table_alloc_t alloc_sys = fake_table_alloc(UVM_APERTURE_SYS, 0x399999999999000LL); uvm_mmu_page_table_alloc_t alloc_vid = fake_table_alloc(UVM_APERTURE_VID, 0x1BBBBBB000LL); - // big versions have [11:8] set as well to test the page table merging uvm_mmu_page_table_alloc_t alloc_big_sys = fake_table_alloc(UVM_APERTURE_SYS, 0x399999999999900LL); uvm_mmu_page_table_alloc_t alloc_big_vid = fake_table_alloc(UVM_APERTURE_VID, 0x1BBBBBBB00LL); @@ -1674,31 +1639,31 @@ static NV_STATUS entry_test_pascal(uvm_gpu_t *gpu, entry_test_page_size_func ent uvm_mmu_mode_hal_t *hal = gpu->parent->arch_hal->mmu_mode_hal(UVM_PAGE_SIZE_64K); // Make sure cleared PDEs work as expected - hal->make_pde(pde_bits, phys_allocs, 0, NULL); + hal->make_pde(pde_bits, phys_allocs, 0); TEST_CHECK_RET(pde_bits[0] == 0); memset(pde_bits, 0xFF, sizeof(pde_bits)); - hal->make_pde(pde_bits, phys_allocs, 3, NULL); + hal->make_pde(pde_bits, phys_allocs, 3); TEST_CHECK_RET(pde_bits[0] == 0 && pde_bits[1] == 0); // Sys and vidmem PDEs phys_allocs[0] = &alloc_sys; - hal->make_pde(pde_bits, phys_allocs, 0, NULL); + hal->make_pde(pde_bits, phys_allocs, 0); TEST_CHECK_RET(pde_bits[0] == 0x3999999999990C); phys_allocs[0] = &alloc_vid; - hal->make_pde(pde_bits, phys_allocs, 0, NULL); + hal->make_pde(pde_bits, phys_allocs, 0); TEST_CHECK_RET(pde_bits[0] == 0x1BBBBBB0A); // Dual PDEs phys_allocs[0] = &alloc_big_sys; phys_allocs[1] = &alloc_vid; - hal->make_pde(pde_bits, phys_allocs, 3, NULL); + hal->make_pde(pde_bits, phys_allocs, 3); TEST_CHECK_RET(pde_bits[0] == 0x3999999999999C && pde_bits[1] == 0x1BBBBBB0A); phys_allocs[0] = &alloc_big_vid; phys_allocs[1] = &alloc_sys; - hal->make_pde(pde_bits, phys_allocs, 3, NULL); + hal->make_pde(pde_bits, phys_allocs, 3); TEST_CHECK_RET(pde_bits[0] == 0x1BBBBBBBA && pde_bits[1] == 0x3999999999990C); // uncached, i.e., the sysmem data is not cached in GPU's L2 cache. Clear @@ -1762,36 +1727,36 @@ static NV_STATUS entry_test_volta(uvm_gpu_t *gpu, entry_test_page_size_func entr uvm_mmu_mode_hal_t *hal = gpu->parent->arch_hal->mmu_mode_hal(UVM_PAGE_SIZE_64K); // Make sure cleared PDEs work as expected - hal->make_pde(pde_bits, phys_allocs, 0, NULL); + hal->make_pde(pde_bits, phys_allocs, 0); TEST_CHECK_RET(pde_bits[0] == 0); memset(pde_bits, 0xFF, sizeof(pde_bits)); - hal->make_pde(pde_bits, phys_allocs, 3, NULL); + hal->make_pde(pde_bits, phys_allocs, 3); TEST_CHECK_RET(pde_bits[0] == 0 && pde_bits[1] == 0); // Sys and vidmem PDEs phys_allocs[0] = &alloc_sys; - hal->make_pde(pde_bits, phys_allocs, 0, NULL); + hal->make_pde(pde_bits, phys_allocs, 0); TEST_CHECK_RET(pde_bits[0] == 0x3999999999990C); phys_allocs[0] = &alloc_vid; - hal->make_pde(pde_bits, phys_allocs, 0, NULL); + hal->make_pde(pde_bits, phys_allocs, 0); TEST_CHECK_RET(pde_bits[0] == 0x1BBBBBB0A); // Dual PDEs phys_allocs[0] = &alloc_big_sys; phys_allocs[1] = &alloc_vid; - hal->make_pde(pde_bits, phys_allocs, 3, NULL); + hal->make_pde(pde_bits, phys_allocs, 3); TEST_CHECK_RET(pde_bits[0] == 0x3999999999999C && pde_bits[1] == 0x1BBBBBB0A); phys_allocs[0] = &alloc_big_vid; phys_allocs[1] = &alloc_sys; - hal->make_pde(pde_bits, phys_allocs, 3, NULL); + hal->make_pde(pde_bits, phys_allocs, 3); TEST_CHECK_RET(pde_bits[0] == 0x1BBBBBBBA && pde_bits[1] == 0x3999999999990C); // NO_ATS PDE1 (depth 2) phys_allocs[0] = &alloc_vid; - hal->make_pde(pde_bits, phys_allocs, 2, NULL); + hal->make_pde(pde_bits, phys_allocs, 2); if (g_uvm_global.ats.enabled) TEST_CHECK_RET(pde_bits[0] == 0x1BBBBBB2A); else @@ -1840,32 +1805,32 @@ static NV_STATUS entry_test_hopper(uvm_gpu_t *gpu, entry_test_page_size_func ent uvm_mmu_mode_hal_t *hal = gpu->parent->arch_hal->mmu_mode_hal(UVM_PAGE_SIZE_64K); // Make sure cleared PDEs work as expected - hal->make_pde(pde_bits, phys_allocs, 0, NULL); + hal->make_pde(pde_bits, phys_allocs, 0); TEST_CHECK_RET(pde_bits[0] == 0); // Cleared PDEs work as expected for big and small PDEs. memset(pde_bits, 0xFF, sizeof(pde_bits)); - hal->make_pde(pde_bits, phys_allocs, 4, NULL); + hal->make_pde(pde_bits, phys_allocs, 4); TEST_CHECK_RET(pde_bits[0] == 0 && pde_bits[1] == 0); // Sys and vidmem PDEs, uncached ATS allowed. phys_allocs[0] = &alloc_sys; - hal->make_pde(pde_bits, phys_allocs, 0, NULL); + hal->make_pde(pde_bits, phys_allocs, 0); TEST_CHECK_RET(pde_bits[0] == 0x999999999900C); phys_allocs[0] = &alloc_vid; - hal->make_pde(pde_bits, phys_allocs, 0, NULL); + hal->make_pde(pde_bits, phys_allocs, 0); TEST_CHECK_RET(pde_bits[0] == 0xBBBBBBB00A); // Dual PDEs, uncached. phys_allocs[0] = &alloc_big_sys; phys_allocs[1] = &alloc_vid; - hal->make_pde(pde_bits, phys_allocs, 4, NULL); + hal->make_pde(pde_bits, phys_allocs, 4); TEST_CHECK_RET(pde_bits[0] == 0x999999999991C && pde_bits[1] == 0xBBBBBBB01A); phys_allocs[0] = &alloc_big_vid; phys_allocs[1] = &alloc_sys; - hal->make_pde(pde_bits, phys_allocs, 4, NULL); + hal->make_pde(pde_bits, phys_allocs, 4); TEST_CHECK_RET(pde_bits[0] == 0xBBBBBBBB1A && pde_bits[1] == 0x999999999901C); // uncached, i.e., the sysmem data is not cached in GPU's L2 cache, and @@ -2338,8 +2303,7 @@ NV_STATUS uvm_test_page_tree(UVM_TEST_PAGE_TREE_PARAMS *params, struct file *fil gpu->parent = parent_gpu; // At least test_tlb_invalidates() relies on global state - // (g_tlb_invalidate_*) so make sure only one test instance can run at a - // time. + // (g_tlb_invalidate_*) so make sure only one test instance can run at a time. uvm_mutex_lock(&g_uvm_global.global_lock); // Allocate the fake TLB tracking state. Notably tests still need to enable diff --git a/kernel-open/nvidia-uvm/uvm_pascal_mmu.c b/kernel-open/nvidia-uvm/uvm_pascal_mmu.c index cb77178dbc..8b17319e9a 100644 --- a/kernel-open/nvidia-uvm/uvm_pascal_mmu.c +++ b/kernel-open/nvidia-uvm/uvm_pascal_mmu.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2023 NVIDIA Corporation + Copyright (c) 2015-2020 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -140,10 +140,7 @@ static NvU64 small_half_pde_pascal(uvm_mmu_page_table_alloc_t *phys_alloc) return pde_bits; } -static void make_pde_pascal(void *entry, - uvm_mmu_page_table_alloc_t **phys_allocs, - NvU32 depth, - uvm_page_directory_t *child_dir) +static void make_pde_pascal(void *entry, uvm_mmu_page_table_alloc_t **phys_allocs, NvU32 depth) { NvU32 entry_count = entries_per_index_pascal(depth); NvU64 *entry_bits = (NvU64 *)entry; diff --git a/kernel-open/nvidia-uvm/uvm_perf_events_test.c b/kernel-open/nvidia-uvm/uvm_perf_events_test.c index c91adee3a6..2b1e8ae173 100644 --- a/kernel-open/nvidia-uvm/uvm_perf_events_test.c +++ b/kernel-open/nvidia-uvm/uvm_perf_events_test.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2019 NVIDIA Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -22,10 +22,7 @@ *******************************************************************************/ #include "uvm_perf_events.h" -#include "uvm_va_block.h" -#include "uvm_va_range.h" #include "uvm_va_space.h" -#include "uvm_kvmalloc.h" #include "uvm_test.h" // Global variable used to check that callbacks are correctly executed @@ -46,10 +43,7 @@ static NV_STATUS test_events(uvm_va_space_t *va_space) NV_STATUS status; uvm_perf_event_data_t event_data; - uvm_va_block_t block; - test_data = 0; - memset(&event_data, 0, sizeof(event_data)); // Use CPU id to avoid triggering the GPU stats update code @@ -58,6 +52,7 @@ static NV_STATUS test_events(uvm_va_space_t *va_space) // Register a callback for page fault status = uvm_perf_register_event_callback(&va_space->perf_events, UVM_PERF_EVENT_FAULT, callback_inc_1); TEST_CHECK_GOTO(status == NV_OK, done); + // Register a callback for page fault status = uvm_perf_register_event_callback(&va_space->perf_events, UVM_PERF_EVENT_FAULT, callback_inc_2); TEST_CHECK_GOTO(status == NV_OK, done); @@ -65,13 +60,14 @@ static NV_STATUS test_events(uvm_va_space_t *va_space) // va_space read lock is required for page fault event notification uvm_va_space_down_read(va_space); - // Notify (fake) page fault. The two registered callbacks for this event increment the value of test_value - event_data.fault.block = █ + // Notify (fake) page fault. The two registered callbacks for this event + // increment the value of test_value uvm_perf_event_notify(&va_space->perf_events, UVM_PERF_EVENT_FAULT, &event_data); uvm_va_space_up_read(va_space); - // test_data was initialized to zero. It should have been incremented by 1 and 2, respectively in the callbacks + // test_data was initialized to zero. It should have been incremented by 1 + // and 2, respectively in the callbacks TEST_CHECK_GOTO(test_data == 3, done); done: @@ -96,4 +92,3 @@ NV_STATUS uvm_test_perf_events_sanity(UVM_TEST_PERF_EVENTS_SANITY_PARAMS *params done: return status; } - diff --git a/kernel-open/nvidia-uvm/uvm_perf_prefetch.c b/kernel-open/nvidia-uvm/uvm_perf_prefetch.c index 451866b482..fd3e003a64 100644 --- a/kernel-open/nvidia-uvm/uvm_perf_prefetch.c +++ b/kernel-open/nvidia-uvm/uvm_perf_prefetch.c @@ -355,7 +355,7 @@ static NvU32 uvm_perf_prefetch_prenotify_fault_migrations(uvm_va_block_t *va_blo uvm_page_mask_zero(prefetch_pages); if (UVM_ID_IS_CPU(new_residency) || va_block->gpus[uvm_id_gpu_index(new_residency)] != NULL) - resident_mask = uvm_va_block_resident_mask_get(va_block, new_residency); + resident_mask = uvm_va_block_resident_mask_get(va_block, new_residency, NUMA_NO_NODE); // If this is a first-touch fault and the destination processor is the // preferred location, populate the whole max_prefetch_region. diff --git a/kernel-open/nvidia-uvm/uvm_perf_thrashing.c b/kernel-open/nvidia-uvm/uvm_perf_thrashing.c index ee5eef43b8..8eb27f0483 100644 --- a/kernel-open/nvidia-uvm/uvm_perf_thrashing.c +++ b/kernel-open/nvidia-uvm/uvm_perf_thrashing.c @@ -164,7 +164,7 @@ typedef struct uvm_spinlock_t lock; - uvm_va_block_context_t va_block_context; + uvm_va_block_context_t *va_block_context; // Flag used to avoid scheduling delayed unpinning operations after // uvm_perf_thrashing_stop has been called. @@ -601,6 +601,14 @@ static va_space_thrashing_info_t *va_space_thrashing_info_create(uvm_va_space_t va_space_thrashing = uvm_kvmalloc_zero(sizeof(*va_space_thrashing)); if (va_space_thrashing) { + uvm_va_block_context_t *block_context = uvm_va_block_context_alloc(NULL); + + if (!block_context) { + uvm_kvfree(va_space_thrashing); + return NULL; + } + + va_space_thrashing->pinned_pages.va_block_context = block_context; va_space_thrashing->va_space = va_space; va_space_thrashing_info_init_params(va_space_thrashing); @@ -621,6 +629,7 @@ static void va_space_thrashing_info_destroy(uvm_va_space_t *va_space) if (va_space_thrashing) { uvm_perf_module_type_unset_data(va_space->perf_modules_data, UVM_PERF_MODULE_TYPE_THRASHING); + uvm_va_block_context_free(va_space_thrashing->pinned_pages.va_block_context); uvm_kvfree(va_space_thrashing); } } @@ -1104,7 +1113,7 @@ static NV_STATUS unmap_remote_pinned_pages(uvm_va_block_t *va_block, !uvm_processor_mask_test(&policy->accessed_by, processor_id)); if (uvm_processor_mask_test(&va_block->resident, processor_id)) { - const uvm_page_mask_t *resident_mask = uvm_va_block_resident_mask_get(va_block, processor_id); + const uvm_page_mask_t *resident_mask = uvm_va_block_resident_mask_get(va_block, processor_id, NUMA_NO_NODE); if (!uvm_page_mask_andnot(&va_block_context->caller_page_mask, &block_thrashing->pinned_pages.mask, @@ -1312,9 +1321,8 @@ void thrashing_event_cb(uvm_perf_event_t event_id, uvm_perf_event_data_t *event_ if (block_thrashing->last_time_stamp == 0 || uvm_id_equal(block_thrashing->last_processor, processor_id) || - time_stamp - block_thrashing->last_time_stamp > va_space_thrashing->params.lapse_ns) { + time_stamp - block_thrashing->last_time_stamp > va_space_thrashing->params.lapse_ns) goto done; - } num_block_pages = uvm_va_block_size(va_block) / PAGE_SIZE; @@ -1803,7 +1811,7 @@ static void thrashing_unpin_pages(struct work_struct *work) struct delayed_work *dwork = to_delayed_work(work); va_space_thrashing_info_t *va_space_thrashing = container_of(dwork, va_space_thrashing_info_t, pinned_pages.dwork); uvm_va_space_t *va_space = va_space_thrashing->va_space; - uvm_va_block_context_t *va_block_context = &va_space_thrashing->pinned_pages.va_block_context; + uvm_va_block_context_t *va_block_context = va_space_thrashing->pinned_pages.va_block_context; // Take the VA space lock so that VA blocks don't go away during this // operation. @@ -1937,7 +1945,6 @@ void uvm_perf_thrashing_unload(uvm_va_space_t *va_space) // Make sure that there are not pending work items if (va_space_thrashing) { - UVM_ASSERT(va_space_thrashing->pinned_pages.in_va_space_teardown); UVM_ASSERT(list_empty(&va_space_thrashing->pinned_pages.list)); va_space_thrashing_info_destroy(va_space); diff --git a/kernel-open/nvidia-uvm/uvm_pmm_gpu.c b/kernel-open/nvidia-uvm/uvm_pmm_gpu.c index 4e573185d5..9ff2d63f73 100644 --- a/kernel-open/nvidia-uvm/uvm_pmm_gpu.c +++ b/kernel-open/nvidia-uvm/uvm_pmm_gpu.c @@ -3377,76 +3377,47 @@ uvm_gpu_id_t uvm_pmm_devmem_page_to_gpu_id(struct page *page) return gpu->id; } -static void evict_orphan_pages(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk) -{ - NvU32 i; - - UVM_ASSERT(chunk->state == UVM_PMM_GPU_CHUNK_STATE_IS_SPLIT); - UVM_ASSERT(chunk->suballoc); - - for (i = 0; i < num_subchunks(chunk); i++) { - uvm_gpu_chunk_t *subchunk = chunk->suballoc->subchunks[i]; - - uvm_spin_lock(&pmm->list_lock); - - if (subchunk->state == UVM_PMM_GPU_CHUNK_STATE_IS_SPLIT) { - uvm_spin_unlock(&pmm->list_lock); - - evict_orphan_pages(pmm, subchunk); - continue; - } - - if (subchunk->state == UVM_PMM_GPU_CHUNK_STATE_ALLOCATED && subchunk->is_referenced) { - unsigned long pfn = uvm_pmm_gpu_devmem_get_pfn(pmm, subchunk); - - // TODO: Bug 3368756: add support for large GPU pages. - UVM_ASSERT(uvm_gpu_chunk_get_size(subchunk) == PAGE_SIZE); - uvm_spin_unlock(&pmm->list_lock); - - // The above check for subchunk state is racy because the - // chunk may be freed after the lock is dropped. It is - // still safe to proceed in that case because the struct - // page reference will have dropped to zero and cannot - // have been re-allocated as this is only called during - // GPU teardown. Therefore migrate_device_range() will - // simply fail. - uvm_hmm_pmm_gpu_evict_pfn(pfn); - continue; - } - - uvm_spin_unlock(&pmm->list_lock); - } -} - -// Free any orphan pages. -// This should be called as part of removing a GPU: after all work is stopped -// and all va_blocks have been destroyed. There normally won't be any -// device private struct page references left but there can be cases after -// fork() where a child process still holds a reference. This function searches -// for pages that still have a reference and migrates the page to the GPU in -// order to release the reference in the CPU page table. -static void uvm_pmm_gpu_free_orphan_pages(uvm_pmm_gpu_t *pmm) +// Check there are no orphan pages. This should be only called as part of +// removing a GPU: after all work is stopped and all va_blocks have been +// destroyed. By now there should be no device-private page references left as +// there are no va_space's left on this GPU and orphan pages should be removed +// by va_space destruction or unregistration from the GPU. +static bool uvm_pmm_gpu_check_orphan_pages(uvm_pmm_gpu_t *pmm) { size_t i; + bool ret = true; + unsigned long pfn; + struct range range = pmm->devmem.pagemap.range; - if (!pmm->initialized) - return; - - // This is only safe to call during GPU teardown where chunks - // cannot be re-allocated. - UVM_ASSERT(uvm_gpu_retained_count(uvm_pmm_to_gpu(pmm)) == 0); + if (!pmm->initialized || !uvm_hmm_is_enabled_system_wide()) + return ret; // Scan all the root chunks looking for subchunks which are still - // referenced. This is slow, but we only do this when unregistering a GPU - // and is not critical for performance. + // referenced. for (i = 0; i < pmm->root_chunks.count; i++) { uvm_gpu_root_chunk_t *root_chunk = &pmm->root_chunks.array[i]; root_chunk_lock(pmm, root_chunk); if (root_chunk->chunk.state == UVM_PMM_GPU_CHUNK_STATE_IS_SPLIT) - evict_orphan_pages(pmm, &root_chunk->chunk); + ret = false; root_chunk_unlock(pmm, root_chunk); } + + for (pfn = __phys_to_pfn(range.start); pfn <= __phys_to_pfn(range.end); pfn++) { + struct page *page = pfn_to_page(pfn); + + if (!is_device_private_page(page)) { + ret = false; + break; + } + + if (page_count(page)) { + ret = false; + break; + } + } + + return ret; } static void devmem_page_free(struct page *page) @@ -3479,7 +3450,7 @@ static vm_fault_t devmem_fault(struct vm_fault *vmf) { uvm_va_space_t *va_space = vmf->page->zone_device_data; - if (!va_space || va_space->va_space_mm.mm != vmf->vma->vm_mm) + if (!va_space) return VM_FAULT_SIGBUS; return uvm_va_space_cpu_fault_hmm(va_space, vmf->vma, vmf); @@ -3568,8 +3539,9 @@ static void devmem_deinit(uvm_pmm_gpu_t *pmm) { } -static void uvm_pmm_gpu_free_orphan_pages(uvm_pmm_gpu_t *pmm) +static bool uvm_pmm_gpu_check_orphan_pages(uvm_pmm_gpu_t *pmm) { + return true; } #endif // UVM_IS_CONFIG_HMM() @@ -3744,7 +3716,7 @@ void uvm_pmm_gpu_deinit(uvm_pmm_gpu_t *pmm) gpu = uvm_pmm_to_gpu(pmm); - uvm_pmm_gpu_free_orphan_pages(pmm); + UVM_ASSERT(uvm_pmm_gpu_check_orphan_pages(pmm)); nv_kthread_q_flush(&gpu->parent->lazy_free_q); UVM_ASSERT(list_empty(&pmm->root_chunks.va_block_lazy_free)); release_free_root_chunks(pmm); diff --git a/kernel-open/nvidia-uvm/uvm_pmm_sysmem.c b/kernel-open/nvidia-uvm/uvm_pmm_sysmem.c index 7e843282c6..f6a48c2e5b 100644 --- a/kernel-open/nvidia-uvm/uvm_pmm_sysmem.c +++ b/kernel-open/nvidia-uvm/uvm_pmm_sysmem.c @@ -749,6 +749,7 @@ NV_STATUS uvm_cpu_chunk_map_gpu(uvm_cpu_chunk_t *chunk, uvm_gpu_t *gpu) } static struct page *uvm_cpu_chunk_alloc_page(uvm_chunk_size_t alloc_size, + int nid, uvm_cpu_chunk_alloc_flags_t alloc_flags) { gfp_t kernel_alloc_flags; @@ -764,18 +765,27 @@ static struct page *uvm_cpu_chunk_alloc_page(uvm_chunk_size_t alloc_size, kernel_alloc_flags |= GFP_HIGHUSER; - // For allocation sizes higher than PAGE_SIZE, use __GFP_NORETRY in - // order to avoid higher allocation latency from the kernel compacting - // memory to satisfy the request. + // For allocation sizes higher than PAGE_SIZE, use __GFP_NORETRY in order + // to avoid higher allocation latency from the kernel compacting memory to + // satisfy the request. + // Use __GFP_NOWARN to avoid printing allocation failure to the kernel log. + // High order allocation failures are handled gracefully by the caller. if (alloc_size > PAGE_SIZE) - kernel_alloc_flags |= __GFP_COMP | __GFP_NORETRY; + kernel_alloc_flags |= __GFP_COMP | __GFP_NORETRY | __GFP_NOWARN; if (alloc_flags & UVM_CPU_CHUNK_ALLOC_FLAGS_ZERO) kernel_alloc_flags |= __GFP_ZERO; - page = alloc_pages(kernel_alloc_flags, get_order(alloc_size)); - if (page && (alloc_flags & UVM_CPU_CHUNK_ALLOC_FLAGS_ZERO)) - SetPageDirty(page); + UVM_ASSERT(nid < num_online_nodes()); + if (nid == NUMA_NO_NODE) + page = alloc_pages(kernel_alloc_flags, get_order(alloc_size)); + else + page = alloc_pages_node(nid, kernel_alloc_flags, get_order(alloc_size)); + + if (page) { + if (alloc_flags & UVM_CPU_CHUNK_ALLOC_FLAGS_ZERO) + SetPageDirty(page); + } return page; } @@ -805,6 +815,7 @@ static uvm_cpu_physical_chunk_t *uvm_cpu_chunk_create(uvm_chunk_size_t alloc_siz NV_STATUS uvm_cpu_chunk_alloc(uvm_chunk_size_t alloc_size, uvm_cpu_chunk_alloc_flags_t alloc_flags, + int nid, uvm_cpu_chunk_t **new_chunk) { uvm_cpu_physical_chunk_t *chunk; @@ -812,7 +823,7 @@ NV_STATUS uvm_cpu_chunk_alloc(uvm_chunk_size_t alloc_size, UVM_ASSERT(new_chunk); - page = uvm_cpu_chunk_alloc_page(alloc_size, alloc_flags); + page = uvm_cpu_chunk_alloc_page(alloc_size, nid, alloc_flags); if (!page) return NV_ERR_NO_MEMORY; @@ -847,6 +858,13 @@ NV_STATUS uvm_cpu_chunk_alloc_hmm(struct page *page, return NV_OK; } +int uvm_cpu_chunk_get_numa_node(uvm_cpu_chunk_t *chunk) +{ + UVM_ASSERT(chunk); + UVM_ASSERT(chunk->page); + return page_to_nid(chunk->page); +} + NV_STATUS uvm_cpu_chunk_split(uvm_cpu_chunk_t *chunk, uvm_cpu_chunk_t **new_chunks) { NV_STATUS status = NV_OK; diff --git a/kernel-open/nvidia-uvm/uvm_pmm_sysmem.h b/kernel-open/nvidia-uvm/uvm_pmm_sysmem.h index a09a003b70..f2fd4d90bf 100644 --- a/kernel-open/nvidia-uvm/uvm_pmm_sysmem.h +++ b/kernel-open/nvidia-uvm/uvm_pmm_sysmem.h @@ -304,11 +304,24 @@ uvm_chunk_sizes_mask_t uvm_cpu_chunk_get_allocation_sizes(void); // Allocate a physical CPU chunk of the specified size. // +// The nid argument is used to indicate a memory node preference. If the +// value is a memory node ID, the chunk allocation will be attempted on +// that memory node. If the chunk cannot be allocated on that memory node, +// it will be allocated on any memory node allowed by the process's policy. +// +// If the value of nid is a memory node ID that is not in the set of +// current process's allowed memory nodes, it will be allocated on one of the +// nodes in the allowed set. +// +// If the value of nid is NUMA_NO_NODE, the chunk will be allocated from any +// of the allowed memory nodes by the process policy. +// // If a CPU chunk allocation succeeds, NV_OK is returned. new_chunk will be set // to point to the newly allocated chunk. On failure, NV_ERR_NO_MEMORY is // returned. NV_STATUS uvm_cpu_chunk_alloc(uvm_chunk_size_t alloc_size, uvm_cpu_chunk_alloc_flags_t flags, + int nid, uvm_cpu_chunk_t **new_chunk); // Allocate a HMM CPU chunk. @@ -375,6 +388,9 @@ static uvm_cpu_logical_chunk_t *uvm_cpu_chunk_to_logical(uvm_cpu_chunk_t *chunk) return container_of((chunk), uvm_cpu_logical_chunk_t, common); } +// Return the NUMA node ID of the physical page backing the chunk. +int uvm_cpu_chunk_get_numa_node(uvm_cpu_chunk_t *chunk); + // Free a CPU chunk. // This may not result in the immediate freeing of the physical pages of the // chunk if this is a logical chunk and there are other logical chunks holding diff --git a/kernel-open/nvidia-uvm/uvm_pmm_sysmem_test.c b/kernel-open/nvidia-uvm/uvm_pmm_sysmem_test.c index ec4a630dc3..71e06020c3 100644 --- a/kernel-open/nvidia-uvm/uvm_pmm_sysmem_test.c +++ b/kernel-open/nvidia-uvm/uvm_pmm_sysmem_test.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2017-2019 NVIDIA Corporation + Copyright (c) 2017-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -664,6 +664,7 @@ static NV_STATUS test_cpu_chunk_mapping_access(uvm_cpu_chunk_t *chunk, uvm_gpu_t static NV_STATUS test_cpu_chunk_alloc(uvm_chunk_size_t size, uvm_cpu_chunk_alloc_flags_t flags, + int nid, uvm_cpu_chunk_t **out_chunk) { uvm_cpu_chunk_t *chunk; @@ -675,7 +676,7 @@ static NV_STATUS test_cpu_chunk_alloc(uvm_chunk_size_t size, // It is possible that the allocation fails due to lack of large pages // rather than an API issue, which will result in a false negative. // However, that should be very rare. - TEST_NV_CHECK_RET(uvm_cpu_chunk_alloc(size, flags, &chunk)); + TEST_NV_CHECK_RET(uvm_cpu_chunk_alloc(size, flags, nid, &chunk)); // Check general state of the chunk: // - chunk should be a physical chunk, @@ -685,6 +686,12 @@ static NV_STATUS test_cpu_chunk_alloc(uvm_chunk_size_t size, TEST_CHECK_GOTO(uvm_cpu_chunk_get_size(chunk) == size, done); TEST_CHECK_GOTO(uvm_cpu_chunk_num_pages(chunk) == size / PAGE_SIZE, done); + // It is possible for the kernel to allocate a chunk on a NUMA node other + // than the one requested. However, that should not be an issue with + // sufficient memory on each NUMA node. + if (nid != NUMA_NO_NODE) + TEST_CHECK_GOTO(uvm_cpu_chunk_get_numa_node(chunk) == nid, done); + if (flags & UVM_CPU_CHUNK_ALLOC_FLAGS_ZERO) { NvU64 *cpu_addr; @@ -719,7 +726,7 @@ static NV_STATUS test_cpu_chunk_mapping_basic_verify(uvm_gpu_t *gpu, NvU64 dma_addr; NV_STATUS status = NV_OK; - TEST_NV_CHECK_RET(test_cpu_chunk_alloc(size, flags, &chunk)); + TEST_NV_CHECK_RET(test_cpu_chunk_alloc(size, flags, NUMA_NO_NODE, &chunk)); phys_chunk = uvm_cpu_chunk_to_physical(chunk); // Check state of the physical chunk: @@ -763,27 +770,27 @@ static NV_STATUS test_cpu_chunk_mapping_basic(uvm_gpu_t *gpu, uvm_cpu_chunk_allo return NV_OK; } -static NV_STATUS test_cpu_chunk_mapping_array(uvm_gpu_t *gpu1, uvm_gpu_t *gpu2, uvm_gpu_t *gpu3) +static NV_STATUS test_cpu_chunk_mapping_array(uvm_gpu_t *gpu0, uvm_gpu_t *gpu1, uvm_gpu_t *gpu2) { NV_STATUS status = NV_OK; uvm_cpu_chunk_t *chunk; uvm_cpu_physical_chunk_t *phys_chunk; - NvU64 dma_addr_gpu2; + NvU64 dma_addr_gpu1; - TEST_NV_CHECK_RET(test_cpu_chunk_alloc(PAGE_SIZE, UVM_CPU_CHUNK_ALLOC_FLAGS_NONE, &chunk)); + TEST_NV_CHECK_RET(test_cpu_chunk_alloc(PAGE_SIZE, UVM_CPU_CHUNK_ALLOC_FLAGS_NONE, NUMA_NO_NODE, &chunk)); phys_chunk = uvm_cpu_chunk_to_physical(chunk); - TEST_NV_CHECK_GOTO(uvm_cpu_chunk_map_gpu(chunk, gpu2), done); - TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(chunk, gpu2), done); - TEST_NV_CHECK_GOTO(uvm_cpu_chunk_map_gpu(chunk, gpu3), done); - TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(chunk, gpu2), done); - TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(chunk, gpu3), done); - dma_addr_gpu2 = uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu2->parent); - uvm_cpu_chunk_unmap_gpu_phys(chunk, gpu3->parent); - TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(chunk, gpu2), done); TEST_NV_CHECK_GOTO(uvm_cpu_chunk_map_gpu(chunk, gpu1), done); TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(chunk, gpu1), done); + TEST_NV_CHECK_GOTO(uvm_cpu_chunk_map_gpu(chunk, gpu2), done); + TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(chunk, gpu1), done); TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(chunk, gpu2), done); + dma_addr_gpu1 = uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu1->parent); + uvm_cpu_chunk_unmap_gpu_phys(chunk, gpu2->parent); + TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(chunk, gpu1), done); + TEST_NV_CHECK_GOTO(uvm_cpu_chunk_map_gpu(chunk, gpu0), done); + TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(chunk, gpu0), done); + TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(chunk, gpu1), done); // DMA mapping addresses for different GPUs live in different IOMMU spaces, // so it would be perfectly legal for them to have the same IOVA, and even @@ -793,7 +800,7 @@ static NV_STATUS test_cpu_chunk_mapping_array(uvm_gpu_t *gpu1, uvm_gpu_t *gpu2, // GPU1. It's true that we may get a false negative if both addresses // happened to alias and we had a bug in how the addresses are shifted in // the dense array, but that's better than intermittent failure. - TEST_CHECK_GOTO(uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu2->parent) == dma_addr_gpu2, done); + TEST_CHECK_GOTO(uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu1->parent) == dma_addr_gpu1, done); done: uvm_cpu_chunk_free(chunk); @@ -911,7 +918,7 @@ static NV_STATUS test_cpu_chunk_split_and_merge(uvm_gpu_t *gpu) uvm_cpu_chunk_t *chunk; NV_STATUS status; - TEST_NV_CHECK_RET(test_cpu_chunk_alloc(size, UVM_CPU_CHUNK_ALLOC_FLAGS_NONE, &chunk)); + TEST_NV_CHECK_RET(test_cpu_chunk_alloc(size, UVM_CPU_CHUNK_ALLOC_FLAGS_NONE, NUMA_NO_NODE, &chunk)); status = do_test_cpu_chunk_split_and_merge(chunk, gpu); uvm_cpu_chunk_free(chunk); @@ -993,7 +1000,7 @@ static NV_STATUS test_cpu_chunk_dirty(uvm_gpu_t *gpu) uvm_cpu_physical_chunk_t *phys_chunk; size_t num_pages; - TEST_NV_CHECK_RET(test_cpu_chunk_alloc(size, UVM_CPU_CHUNK_ALLOC_FLAGS_NONE, &chunk)); + TEST_NV_CHECK_RET(test_cpu_chunk_alloc(size, UVM_CPU_CHUNK_ALLOC_FLAGS_NONE, NUMA_NO_NODE, &chunk)); phys_chunk = uvm_cpu_chunk_to_physical(chunk); num_pages = uvm_cpu_chunk_num_pages(chunk); @@ -1005,7 +1012,7 @@ static NV_STATUS test_cpu_chunk_dirty(uvm_gpu_t *gpu) uvm_cpu_chunk_free(chunk); - TEST_NV_CHECK_RET(test_cpu_chunk_alloc(size, UVM_CPU_CHUNK_ALLOC_FLAGS_ZERO, &chunk)); + TEST_NV_CHECK_RET(test_cpu_chunk_alloc(size, UVM_CPU_CHUNK_ALLOC_FLAGS_ZERO, NUMA_NO_NODE, &chunk)); phys_chunk = uvm_cpu_chunk_to_physical(chunk); num_pages = uvm_cpu_chunk_num_pages(chunk); @@ -1170,13 +1177,35 @@ NV_STATUS test_cpu_chunk_free(uvm_va_space_t *va_space, uvm_processor_mask_t *te size_t size = uvm_chunk_find_next_size(alloc_sizes, PAGE_SIZE); for_each_chunk_size_from(size, alloc_sizes) { - TEST_NV_CHECK_RET(test_cpu_chunk_alloc(size, UVM_CPU_CHUNK_ALLOC_FLAGS_NONE, &chunk)); + TEST_NV_CHECK_RET(test_cpu_chunk_alloc(size, UVM_CPU_CHUNK_ALLOC_FLAGS_NONE, NUMA_NO_NODE, &chunk)); TEST_NV_CHECK_RET(do_test_cpu_chunk_free(chunk, va_space, test_gpus)); } return NV_OK; } +static NV_STATUS test_cpu_chunk_numa_alloc(uvm_va_space_t *va_space) +{ + uvm_cpu_chunk_t *chunk; + uvm_chunk_sizes_mask_t alloc_sizes = uvm_cpu_chunk_get_allocation_sizes(); + size_t size; + + for_each_chunk_size(size, alloc_sizes) { + int nid; + + for_each_possible_uvm_node(nid) { + // Do not test CPU allocation on nodes that have no memory or CPU + if (!node_state(nid, N_MEMORY) || !node_state(nid, N_CPU)) + continue; + + TEST_NV_CHECK_RET(test_cpu_chunk_alloc(size, UVM_CPU_CHUNK_ALLOC_FLAGS_NONE, nid, &chunk)); + uvm_cpu_chunk_free(chunk); + } + } + + return NV_OK; +} + NV_STATUS uvm_test_cpu_chunk_api(UVM_TEST_CPU_CHUNK_API_PARAMS *params, struct file *filp) { uvm_va_space_t *va_space = uvm_va_space_get(filp); @@ -1197,6 +1226,7 @@ NV_STATUS uvm_test_cpu_chunk_api(UVM_TEST_CPU_CHUNK_API_PARAMS *params, struct f } TEST_NV_CHECK_GOTO(test_cpu_chunk_free(va_space, &test_gpus), done); + TEST_NV_CHECK_GOTO(test_cpu_chunk_numa_alloc(va_space), done); if (uvm_processor_mask_get_gpu_count(&test_gpus) >= 3) { uvm_gpu_t *gpu2, *gpu3; diff --git a/kernel-open/nvidia-uvm/uvm_pmm_test.c b/kernel-open/nvidia-uvm/uvm_pmm_test.c index 4c1ee66799..ec49caada6 100644 --- a/kernel-open/nvidia-uvm/uvm_pmm_test.c +++ b/kernel-open/nvidia-uvm/uvm_pmm_test.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2023 NVIDIA Corporation + Copyright (c) 2015-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -324,7 +324,7 @@ static NV_STATUS gpu_mem_check(uvm_gpu_t *gpu, // TODO: Bug 3839176: [UVM][HCC][uvm_test] Update tests that assume GPU // engines can directly access sysmem - // Skip this test for now. To enable this test in Confidential Computing, + // Skip this test for now. To enable this test under SEV, // The GPU->CPU CE copy needs to be updated so it uses encryption when // CC is enabled. if (uvm_conf_computing_mode_enabled(gpu)) @@ -1068,7 +1068,7 @@ static NV_STATUS test_pmm_reverse_map_single(uvm_gpu_t *gpu, uvm_va_space_t *va_ uvm_mutex_lock(&va_block->lock); is_resident = uvm_processor_mask_test(&va_block->resident, gpu->id) && - uvm_page_mask_full(uvm_va_block_resident_mask_get(va_block, gpu->id)); + uvm_page_mask_full(uvm_va_block_resident_mask_get(va_block, gpu->id, NUMA_NO_NODE)); if (is_resident) phys_addr = uvm_va_block_gpu_phys_page_address(va_block, 0, gpu); @@ -1154,7 +1154,7 @@ static NV_STATUS test_pmm_reverse_map_many_blocks(uvm_gpu_t *gpu, uvm_va_space_t uvm_mutex_lock(&va_block->lock); // Verify that all pages are populated on the GPU - is_resident = uvm_page_mask_region_full(uvm_va_block_resident_mask_get(va_block, gpu->id), + is_resident = uvm_page_mask_region_full(uvm_va_block_resident_mask_get(va_block, gpu->id, NUMA_NO_NODE), reverse_mapping->region); uvm_mutex_unlock(&va_block->lock); @@ -1223,6 +1223,8 @@ static NV_STATUS test_indirect_peers(uvm_gpu_t *owning_gpu, uvm_gpu_t *accessing if (!chunks) return NV_ERR_NO_MEMORY; + UVM_ASSERT(!g_uvm_global.sev_enabled); + TEST_NV_CHECK_GOTO(uvm_mem_alloc_sysmem_and_map_cpu_kernel(UVM_CHUNK_SIZE_MAX, current->mm, &verif_mem), out); TEST_NV_CHECK_GOTO(uvm_mem_map_gpu_kernel(verif_mem, owning_gpu), out); TEST_NV_CHECK_GOTO(uvm_mem_map_gpu_kernel(verif_mem, accessing_gpu), out); diff --git a/kernel-open/nvidia-uvm/uvm_policy.c b/kernel-open/nvidia-uvm/uvm_policy.c index 09e86c31d4..17c0dabd82 100644 --- a/kernel-open/nvidia-uvm/uvm_policy.c +++ b/kernel-open/nvidia-uvm/uvm_policy.c @@ -176,7 +176,9 @@ static NV_STATUS preferred_location_unmap_remote_pages(uvm_va_block_t *va_block, mapped_mask = uvm_va_block_map_mask_get(va_block, preferred_location); if (uvm_processor_mask_test(&va_block->resident, preferred_location)) { - const uvm_page_mask_t *resident_mask = uvm_va_block_resident_mask_get(va_block, preferred_location); + const uvm_page_mask_t *resident_mask = uvm_va_block_resident_mask_get(va_block, + preferred_location, + NUMA_NO_NODE); if (!uvm_page_mask_andnot(&va_block_context->caller_page_mask, mapped_mask, resident_mask)) goto done; @@ -638,7 +640,7 @@ static NV_STATUS va_block_set_read_duplication_locked(uvm_va_block_t *va_block, for_each_id_in_mask(src_id, &va_block->resident) { NV_STATUS status; - uvm_page_mask_t *resident_mask = uvm_va_block_resident_mask_get(va_block, src_id); + uvm_page_mask_t *resident_mask = uvm_va_block_resident_mask_get(va_block, src_id, NUMA_NO_NODE); // Calling uvm_va_block_make_resident_read_duplicate will break all // SetAccessedBy and remote mappings @@ -695,7 +697,7 @@ static NV_STATUS va_block_unset_read_duplication_locked(uvm_va_block_t *va_block // If preferred_location is set and has resident copies, give it preference if (UVM_ID_IS_VALID(preferred_location) && uvm_processor_mask_test(&va_block->resident, preferred_location)) { - uvm_page_mask_t *resident_mask = uvm_va_block_resident_mask_get(va_block, preferred_location); + uvm_page_mask_t *resident_mask = uvm_va_block_resident_mask_get(va_block, preferred_location, NUMA_NO_NODE); bool is_mask_empty = !uvm_page_mask_and(break_read_duplication_pages, &va_block->read_duplicated_pages, resident_mask); @@ -723,7 +725,7 @@ static NV_STATUS va_block_unset_read_duplication_locked(uvm_va_block_t *va_block if (uvm_id_equal(processor_id, preferred_location)) continue; - resident_mask = uvm_va_block_resident_mask_get(va_block, processor_id); + resident_mask = uvm_va_block_resident_mask_get(va_block, processor_id, NUMA_NO_NODE); is_mask_empty = !uvm_page_mask_and(break_read_duplication_pages, &va_block->read_duplicated_pages, resident_mask); diff --git a/kernel-open/nvidia-uvm/uvm_processors.c b/kernel-open/nvidia-uvm/uvm_processors.c new file mode 100644 index 0000000000..6938959cc8 --- /dev/null +++ b/kernel-open/nvidia-uvm/uvm_processors.c @@ -0,0 +1,40 @@ +/******************************************************************************* + Copyright (c) 2023 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#include "uvm_processors.h" + +int uvm_find_closest_node_mask(int src, const nodemask_t *mask) +{ + int nid; + int closest_nid = NUMA_NO_NODE; + + if (node_isset(src, *mask)) + return src; + + for_each_set_bit(nid, mask->bits, MAX_NUMNODES) { + if (closest_nid == NUMA_NO_NODE || node_distance(src, nid) < node_distance(src, closest_nid)) + closest_nid = nid; + } + + return closest_nid; +} diff --git a/kernel-open/nvidia-uvm/uvm_processors.h b/kernel-open/nvidia-uvm/uvm_processors.h index 6ffd293c81..f6d2a5ed4f 100644 --- a/kernel-open/nvidia-uvm/uvm_processors.h +++ b/kernel-open/nvidia-uvm/uvm_processors.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2019 NVIDIA Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -26,6 +26,7 @@ #include "uvm_linux.h" #include "uvm_common.h" +#include #define UVM_MAX_UNIQUE_GPU_PAIRS SUM_FROM_0_TO_N(UVM_MAX_GPUS - 1) @@ -37,11 +38,11 @@ // provide type safety, they are wrapped within the uvm_processor_id_t struct. // The range of valid identifiers needs to cover the maximum number of // supported GPUs on a system plus the CPU. CPU is assigned value 0, and GPUs -// range: [1, UVM_ID_MAX_GPUS]. +// range: [1, UVM_PARENT_ID_MAX_GPUS]. // // There are some functions that only expect GPU identifiers and, in order to -// make it clearer, the uvm_gpu_id_t alias type is provided. However, as this -// type is just a typedef of uvm_processor_id_t, there is no type checking +// make it clearer, the uvm_parent_gpu_id_t alias type is provided. However, as +// this type is just a typedef of uvm_processor_id_t, there is no type checking // performed by the compiler. // // Identifier value vs index @@ -60,22 +61,25 @@ // the GPU within the GPU id space (basically id - 1). // // In the diagram below, MAX_SUB is used to abbreviate -// UVM_ID_MAX_SUB_PROCESSORS. +// UVM_PARENT_ID_MAX_SUB_PROCESSORS. // -// |-------------------------- uvm_processor_id_t ----------------------| -// | | -// | |----------------------- uvm_gpu_id_t ------------------------|| -// | | || -// Proc type | CPU | GPU ... GPU ... GPU || -// | | || -// ID values | 0 | 1 ... i+1 ... UVM_ID_MAX_PROCESSORS-1 || +// TODO: Bug 4195538: uvm_parent_processor_id_t is currently but temporarily the +// same as uvm_processor_id_t. // -// GPU index 0 ... i ... UVM_ID_MAX_GPUS-1 +// |-------------------------- uvm_parent_processor_id_t ----------------------| +// | | +// | |----------------------- uvm_parent_gpu_id_t ------------------------|| +// | | || +// Proc type | CPU | GPU ... GPU ... GPU || +// | | || +// ID values | 0 | 1 ... i+1 ... UVM_PARENT_ID_MAX_PROCESSORS-1 || +// +// GPU index 0 ... i ... UVM_PARENT_ID_MAX_GPUS-1 // | | | | // | | | | -// | |-------------| | |-----------------------------| -// | | | | -// | | | | +// | |-------------| | |------------------------------------| +// | | | | +// | | | | // GPU index 0 ... MAX_SUB-1 ... i*MAX_SUB ... (i+1)*MAX_SUB-1 ... UVM_GLOBAL_ID_MAX_GPUS-1 // // ID values | 0 | 1 ... MAX_SUB ... (i*MAX_SUB)+1 ... (i+1)*MAX_SUB ... UVM_GLOBAL_ID_MAX_PROCESSORS-1 || @@ -210,7 +214,7 @@ static proc_id_t prefix_fn_mask##_find_first_id(const mask_t *mask) \ static proc_id_t prefix_fn_mask##_find_first_gpu_id(const mask_t *mask) \ { \ - return proc_id_ctor(find_next_bit(mask->bitmap, (maxval), UVM_ID_GPU0_VALUE)); \ + return proc_id_ctor(find_next_bit(mask->bitmap, (maxval), UVM_PARENT_ID_GPU0_VALUE)); \ } \ \ static proc_id_t prefix_fn_mask##_find_next_id(const mask_t *mask, proc_id_t min_id) \ @@ -252,7 +256,7 @@ static NvU32 prefix_fn_mask##_get_gpu_count(const mask_t *mask) { \ NvU32 gpu_count = prefix_fn_mask##_get_count(mask); \ \ - if (prefix_fn_mask##_test(mask, proc_id_ctor(UVM_ID_CPU_VALUE))) \ + if (prefix_fn_mask##_test(mask, proc_id_ctor(UVM_PARENT_ID_CPU_VALUE))) \ --gpu_count; \ \ return gpu_count; \ @@ -261,55 +265,55 @@ static NvU32 prefix_fn_mask##_get_gpu_count(const mask_t *mask) typedef struct { NvU32 val; -} uvm_processor_id_t; +} uvm_parent_processor_id_t; typedef struct { NvU32 val; } uvm_global_processor_id_t; -typedef uvm_processor_id_t uvm_gpu_id_t; +typedef uvm_parent_processor_id_t uvm_parent_gpu_id_t; typedef uvm_global_processor_id_t uvm_global_gpu_id_t; // Static value assigned to the CPU -#define UVM_ID_CPU_VALUE 0 -#define UVM_ID_GPU0_VALUE (UVM_ID_CPU_VALUE + 1) +#define UVM_PARENT_ID_CPU_VALUE 0 +#define UVM_PARENT_ID_GPU0_VALUE (UVM_PARENT_ID_CPU_VALUE + 1) // ID values for the CPU and first GPU, respectively; the values for both types // of IDs must match to enable sharing of UVM_PROCESSOR_MASK(). -#define UVM_GLOBAL_ID_CPU_VALUE UVM_ID_CPU_VALUE -#define UVM_GLOBAL_ID_GPU0_VALUE UVM_ID_GPU0_VALUE +#define UVM_GLOBAL_ID_CPU_VALUE UVM_PARENT_ID_CPU_VALUE +#define UVM_GLOBAL_ID_GPU0_VALUE UVM_PARENT_ID_GPU0_VALUE // Maximum number of GPUs/processors that can be represented with the id types -#define UVM_ID_MAX_GPUS UVM_MAX_GPUS -#define UVM_ID_MAX_PROCESSORS UVM_MAX_PROCESSORS +#define UVM_PARENT_ID_MAX_GPUS UVM_MAX_GPUS +#define UVM_PARENT_ID_MAX_PROCESSORS UVM_MAX_PROCESSORS -#define UVM_ID_MAX_SUB_PROCESSORS 8 +#define UVM_PARENT_ID_MAX_SUB_PROCESSORS 8 -#define UVM_GLOBAL_ID_MAX_GPUS (UVM_MAX_GPUS * UVM_ID_MAX_SUB_PROCESSORS) +#define UVM_GLOBAL_ID_MAX_GPUS (UVM_PARENT_ID_MAX_GPUS * UVM_PARENT_ID_MAX_SUB_PROCESSORS) #define UVM_GLOBAL_ID_MAX_PROCESSORS (UVM_GLOBAL_ID_MAX_GPUS + 1) -#define UVM_ID_CPU ((uvm_processor_id_t) { .val = UVM_ID_CPU_VALUE }) -#define UVM_ID_INVALID ((uvm_processor_id_t) { .val = UVM_ID_MAX_PROCESSORS }) +#define UVM_PARENT_ID_CPU ((uvm_parent_processor_id_t) { .val = UVM_PARENT_ID_CPU_VALUE }) +#define UVM_PARENT_ID_INVALID ((uvm_parent_processor_id_t) { .val = UVM_PARENT_ID_MAX_PROCESSORS }) #define UVM_GLOBAL_ID_CPU ((uvm_global_processor_id_t) { .val = UVM_GLOBAL_ID_CPU_VALUE }) #define UVM_GLOBAL_ID_INVALID ((uvm_global_processor_id_t) { .val = UVM_GLOBAL_ID_MAX_PROCESSORS }) -#define UVM_ID_CHECK_BOUNDS(id) UVM_ASSERT_MSG(id.val <= UVM_ID_MAX_PROCESSORS, "id %u\n", id.val) +#define UVM_PARENT_ID_CHECK_BOUNDS(id) UVM_ASSERT_MSG(id.val <= UVM_PARENT_ID_MAX_PROCESSORS, "id %u\n", id.val) #define UVM_GLOBAL_ID_CHECK_BOUNDS(id) UVM_ASSERT_MSG(id.val <= UVM_GLOBAL_ID_MAX_PROCESSORS, "id %u\n", id.val) -static int uvm_id_cmp(uvm_processor_id_t id1, uvm_processor_id_t id2) +static int uvm_parent_id_cmp(uvm_parent_processor_id_t id1, uvm_parent_processor_id_t id2) { - UVM_ID_CHECK_BOUNDS(id1); - UVM_ID_CHECK_BOUNDS(id2); + UVM_PARENT_ID_CHECK_BOUNDS(id1); + UVM_PARENT_ID_CHECK_BOUNDS(id2); return UVM_CMP_DEFAULT(id1.val, id2.val); } -static bool uvm_id_equal(uvm_processor_id_t id1, uvm_processor_id_t id2) +static bool uvm_parent_id_equal(uvm_parent_processor_id_t id1, uvm_parent_processor_id_t id2) { - UVM_ID_CHECK_BOUNDS(id1); - UVM_ID_CHECK_BOUNDS(id2); + UVM_PARENT_ID_CHECK_BOUNDS(id1); + UVM_PARENT_ID_CHECK_BOUNDS(id2); return id1.val == id2.val; } @@ -330,30 +334,30 @@ static bool uvm_global_id_equal(uvm_global_processor_id_t id1, uvm_global_proces return id1.val == id2.val; } -#define UVM_ID_IS_CPU(id) uvm_id_equal(id, UVM_ID_CPU) -#define UVM_ID_IS_INVALID(id) uvm_id_equal(id, UVM_ID_INVALID) -#define UVM_ID_IS_VALID(id) (!UVM_ID_IS_INVALID(id)) -#define UVM_ID_IS_GPU(id) (!UVM_ID_IS_CPU(id) && !UVM_ID_IS_INVALID(id)) +#define UVM_PARENT_ID_IS_CPU(id) uvm_parent_id_equal(id, UVM_PARENT_ID_CPU) +#define UVM_PARENT_ID_IS_INVALID(id) uvm_parent_id_equal(id, UVM_PARENT_ID_INVALID) +#define UVM_PARENT_ID_IS_VALID(id) (!UVM_PARENT_ID_IS_INVALID(id)) +#define UVM_PARENT_ID_IS_GPU(id) (!UVM_PARENT_ID_IS_CPU(id) && !UVM_PARENT_ID_IS_INVALID(id)) #define UVM_GLOBAL_ID_IS_CPU(id) uvm_global_id_equal(id, UVM_GLOBAL_ID_CPU) #define UVM_GLOBAL_ID_IS_INVALID(id) uvm_global_id_equal(id, UVM_GLOBAL_ID_INVALID) #define UVM_GLOBAL_ID_IS_VALID(id) (!UVM_GLOBAL_ID_IS_INVALID(id)) #define UVM_GLOBAL_ID_IS_GPU(id) (!UVM_GLOBAL_ID_IS_CPU(id) && !UVM_GLOBAL_ID_IS_INVALID(id)) -static uvm_processor_id_t uvm_id_from_value(NvU32 val) +static uvm_parent_processor_id_t uvm_parent_id_from_value(NvU32 val) { - uvm_processor_id_t ret = { .val = val }; + uvm_parent_processor_id_t ret = { .val = val }; - UVM_ID_CHECK_BOUNDS(ret); + UVM_PARENT_ID_CHECK_BOUNDS(ret); return ret; } -static uvm_gpu_id_t uvm_gpu_id_from_value(NvU32 val) +static uvm_parent_gpu_id_t uvm_parent_gpu_id_from_value(NvU32 val) { - uvm_gpu_id_t ret = uvm_id_from_value(val); + uvm_parent_gpu_id_t ret = uvm_parent_id_from_value(val); - UVM_ASSERT(!UVM_ID_IS_CPU(ret)); + UVM_ASSERT(!UVM_PARENT_ID_IS_CPU(ret)); return ret; } @@ -376,34 +380,34 @@ static uvm_global_gpu_id_t uvm_global_gpu_id_from_value(NvU32 val) return ret; } -// Create a GPU id from the given GPU id index (previously obtained via -// uvm_id_gpu_index) -static uvm_gpu_id_t uvm_gpu_id_from_index(NvU32 index) +// Create a parent GPU id from the given parent GPU id index (previously +// obtained via uvm_parent_id_gpu_index) +static uvm_parent_gpu_id_t uvm_parent_gpu_id_from_index(NvU32 index) { - return uvm_gpu_id_from_value(index + UVM_ID_GPU0_VALUE); + return uvm_parent_gpu_id_from_value(index + UVM_PARENT_ID_GPU0_VALUE); } -static uvm_processor_id_t uvm_id_next(uvm_processor_id_t id) +static uvm_parent_processor_id_t uvm_parent_id_next(uvm_parent_processor_id_t id) { ++id.val; - UVM_ID_CHECK_BOUNDS(id); + UVM_PARENT_ID_CHECK_BOUNDS(id); return id; } -static uvm_gpu_id_t uvm_gpu_id_next(uvm_gpu_id_t id) +static uvm_parent_gpu_id_t uvm_parent_gpu_id_next(uvm_parent_gpu_id_t id) { - UVM_ASSERT(UVM_ID_IS_GPU(id)); + UVM_ASSERT(UVM_PARENT_ID_IS_GPU(id)); ++id.val; - UVM_ID_CHECK_BOUNDS(id); + UVM_PARENT_ID_CHECK_BOUNDS(id); return id; } -// Same as uvm_gpu_id_from_index but for uvm_global_processor_id_t +// Same as uvm_parent_gpu_id_from_index but for uvm_global_processor_id_t static uvm_global_gpu_id_t uvm_global_gpu_id_from_index(NvU32 index) { return uvm_global_gpu_id_from_value(index + UVM_GLOBAL_ID_GPU0_VALUE); @@ -429,11 +433,11 @@ static uvm_global_gpu_id_t uvm_global_gpu_id_next(uvm_global_gpu_id_t id) return id; } -// This function returns the numerical value within [0, UVM_ID_MAX_PROCESSORS) -// of the given processor id -static NvU32 uvm_id_value(uvm_processor_id_t id) +// This function returns the numerical value within +// [0, UVM_PARENT_ID_MAX_PROCESSORS) of the given parent processor id. +static NvU32 uvm_parent_id_value(uvm_parent_processor_id_t id) { - UVM_ASSERT(UVM_ID_IS_VALID(id)); + UVM_ASSERT(UVM_PARENT_ID_IS_VALID(id)); return id.val; } @@ -448,12 +452,12 @@ static NvU32 uvm_global_id_value(uvm_global_processor_id_t id) } // This function returns the index of the given GPU id within the GPU id space -// [0, UVM_ID_MAX_GPUS) -static NvU32 uvm_id_gpu_index(uvm_gpu_id_t id) +// [0, UVM_PARENT_ID_MAX_GPUS) +static NvU32 uvm_parent_id_gpu_index(uvm_parent_gpu_id_t id) { - UVM_ASSERT(UVM_ID_IS_GPU(id)); + UVM_ASSERT(UVM_PARENT_ID_IS_GPU(id)); - return id.val - UVM_ID_GPU0_VALUE; + return id.val - UVM_PARENT_ID_GPU0_VALUE; } // This function returns the index of the given GPU id within the GPU id space @@ -465,61 +469,61 @@ static NvU32 uvm_global_id_gpu_index(const uvm_global_gpu_id_t id) return id.val - UVM_GLOBAL_ID_GPU0_VALUE; } -static NvU32 uvm_global_id_gpu_index_from_gpu_id(const uvm_gpu_id_t id) +static NvU32 uvm_global_id_gpu_index_from_parent_gpu_id(const uvm_parent_gpu_id_t id) { - UVM_ASSERT(UVM_ID_IS_GPU(id)); + UVM_ASSERT(UVM_PARENT_ID_IS_GPU(id)); - return uvm_id_gpu_index(id) * UVM_ID_MAX_SUB_PROCESSORS; + return uvm_parent_id_gpu_index(id) * UVM_PARENT_ID_MAX_SUB_PROCESSORS; } -static NvU32 uvm_id_gpu_index_from_global_gpu_id(const uvm_global_gpu_id_t id) +static NvU32 uvm_parent_id_gpu_index_from_global_gpu_id(const uvm_global_gpu_id_t id) { UVM_ASSERT(UVM_GLOBAL_ID_IS_GPU(id)); - return uvm_global_id_gpu_index(id) / UVM_ID_MAX_SUB_PROCESSORS; + return uvm_global_id_gpu_index(id) / UVM_PARENT_ID_MAX_SUB_PROCESSORS; } -static uvm_global_gpu_id_t uvm_global_gpu_id_from_gpu_id(const uvm_gpu_id_t id) +static uvm_global_gpu_id_t uvm_global_gpu_id_from_parent_gpu_id(const uvm_parent_gpu_id_t id) { - UVM_ASSERT(UVM_ID_IS_GPU(id)); + UVM_ASSERT(UVM_PARENT_ID_IS_GPU(id)); - return uvm_global_gpu_id_from_index(uvm_global_id_gpu_index_from_gpu_id(id)); + return uvm_global_gpu_id_from_index(uvm_global_id_gpu_index_from_parent_gpu_id(id)); } static uvm_global_gpu_id_t uvm_global_gpu_id_from_parent_index(NvU32 index) { - UVM_ASSERT(index < UVM_MAX_GPUS); + UVM_ASSERT(index < UVM_PARENT_ID_MAX_GPUS); - return uvm_global_gpu_id_from_gpu_id(uvm_gpu_id_from_value(index + UVM_GLOBAL_ID_GPU0_VALUE)); + return uvm_global_gpu_id_from_parent_gpu_id(uvm_parent_gpu_id_from_value(index + UVM_GLOBAL_ID_GPU0_VALUE)); } -static uvm_global_gpu_id_t uvm_global_gpu_id_from_sub_processor_index(const uvm_gpu_id_t id, NvU32 sub_index) +static uvm_global_gpu_id_t uvm_global_gpu_id_from_sub_processor_index(const uvm_parent_gpu_id_t id, NvU32 sub_index) { NvU32 index; - UVM_ASSERT(sub_index < UVM_ID_MAX_SUB_PROCESSORS); + UVM_ASSERT(sub_index < UVM_PARENT_ID_MAX_SUB_PROCESSORS); - index = uvm_global_id_gpu_index_from_gpu_id(id) + sub_index; + index = uvm_global_id_gpu_index_from_parent_gpu_id(id) + sub_index; return uvm_global_gpu_id_from_index(index); } -static uvm_gpu_id_t uvm_gpu_id_from_global_gpu_id(const uvm_global_gpu_id_t id) +static uvm_parent_gpu_id_t uvm_parent_gpu_id_from_global_gpu_id(const uvm_global_gpu_id_t id) { UVM_ASSERT(UVM_GLOBAL_ID_IS_GPU(id)); - return uvm_gpu_id_from_index(uvm_id_gpu_index_from_global_gpu_id(id)); + return uvm_parent_gpu_id_from_index(uvm_parent_id_gpu_index_from_global_gpu_id(id)); } static NvU32 uvm_global_id_sub_processor_index(const uvm_global_gpu_id_t id) { - return uvm_global_id_gpu_index(id) % UVM_ID_MAX_SUB_PROCESSORS; + return uvm_global_id_gpu_index(id) % UVM_PARENT_ID_MAX_SUB_PROCESSORS; } UVM_PROCESSOR_MASK(uvm_processor_mask_t, \ uvm_processor_mask, \ - UVM_ID_MAX_PROCESSORS, \ - uvm_processor_id_t, \ - uvm_id_from_value) + UVM_PARENT_ID_MAX_PROCESSORS, \ + uvm_parent_processor_id_t, \ + uvm_parent_id_from_value) UVM_PROCESSOR_MASK(uvm_global_processor_mask_t, \ uvm_global_processor_mask, \ @@ -533,19 +537,19 @@ static bool uvm_processor_mask_gpu_subset(const uvm_processor_mask_t *subset, co { uvm_processor_mask_t subset_gpus; uvm_processor_mask_copy(&subset_gpus, subset); - uvm_processor_mask_clear(&subset_gpus, UVM_ID_CPU); + uvm_processor_mask_clear(&subset_gpus, UVM_PARENT_ID_CPU); return uvm_processor_mask_subset(&subset_gpus, mask); } #define for_each_id_in_mask(id, mask) \ for ((id) = uvm_processor_mask_find_first_id(mask); \ - UVM_ID_IS_VALID(id); \ - (id) = uvm_processor_mask_find_next_id((mask), uvm_id_next(id))) + UVM_PARENT_ID_IS_VALID(id); \ + (id) = uvm_processor_mask_find_next_id((mask), uvm_parent_id_next(id))) #define for_each_gpu_id_in_mask(gpu_id, mask) \ for ((gpu_id) = uvm_processor_mask_find_first_gpu_id((mask)); \ - UVM_ID_IS_VALID(gpu_id); \ - (gpu_id) = uvm_processor_mask_find_next_id((mask), uvm_gpu_id_next(gpu_id))) + UVM_PARENT_ID_IS_VALID(gpu_id); \ + (gpu_id) = uvm_processor_mask_find_next_id((mask), uvm_parent_gpu_id_next(gpu_id))) #define for_each_global_id_in_mask(id, mask) \ for ((id) = uvm_global_processor_mask_find_first_id(mask); \ @@ -559,21 +563,36 @@ static bool uvm_processor_mask_gpu_subset(const uvm_processor_mask_t *subset, co // Helper to iterate over all valid gpu ids #define for_each_gpu_id(i) \ - for (i = uvm_gpu_id_from_value(UVM_ID_GPU0_VALUE); UVM_ID_IS_VALID(i); i = uvm_gpu_id_next(i)) + for (i = uvm_parent_gpu_id_from_value(UVM_PARENT_ID_GPU0_VALUE); UVM_PARENT_ID_IS_VALID(i); i = uvm_parent_gpu_id_next(i)) #define for_each_global_gpu_id(i) \ for (i = uvm_global_gpu_id_from_value(UVM_GLOBAL_ID_GPU0_VALUE); UVM_GLOBAL_ID_IS_VALID(i); i = uvm_global_gpu_id_next(i)) #define for_each_global_sub_processor_id_in_gpu(id, i) \ - for (i = uvm_global_gpu_id_from_gpu_id(id); \ + for (i = uvm_global_gpu_id_from_parent_gpu_id(id); \ UVM_GLOBAL_ID_IS_VALID(i) && \ - (uvm_global_id_value(i) < uvm_global_id_value(uvm_global_gpu_id_from_gpu_id(id)) + UVM_ID_MAX_SUB_PROCESSORS); \ + (uvm_global_id_value(i) < uvm_global_id_value(uvm_global_gpu_id_from_parent_gpu_id(id)) + UVM_PARENT_ID_MAX_SUB_PROCESSORS); \ i = uvm_global_gpu_id_next(i)) // Helper to iterate over all valid gpu ids -#define for_each_processor_id(i) for (i = UVM_ID_CPU; UVM_ID_IS_VALID(i); i = uvm_id_next(i)) +#define for_each_processor_id(i) for (i = UVM_PARENT_ID_CPU; UVM_PARENT_ID_IS_VALID(i); i = uvm_parent_id_next(i)) #define for_each_global_id(i) for (i = UVM_GLOBAL_ID_CPU; UVM_GLOBAL_ID_IS_VALID(i); i = uvm_global_id_next(i)) +// Find the node in mask with the shorted distance (as returned by +// node_distance) for src. +// Note that the search is inclusive of src. +// If mask has no bits set, NUMA_NO_NODE is returned. +int uvm_find_closest_node_mask(int src, const nodemask_t *mask); + +// Iterate over all nodes in mask with increasing distance from src. +// Note that this iterator is destructive of the mask. +#define for_each_closest_uvm_node(nid, src, mask) \ + for ((nid) = uvm_find_closest_node_mask((src), &(mask)); \ + (nid) != NUMA_NO_NODE; \ + node_clear((nid), (mask)), (nid) = uvm_find_closest_node_mask((src), &(mask))) + +#define for_each_possible_uvm_node(nid) for_each_node_mask((nid), node_possible_map) + static bool uvm_processor_uuid_eq(const NvProcessorUuid *uuid1, const NvProcessorUuid *uuid2) { return memcmp(uuid1, uuid2, sizeof(*uuid1)) == 0; @@ -585,4 +604,78 @@ static void uvm_processor_uuid_copy(NvProcessorUuid *dst, const NvProcessorUuid memcpy(dst, src, sizeof(*dst)); } +// TODO: Bug 4195538: [uvm][multi-SMC] Get UVM internal data structures ready to +// meet multi-SMC requirements. Temporary aliases, they must be removed once +// the data structures are converted. +typedef uvm_parent_processor_id_t uvm_processor_id_t; +typedef uvm_parent_gpu_id_t uvm_gpu_id_t; + +#define UVM_ID_CPU_VALUE UVM_PARENT_ID_CPU_VALUE +#define UVM_ID_GPU0_VALUE UVM_PARENT_ID_GPU0_VALUE +#define UVM_ID_MAX_GPUS UVM_PARENT_ID_MAX_GPUS +#define UVM_ID_MAX_PROCESSORS UVM_PARENT_ID_MAX_PROCESSORS +#define UVM_ID_MAX_SUB_PROCESSORS UVM_PARENT_ID_MAX_SUB_PROCESSORS +#define UVM_ID_CPU UVM_PARENT_ID_CPU +#define UVM_ID_INVALID UVM_PARENT_ID_INVALID + +static int uvm_id_cmp(uvm_parent_processor_id_t id1, uvm_parent_processor_id_t id2) +{ + return UVM_CMP_DEFAULT(id1.val, id2.val); +} + +static bool uvm_id_equal(uvm_parent_processor_id_t id1, uvm_parent_processor_id_t id2) +{ + return uvm_parent_id_equal(id1, id2); +} + +#define UVM_ID_IS_CPU(id) uvm_id_equal(id, UVM_ID_CPU) +#define UVM_ID_IS_INVALID(id) uvm_id_equal(id, UVM_ID_INVALID) +#define UVM_ID_IS_VALID(id) (!UVM_ID_IS_INVALID(id)) +#define UVM_ID_IS_GPU(id) (!UVM_ID_IS_CPU(id) && !UVM_ID_IS_INVALID(id)) + +static uvm_parent_gpu_id_t uvm_gpu_id_from_value(NvU32 val) +{ + return uvm_parent_gpu_id_from_value(val); +} + +static NvU32 uvm_id_value(uvm_parent_processor_id_t id) +{ + return uvm_parent_id_value(id); +} + +static NvU32 uvm_id_gpu_index(uvm_parent_gpu_id_t id) +{ + return uvm_parent_id_gpu_index(id); +} + +static NvU32 uvm_id_gpu_index_from_global_gpu_id(const uvm_global_gpu_id_t id) +{ + return uvm_parent_id_gpu_index_from_global_gpu_id(id); +} + +static uvm_parent_gpu_id_t uvm_gpu_id_from_index(NvU32 index) +{ + return uvm_parent_gpu_id_from_index(index); +} + +static uvm_parent_gpu_id_t uvm_gpu_id_next(uvm_parent_gpu_id_t id) +{ + return uvm_parent_gpu_id_next(id); +} + +static uvm_parent_gpu_id_t uvm_gpu_id_from_global_gpu_id(const uvm_global_gpu_id_t id) +{ + return uvm_parent_gpu_id_from_global_gpu_id(id); +} + +static NvU32 uvm_global_id_gpu_index_from_gpu_id(const uvm_parent_gpu_id_t id) +{ + return uvm_global_id_gpu_index_from_parent_gpu_id(id); +} + +static uvm_global_gpu_id_t uvm_global_gpu_id_from_gpu_id(const uvm_parent_gpu_id_t id) +{ + return uvm_global_gpu_id_from_parent_gpu_id(id); +} + #endif diff --git a/kernel-open/nvidia-uvm/uvm_test.c b/kernel-open/nvidia-uvm/uvm_test.c index f9f5744c0a..47bba3512e 100644 --- a/kernel-open/nvidia-uvm/uvm_test.c +++ b/kernel-open/nvidia-uvm/uvm_test.c @@ -106,26 +106,6 @@ static NV_STATUS uvm_test_nv_kthread_q(UVM_TEST_NV_KTHREAD_Q_PARAMS *params, str return NV_ERR_INVALID_STATE; } -static NV_STATUS uvm_test_numa_get_closest_cpu_node_to_gpu(UVM_TEST_NUMA_GET_CLOSEST_CPU_NODE_TO_GPU_PARAMS *params, - struct file *filp) -{ - uvm_gpu_t *gpu; - NV_STATUS status; - uvm_rm_user_object_t user_rm_va_space = { - .rm_control_fd = -1, - .user_client = params->client, - .user_object = params->smc_part_ref - }; - - status = uvm_gpu_retain_by_uuid(¶ms->gpu_uuid, &user_rm_va_space, &gpu); - if (status != NV_OK) - return status; - - params->node_id = gpu->parent->closest_cpu_numa_node; - uvm_gpu_release(gpu); - return NV_OK; -} - // Callers of this function should ensure that node is not NUMA_NO_NODE in order // to avoid overrunning the kernel's node to cpumask map. static NV_STATUS uvm_test_verify_bh_affinity(uvm_intr_handler_t *isr, int node) @@ -307,8 +287,6 @@ long uvm_test_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_DRAIN_REPLAYABLE_FAULTS, uvm_test_drain_replayable_faults); UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_PMA_GET_BATCH_SIZE, uvm_test_pma_get_batch_size); UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_PMM_QUERY_PMA_STATS, uvm_test_pmm_query_pma_stats); - UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_NUMA_GET_CLOSEST_CPU_NODE_TO_GPU, - uvm_test_numa_get_closest_cpu_node_to_gpu); UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_NUMA_CHECK_AFFINITY, uvm_test_numa_check_affinity); UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_VA_SPACE_ADD_DUMMY_THREAD_CONTEXTS, uvm_test_va_space_add_dummy_thread_contexts); diff --git a/kernel-open/nvidia-uvm/uvm_test_ioctl.h b/kernel-open/nvidia-uvm/uvm_test_ioctl.h index ef73be0c0f..91619ca5a6 100644 --- a/kernel-open/nvidia-uvm/uvm_test_ioctl.h +++ b/kernel-open/nvidia-uvm/uvm_test_ioctl.h @@ -561,6 +561,22 @@ typedef struct // user_pages_allocation_retry_force_count, but the injection point simulates // driver metadata allocation failure. // +// cpu_chunk_allocation_target_id and cpu_chunk_allocation_actual_id are used +// to control the NUMA node IDs for CPU chunk allocations, specifically for +// testing overlapping CPU chunk allocations. +// +// Currently, uvm_api_migrate() does not pass the preferred CPU NUMA node to for +// managed memory so it is not possible to request a specific node. +// cpu_chunk_allocation_target_id is used to request the allocation be made on +// specific node. On the other hand, cpu_chunk_allocation_actual_id is the node +// on which the allocation will actually be made. +// +// The two parameters can be used to force a CPU chunk allocation to overlap a +// previously allocated chunk. +// +// Please note that even when specifying cpu_cpu_allocation_actual_id, the +// kernel may end up allocating on a different node. +// // Error returns: // NV_ERR_INVALID_ADDRESS // - lookup_address doesn't match a UVM range @@ -571,6 +587,8 @@ typedef struct NvU32 page_table_allocation_retry_force_count; // In NvU32 user_pages_allocation_retry_force_count; // In NvU32 cpu_chunk_allocation_size_mask; // In + NvS32 cpu_chunk_allocation_target_id; // In + NvS32 cpu_chunk_allocation_actual_id; // In NvU32 cpu_pages_allocation_error_count; // In NvBool eviction_error; // In NvBool populate_error; // In @@ -604,6 +622,10 @@ typedef struct NvProcessorUuid resident_on[UVM_MAX_PROCESSORS]; // Out NvU32 resident_on_count; // Out + // If the memory is resident on the CPU, the NUMA node on which the page + // is resident. Otherwise, -1. + NvS32 resident_nid; // Out + // The size of the physical allocation backing lookup_address. Only the // system-page-sized portion of this allocation which contains // lookup_address is guaranteed to be resident on the corresponding @@ -1168,19 +1190,6 @@ typedef struct NV_STATUS rmStatus; // Out } UVM_TEST_PMM_QUERY_PMA_STATS_PARAMS; -#define UVM_TEST_NUMA_GET_CLOSEST_CPU_NODE_TO_GPU UVM_TEST_IOCTL_BASE(77) -typedef struct -{ - NvProcessorUuid gpu_uuid; // In - NvHandle client; // In - NvHandle smc_part_ref; // In - - // On kernels with NUMA support, this entry contains the closest CPU NUMA - // node to this GPU. Otherwise, the value will be -1. - NvS32 node_id; // Out - NV_STATUS rmStatus; // Out -} UVM_TEST_NUMA_GET_CLOSEST_CPU_NODE_TO_GPU_PARAMS; - // Test whether the bottom halves have run on the correct CPUs based on the // NUMA node locality of the GPU. // diff --git a/kernel-open/nvidia-uvm/uvm_va_block.c b/kernel-open/nvidia-uvm/uvm_va_block.c index 88fdefca84..cd7a2d7287 100644 --- a/kernel-open/nvidia-uvm/uvm_va_block.c +++ b/kernel-open/nvidia-uvm/uvm_va_block.c @@ -54,6 +54,7 @@ static struct kmem_cache *g_uvm_va_block_cache __read_mostly; static struct kmem_cache *g_uvm_va_block_gpu_state_cache __read_mostly; static struct kmem_cache *g_uvm_page_mask_cache __read_mostly; static struct kmem_cache *g_uvm_va_block_context_cache __read_mostly; +static struct kmem_cache *g_uvm_va_block_cpu_node_state_cache __read_mostly; static int uvm_fault_force_sysmem __read_mostly = 0; module_param(uvm_fault_force_sysmem, int, S_IRUGO|S_IWUSR); @@ -179,6 +180,20 @@ void uvm_va_block_retry_init(uvm_va_block_retry_t *retry) INIT_LIST_HEAD(&retry->free_chunks); } +static size_t node_to_index(int nid) +{ + UVM_ASSERT(nid != NUMA_NO_NODE); + UVM_ASSERT(nid < MAX_NUMNODES); + return __nodes_weight(&node_possible_map, nid); +} + +static uvm_va_block_cpu_node_state_t *block_node_state_get(uvm_va_block_t *block, int nid) +{ + size_t index = node_to_index(nid); + UVM_ASSERT(block->cpu.node_state[index]); + return block->cpu.node_state[index]; +} + // The bottom bit of uvm_va_block_t::chunks is used to indicate how CPU chunks // are stored. // @@ -227,14 +242,26 @@ static uvm_va_block_region_t uvm_cpu_chunk_block_region(uvm_va_block_t *va_block return uvm_va_block_chunk_region(va_block, uvm_cpu_chunk_get_size(chunk), page_index); } -static void *uvm_cpu_storage_get_ptr(uvm_va_block_t *block) +static void *uvm_cpu_storage_get_ptr(uvm_va_block_cpu_node_state_t *node_state) { - return (void *)(block->cpu.chunks & ~UVM_CPU_CHUNK_STORAGE_MASK); + return (void *)(node_state->chunks & ~UVM_CPU_CHUNK_STORAGE_MASK); } -static uvm_cpu_chunk_storage_type_t uvm_cpu_storage_get_type(uvm_va_block_t *block) +static uvm_cpu_chunk_storage_type_t uvm_cpu_storage_get_type(uvm_va_block_cpu_node_state_t *node_state) { - return block->cpu.chunks & UVM_CPU_CHUNK_STORAGE_MASK; + return node_state->chunks & UVM_CPU_CHUNK_STORAGE_MASK; +} + +static int block_get_page_node_residency(uvm_va_block_t *block, uvm_page_index_t page_index) +{ + int nid; + + for_each_possible_uvm_node(nid) { + if (uvm_va_block_cpu_is_page_resident_on(block, nid, page_index)) + return nid; + } + + return NUMA_NO_NODE; } static uvm_page_index_t compute_page_prefix(uvm_va_block_t *va_block, uvm_chunk_size_t size) @@ -270,12 +297,12 @@ static size_t compute_small_index(uvm_va_block_t *va_block, uvm_page_index_t pag return (page_index - prefix) % MAX_SMALL_CHUNKS_PER_BIG_SLOT; } -NV_STATUS uvm_cpu_chunk_insert_in_block(uvm_va_block_t *va_block, - uvm_cpu_chunk_t *chunk, - uvm_page_index_t page_index) +NV_STATUS uvm_cpu_chunk_insert_in_block(uvm_va_block_t *va_block, uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index) { uvm_chunk_size_t chunk_size = uvm_cpu_chunk_get_size(chunk); uvm_va_block_region_t chunk_region = uvm_va_block_region(page_index, page_index + uvm_cpu_chunk_num_pages(chunk)); + int nid = uvm_cpu_chunk_get_numa_node(chunk); + uvm_va_block_cpu_node_state_t *node_state = block_node_state_get(va_block, nid); size_t slot_index; uvm_cpu_chunk_storage_mixed_t *mixed; uvm_cpu_chunk_t **chunks = NULL; @@ -291,20 +318,20 @@ NV_STATUS uvm_cpu_chunk_insert_in_block(uvm_va_block_t *va_block, if (chunk_size == UVM_CHUNK_SIZE_2M) { UVM_ASSERT(uvm_va_block_size(va_block) == UVM_PAGE_SIZE_2M); - UVM_ASSERT(!va_block->cpu.chunks); - va_block->cpu.chunks = (unsigned long)chunk | UVM_CPU_CHUNK_STORAGE_CHUNK; + UVM_ASSERT(!node_state->chunks); + node_state->chunks = (unsigned long)chunk | UVM_CPU_CHUNK_STORAGE_CHUNK; } else { - if (!va_block->cpu.chunks) { + if (!node_state->chunks) { mixed = uvm_kvmalloc_zero(sizeof(*mixed)); if (!mixed) return NV_ERR_NO_MEMORY; - va_block->cpu.chunks = (unsigned long)mixed | UVM_CPU_CHUNK_STORAGE_MIXED; + node_state->chunks = (unsigned long)mixed | UVM_CPU_CHUNK_STORAGE_MIXED; } - UVM_ASSERT(uvm_cpu_storage_get_type(va_block) == UVM_CPU_CHUNK_STORAGE_MIXED); - mixed = uvm_cpu_storage_get_ptr(va_block); + UVM_ASSERT(uvm_cpu_storage_get_type(node_state) == UVM_CPU_CHUNK_STORAGE_MIXED); + mixed = uvm_cpu_storage_get_ptr(node_state); slot_index = compute_slot_index(va_block, page_index); UVM_ASSERT(compute_slot_index(va_block, page_index + uvm_cpu_chunk_num_pages(chunk) - 1) == slot_index); UVM_ASSERT(!test_bit(slot_index, mixed->big_chunks)); @@ -331,28 +358,32 @@ NV_STATUS uvm_cpu_chunk_insert_in_block(uvm_va_block_t *va_block, } } + uvm_page_mask_region_fill(&node_state->allocated, chunk_region); uvm_page_mask_region_fill(&va_block->cpu.allocated, chunk_region); return NV_OK; } -uvm_cpu_chunk_t *uvm_cpu_chunk_get_chunk_for_page(uvm_va_block_t *va_block, uvm_page_index_t page_index) +uvm_cpu_chunk_t *uvm_cpu_chunk_get_chunk_for_page(uvm_va_block_t *va_block, int nid, uvm_page_index_t page_index) { + uvm_va_block_cpu_node_state_t *node_state; uvm_cpu_chunk_storage_mixed_t *mixed; uvm_cpu_chunk_t *chunk; uvm_cpu_chunk_t **chunks; size_t slot_index; UVM_ASSERT(page_index < uvm_va_block_num_cpu_pages(va_block)); - if (!uvm_page_mask_test(&va_block->cpu.allocated, page_index)) + UVM_ASSERT(nid != NUMA_NO_NODE); + node_state = block_node_state_get(va_block, nid); + if (!uvm_page_mask_test(&node_state->allocated, page_index)) return NULL; - UVM_ASSERT(va_block->cpu.chunks); + UVM_ASSERT(node_state->chunks); - if (uvm_cpu_storage_get_type(va_block) == UVM_CPU_CHUNK_STORAGE_CHUNK) { - return uvm_cpu_storage_get_ptr(va_block); + if (uvm_cpu_storage_get_type(node_state) == UVM_CPU_CHUNK_STORAGE_CHUNK) { + return uvm_cpu_storage_get_ptr(node_state); } else { - mixed = uvm_cpu_storage_get_ptr(va_block); + mixed = uvm_cpu_storage_get_ptr(node_state); slot_index = compute_slot_index(va_block, page_index); UVM_ASSERT(mixed->slots[slot_index] != NULL); if (test_bit(slot_index, mixed->big_chunks)) @@ -366,31 +397,43 @@ uvm_cpu_chunk_t *uvm_cpu_chunk_get_chunk_for_page(uvm_va_block_t *va_block, uvm_ return chunk; } -void uvm_cpu_chunk_remove_from_block(uvm_va_block_t *va_block, - uvm_page_index_t page_index) +static uvm_cpu_chunk_t *uvm_cpu_chunk_get_chunk_for_page_resident(uvm_va_block_t *va_block, uvm_page_index_t page_index) +{ + uvm_cpu_chunk_t *chunk = NULL; + int nid = block_get_page_node_residency(va_block, page_index); + + if (nid != NUMA_NO_NODE) + chunk = uvm_cpu_chunk_get_chunk_for_page(va_block, nid, page_index); + + return chunk; +} + +void uvm_cpu_chunk_remove_from_block(uvm_va_block_t *va_block, int nid, uvm_page_index_t page_index) { + uvm_va_block_cpu_node_state_t *node_state = block_node_state_get(va_block, nid); uvm_cpu_chunk_storage_mixed_t *mixed; - uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(va_block, page_index); + uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(va_block, nid, page_index); uvm_va_block_region_t chunk_region = uvm_cpu_chunk_block_region(va_block, chunk, page_index); size_t slot_index; uvm_cpu_chunk_t **chunks; + int nid_iter; // We want to protect against two threads manipulating the VA block's CPU // chunks at the same time. However, when a block is split, the new block's // lock is locked without tracking. So, we can't use // uvm_assert_mutex_locked(). UVM_ASSERT(mutex_is_locked(&va_block->lock.m)); - UVM_ASSERT(va_block->cpu.chunks); + UVM_ASSERT(node_state->chunks); UVM_ASSERT(uvm_va_block_region_num_pages(chunk_region) == uvm_cpu_chunk_num_pages(chunk)); - if (uvm_cpu_storage_get_type(va_block) == UVM_CPU_CHUNK_STORAGE_CHUNK) { + if (uvm_cpu_storage_get_type(node_state) == UVM_CPU_CHUNK_STORAGE_CHUNK) { UVM_ASSERT(uvm_cpu_chunk_get_size(chunk) == UVM_CHUNK_SIZE_2M); - UVM_ASSERT(uvm_cpu_storage_get_ptr(va_block) == chunk); - va_block->cpu.chunks = 0; + UVM_ASSERT(uvm_cpu_storage_get_ptr(node_state) == chunk); + node_state->chunks = 0; } else { UVM_ASSERT(uvm_cpu_chunk_get_size(chunk) != UVM_CHUNK_SIZE_2M); - mixed = uvm_cpu_storage_get_ptr(va_block); + mixed = uvm_cpu_storage_get_ptr(node_state); slot_index = compute_slot_index(va_block, page_index); UVM_ASSERT(mixed->slots[slot_index] != NULL); @@ -421,18 +464,22 @@ void uvm_cpu_chunk_remove_from_block(uvm_va_block_t *va_block, } } - uvm_page_mask_region_clear(&va_block->cpu.allocated, chunk_region); + uvm_page_mask_region_clear(&node_state->allocated, chunk_region); + uvm_page_mask_zero(&va_block->cpu.allocated); + for_each_possible_uvm_node(nid_iter) { + uvm_va_block_cpu_node_state_t *iter_node_state = block_node_state_get(va_block, nid_iter); + uvm_page_mask_or(&va_block->cpu.allocated, &va_block->cpu.allocated, &iter_node_state->allocated); + } - if (uvm_page_mask_empty(&va_block->cpu.allocated) && va_block->cpu.chunks) { - uvm_kvfree(uvm_cpu_storage_get_ptr(va_block)); - va_block->cpu.chunks = 0; + if (uvm_page_mask_empty(&node_state->allocated) && node_state->chunks) { + uvm_kvfree(uvm_cpu_storage_get_ptr(node_state)); + node_state->chunks = 0; } } -struct page *uvm_cpu_chunk_get_cpu_page(uvm_va_block_t *va_block, uvm_page_index_t page_index) +struct page *uvm_cpu_chunk_get_cpu_page(uvm_va_block_t *va_block, uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index) { uvm_va_block_region_t chunk_region; - uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(va_block, page_index); UVM_ASSERT(chunk); UVM_ASSERT(chunk->page); @@ -440,16 +487,28 @@ struct page *uvm_cpu_chunk_get_cpu_page(uvm_va_block_t *va_block, uvm_page_index return chunk->page + (page_index - chunk_region.first); } +struct page *uvm_va_block_get_cpu_page(uvm_va_block_t *va_block, uvm_page_index_t page_index) +{ + uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page_resident(va_block, page_index); + + return uvm_cpu_chunk_get_cpu_page(va_block, chunk, page_index); +} + static uvm_cpu_chunk_t *uvm_cpu_chunk_first_in_region(uvm_va_block_t *va_block, uvm_va_block_region_t region, + int nid, uvm_page_index_t *first_chunk_page) { uvm_cpu_chunk_t *chunk = NULL; uvm_page_index_t page_index; + uvm_va_block_cpu_node_state_t *node_state = block_node_state_get(va_block, nid); + + if (!node_state) + return NULL; - page_index = uvm_va_block_first_page_in_mask(region, &va_block->cpu.allocated); + page_index = uvm_va_block_first_page_in_mask(region, &node_state->allocated); if (page_index < region.outer) - chunk = uvm_cpu_chunk_get_chunk_for_page(va_block, page_index); + chunk = uvm_cpu_chunk_get_chunk_for_page(va_block, nid, page_index); if (first_chunk_page && chunk) { uvm_va_block_region_t chunk_region = uvm_cpu_chunk_block_region(va_block, chunk, page_index); @@ -459,33 +518,156 @@ static uvm_cpu_chunk_t *uvm_cpu_chunk_first_in_region(uvm_va_block_t *va_block, return chunk; } -#define for_each_cpu_chunk_in_block_region(chunk, page_index, va_block, region) \ - for ((chunk) = uvm_cpu_chunk_first_in_region((va_block), (region), &(page_index)); \ - (chunk) != NULL; \ - (chunk) = uvm_cpu_chunk_first_in_region((va_block), \ - uvm_va_block_region((page_index) + uvm_cpu_chunk_num_pages((chunk)), \ - (region).outer), \ - &(page_index))) - -#define for_each_cpu_chunk_in_block_region_safe(chunk, page_index, next_page_index, va_block, region) \ - for ((chunk) = uvm_cpu_chunk_first_in_region((va_block), (region), &(page_index)), \ - (next_page_index) = (page_index) + (chunk ? uvm_cpu_chunk_num_pages(chunk) : 0); \ - (chunk) != NULL; \ - (chunk) = uvm_cpu_chunk_first_in_region((va_block), \ - uvm_va_block_region((next_page_index), (region).outer), \ - &(page_index)), \ - (next_page_index) = (page_index) + ((chunk) ? uvm_cpu_chunk_num_pages((chunk)) : 0)) - -#define for_each_cpu_chunk_in_block(chunk, page_index, va_block) \ - for_each_cpu_chunk_in_block_region((chunk), (page_index), (va_block), uvm_va_block_region_from_block((va_block))) - -#define for_each_cpu_chunk_in_block_safe(chunk, page_index, next_page_index, va_block) \ - for_each_cpu_chunk_in_block_region_safe((chunk), \ - (page_index), \ - (next_page_index), \ - (va_block), \ +static uvm_cpu_chunk_t *uvm_cpu_chunk_next_in_region(uvm_va_block_t *va_block, + uvm_va_block_region_t region, + int nid, + uvm_page_index_t prev_page_index, + uvm_page_index_t *next_chunk_page) +{ + if (prev_page_index >= region.outer) + return NULL; + + return uvm_cpu_chunk_first_in_region(va_block, + uvm_va_block_region(prev_page_index, region.outer), + nid, next_chunk_page); +} + +#define for_each_cpu_chunk_in_block_region(chunk, chunk_start, va_block, nid, region) \ + for ((chunk) = uvm_cpu_chunk_first_in_region((va_block), (region), (nid), &(chunk_start)); \ + (chunk) != NULL; \ + (chunk) = uvm_cpu_chunk_next_in_region((va_block), \ + (region), \ + (nid), \ + (chunk_start) + uvm_cpu_chunk_num_pages((chunk)), \ + &(chunk_start))) + +#define for_each_cpu_chunk_in_block_region_safe(chunk, chunk_start, next_chunk_start, va_block, nid, region) \ + for ((chunk) = uvm_cpu_chunk_first_in_region((va_block), (region), (nid), &(chunk_start)), \ + (next_chunk_start) = (chunk_start) + (chunk ? uvm_cpu_chunk_num_pages(chunk) : 0); \ + (chunk) != NULL; \ + (chunk) = uvm_cpu_chunk_next_in_region((va_block), (region), (nid), (next_chunk_start), &(chunk_start)), \ + (next_chunk_start) = (chunk_start) + ((chunk) ? uvm_cpu_chunk_num_pages((chunk)) : 0)) + +#define for_each_cpu_chunk_in_block(chunk, chunk_start, va_block, nid) \ + for_each_cpu_chunk_in_block_region((chunk), \ + (chunk_start), \ + (va_block), \ + (nid), \ + uvm_va_block_region_from_block((va_block))) + +#define for_each_cpu_chunk_in_block_safe(chunk, chunk_start, next_chunk_start, va_block, nid) \ + for_each_cpu_chunk_in_block_region_safe((chunk), \ + (chunk_start), \ + (next_chunk_start), \ + (va_block), \ + (nid), \ uvm_va_block_region_from_block((va_block))) +static void block_update_cpu_resident_mask(uvm_va_block_t *va_block) +{ + int nid; + + uvm_page_mask_zero(&va_block->cpu.resident); + for_each_possible_uvm_node(nid) { + uvm_va_block_cpu_node_state_t *node_state = block_node_state_get(va_block, nid); + uvm_page_mask_or(&va_block->cpu.resident, &va_block->cpu.resident, &node_state->resident); + } +} + +void uvm_va_block_cpu_set_resident_page(uvm_va_block_t *va_block, int nid, uvm_page_index_t page_index) +{ + uvm_va_block_cpu_node_state_t *node_state; + + node_state = block_node_state_get(va_block, nid); + UVM_ASSERT(node_state); + UVM_ASSERT(uvm_page_mask_test(&node_state->allocated, page_index)); + uvm_page_mask_set(&node_state->resident, page_index); + uvm_page_mask_set(&va_block->cpu.resident, page_index); + uvm_processor_mask_set(&va_block->resident, UVM_ID_CPU); +} + +// Set all CPU pages in the mask as resident on NUMA node nid. +// nid cannot be NUMA_NO_NODE. +static void uvm_va_block_cpu_set_resident_mask(uvm_va_block_t *va_block, int nid, const uvm_page_mask_t *mask) +{ + uvm_va_block_cpu_node_state_t *node_state; + + node_state = block_node_state_get(va_block, nid); + UVM_ASSERT(node_state); + UVM_ASSERT(uvm_page_mask_subset(mask, &node_state->allocated)); + uvm_page_mask_or(&node_state->resident, &node_state->resident, mask); + uvm_page_mask_or(&va_block->cpu.resident, &va_block->cpu.resident, mask); +} + +static void uvm_va_block_cpu_set_resident_all_chunks(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + const uvm_page_mask_t *page_mask) +{ + uvm_make_resident_page_tracking_t *tracking = &va_block_context->make_resident.cpu_pages_used; + uvm_page_mask_t *node_pages_mask = &va_block_context->make_resident.node_pages_mask; + uvm_page_mask_t *page_mask_copy = &va_block_context->scratch_page_mask; + int nid; + + if (uvm_page_mask_empty(page_mask)) + return; + + uvm_page_mask_copy(page_mask_copy, page_mask); + for_each_node_mask(nid, tracking->nodes) { + size_t index = node_to_index(nid); + + if (uvm_page_mask_and(node_pages_mask, page_mask_copy, tracking->node_masks[index])) { + uvm_va_block_cpu_set_resident_mask(va_block, nid, node_pages_mask); + uvm_page_mask_andnot(page_mask_copy, page_mask_copy, node_pages_mask); + } + } + + UVM_ASSERT(uvm_page_mask_empty(page_mask_copy)); +} + +// Clear residency for all CPU pages in the mask. +// nid cannot be NUMA_NO_NODE. +static void uvm_va_block_cpu_clear_resident_mask(uvm_va_block_t *va_block, int nid, const uvm_page_mask_t *mask) +{ + uvm_va_block_cpu_node_state_t *node_state; + + node_state = block_node_state_get(va_block, nid); + UVM_ASSERT(node_state); + uvm_page_mask_andnot(&node_state->resident, &node_state->resident, mask); + block_update_cpu_resident_mask(va_block); +} + +static void uvm_va_block_cpu_clear_resident_region(uvm_va_block_t *va_block, int nid, uvm_va_block_region_t region) +{ + uvm_va_block_cpu_node_state_t *node_state; + + node_state = block_node_state_get(va_block, nid); + UVM_ASSERT(node_state); + uvm_page_mask_region_clear(&node_state->resident, region); + block_update_cpu_resident_mask(va_block); +} + +bool uvm_va_block_cpu_is_page_resident_on(uvm_va_block_t *va_block, int nid, uvm_page_index_t page_index) +{ + uvm_page_mask_t *resident_mask = uvm_va_block_resident_mask_get(va_block, UVM_ID_CPU, nid); + + return uvm_page_mask_test(resident_mask, page_index); +} + +bool uvm_va_block_cpu_is_region_resident_on(uvm_va_block_t *va_block, int nid, uvm_va_block_region_t region) +{ + uvm_page_mask_t *resident_mask = uvm_va_block_resident_mask_get(va_block, UVM_ID_CPU, nid); + + return uvm_page_mask_region_full(resident_mask, region); +} + +int uvm_va_block_context_get_node(uvm_va_block_context_t *va_block_context) +{ + if (va_block_context->make_resident.dest_nid != NUMA_NO_NODE) + return va_block_context->make_resident.dest_nid; + + return numa_mem_id(); +} + struct vm_area_struct *uvm_va_block_find_vma_region(uvm_va_block_t *va_block, struct mm_struct *mm, NvU64 start, @@ -515,29 +697,48 @@ struct vm_area_struct *uvm_va_block_find_vma_region(uvm_va_block_t *va_block, static bool block_check_cpu_chunks(uvm_va_block_t *block) { - uvm_cpu_chunk_t *chunk; - size_t alloced_pages = 0; - uvm_va_block_region_t prev_region = { 0 }; - uvm_page_index_t page_index; + int nid; + uvm_page_mask_t *temp_resident_mask; + + temp_resident_mask = kmem_cache_alloc(g_uvm_page_mask_cache, NV_UVM_GFP_FLAGS | __GFP_ZERO); + + for_each_possible_uvm_node(nid) { + uvm_cpu_chunk_t *chunk; + uvm_page_index_t page_index; + uvm_va_block_region_t prev_region = {0}; + uvm_va_block_cpu_node_state_t *node_state = block_node_state_get(block, nid); + size_t alloced_pages = 0; + + for_each_cpu_chunk_in_block(chunk, page_index, block, nid) { + uvm_va_block_region_t chunk_region = uvm_cpu_chunk_block_region(block, chunk, page_index); + size_t num_chunk_pages = uvm_cpu_chunk_num_pages(chunk); + uvm_page_index_t chunk_page; - for_each_cpu_chunk_in_block(chunk, page_index, block) { - uvm_va_block_region_t chunk_region = uvm_cpu_chunk_block_region(block, chunk, page_index); - size_t num_chunk_pages = uvm_cpu_chunk_num_pages(chunk); - uvm_page_index_t chunk_page; + UVM_ASSERT(prev_region.outer <= chunk_region.first); + UVM_ASSERT(IS_ALIGNED(uvm_va_block_region_start(block, chunk_region), uvm_cpu_chunk_get_size(chunk))); + UVM_ASSERT(chunk_region.outer <= uvm_va_block_num_cpu_pages(block)); - UVM_ASSERT(prev_region.outer <= chunk_region.first); - UVM_ASSERT(IS_ALIGNED(uvm_va_block_region_start(block, chunk_region), uvm_cpu_chunk_get_size(chunk))); - UVM_ASSERT(chunk_region.outer <= uvm_va_block_num_cpu_pages(block)); + alloced_pages += uvm_cpu_chunk_num_pages(chunk); + UVM_ASSERT(uvm_page_mask_region_full(&node_state->allocated, chunk_region)); + prev_region = chunk_region; - alloced_pages += uvm_cpu_chunk_num_pages(chunk); - UVM_ASSERT(uvm_page_mask_region_full(&block->cpu.allocated, chunk_region)); - prev_region = chunk_region; + for (chunk_page = page_index; chunk_page < page_index + num_chunk_pages; chunk_page++) + UVM_ASSERT(uvm_cpu_chunk_get_chunk_for_page(block, nid, chunk_page) == chunk); + } - for (chunk_page = page_index; chunk_page < page_index + num_chunk_pages; chunk_page++) - UVM_ASSERT(uvm_cpu_chunk_get_chunk_for_page(block, chunk_page) == chunk); + UVM_ASSERT(alloced_pages == uvm_page_mask_weight(&node_state->allocated)); + UVM_ASSERT(uvm_page_mask_subset(&node_state->resident, &node_state->allocated)); + UVM_ASSERT(uvm_page_mask_subset(&node_state->resident, &block->cpu.resident)); + if (temp_resident_mask && !uvm_page_mask_empty(&node_state->resident)) { + UVM_ASSERT(!uvm_page_mask_intersects(&node_state->resident, temp_resident_mask)); + uvm_page_mask_or(temp_resident_mask, temp_resident_mask, &node_state->resident); + } } - UVM_ASSERT(alloced_pages == uvm_page_mask_weight(&block->cpu.allocated)); + if (temp_resident_mask) { + UVM_ASSERT(uvm_page_mask_equal(temp_resident_mask, &block->cpu.resident)); + kmem_cache_free(g_uvm_page_mask_cache, temp_resident_mask); + } return true; } @@ -607,11 +808,17 @@ typedef struct // The page index uvm_page_index_t page_index; + + // If processor is the CPU, the NUMA node of the page. + int nid; } block_phys_page_t; -static block_phys_page_t block_phys_page(uvm_processor_id_t processor, uvm_page_index_t page_index) +static block_phys_page_t block_phys_page(uvm_processor_id_t processor, int nid, uvm_page_index_t page_index) { - return (block_phys_page_t){ processor, page_index }; + if (UVM_ID_IS_CPU(processor)) + UVM_ASSERT(nid != NUMA_NO_NODE); + + return (block_phys_page_t){ processor, page_index, nid }; } NV_STATUS uvm_va_block_init(void) @@ -636,30 +843,102 @@ NV_STATUS uvm_va_block_init(void) if (!g_uvm_va_block_context_cache) return NV_ERR_NO_MEMORY; + g_uvm_va_block_cpu_node_state_cache = NV_KMEM_CACHE_CREATE("uvm_va_block_cpu_node_state_t", + uvm_va_block_cpu_node_state_t); + if (!g_uvm_va_block_cpu_node_state_cache) + return NV_ERR_NO_MEMORY; + return NV_OK; } void uvm_va_block_exit(void) { + kmem_cache_destroy_safe(&g_uvm_va_block_cpu_node_state_cache); kmem_cache_destroy_safe(&g_uvm_va_block_context_cache); kmem_cache_destroy_safe(&g_uvm_page_mask_cache); kmem_cache_destroy_safe(&g_uvm_va_block_gpu_state_cache); kmem_cache_destroy_safe(&g_uvm_va_block_cache); } +static void block_context_free_tracking(uvm_make_resident_page_tracking_t *tracking) +{ + size_t index; + + for (index = 0; index < num_possible_nodes(); index++) { + if (tracking->node_masks[index]) + kmem_cache_free(g_uvm_page_mask_cache, tracking->node_masks[index]); + } + + uvm_kvfree(tracking->node_masks); +} + +static NV_STATUS block_context_alloc_tracking(uvm_make_resident_page_tracking_t *tracking) +{ + size_t index; + + tracking->node_masks = uvm_kvmalloc_zero(num_possible_nodes() * sizeof(*tracking->node_masks)); + if (!tracking->node_masks) + return NV_ERR_NO_MEMORY; + + for (index = 0; index < num_possible_nodes(); index++) { + tracking->node_masks[index] = kmem_cache_alloc(g_uvm_page_mask_cache, NV_UVM_GFP_FLAGS); + if (!tracking->node_masks[index]) + goto error; + } + + return NV_OK; + +error: + block_context_free_tracking(tracking); + return NV_ERR_NO_MEMORY; +} + uvm_va_block_context_t *uvm_va_block_context_alloc(struct mm_struct *mm) { uvm_va_block_context_t *block_context = kmem_cache_alloc(g_uvm_va_block_context_cache, NV_UVM_GFP_FLAGS); - if (block_context) - uvm_va_block_context_init(block_context, mm); + NV_STATUS status; + if (!block_context) + return NULL; + + status = block_context_alloc_tracking(&block_context->make_resident.cpu_pages_used); + if (status != NV_OK) { + kmem_cache_free(g_uvm_va_block_context_cache, block_context); + return NULL; + } + + uvm_va_block_context_init(block_context, mm); return block_context; } +void uvm_va_block_context_init(uvm_va_block_context_t *va_block_context, struct mm_struct *mm) +{ + UVM_ASSERT(va_block_context); + + // Write garbage into the VA Block context to ensure that the UVM code + // clears masks appropriately + if (UVM_IS_DEBUG()) { + uvm_page_mask_t **mask_array = va_block_context->make_resident.cpu_pages_used.node_masks; + int nid; + + memset(va_block_context, 0xff, sizeof(*va_block_context)); + + for_each_possible_uvm_node(nid) + uvm_page_mask_fill(mask_array[node_to_index(nid)]); + + va_block_context->make_resident.cpu_pages_used.node_masks = mask_array; + } + + va_block_context->mm = mm; + va_block_context->make_resident.dest_nid = NUMA_NO_NODE; +} + void uvm_va_block_context_free(uvm_va_block_context_t *va_block_context) { - if (va_block_context) + if (va_block_context) { + block_context_free_tracking(&va_block_context->make_resident.cpu_pages_used); kmem_cache_free(g_uvm_va_block_context_cache, va_block_context); + } } // Convert from page_index to chunk_index. The goal is for each system page in @@ -884,6 +1163,18 @@ uvm_gpu_chunk_t *uvm_va_block_lookup_gpu_chunk(uvm_va_block_t *va_block, uvm_gpu return gpu_state->chunks[chunk_index]; } +static void uvm_va_block_free(uvm_va_block_t *block) +{ + if (uvm_enable_builtin_tests) { + uvm_va_block_wrapper_t *block_wrapper = container_of(block, uvm_va_block_wrapper_t, block); + + kmem_cache_free(g_uvm_va_block_cache, block_wrapper); + } + else { + kmem_cache_free(g_uvm_va_block_cache, block); + } +} + NV_STATUS uvm_va_block_create(uvm_va_range_t *va_range, NvU64 start, NvU64 end, @@ -891,6 +1182,7 @@ NV_STATUS uvm_va_block_create(uvm_va_range_t *va_range, { uvm_va_block_t *block = NULL; NvU64 size = end - start + 1; + int nid; UVM_ASSERT(PAGE_ALIGNED(start)); UVM_ASSERT(PAGE_ALIGNED(end + 1)); @@ -911,8 +1203,11 @@ NV_STATUS uvm_va_block_create(uvm_va_range_t *va_range, if (uvm_enable_builtin_tests) { uvm_va_block_wrapper_t *block_wrapper = nv_kmem_cache_zalloc(g_uvm_va_block_cache, NV_UVM_GFP_FLAGS); - if (block_wrapper) + if (block_wrapper) { block = &block_wrapper->block; + block_wrapper->test.cpu_chunk_allocation_target_id = NUMA_NO_NODE; + block_wrapper->test.cpu_chunk_allocation_actual_id = NUMA_NO_NODE; + } } else { block = nv_kmem_cache_zalloc(g_uvm_va_block_cache, NV_UVM_GFP_FLAGS); @@ -921,6 +1216,18 @@ NV_STATUS uvm_va_block_create(uvm_va_range_t *va_range, if (!block) return NV_ERR_NO_MEMORY; + block->cpu.node_state = uvm_kvmalloc_zero(sizeof(*block->cpu.node_state) * num_possible_nodes()); + if (!block->cpu.node_state) + goto error_block_free; + + for_each_possible_uvm_node(nid) { + size_t index = node_to_index(nid); + + block->cpu.node_state[index] = nv_kmem_cache_zalloc(g_uvm_va_block_cpu_node_state_cache, NV_UVM_GFP_FLAGS); + if (!block->cpu.node_state[index]) + goto error; + } + nv_kref_init(&block->kref); uvm_mutex_init(&block->lock, UVM_LOCK_ORDER_VA_BLOCK); block->start = start; @@ -933,6 +1240,20 @@ NV_STATUS uvm_va_block_create(uvm_va_range_t *va_range, *out_block = block; return NV_OK; + +error: + for_each_possible_uvm_node(nid) { + size_t index = node_to_index(nid); + + if (block->cpu.node_state[index]) + kmem_cache_free(g_uvm_va_block_cpu_node_state_cache, block->cpu.node_state[index]); + } + + uvm_kvfree(block->cpu.node_state); + +error_block_free: + uvm_va_block_free(block); + return NV_ERR_NO_MEMORY; } static void cpu_chunk_remove_sysmem_gpu_mapping(uvm_cpu_chunk_t *chunk, uvm_gpu_t *gpu) @@ -984,9 +1305,12 @@ static void block_gpu_unmap_phys_all_cpu_pages(uvm_va_block_t *block, uvm_gpu_t { uvm_cpu_chunk_t *chunk; uvm_page_index_t page_index; + int nid; - for_each_cpu_chunk_in_block(chunk, page_index, block) - cpu_chunk_remove_sysmem_gpu_mapping(chunk, gpu); + for_each_possible_uvm_node(nid) { + for_each_cpu_chunk_in_block(chunk, page_index, block, nid) + cpu_chunk_remove_sysmem_gpu_mapping(chunk, gpu); + } } static NV_STATUS block_gpu_map_phys_all_cpu_pages(uvm_va_block_t *block, uvm_gpu_t *gpu) @@ -995,18 +1319,21 @@ static NV_STATUS block_gpu_map_phys_all_cpu_pages(uvm_va_block_t *block, uvm_gpu uvm_cpu_chunk_t *chunk; NvU64 block_mapping_size = uvm_va_block_size(block); uvm_page_index_t page_index; + int nid; UVM_ASSERT(IS_ALIGNED(block_mapping_size, UVM_PAGE_SIZE_4K)); - for_each_cpu_chunk_in_block(chunk, page_index, block) { - UVM_ASSERT_MSG(uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent) == 0, - "GPU%u DMA address 0x%llx\n", - uvm_id_value(gpu->id), - uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent)); + for_each_possible_uvm_node(nid) { + for_each_cpu_chunk_in_block(chunk, page_index, block, nid) { + UVM_ASSERT_MSG(uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent) == 0, + "GPU%u DMA address 0x%llx\n", + uvm_id_value(gpu->id), + uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent)); - status = cpu_chunk_add_sysmem_gpu_mapping(chunk, block, page_index, gpu); - if (status != NV_OK) - goto error; + status = cpu_chunk_add_sysmem_gpu_mapping(chunk, block, page_index, gpu); + if (status != NV_OK) + goto error; + } } return NV_OK; @@ -1176,11 +1503,11 @@ void uvm_va_block_unmap_cpu_chunk_on_gpus(uvm_va_block_t *block, } NV_STATUS uvm_va_block_map_cpu_chunk_on_gpus(uvm_va_block_t *block, + uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index) { NV_STATUS status; uvm_gpu_id_t id; - uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(block, page_index); uvm_chunk_size_t chunk_size = uvm_cpu_chunk_get_size(chunk); uvm_va_block_region_t chunk_region = uvm_va_block_chunk_region(block, chunk_size, page_index); @@ -1213,21 +1540,25 @@ void uvm_va_block_remove_cpu_chunks(uvm_va_block_t *va_block, uvm_va_block_regio uvm_cpu_chunk_t *chunk; uvm_page_index_t page_index, next_page_index; uvm_va_block_region_t chunk_region; + int nid; - for_each_cpu_chunk_in_block_region_safe(chunk, page_index, next_page_index, va_block, region) { - chunk_region = uvm_va_block_region(page_index, page_index + uvm_cpu_chunk_num_pages(chunk)); + for_each_possible_uvm_node(nid) { + for_each_cpu_chunk_in_block_region_safe(chunk, page_index, next_page_index, va_block, nid, region) { + chunk_region = uvm_va_block_region(page_index, page_index + uvm_cpu_chunk_num_pages(chunk)); - uvm_page_mask_region_clear(&va_block->cpu.pte_bits[UVM_PTE_BITS_CPU_READ], chunk_region); - uvm_page_mask_region_clear(&va_block->cpu.pte_bits[UVM_PTE_BITS_CPU_WRITE], chunk_region); - uvm_page_mask_region_clear(&va_block->cpu.resident, chunk_region); - uvm_cpu_chunk_remove_from_block(va_block, page_index); - uvm_va_block_unmap_cpu_chunk_on_gpus(va_block, chunk, page_index); - uvm_cpu_chunk_free(chunk); + uvm_page_mask_region_clear(&va_block->cpu.pte_bits[UVM_PTE_BITS_CPU_READ], chunk_region); + uvm_page_mask_region_clear(&va_block->cpu.pte_bits[UVM_PTE_BITS_CPU_WRITE], chunk_region); + uvm_va_block_cpu_clear_resident_region(va_block, nid, chunk_region); + uvm_cpu_chunk_remove_from_block(va_block, nid, page_index); + uvm_va_block_unmap_cpu_chunk_on_gpus(va_block, chunk, page_index); + uvm_cpu_chunk_free(chunk); + } } if (uvm_page_mask_empty(&va_block->cpu.pte_bits[UVM_PTE_BITS_CPU_READ])) uvm_processor_mask_clear(&va_block->mapped, UVM_ID_CPU); - if (uvm_page_mask_empty(&va_block->cpu.resident)) + + if (uvm_page_mask_empty(uvm_va_block_resident_mask_get(va_block, UVM_ID_CPU, NUMA_NO_NODE))) uvm_processor_mask_clear(&va_block->resident, UVM_ID_CPU); } @@ -1291,25 +1622,25 @@ static void block_unmap_indirect_peers_from_gpu_chunk(uvm_va_block_t *block, uvm } // Mark a CPU page as dirty. -static void block_mark_cpu_page_dirty(uvm_va_block_t *block, uvm_page_index_t page_index) +static void block_mark_cpu_page_dirty(uvm_va_block_t *block, uvm_page_index_t page_index, int nid) { - uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(block, page_index); + uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(block, nid, page_index); uvm_va_block_region_t chunk_region = uvm_va_block_chunk_region(block, uvm_cpu_chunk_get_size(chunk), page_index); uvm_cpu_chunk_mark_dirty(chunk, page_index - chunk_region.first); } // Mark a CPU page as clean. -static void block_mark_cpu_page_clean(uvm_va_block_t *block, uvm_page_index_t page_index) +static void block_mark_cpu_page_clean(uvm_va_block_t *block, uvm_page_index_t page_index, int nid) { - uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(block, page_index); + uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(block, nid, page_index); uvm_va_block_region_t chunk_region = uvm_va_block_chunk_region(block, uvm_cpu_chunk_get_size(chunk), page_index); uvm_cpu_chunk_mark_clean(chunk, page_index - chunk_region.first); } // Check if a CPU page is dirty. -static bool block_cpu_page_is_dirty(uvm_va_block_t *block, uvm_page_index_t page_index) +static bool block_cpu_page_is_dirty(uvm_va_block_t *block, uvm_page_index_t page_index, int nid) { - uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(block, page_index); + uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(block, nid, page_index); uvm_va_block_region_t chunk_region = uvm_va_block_chunk_region(block, uvm_cpu_chunk_get_size(chunk), page_index); return uvm_cpu_chunk_is_dirty(chunk, page_index - chunk_region.first); } @@ -1317,21 +1648,177 @@ static bool block_cpu_page_is_dirty(uvm_va_block_t *block, uvm_page_index_t page static NV_STATUS block_alloc_cpu_chunk(uvm_va_block_t *block, uvm_chunk_size_t alloc_size, uvm_cpu_chunk_alloc_flags_t flags, + int nid, uvm_cpu_chunk_t **chunk) { uvm_va_block_test_t *block_test = uvm_va_block_get_test(block); - // Return out of memory error if the tests have requested it. As opposed to - // other error injection settings, this one fails N times and then succeeds. - // TODO: Bug 3701182: This will print a warning in Linux kernels newer than - // 5.16.0-rc1+. - if (block_test && block_test->inject_cpu_pages_allocation_error_count) { - if (block_test->inject_cpu_pages_allocation_error_count != ~(NvU32)0) - block_test->inject_cpu_pages_allocation_error_count--; + if (block_test) { + // Return out of memory error if the tests have requested it. As opposed + // to other error injection settings, this one fails N times and then + // succeeds. + // TODO: Bug 3701182: This will print a warning in Linux kernels newer + // than 5.16.0-rc1+. + if (block_test->inject_cpu_pages_allocation_error_count) { + if (block_test->inject_cpu_pages_allocation_error_count != ~(NvU32)0) + block_test->inject_cpu_pages_allocation_error_count--; + return NV_ERR_NO_MEMORY; + } + + if (block_test->cpu_chunk_allocation_actual_id != NUMA_NO_NODE) + nid = block_test->cpu_chunk_allocation_actual_id; + } + + return uvm_cpu_chunk_alloc(alloc_size, flags, nid, chunk); +} + +// Handle insertion of overlapping CPU chunks. +// In cases where the kernel allocates CPU chunks on NUMA nodes that already +// have existing chunks, it's possible that the newly allocated chunk overlaps +// existing chunks. +// In such cases, the newly allocated chunk has to be appropriately split and +// only the non-overlapping subchunks inserted into the block. +// The subchunks, which are not inserted are freed. +// If there is an error during split, insertion, or mapping, any sub-chunks that +// have already been successfully inserted will remain in the block. The rest of +// the sub-chunks will be freed in order to maintain proper refcounts on the +// parent chunk. +static NV_STATUS block_populate_overlapping_cpu_chunks(uvm_va_block_t *block, + uvm_va_block_context_t *block_context, + uvm_cpu_chunk_t *chunk, + uvm_page_index_t page_index) +{ + int nid = uvm_cpu_chunk_get_numa_node(chunk); + uvm_va_block_cpu_node_state_t *node_state = block_node_state_get(block, nid); + uvm_chunk_size_t chunk_size = uvm_cpu_chunk_get_size(chunk); + uvm_va_block_region_t chunk_region = uvm_va_block_chunk_region(block, chunk_size, page_index); + uvm_page_index_t running_page_index; + uvm_cpu_chunk_t **split_chunks; + uvm_cpu_chunk_t **small_chunks = NULL; + uvm_cpu_chunk_t *chunk_ptr; + uvm_page_mask_t *node_pages_mask = &block_context->make_resident.node_pages_mask; + uvm_chunk_size_t split_size; + size_t i; + NV_STATUS status; + + UVM_ASSERT(IS_ALIGNED(uvm_va_block_cpu_page_address(block, page_index), chunk_size)); + + // Get a mask of all the chunk pages that are not overlapping existing + // chunks. + uvm_page_mask_init_from_region(node_pages_mask, chunk_region, NULL); + uvm_page_mask_andnot(node_pages_mask, node_pages_mask, &node_state->allocated); + + split_size = uvm_chunk_find_prev_size(uvm_cpu_chunk_get_allocation_sizes(), chunk_size); + split_chunks = uvm_kvmalloc_zero((chunk_size / split_size) * sizeof(*split_chunks)); + if (!split_chunks) { + uvm_cpu_chunk_free(chunk); return NV_ERR_NO_MEMORY; } - return uvm_cpu_chunk_alloc(alloc_size, flags, chunk); + if (split_size > UVM_PAGE_SIZE_4K) { + small_chunks = uvm_kvmalloc_zero(MAX_SMALL_CHUNKS_PER_BIG_SLOT * sizeof(*small_chunks)); + if (!small_chunks) { + uvm_kvfree(split_chunks); + uvm_cpu_chunk_free(chunk); + return NV_ERR_NO_MEMORY; + } + } + + // If we are here, we have to do at least one split. + // We can't call any of the block_split_cpu_chunk_to_* functions since they + // insert all of the split chunks into the block. + // We only want to insert the sub-chunks that don't overlap. So, we have to + // handle that by calling uvm_cpu_chunk_split() directly. + status = uvm_cpu_chunk_split(chunk, split_chunks); + if (status != NV_OK) + goto done; + + // Insert all split chunks that don't overlap existing allocations. + // Note that this handles both splitting to 64K and 4K. + running_page_index = page_index; + for (i = 0; i < chunk_size / split_size; i++) { + uvm_va_block_region_t subchunk_region = uvm_va_block_chunk_region(block, split_size, running_page_index); + + // - If all the pages covered by the split chunk are missing, insert the + // chunk into the block. + // - If none of the pages are missing, free the chunk. + // - Otherwise, some of the pages covered by the chunk are missing and a + // second split will be needed. + if (uvm_page_mask_region_full(node_pages_mask, subchunk_region)) { + status = uvm_cpu_chunk_insert_in_block(block, split_chunks[i], running_page_index); + if (status != NV_OK) + goto done; + + // To prevent double chunk freeing on error, clear the array pointer + // before mapping. + chunk_ptr = split_chunks[i]; + split_chunks[i] = NULL; + status = uvm_va_block_map_cpu_chunk_on_gpus(block, chunk_ptr, running_page_index); + if (status != NV_OK) + goto done; + } + else if (uvm_page_mask_region_empty(node_pages_mask, subchunk_region)) { + uvm_cpu_chunk_free(split_chunks[i]); + split_chunks[i] = NULL; + } + + running_page_index = subchunk_region.outer; + } + + if (split_size > UVM_PAGE_SIZE_4K) { + // Split any 64K chunks that overlap 4K chunks. + for (i = 0; i < chunk_size / split_size; i++) { + size_t j; + + if (!split_chunks[i]) + continue; + + running_page_index = page_index + ((split_size * i) / PAGE_SIZE); + status = uvm_cpu_chunk_split(split_chunks[i], small_chunks); + if (status != NV_OK) + goto done; + + for (j = 0; j < MAX_SMALL_CHUNKS_PER_BIG_SLOT; j++) { + size_t chunk_num_pages = uvm_cpu_chunk_num_pages(small_chunks[j]); + + if (uvm_page_mask_test(node_pages_mask, running_page_index)) { + status = uvm_cpu_chunk_insert_in_block(block, small_chunks[j], running_page_index); + if (status != NV_OK) + goto done; + + // To prevent double chunk freeing on error, clear the array pointer + // before mapping. + chunk_ptr = small_chunks[j]; + small_chunks[j] = NULL; + status = uvm_va_block_map_cpu_chunk_on_gpus(block, chunk_ptr, running_page_index); + if (status != NV_OK) + goto done; + } + else { + uvm_cpu_chunk_free(small_chunks[j]); + } + + running_page_index += chunk_num_pages; + } + } + } + +done: + if (status != NV_OK) { + // First, free any small chunks that have not been inserted. + if (small_chunks) { + for (i = 0; i < MAX_SMALL_CHUNKS_PER_BIG_SLOT; i++) + uvm_cpu_chunk_free(small_chunks[i]); + } + + // Next, free any large chunks that have not been inserted. + for (i = 0; i < chunk_size / split_size; i++) + uvm_cpu_chunk_free(split_chunks[i]); + } + + uvm_kvfree(small_chunks); + uvm_kvfree(split_chunks); + return status; } // Allocates the input page in the block, if it doesn't already exist @@ -1350,17 +1837,31 @@ static NV_STATUS block_populate_pages_cpu(uvm_va_block_t *block, uvm_chunk_sizes_mask_t cpu_allocation_sizes = uvm_cpu_chunk_get_allocation_sizes(); uvm_chunk_size_t alloc_size; uvm_page_mask_t *resident_mask = &block_context->scratch_page_mask; + uvm_page_mask_t *allocated_mask; uvm_cpu_chunk_alloc_flags_t alloc_flags = UVM_CPU_CHUNK_ALLOC_FLAGS_NONE; uvm_va_space_t *va_space = uvm_va_block_get_va_space(block); uvm_processor_mask_t uvm_lite_gpus; uvm_page_index_t page_index; uvm_gpu_id_t id; + int preferred_nid = block_context->make_resident.dest_nid; + + if (block_test && block_test->cpu_chunk_allocation_target_id != NUMA_NO_NODE) + preferred_nid = block_test->cpu_chunk_allocation_target_id; + + // TODO: Bug 4158598: Using NUMA_NO_NODE for staging allocations is sub-optimal. + if (preferred_nid != NUMA_NO_NODE) { + uvm_va_block_cpu_node_state_t *node_state = block_node_state_get(block, preferred_nid); + allocated_mask = &node_state->allocated; + } + else { + allocated_mask = &block->cpu.allocated; + } // Check whether all requested pages have already been allocated. uvm_page_mask_init_from_region(&block_context->scratch_page_mask, populate_region, populate_page_mask); if (!uvm_page_mask_andnot(&block_context->scratch_page_mask, &block_context->scratch_page_mask, - &block->cpu.allocated)) + allocated_mask)) return NV_OK; if (block_test) { @@ -1369,8 +1870,8 @@ static NV_STATUS block_populate_pages_cpu(uvm_va_block_t *block, } uvm_page_mask_zero(resident_mask); - for_each_id_in_mask (id, &block->resident) - uvm_page_mask_or(resident_mask, resident_mask, uvm_va_block_resident_mask_get(block, id)); + for_each_id_in_mask(id, &block->resident) + uvm_page_mask_or(resident_mask, resident_mask, uvm_va_block_resident_mask_get(block, id, NUMA_NO_NODE)); // If the VA space has a UVM-Lite GPU registered, only PAGE_SIZE allocations // should be used in order to avoid extra copies due to dirty compound @@ -1390,13 +1891,15 @@ static NV_STATUS block_populate_pages_cpu(uvm_va_block_t *block, for_each_va_block_page_in_region_mask(page_index, populate_page_mask, populate_region) { uvm_cpu_chunk_alloc_flags_t chunk_alloc_flags; uvm_va_block_region_t region = populate_region; + uvm_va_block_cpu_node_state_t *node_state; + int alloced_nid; - if (uvm_page_mask_test(&block->cpu.allocated, page_index)) { - page_index = uvm_va_block_next_unset_page_in_mask(populate_region, &block->cpu.allocated, page_index) - 1; + if (uvm_page_mask_test(allocated_mask, page_index)) { + page_index = uvm_va_block_next_unset_page_in_mask(populate_region, allocated_mask, page_index) - 1; continue; } - UVM_ASSERT(!uvm_page_mask_test(&block->cpu.resident, page_index)); + UVM_ASSERT(!uvm_va_block_cpu_is_page_resident_on(block, preferred_nid, page_index)); chunk_alloc_flags = alloc_flags; @@ -1419,7 +1922,7 @@ static NV_STATUS block_populate_pages_cpu(uvm_va_block_t *block, region = uvm_va_block_region_from_start_end(block, alloc_virt_addr, alloc_virt_addr + alloc_size - 1); - if (!uvm_page_mask_region_empty(&block->cpu.allocated, region)) + if (!uvm_page_mask_region_empty(allocated_mask, region)) continue; // If not all pages in the allocation region are resident somewhere, @@ -1430,7 +1933,7 @@ static NV_STATUS block_populate_pages_cpu(uvm_va_block_t *block, if (!uvm_page_mask_region_full(resident_mask, region)) chunk_alloc_flags |= UVM_CPU_CHUNK_ALLOC_FLAGS_ZERO; - status = block_alloc_cpu_chunk(block, alloc_size, chunk_alloc_flags, &chunk); + status = block_alloc_cpu_chunk(block, alloc_size, chunk_alloc_flags, preferred_nid, &chunk); if (status == NV_OK) { page_index = region.first; break; @@ -1442,22 +1945,39 @@ static NV_STATUS block_populate_pages_cpu(uvm_va_block_t *block, if (status != NV_OK) break; - status = uvm_cpu_chunk_insert_in_block(block, chunk, page_index); - if (status != NV_OK) { - uvm_cpu_chunk_free(chunk); - return status; + alloced_nid = uvm_cpu_chunk_get_numa_node(chunk); + node_state = block_node_state_get(block, alloced_nid); + if (!uvm_page_mask_region_empty(&node_state->allocated, region)) { + UVM_ASSERT(preferred_nid != NUMA_NO_NODE); + + if (uvm_page_mask_region_full(&node_state->allocated, region)) { + uvm_cpu_chunk_free(chunk); + goto skip; + } + + status = block_populate_overlapping_cpu_chunks(block, block_context, chunk, page_index); + if (status != NV_OK) + return status; } + else { + status = uvm_cpu_chunk_insert_in_block(block, chunk, page_index); + if (status != NV_OK) { + uvm_cpu_chunk_free(chunk); + return status; + } - status = uvm_va_block_map_cpu_chunk_on_gpus(block, page_index); - if (status != NV_OK) - break; + status = uvm_va_block_map_cpu_chunk_on_gpus(block, chunk, page_index); + if (status != NV_OK) + break; + } +skip: // Skip iterating over all pages covered by the allocated chunk. page_index = region.outer - 1; } if (status != NV_OK && chunk) { - uvm_cpu_chunk_remove_from_block(block, page_index); + uvm_cpu_chunk_remove_from_block(block, uvm_cpu_chunk_get_numa_node(chunk), page_index); uvm_cpu_chunk_free(chunk); } @@ -1742,9 +2262,10 @@ static NvU32 block_phys_page_size(uvm_va_block_t *block, block_phys_page_t page) uvm_chunk_size_t chunk_size; if (UVM_ID_IS_CPU(page.processor)) { - uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(block, page.page_index); + uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(block, page.nid, page.page_index); + uvm_page_mask_t *resident_mask = uvm_va_block_resident_mask_get(block, page.processor, NUMA_NO_NODE); - if (!uvm_page_mask_test(&block->cpu.resident, page.page_index)) + if (!uvm_page_mask_test(resident_mask, page.page_index)) return 0; UVM_ASSERT(uvm_processor_mask_test(&block->resident, UVM_ID_CPU)); @@ -1791,29 +2312,41 @@ static uvm_pte_bits_gpu_t get_gpu_pte_bit_index(uvm_prot_t prot) return pte_bit_index; } -uvm_page_mask_t *uvm_va_block_resident_mask_get(uvm_va_block_t *block, uvm_processor_id_t processor) +uvm_page_mask_t *uvm_va_block_resident_mask_get(uvm_va_block_t *block, uvm_processor_id_t processor, int nid) { uvm_va_block_gpu_state_t *gpu_state; + uvm_page_mask_t *resident_mask; - if (UVM_ID_IS_CPU(processor)) - return &block->cpu.resident; + if (UVM_ID_IS_CPU(processor)) { + uvm_va_block_cpu_node_state_t *node_state; - gpu_state = uvm_va_block_gpu_state_get(block, processor); + if (nid == NUMA_NO_NODE) { + resident_mask = &block->cpu.resident; + } + else { + node_state = block_node_state_get(block, nid); + resident_mask = &node_state->resident; + } + } + else { + gpu_state = uvm_va_block_gpu_state_get(block, processor); + UVM_ASSERT(gpu_state); + resident_mask = &gpu_state->resident; + } - UVM_ASSERT(gpu_state); - return &gpu_state->resident; + return resident_mask; } // Get the page residency mask for a processor // // Notably this will allocate GPU state if not yet present and if that fails // NULL is returned. -static uvm_page_mask_t *block_resident_mask_get_alloc(uvm_va_block_t *block, uvm_processor_id_t processor) +static uvm_page_mask_t *block_resident_mask_get_alloc(uvm_va_block_t *block, uvm_processor_id_t processor, int nid) { uvm_va_block_gpu_state_t *gpu_state; if (UVM_ID_IS_CPU(processor)) - return &block->cpu.resident; + return uvm_va_block_resident_mask_get(block, processor, nid); gpu_state = block_gpu_state_get_alloc(block, block_get_gpu(block, processor)); if (!gpu_state) @@ -1842,6 +2375,28 @@ const uvm_page_mask_t *uvm_va_block_map_mask_get(uvm_va_block_t *block, uvm_proc return block_map_with_prot_mask_get(block, processor, UVM_PROT_READ_ONLY); } +void uvm_va_block_unmapped_pages_get(uvm_va_block_t *va_block, + uvm_va_block_region_t region, + uvm_page_mask_t *out_mask) +{ + uvm_processor_mask_t non_uvm_lite_gpus; + uvm_processor_id_t id; + + uvm_assert_mutex_locked(&va_block->lock); + + if (!uvm_va_block_is_hmm(va_block)) { + uvm_page_mask_complement(out_mask, &va_block->maybe_mapped_pages); + return; + } + + uvm_page_mask_region_fill(out_mask, region); + uvm_processor_mask_andnot(&non_uvm_lite_gpus, &va_block->mapped, block_get_uvm_lite_gpus(va_block)); + + for_each_id_in_mask(id, &non_uvm_lite_gpus) { + uvm_page_mask_andnot(out_mask, out_mask, uvm_va_block_map_mask_get(va_block, id)); + } +} + static const uvm_page_mask_t *block_evicted_mask_get(uvm_va_block_t *block, uvm_gpu_id_t gpu_id) { uvm_va_block_gpu_state_t *gpu_state = uvm_va_block_gpu_state_get(block, gpu_id); @@ -1854,7 +2409,7 @@ static bool block_is_page_resident_anywhere(uvm_va_block_t *block, uvm_page_inde { uvm_processor_id_t id; for_each_id_in_mask(id, &block->resident) { - if (uvm_page_mask_test(uvm_va_block_resident_mask_get(block, id), page_index)) + if (uvm_page_mask_test(uvm_va_block_resident_mask_get(block, id, NUMA_NO_NODE), page_index)) return true; } @@ -1877,24 +2432,6 @@ static bool block_processor_page_is_populated(uvm_va_block_t *block, uvm_process return gpu_state->chunks[chunk_index] != NULL; } -static bool block_processor_page_is_resident_on(uvm_va_block_t *block, uvm_processor_id_t proc, uvm_page_index_t page_index) -{ - const uvm_page_mask_t *resident_mask; - - if (UVM_ID_IS_CPU(proc)) { - resident_mask = &block->cpu.resident; - } - else { - uvm_va_block_gpu_state_t *gpu_state = uvm_va_block_gpu_state_get(block, proc); - if (!gpu_state) - return false; - - resident_mask = &gpu_state->resident; - } - - return uvm_page_mask_test(resident_mask, page_index); -} - // Compute the gpus that have at least the given access permissions for the // range described by region and page_mask. The function sets the bit if any // page in the region has the permissions. @@ -2007,7 +2544,7 @@ static void block_page_resident_gpus(uvm_va_block_t *va_block, uvm_processor_mask_zero(resident_gpus); for_each_gpu_id_in_mask(id, &va_block->resident) { - if (uvm_page_mask_test(uvm_va_block_resident_mask_get(va_block, id), page_index)) { + if (uvm_page_mask_test(uvm_va_block_resident_mask_get(va_block, id, NUMA_NO_NODE), page_index)) { UVM_ASSERT(block_processor_page_is_populated(va_block, id, page_index)); uvm_processor_mask_set(resident_gpus, id); } @@ -2020,7 +2557,7 @@ void uvm_va_block_page_resident_processors(uvm_va_block_t *va_block, { block_page_resident_gpus(va_block, page_index, resident_processors); - if (uvm_page_mask_test(uvm_va_block_resident_mask_get(va_block, UVM_ID_CPU), page_index)) { + if (uvm_page_mask_test(uvm_va_block_resident_mask_get(va_block, UVM_ID_CPU, NUMA_NO_NODE), page_index)) { UVM_ASSERT(block_processor_page_is_populated(va_block, UVM_ID_CPU, page_index)); uvm_processor_mask_set(resident_processors, UVM_ID_CPU); } @@ -2049,7 +2586,7 @@ static uvm_processor_id_t block_page_get_closest_resident_in_mask(uvm_va_block_t uvm_processor_mask_copy(&search_mask, &va_block->resident); for_each_closest_id(id, &search_mask, processor, va_space) { - if (uvm_page_mask_test(uvm_va_block_resident_mask_get(va_block, id), page_index)) + if (uvm_page_mask_test(uvm_va_block_resident_mask_get(va_block, id, NUMA_NO_NODE), page_index)) return id; } @@ -2245,7 +2782,7 @@ static NV_STATUS block_zero_new_gpu_chunk(uvm_va_block_t *block, // Roll up all pages in chunk_region which are resident somewhere uvm_page_mask_zero(zero_mask); for_each_id_in_mask(id, &block->resident) - uvm_page_mask_or(zero_mask, zero_mask, uvm_va_block_resident_mask_get(block, id)); + uvm_page_mask_or(zero_mask, zero_mask, uvm_va_block_resident_mask_get(block, id, NUMA_NO_NODE)); // If all pages in the chunk are resident somewhere, we don't need to clear // anything. Just make sure the chunk is tracked properly. @@ -2434,6 +2971,13 @@ static NV_STATUS block_populate_pages_gpu(uvm_va_block_t *block, return NV_OK; } +static const uvm_processor_mask_t *block_get_can_copy_from_mask(uvm_va_block_t *block, uvm_processor_id_t from) +{ + uvm_va_space_t *va_space = uvm_va_block_get_va_space(block); + + return &va_space->can_copy_from[uvm_id_value(from)]; +} + static NV_STATUS block_populate_pages(uvm_va_block_t *block, uvm_va_block_retry_t *retry, uvm_va_block_context_t *block_context, @@ -2442,8 +2986,10 @@ static NV_STATUS block_populate_pages(uvm_va_block_t *block, const uvm_page_mask_t *page_mask) { NV_STATUS status; - const uvm_page_mask_t *resident_mask = block_resident_mask_get_alloc(block, dest_id); + const uvm_page_mask_t *resident_mask = block_resident_mask_get_alloc(block, dest_id, NUMA_NO_NODE); uvm_page_mask_t *populate_page_mask = &block_context->make_resident.page_mask; + uvm_page_mask_t *pages_staged = &block_context->make_resident.pages_staged; + uvm_page_mask_t *cpu_populate_mask; uvm_memcg_context_t memcg_context; if (!resident_mask) @@ -2454,22 +3000,58 @@ static NV_STATUS block_populate_pages(uvm_va_block_t *block, else uvm_page_mask_complement(populate_page_mask, resident_mask); - if (UVM_ID_IS_GPU(dest_id)) - return block_populate_pages_gpu(block, retry, block_get_gpu(block, dest_id), region, populate_page_mask); + if (UVM_ID_IS_GPU(dest_id)) { + uvm_processor_mask_t staged_processors; + uvm_processor_mask_t accessible_resident_processors; + const uvm_processor_mask_t *can_copy_from_processors; + uvm_page_mask_t *scratch_page_mask = &block_context->scratch_page_mask; + uvm_page_mask_t *id_resident_mask; + uvm_processor_id_t id; + + status = block_populate_pages_gpu(block, retry, block_get_gpu(block, dest_id), region, populate_page_mask); + if (status != NV_OK) + return status; + + uvm_page_mask_zero(pages_staged); + + // Get the mask of all processors that have resident pages from which + // the destination cannot copy directly. + can_copy_from_processors = block_get_can_copy_from_mask(block, dest_id); + if (!uvm_processor_mask_andnot(&staged_processors, &block->resident, can_copy_from_processors)) + return status; + + // Compute the pages that will be staged through the CPU by: + // 1. Computing all of the pages resident on the processors from which + // dest_id cannot directly copy. + for_each_id_in_mask(id, &staged_processors) { + id_resident_mask = uvm_va_block_resident_mask_get(block, id, NUMA_NO_NODE); + uvm_page_mask_and(scratch_page_mask, populate_page_mask, id_resident_mask); + uvm_page_mask_or(pages_staged, pages_staged, scratch_page_mask); + } + + // 2. Remove any pages in pages_staged that are on any resident processor + // dest_id can copy from. + if (uvm_processor_mask_and(&accessible_resident_processors, can_copy_from_processors, &block->resident)) { + for_each_id_in_mask(id, &accessible_resident_processors) { + id_resident_mask = uvm_va_block_resident_mask_get(block, id, NUMA_NO_NODE); + uvm_page_mask_andnot(pages_staged, pages_staged, id_resident_mask); + } + } + + // 3. Removing any pages not in the populate mask. + uvm_page_mask_region_clear_outside(pages_staged, region); + cpu_populate_mask = pages_staged; + } + else { + cpu_populate_mask = populate_page_mask; + } uvm_memcg_context_start(&memcg_context, block_context->mm); - status = block_populate_pages_cpu(block, populate_page_mask, region, block_context); + status = block_populate_pages_cpu(block, cpu_populate_mask, region, block_context); uvm_memcg_context_end(&memcg_context); return status; } -static const uvm_processor_mask_t *block_get_can_copy_from_mask(uvm_va_block_t *block, uvm_processor_id_t from) -{ - uvm_va_space_t *va_space = uvm_va_block_get_va_space(block); - - return &va_space->can_copy_from[uvm_id_value(from)]; -} - static bool block_can_copy_from(uvm_va_block_t *va_block, uvm_processor_id_t from, uvm_processor_id_t to) { return uvm_processor_mask_test(block_get_can_copy_from_mask(va_block, to), from); @@ -2513,7 +3095,7 @@ static uvm_gpu_phys_address_t block_phys_page_address(uvm_va_block_t *block, UVM_ASSERT(accessing_gpu_state); if (UVM_ID_IS_CPU(block_page.processor)) { - uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(block, block_page.page_index); + uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(block, block_page.nid, block_page.page_index); NvU64 dma_addr = uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent); uvm_va_block_region_t chunk_region = uvm_va_block_chunk_region(block, uvm_cpu_chunk_get_size(chunk), @@ -2588,9 +3170,15 @@ uvm_gpu_phys_address_t uvm_va_block_res_phys_page_address(uvm_va_block_t *va_blo uvm_processor_id_t residency, uvm_gpu_t *gpu) { + int nid = NUMA_NO_NODE; + uvm_assert_mutex_locked(&va_block->lock); + if (UVM_ID_IS_CPU(residency)) { + nid = block_get_page_node_residency(va_block, page_index); + UVM_ASSERT(nid != NUMA_NO_NODE); + } - return block_phys_page_address(va_block, block_phys_page(residency, page_index), gpu); + return block_phys_page_address(va_block, block_phys_page(residency, nid, page_index), gpu); } uvm_gpu_phys_address_t uvm_va_block_gpu_phys_page_address(uvm_va_block_t *va_block, @@ -2605,6 +3193,9 @@ typedef struct // Location of the memory uvm_processor_id_t id; + // NUMA node ID if the processor is the CPU. Ignored otherwise. + int nid; + // Whether the whole block has a single physically-contiguous chunk of // storage on the processor. bool is_block_contig; @@ -2734,13 +3325,14 @@ static NV_STATUS block_copy_begin_push(uvm_va_block_t *va_block, static bool block_page_is_clean(uvm_va_block_t *block, uvm_processor_id_t dst_id, uvm_processor_id_t src_id, - uvm_page_index_t page_index) + uvm_page_index_t page_index, + int nid) { return !uvm_va_block_is_hmm(block) && uvm_id_equal(dst_id, uvm_va_range_get_policy(block->va_range)->preferred_location) && UVM_ID_IS_CPU(src_id) && !block_get_gpu(block, dst_id)->parent->isr.replayable_faults.handling && - !block_cpu_page_is_dirty(block, page_index); + !block_cpu_page_is_dirty(block, page_index, nid); } // When the destination is the CPU... @@ -2749,15 +3341,16 @@ static bool block_page_is_clean(uvm_va_block_t *block, static void block_update_page_dirty_state(uvm_va_block_t *block, uvm_processor_id_t dst_id, uvm_processor_id_t src_id, + int nid, uvm_page_index_t page_index) { if (UVM_ID_IS_GPU(dst_id)) return; if (uvm_id_equal(src_id, uvm_va_range_get_policy(block->va_range)->preferred_location)) - block_mark_cpu_page_clean(block, page_index); + block_mark_cpu_page_clean(block, page_index, nid); else - block_mark_cpu_page_dirty(block, page_index); + block_mark_cpu_page_dirty(block, page_index, nid); } static void block_mark_memory_used(uvm_va_block_t *block, uvm_processor_id_t id) @@ -2783,7 +3376,7 @@ static void block_mark_memory_used(uvm_va_block_t *block, uvm_processor_id_t id) static void block_set_resident_processor(uvm_va_block_t *block, uvm_processor_id_t id) { - UVM_ASSERT(!uvm_page_mask_empty(uvm_va_block_resident_mask_get(block, id))); + UVM_ASSERT(!uvm_page_mask_empty(uvm_va_block_resident_mask_get(block, id, NUMA_NO_NODE))); if (uvm_processor_mask_test_and_set(&block->resident, id)) return; @@ -2795,7 +3388,7 @@ static void block_clear_resident_processor(uvm_va_block_t *block, uvm_processor_ { uvm_gpu_t *gpu; - UVM_ASSERT(uvm_page_mask_empty(uvm_va_block_resident_mask_get(block, id))); + UVM_ASSERT(uvm_page_mask_empty(uvm_va_block_resident_mask_get(block, id, NUMA_NO_NODE))); if (!uvm_processor_mask_test_and_clear(&block->resident, id)) return; @@ -2821,37 +3414,41 @@ static bool block_phys_copy_contig_check(uvm_va_block_t *block, uvm_page_index_t page_index, const uvm_gpu_address_t *base_address, uvm_processor_id_t proc_id, + int nid, uvm_gpu_t *copying_gpu) { uvm_gpu_address_t page_address; uvm_gpu_address_t contig_address = *base_address; contig_address.address += page_index * PAGE_SIZE; - - page_address = block_phys_page_copy_address(block, block_phys_page(proc_id, page_index), copying_gpu); + page_address = block_phys_page_copy_address(block, block_phys_page(proc_id, nid, page_index), copying_gpu); return uvm_gpu_addr_cmp(page_address, contig_address) == 0; } // Check if the VA block has a single physically-contiguous chunk of storage // on the processor. -static bool is_block_phys_contig(uvm_va_block_t *block, uvm_processor_id_t id) +static bool is_block_phys_contig(uvm_va_block_t *block, uvm_processor_id_t id, int nid) { uvm_cpu_chunk_t *chunk; if (UVM_ID_IS_GPU(id)) return uvm_va_block_size(block) == block_gpu_chunk_size(block, block_get_gpu(block, id), 0); - chunk = uvm_cpu_chunk_first_in_region(block, uvm_va_block_region_from_block(block), NULL); + UVM_ASSERT(nid != NUMA_NO_NODE); + chunk = uvm_cpu_chunk_first_in_region(block, uvm_va_block_region_from_block(block), nid, NULL); return chunk && (uvm_va_block_size(block) == uvm_cpu_chunk_get_size(chunk)); } static uvm_va_block_region_t block_phys_contig_region(uvm_va_block_t *block, uvm_page_index_t page_index, - uvm_processor_id_t resident_id) + uvm_processor_id_t resident_id, + int nid) { if (UVM_ID_IS_CPU(resident_id)) { - uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(block, page_index); + uvm_cpu_chunk_t *chunk; + UVM_ASSERT(nid != NUMA_NO_NODE); + chunk = uvm_cpu_chunk_get_chunk_for_page(block, nid, page_index); return uvm_cpu_chunk_block_region(block, chunk, page_index); } else { @@ -2871,11 +3468,11 @@ static uvm_gpu_address_t block_copy_get_address(uvm_va_block_t *block, if (bca->is_block_contig) { uvm_gpu_address_t addr = bca->gpu_address; addr.address += page_index * PAGE_SIZE; - UVM_ASSERT(block_phys_copy_contig_check(block, page_index, &bca->gpu_address, bca->id, copying_gpu)); + UVM_ASSERT(block_phys_copy_contig_check(block, page_index, &bca->gpu_address, bca->id, bca->nid, copying_gpu)); return addr; } - return block_phys_page_copy_address(block, block_phys_page(bca->id, page_index), copying_gpu); + return block_phys_page_copy_address(block, block_phys_page(bca->id, bca->nid, page_index), copying_gpu); } // When the Confidential Computing feature is enabled, the function performs @@ -2886,17 +3483,19 @@ static void conf_computing_block_copy_push_cpu_to_gpu(uvm_va_block_t *block, uvm_va_block_region_t region, uvm_push_t *push) { - uvm_push_flag_t membar_flag = 0; + uvm_push_flag_t push_membar_flag = UVM_PUSH_FLAG_COUNT; uvm_gpu_t *gpu = uvm_push_get_gpu(push); uvm_page_index_t page_index = region.first; uvm_conf_computing_dma_buffer_t *dma_buffer = copy_state->dma_buffer; - struct page *src_page = uvm_cpu_chunk_get_cpu_page(block, page_index); + struct page *src_page; uvm_gpu_address_t staging_buffer = uvm_mem_gpu_address_virtual_kernel(dma_buffer->alloc, gpu); uvm_gpu_address_t auth_tag_buffer = uvm_mem_gpu_address_virtual_kernel(dma_buffer->auth_tag, gpu); char *cpu_auth_tag_buffer = (char *)uvm_mem_get_cpu_addr_kernel(dma_buffer->auth_tag) + (page_index * UVM_CONF_COMPUTING_AUTH_TAG_SIZE); uvm_gpu_address_t dst_address = block_copy_get_address(block, ©_state->dst, page_index, gpu); char *cpu_va_staging_buffer = (char *)uvm_mem_get_cpu_addr_kernel(dma_buffer->alloc) + (page_index * PAGE_SIZE); + uvm_cpu_chunk_t *chunk; + uvm_va_block_region_t chunk_region; UVM_ASSERT(UVM_ID_IS_CPU(copy_state->src.id)); UVM_ASSERT(UVM_ID_IS_GPU(copy_state->dst.id)); @@ -2906,23 +3505,27 @@ static void conf_computing_block_copy_push_cpu_to_gpu(uvm_va_block_t *block, // See comment in block_copy_begin_push. UVM_ASSERT(uvm_tracker_is_completed(&block->tracker)); + chunk = uvm_cpu_chunk_get_chunk_for_page(block, copy_state->src.nid, page_index); + UVM_ASSERT(chunk); + // The caller guarantees that all pages in region are contiguous, + // meaning they're guaranteed to be part of the same compound page. + chunk_region = uvm_va_block_chunk_region(block, uvm_cpu_chunk_get_size(chunk), page_index); + UVM_ASSERT(uvm_va_block_region_contains_region(region, chunk_region)); + + src_page = uvm_cpu_chunk_get_cpu_page(block, chunk, page_index); staging_buffer.address += page_index * PAGE_SIZE; auth_tag_buffer.address += page_index * UVM_CONF_COMPUTING_AUTH_TAG_SIZE; if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE)) - membar_flag = UVM_PUSH_FLAG_NEXT_MEMBAR_NONE; + push_membar_flag = UVM_PUSH_FLAG_NEXT_MEMBAR_NONE; else if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU)) - membar_flag = UVM_PUSH_FLAG_NEXT_MEMBAR_GPU; + push_membar_flag = UVM_PUSH_FLAG_NEXT_MEMBAR_GPU; // kmap() only guarantees PAGE_SIZE contiguity, all encryption and // decryption must happen on a PAGE_SIZE basis. for_each_va_block_page_in_region(page_index, region) { void *src_cpu_virt_addr; - // The caller guarantees that all pages in region are contiguous, - // meaning they're guaranteed to be part of the same compound page. - UVM_ASSERT(src_page == uvm_cpu_chunk_get_cpu_page(block, page_index)); - src_cpu_virt_addr = kmap(src_page); uvm_conf_computing_cpu_encrypt(push->channel, cpu_va_staging_buffer, @@ -2942,8 +3545,8 @@ static void conf_computing_block_copy_push_cpu_to_gpu(uvm_va_block_t *block, if (page_index < (region.outer - 1)) uvm_push_set_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); - else if (membar_flag) - uvm_push_set_flag(push, membar_flag); + else if (push_membar_flag != UVM_PUSH_FLAG_COUNT) + uvm_push_set_flag(push, push_membar_flag); gpu->parent->ce_hal->decrypt(push, dst_address, staging_buffer, PAGE_SIZE, auth_tag_buffer); @@ -2964,7 +3567,7 @@ static void conf_computing_block_copy_push_gpu_to_cpu(uvm_va_block_t *block, uvm_va_block_region_t region, uvm_push_t *push) { - uvm_push_flag_t membar_flag = 0; + uvm_push_flag_t push_membar_flag = UVM_PUSH_FLAG_COUNT; uvm_gpu_t *gpu = uvm_push_get_gpu(push); uvm_page_index_t page_index = region.first; uvm_conf_computing_dma_buffer_t *dma_buffer = copy_state->dma_buffer; @@ -2981,9 +3584,9 @@ static void conf_computing_block_copy_push_gpu_to_cpu(uvm_va_block_t *block, auth_tag_buffer.address += page_index * UVM_CONF_COMPUTING_AUTH_TAG_SIZE; if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE)) - membar_flag = UVM_PUSH_FLAG_NEXT_MEMBAR_NONE; + push_membar_flag = UVM_PUSH_FLAG_NEXT_MEMBAR_NONE; else if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU)) - membar_flag = UVM_PUSH_FLAG_NEXT_MEMBAR_GPU; + push_membar_flag = UVM_PUSH_FLAG_NEXT_MEMBAR_GPU; // Because we use kmap() for mapping pages for CPU side // crypto-operations and it only guarantees PAGE_SIZE contiguity, all @@ -3001,8 +3604,8 @@ static void conf_computing_block_copy_push_gpu_to_cpu(uvm_va_block_t *block, if (page_index < (region.outer - 1)) uvm_push_set_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); - else if (membar_flag) - uvm_push_set_flag(push, membar_flag); + else if (push_membar_flag != UVM_PUSH_FLAG_COUNT) + uvm_push_set_flag(push, push_membar_flag); gpu->parent->ce_hal->encrypt(push, staging_buffer, src_address, PAGE_SIZE, auth_tag_buffer); @@ -3039,7 +3642,7 @@ static NV_STATUS conf_computing_copy_pages_finish(uvm_va_block_t *block, // kmap() only guarantees PAGE_SIZE contiguity, all encryption and // decryption must happen on a PAGE_SIZE basis. for_each_va_block_page_in_mask(page_index, encrypted_page_mask, block) { - struct page *dst_page = uvm_cpu_chunk_get_cpu_page(block, page_index); + struct page *dst_page = uvm_va_block_get_cpu_page(block, page_index); void *staging_buffer = (char *)staging_buffer_base + (page_index * PAGE_SIZE); void *auth_tag_buffer = (char *)auth_tag_buffer_base + (page_index * UVM_CONF_COMPUTING_AUTH_TAG_SIZE); void *cpu_page_address = kmap(dst_page); @@ -3135,7 +3738,9 @@ static NV_STATUS block_copy_end_push(uvm_va_block_t *block, static NV_STATUS block_copy_resident_pages_between(uvm_va_block_t *block, uvm_va_block_context_t *block_context, uvm_processor_id_t dst_id, + int dst_nid, uvm_processor_id_t src_id, + int src_nid, uvm_va_block_region_t region, uvm_page_mask_t *copy_mask, const uvm_page_mask_t *prefetch_page_mask, @@ -3145,7 +3750,7 @@ static NV_STATUS block_copy_resident_pages_between(uvm_va_block_t *block, uvm_tracker_t *copy_tracker) { NV_STATUS status = NV_OK; - uvm_page_mask_t *dst_resident_mask = uvm_va_block_resident_mask_get(block, dst_id); + uvm_page_mask_t *dst_resident_mask = uvm_va_block_resident_mask_get(block, dst_id, dst_nid); uvm_gpu_t *copying_gpu = NULL; uvm_push_t push; uvm_page_index_t page_index; @@ -3162,18 +3767,31 @@ static NV_STATUS block_copy_resident_pages_between(uvm_va_block_t *block, uvm_va_range_t *va_range = block->va_range; uvm_va_space_t *va_space = uvm_va_block_get_va_space(block); - copy_state.src.id = src_id; - copy_state.dst.id = dst_id; - copy_state.src.is_block_contig = is_block_phys_contig(block, src_id); - copy_state.dst.is_block_contig = is_block_phys_contig(block, dst_id); - *copied_pages = 0; + UVM_ASSERT(UVM_ID_IS_GPU(src_id) || UVM_ID_IS_GPU(dst_id)); + + if (UVM_ID_IS_CPU(src_id)) + UVM_ASSERT(src_nid != NUMA_NO_NODE); + + if (UVM_ID_IS_CPU(dst_id)) + UVM_ASSERT(dst_nid != NUMA_NO_NODE); + // If there are no pages to be copied, exit early - if (!uvm_page_mask_andnot(copy_mask, copy_mask, dst_resident_mask) || - !uvm_page_mask_andnot(copy_mask, copy_mask, migrated_pages)) + if (!uvm_page_mask_andnot(copy_mask, copy_mask, dst_resident_mask)) return NV_OK; + if (migrated_pages && !uvm_page_mask_andnot(copy_mask, copy_mask, migrated_pages)) + return NV_OK; + + copy_state.src.id = src_id; + copy_state.dst.id = dst_id; + copy_state.src.nid = src_nid; + copy_state.dst.nid = dst_nid; + + copy_state.src.is_block_contig = is_block_phys_contig(block, src_id, copy_state.src.nid); + copy_state.dst.is_block_contig = is_block_phys_contig(block, dst_id, copy_state.dst.nid); + // uvm_range_group_range_iter_first should only be called when the va_space // lock is held, which is always the case unless an eviction is taking // place. @@ -3184,19 +3802,6 @@ static NV_STATUS block_copy_resident_pages_between(uvm_va_block_t *block, rgr_has_changed = true; } - if (UVM_ID_IS_CPU(dst_id)) { - uvm_memcg_context_t memcg_context; - - // To support staging through CPU, populate CPU pages on demand. - // GPU destinations should have their pages populated already, but - // that might change if we add staging through GPUs. - uvm_memcg_context_start(&memcg_context, block_context->mm); - status = block_populate_pages_cpu(block, copy_mask, region, block_context); - uvm_memcg_context_end(&memcg_context); - if (status != NV_OK) - return status; - } - // TODO: Bug 3745051: This function is complicated and needs refactoring for_each_va_block_page_in_region_mask(page_index, copy_mask, region) { NvU64 page_start = uvm_va_block_cpu_page_address(block, page_index); @@ -3244,7 +3849,7 @@ static NV_STATUS block_copy_resident_pages_between(uvm_va_block_t *block, // No need to copy pages that haven't changed. Just clear residency // information - if (block_page_is_clean(block, dst_id, src_id, page_index)) + if (block_page_is_clean(block, dst_id, src_id, page_index, copy_state.src.nid)) continue; if (!copying_gpu) { @@ -3270,7 +3875,7 @@ static NV_STATUS block_copy_resident_pages_between(uvm_va_block_t *block, } if (!uvm_va_block_is_hmm(block)) - block_update_page_dirty_state(block, dst_id, src_id, page_index); + block_update_page_dirty_state(block, dst_id, src_id, copy_state.dst.nid, page_index); if (last_index == region.outer) { bool can_cache_src_phys_addr = copy_state.src.is_block_contig; @@ -3291,12 +3896,16 @@ static NV_STATUS block_copy_resident_pages_between(uvm_va_block_t *block, // using the page index. if (can_cache_src_phys_addr) { copy_state.src.gpu_address = block_phys_page_copy_address(block, - block_phys_page(src_id, 0), + block_phys_page(src_id, + copy_state.src.nid, + 0), copying_gpu); } if (can_cache_dst_phys_addr) { copy_state.dst.gpu_address = block_phys_page_copy_address(block, - block_phys_page(dst_id, 0), + block_phys_page(dst_id, + copy_state.dst.nid, + 0), copying_gpu); } } @@ -3359,12 +3968,87 @@ static NV_STATUS block_copy_resident_pages_between(uvm_va_block_t *block, uvm_page_mask_region_clear(copy_mask, uvm_va_block_region(page_index, PAGES_PER_UVM_VA_BLOCK)); *copied_pages = uvm_page_mask_weight(copy_mask); - if (*copied_pages) + if (*copied_pages && migrated_pages) uvm_page_mask_or(migrated_pages, migrated_pages, copy_mask); return status; } +static NV_STATUS block_copy_resident_pages_from(uvm_va_block_t *block, + uvm_va_block_context_t *block_context, + uvm_processor_id_t dst_id, + uvm_processor_id_t src_id, + int src_nid, + uvm_va_block_region_t region, + const uvm_page_mask_t *page_mask, + const uvm_page_mask_t *prefetch_page_mask, + uvm_va_block_transfer_mode_t transfer_mode, + uvm_page_mask_t *migrated_pages, + NvU32 *copied_pages_out, + uvm_tracker_t *copy_tracker) +{ + uvm_page_mask_t *copy_mask = &block_context->make_resident.copy_resident_pages_mask; + uvm_page_mask_t *src_resident_mask; + uvm_page_mask_t *node_pages_mask = &block_context->make_resident.node_pages_mask; + uvm_make_resident_page_tracking_t *page_tracking = &block_context->make_resident.cpu_pages_used; + NvU32 copied_pages_from_src; + NV_STATUS status = NV_OK; + int dst_nid; + + src_resident_mask = uvm_va_block_resident_mask_get(block, src_id, src_nid); + uvm_page_mask_init_from_region(copy_mask, region, src_resident_mask); + + if (page_mask) + uvm_page_mask_and(copy_mask, copy_mask, page_mask); + + if (UVM_ID_IS_CPU(dst_id)) { + for_each_node_mask(dst_nid, page_tracking->nodes) { + if (!uvm_page_mask_and(node_pages_mask, copy_mask, page_tracking->node_masks[node_to_index(dst_nid)])) + continue; + + status = block_copy_resident_pages_between(block, + block_context, + dst_id, + dst_nid, + src_id, + src_nid, + region, + node_pages_mask, + prefetch_page_mask, + transfer_mode, + migrated_pages, + &copied_pages_from_src, + copy_tracker); + + *copied_pages_out += copied_pages_from_src; + + if (status != NV_OK) + break; + + if (!uvm_page_mask_andnot(copy_mask, copy_mask, node_pages_mask)) + break; + } + } + else { + status = block_copy_resident_pages_between(block, + block_context, + dst_id, + NUMA_NO_NODE, + src_id, + src_nid, + region, + copy_mask, + prefetch_page_mask, + transfer_mode, + migrated_pages, + &copied_pages_from_src, + copy_tracker); + *copied_pages_out += copied_pages_from_src; + } + + return status; +} + // Copy resident pages to the destination from all source processors in the // src_processor_mask // @@ -3387,36 +4071,53 @@ static NV_STATUS block_copy_resident_pages_mask(uvm_va_block_t *block, uvm_va_space_t *va_space = uvm_va_block_get_va_space(block); uvm_processor_id_t src_id; uvm_processor_mask_t search_mask; - uvm_page_mask_t *copy_mask = &block_context->make_resident.copy_resident_pages_mask; uvm_processor_mask_copy(&search_mask, src_processor_mask); *copied_pages_out = 0; for_each_closest_id(src_id, &search_mask, dst_id, va_space) { - uvm_page_mask_t *src_resident_mask = uvm_va_block_resident_mask_get(block, src_id); NV_STATUS status; - NvU32 copied_pages_from_src; UVM_ASSERT(!uvm_id_equal(src_id, dst_id)); - uvm_page_mask_init_from_region(copy_mask, region, src_resident_mask); + if (UVM_ID_IS_CPU(src_id)) { + int nid; + + for_each_possible_uvm_node(nid) { + status = block_copy_resident_pages_from(block, + block_context, + dst_id, + src_id, + nid, + region, + page_mask, + prefetch_page_mask, + transfer_mode, + migrated_pages, + copied_pages_out, + tracker_out); - if (page_mask) - uvm_page_mask_and(copy_mask, copy_mask, page_mask); + if (status != NV_OK) + break; + } + } + else { + status = block_copy_resident_pages_from(block, + block_context, + dst_id, + src_id, + NUMA_NO_NODE, + region, + page_mask, + prefetch_page_mask, + transfer_mode, + migrated_pages, + copied_pages_out, + tracker_out); + + } - status = block_copy_resident_pages_between(block, - block_context, - dst_id, - src_id, - region, - copy_mask, - prefetch_page_mask, - transfer_mode, - migrated_pages, - &copied_pages_from_src, - tracker_out); - *copied_pages_out += copied_pages_from_src; UVM_ASSERT(*copied_pages_out <= max_pages_to_copy); if (status != NV_OK) @@ -3441,7 +4142,8 @@ static void break_read_duplication_in_region(uvm_va_block_t *block, uvm_page_mask_init_from_region(break_pages_in_region, region, page_mask); - UVM_ASSERT(uvm_page_mask_subset(break_pages_in_region, uvm_va_block_resident_mask_get(block, dst_id))); + UVM_ASSERT( + uvm_page_mask_subset(break_pages_in_region, uvm_va_block_resident_mask_get(block, dst_id, NUMA_NO_NODE))); // Clear read_duplicated bit for all pages in region uvm_page_mask_andnot(&block->read_duplicated_pages, &block->read_duplicated_pages, break_pages_in_region); @@ -3453,9 +4155,20 @@ static void break_read_duplication_in_region(uvm_va_block_t *block, if (uvm_id_equal(id, dst_id)) continue; - other_resident_mask = uvm_va_block_resident_mask_get(block, id); + if (UVM_ID_IS_CPU(id)) { + int nid; + + for_each_possible_uvm_node(nid) + uvm_va_block_cpu_clear_resident_mask(block, nid, break_pages_in_region); + + other_resident_mask = uvm_va_block_resident_mask_get(block, UVM_ID_CPU, NUMA_NO_NODE); + } + else { + other_resident_mask = uvm_va_block_resident_mask_get(block, id, NUMA_NO_NODE); + uvm_page_mask_andnot(other_resident_mask, other_resident_mask, break_pages_in_region); + } - if (!uvm_page_mask_andnot(other_resident_mask, other_resident_mask, break_pages_in_region)) + if (uvm_page_mask_empty(other_resident_mask)) block_clear_resident_processor(block, id); } } @@ -3467,7 +4180,7 @@ static void block_copy_set_first_touch_residency(uvm_va_block_t *block, const uvm_page_mask_t *page_mask) { uvm_page_index_t page_index; - uvm_page_mask_t *resident_mask = uvm_va_block_resident_mask_get(block, dst_id); + uvm_page_mask_t *resident_mask = uvm_va_block_resident_mask_get(block, dst_id, NUMA_NO_NODE); uvm_page_mask_t *first_touch_mask = &block_context->make_resident.page_mask; if (page_mask) @@ -3483,7 +4196,14 @@ static void block_copy_set_first_touch_residency(uvm_va_block_t *block, UVM_ASSERT(block_check_resident_proximity(block, page_index, dst_id)); } - uvm_page_mask_or(resident_mask, resident_mask, first_touch_mask); + if (UVM_ID_IS_CPU(dst_id)) { + uvm_va_block_cpu_set_resident_all_chunks(block, block_context, first_touch_mask); + resident_mask = uvm_va_block_resident_mask_get(block, UVM_ID_CPU, NUMA_NO_NODE); + } + else { + uvm_page_mask_or(resident_mask, resident_mask, first_touch_mask); + } + if (!uvm_page_mask_empty(resident_mask)) block_set_resident_processor(block, dst_id); @@ -3493,6 +4213,41 @@ static void block_copy_set_first_touch_residency(uvm_va_block_t *block, first_touch_mask); } +// Select the set of CPU pages to be used for the migration. The pages selected +// could be used for either CPU destination pages (when the destination of the +// migration is the CPU) or staging pages (when the migration to the destination +// processor requires staging through the CPU). +static void block_select_cpu_node_pages(uvm_va_block_t *block, + uvm_va_block_context_t *block_context, + const uvm_page_mask_t *page_mask, + uvm_va_block_region_t region) +{ + uvm_va_block_cpu_node_state_t *node_state; + uvm_make_resident_page_tracking_t *tracking = &block_context->make_resident.cpu_pages_used; + uvm_page_mask_t **node_masks = tracking->node_masks; + uvm_page_mask_t *scratch_page_mask = &block_context->scratch_page_mask; + size_t index; + int nid; + + nodes_clear(tracking->nodes); + + if (uvm_page_mask_empty(page_mask)) + return; + + block_context->scratch_node_mask = node_possible_map; + uvm_page_mask_init_from_region(scratch_page_mask, region, page_mask); + + for_each_closest_uvm_node(nid, uvm_va_block_context_get_node(block_context), block_context->scratch_node_mask) { + node_state = block_node_state_get(block, nid); + index = node_to_index(nid); + if (uvm_page_mask_and(node_masks[index], scratch_page_mask, &node_state->allocated)) { + node_set(nid, tracking->nodes); + if (!uvm_page_mask_andnot(scratch_page_mask, scratch_page_mask, node_masks[index])) + return; + } + } +} + // Copy resident pages from other processors to the destination. // All the pages on the destination need to be populated by the caller first. // Pages not resident anywhere else need to be zeroed out as well. @@ -3509,17 +4264,18 @@ static NV_STATUS block_copy_resident_pages(uvm_va_block_t *block, NV_STATUS status = NV_OK; NV_STATUS tracker_status; uvm_tracker_t local_tracker = UVM_TRACKER_INIT(); - uvm_page_mask_t *resident_mask = uvm_va_block_resident_mask_get(block, dst_id); + uvm_page_mask_t *resident_mask = uvm_va_block_resident_mask_get(block, dst_id, NUMA_NO_NODE); NvU32 missing_pages_count; NvU32 pages_copied; - NvU32 pages_copied_to_cpu; + NvU32 pages_copied_to_cpu = 0; uvm_processor_mask_t src_processor_mask; uvm_page_mask_t *copy_page_mask = &block_context->make_resident.page_mask; uvm_page_mask_t *migrated_pages = &block_context->make_resident.pages_migrated; - uvm_page_mask_t *staged_pages = &block_context->make_resident.pages_staged; + uvm_page_mask_t *pages_staged = &block_context->make_resident.pages_staged; + uvm_page_mask_t *cpu_page_mask; + int nid; uvm_page_mask_zero(migrated_pages); - uvm_page_mask_zero(staged_pages); if (page_mask) uvm_page_mask_andnot(copy_page_mask, page_mask, resident_mask); @@ -3538,7 +4294,7 @@ static NV_STATUS block_copy_resident_pages(uvm_va_block_t *block, uvm_processor_mask_zero(&src_processor_mask); - if (!uvm_id_equal(dst_id, UVM_ID_CPU)) { + if (UVM_ID_IS_GPU(dst_id)) { // If the destination is a GPU, first copy everything from processors // with copy access supported. Notably this will copy pages from the CPU // as well even if later some extra copies from CPU are required for @@ -3546,6 +4302,15 @@ static NV_STATUS block_copy_resident_pages(uvm_va_block_t *block, uvm_processor_mask_and(&src_processor_mask, block_get_can_copy_from_mask(block, dst_id), &block->resident); uvm_processor_mask_clear(&src_processor_mask, dst_id); + cpu_page_mask = pages_staged; + } + else { + cpu_page_mask = copy_page_mask; + } + + block_select_cpu_node_pages(block, block_context, cpu_page_mask, region); + + if (UVM_ID_IS_GPU(dst_id)) { status = block_copy_resident_pages_mask(block, block_context, dst_id, @@ -3565,8 +4330,10 @@ static NV_STATUS block_copy_resident_pages(uvm_va_block_t *block, if (status != NV_OK) goto out; - if (missing_pages_count == 0) + if (missing_pages_count == 0) { + UVM_ASSERT(uvm_page_mask_empty(pages_staged)); goto out; + } if (pages_copied) uvm_page_mask_andnot(copy_page_mask, copy_page_mask, migrated_pages); @@ -3579,28 +4346,27 @@ static NV_STATUS block_copy_resident_pages(uvm_va_block_t *block, uvm_processor_mask_clear(&src_processor_mask, dst_id); uvm_processor_mask_clear(&src_processor_mask, UVM_ID_CPU); - status = block_copy_resident_pages_mask(block, - block_context, - UVM_ID_CPU, - &src_processor_mask, - region, - copy_page_mask, - prefetch_page_mask, - transfer_mode, - missing_pages_count, - staged_pages, - &pages_copied_to_cpu, - &local_tracker); - if (status != NV_OK) - goto out; + if (!uvm_page_mask_empty(cpu_page_mask)) { + status = block_copy_resident_pages_mask(block, + block_context, + UVM_ID_CPU, + &src_processor_mask, + region, + cpu_page_mask, + prefetch_page_mask, + transfer_mode, + missing_pages_count, + UVM_ID_IS_CPU(dst_id) ? migrated_pages : NULL, + &pages_copied_to_cpu, + &local_tracker); - // If destination is the CPU then we copied everything there above - if (UVM_ID_IS_CPU(dst_id)) { - uvm_page_mask_or(migrated_pages, migrated_pages, staged_pages); - missing_pages_count -= pages_copied_to_cpu; + if (status != NV_OK) + goto out; + } + // If destination is the CPU then we copied everything there above + if (!UVM_ID_IS_GPU(dst_id)) goto out; - } // Add everything to the block's tracker so that the // block_copy_resident_pages_between() call below will acquire it. @@ -3610,20 +4376,37 @@ static NV_STATUS block_copy_resident_pages(uvm_va_block_t *block, uvm_tracker_clear(&local_tracker); // Now copy staged pages from the CPU to the destination. - status = block_copy_resident_pages_between(block, - block_context, - dst_id, - UVM_ID_CPU, - region, - staged_pages, - prefetch_page_mask, - transfer_mode, - migrated_pages, - &pages_copied, - &local_tracker); + // The staging copy above could have allocated pages on any NUMA node. + // Loop over all nodes where pages were allocated and copy from those + // nodes. + pages_copied = 0; + for_each_node_mask(nid, block_context->make_resident.cpu_pages_used.nodes) { + NvU32 pages_copied_from_node; + uvm_page_mask_t *node_pages_mask = &block_context->make_resident.node_pages_mask; + uvm_page_mask_t *node_alloc_mask = block_context->make_resident.cpu_pages_used.node_masks[node_to_index(nid)]; + + if (uvm_page_mask_and(node_pages_mask, pages_staged, node_alloc_mask)) { + status = block_copy_resident_pages_between(block, + block_context, + dst_id, + NUMA_NO_NODE, + UVM_ID_CPU, + nid, + region, + node_pages_mask, + prefetch_page_mask, + transfer_mode, + migrated_pages, + &pages_copied_from_node, + &local_tracker); + UVM_ASSERT(missing_pages_count >= pages_copied_from_node); + missing_pages_count -= pages_copied_from_node; + pages_copied += pages_copied_from_node; + } - UVM_ASSERT(missing_pages_count >= pages_copied); - missing_pages_count -= pages_copied; + if (status != NV_OK) + break; + } if (status != NV_OK) goto out; @@ -3668,7 +4451,7 @@ NV_STATUS uvm_va_block_make_resident_copy(uvm_va_block_t *va_block, uvm_assert_mutex_locked(&va_block->lock); UVM_ASSERT(uvm_va_block_is_hmm(va_block) || va_block->va_range->type == UVM_VA_RANGE_TYPE_MANAGED); - resident_mask = block_resident_mask_get_alloc(va_block, dest_id); + resident_mask = block_resident_mask_get_alloc(va_block, dest_id, NUMA_NO_NODE); if (!resident_mask) return NV_ERR_NO_MEMORY; @@ -3740,9 +4523,17 @@ static void block_make_resident_update_state(uvm_va_block_t *va_block, uvm_page_mask_t *copy_mask, uvm_make_resident_cause_t cause) { - uvm_page_mask_t *dst_resident_mask = uvm_va_block_resident_mask_get(va_block, dst_id); + if (UVM_ID_IS_CPU(dst_id)) { + // CPU chunks may not have been allocated on the preferred NUMA node. So, + // the residency has to be updated based on the chunk's NUMA ID. + uvm_va_block_cpu_set_resident_all_chunks(va_block, va_block_context, copy_mask); + } + else { + uvm_page_mask_t *dst_resident_mask = uvm_va_block_resident_mask_get(va_block, dst_id, NUMA_NO_NODE); + + uvm_page_mask_or(dst_resident_mask, dst_resident_mask, copy_mask); + } - uvm_page_mask_or(dst_resident_mask, dst_resident_mask, copy_mask); block_set_resident_processor(va_block, dst_id); // Accumulate the pages that migrated into the output mask. @@ -3752,7 +4543,8 @@ static void block_make_resident_update_state(uvm_va_block_t *va_block, // Any move operation implies that mappings have been removed from all // non-UVM-Lite GPUs. - uvm_page_mask_andnot(&va_block->maybe_mapped_pages, &va_block->maybe_mapped_pages, copy_mask); + if (!uvm_va_block_is_hmm(va_block)) + uvm_page_mask_andnot(&va_block->maybe_mapped_pages, &va_block->maybe_mapped_pages, copy_mask); // If we are migrating due to an eviction, set the GPU as evicted and // mark the evicted pages. If we are migrating away from the CPU this @@ -3814,6 +4606,10 @@ void uvm_va_block_make_resident_finish(uvm_va_block_t *va_block, // empty). if (uvm_processor_mask_test(&va_block->resident, dst_id)) block_mark_memory_used(va_block, dst_id); + + // Check state of all chunks after residency change. + // TODO: Bug 4207783: Check both CPU and GPU chunks. + UVM_ASSERT(block_check_cpu_chunks(va_block)); } NV_STATUS uvm_va_block_make_resident(uvm_va_block_t *va_block, @@ -3906,7 +4702,6 @@ NV_STATUS uvm_va_block_make_resident_read_duplicate(uvm_va_block_t *va_block, NV_STATUS status = NV_OK; uvm_processor_id_t src_id; uvm_page_mask_t *dst_resident_mask; - uvm_page_mask_t *cpu_resident_mask; uvm_page_mask_t *migrated_pages; uvm_page_mask_t *staged_pages; uvm_page_mask_t *first_touch_mask; @@ -3938,7 +4733,7 @@ NV_STATUS uvm_va_block_make_resident_read_duplicate(uvm_va_block_t *va_block, // block_copy_resident_pages also use // va_block_context->make_resident.page_mask. uvm_page_mask_t *preprocess_page_mask = &va_block_context->make_resident.page_mask; - const uvm_page_mask_t *resident_mask = uvm_va_block_resident_mask_get(va_block, src_id); + const uvm_page_mask_t *resident_mask = uvm_va_block_resident_mask_get(va_block, src_id, NUMA_NO_NODE); UVM_ASSERT(!uvm_page_mask_empty(resident_mask)); if (page_mask) @@ -3987,16 +4782,21 @@ NV_STATUS uvm_va_block_make_resident_read_duplicate(uvm_va_block_t *va_block, staged_pages = &va_block_context->make_resident.pages_staged; if (!UVM_ID_IS_CPU(dest_id) && !uvm_page_mask_empty(staged_pages)) { - cpu_resident_mask = uvm_va_block_resident_mask_get(va_block, UVM_ID_CPU); - uvm_page_mask_or(cpu_resident_mask, cpu_resident_mask, staged_pages); + uvm_va_block_cpu_set_resident_all_chunks(va_block, va_block_context, staged_pages); block_set_resident_processor(va_block, UVM_ID_CPU); uvm_page_mask_or(&va_block->read_duplicated_pages, &va_block->read_duplicated_pages, staged_pages); uvm_tools_record_read_duplicate(va_block, UVM_ID_CPU, region, staged_pages); } if (!uvm_page_mask_empty(migrated_pages)) { - dst_resident_mask = uvm_va_block_resident_mask_get(va_block, dest_id); - uvm_page_mask_or(dst_resident_mask, dst_resident_mask, migrated_pages); + if (UVM_ID_IS_CPU(dest_id)) { + uvm_va_block_cpu_set_resident_all_chunks(va_block, va_block_context, migrated_pages); + } + else { + dst_resident_mask = uvm_va_block_resident_mask_get(va_block, dest_id, NUMA_NO_NODE); + uvm_page_mask_or(dst_resident_mask, dst_resident_mask, migrated_pages); + } + block_set_resident_processor(va_block, dest_id); uvm_page_mask_or(&va_block->read_duplicated_pages, &va_block->read_duplicated_pages, migrated_pages); uvm_tools_record_read_duplicate(va_block, dest_id, region, migrated_pages); @@ -4015,6 +4815,9 @@ NV_STATUS uvm_va_block_make_resident_read_duplicate(uvm_va_block_t *va_block, if (uvm_processor_mask_test(&va_block->resident, dest_id)) block_mark_memory_used(va_block, dest_id); + // Check state of all chunks after residency change. + // TODO: Bug 4207783: Check both CPU and GPU chunks. + UVM_ASSERT(block_check_cpu_chunks(va_block)); return NV_OK; } @@ -4301,7 +5104,7 @@ static bool block_check_mappings_page(uvm_va_block_t *block, uvm_page_index_t pa // Pages set to zero in maybe_mapped_pages must not be mapped on any // non-UVM-Lite GPU - if (!uvm_page_mask_test(&block->maybe_mapped_pages, page_index)) { + if (!uvm_va_block_is_hmm(block) && !uvm_page_mask_test(&block->maybe_mapped_pages, page_index)) { UVM_ASSERT_MSG(uvm_processor_mask_get_count(&read_mappings) == 0, "Resident: 0x%lx - Mappings Block: 0x%lx / Page R: 0x%lx W: 0x%lx A: 0x%lx\n", *resident_processors.bitmap, @@ -4346,7 +5149,9 @@ static bool block_check_mappings_page(uvm_va_block_t *block, uvm_page_index_t pa if (uvm_processor_mask_test(&va_space->indirect_peers[uvm_id_value(residency)], id)) { uvm_gpu_t *resident_gpu = uvm_va_space_get_gpu(va_space, residency); uvm_gpu_t *mapped_gpu = uvm_va_space_get_gpu(va_space, id); - uvm_gpu_chunk_t *chunk = block_phys_page_chunk(block, block_phys_page(residency, page_index), NULL); + uvm_gpu_chunk_t *chunk = block_phys_page_chunk(block, + block_phys_page(residency, NUMA_NO_NODE, page_index), + NULL); // This function will assert if no mapping exists (void)uvm_pmm_gpu_indirect_peer_addr(&resident_gpu->pmm, chunk, mapped_gpu); @@ -4519,7 +5324,7 @@ static bool block_check_mappings_ptes(uvm_va_block_t *block, uvm_gpu_t *gpu) // The mapped processor should be fully resident and physically- // contiguous. - UVM_ASSERT(uvm_page_mask_full(uvm_va_block_resident_mask_get(block, resident_id))); + UVM_ASSERT(uvm_page_mask_full(uvm_va_block_resident_mask_get(block, resident_id, NUMA_NO_NODE))); if (UVM_ID_IS_GPU(resident_id)) { resident_gpu_state = uvm_va_block_gpu_state_get(block, resident_id); @@ -4527,13 +5332,15 @@ static bool block_check_mappings_ptes(uvm_va_block_t *block, uvm_gpu_t *gpu) UVM_ASSERT(uvm_gpu_chunk_get_size(resident_gpu_state->chunks[0]) == UVM_CHUNK_SIZE_2M); } else { - uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_first_in_region(block, - uvm_va_block_region_from_block(block), - NULL); + uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page_resident(block, 0); + int chunk_nid = uvm_cpu_chunk_get_numa_node(chunk); UVM_ASSERT(uvm_page_mask_full(&block->cpu.allocated)); UVM_ASSERT(chunk); UVM_ASSERT(uvm_cpu_chunk_get_size(chunk) == UVM_CHUNK_SIZE_2M); + UVM_ASSERT(uvm_va_block_cpu_is_region_resident_on(block, + chunk_nid, + uvm_va_block_region_from_block(block))); } } } @@ -4572,19 +5379,28 @@ static bool block_check_mappings_ptes(uvm_va_block_t *block, uvm_gpu_t *gpu) // location even if the memory is resident elsewhere. Skip the // residency check but still verify contiguity. if (!uvm_processor_mask_test(block_get_uvm_lite_gpus(block), gpu->id)) { - UVM_ASSERT(uvm_page_mask_region_full(uvm_va_block_resident_mask_get(block, resident_id), - big_region)); + UVM_ASSERT( + uvm_page_mask_region_full(uvm_va_block_resident_mask_get(block, resident_id, NUMA_NO_NODE), + big_region)); } if (UVM_ID_IS_CPU(resident_id)) { - uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(block, big_region.first); + int resident_nid = block_get_page_node_residency(block, big_region.first); + uvm_va_block_cpu_node_state_t *node_state = block_node_state_get(block, resident_nid); + uvm_cpu_chunk_t *chunk; + UVM_ASSERT(resident_nid != NUMA_NO_NODE); + UVM_ASSERT(uvm_page_mask_region_full(&node_state->allocated, big_region)); + chunk = uvm_cpu_chunk_get_chunk_for_page(block, resident_nid, big_region.first); UVM_ASSERT(gpu->parent->can_map_sysmem_with_large_pages); UVM_ASSERT(uvm_cpu_chunk_get_size(chunk) >= uvm_va_block_region_size(big_region)); + UVM_ASSERT(uvm_page_mask_region_full(&node_state->resident, big_region)); } else { // Check GPU chunks - chunk = block_phys_page_chunk(block, block_phys_page(resident_id, big_region.first), NULL); + chunk = block_phys_page_chunk(block, + block_phys_page(resident_id, NUMA_NO_NODE, big_region.first), + NULL); chunk_region = uvm_va_block_chunk_region(block, uvm_gpu_chunk_get_size(chunk), big_region.first); UVM_ASSERT(uvm_va_block_region_contains_region(chunk_region, big_region)); } @@ -4611,7 +5427,7 @@ static bool block_check_mappings(uvm_va_block_t *block) continue; } - resident_mask = uvm_va_block_resident_mask_get(block, id); + resident_mask = uvm_va_block_resident_mask_get(block, id, NUMA_NO_NODE); UVM_ASSERT(uvm_processor_mask_test(&block->resident, id) == !uvm_page_mask_empty(resident_mask)); map_mask = uvm_va_block_map_mask_get(block, id); @@ -4689,7 +5505,7 @@ static void block_unmap_cpu(uvm_va_block_t *block, uvm_va_block_region_t region, // If the CPU is the only processor with mappings we can safely mark // the pages as fully unmapped - if (num_mapped_processors == 1) + if (num_mapped_processors == 1 && !uvm_va_block_is_hmm(block)) uvm_page_mask_region_clear(&block->maybe_mapped_pages, subregion); unmapped_something = true; @@ -4799,6 +5615,7 @@ static void block_gpu_pte_write_4k(uvm_va_block_t *block, uvm_gpu_phys_address_t page_addr = {0}; uvm_page_index_t page_index; NvU64 pte_flags = block_gpu_pte_flag_cacheable(block, gpu, resident_id); + int contig_nid = NUMA_NO_NODE; UVM_ASSERT(new_prot != UVM_PROT_NONE); UVM_ASSERT(UVM_ID_IS_VALID(resident_id)); @@ -4806,15 +5623,22 @@ static void block_gpu_pte_write_4k(uvm_va_block_t *block, for_each_va_block_page_in_mask(page_index, write_page_mask, block) { uvm_gpu_phys_address_t pte_addr; size_t i; + int nid = NUMA_NO_NODE; - // Assume that this mapping will be used to write to the page - if (new_prot > UVM_PROT_READ_ONLY && UVM_ID_IS_CPU(resident_id) && !uvm_va_block_is_hmm(block)) - block_mark_cpu_page_dirty(block, page_index); + if (UVM_ID_IS_CPU(resident_id)) { + nid = block_get_page_node_residency(block, page_index); + UVM_ASSERT(nid != NUMA_NO_NODE); + + // Assume that this mapping will be used to write to the page + if (new_prot > UVM_PROT_READ_ONLY && !uvm_va_block_is_hmm(block)) + block_mark_cpu_page_dirty(block, page_index, nid); + } - if (page_index >= contig_region.outer) { - contig_region = block_phys_contig_region(block, page_index, resident_id); - contig_addr = block_phys_page_address(block, block_phys_page(resident_id, contig_region.first), gpu); + if (page_index >= contig_region.outer || nid != contig_nid) { + contig_region = block_phys_contig_region(block, page_index, resident_id, nid); + contig_addr = block_phys_page_address(block, block_phys_page(resident_id, nid, contig_region.first), gpu); page_addr = contig_addr; + contig_nid = nid; } page_addr.address = contig_addr.address + (page_index - contig_region.first) * PAGE_SIZE; @@ -4998,6 +5822,7 @@ static void block_gpu_pte_write_big(uvm_va_block_t *block, uvm_gpu_phys_address_t contig_addr = {0}; uvm_gpu_phys_address_t page_addr = {0}; NvU64 pte_flags = block_gpu_pte_flag_cacheable(block, gpu, resident_id); + int contig_nid = NUMA_NO_NODE; UVM_ASSERT(new_prot != UVM_PROT_NONE); UVM_ASSERT(UVM_ID_IS_VALID(resident_id)); @@ -5014,19 +5839,26 @@ static void block_gpu_pte_write_big(uvm_va_block_t *block, NvU64 pte_val; uvm_gpu_phys_address_t pte_addr; uvm_va_block_region_t big_region = uvm_va_block_big_page_region(block, big_page_index, big_page_size); + int nid = NUMA_NO_NODE; - // Assume that this mapping will be used to write to the page - if (new_prot > UVM_PROT_READ_ONLY && UVM_ID_IS_CPU(resident_id) && !uvm_va_block_is_hmm(block)) { - uvm_page_index_t page_index; + if (UVM_ID_IS_CPU(resident_id)) { + nid = block_get_page_node_residency(block, big_region.first); + UVM_ASSERT(nid != NUMA_NO_NODE); + + // Assume that this mapping will be used to write to the page + if (new_prot > UVM_PROT_READ_ONLY && !uvm_va_block_is_hmm(block)) { + uvm_page_index_t page_index; - for_each_va_block_page_in_region(page_index, big_region) - block_mark_cpu_page_dirty(block, page_index); + for_each_va_block_page_in_region(page_index, big_region) + block_mark_cpu_page_dirty(block, page_index, nid); + } } - if (big_region.first >= contig_region.outer) { - contig_region = block_phys_contig_region(block, big_region.first, resident_id); - contig_addr = block_phys_page_address(block, block_phys_page(resident_id, contig_region.first), gpu); + if (big_region.first >= contig_region.outer || nid != contig_nid) { + contig_region = block_phys_contig_region(block, big_region.first, resident_id, nid); + contig_addr = block_phys_page_address(block, block_phys_page(resident_id, nid, contig_region.first), gpu); page_addr = contig_addr; + contig_nid = nid; } page_addr.address = contig_addr.address + (big_region.first - contig_region.first) * PAGE_SIZE; @@ -5164,14 +5996,19 @@ static void block_gpu_pte_write_2m(uvm_va_block_t *block, NvU32 pte_size = uvm_mmu_pte_size(tree, UVM_PAGE_SIZE_2M); NvU64 pte_val; NvU64 pte_flags = block_gpu_pte_flag_cacheable(block, gpu, resident_id); + int nid = NUMA_NO_NODE; UVM_ASSERT(new_prot != UVM_PROT_NONE); UVM_ASSERT(UVM_ID_IS_VALID(resident_id)); - if (UVM_ID_IS_CPU(resident_id) && !uvm_va_block_is_hmm(block)) - block_mark_cpu_page_dirty(block, 0); + if (UVM_ID_IS_CPU(resident_id)) { + nid = block_get_page_node_residency(block, 0); + UVM_ASSERT(nid != NUMA_NO_NODE); + if (!uvm_va_block_is_hmm(block)) + block_mark_cpu_page_dirty(block, 0, nid); + } - page_addr = block_phys_page_address(block, block_phys_page(resident_id, 0), gpu); + page_addr = block_phys_page_address(block, block_phys_page(resident_id, nid, 0), gpu); pte_val = tree->hal->make_pte(page_addr.aperture, page_addr.address, new_prot, pte_flags); uvm_pte_batch_write_pte(pte_batch, pte_addr, pte_val, pte_size); @@ -6195,9 +7032,9 @@ static void block_gpu_compute_new_pte_state(uvm_va_block_t *block, // If all pages in the 2M mask have the same attributes after the // operation is applied, we can use a 2M PTE. - if (block_gpu_supports_2m(block, gpu) && - uvm_page_mask_full(page_mask_after) && - (UVM_ID_IS_INVALID(resident_id) || is_block_phys_contig(block, resident_id))) { + if (block_gpu_supports_2m(block, gpu) && uvm_page_mask_full(page_mask_after) && + (UVM_ID_IS_INVALID(resident_id) || + is_block_phys_contig(block, resident_id, block_get_page_node_residency(block, 0)))) { new_pte_state->pte_is_2m = true; new_pte_state->needs_4k = false; return; @@ -6233,14 +7070,18 @@ static void block_gpu_compute_new_pte_state(uvm_va_block_t *block, can_make_new_big_ptes = false; for_each_va_block_page_in_region_mask(page_index, pages_changing, big_region_all) { - uvm_va_block_region_t contig_region = {0}; + uvm_cpu_chunk_t *chunk = NULL; + int nid; + + if (UVM_ID_IS_CPU(resident_id)) { + nid = block_get_page_node_residency(block, page_index); + UVM_ASSERT(nid != NUMA_NO_NODE); + chunk = uvm_cpu_chunk_get_chunk_for_page(block, nid, page_index); + } big_page_index = uvm_va_block_big_page_index(block, page_index, big_page_size); big_page_region = uvm_va_block_big_page_region(block, big_page_index, big_page_size); - if (!UVM_ID_IS_INVALID(resident_id)) - contig_region = block_phys_contig_region(block, page_index, resident_id); - __set_bit(big_page_index, new_pte_state->big_ptes_covered); // When mapping sysmem, we can use big pages only if we are mapping all @@ -6249,9 +7090,9 @@ static void block_gpu_compute_new_pte_state(uvm_va_block_t *block, if (can_make_new_big_ptes && uvm_page_mask_region_full(page_mask_after, big_page_region) && (!UVM_ID_IS_CPU(resident_id) || - (contig_region.first <= big_page_region.first && contig_region.outer >= big_page_region.outer))) { + (uvm_cpu_chunk_get_size(chunk) >= big_page_size && + uvm_va_block_cpu_is_region_resident_on(block, nid, big_page_region)))) __set_bit(big_page_index, new_pte_state->big_ptes); - } if (!test_bit(big_page_index, new_pte_state->big_ptes)) new_pte_state->needs_4k = true; @@ -6667,7 +7508,7 @@ static NV_STATUS block_unmap_gpu(uvm_va_block_t *block, // If the GPU is the only non-UVM-Lite processor with mappings, we can // safely mark pages as fully unmapped - if (uvm_processor_mask_get_count(&non_uvm_lite_gpus) == 1) + if (uvm_processor_mask_get_count(&non_uvm_lite_gpus) == 1 && !uvm_va_block_is_hmm(block)) uvm_page_mask_andnot(&block->maybe_mapped_pages, &block->maybe_mapped_pages, pages_to_unmap); } @@ -6803,7 +7644,7 @@ static struct page *block_page_get(uvm_va_block_t *block, block_phys_page_t bloc struct page *page; if (UVM_ID_IS_CPU(block_page.processor)) { - page = uvm_cpu_chunk_get_cpu_page(block, block_page.page_index); + page = uvm_va_block_get_cpu_page(block, block_page.page_index); } else { uvm_va_space_t *va_space = uvm_va_block_get_va_space(block); @@ -6853,6 +7694,7 @@ static NV_STATUS block_map_cpu_page_to(uvm_va_block_t *block, NV_STATUS status; NvU64 addr; struct page *page; + int nid = NUMA_NO_NODE; UVM_ASSERT((uvm_va_block_is_hmm(block) && hmm_vma) || va_range->type == UVM_VA_RANGE_TYPE_MANAGED); UVM_ASSERT(new_prot != UVM_PROT_NONE); @@ -6885,16 +7727,21 @@ static NV_STATUS block_map_cpu_page_to(uvm_va_block_t *block, UVM_ASSERT(va_range); - if (UVM_ID_IS_CPU(resident_id) && UVM_ID_IS_CPU(uvm_va_range_get_policy(va_range)->preferred_location)) { - // Add the page's range group range to the range group's migrated list. - uvm_range_group_range_t *rgr = uvm_range_group_range_find(va_space, - uvm_va_block_cpu_page_address(block, page_index)); - if (rgr != NULL) { - uvm_spin_lock(&rgr->range_group->migrated_ranges_lock); - if (list_empty(&rgr->range_group_migrated_list_node)) - list_move_tail(&rgr->range_group_migrated_list_node, &rgr->range_group->migrated_ranges); - uvm_spin_unlock(&rgr->range_group->migrated_ranges_lock); + if (UVM_ID_IS_CPU(resident_id)) { + if (UVM_ID_IS_CPU(uvm_va_range_get_policy(va_range)->preferred_location)) { + // Add the page's range group range to the range group's migrated list. + uvm_range_group_range_t *rgr = uvm_range_group_range_find(va_space, + uvm_va_block_cpu_page_address(block, page_index)); + if (rgr != NULL) { + uvm_spin_lock(&rgr->range_group->migrated_ranges_lock); + if (list_empty(&rgr->range_group_migrated_list_node)) + list_move_tail(&rgr->range_group_migrated_list_node, &rgr->range_group->migrated_ranges); + uvm_spin_unlock(&rgr->range_group->migrated_ranges_lock); + } } + + nid = block_get_page_node_residency(block, page_index); + UVM_ASSERT(nid != NUMA_NO_NODE); } // It's possible here that current->mm != vma->vm_mm. That can happen for @@ -6923,7 +7770,7 @@ static NV_STATUS block_map_cpu_page_to(uvm_va_block_t *block, if (status != NV_OK) return status; - page = block_page_get(block, block_phys_page(resident_id, page_index)); + page = block_page_get(block, block_phys_page(resident_id, nid, page_index)); return uvm_cpu_insert_page(vma, addr, page, new_prot); } @@ -6946,7 +7793,7 @@ static NV_STATUS block_map_cpu_to(uvm_va_block_t *block, uvm_va_space_t *va_space = uvm_va_block_get_va_space(block); uvm_page_index_t page_index; uvm_page_mask_t *pages_to_map = &block_context->mapping.page_mask; - const uvm_page_mask_t *resident_mask = uvm_va_block_resident_mask_get(block, resident_id); + const uvm_page_mask_t *resident_mask = uvm_va_block_resident_mask_get(block, resident_id, NUMA_NO_NODE); uvm_pte_bits_cpu_t prot_pte_bit = get_cpu_pte_bit_index(new_prot); uvm_pte_bits_cpu_t pte_bit; @@ -7012,7 +7859,8 @@ static NV_STATUS block_map_cpu_to(uvm_va_block_t *block, for (pte_bit = 0; pte_bit <= prot_pte_bit; pte_bit++) uvm_page_mask_or(&block->cpu.pte_bits[pte_bit], &block->cpu.pte_bits[pte_bit], pages_to_map); - uvm_page_mask_or(&block->maybe_mapped_pages, &block->maybe_mapped_pages, pages_to_map); + if (!uvm_va_block_is_hmm(block)) + uvm_page_mask_or(&block->maybe_mapped_pages, &block->maybe_mapped_pages, pages_to_map); UVM_ASSERT(block_check_mappings(block)); @@ -7042,7 +7890,7 @@ static NV_STATUS block_map_gpu_to(uvm_va_block_t *va_block, uvm_push_t push; NV_STATUS status; uvm_page_mask_t *pages_to_map = &block_context->mapping.page_mask; - const uvm_page_mask_t *resident_mask = uvm_va_block_resident_mask_get(va_block, resident_id); + const uvm_page_mask_t *resident_mask = uvm_va_block_resident_mask_get(va_block, resident_id, NUMA_NO_NODE); uvm_pte_bits_gpu_t pte_bit; uvm_pte_bits_gpu_t prot_pte_bit = get_gpu_pte_bit_index(new_prot); uvm_va_block_new_pte_state_t *new_pte_state = &block_context->mapping.new_pte_state; @@ -7139,8 +7987,10 @@ static NV_STATUS block_map_gpu_to(uvm_va_block_t *va_block, uvm_processor_mask_set(&va_block->mapped, gpu->id); - // If we are mapping a UVM-Lite GPU do not update maybe_mapped_pages - if (!uvm_processor_mask_test(block_get_uvm_lite_gpus(va_block), gpu->id)) + // If we are mapping a UVM-Lite GPU or HMM va_block, do not update + // maybe_mapped_pages. + if (!uvm_processor_mask_test(block_get_uvm_lite_gpus(va_block), gpu->id) && + !uvm_va_block_is_hmm(va_block)) uvm_page_mask_or(&va_block->maybe_mapped_pages, &va_block->maybe_mapped_pages, pages_to_map); // Remove all pages resident on this processor from the input mask, which @@ -7389,7 +8239,7 @@ static NV_STATUS block_revoke_prot_gpu_to(uvm_va_block_t *va_block, uvm_prot_t new_prot = prot_to_revoke - 1; uvm_va_block_new_pte_state_t *new_pte_state = &block_context->mapping.new_pte_state; block_pte_op_t pte_op; - const uvm_page_mask_t *resident_mask = uvm_va_block_resident_mask_get(va_block, resident_id); + const uvm_page_mask_t *resident_mask = uvm_va_block_resident_mask_get(va_block, resident_id, NUMA_NO_NODE); uvm_page_mask_t *pages_to_revoke = &block_context->mapping.page_mask; UVM_ASSERT(revoke_page_mask); @@ -7663,7 +8513,7 @@ static void update_read_duplicated_pages_mask(uvm_va_block_t *block, if (uvm_id_equal(running_id, id)) continue; - running_residency_mask = uvm_va_block_resident_mask_get(block, running_id); + running_residency_mask = uvm_va_block_resident_mask_get(block, running_id, NUMA_NO_NODE); if (first) { uvm_page_mask_copy(running_page_mask, running_residency_mask); @@ -7920,8 +8770,8 @@ void uvm_va_block_disable_peer(uvm_va_block_t *va_block, uvm_gpu_t *gpu0, uvm_gp if (!uvm_va_block_gpu_state_get(va_block, gpu0->id) || !uvm_va_block_gpu_state_get(va_block, gpu1->id)) return; - resident0 = uvm_va_block_resident_mask_get(va_block, gpu0->id); - resident1 = uvm_va_block_resident_mask_get(va_block, gpu1->id); + resident0 = uvm_va_block_resident_mask_get(va_block, gpu0->id, NUMA_NO_NODE); + resident1 = uvm_va_block_resident_mask_get(va_block, gpu1->id, NUMA_NO_NODE); // Unmap all pages resident on gpu1, but not on gpu0, from gpu0 if (uvm_page_mask_andnot(unmap_page_mask, resident1, resident0)) { @@ -7998,7 +8848,7 @@ void uvm_va_block_unmap_preferred_location_uvm_lite(uvm_va_block_t *va_block, uv static NV_STATUS block_evict_pages_from_gpu(uvm_va_block_t *va_block, uvm_gpu_t *gpu, struct mm_struct *mm) { NV_STATUS status = NV_OK; - const uvm_page_mask_t *resident = uvm_va_block_resident_mask_get(va_block, gpu->id); + const uvm_page_mask_t *resident = uvm_va_block_resident_mask_get(va_block, gpu->id, NUMA_NO_NODE); uvm_va_block_region_t region = uvm_va_block_region_from_block(va_block); uvm_va_block_region_t subregion; uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); @@ -8083,11 +8933,15 @@ void uvm_va_block_unregister_gpu(uvm_va_block_t *va_block, uvm_gpu_t *gpu, struc static void block_mark_region_cpu_dirty(uvm_va_block_t *va_block, uvm_va_block_region_t region) { uvm_page_index_t page_index; + uvm_page_mask_t *resident_mask; uvm_assert_mutex_locked(&va_block->lock); - - for_each_va_block_page_in_region_mask (page_index, &va_block->cpu.resident, region) - block_mark_cpu_page_dirty(va_block, page_index); + resident_mask = uvm_va_block_resident_mask_get(va_block, UVM_ID_CPU, NUMA_NO_NODE); + for_each_va_block_page_in_region_mask(page_index, resident_mask, region) { + int nid = block_get_page_node_residency(va_block, page_index); + UVM_ASSERT(nid != NUMA_NO_NODE); + block_mark_cpu_page_dirty(va_block, page_index, nid); + } } // Tears down everything within the block, but doesn't free the block itself. @@ -8105,6 +8959,7 @@ static void block_kill(uvm_va_block_t *block) uvm_va_block_region_t region = uvm_va_block_region_from_block(block); uvm_page_index_t page_index; uvm_page_index_t next_page_index; + int nid; if (uvm_va_block_is_dead(block)) return; @@ -8147,18 +9002,28 @@ static void block_kill(uvm_va_block_t *block) UVM_ASSERT(block_check_processor_not_mapped(block, UVM_ID_CPU)); // Free CPU pages - for_each_cpu_chunk_in_block_safe(chunk, page_index, next_page_index, block) { - // be conservative. - // Tell the OS we wrote to the page because we sometimes clear the dirty - // bit after writing to it. HMM dirty flags are managed by the kernel. - if (!uvm_va_block_is_hmm(block)) - uvm_cpu_chunk_mark_dirty(chunk, 0); - uvm_cpu_chunk_remove_from_block(block, page_index); - uvm_cpu_chunk_free(chunk); + for_each_possible_uvm_node(nid) { + uvm_va_block_cpu_node_state_t *node_state = block_node_state_get(block, nid); + size_t index = node_to_index(nid); + + for_each_cpu_chunk_in_block_safe(chunk, page_index, next_page_index, block, nid) { + // be conservative. + // Tell the OS we wrote to the page because we sometimes clear the dirty + // bit after writing to it. HMM dirty flags are managed by the kernel. + if (!uvm_va_block_is_hmm(block)) + uvm_cpu_chunk_mark_dirty(chunk, 0); + + uvm_cpu_chunk_remove_from_block(block, nid, page_index); + uvm_cpu_chunk_free(chunk); + } + + UVM_ASSERT(uvm_page_mask_empty(&node_state->allocated)); + UVM_ASSERT(node_state->chunks == 0); + kmem_cache_free(g_uvm_va_block_cpu_node_state_cache, block->cpu.node_state[index]); } - uvm_kvfree((void *)block->cpu.chunks); - block->cpu.chunks = 0; + uvm_kvfree((void *)block->cpu.node_state); + block->cpu.node_state = NULL; // Clearing the resident bit isn't strictly necessary since this block // is getting destroyed, but it keeps state consistent for assertions. @@ -8185,15 +9050,7 @@ void uvm_va_block_destroy(nv_kref_t *nv_kref) uvm_mutex_lock(&block->lock); block_kill(block); uvm_mutex_unlock(&block->lock); - - if (uvm_enable_builtin_tests) { - uvm_va_block_wrapper_t *block_wrapper = container_of(block, uvm_va_block_wrapper_t, block); - - kmem_cache_free(g_uvm_va_block_cache, block_wrapper); - } - else { - kmem_cache_free(g_uvm_va_block_cache, block); - } + uvm_va_block_free(block); } void uvm_va_block_kill(uvm_va_block_t *va_block) @@ -8248,14 +9105,6 @@ void uvm_va_block_munmap_region(uvm_va_block_t *va_block, event_data.block_munmap.region = region; uvm_perf_event_notify(&va_space->perf_events, UVM_PERF_EVENT_BLOCK_MUNMAP, &event_data); - // Set a flag so that GPU fault events are flushed since they might refer - // to the region being unmapped. - // Note that holding the va_block lock prevents GPU VA spaces from - // being removed so the registered_gpu_va_spaces mask is stable. - for_each_gpu_id_in_mask(gpu_id, &va_space->registered_gpu_va_spaces) { - uvm_processor_mask_set_atomic(&va_space->needs_fault_buffer_flush, gpu_id); - } - // Release any remaining vidmem chunks in the given region. for_each_gpu_id(gpu_id) { uvm_va_block_gpu_state_t *gpu_state = uvm_va_block_gpu_state_get(va_block, gpu_id); @@ -8545,14 +9394,15 @@ static NV_STATUS block_presplit_gpu_chunks(uvm_va_block_t *existing, uvm_va_bloc return status; } -static NV_STATUS block_split_cpu_chunk_to_64k(uvm_va_block_t *block) +static NV_STATUS block_split_cpu_chunk_to_64k(uvm_va_block_t *block, int nid) { uvm_cpu_chunk_storage_mixed_t *mixed; - uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(block, 0); + uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(block, nid, 0); + uvm_va_block_cpu_node_state_t *node_state = block_node_state_get(block, nid); NV_STATUS status; UVM_ASSERT(uvm_cpu_chunk_get_size(chunk) == UVM_CHUNK_SIZE_2M); - UVM_ASSERT(uvm_cpu_storage_get_type(block) == UVM_CPU_CHUNK_STORAGE_CHUNK); + UVM_ASSERT(uvm_cpu_storage_get_type(node_state) == UVM_CPU_CHUNK_STORAGE_CHUNK); mixed = uvm_kvmalloc_zero(sizeof(*mixed)); if (!mixed) @@ -8565,23 +9415,25 @@ static NV_STATUS block_split_cpu_chunk_to_64k(uvm_va_block_t *block) } bitmap_fill(mixed->big_chunks, MAX_BIG_CPU_CHUNK_SLOTS_PER_UVM_VA_BLOCK); - block->cpu.chunks = (unsigned long)mixed | UVM_CPU_CHUNK_STORAGE_MIXED; + node_state->chunks = (unsigned long)mixed | UVM_CPU_CHUNK_STORAGE_MIXED; + return status; } -static NV_STATUS block_split_cpu_chunk_to_4k(uvm_va_block_t *block, uvm_page_index_t page_index) +static NV_STATUS block_split_cpu_chunk_to_4k(uvm_va_block_t *block, uvm_page_index_t page_index, int nid) { + uvm_va_block_cpu_node_state_t *node_state = block_node_state_get(block, nid); uvm_cpu_chunk_storage_mixed_t *mixed; - uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(block, page_index); + uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(block, nid, page_index); uvm_cpu_chunk_t **small_chunks; size_t slot_index; NV_STATUS status; UVM_ASSERT(chunk); UVM_ASSERT(uvm_cpu_chunk_get_size(chunk) == UVM_CHUNK_SIZE_64K); - UVM_ASSERT(uvm_cpu_storage_get_type(block) == UVM_CPU_CHUNK_STORAGE_MIXED); + UVM_ASSERT(uvm_cpu_storage_get_type(node_state) == UVM_CPU_CHUNK_STORAGE_MIXED); - mixed = uvm_cpu_storage_get_ptr(block); + mixed = uvm_cpu_storage_get_ptr(node_state); slot_index = compute_slot_index(block, page_index); small_chunks = uvm_kvmalloc_zero(sizeof(*small_chunks) * MAX_SMALL_CHUNKS_PER_BIG_SLOT); if (!small_chunks) @@ -8595,12 +9447,13 @@ static NV_STATUS block_split_cpu_chunk_to_4k(uvm_va_block_t *block, uvm_page_ind mixed->slots[slot_index] = small_chunks; clear_bit(slot_index, mixed->big_chunks); + return status; } -static NV_STATUS block_split_cpu_chunk_one(uvm_va_block_t *block, uvm_page_index_t page_index) +static NV_STATUS block_split_cpu_chunk_one(uvm_va_block_t *block, uvm_page_index_t page_index, int nid) { - uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(block, page_index); + uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(block, nid, page_index); uvm_chunk_size_t chunk_size = uvm_cpu_chunk_get_size(chunk); uvm_chunk_size_t new_size; uvm_gpu_t *gpu; @@ -8638,9 +9491,9 @@ static NV_STATUS block_split_cpu_chunk_one(uvm_va_block_t *block, uvm_page_index } if (new_size == UVM_CHUNK_SIZE_64K) - status = block_split_cpu_chunk_to_64k(block); + status = block_split_cpu_chunk_to_64k(block, nid); else - status = block_split_cpu_chunk_to_4k(block, page_index); + status = block_split_cpu_chunk_to_4k(block, page_index, nid); if (status != NV_OK) { merge: @@ -8656,16 +9509,18 @@ static NV_STATUS block_split_cpu_chunk_one(uvm_va_block_t *block, uvm_page_index return status; } -static NV_STATUS block_prealloc_cpu_chunk_storage(uvm_va_block_t *existing, uvm_va_block_t *new) +static NV_STATUS block_prealloc_cpu_chunk_storage(uvm_va_block_t *existing, uvm_va_block_t *new, int nid) { uvm_cpu_chunk_storage_mixed_t *existing_mixed; uvm_cpu_chunk_storage_mixed_t *new_mixed = NULL; + uvm_va_block_cpu_node_state_t *node_state = block_node_state_get(existing, nid); + uvm_va_block_cpu_node_state_t *new_node_state = block_node_state_get(new, nid); size_t slot_offset; size_t existing_slot; NV_STATUS status = NV_OK; - UVM_ASSERT(uvm_cpu_storage_get_type(existing) == UVM_CPU_CHUNK_STORAGE_MIXED); - existing_mixed = uvm_cpu_storage_get_ptr(existing); + UVM_ASSERT(uvm_cpu_storage_get_type(node_state) == UVM_CPU_CHUNK_STORAGE_MIXED); + existing_mixed = uvm_cpu_storage_get_ptr(node_state); // Pre-allocate chunk storage for the new block. By definition, the new block // will contain either 64K and/or 4K chunks. @@ -8692,7 +9547,7 @@ static NV_STATUS block_prealloc_cpu_chunk_storage(uvm_va_block_t *existing, uvm_ } } - new->cpu.chunks = (unsigned long)new_mixed | UVM_CPU_CHUNK_STORAGE_MIXED; + new_node_state->chunks = (unsigned long)new_mixed | UVM_CPU_CHUNK_STORAGE_MIXED; UVM_ASSERT(status == NV_OK); done: @@ -8706,19 +9561,21 @@ static NV_STATUS block_prealloc_cpu_chunk_storage(uvm_va_block_t *existing, uvm_ return status; } -static void block_free_cpu_chunk_storage(uvm_va_block_t *block) +static void block_free_cpu_chunk_storage(uvm_va_block_t *block, int nid) { - if (block->cpu.chunks) { + uvm_va_block_cpu_node_state_t *node_state = block_node_state_get(block, nid); + + if (node_state->chunks) { uvm_cpu_chunk_storage_mixed_t *mixed; size_t slot_index; - UVM_ASSERT(uvm_cpu_storage_get_type(block) == UVM_CPU_CHUNK_STORAGE_MIXED); - mixed = uvm_cpu_storage_get_ptr(block); + UVM_ASSERT(uvm_cpu_storage_get_type(node_state) == UVM_CPU_CHUNK_STORAGE_MIXED); + mixed = uvm_cpu_storage_get_ptr(node_state); for (slot_index = 0; slot_index < MAX_BIG_CPU_CHUNK_SLOTS_PER_UVM_VA_BLOCK; slot_index++) uvm_kvfree(mixed->slots[slot_index]); uvm_kvfree(mixed); - block->cpu.chunks = 0; + node_state->chunks = 0; } } @@ -8731,42 +9588,51 @@ static NV_STATUS block_presplit_cpu_chunks(uvm_va_block_t *existing, uvm_va_bloc uvm_chunk_sizes_mask_t split_sizes = uvm_cpu_chunk_get_allocation_sizes(); uvm_chunk_size_t subchunk_size; NV_STATUS status = NV_OK; + int nid; UVM_ASSERT(!IS_ALIGNED(new->start, UVM_VA_BLOCK_SIZE)); - splitting_chunk = uvm_cpu_chunk_get_chunk_for_page(existing, page_index); - // If the page covering the split point has not been populated, there is no - // need to split. - if (!splitting_chunk) - return NV_OK; + for_each_possible_uvm_node(nid) { + splitting_chunk = uvm_cpu_chunk_get_chunk_for_page(existing, nid, page_index); - // If the split point is aligned on the chunk size, there is no need to - // split. - if (IS_ALIGNED(new->start, uvm_cpu_chunk_get_size(splitting_chunk))) - return NV_OK; + // If the page covering the split point has not been populated, there is no + // need to split. + if (!splitting_chunk) + continue; - // Remove all sizes above the chunk's current size. - split_sizes &= uvm_cpu_chunk_get_size(splitting_chunk) - 1; - // Remove all sizes below the alignment of the new block's start. - split_sizes &= ~(IS_ALIGNED(new->start, UVM_CHUNK_SIZE_64K) ? UVM_CHUNK_SIZE_64K - 1 : 0); + // If the split point is aligned on the chunk size, there is no need to + // split. + if (IS_ALIGNED(new->start, uvm_cpu_chunk_get_size(splitting_chunk))) + continue; - for_each_chunk_size_rev(subchunk_size, split_sizes) { - status = block_split_cpu_chunk_one(existing, page_index); + // Remove all sizes above the chunk's current size. + split_sizes &= uvm_cpu_chunk_get_size(splitting_chunk) - 1; + // Remove all sizes below the alignment of the new block's start. + split_sizes &= ~(IS_ALIGNED(new->start, UVM_CHUNK_SIZE_64K) ? UVM_CHUNK_SIZE_64K - 1 : 0); + + for_each_chunk_size_rev(subchunk_size, split_sizes) { + status = block_split_cpu_chunk_one(existing, page_index, nid); + if (status != NV_OK) + return status; + } + + status = block_prealloc_cpu_chunk_storage(existing, new, nid); if (status != NV_OK) - return status; + break; } - return block_prealloc_cpu_chunk_storage(existing, new); + return status; } -static void block_merge_cpu_chunks_to_64k(uvm_va_block_t *block, uvm_page_index_t page_index) +static void block_merge_cpu_chunks_to_64k(uvm_va_block_t *block, uvm_page_index_t page_index, int nid) { - uvm_cpu_chunk_storage_mixed_t *mixed = uvm_cpu_storage_get_ptr(block); + uvm_va_block_cpu_node_state_t *node_state = block_node_state_get(block, nid); + uvm_cpu_chunk_storage_mixed_t *mixed = uvm_cpu_storage_get_ptr(node_state); size_t slot_index = compute_slot_index(block, page_index); uvm_cpu_chunk_t **small_chunks = mixed->slots[slot_index]; uvm_cpu_chunk_t *merged_chunk; - UVM_ASSERT(uvm_cpu_storage_get_type(block) == UVM_CPU_CHUNK_STORAGE_MIXED); + UVM_ASSERT(uvm_cpu_storage_get_type(node_state) == UVM_CPU_CHUNK_STORAGE_MIXED); UVM_ASSERT(small_chunks); UVM_ASSERT(!test_bit(slot_index, mixed->big_chunks)); @@ -8776,34 +9642,38 @@ static void block_merge_cpu_chunks_to_64k(uvm_va_block_t *block, uvm_page_index_ uvm_kvfree(small_chunks); } -static void block_merge_cpu_chunks_to_2m(uvm_va_block_t *block, uvm_page_index_t page_index) +static void block_merge_cpu_chunks_to_2m(uvm_va_block_t *block, uvm_page_index_t page_index, int nid) { - uvm_cpu_chunk_storage_mixed_t *mixed = uvm_cpu_storage_get_ptr(block); + uvm_va_block_cpu_node_state_t *node_state = block_node_state_get(block, nid); + uvm_cpu_chunk_storage_mixed_t *mixed = uvm_cpu_storage_get_ptr(node_state); uvm_cpu_chunk_t **big_chunks = (uvm_cpu_chunk_t **)&mixed->slots; uvm_cpu_chunk_t *merged_chunk; - UVM_ASSERT(uvm_cpu_storage_get_type(block) == UVM_CPU_CHUNK_STORAGE_MIXED); + UVM_ASSERT(uvm_cpu_storage_get_type(node_state) == UVM_CPU_CHUNK_STORAGE_MIXED); UVM_ASSERT(bitmap_full(mixed->big_chunks, MAX_BIG_CPU_CHUNK_SLOTS_PER_UVM_VA_BLOCK)); merged_chunk = uvm_cpu_chunk_merge(big_chunks); - block->cpu.chunks = (unsigned long)merged_chunk | UVM_CPU_CHUNK_STORAGE_CHUNK; + node_state->chunks = (unsigned long)merged_chunk | UVM_CPU_CHUNK_STORAGE_CHUNK; uvm_kvfree(mixed); } -static void block_merge_cpu_chunks_one(uvm_va_block_t *block, uvm_page_index_t page_index) +static void block_merge_cpu_chunks_one(uvm_va_block_t *block, uvm_page_index_t page_index, int nid) { - uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(block, page_index); + uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(block, nid, page_index); uvm_gpu_id_t id; + if (!chunk) + return; + if (uvm_cpu_chunk_get_size(chunk) == UVM_CHUNK_SIZE_4K) { - block_merge_cpu_chunks_to_64k(block, page_index); + block_merge_cpu_chunks_to_64k(block, page_index, nid); } else { UVM_ASSERT(uvm_cpu_chunk_get_size(chunk) == UVM_CHUNK_SIZE_64K); - block_merge_cpu_chunks_to_2m(block, page_index); + block_merge_cpu_chunks_to_2m(block, page_index, nid); } - chunk = uvm_cpu_chunk_get_chunk_for_page(block, page_index); + chunk = uvm_cpu_chunk_get_chunk_for_page(block, nid, page_index); for_each_gpu_id(id) { NvU64 gpu_mapping_addr; @@ -8826,50 +9696,56 @@ static void block_merge_cpu_chunks_one(uvm_va_block_t *block, uvm_page_index_t p static void block_merge_cpu_chunks(uvm_va_block_t *existing, uvm_va_block_t *new) { uvm_page_index_t page_index = uvm_va_block_cpu_page_index(existing, new->start); - uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(existing, page_index); uvm_chunk_sizes_mask_t merge_sizes = uvm_cpu_chunk_get_allocation_sizes(); uvm_chunk_size_t largest_size; - uvm_chunk_size_t chunk_size; - uvm_chunk_size_t merge_size; size_t block_size = uvm_va_block_size(existing); + int nid; - if (!chunk || uvm_cpu_chunk_is_physical(chunk)) - return; - - chunk_size = uvm_cpu_chunk_get_size(chunk); - - // Remove all CPU chunk sizes above the size of the existing VA block. // Since block sizes are not always powers of 2, use the largest power of 2 // less than or equal to the block size since we can't merge to a size // larger than the block's size. largest_size = rounddown_pow_of_two(block_size); - merge_sizes &= (largest_size | (largest_size - 1)); - // Remove all CPU chunk sizes smaller than the size of the chunk being merged up. - merge_sizes &= ~(chunk_size | (chunk_size - 1)); + for_each_possible_uvm_node(nid) { + uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(existing, nid, page_index); + uvm_va_block_cpu_node_state_t *node_state = block_node_state_get(existing, nid); + uvm_chunk_size_t chunk_size; + uvm_chunk_size_t merge_size; - for_each_chunk_size(merge_size, merge_sizes) { - uvm_va_block_region_t chunk_region; + if (!chunk || uvm_cpu_chunk_is_physical(chunk)) + continue; - // The block has to fully contain the VA range after the merge. - if (!uvm_va_block_contains_address(existing, UVM_ALIGN_DOWN(new->start, merge_size)) || - !uvm_va_block_contains_address(existing, UVM_ALIGN_DOWN(new->start, merge_size) + merge_size - 1)) - break; + chunk_size = uvm_cpu_chunk_get_size(chunk); - chunk_region = uvm_va_block_chunk_region(existing, merge_size, page_index); + // Remove all CPU chunk sizes above the size of the existing VA block. + merge_sizes &= (largest_size | (largest_size - 1)); - // If not all pages in the region covered by the chunk are allocated, - // we can't merge. - if (!uvm_page_mask_region_full(&existing->cpu.allocated, chunk_region)) - break; + // Remove all CPU chunk sizes smaller than the size of the chunk being merged up. + merge_sizes &= ~(chunk_size | (chunk_size - 1)); - block_merge_cpu_chunks_one(existing, chunk_region.first); - chunk = uvm_cpu_chunk_get_chunk_for_page(existing, page_index); - if (uvm_cpu_chunk_is_physical(chunk)) - break; - } + for_each_chunk_size(merge_size, merge_sizes) { + uvm_va_block_region_t chunk_region; + + // The block has to fully contain the VA range after the merge. + if (!uvm_va_block_contains_address(existing, UVM_ALIGN_DOWN(new->start, merge_size)) || + !uvm_va_block_contains_address(existing, UVM_ALIGN_DOWN(new->start, merge_size) + merge_size - 1)) + break; + + chunk_region = uvm_va_block_chunk_region(existing, merge_size, page_index); + + // If not all pages in the region covered by the chunk are allocated, + // we can't merge. + if (!uvm_page_mask_region_full(&node_state->allocated, chunk_region)) + break; + + block_merge_cpu_chunks_one(existing, chunk_region.first, nid); + chunk = uvm_cpu_chunk_get_chunk_for_page(existing, nid, page_index); + if (uvm_cpu_chunk_is_physical(chunk)) + break; + } - block_free_cpu_chunk_storage(new); + block_free_cpu_chunk_storage(new, nid); + } } // Pre-allocate everything which doesn't require retry on both existing and new @@ -8977,7 +9853,7 @@ static void block_set_processor_masks(uvm_va_block_t *block) uvm_processor_mask_set(&block->mapped, UVM_ID_CPU); } - if (uvm_page_mask_region_empty(&block->cpu.resident, block_region)) { + if (uvm_page_mask_region_empty(uvm_va_block_resident_mask_get(block, UVM_ID_CPU, NUMA_NO_NODE), block_region)) { uvm_va_space_t *va_space = uvm_va_block_get_va_space(block); if (uvm_processor_mask_get_gpu_count(&va_space->can_access[UVM_ID_CPU_VALUE]) == 0) @@ -9046,6 +9922,7 @@ static void block_split_cpu(uvm_va_block_t *existing, uvm_va_block_t *new) uvm_page_index_t next_page_index; uvm_cpu_chunk_t *chunk; uvm_va_range_t *existing_va_range = existing->va_range; + int nid; if (existing_va_range) { UVM_ASSERT(existing->va_range->type == UVM_VA_RANGE_TYPE_MANAGED); @@ -9063,30 +9940,35 @@ static void block_split_cpu(uvm_va_block_t *existing, uvm_va_block_t *new) // We don't have to unmap the CPU since its virtual -> physical mappings // don't change. - page_index = uvm_va_block_next_page_in_mask(block_region, &existing->cpu.allocated, split_page_index - 1); + for_each_possible_uvm_node(nid) { + uvm_page_mask_t *existing_resident_mask = uvm_va_block_resident_mask_get(existing, UVM_ID_CPU, nid); + uvm_page_mask_t *new_resident_mask = uvm_va_block_resident_mask_get(new, UVM_ID_CPU, nid); - for_each_cpu_chunk_in_block_region_safe(chunk, - page_index, - next_page_index, - existing, - uvm_va_block_region(split_page_index, block_region.outer)) { - uvm_page_index_t new_chunk_page_index; - NV_STATUS status; + for_each_cpu_chunk_in_block_region_safe(chunk, + page_index, + next_page_index, + existing, + nid, + uvm_va_block_region(split_page_index, block_region.outer)) { + uvm_page_index_t new_chunk_page_index; + NV_STATUS status; - uvm_cpu_chunk_remove_from_block(existing, page_index); + uvm_cpu_chunk_remove_from_block(existing, nid, page_index); - // The chunk has to be adjusted for the new block before inserting it. - new_chunk_page_index = page_index - split_page_index; + // The chunk has to be adjusted for the new block before inserting it. + new_chunk_page_index = page_index - split_page_index; - // This should never fail because all necessary storage was allocated - // in block_presplit_cpu_chunks(). - status = uvm_cpu_chunk_insert_in_block(new, chunk, new_chunk_page_index); - UVM_ASSERT(status == NV_OK); - } + // This should never fail because all necessary storage was allocated + // in block_presplit_cpu_chunks(). + status = uvm_cpu_chunk_insert_in_block(new, chunk, new_chunk_page_index); + UVM_ASSERT(status == NV_OK); + } - new->cpu.ever_mapped = existing->cpu.ever_mapped; + block_split_page_mask(existing_resident_mask, existing_pages, new_resident_mask, new_pages); + } block_split_page_mask(&existing->cpu.resident, existing_pages, &new->cpu.resident, new_pages); + new->cpu.ever_mapped = existing->cpu.ever_mapped; for (pte_bit = 0; pte_bit < UVM_PTE_BITS_CPU_MAX; pte_bit++) block_split_page_mask(&existing->cpu.pte_bits[pte_bit], existing_pages, &new->cpu.pte_bits[pte_bit], new_pages); @@ -9236,6 +10118,7 @@ static void block_split_gpu(uvm_va_block_t *existing, uvm_va_block_t *new, uvm_g size_t num_chunks, i; uvm_cpu_chunk_t *cpu_chunk; uvm_page_index_t page_index; + int nid; if (!existing_gpu_state) return; @@ -9249,10 +10132,12 @@ static void block_split_gpu(uvm_va_block_t *existing, uvm_va_block_t *new, uvm_g UVM_ASSERT(PAGE_ALIGNED(existing->start)); existing_pages = (new->start - existing->start) / PAGE_SIZE; - for_each_cpu_chunk_in_block(cpu_chunk, page_index, new) { - uvm_pmm_sysmem_mappings_reparent_gpu_mapping(&gpu->pmm_reverse_sysmem_mappings, - uvm_cpu_chunk_get_gpu_phys_addr(cpu_chunk, gpu->parent), - new); + for_each_possible_uvm_node(nid) { + for_each_cpu_chunk_in_block(cpu_chunk, page_index, new, nid) { + uvm_pmm_sysmem_mappings_reparent_gpu_mapping(&gpu->pmm_reverse_sysmem_mappings, + uvm_cpu_chunk_get_gpu_phys_addr(cpu_chunk, gpu->parent), + new); + } } block_copy_split_gpu_chunks(existing, new, gpu); @@ -9483,10 +10368,12 @@ NV_STATUS uvm_va_block_split_locked(uvm_va_block_t *existing_va_block, &new_block->read_duplicated_pages, uvm_va_block_num_cpu_pages(new_block)); - block_split_page_mask(&existing_va_block->maybe_mapped_pages, - uvm_va_block_num_cpu_pages(existing_va_block), - &new_block->maybe_mapped_pages, - uvm_va_block_num_cpu_pages(new_block)); + if (!uvm_va_block_is_hmm(existing_va_block)) { + block_split_page_mask(&existing_va_block->maybe_mapped_pages, + uvm_va_block_num_cpu_pages(existing_va_block), + &new_block->maybe_mapped_pages, + uvm_va_block_num_cpu_pages(new_block)); + } block_set_processor_masks(existing_va_block); block_set_processor_masks(new_block); @@ -9506,7 +10393,10 @@ NV_STATUS uvm_va_block_split_locked(uvm_va_block_t *existing_va_block, UVM_ASSERT(block_check_mappings(new_block)); } else { - block_free_cpu_chunk_storage(new_block); + int nid; + + for_each_possible_uvm_node(nid) + block_free_cpu_chunk_storage(new_block, nid); } uvm_mutex_unlock_no_tracking(&new_block->lock); @@ -9868,7 +10758,8 @@ uvm_prot_t uvm_va_block_page_compute_highest_permission(uvm_va_block_t *va_block // Fast path: if the page is not mapped anywhere else, it can be safely // mapped with RWA permission - if (!uvm_page_mask_test(&va_block->maybe_mapped_pages, page_index)) + if (!uvm_page_mask_test(&va_block->maybe_mapped_pages, page_index) && + !uvm_va_block_is_hmm(va_block)) return UVM_PROT_READ_WRITE_ATOMIC; block_page_authorized_processors(va_block, page_index, UVM_PROT_READ_WRITE_ATOMIC, &atomic_mappings); @@ -10155,30 +11046,6 @@ static uvm_processor_id_t block_select_residency(uvm_va_block_t *va_block, uvm_processor_mask_test(&va_space->accessible_from[uvm_id_value(preferred_location)], processor_id)) return preferred_location; - // Check if we should map the closest resident processor remotely on remote CPU fault - // - // When faulting on CPU, there's a linux process on behalf of it, which is associated - // with a unique VM pointed by current->mm. A block of memory residing on GPU is also - // associated with VM, pointed by va_block_context->mm. If they match, it's a regular - // (local) fault, and we may want to migrate a page from GPU to CPU. - // If it's a 'remote' fault, i.e. linux process differs from one associated with block - // VM, we might preserve residence. - // - // Establishing a remote fault without access counters means the memory could stay in - // the wrong spot for a long time, which is why we prefer to avoid creating remote - // mappings. However when NIC accesses a memory residing on GPU, it's worth to keep it - // in place for NIC accesses. - // - // The logic that's used to detect remote faulting also keeps memory in place for - // ptrace accesses. We would prefer to control those policies separately, but the - // NIC case takes priority. - if (UVM_ID_IS_CPU(processor_id) && - uvm_processor_mask_test(&va_space->accessible_from[uvm_id_value(closest_resident_processor)], processor_id) && - va_block_context->mm != current->mm) { - UVM_ASSERT(va_block_context->mm != NULL); - return closest_resident_processor; - } - // If the page is resident on a processor other than the preferred location, // or the faulting processor can't access the preferred location, we select // the faulting processor as the new residency. @@ -10214,9 +11081,14 @@ uvm_processor_id_t uvm_va_block_select_residency(uvm_va_block_t *va_block, // If the intended residency doesn't have memory, fall back to the CPU. if (!block_processor_has_memory(va_block, id)) { *read_duplicate = false; - return UVM_ID_CPU; + id = UVM_ID_CPU; } + // Set the destination NUMA node unconditionally since it could be used + // for CPU allocations (if staging pages are needed) even if the new + // residency is not the CPU. + va_block_context->make_resident.dest_nid = policy->preferred_nid; + return id; } @@ -10260,7 +11132,7 @@ static void uvm_va_block_get_prefetch_hint(uvm_va_block_t *va_block, // Update prefetch tracking structure with the pages that will migrate // due to faults uvm_perf_prefetch_get_hint_va_block(va_block, - &service_context->block_context, + service_context->block_context, new_residency, new_residency_mask, service_context->region, @@ -10304,11 +11176,11 @@ NV_STATUS uvm_va_block_service_copy(uvm_processor_id_t processor_id, { uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); uvm_processor_mask_t *all_involved_processors = - &service_context->block_context.make_resident.all_involved_processors; + &service_context->block_context->make_resident.all_involved_processors; uvm_page_mask_t *new_residency_mask = &service_context->per_processor_masks[uvm_id_value(new_residency)].new_residency; - uvm_page_mask_t *did_migrate_mask = &service_context->block_context.make_resident.pages_changed_residency; - uvm_page_mask_t *caller_page_mask = &service_context->block_context.caller_page_mask; + uvm_page_mask_t *did_migrate_mask = &service_context->block_context->make_resident.pages_changed_residency; + uvm_page_mask_t *caller_page_mask = &service_context->block_context->caller_page_mask; uvm_make_resident_cause_t cause; NV_STATUS status; @@ -10343,7 +11215,7 @@ NV_STATUS uvm_va_block_service_copy(uvm_processor_id_t processor_id, &service_context->read_duplicate_mask)) { status = uvm_va_block_make_resident_read_duplicate(va_block, block_retry, - &service_context->block_context, + service_context->block_context, new_residency, service_context->region, caller_page_mask, @@ -10359,7 +11231,7 @@ NV_STATUS uvm_va_block_service_copy(uvm_processor_id_t processor_id, uvm_page_mask_copy(caller_page_mask, new_residency_mask); status = uvm_va_block_make_resident_copy(va_block, block_retry, - &service_context->block_context, + service_context->block_context, new_residency, service_context->region, caller_page_mask, @@ -10417,11 +11289,11 @@ NV_STATUS uvm_va_block_service_finish(uvm_processor_id_t processor_id, uvm_va_block_t *va_block, uvm_service_block_context_t *service_context) { - uvm_processor_id_t new_residency = service_context->block_context.make_resident.dest_id; + uvm_processor_id_t new_residency = service_context->block_context->make_resident.dest_id; uvm_page_mask_t *new_residency_mask = &service_context->per_processor_masks[uvm_id_value(new_residency)].new_residency; - uvm_page_mask_t *did_migrate_mask = &service_context->block_context.make_resident.pages_changed_residency; - uvm_page_mask_t *caller_page_mask = &service_context->block_context.caller_page_mask; + uvm_page_mask_t *did_migrate_mask = &service_context->block_context->make_resident.pages_changed_residency; + uvm_page_mask_t *caller_page_mask = &service_context->block_context->caller_page_mask; uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); uvm_prot_t new_prot; uvm_page_index_t page_index; @@ -10430,7 +11302,7 @@ NV_STATUS uvm_va_block_service_finish(uvm_processor_id_t processor_id, // Update residency. if (service_context->read_duplicate_count == 0 || !uvm_page_mask_empty(caller_page_mask)) uvm_va_block_make_resident_finish(va_block, - &service_context->block_context, + service_context->block_context, service_context->region, caller_page_mask); @@ -10450,7 +11322,7 @@ NV_STATUS uvm_va_block_service_finish(uvm_processor_id_t processor_id, for_each_va_block_page_in_region_mask(page_index, new_residency_mask, service_context->region) { new_prot = compute_new_permission(va_block, - service_context->block_context.hmm.vma, + service_context->block_context->hmm.vma, page_index, processor_id, new_residency, @@ -10523,7 +11395,7 @@ NV_STATUS uvm_va_block_service_finish(uvm_processor_id_t processor_id, // uvm_va_block_make_resident_read_duplicate, above. if (service_context->operation == UVM_SERVICE_OPERATION_ACCESS_COUNTERS) { UVM_ASSERT(check_access_counters_dont_revoke(va_block, - &service_context->block_context, + service_context->block_context, service_context->region, &revoke_processors, &service_context->revocation_mask, @@ -10532,7 +11404,7 @@ NV_STATUS uvm_va_block_service_finish(uvm_processor_id_t processor_id, // Downgrade other processors' mappings status = uvm_va_block_revoke_prot_mask(va_block, - &service_context->block_context, + service_context->block_context, &revoke_processors, service_context->region, &service_context->revocation_mask, @@ -10562,7 +11434,7 @@ NV_STATUS uvm_va_block_service_finish(uvm_processor_id_t processor_id, // A CPU fault is unexpected if: // curr_prot == RW || (!is_write && curr_prot == RO) status = uvm_va_block_unmap(va_block, - &service_context->block_context, + service_context->block_context, UVM_ID_CPU, service_context->region, map_prot_mask, @@ -10579,13 +11451,13 @@ NV_STATUS uvm_va_block_service_finish(uvm_processor_id_t processor_id, // Map pages that are thrashing first if (service_context->thrashing_pin_count > 0 && va_space->tools.enabled) { - uvm_page_mask_t *helper_page_mask = &service_context->block_context.caller_page_mask; + uvm_page_mask_t *helper_page_mask = &service_context->block_context->caller_page_mask; bool pages_need_mapping = uvm_page_mask_and(helper_page_mask, map_prot_mask, &service_context->thrashing_pin_mask); if (pages_need_mapping) { status = uvm_va_block_map(va_block, - &service_context->block_context, + service_context->block_context, processor_id, service_context->region, helper_page_mask, @@ -10607,7 +11479,7 @@ NV_STATUS uvm_va_block_service_finish(uvm_processor_id_t processor_id, } status = uvm_va_block_map(va_block, - &service_context->block_context, + service_context->block_context, processor_id, service_context->region, map_prot_mask, @@ -10649,7 +11521,7 @@ NV_STATUS uvm_va_block_service_finish(uvm_processor_id_t processor_id, map_thrashing_processors = uvm_perf_thrashing_get_thrashing_processors(va_block, page_addr); status = uvm_va_block_add_mappings_after_migration(va_block, - &service_context->block_context, + service_context->block_context, new_residency, processor_id, uvm_va_block_region_for_page(page_index), @@ -10669,7 +11541,7 @@ NV_STATUS uvm_va_block_service_finish(uvm_processor_id_t processor_id, // Map the rest of pages in a single shot status = uvm_va_block_add_mappings_after_migration(va_block, - &service_context->block_context, + service_context->block_context, new_residency, processor_id, service_context->region, @@ -10694,7 +11566,7 @@ NV_STATUS uvm_va_block_service_locked(uvm_processor_id_t processor_id, uvm_assert_mutex_locked(&va_block->lock); UVM_ASSERT(uvm_hmm_check_context_vma_is_valid(va_block, - service_context->block_context.hmm.vma, + service_context->block_context->hmm.vma, service_context->region)); // GPU fault servicing must be done under the VA space read lock. GPU fault @@ -10777,7 +11649,7 @@ NV_STATUS uvm_va_block_check_logical_permissions(uvm_va_block_t *va_block, return NV_ERR_INVALID_OPERATION; } else { - uvm_va_space_t *va_space = va_range->va_space; + uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); return uvm_processor_mask_test( &va_space->accessible_from[uvm_id_value(uvm_va_range_get_policy(va_range)->preferred_location)], @@ -10856,7 +11728,7 @@ static NV_STATUS block_cpu_fault_locked(uvm_va_block_t *va_block, UVM_ASSERT(fault_addr >= va_block->start); UVM_ASSERT(fault_addr <= va_block->end); - uvm_assert_mmap_lock_locked(service_context->block_context.mm); + uvm_assert_mmap_lock_locked(service_context->block_context->mm); policy = uvm_va_policy_get(va_block, fault_addr); @@ -10873,7 +11745,7 @@ static NV_STATUS block_cpu_fault_locked(uvm_va_block_t *va_block, // Check logical permissions page_index = uvm_va_block_cpu_page_index(va_block, fault_addr); status = uvm_va_block_check_logical_permissions(va_block, - &service_context->block_context, + service_context->block_context, UVM_ID_CPU, page_index, fault_access_type, @@ -10905,7 +11777,7 @@ static NV_STATUS block_cpu_fault_locked(uvm_va_block_t *va_block, // Compute new residency and update the masks new_residency = uvm_va_block_select_residency(va_block, - &service_context->block_context, + service_context->block_context, page_index, UVM_ID_CPU, uvm_fault_access_type_mask_bit(fault_access_type), @@ -11251,7 +12123,7 @@ NV_STATUS uvm_va_block_write_from_cpu(uvm_va_block_t *va_block, if (UVM_ID_IS_CPU(proc)) { char *mapped_page; - struct page *page = uvm_cpu_chunk_get_cpu_page(va_block, page_index); + struct page *page = uvm_va_block_get_cpu_page(va_block, page_index); void *src = uvm_mem_get_cpu_addr_kernel(src_mem); status = uvm_tracker_wait(&va_block->tracker); @@ -11272,7 +12144,9 @@ NV_STATUS uvm_va_block_write_from_cpu(uvm_va_block_t *va_block, dst_gpu = block_get_gpu(va_block, proc); - dst_gpu_address = block_phys_page_copy_address(va_block, block_phys_page(proc, page_index), dst_gpu); + dst_gpu_address = block_phys_page_copy_address(va_block, + block_phys_page(proc, NUMA_NO_NODE, page_index), + dst_gpu); dst_gpu_address.address += page_offset; return va_block_write_cpu_to_gpu(va_block, dst_gpu, dst_gpu_address, dst, src_mem, size); @@ -11333,7 +12207,7 @@ NV_STATUS uvm_va_block_read_to_cpu(uvm_va_block_t *va_block, uvm_mem_t *dst_mem, else if (UVM_ID_IS_CPU(proc)) { NV_STATUS status; char *mapped_page; - struct page *page = uvm_cpu_chunk_get_cpu_page(va_block, page_index); + struct page *page = uvm_va_block_get_cpu_page(va_block, page_index); status = uvm_tracker_wait(&va_block->tracker); if (status != NV_OK) @@ -11349,7 +12223,9 @@ NV_STATUS uvm_va_block_read_to_cpu(uvm_va_block_t *va_block, uvm_mem_t *dst_mem, uvm_gpu_address_t src_gpu_address; uvm_gpu_t *gpu = block_get_gpu(va_block, proc); - src_gpu_address = block_phys_page_copy_address(va_block, block_phys_page(proc, page_index), gpu); + src_gpu_address = block_phys_page_copy_address(va_block, + block_phys_page(proc, NUMA_NO_NODE, page_index), + gpu); src_gpu_address.address += page_offset; return va_block_read_gpu_to_cpu(va_block, dst_mem, gpu, src_gpu_address, src, size); @@ -11539,7 +12415,7 @@ NV_STATUS uvm_va_block_evict_chunks(uvm_va_block_t *va_block, goto out; // Only move pages resident on the GPU - uvm_page_mask_and(pages_to_evict, pages_to_evict, uvm_va_block_resident_mask_get(va_block, gpu->id)); + uvm_page_mask_and(pages_to_evict, pages_to_evict, uvm_va_block_resident_mask_get(va_block, gpu->id, NUMA_NO_NODE)); uvm_processor_mask_zero(&block_context->make_resident.all_involved_processors); if (uvm_va_block_is_hmm(va_block)) { @@ -11776,6 +12652,12 @@ NV_STATUS uvm_test_va_block_inject_error(UVM_TEST_VA_BLOCK_INJECT_ERROR_PARAMS * va_block_test->cpu_chunk_allocation_size_mask = params->cpu_chunk_allocation_size_mask & UVM_CPU_CHUNK_SIZES; } + if (params->cpu_chunk_allocation_target_id != NUMA_NO_NODE) + va_block_test->cpu_chunk_allocation_target_id = params->cpu_chunk_allocation_target_id; + + if (params->cpu_chunk_allocation_actual_id != NUMA_NO_NODE) + va_block_test->cpu_chunk_allocation_actual_id = params->cpu_chunk_allocation_actual_id; + if (params->eviction_error) va_block_test->inject_eviction_error = params->eviction_error; @@ -12028,6 +12910,7 @@ NV_STATUS uvm_test_va_residency_info(UVM_TEST_VA_RESIDENCY_INFO_PARAMS *params, params->resident_on_count = 0; params->populated_on_count = 0; params->mapped_on_count = 0; + params->resident_nid = -1; status = NV_OK; @@ -12040,19 +12923,34 @@ NV_STATUS uvm_test_va_residency_info(UVM_TEST_VA_RESIDENCY_INFO_PARAMS *params, page_index = uvm_va_block_cpu_page_index(block, addr); uvm_va_block_page_resident_processors(block, page_index, &resident_on_mask); + params->resident_nid = -1; for_each_id_in_mask(id, &resident_on_mask) { - block_phys_page_t block_page = block_phys_page(id, page_index); + block_phys_page_t block_page; + int nid = block_get_page_node_residency(block, page_index); + + block_page = block_phys_page(id, nid, page_index); uvm_va_space_processor_uuid(va_space, ¶ms->resident_on[count], id); params->resident_physical_size[count] = block_phys_page_size(block, block_page); if (UVM_ID_IS_CPU(id)) { - params->resident_physical_address[count] = page_to_phys(uvm_cpu_chunk_get_cpu_page(block, page_index)); + params->resident_physical_address[count] = page_to_phys(uvm_va_block_get_cpu_page(block, page_index)); + params->resident_nid = nid; + + // Check that the page is only resident on a single CPU NUMA node. + for_each_possible_uvm_node(nid) { + if (uvm_va_block_cpu_is_page_resident_on(block, nid, page_index) && nid != params->resident_nid) { + status = NV_ERR_INVALID_STATE; + goto out; + } + } } else { params->resident_physical_address[count] = block_phys_page_address(block, block_page, uvm_va_space_get_gpu(va_space, id)).address; } + ++count; } + params->resident_on_count = count; count = 0; @@ -12060,6 +12958,7 @@ NV_STATUS uvm_test_va_residency_info(UVM_TEST_VA_RESIDENCY_INFO_PARAMS *params, uvm_processor_id_t processor_to_map; block_phys_page_t block_page; NvU32 page_size = uvm_va_block_page_size_processor(block, id, page_index); + int nid = NUMA_NO_NODE; if (page_size == 0) continue; @@ -12069,7 +12968,10 @@ NV_STATUS uvm_test_va_residency_info(UVM_TEST_VA_RESIDENCY_INFO_PARAMS *params, params->mapping_type[count] = g_uvm_prot_to_test_pte_mapping[block_page_prot(block, id, page_index)]; UVM_ASSERT(params->mapping_type[count] != UVM_TEST_PTE_MAPPING_INVALID); processor_to_map = block_get_processor_to_map(block, id, page_index); - block_page = block_phys_page(processor_to_map, page_index); + if (UVM_ID_IS_CPU(processor_to_map)) + nid = block_get_page_node_residency(block, page_index); + + block_page = block_phys_page(processor_to_map, nid, page_index); if (!UVM_ID_IS_CPU(id)) { uvm_gpu_phys_address_t gpu_phys_addr = block_phys_page_address(block, @@ -12093,7 +12995,7 @@ NV_STATUS uvm_test_va_residency_info(UVM_TEST_VA_RESIDENCY_INFO_PARAMS *params, for_each_gpu_id(id) { NvU32 page_size = uvm_va_block_page_size_processor(block, id, page_index); uvm_reverse_map_t sysmem_page; - uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(block, page_index); + uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page_resident(block, page_index); size_t num_pages; uvm_gpu_t *gpu; diff --git a/kernel-open/nvidia-uvm/uvm_va_block.h b/kernel-open/nvidia-uvm/uvm_va_block.h index 364cba79df..fdd4a0d2f7 100644 --- a/kernel-open/nvidia-uvm/uvm_va_block.h +++ b/kernel-open/nvidia-uvm/uvm_va_block.h @@ -44,6 +44,7 @@ #include #include +#include // VA blocks are the leaf nodes in the uvm_va_space tree for managed allocations // (VA ranges with type == UVM_VA_RANGE_TYPE_MANAGED): @@ -229,6 +230,42 @@ typedef struct } uvm_va_block_gpu_state_t; +typedef struct +{ + // Per-page residency bit vector, used for fast traversal of resident + // pages. + // + // A set bit means the CPU has a coherent copy of the physical page + // resident in the NUMA node's memory, and that a CPU chunk for the + // corresponding page index has been allocated. This does not mean that + // the coherent copy is currently mapped anywhere, however. A page may be + // resident on multiple processors (but not multiple CPU NUMA nodes) when in + // read-duplicate mode. + // + // A cleared bit means the CPU NUMA node does not have a coherent copy of + // that page resident. A CPU chunk for the corresponding page index may or + // may not have been allocated. If the chunk is present, it's a cached chunk + // which can be reused in the future. + // + // Allocating PAGES_PER_UVM_VA_BLOCK is overkill when the block is + // smaller than UVM_VA_BLOCK_SIZE, but it's not much extra memory + // overhead on the whole. + uvm_page_mask_t resident; + + // Per-page allocation bit vector. + // + // A set bit means that a CPU chunk has been allocated for the + // corresponding page index on this NUMA node. + uvm_page_mask_t allocated; + + // CPU memory chunks represent physically contiguous CPU memory + // allocations. See uvm_pmm_sysmem.h for more details on CPU chunks. + // This member is meant to hold an opaque value indicating the CPU + // chunk storage method. For more details on CPU chunk storage, + // see uvm_cpu_chunk_storage_type_t in uvm_va_block.c. + unsigned long chunks; +} uvm_va_block_cpu_node_state_t; + // TODO: Bug 1766180: Worst-case we could have one of these per system page. // Options: // 1) Rely on the OOM killer to prevent the user from trying to do that @@ -306,38 +343,30 @@ struct uvm_va_block_struct struct { - // Per-page residency bit vector, used for fast traversal of resident - // pages. - // - // A set bit means the CPU has a coherent copy of the physical page - // resident in its memory, and that the corresponding entry in the pages - // array is present. This does not mean that the coherent copy is - // currently mapped anywhere, however. A page may be resident on - // multiple processors when in read-duplicate mode. - // - // A cleared bit means the CPU does not have a coherent copy of that - // page resident. The corresponding entry in the pages array may or may - // not present. If the entry is present, it's a cached page which can be - // reused in the future. - // - // Allocating PAGES_PER_UVM_VA_BLOCK is overkill when the block is - // smaller than UVM_VA_BLOCK_SIZE, but it's not much extra memory - // overhead on the whole. - uvm_page_mask_t resident; - - // CPU memory chunks represent physically contiguous CPU memory - // allocations. See uvm_pmm_sysmem.h for more details on CPU chunks. - // This member is meant to hold an opaque value indicating the CPU - // chunk storage method. For more details on CPU chunk storage, - // see uvm_cpu_chunk_storage_type_t in uvm_va_block.c. - unsigned long chunks; + // Per-NUMA node tracking of CPU allocations. + // This is a dense array with one entry per possible NUMA node. + uvm_va_block_cpu_node_state_t **node_state; // Per-page allocation bit vector. // // A set bit means that a CPU page has been allocated for the - // corresponding page index. + // corresponding page index on at least one CPU NUMA node. uvm_page_mask_t allocated; + // Per-page residency bit vector. See + // uvm_va_block_cpu_numa_state_t::resident for a detailed description. + // This mask is a cumulative mask (logical OR) of all + // uvm_va_block_cpu_node_state_t::resident masks. It is meant to be used + // only for fast testing of page residency when it matters only if the + // page is resident on the CPU. + // + // Note that this mask cannot be set directly as this will cause + // inconsistencies between this mask and the per-NUMA residency masks. + // In order to properly maintain consistency between the per-NUMA masks + // and this one, uvm_va_block_cpu_[set|clear]_residency_*() helpers + // should be used. + uvm_page_mask_t resident; + // Per-page mapping bit vectors, one per bit we need to track. These are // used for fast traversal of valid mappings in the block. These contain // all non-address bits needed to establish a virtual mapping on this @@ -418,7 +447,8 @@ struct uvm_va_block_struct uvm_page_mask_t read_duplicated_pages; // Mask to keep track of the pages that are not mapped on any non-UVM-Lite - // processor. + // processor. This mask is not used for HMM because the CPU can map pages + // at any time without notifying the driver. // 0: Page is definitely not mapped by any processors // 1: Page may or may not be mapped by a processor // @@ -525,6 +555,13 @@ struct uvm_va_block_wrapper_struct // a successful migration if this error flag is cleared. NvU32 inject_cpu_pages_allocation_error_count; + // A NUMA node ID on which any CPU chunks will be allocated from. + // This will override any other setting and/or policy. + // Note that the kernel is still free to allocate from any of the + // nodes in the thread's policy. + int cpu_chunk_allocation_target_id; + int cpu_chunk_allocation_actual_id; + // Force the next eviction attempt on this block to fail. Used for // testing only. bool inject_eviction_error; @@ -668,17 +705,12 @@ void uvm_va_block_context_free(uvm_va_block_context_t *va_block_context); // Initialization of an already-allocated uvm_va_block_context_t. // // mm is used to initialize the value of va_block_context->mm. NULL is allowed. -static void uvm_va_block_context_init(uvm_va_block_context_t *va_block_context, struct mm_struct *mm) -{ - UVM_ASSERT(va_block_context); +void uvm_va_block_context_init(uvm_va_block_context_t *va_block_context, struct mm_struct *mm); - // Write garbage into the VA Block context to ensure that the UVM code - // clears masks appropriately - if (UVM_IS_DEBUG()) - memset(va_block_context, 0xff, sizeof(*va_block_context)); - - va_block_context->mm = mm; -} +// Return the preferred NUMA node ID for the block's policy. +// If the preferred node ID is NUMA_NO_NODE, the current NUMA node ID +// is returned. +int uvm_va_block_context_get_node(uvm_va_block_context_t *va_block_context); // TODO: Bug 1766480: Using only page masks instead of a combination of regions // and page masks could simplify the below APIs and their implementations @@ -734,6 +766,9 @@ static void uvm_va_block_context_init(uvm_va_block_context_t *va_block_context, // those masks. It is the caller's responsiblity to zero the masks or // not first. // +// va_block_context->make_resident.dest_nid is used to guide the NUMA node for +// CPU allocations. +// // Notably any status other than NV_OK indicates that the block's lock might // have been unlocked and relocked. // @@ -1377,8 +1412,14 @@ static uvm_va_block_test_t *uvm_va_block_get_test(uvm_va_block_t *va_block) // Get the page residency mask for a processor if it's known to be there. // +// If the processor is the CPU, the residency mask for the NUMA node ID +// specified by nid will be returned (see +// uvm_va_block_cpu_node_state_t::resident). If nid is NUMA_NO_NODE, +// the cumulative CPU residency mask will be returned (see +// uvm_va_block_t::cpu::resident). +// // If the processor is a GPU, this will assert that GPU state is indeed present. -uvm_page_mask_t *uvm_va_block_resident_mask_get(uvm_va_block_t *block, uvm_processor_id_t processor); +uvm_page_mask_t *uvm_va_block_resident_mask_get(uvm_va_block_t *block, uvm_processor_id_t processor, int nid); // Get the page mapped mask for a processor. The returned mask cannot be // directly modified by the caller @@ -1386,6 +1427,13 @@ uvm_page_mask_t *uvm_va_block_resident_mask_get(uvm_va_block_t *block, uvm_proce // If the processor is a GPU, this will assert that GPU state is indeed present. const uvm_page_mask_t *uvm_va_block_map_mask_get(uvm_va_block_t *block, uvm_processor_id_t processor); +// Return a mask of non-UVM-Lite pages that are unmapped within the given +// region. +// Locking: The block lock must be held. +void uvm_va_block_unmapped_pages_get(uvm_va_block_t *va_block, + uvm_va_block_region_t region, + uvm_page_mask_t *out_mask); + // VA block lookup functions. There are a number of permutations which might be // useful, such as looking up the block from {va_space, va_range} x {addr, // block index}. The ones implemented here and in uvm_va_range.h support the @@ -1756,17 +1804,28 @@ static bool uvm_page_mask_full(const uvm_page_mask_t *mask) return bitmap_full(mask->bitmap, PAGES_PER_UVM_VA_BLOCK); } -static bool uvm_page_mask_and(uvm_page_mask_t *mask_out, const uvm_page_mask_t *mask_in1, const uvm_page_mask_t *mask_in2) +static void uvm_page_mask_fill(uvm_page_mask_t *mask) +{ + bitmap_fill(mask->bitmap, PAGES_PER_UVM_VA_BLOCK); +} + +static bool uvm_page_mask_and(uvm_page_mask_t *mask_out, + const uvm_page_mask_t *mask_in1, + const uvm_page_mask_t *mask_in2) { return bitmap_and(mask_out->bitmap, mask_in1->bitmap, mask_in2->bitmap, PAGES_PER_UVM_VA_BLOCK); } -static bool uvm_page_mask_andnot(uvm_page_mask_t *mask_out, const uvm_page_mask_t *mask_in1, const uvm_page_mask_t *mask_in2) +static bool uvm_page_mask_andnot(uvm_page_mask_t *mask_out, + const uvm_page_mask_t *mask_in1, + const uvm_page_mask_t *mask_in2) { return bitmap_andnot(mask_out->bitmap, mask_in1->bitmap, mask_in2->bitmap, PAGES_PER_UVM_VA_BLOCK); } -static void uvm_page_mask_or(uvm_page_mask_t *mask_out, const uvm_page_mask_t *mask_in1, const uvm_page_mask_t *mask_in2) +static void uvm_page_mask_or(uvm_page_mask_t *mask_out, + const uvm_page_mask_t *mask_in1, + const uvm_page_mask_t *mask_in2) { bitmap_or(mask_out->bitmap, mask_in1->bitmap, mask_in2->bitmap, PAGES_PER_UVM_VA_BLOCK); } @@ -2036,30 +2095,49 @@ uvm_processor_id_t uvm_va_block_page_get_closest_resident(uvm_va_block_t *va_blo uvm_page_index_t page_index, uvm_processor_id_t processor); +// Mark CPU page page_index as resident on NUMA node specified by nid. +// nid cannot be NUMA_NO_NODE. +void uvm_va_block_cpu_set_resident_page(uvm_va_block_t *va_block, int nid, uvm_page_index_t page_index); + +// Test if a CPU page is resident on NUMA node nid. If nid is NUMA_NO_NODE, +// the function will return True if the page is resident on any CPU NUMA node. +bool uvm_va_block_cpu_is_page_resident_on(uvm_va_block_t *va_block, int nid, uvm_page_index_t page_index); + +// Test if all pages in region are resident on NUMA node nid. If nid is +// NUMA_NO_NODE, the function will test if the pages in the region are +// resident on any CPU NUMA node. +bool uvm_va_block_cpu_is_region_resident_on(uvm_va_block_t *va_block, int nid, uvm_va_block_region_t region); + // Insert a CPU chunk at the given page_index into the va_block. // Locking: The va_block lock must be held. -NV_STATUS uvm_cpu_chunk_insert_in_block(uvm_va_block_t *va_block, - uvm_cpu_chunk_t *chunk, - uvm_page_index_t page_index); +NV_STATUS uvm_cpu_chunk_insert_in_block(uvm_va_block_t *va_block, uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index); // Remove a CPU chunk at the given page_index from the va_block. +// nid cannot be NUMA_NO_NODE. // Locking: The va_block lock must be held. -void uvm_cpu_chunk_remove_from_block(uvm_va_block_t *va_block, - uvm_page_index_t page_index); +void uvm_cpu_chunk_remove_from_block(uvm_va_block_t *va_block, int nid, uvm_page_index_t page_index); -// Return the CPU chunk at the given page_index from the va_block. +// Return the CPU chunk at the given page_index on the given NUMA node from the +// va_block. nid cannot be NUMA_NO_NODE. // Locking: The va_block lock must be held. uvm_cpu_chunk_t *uvm_cpu_chunk_get_chunk_for_page(uvm_va_block_t *va_block, + int nid, uvm_page_index_t page_index); -// Return the CPU chunk at the given page_index from the va_block. +// Return the struct page * from the chunk corresponding to the given page_index +// Locking: The va_block lock must be held. +struct page *uvm_cpu_chunk_get_cpu_page(uvm_va_block_t *va_block, uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index); + +// Return the struct page * of the resident chunk at the given page_index from +// the va_block. The given page_index must be resident on the CPU. // Locking: The va_block lock must be held. -struct page *uvm_cpu_chunk_get_cpu_page(uvm_va_block_t *va_block, - uvm_page_index_t page_index); +struct page *uvm_va_block_get_cpu_page(uvm_va_block_t *va_block, uvm_page_index_t page_index); // Physically map a CPU chunk so it is DMA'able from all registered GPUs. +// nid cannot be NUMA_NO_NODE. // Locking: The va_block lock must be held. NV_STATUS uvm_va_block_map_cpu_chunk_on_gpus(uvm_va_block_t *va_block, + uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index); // Physically unmap a CPU chunk from all registered GPUs. diff --git a/kernel-open/nvidia-uvm/uvm_va_block_types.h b/kernel-open/nvidia-uvm/uvm_va_block_types.h index 7000ce4df1..8d68527884 100644 --- a/kernel-open/nvidia-uvm/uvm_va_block_types.h +++ b/kernel-open/nvidia-uvm/uvm_va_block_types.h @@ -30,6 +30,7 @@ #include "uvm_forward_decl.h" #include +#include // UVM_VA_BLOCK_BITS is 21, meaning the maximum block size is 2MB. Rationale: // - 2MB matches the largest Pascal GPU page size so it's a natural fit @@ -145,6 +146,18 @@ typedef struct unsigned count; } uvm_prot_page_mask_array_t[UVM_PROT_MAX - 1]; +typedef struct +{ + // A per-NUMA-node array of page masks (size num_possible_nodes()) that hold + // the set of CPU pages used by the migration operation. + uvm_page_mask_t **node_masks; + + // Node mask used to iterate over the page masks above. + // If a node's bit is set, it means that the page mask given by + // node_to_index() in node_masks has set pages. + nodemask_t nodes; +} uvm_make_resident_page_tracking_t; + // In the worst case some VA block operations require more state than we should // reasonably store on the stack. Instead, we dynamically allocate VA block // contexts. These are used for almost all operations on VA blocks. @@ -159,6 +172,9 @@ typedef struct // this block_context. uvm_page_mask_t scratch_page_mask; + // Scratch node mask. This follows the same rules as scratch_page_mask; + nodemask_t scratch_node_mask; + // State used by uvm_va_block_make_resident struct uvm_make_resident_context_struct { @@ -181,10 +197,24 @@ typedef struct // Used to perform ECC checks after the migration is done. uvm_processor_mask_t all_involved_processors; + // Page mask used to compute the set of CPU pages for each CPU node. + uvm_page_mask_t node_pages_mask; + // Final residency for the data. This is useful for callees to know if // a migration is part of a staging copy uvm_processor_id_t dest_id; + // Final residency NUMA node if the migration destination is the CPU. + int dest_nid; + + // This structure is used to track CPU pages used for migrations on + // a per-NUMA node basis. + // + // The pages could be used for either migrations to the CPU (used to + // track the destination CPU pages) or staging copies (used to track + // the CPU pages used for the staging). + uvm_make_resident_page_tracking_t cpu_pages_used; + // Event that triggered the call uvm_make_resident_cause_t cause; } make_resident; diff --git a/kernel-open/nvidia-uvm/uvm_va_policy.c b/kernel-open/nvidia-uvm/uvm_va_policy.c index f2c847ebff..f125eefe12 100644 --- a/kernel-open/nvidia-uvm/uvm_va_policy.c +++ b/kernel-open/nvidia-uvm/uvm_va_policy.c @@ -31,6 +31,7 @@ const uvm_va_policy_t uvm_va_policy_default = { .preferred_location = UVM_ID_INVALID, + .preferred_nid = NUMA_NO_NODE, .read_duplication = UVM_READ_DUPLICATION_UNSET, }; diff --git a/kernel-open/nvidia-uvm/uvm_va_policy.h b/kernel-open/nvidia-uvm/uvm_va_policy.h index 11b54ab4ae..7bb6ebd023 100644 --- a/kernel-open/nvidia-uvm/uvm_va_policy.h +++ b/kernel-open/nvidia-uvm/uvm_va_policy.h @@ -24,6 +24,7 @@ #ifndef __UVM_VA_POLICY_H__ #define __UVM_VA_POLICY_H__ +#include #include "uvm_linux.h" #include "uvm_forward_decl.h" #include "uvm_processors.h" @@ -62,6 +63,18 @@ struct uvm_va_policy_struct // This is set to UVM_ID_INVALID if no preferred location is set. uvm_processor_id_t preferred_location; + // If the preferred location is the CPU, this is either the preferred NUMA + // node ID or NUMA_NO_NODE to indicate that there is no preference among + // nodes. + // If preferred_location is a GPU, preferred_nid will be used if CPU + // pages have to be allocated for any staging copies. Otherwise, it is + // not used. + // + // TODO: Bug 4148100 - Preferred_location and preferred_nid should be + // combined into a new type that combines the processor and NUMA node + // ID. + int preferred_nid; + // Mask of processors that are accessing this VA range and should have // their page tables updated to access the (possibly remote) pages. uvm_processor_mask_t accessed_by; diff --git a/kernel-open/nvidia-uvm/uvm_va_range.c b/kernel-open/nvidia-uvm/uvm_va_range.c index d8291e7fcd..adceea8a2b 100644 --- a/kernel-open/nvidia-uvm/uvm_va_range.c +++ b/kernel-open/nvidia-uvm/uvm_va_range.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2023 NVIDIA Corporation + Copyright (c) 2015-2022 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -162,9 +162,7 @@ static uvm_va_range_t *uvm_va_range_alloc_managed(uvm_va_space_t *va_space, NvU6 goto error; va_range->type = UVM_VA_RANGE_TYPE_MANAGED; - - uvm_va_range_get_policy(va_range)->read_duplication = UVM_READ_DUPLICATION_UNSET; - uvm_va_range_get_policy(va_range)->preferred_location = UVM_ID_INVALID; + va_range->managed.policy = uvm_va_policy_default; va_range->blocks = uvm_kvmalloc_zero(uvm_va_range_num_blocks(va_range) * sizeof(va_range->blocks[0])); if (!va_range->blocks) { @@ -376,7 +374,7 @@ NV_STATUS uvm_va_range_create_semaphore_pool(uvm_va_space_t *va_space, if (status != NV_OK) goto error; - if (i == 0 && g_uvm_global.conf_computing_enabled) + if (i == 0 && g_uvm_global.sev_enabled) mem_alloc_params.dma_owner = gpu; if (attrs.is_cacheable) { @@ -835,7 +833,7 @@ static void uvm_va_range_disable_peer_external(uvm_va_range_t *va_range, range_tree = uvm_ext_gpu_range_tree(va_range, mapping_gpu); uvm_mutex_lock(&range_tree->lock); uvm_ext_gpu_map_for_each_safe(ext_map, ext_map_next, va_range, mapping_gpu) { - if (ext_map->owning_gpu == owning_gpu && !ext_map->is_sysmem) { + if (ext_map->owning_gpu == owning_gpu && (!ext_map->is_sysmem || ext_map->is_egm)) { UVM_ASSERT(deferred_free_list); uvm_ext_gpu_map_destroy(va_range, ext_map, deferred_free_list); } @@ -1807,7 +1805,7 @@ NV_STATUS uvm_api_alloc_semaphore_pool(UVM_ALLOC_SEMAPHORE_POOL_PARAMS *params, if (params->gpuAttributesCount > UVM_MAX_GPUS) return NV_ERR_INVALID_ARGUMENT; - if (g_uvm_global.conf_computing_enabled && params->gpuAttributesCount == 0) + if (g_uvm_global.sev_enabled && params->gpuAttributesCount == 0) return NV_ERR_INVALID_ARGUMENT; // The mm needs to be locked in order to remove stale HMM va_blocks. diff --git a/kernel-open/nvidia-uvm/uvm_va_range.h b/kernel-open/nvidia-uvm/uvm_va_range.h index d76f9eef44..e837924deb 100644 --- a/kernel-open/nvidia-uvm/uvm_va_range.h +++ b/kernel-open/nvidia-uvm/uvm_va_range.h @@ -189,6 +189,7 @@ typedef struct // sysmem was originally allocated under. For the allocation to remain valid // we need to prevent the GPU from going away, similarly to P2P mapped // memory. + // Similarly for EGM memory. // // This field is not used for sparse mappings as they don't have an // allocation and, hence, owning GPU. @@ -208,6 +209,9 @@ typedef struct // backing. bool is_sysmem; + // EGM memory. If true is_sysmem also has to be true and owning_gpu + // has to be valid. + bool is_egm; // GPU page tables mapping the allocation uvm_page_table_range_vec_t pt_range_vec; diff --git a/kernel-open/nvidia-uvm/uvm_va_space.c b/kernel-open/nvidia-uvm/uvm_va_space.c index daa49d2fba..4334eaff07 100644 --- a/kernel-open/nvidia-uvm/uvm_va_space.c +++ b/kernel-open/nvidia-uvm/uvm_va_space.c @@ -222,6 +222,12 @@ NV_STATUS uvm_va_space_create(struct address_space *mapping, uvm_va_space_t **va uvm_down_write_mmap_lock(current->mm); uvm_va_space_down_write(va_space); + va_space->va_block_context = uvm_va_block_context_alloc(NULL); + if (!va_space->va_block_context) { + status = NV_ERR_NO_MEMORY; + goto fail; + } + status = uvm_perf_init_va_space_events(va_space, &va_space->perf_events); if (status != NV_OK) goto fail; @@ -258,6 +264,7 @@ NV_STATUS uvm_va_space_create(struct address_space *mapping, uvm_va_space_t **va fail: uvm_perf_heuristics_unload(va_space); uvm_perf_destroy_va_space_events(&va_space->perf_events); + uvm_va_block_context_free(va_space->va_block_context); uvm_va_space_up_write(va_space); uvm_up_write_mmap_lock(current->mm); @@ -457,8 +464,6 @@ void uvm_va_space_destroy(uvm_va_space_t *va_space) uvm_va_range_destroy(va_range, &deferred_free_list); } - uvm_hmm_va_space_destroy(va_space); - uvm_range_group_radix_tree_destroy(va_space); // Unregister all GPUs in the VA space. Note that this does not release the @@ -466,11 +471,17 @@ void uvm_va_space_destroy(uvm_va_space_t *va_space) for_each_va_space_gpu(gpu, va_space) unregister_gpu(va_space, gpu, NULL, &deferred_free_list, NULL); + uvm_hmm_va_space_destroy(va_space); + uvm_perf_heuristics_unload(va_space); uvm_perf_destroy_va_space_events(&va_space->perf_events); va_space_remove_dummy_thread_contexts(va_space); + // Destroy the VA space's block context node tracking after all ranges have + // been destroyed as the VA blocks may reference it. + uvm_va_block_context_free(va_space->va_block_context); + uvm_va_space_up_write(va_space); UVM_ASSERT(uvm_processor_mask_empty(&va_space->registered_gpus)); @@ -688,7 +699,7 @@ NV_STATUS uvm_va_space_register_gpu(uvm_va_space_t *va_space, // Mixing coherent and non-coherent GPUs is not supported for_each_va_space_gpu(other_gpu, va_space) { - if (uvm_gpu_is_coherent(gpu->parent) != uvm_gpu_is_coherent(other_gpu->parent)) { + if (uvm_parent_gpu_is_coherent(gpu->parent) != uvm_parent_gpu_is_coherent(other_gpu->parent)) { status = NV_ERR_INVALID_DEVICE; goto done; } @@ -729,7 +740,7 @@ NV_STATUS uvm_va_space_register_gpu(uvm_va_space_t *va_space, processor_mask_array_set(va_space->has_nvlink, UVM_ID_CPU, gpu->id); } - if (uvm_gpu_is_coherent(gpu->parent)) { + if (uvm_parent_gpu_is_coherent(gpu->parent)) { processor_mask_array_set(va_space->has_native_atomics, gpu->id, UVM_ID_CPU); if (gpu->mem_info.numa.enabled) { @@ -1540,7 +1551,6 @@ static void remove_gpu_va_space(uvm_gpu_va_space_t *gpu_va_space, atomic_inc(&va_space->gpu_va_space_deferred_free.num_pending); uvm_processor_mask_clear(&va_space->registered_gpu_va_spaces, gpu_va_space->gpu->id); - uvm_processor_mask_clear_atomic(&va_space->needs_fault_buffer_flush, gpu_va_space->gpu->id); va_space->gpu_va_spaces[uvm_id_gpu_index(gpu_va_space->gpu->id)] = NULL; gpu_va_space->state = UVM_GPU_VA_SPACE_STATE_DEAD; } @@ -1610,14 +1620,14 @@ NV_STATUS uvm_va_space_unregister_gpu_va_space(uvm_va_space_t *va_space, const N return status; } -bool uvm_va_space_peer_enabled(uvm_va_space_t *va_space, uvm_gpu_t *gpu1, uvm_gpu_t *gpu2) +bool uvm_va_space_peer_enabled(uvm_va_space_t *va_space, const uvm_gpu_t *gpu0, const uvm_gpu_t *gpu1) { size_t table_index; + UVM_ASSERT(uvm_processor_mask_test(&va_space->registered_gpus, gpu0->id)); UVM_ASSERT(uvm_processor_mask_test(&va_space->registered_gpus, gpu1->id)); - UVM_ASSERT(uvm_processor_mask_test(&va_space->registered_gpus, gpu2->id)); - table_index = uvm_gpu_peer_table_index(gpu1->id, gpu2->id); + table_index = uvm_gpu_peer_table_index(gpu0->id, gpu1->id); return !!test_bit(table_index, va_space->enabled_peers); } @@ -2073,9 +2083,16 @@ NV_STATUS uvm_service_block_context_init(void) // Pre-allocate some fault service contexts for the CPU and add them to the global list while (num_preallocated_contexts-- > 0) { uvm_service_block_context_t *service_context = uvm_kvmalloc(sizeof(*service_context)); + if (!service_context) return NV_ERR_NO_MEMORY; + service_context->block_context = uvm_va_block_context_alloc(NULL); + if (!service_context->block_context) { + uvm_kvfree(service_context); + return NV_ERR_NO_MEMORY; + } + list_add(&service_context->cpu_fault.service_context_list, &g_cpu_service_block_context_list); } @@ -2089,6 +2106,7 @@ void uvm_service_block_context_exit(void) // Free fault service contexts for the CPU and add clear the global list list_for_each_entry_safe(service_context, service_context_tmp, &g_cpu_service_block_context_list, cpu_fault.service_context_list) { + uvm_va_block_context_free(service_context->block_context); uvm_kvfree(service_context); } INIT_LIST_HEAD(&g_cpu_service_block_context_list); @@ -2110,8 +2128,17 @@ static uvm_service_block_context_t *service_block_context_cpu_alloc(void) uvm_spin_unlock(&g_cpu_service_block_context_list_lock); - if (!service_context) + if (!service_context) { service_context = uvm_kvmalloc(sizeof(*service_context)); + service_context->block_context = uvm_va_block_context_alloc(NULL); + if (!service_context->block_context) { + uvm_kvfree(service_context); + service_context = NULL; + } + } + else { + uvm_va_block_context_init(service_context->block_context, NULL); + } return service_context; } @@ -2137,6 +2164,7 @@ static vm_fault_t uvm_va_space_cpu_fault(uvm_va_space_t *va_space, NV_STATUS status = uvm_global_get_status(); bool tools_enabled; bool major_fault = false; + bool is_remote_mm = false; uvm_service_block_context_t *service_context; uvm_global_processor_mask_t gpus_to_check_for_ecc; @@ -2177,7 +2205,7 @@ static vm_fault_t uvm_va_space_cpu_fault(uvm_va_space_t *va_space, // mmap_lock held on the CPU fault path, so tell the fault handler to use // that one. current->mm might differ if we're on the access_process_vm // (ptrace) path or if another driver is calling get_user_pages. - service_context->block_context.mm = vma->vm_mm; + service_context->block_context->mm = vma->vm_mm; // The mmap_lock might be held in write mode, but the mode doesn't matter // for the purpose of lock ordering and we don't rely on it being in write @@ -2216,25 +2244,32 @@ static vm_fault_t uvm_va_space_cpu_fault(uvm_va_space_t *va_space, uvm_tools_record_throttling_end(va_space, fault_addr, UVM_ID_CPU); if (is_hmm) { - // Note that normally we should find a va_block for the faulting - // address because the block had to be created when migrating a - // page to the GPU and a device private PTE inserted into the CPU - // page tables in order for migrate_to_ram() to be called. Not - // finding it means the PTE was remapped to a different virtual - // address with mremap() so create a new va_block if needed. - status = uvm_hmm_va_block_find_create(va_space, - fault_addr, - &service_context->block_context.hmm.vma, - &va_block); - if (status != NV_OK) - break; - - UVM_ASSERT(service_context->block_context.hmm.vma == vma); - status = uvm_hmm_migrate_begin(va_block); - if (status != NV_OK) + if (va_space->va_space_mm.mm == vma->vm_mm) { + // Note that normally we should find a va_block for the faulting + // address because the block had to be created when migrating a + // page to the GPU and a device private PTE inserted into the CPU + // page tables in order for migrate_to_ram() to be called. Not + // finding it means the PTE was remapped to a different virtual + // address with mremap() so create a new va_block if needed. + status = uvm_hmm_va_block_find_create(va_space, + fault_addr, + &service_context->block_context->hmm.vma, + &va_block); + if (status != NV_OK) + break; + + UVM_ASSERT(service_context->block_context->hmm.vma == vma); + status = uvm_hmm_migrate_begin(va_block); + if (status != NV_OK) + break; + + service_context->cpu_fault.vmf = vmf; + } + else { + is_remote_mm = true; + status = uvm_hmm_remote_cpu_fault(vmf); break; - - service_context->cpu_fault.vmf = vmf; + } } else { status = uvm_va_block_find_create_managed(va_space, fault_addr, &va_block); @@ -2265,7 +2300,7 @@ static vm_fault_t uvm_va_space_cpu_fault(uvm_va_space_t *va_space, tools_enabled = va_space->tools.enabled; - if (status == NV_OK) { + if (status == NV_OK && !is_remote_mm) { uvm_va_space_global_gpus_in_mask(va_space, &gpus_to_check_for_ecc, &service_context->cpu_fault.gpus_to_check_for_ecc); @@ -2275,7 +2310,7 @@ static vm_fault_t uvm_va_space_cpu_fault(uvm_va_space_t *va_space, uvm_va_space_up_read(va_space); uvm_record_unlock_mmap_lock_read(vma->vm_mm); - if (status == NV_OK) { + if (status == NV_OK && !is_remote_mm) { status = uvm_global_mask_check_ecc_error(&gpus_to_check_for_ecc); uvm_global_mask_release(&gpus_to_check_for_ecc); } diff --git a/kernel-open/nvidia-uvm/uvm_va_space.h b/kernel-open/nvidia-uvm/uvm_va_space.h index 1962ada985..8099dcd1dc 100644 --- a/kernel-open/nvidia-uvm/uvm_va_space.h +++ b/kernel-open/nvidia-uvm/uvm_va_space.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -253,17 +253,6 @@ struct uvm_va_space_struct // corrupting state. uvm_processor_mask_t gpu_unregister_in_progress; - // On VMA destruction, the fault buffer needs to be flushed for all the GPUs - // registered in the VA space to avoid leaving stale entries of the VA range - // that is going to be destroyed. Otherwise, these fault entries can be - // attributed to new VA ranges reallocated at the same addresses. However, - // uvm_vm_close is called with mm->mmap_lock taken and we cannot take the - // ISR lock. Therefore, we use a flag to notify the GPU fault handler that - // the fault buffer needs to be flushed, before servicing the faults that - // belong to the va_space. The bits are set and cleared atomically so no - // va_space lock is required. - uvm_processor_mask_t needs_fault_buffer_flush; - // Mask of processors that are participating in system-wide atomics uvm_processor_mask_t system_wide_atomics_enabled_processors; @@ -335,7 +324,7 @@ struct uvm_va_space_struct // Block context used for GPU unmap operations so that allocation is not // required on the teardown path. This can only be used while the VA space // lock is held in write mode. Access using uvm_va_space_block_context(). - uvm_va_block_context_t va_block_context; + uvm_va_block_context_t *va_block_context; NvU64 initialization_flags; @@ -541,7 +530,7 @@ void uvm_va_space_detach_all_user_channels(uvm_va_space_t *va_space, struct list // Returns whether peer access between these two GPUs has been enabled in this // VA space. Both GPUs must be registered in the VA space. -bool uvm_va_space_peer_enabled(uvm_va_space_t *va_space, uvm_gpu_t *gpu1, uvm_gpu_t *gpu2); +bool uvm_va_space_peer_enabled(uvm_va_space_t *va_space, const uvm_gpu_t *gpu0, const uvm_gpu_t *gpu1); // Returns the va_space this file points to. Returns NULL if this file // does not point to a va_space. @@ -575,8 +564,8 @@ static uvm_va_block_context_t *uvm_va_space_block_context(uvm_va_space_t *va_spa if (mm) uvm_assert_mmap_lock_locked(mm); - uvm_va_block_context_init(&va_space->va_block_context, mm); - return &va_space->va_block_context; + uvm_va_block_context_init(va_space->va_block_context, mm); + return va_space->va_block_context; } // Retains the GPU VA space memory object. destroy_gpu_va_space and diff --git a/kernel-open/nvidia-uvm/uvm_va_space_mm.c b/kernel-open/nvidia-uvm/uvm_va_space_mm.c index 19b5705000..9e814577a4 100644 --- a/kernel-open/nvidia-uvm/uvm_va_space_mm.c +++ b/kernel-open/nvidia-uvm/uvm_va_space_mm.c @@ -215,7 +215,13 @@ bool uvm_va_space_mm_enabled(uvm_va_space_t *va_space) static struct mmu_notifier_ops uvm_mmu_notifier_ops_ats = { +#if defined(NV_MMU_NOTIFIER_OPS_HAS_INVALIDATE_RANGE) .invalidate_range = uvm_mmu_notifier_invalidate_range_ats, +#elif defined(NV_MMU_NOTIFIER_OPS_HAS_ARCH_INVALIDATE_SECONDARY_TLBS) + .arch_invalidate_secondary_tlbs = uvm_mmu_notifier_invalidate_range_ats, +#else + #error One of invalidate_range/arch_invalid_secondary must be present +#endif }; static int uvm_mmu_notifier_register(uvm_va_space_mm_t *va_space_mm) @@ -310,17 +316,6 @@ void uvm_va_space_mm_unregister(uvm_va_space_t *va_space) if (!va_space_mm->mm) return; - // At this point the mm is still valid because uvm_mm_release() - // hasn't yet called mmput(). uvm_hmm_va_space_destroy() will kill - // all the va_blocks along with any associated gpu_chunks, so we - // need to make sure these chunks are free. However freeing them - // requires a valid mm so we can call migrate_vma_setup(), so we - // do that here. - // TODO: Bug 3902536: [UVM-HMM] add code to migrate GPU memory - // without having a va_block - if (uvm_hmm_is_enabled(va_space)) - uvm_hmm_evict_va_blocks(va_space); - if (uvm_va_space_mm_enabled(va_space)) { if (UVM_ATS_IBM_SUPPORTED_IN_DRIVER() && g_uvm_global.ats.enabled) uvm_mmu_notifier_unregister(va_space_mm); diff --git a/kernel-open/nvidia-uvm/uvm_volta_mmu.c b/kernel-open/nvidia-uvm/uvm_volta_mmu.c index 7bb163facb..e064360021 100644 --- a/kernel-open/nvidia-uvm/uvm_volta_mmu.c +++ b/kernel-open/nvidia-uvm/uvm_volta_mmu.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2017-2023 NVIDIA Corporation + Copyright (c) 2017-2021 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -145,10 +145,7 @@ static NvU64 small_half_pde_volta(uvm_mmu_page_table_alloc_t *phys_alloc) return pde_bits; } -static void make_pde_volta(void *entry, - uvm_mmu_page_table_alloc_t **phys_allocs, - NvU32 depth, - uvm_page_directory_t *child_dir) +static void make_pde_volta(void *entry, uvm_mmu_page_table_alloc_t **phys_allocs, NvU32 depth) { NvU32 entry_count = entries_per_index_volta(depth); NvU64 *entry_bits = (NvU64 *)entry; diff --git a/kernel-open/nvidia/export_nvswitch.h b/kernel-open/nvidia/export_nvswitch.h index 40b4b3c4bf..f0e10fd8fb 100644 --- a/kernel-open/nvidia/export_nvswitch.h +++ b/kernel-open/nvidia/export_nvswitch.h @@ -50,10 +50,11 @@ extern "C" { #define NVSWITCH_NSEC_PER_SEC 1000000000ULL #define NVSWITCH_DBG_LEVEL_MMIO 0x0 -#define NVSWITCH_DBG_LEVEL_INFO 0x1 -#define NVSWITCH_DBG_LEVEL_SETUP 0x2 -#define NVSWITCH_DBG_LEVEL_WARN 0x3 -#define NVSWITCH_DBG_LEVEL_ERROR 0x4 +#define NVSWITCH_DBG_LEVEL_NOISY 0x1 +#define NVSWITCH_DBG_LEVEL_INFO 0x2 +#define NVSWITCH_DBG_LEVEL_SETUP 0x3 +#define NVSWITCH_DBG_LEVEL_WARN 0x4 +#define NVSWITCH_DBG_LEVEL_ERROR 0x5 #define NVSWITCH_LOG_BUFFER_SIZE 512 @@ -337,7 +338,7 @@ nvswitch_lib_service_interrupts ); /* - * @Brief : Get depth of error logs + * @Brief : Get depth of error logs and port event log * * @Description : * @@ -345,6 +346,7 @@ nvswitch_lib_service_interrupts * * @param[out] fatal Count of fatal errors * @param[out] nonfatal Count of non-fatal errors + * @param[out] portEvent Count of port events * * @returns NVL_SUCCESS if there were no errors and interrupts were handled * -NVL_NOT_FOUND if bad arguments provided @@ -353,7 +355,7 @@ NvlStatus nvswitch_lib_get_log_count ( nvswitch_device *device, - NvU32 *fatal, NvU32 *nonfatal + NvU32 *fatal, NvU32 *nonfatal, NvU32 *portEvent ); /* diff --git a/kernel-open/nvidia/i2c_nvswitch.c b/kernel-open/nvidia/i2c_nvswitch.c index de8318a707..eecea816da 100644 --- a/kernel-open/nvidia/i2c_nvswitch.c +++ b/kernel-open/nvidia/i2c_nvswitch.c @@ -294,7 +294,7 @@ nvswitch_i2c_add_adapter NV_PCI_BUS_NUMBER(pci_dev), NV_PCI_SLOT_NUMBER(pci_dev), PCI_FUNC(pci_dev->devfn)); - if ((rc < 0) && (rc >= sizeof(adapter->name))) + if ((rc < 0) || (rc >= sizeof(adapter->name))) { goto cleanup; } diff --git a/kernel-open/nvidia/linux_nvswitch.c b/kernel-open/nvidia/linux_nvswitch.c index 5d4ca3bb00..02d5906acb 100644 --- a/kernel-open/nvidia/linux_nvswitch.c +++ b/kernel-open/nvidia/linux_nvswitch.c @@ -1865,11 +1865,10 @@ nvswitch_os_print switch (log_level) { case NVSWITCH_DBG_LEVEL_MMIO: + case NVSWITCH_DBG_LEVEL_NOISY: kern_level = KERN_DEBUG; break; case NVSWITCH_DBG_LEVEL_INFO: - kern_level = KERN_INFO; - break; case NVSWITCH_DBG_LEVEL_SETUP: kern_level = KERN_INFO; break; diff --git a/kernel-open/nvidia/nv-caps.c b/kernel-open/nvidia/nv-caps.c index 7840414b4f..50e04b0519 100644 --- a/kernel-open/nvidia/nv-caps.c +++ b/kernel-open/nvidia/nv-caps.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2019-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -490,6 +490,7 @@ static struct file_operations g_nv_cap_drv_fops; int NV_API_CALL nv_cap_validate_and_dup_fd(const nv_cap_t *cap, int fd) { +#if NV_FILESYSTEM_ACCESS_AVAILABLE struct file *file; int dup_fd; struct inode *inode = NULL; @@ -558,10 +559,14 @@ int NV_API_CALL nv_cap_validate_and_dup_fd(const nv_cap_t *cap, int fd) err: fput(file); return -1; +#else + return -1; +#endif } void NV_API_CALL nv_cap_close_fd(int fd) { +#if NV_FILESYSTEM_ACCESS_AVAILABLE if (fd == -1) { return; @@ -599,6 +604,7 @@ void NV_API_CALL nv_cap_close_fd(int fd) #endif task_unlock(current); +#endif } static nv_cap_t* nv_cap_alloc(nv_cap_t *parent_cap, const char *name) diff --git a/kernel-open/nvidia/nv-dmabuf.c b/kernel-open/nvidia/nv-dmabuf.c index 23462567b3..f06083968d 100644 --- a/kernel-open/nvidia/nv-dmabuf.c +++ b/kernel-open/nvidia/nv-dmabuf.c @@ -107,7 +107,7 @@ nv_dma_buf_free_file_private( if (priv->handles != NULL) { - NV_KFREE(priv->handles, priv->total_objects * sizeof(priv->handles[0])); + os_free_mem(priv->handles); priv->handles = NULL; } @@ -122,6 +122,8 @@ nv_dma_buf_alloc_file_private( ) { nv_dma_buf_file_private_t *priv = NULL; + NvU64 handles_size = num_handles * sizeof(priv->handles[0]); + NV_STATUS status; NV_KZALLOC(priv, sizeof(nv_dma_buf_file_private_t)); if (priv == NULL) @@ -131,11 +133,12 @@ nv_dma_buf_alloc_file_private( mutex_init(&priv->lock); - NV_KZALLOC(priv->handles, num_handles * sizeof(priv->handles[0])); - if (priv->handles == NULL) + status = os_alloc_mem((void **) &priv->handles, handles_size); + if (status != NV_OK) { goto failed; } + os_mem_set(priv->handles, 0, handles_size); return priv; @@ -1065,6 +1068,7 @@ nv_dma_buf_create( status = rm_dma_buf_get_client_and_device(sp, priv->nv, params->hClient, + params->handles[0], &priv->h_client, &priv->h_device, &priv->h_subdevice, diff --git a/kernel-open/nvidia/nv-frontend.c b/kernel-open/nvidia/nv-frontend.c deleted file mode 100644 index f5b871e6cc..0000000000 --- a/kernel-open/nvidia/nv-frontend.c +++ /dev/null @@ -1,395 +0,0 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2012-2013 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "os-interface.h" -#include "nv-linux.h" -#include "nv-reg.h" -#include "nv-frontend.h" - -MODULE_LICENSE("Dual MIT/GPL"); - -MODULE_INFO(supported, "external"); -MODULE_VERSION(NV_VERSION_STRING); -MODULE_ALIAS_CHARDEV_MAJOR(NV_MAJOR_DEVICE_NUMBER); - -/* - * MODULE_IMPORT_NS() is added by commit id 8651ec01daeda - * ("module: add support for symbol namespaces") in 5.4 - */ -#if defined(MODULE_IMPORT_NS) - -/* - * DMA_BUF namespace is added by commit id 16b0314aa746 - * ("dma-buf: move dma-buf symbols into the DMA_BUF module namespace") in 5.16 - */ -MODULE_IMPORT_NS(DMA_BUF); - -#endif - -static NvU32 nv_num_instances; - -// lock required to protect table. -struct semaphore nv_module_table_lock; - -// minor number table -nvidia_module_t *nv_minor_num_table[NV_FRONTEND_CONTROL_DEVICE_MINOR_MAX + 1]; - -int nvidia_init_module(void); -void nvidia_exit_module(void); - -/* EXPORTS to Linux Kernel */ - -int nvidia_frontend_open(struct inode *, struct file *); -int nvidia_frontend_close(struct inode *, struct file *); -unsigned int nvidia_frontend_poll(struct file *, poll_table *); -int nvidia_frontend_ioctl(struct inode *, struct file *, unsigned int, unsigned long); -long nvidia_frontend_unlocked_ioctl(struct file *, unsigned int, unsigned long); -long nvidia_frontend_compat_ioctl(struct file *, unsigned int, unsigned long); -int nvidia_frontend_mmap(struct file *, struct vm_area_struct *); - -/* character driver entry points */ -static struct file_operations nv_frontend_fops = { - .owner = THIS_MODULE, - .poll = nvidia_frontend_poll, - .unlocked_ioctl = nvidia_frontend_unlocked_ioctl, -#if NVCPU_IS_X86_64 || NVCPU_IS_AARCH64 - .compat_ioctl = nvidia_frontend_compat_ioctl, -#endif - .mmap = nvidia_frontend_mmap, - .open = nvidia_frontend_open, - .release = nvidia_frontend_close, -}; - -/* Helper functions */ - -static int add_device(nvidia_module_t *module, nv_linux_state_t *device, NvBool all) -{ - NvU32 i; - int rc = -1; - - // look for free a minor number and assign unique minor number to this device - for (i = 0; i <= NV_FRONTEND_CONTROL_DEVICE_MINOR_MIN; i++) - { - if (nv_minor_num_table[i] == NULL) - { - nv_minor_num_table[i] = module; - device->minor_num = i; - if (all == NV_TRUE) - { - device = device->next; - if (device == NULL) - { - rc = 0; - break; - } - } - else - { - rc = 0; - break; - } - } - } - return rc; -} - -static int remove_device(nvidia_module_t *module, nv_linux_state_t *device) -{ - int rc = -1; - - // remove this device from minor_number table - if ((device != NULL) && (nv_minor_num_table[device->minor_num] != NULL)) - { - nv_minor_num_table[device->minor_num] = NULL; - device->minor_num = 0; - rc = 0; - } - return rc; -} - -/* Export functions */ - -int nvidia_register_module(nvidia_module_t *module) -{ - int rc = 0; - NvU32 ctrl_minor_num; - - down(&nv_module_table_lock); - if (module->instance >= NV_MAX_MODULE_INSTANCES) - { - printk("NVRM: NVIDIA module instance %d registration failed.\n", - module->instance); - rc = -EINVAL; - goto done; - } - - ctrl_minor_num = NV_FRONTEND_CONTROL_DEVICE_MINOR_MAX - module->instance; - nv_minor_num_table[ctrl_minor_num] = module; - nv_num_instances++; -done: - up(&nv_module_table_lock); - - return rc; -} -EXPORT_SYMBOL(nvidia_register_module); - -int nvidia_unregister_module(nvidia_module_t *module) -{ - int rc = 0; - NvU32 ctrl_minor_num; - - down(&nv_module_table_lock); - - ctrl_minor_num = NV_FRONTEND_CONTROL_DEVICE_MINOR_MAX - module->instance; - if (nv_minor_num_table[ctrl_minor_num] == NULL) - { - printk("NVRM: NVIDIA module for %d instance does not exist\n", - module->instance); - rc = -1; - } - else - { - nv_minor_num_table[ctrl_minor_num] = NULL; - nv_num_instances--; - } - - up(&nv_module_table_lock); - - return rc; -} -EXPORT_SYMBOL(nvidia_unregister_module); - -int nvidia_frontend_add_device(nvidia_module_t *module, nv_linux_state_t * device) -{ - int rc = -1; - NvU32 ctrl_minor_num; - - down(&nv_module_table_lock); - ctrl_minor_num = NV_FRONTEND_CONTROL_DEVICE_MINOR_MAX - module->instance; - if (nv_minor_num_table[ctrl_minor_num] == NULL) - { - printk("NVRM: NVIDIA module for %d instance does not exist\n", - module->instance); - rc = -1; - } - else - { - rc = add_device(module, device, NV_FALSE); - } - up(&nv_module_table_lock); - - return rc; -} -EXPORT_SYMBOL(nvidia_frontend_add_device); - -int nvidia_frontend_remove_device(nvidia_module_t *module, nv_linux_state_t * device) -{ - int rc = 0; - NvU32 ctrl_minor_num; - - down(&nv_module_table_lock); - ctrl_minor_num = NV_FRONTEND_CONTROL_DEVICE_MINOR_MAX - module->instance; - if (nv_minor_num_table[ctrl_minor_num] == NULL) - { - printk("NVRM: NVIDIA module for %d instance does not exist\n", - module->instance); - rc = -1; - } - else - { - rc = remove_device(module, device); - } - up(&nv_module_table_lock); - - return rc; -} -EXPORT_SYMBOL(nvidia_frontend_remove_device); - -int nvidia_frontend_open( - struct inode *inode, - struct file *file -) -{ - int rc = -ENODEV; - nvidia_module_t *module = NULL; - - NvU32 minor_num = NV_FRONTEND_MINOR_NUMBER(inode); - - down(&nv_module_table_lock); - module = nv_minor_num_table[minor_num]; - - if ((module != NULL) && (module->open != NULL)) - { - // Increment the reference count of module to ensure that module does - // not get unloaded if its corresponding device file is open, for - // example nvidiaN.ko should not get unloaded if /dev/nvidiaN is open. - if (!try_module_get(module->owner)) - { - up(&nv_module_table_lock); - return -ENODEV; - } - rc = module->open(inode, file); - if (rc < 0) - { - module_put(module->owner); - } - } - - up(&nv_module_table_lock); - return rc; -} - -int nvidia_frontend_close( - struct inode *inode, - struct file *file -) -{ - int rc = -ENODEV; - nvidia_module_t *module = NULL; - - NvU32 minor_num = NV_FRONTEND_MINOR_NUMBER(inode); - - module = nv_minor_num_table[minor_num]; - - if ((module != NULL) && (module->close != NULL)) - { - rc = module->close(inode, file); - - // Decrement the reference count of module. - module_put(module->owner); - } - - return rc; -} - -unsigned int nvidia_frontend_poll( - struct file *file, - poll_table *wait -) -{ - unsigned int mask = 0; - struct inode *inode = NV_FILE_INODE(file); - NvU32 minor_num = NV_FRONTEND_MINOR_NUMBER(inode); - nvidia_module_t *module = nv_minor_num_table[minor_num]; - - if ((module != NULL) && (module->poll != NULL)) - mask = module->poll(file, wait); - - return mask; -} - -int nvidia_frontend_ioctl( - struct inode *inode, - struct file *file, - unsigned int cmd, - unsigned long i_arg) -{ - int rc = -ENODEV; - nvidia_module_t *module = NULL; - - NvU32 minor_num = NV_FRONTEND_MINOR_NUMBER(inode); - module = nv_minor_num_table[minor_num]; - - if ((module != NULL) && (module->ioctl != NULL)) - rc = module->ioctl(inode, file, cmd, i_arg); - - return rc; -} - -long nvidia_frontend_unlocked_ioctl( - struct file *file, - unsigned int cmd, - unsigned long i_arg -) -{ - return nvidia_frontend_ioctl(NV_FILE_INODE(file), file, cmd, i_arg); -} - -long nvidia_frontend_compat_ioctl( - struct file *file, - unsigned int cmd, - unsigned long i_arg -) -{ - return nvidia_frontend_ioctl(NV_FILE_INODE(file), file, cmd, i_arg); -} - -int nvidia_frontend_mmap( - struct file *file, - struct vm_area_struct *vma -) -{ - int rc = -ENODEV; - struct inode *inode = NV_FILE_INODE(file); - NvU32 minor_num = NV_FRONTEND_MINOR_NUMBER(inode); - nvidia_module_t *module = nv_minor_num_table[minor_num]; - - if ((module != NULL) && (module->mmap != NULL)) - rc = module->mmap(file, vma); - - return rc; -} - -static int __init nvidia_frontend_init_module(void) -{ - int status = 0; - - // initialise nvidia module table; - nv_num_instances = 0; - memset(nv_minor_num_table, 0, sizeof(nv_minor_num_table)); - NV_INIT_MUTEX(&nv_module_table_lock); - - status = nvidia_init_module(); - if (status < 0) - { - return status; - } - - // register char device - status = register_chrdev(NV_MAJOR_DEVICE_NUMBER, "nvidia-frontend", &nv_frontend_fops); - if (status < 0) - { - printk("NVRM: register_chrdev() failed!\n"); - nvidia_exit_module(); - } - - return status; -} - -static void __exit nvidia_frontend_exit_module(void) -{ - /* - * If this is the last nvidia_module to be unregistered, cleanup and - * unregister char dev - */ - if (nv_num_instances == 1) - { - unregister_chrdev(NV_MAJOR_DEVICE_NUMBER, "nvidia-frontend"); - } - - nvidia_exit_module(); -} - -module_init(nvidia_frontend_init_module); -module_exit(nvidia_frontend_exit_module); - diff --git a/kernel-open/nvidia/nv-kthread-q.c b/kernel-open/nvidia/nv-kthread-q.c index 2098f27a70..c3b5570557 100644 --- a/kernel-open/nvidia/nv-kthread-q.c +++ b/kernel-open/nvidia/nv-kthread-q.c @@ -247,6 +247,11 @@ int nv_kthread_q_init_on_node(nv_kthread_q_t *q, const char *q_name, int preferr return 0; } +int nv_kthread_q_init(nv_kthread_q_t *q, const char *qname) +{ + return nv_kthread_q_init_on_node(q, qname, NV_KTHREAD_NO_NODE); +} + // Returns true (non-zero) if the item was actually scheduled, and false if the // item was already pending in a queue. static int _raw_q_schedule(nv_kthread_q_t *q, nv_kthread_q_item_t *q_item) diff --git a/kernel-open/nvidia/nv-mmap.c b/kernel-open/nvidia/nv-mmap.c index 152b22add5..e7dcb16a4b 100644 --- a/kernel-open/nvidia/nv-mmap.c +++ b/kernel-open/nvidia/nv-mmap.c @@ -648,6 +648,16 @@ int nvidia_mmap_helper( ret = nvidia_mmap_peer_io(vma, at, page_index, pages); BUG_ON(NV_VMA_PRIVATE(vma)); + + if (ret) + { + return ret; + } + + NV_PRINT_AT(NV_DBG_MEMINFO, at); + + nv_vm_flags_set(vma, VM_IO); + nv_vm_flags_set(vma, VM_DONTEXPAND | VM_DONTDUMP); } else { @@ -661,17 +671,21 @@ int nvidia_mmap_helper( NV_VMA_PRIVATE(vma) = at; ret = nvidia_mmap_sysmem(vma, at, page_index, pages); - } - if (ret) - { - return ret; - } + if (ret) + { + return ret; + } - NV_PRINT_AT(NV_DBG_MEMINFO, at); + NV_PRINT_AT(NV_DBG_MEMINFO, at); - nv_vm_flags_set(vma, VM_IO | VM_LOCKED | VM_RESERVED); - nv_vm_flags_set(vma, VM_DONTEXPAND | VM_DONTDUMP); + // + // VM_MIXEDMAP will be set by vm_insert_page() in nvidia_mmap_sysmem(). + // VM_SHARED is added to avoid any undesired copy-on-write effects. + // + nv_vm_flags_set(vma, VM_SHARED); + nv_vm_flags_set(vma, VM_DONTEXPAND | VM_DONTDUMP); + } } if ((prot & NV_PROTECT_WRITEABLE) == 0) @@ -706,11 +720,16 @@ int nvidia_mmap( return -EINVAL; } - sp = nv_nvlfp_get_sp(nvlfp, NV_FOPS_STACK_INDEX_MMAP); + status = nv_kmem_cache_alloc_stack(&sp); + if (status != 0) + { + nv_printf(NV_DBG_ERRORS, "NVRM: Unable to allocate altstack for mmap\n"); + return status; + } status = nvidia_mmap_helper(nv, nvlfp, sp, vma, NULL); - nv_nvlfp_put_sp(nvlfp, NV_FOPS_STACK_INDEX_MMAP); + nv_kmem_cache_free_stack(sp); return status; } diff --git a/kernel-open/nvidia/nv-p2p.c b/kernel-open/nvidia/nv-p2p.c index e6fa5c5e87..bf497c7e1a 100644 --- a/kernel-open/nvidia/nv-p2p.c +++ b/kernel-open/nvidia/nv-p2p.c @@ -640,7 +640,6 @@ int nvidia_p2p_put_pages( status = nv_p2p_put_pages(NV_P2P_PAGE_TABLE_TYPE_NON_PERSISTENT, sp, p2p_token, va_space, virtual_address, &page_table); - nv_kmem_cache_free_stack(sp); return nvidia_p2p_map_status(status); diff --git a/kernel-open/nvidia/nv-pci.c b/kernel-open/nvidia/nv-pci.c index 79c9fc7dd9..f7bec54731 100644 --- a/kernel-open/nvidia/nv-pci.c +++ b/kernel-open/nvidia/nv-pci.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2019-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -25,7 +25,6 @@ #include "nv-pci-types.h" #include "nv-pci.h" #include "nv-ibmnpu.h" -#include "nv-frontend.h" #include "nv-msi.h" #include "nv-hypervisor.h" @@ -80,19 +79,15 @@ static NvBool nv_treat_missing_irq_as_error(void) #endif } -static void nv_init_dynamic_power_management +static void nv_get_pci_sysfs_config ( - nvidia_stack_t *sp, - struct pci_dev *pci_dev + struct pci_dev *pci_dev, + nv_linux_state_t *nvl ) { - nv_linux_state_t *nvl = pci_get_drvdata(pci_dev); - nv_state_t *nv = NV_STATE_PTR(nvl); +#if NV_FILESYSTEM_ACCESS_AVAILABLE char filename[50]; int ret; - NvBool pr3_acpi_method_present = NV_FALSE; - - nvl->sysfs_config_file = NULL; ret = snprintf(filename, sizeof(filename), "/sys/bus/pci/devices/%04x:%02x:%02x.0/config", @@ -143,6 +138,22 @@ static void nv_init_dynamic_power_management #endif } } +#endif +} + +static void nv_init_dynamic_power_management +( + nvidia_stack_t *sp, + struct pci_dev *pci_dev +) +{ + nv_linux_state_t *nvl = pci_get_drvdata(pci_dev); + nv_state_t *nv = NV_STATE_PTR(nvl); + NvBool pr3_acpi_method_present = NV_FALSE; + + nvl->sysfs_config_file = NULL; + + nv_get_pci_sysfs_config(pci_dev, nvl); if (nv_get_hypervisor_type() != OS_HYPERVISOR_UNKNOWN) { @@ -287,12 +298,29 @@ nv_init_coherent_link_info if (!NVCPU_IS_AARCH64) return; - if (device_property_read_u64(nvl->dev, "nvidia,gpu-mem-base-pa", &pa) != 0) - goto failed; if (device_property_read_u64(nvl->dev, "nvidia,gpu-mem-pxm-start", &pxm_start) != 0) goto failed; if (device_property_read_u64(nvl->dev, "nvidia,gpu-mem-pxm-count", &pxm_count) != 0) goto failed; + if (device_property_read_u64(nvl->dev, "nvidia,gpu-mem-base-pa", &pa) != 0) + { + /* + * This implies that the DSD key for PXM start and count is present + * while the one for Physical Address (PA) is absent. + */ + if (nv_get_hypervisor_type() == OS_HYPERVISOR_UNKNOWN) + { + /* Fail for the baremetal case */ + goto failed; + } + + /* + * For the virtualization usecase on SHH, the coherent GPU memory + * PA is exposed as BAR1 to the VM and the nvidia,gpu-mem-base-pa + * is not present. Set the GPU memory PA to the BAR1 start address. + */ + pa = nv->fb->cpu_address; + } NV_DEV_PRINTF(NV_DBG_INFO, nv, "DSD properties: \n"); NV_DEV_PRINTF(NV_DBG_INFO, nv, "\tGPU memory PA: 0x%lx \n", pa); @@ -310,7 +338,7 @@ nv_init_coherent_link_info } } - if (NVreg_EnableUserNUMAManagement) + if (NVreg_EnableUserNUMAManagement && !os_is_vgx_hyper()) { NV_ATOMIC_SET(nvl->numa_info.status, NV_IOCTL_NUMA_STATUS_OFFLINE); nvl->numa_info.use_auto_online = NV_TRUE; @@ -689,13 +717,14 @@ nv_pci_probe */ LOCK_NV_LINUX_DEVICES(); - nv_linux_add_device_locked(nvl); + if (nv_linux_add_device_locked(nvl) != 0) + { + UNLOCK_NV_LINUX_DEVICES(); + goto err_zero_dev; + } UNLOCK_NV_LINUX_DEVICES(); - if (nvidia_frontend_add_device((void *)&nv_fops, nvl) != 0) - goto err_remove_device; - pm_vt_switch_required(nvl->dev, NV_TRUE); nv_init_dynamic_power_management(sp, pci_dev); @@ -711,7 +740,6 @@ nv_pci_probe if (nvidia_vgpu_vfio_probe(nvl->pci_dev) != NV_OK) { NV_DEV_PRINTF(NV_DBG_ERRORS, nv, "Failed to register device to vGPU VFIO module"); - nvidia_frontend_remove_device((void *)&nv_fops, nvl); goto err_vgpu_kvm; } #endif @@ -741,7 +769,6 @@ nv_pci_probe nv_procfs_remove_gpu(nvl); rm_cleanup_dynamic_power_management(sp, nv); pm_vt_switch_unregister(nvl->dev); -err_remove_device: LOCK_NV_LINUX_DEVICES(); nv_linux_remove_device_locked(nvl); UNLOCK_NV_LINUX_DEVICES(); @@ -874,12 +901,6 @@ nv_pci_remove(struct pci_dev *pci_dev) nvidia_vgpu_vfio_remove(pci_dev, NV_TRUE); #endif - /* Update the frontend data structures */ - if (NV_ATOMIC_READ(nvl->usage_count) == 0) - { - nvidia_frontend_remove_device((void *)&nv_fops, nvl); - } - if ((nv->flags & NV_FLAG_PERSISTENT_SW_STATE) || (nv->flags & NV_FLAG_OPEN)) { nv_acpi_unregister_notifier(nvl); diff --git a/kernel-open/nvidia/nv-procfs.c b/kernel-open/nvidia/nv-procfs.c index d4d2007602..63a0fe597f 100644 --- a/kernel-open/nvidia/nv-procfs.c +++ b/kernel-open/nvidia/nv-procfs.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -977,13 +977,9 @@ numa_is_change_allowed(nv_numa_status_t current_state, nv_numa_status_t requeste static NV_STATUS numa_status_read( - nv_state_t *nv, - nv_stack_t *sp, - NvS32 *nid, - NvS32 *status, - NvU64 *numa_mem_addr, - NvU64 *numa_mem_size, - nv_offline_addresses_t *list + nv_state_t *nv, + nv_stack_t *sp, + nv_ioctl_numa_info_t *numa_info ) { NV_STATUS rm_status; @@ -1000,24 +996,17 @@ numa_status_read( { if (nv_platform_supports_numa(nvl)) { - *nid = nvl->numa_info.node_id; - *status = nv_get_numa_status(nvl); - *numa_mem_addr = 0; - *numa_mem_size = 0; - memset(list, 0x0, sizeof(*list)); + memset(numa_info, 0x0, sizeof(*numa_info)); + numa_info->nid = nvl->numa_info.node_id; + numa_info->status = nv_get_numa_status(nvl); } rm_status = NV_ERR_NOT_READY; goto done; } - list->numEntries = ARRAY_SIZE(list->addresses); - - rm_status = rm_get_gpu_numa_info(sp, nv, - nid, numa_mem_addr, numa_mem_size, - list->addresses, &list->numEntries); - - if (rm_status == NV_OK && *nid == NUMA_NO_NODE) + rm_status = rm_get_gpu_numa_info(sp, nv, numa_info); + if (rm_status == NV_OK && numa_info->nid == NUMA_NO_NODE) { // // RM returns NUMA_NO_NODE when running MIG instances because @@ -1033,7 +1022,7 @@ numa_status_read( // rm_status = NV_ERR_NOT_SUPPORTED; } - *status = nv_get_numa_status(nvl); + numa_info->status = nv_get_numa_status(nvl); done: up(&nvl->ldata_lock); @@ -1049,18 +1038,15 @@ nv_procfs_read_offline_pages( NvU32 i; int retval = 0; NV_STATUS rm_status; - nv_ioctl_numa_info_t numa_info; + nv_ioctl_numa_info_t numa_info = { 0 }; nv_procfs_private_t *nvpp = s->private; nv_stack_t *sp = nvpp->sp; nv_state_t *nv = nvpp->nv; - rm_status = numa_status_read(nv, sp, - &numa_info.nid, - &numa_info.status, - &numa_info.numa_mem_addr, - &numa_info.numa_mem_size, - &numa_info.offline_addresses); + numa_info.offline_addresses.numEntries = + ARRAY_SIZE(numa_info.offline_addresses.addresses); + rm_status = numa_status_read(nv, sp, &numa_info); if (rm_status != NV_OK) return -EIO; @@ -1131,18 +1117,17 @@ nv_procfs_read_numa_status( { int retval = 0; NV_STATUS rm_status; - nv_ioctl_numa_info_t numa_info; + nv_ioctl_numa_info_t numa_info = { 0 }; nv_procfs_private_t *nvpp = s->private; nv_stack_t *sp = nvpp->sp; nv_state_t *nv = nvpp->nv; - rm_status = numa_status_read(nv, sp, - &numa_info.nid, - &numa_info.status, - &numa_info.numa_mem_addr, - &numa_info.numa_mem_size, - &numa_info.offline_addresses); - + /* + * Note: we leave numa_info.offline_addresses.numEntries as 0, so that + * the numa_status_read() callchain doesn't perform expensive page + * querying that we don't need here. + */ + rm_status = numa_status_read(nv, sp, &numa_info); if ((rm_status != NV_OK) && (rm_status != NV_ERR_NOT_READY)) return -EIO; diff --git a/kernel-open/nvidia/nv-reg.h b/kernel-open/nvidia/nv-reg.h index c8ea2ced09..d552477293 100644 --- a/kernel-open/nvidia/nv-reg.h +++ b/kernel-open/nvidia/nv-reg.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2006-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2006-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -771,16 +771,11 @@ /* * Option: OpenRmEnableUnsupportedGpus * - * Open nvidia.ko support for features beyond what is used on Data Center GPUs - * is still fairly immature, so for now require users to opt into use of open - * nvidia.ko with a special registry key, if not on a Data Center GPU. + * This option to require opt in for use of Open RM on non-Data Center + * GPUs is deprecated and no longer required. The kernel module parameter + * is left here, though ignored, for backwards compatibility. */ - #define __NV_OPENRM_ENABLE_UNSUPPORTED_GPUS OpenRmEnableUnsupportedGpus -#define NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS NV_REG_STRING(__NV_OPENRM_ENABLE_UNSUPPORTED_GPUS) -#define NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS_DISABLE 0x00000000 -#define NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS_ENABLE 0x00000001 -#define NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS_DEFAULT NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS_DISABLE /* * Option: NVreg_DmaRemapPeerMmio @@ -853,7 +848,7 @@ NV_DEFINE_REG_ENTRY(__NV_DYNAMIC_POWER_MANAGEMENT, 3); NV_DEFINE_REG_ENTRY(__NV_DYNAMIC_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD, 200); NV_DEFINE_REG_ENTRY(__NV_ENABLE_GPU_FIRMWARE, NV_REG_ENABLE_GPU_FIRMWARE_DEFAULT_VALUE); NV_DEFINE_REG_ENTRY(__NV_ENABLE_GPU_FIRMWARE_LOGS, NV_REG_ENABLE_GPU_FIRMWARE_LOGS_ENABLE_ON_DEBUG); -NV_DEFINE_REG_ENTRY(__NV_OPENRM_ENABLE_UNSUPPORTED_GPUS, NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS_DEFAULT); +NV_DEFINE_REG_ENTRY(__NV_OPENRM_ENABLE_UNSUPPORTED_GPUS, 1); NV_DEFINE_REG_ENTRY_GLOBAL(__NV_ENABLE_USER_NUMA_MANAGEMENT, 1); NV_DEFINE_REG_ENTRY_GLOBAL(__NV_MEMORY_POOL_SIZE, 0); diff --git a/kernel-open/nvidia/nv-usermap.c b/kernel-open/nvidia/nv-usermap.c index 47361f7318..0cc927a6c1 100644 --- a/kernel-open/nvidia/nv-usermap.c +++ b/kernel-open/nvidia/nv-usermap.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -25,7 +25,6 @@ #include "os-interface.h" #include "nv-linux.h" -#include "nv-frontend.h" NV_STATUS NV_API_CALL nv_add_mapping_context_to_file( nv_state_t *nv, diff --git a/kernel-open/nvidia/nv-vm.c b/kernel-open/nvidia/nv-vm.c index d183b7c5cb..1c7c15ce7f 100644 --- a/kernel-open/nvidia/nv-vm.c +++ b/kernel-open/nvidia/nv-vm.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -514,28 +514,37 @@ NV_STATUS nv_alloc_system_pages( struct device *dev = at->dev; dma_addr_t bus_addr; + // Order should be zero except for EGM allocations. + unsigned int alloc_page_size = PAGE_SIZE << at->order; + unsigned int alloc_page_shift = BIT_IDX_32(alloc_page_size); + unsigned int alloc_num_pages = NV_CEIL(at->num_pages * PAGE_SIZE, alloc_page_size); + + unsigned int sub_page_idx; + unsigned int sub_page_offset; + unsigned int os_pages_in_page = alloc_page_size / PAGE_SIZE; + nv_printf(NV_DBG_MEMINFO, - "NVRM: VM: %u: %u pages\n", __FUNCTION__, at->num_pages); + "NVRM: VM: %u: %u order0 pages, %u order\n", __FUNCTION__, at->num_pages, at->order); gfp_mask = nv_compute_gfp_mask(nv, at); - for (i = 0; i < at->num_pages; i++) + for (i = 0; i < alloc_num_pages; i++) { if (at->flags.unencrypted && (dev != NULL)) { virt_addr = (unsigned long)dma_alloc_coherent(dev, - PAGE_SIZE, + alloc_page_size, &bus_addr, gfp_mask); at->flags.coherent = NV_TRUE; } else if (at->flags.node) { - NV_ALLOC_PAGES_NODE(virt_addr, at->node_id, 0, gfp_mask); + NV_ALLOC_PAGES_NODE(virt_addr, at->node_id, at->order, gfp_mask); } else { - NV_GET_FREE_PAGES(virt_addr, 0, gfp_mask); + NV_GET_FREE_PAGES(virt_addr, at->order, gfp_mask); } if (virt_addr == 0) @@ -547,49 +556,55 @@ NV_STATUS nv_alloc_system_pages( } #if !defined(__GFP_ZERO) if (at->flags.zeroed) - memset((void *)virt_addr, 0, PAGE_SIZE); + memset((void *)virt_addr, 0, alloc_page_size); #endif - phys_addr = nv_get_kern_phys_address(virt_addr); - if (phys_addr == 0) + sub_page_offset = 0; + for (sub_page_idx = 0; sub_page_idx < os_pages_in_page; sub_page_idx++) { - nv_printf(NV_DBG_ERRORS, - "NVRM: VM: %s: failed to look up physical address\n", - __FUNCTION__); - NV_FREE_PAGES(virt_addr, 0); - status = NV_ERR_OPERATING_SYSTEM; - goto failed; - } + unsigned long sub_page_virt_addr = virt_addr + sub_page_offset; + phys_addr = nv_get_kern_phys_address(sub_page_virt_addr); + if (phys_addr == 0) + { + nv_printf(NV_DBG_ERRORS, + "NVRM: VM: %s: failed to look up physical address\n", + __FUNCTION__); + NV_FREE_PAGES(sub_page_virt_addr, at->order); + status = NV_ERR_OPERATING_SYSTEM; + goto failed; + } #if defined(_PAGE_NX) - if (((_PAGE_NX & pgprot_val(PAGE_KERNEL)) != 0) && - (phys_addr < 0x400000)) - { - nv_printf(NV_DBG_SETUP, - "NVRM: VM: %s: discarding page @ 0x%llx\n", - __FUNCTION__, phys_addr); - --i; - continue; - } + if (((_PAGE_NX & pgprot_val(PAGE_KERNEL)) != 0) && + (phys_addr < 0x400000)) + { + nv_printf(NV_DBG_SETUP, + "NVRM: VM: %s: discarding page @ 0x%llx\n", + __FUNCTION__, phys_addr); + --i; + continue; + } #endif - page_ptr = at->page_table[i]; - page_ptr->phys_addr = phys_addr; - page_ptr->page_count = NV_GET_PAGE_COUNT(page_ptr); - page_ptr->virt_addr = virt_addr; + page_ptr = at->page_table[(i * os_pages_in_page) + sub_page_idx]; + page_ptr->phys_addr = phys_addr; + page_ptr->page_count = NV_GET_PAGE_COUNT(page_ptr); + page_ptr->virt_addr = sub_page_virt_addr; - // - // Use unencrypted dma_addr returned by dma_alloc_coherent() as - // nv_phys_to_dma() returns encrypted dma_addr when AMD SEV is enabled. - // - if (at->flags.coherent) - page_ptr->dma_addr = bus_addr; - else if (dev) - page_ptr->dma_addr = nv_phys_to_dma(dev, page_ptr->phys_addr); - else - page_ptr->dma_addr = page_ptr->phys_addr; + // + // Use unencrypted dma_addr returned by dma_alloc_coherent() as + // nv_phys_to_dma() returns encrypted dma_addr when AMD SEV is enabled. + // + if (at->flags.coherent) + page_ptr->dma_addr = bus_addr; + else if (dev != NULL) + page_ptr->dma_addr = nv_phys_to_dma(dev, page_ptr->phys_addr); + else + page_ptr->dma_addr = page_ptr->phys_addr; - NV_MAYBE_RESERVE_PAGE(page_ptr); + NV_MAYBE_RESERVE_PAGE(page_ptr); + sub_page_offset += PAGE_SIZE; + } } if (at->cache_type != NV_MEMORY_CACHED) @@ -602,16 +617,16 @@ NV_STATUS nv_alloc_system_pages( { for (j = 0; j < i; j++) { - page_ptr = at->page_table[j]; + page_ptr = at->page_table[j * os_pages_in_page]; NV_MAYBE_UNRESERVE_PAGE(page_ptr); if (at->flags.coherent) { - dma_free_coherent(dev, PAGE_SIZE, (void *)page_ptr->virt_addr, + dma_free_coherent(dev, alloc_page_size, (void *)page_ptr->virt_addr, page_ptr->dma_addr); } else { - NV_FREE_PAGES(page_ptr->virt_addr, 0); + NV_FREE_PAGES(page_ptr->virt_addr, at->order); } } } @@ -627,6 +642,12 @@ void nv_free_system_pages( unsigned int i; struct device *dev = at->dev; + // Order should be zero except for EGM allocations. + unsigned int alloc_page_size = PAGE_SIZE << at->order; + unsigned int alloc_page_shift = BIT_IDX_32(alloc_page_size); + unsigned int alloc_num_pages = NV_CEIL(at->num_pages * PAGE_SIZE, alloc_page_size); + unsigned int os_pages_in_page = alloc_page_size / PAGE_SIZE; + nv_printf(NV_DBG_MEMINFO, "NVRM: VM: %s: %u pages\n", __FUNCTION__, at->num_pages); @@ -650,14 +671,20 @@ void nv_free_system_pages( } NV_MAYBE_UNRESERVE_PAGE(page_ptr); + } + + for (i = 0; i < at->num_pages; i += os_pages_in_page) + { + page_ptr = at->page_table[i]; + if (at->flags.coherent) { - dma_free_coherent(dev, PAGE_SIZE, (void *)page_ptr->virt_addr, + dma_free_coherent(dev, alloc_page_size, (void *)page_ptr->virt_addr, page_ptr->dma_addr); } else { - NV_FREE_PAGES(page_ptr->virt_addr, 0); + NV_FREE_PAGES(page_ptr->virt_addr, at->order); } } } diff --git a/kernel-open/nvidia/nv.c b/kernel-open/nvidia/nv.c index 38464875a1..6aa36099d4 100644 --- a/kernel-open/nvidia/nv.c +++ b/kernel-open/nvidia/nv.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -36,6 +36,8 @@ #include "nv-reg.h" #include "nv-msi.h" #include "nv-pci-table.h" +#include "nv-chardev-numbers.h" +#include "nv-register-module.h" // TODO remove once NVKMS migrates #if defined(NV_UVM_ENABLE) #include "nv_uvm_interface.h" @@ -48,7 +50,6 @@ #include "nvlink_proto.h" #include "nvlink_caps.h" -#include "nv-frontend.h" #include "nv-hypervisor.h" #include "nv-ibmnpu.h" #include "nv-rsync.h" @@ -61,6 +62,7 @@ #endif #include +#include #include /* HDA struct snd_card */ @@ -102,6 +104,24 @@ #define RM_THRESHOLD_UNAHNDLED_IRQ_COUNT 99900 #define RM_UNHANDLED_TIMEOUT_US 100000 +MODULE_LICENSE("Dual MIT/GPL"); + +MODULE_INFO(supported, "external"); +MODULE_VERSION(NV_VERSION_STRING); +MODULE_ALIAS_CHARDEV_MAJOR(NV_MAJOR_DEVICE_NUMBER); + +/* + * MODULE_IMPORT_NS() is added by commit id 8651ec01daeda + * ("module: add support for symbol namespaces") in 5.4 + */ +#if defined(MODULE_IMPORT_NS) +/* + * DMA_BUF namespace is added by commit id 16b0314aa746 + * ("dma-buf: move dma-buf symbols into the DMA_BUF module namespace") in 5.16 + */ +MODULE_IMPORT_NS(DMA_BUF); +#endif // defined(MODULE_IMPORT_NS) + const NvBool nv_is_rm_firmware_supported_os = NV_TRUE; // Deprecated, use NV_REG_ENABLE_GPU_FIRMWARE instead @@ -114,17 +134,32 @@ NV_MODULE_STRING_PARAMETER(rm_firmware_active); nv_cap_t *nvidia_caps_root = NULL; /* - * our global state; one per device + * Global counts for tracking if all devices were initialized properly */ NvU32 num_nv_devices = 0; NvU32 num_probed_nv_devices = 0; -nv_linux_state_t *nv_linux_devices; - /* - * And one for the control device + * Global list and table of per-device state + * note: both nv_linux_devices and nv_linux_minor_num_table + * are protected by nv_linux_devices_lock */ +nv_linux_state_t *nv_linux_devices; +static nv_linux_state_t *nv_linux_minor_num_table[NV_MINOR_DEVICE_NUMBER_REGULAR_MAX + 1]; + +// Global state for the control device nv_linux_state_t nv_ctl_device = { { 0 } }; + +// cdev covering the region of regular (non-control) devices +static struct cdev nv_linux_devices_cdev; + +// cdev covering the control device +static struct cdev nv_linux_control_device_cdev; + +// lock for nvidia_register_module "extmod" emulation +// TODO remove once NVKMS migrates +static struct semaphore nv_extmod_lock; + extern NvU32 nv_dma_remap_peer_mmio; nv_kthread_q_t nv_kthread_q; @@ -199,17 +234,19 @@ static int nvidia_open (struct inode *, struct file *); static int nvidia_close (struct inode *, struct file *); static unsigned int nvidia_poll (struct file *, poll_table *); static int nvidia_ioctl (struct inode *, struct file *, unsigned int, unsigned long); +static long nvidia_unlocked_ioctl (struct file *, unsigned int, unsigned long); /* character device entry points*/ -nvidia_module_t nv_fops = { - .owner = THIS_MODULE, - .module_name = MODULE_NAME, - .instance = MODULE_INSTANCE_NUMBER, - .open = nvidia_open, - .close = nvidia_close, - .ioctl = nvidia_ioctl, - .mmap = nvidia_mmap, - .poll = nvidia_poll, +static struct file_operations nvidia_fops = { + .owner = THIS_MODULE, + .poll = nvidia_poll, + .unlocked_ioctl = nvidia_unlocked_ioctl, +#if NVCPU_IS_X86_64 || NVCPU_IS_AARCH64 + .compat_ioctl = nvidia_unlocked_ioctl, +#endif + .mmap = nvidia_mmap, + .open = nvidia_open, + .release = nvidia_close, }; #if defined(CONFIG_PM) @@ -512,6 +549,7 @@ nv_module_state_init(nv_stack_t *sp) } nv_linux_devices = NULL; + memset(nv_linux_minor_num_table, 0, sizeof(nv_linux_minor_num_table)); NV_INIT_MUTEX(&nv_linux_devices_lock); init_rwsem(&nv_system_pm_lock); @@ -590,8 +628,6 @@ static void nv_drivers_exit(void) { nv_pci_unregister_driver(); - - nvidia_unregister_module(&nv_fops); } static int __init @@ -599,14 +635,6 @@ nv_drivers_init(void) { int rc; - rc = nvidia_register_module(&nv_fops); - if (rc < 0) - { - nv_printf(NV_DBG_ERRORS, - "NVRM: failed to register character device.\n"); - return rc; - } - rc = nv_pci_register_driver(); if (rc < 0) { @@ -616,11 +644,6 @@ nv_drivers_init(void) } exit: - if (rc < 0) - { - nvidia_unregister_module(&nv_fops); - } - return rc; } @@ -644,6 +667,8 @@ nv_module_init(nv_stack_t **sp) { int rc; + NV_INIT_MUTEX(&nv_extmod_lock); // TODO remove once NVKMS migrates + rc = nv_module_resources_init(sp); if (rc < 0) { @@ -745,7 +770,48 @@ static void nv_caps_root_exit(void) nvidia_caps_root = NULL; } -int __init nvidia_init_module(void) +static int nv_register_chrdev( + unsigned int minor, + unsigned int count, + struct cdev *cdev, + const char *name, + struct file_operations *fops +) +{ + int rc; + + rc = register_chrdev_region(MKDEV(NV_MAJOR_DEVICE_NUMBER, minor), + count, name); + if (rc < 0) + { + nv_printf(NV_DBG_ERRORS, + "NVRM: register_chrdev_region() failed for %s!\n", name); + return rc; + } + + cdev_init(cdev, fops); + rc = cdev_add(cdev, MKDEV(NV_MAJOR_DEVICE_NUMBER, minor), count); + if (rc < 0) + { + nv_printf(NV_DBG_ERRORS, "NVRM: cdev_add() failed for %s!\n", name); + unregister_chrdev_region(MKDEV(NV_MAJOR_DEVICE_NUMBER, minor), count); + return rc; + } + + return rc; +} + +static void nv_unregister_chrdev( + unsigned int minor, + unsigned int count, + struct cdev *cdev +) +{ + cdev_del(cdev); + unregister_chrdev_region(MKDEV(NV_MAJOR_DEVICE_NUMBER, minor), count); +} + +static int __init nvidia_init_module(void) { int rc; NvU32 count; @@ -846,10 +912,39 @@ int __init nvidia_init_module(void) } #endif + /* + * Register char devices for both the region of regular devices + * as well as the control device. + * + * NOTE: THIS SHOULD BE DONE LAST. + */ + rc = nv_register_chrdev(0, NV_MINOR_DEVICE_NUMBER_REGULAR_MAX + 1, + &nv_linux_devices_cdev, "nvidia", &nvidia_fops); + if (rc < 0) + { + goto no_chrdev_exit; + } + + rc = nv_register_chrdev(NV_MINOR_DEVICE_NUMBER_CONTROL_DEVICE, 1, + &nv_linux_control_device_cdev, "nvidiactl", &nvidia_fops); + if (rc < 0) + { + goto partial_chrdev_exit; + } + __nv_init_sp = sp; return 0; +partial_chrdev_exit: + nv_unregister_chrdev(0, NV_MINOR_DEVICE_NUMBER_REGULAR_MAX + 1, + &nv_linux_devices_cdev); + +no_chrdev_exit: +#if defined(NV_UVM_ENABLE) + nv_uvm_exit(); +#endif + drivers_exit: nv_drivers_exit(); @@ -865,10 +960,15 @@ int __init nvidia_init_module(void) return rc; } -void nvidia_exit_module(void) +static void __exit nvidia_exit_module(void) { nvidia_stack_t *sp = __nv_init_sp; + nv_unregister_chrdev(NV_MINOR_DEVICE_NUMBER_CONTROL_DEVICE, 1, + &nv_linux_control_device_cdev); + nv_unregister_chrdev(0, NV_MINOR_DEVICE_NUMBER_REGULAR_MAX + 1, + &nv_linux_devices_cdev); + #if defined(NV_UVM_ENABLE) nv_uvm_exit(); #endif @@ -887,20 +987,11 @@ void nvidia_exit_module(void) static void *nv_alloc_file_private(void) { nv_linux_file_private_t *nvlfp; - unsigned int i; NV_KZALLOC(nvlfp, sizeof(nv_linux_file_private_t)); if (!nvlfp) return NULL; - if (rm_is_altstack_in_use()) - { - for (i = 0; i < NV_FOPS_STACK_INDEX_COUNT; ++i) - { - NV_INIT_MUTEX(&nvlfp->fops_sp_lock[i]); - } - } - init_waitqueue_head(&nvlfp->waitqueue); NV_SPIN_LOCK_INIT(&nvlfp->fp_lock); @@ -933,27 +1024,32 @@ static int nv_is_control_device( struct inode *inode ) { - return (minor((inode)->i_rdev) == NV_CONTROL_DEVICE_MINOR); + return (minor((inode)->i_rdev) == NV_MINOR_DEVICE_NUMBER_CONTROL_DEVICE); } /* - * Search the global list of nv devices for the one with the given minor device - * number. If found, nvl is returned with nvl->ldata_lock taken. + * Find the nv device with the given minor device number in the minor number + * table. If found, nvl is returned with nvl->ldata_lock taken. */ static nv_linux_state_t *find_minor(NvU32 minor) { nv_linux_state_t *nvl; + if (minor > NV_MINOR_DEVICE_NUMBER_REGULAR_MAX) + return NULL; + LOCK_NV_LINUX_DEVICES(); - nvl = nv_linux_devices; - while (nvl != NULL) + + nvl = nv_linux_minor_num_table[minor]; + if (nvl->minor_num == minor) { - if (nvl->minor_num == minor) - { - down(&nvl->ldata_lock); - break; - } - nvl = nvl->next; + down(&nvl->ldata_lock); + } + else + { + // nv_linux_minor_num_table out of sync -- this shouldn't happen + WARN_ON(1); + nvl = NULL; } UNLOCK_NV_LINUX_DEVICES(); @@ -1521,8 +1617,6 @@ nvidia_open( int rc = 0; nv_linux_file_private_t *nvlfp = NULL; nvidia_stack_t *sp = NULL; - unsigned int i; - unsigned int k; nv_printf(NV_DBG_INFO, "NVRM: nvidia_open...\n"); @@ -1540,21 +1634,6 @@ nvidia_open( return rc; } - for (i = 0; i < NV_FOPS_STACK_INDEX_COUNT; ++i) - { - rc = nv_kmem_cache_alloc_stack(&nvlfp->fops_sp[i]); - if (rc != 0) - { - nv_kmem_cache_free_stack(sp); - for (k = 0; k < i; ++k) - { - nv_kmem_cache_free_stack(nvlfp->fops_sp[k]); - } - nv_free_file_private(nvlfp); - return rc; - } - } - NV_SET_FILE_PRIVATE(file, nvlfp); nvlfp->sp = sp; @@ -1610,11 +1689,6 @@ nvidia_open( { if (nvlfp != NULL) { - nv_kmem_cache_free_stack(sp); - for (i = 0; i < NV_FOPS_STACK_INDEX_COUNT; ++i) - { - nv_kmem_cache_free_stack(nvlfp->fops_sp[i]); - } nv_free_file_private(nvlfp); NV_SET_FILE_PRIVATE(file, NULL); } @@ -1805,7 +1879,6 @@ nvidia_close_callback( nv_linux_state_t *nvl = nvlfp->nvptr; nv_state_t *nv = NV_STATE_PTR(nvl); nvidia_stack_t *sp = nvlfp->sp; - unsigned int i; NvBool bRemove = NV_FALSE; rm_cleanup_file_private(sp, nv, &nvlfp->nvfp); @@ -1821,11 +1894,6 @@ nvidia_close_callback( (NV_ATOMIC_READ(nvl->usage_count) == 0) && rm_get_device_remove_flag(sp, nv->gpu_id); - for (i = 0; i < NV_FOPS_STACK_INDEX_COUNT; ++i) - { - nv_kmem_cache_free_stack(nvlfp->fops_sp[i]); - } - nv_free_file_private(nvlfp); /* @@ -1844,7 +1912,6 @@ nvidia_close_callback( */ if ((NV_ATOMIC_READ(nvl->usage_count) == 0) && nv->removed) { - nvidia_frontend_remove_device((void *)&nv_fops, nvl); nv_lock_destroy_locks(sp, nv); NV_KFREE(nvl, sizeof(nv_linux_state_t)); } @@ -2047,7 +2114,12 @@ nvidia_ioctl( if (status < 0) return status; - sp = nv_nvlfp_get_sp(nvlfp, NV_FOPS_STACK_INDEX_IOCTL); + status = nv_kmem_cache_alloc_stack(&sp); + if (status != 0) + { + nv_printf(NV_DBG_ERRORS, "NVRM: Unable to allocate altstack for ioctl\n"); + goto done; + } rmStatus = nv_check_gpu_state(nv); if (rmStatus == NV_ERR_GPU_IS_LOST) @@ -2233,15 +2305,7 @@ nvidia_ioctl( goto done; } - api->offline_addresses.numEntries = - ARRAY_SIZE(api->offline_addresses.addresses), - - rmStatus = rm_get_gpu_numa_info(sp, nv, - &(api->nid), - &(api->numa_mem_addr), - &(api->numa_mem_size), - (api->offline_addresses.addresses), - &(api->offline_addresses.numEntries)); + rmStatus = rm_get_gpu_numa_info(sp, nv, api); if (rmStatus != NV_OK) { status = -EBUSY; @@ -2359,7 +2423,7 @@ nvidia_ioctl( } done: - nv_nvlfp_put_sp(nvlfp, NV_FOPS_STACK_INDEX_IOCTL); + nv_kmem_cache_free_stack(sp); up_read(&nv_system_pm_lock); @@ -2379,6 +2443,15 @@ nvidia_ioctl( return status; } +long nvidia_unlocked_ioctl( + struct file *file, + unsigned int cmd, + unsigned long i_arg +) +{ + return nvidia_ioctl(NV_FILE_INODE(file), file, cmd, i_arg); +} + irqreturn_t nvidia_isr_msix( int irq, @@ -2693,7 +2766,6 @@ nvidia_ctl_close( nv_state_t *nv = NV_STATE_PTR(nvl); nv_linux_file_private_t *nvlfp = NV_GET_LINUX_FILE_PRIVATE(file); nvidia_stack_t *sp = nvlfp->sp; - unsigned int i; nv_printf(NV_DBG_INFO, "NVRM: nvidia_ctl_close\n"); @@ -2736,11 +2808,6 @@ nvidia_ctl_close( nvlfp->num_attached_gpus = 0; } - for (i = 0; i < NV_FOPS_STACK_INDEX_COUNT; ++i) - { - nv_kmem_cache_free_stack(nvlfp->fops_sp[i]); - } - nv_free_file_private(nvlfp); NV_SET_FILE_PRIVATE(file, NULL); @@ -3326,6 +3393,7 @@ NV_STATUS NV_API_CALL nv_free_kernel_mapping( NV_STATUS NV_API_CALL nv_alloc_pages( nv_state_t *nv, NvU32 page_count, + NvU64 page_size, NvBool contiguous, NvU32 cache_type, NvBool zeroed, @@ -3413,9 +3481,14 @@ NV_STATUS NV_API_CALL nv_alloc_pages( } if (at->flags.contig) + { status = nv_alloc_contig_pages(nv, at); + } else + { + at->order = get_order(page_size); status = nv_alloc_system_pages(nv, at); + } if (status != NV_OK) goto failed; @@ -3643,7 +3716,7 @@ nv_file_private_t* NV_API_CALL nv_get_file_private( if (ctl) { - if (MINOR(rdev) != NV_CONTROL_DEVICE_MINOR) + if (MINOR(rdev) != NV_MINOR_DEVICE_NUMBER_CONTROL_DEVICE) goto fail; } else @@ -3651,9 +3724,9 @@ nv_file_private_t* NV_API_CALL nv_get_file_private( NvBool found = NV_FALSE; int i; - for (i = 0; i <= NV_FRONTEND_CONTROL_DEVICE_MINOR_MIN; i++) + for (i = 0; i <= NV_MINOR_DEVICE_NUMBER_REGULAR_MAX; i++) { - if ((nv_minor_num_table[i] != NULL) && (MINOR(rdev) == i)) + if ((nv_linux_minor_num_table[i] != NULL) && (MINOR(rdev) == i)) { found = NV_TRUE; break; @@ -4375,6 +4448,7 @@ nvidia_transition_dynamic_power( nv_linux_state_t *nvl = pci_get_drvdata(pci_dev); nv_state_t *nv = NV_STATE_PTR(nvl); nvidia_stack_t *sp = NULL; + NvBool bTryAgain = NV_FALSE; NV_STATUS status; if ((nv->flags & (NV_FLAG_OPEN | NV_FLAG_PERSISTENT_SW_STATE)) == 0) @@ -4387,10 +4461,19 @@ nvidia_transition_dynamic_power( return -ENOMEM; } - status = rm_transition_dynamic_power(sp, nv, enter); + status = rm_transition_dynamic_power(sp, nv, enter, &bTryAgain); nv_kmem_cache_free_stack(sp); + if (bTryAgain) + { + /* + * Return -EAGAIN so that kernel PM core will not treat this as a fatal error and + * reschedule the callback again in the future. + */ + return -EAGAIN; + } + return (status == NV_OK) ? 0 : -EIO; } @@ -4885,34 +4968,37 @@ NV_STATUS NV_API_CALL nv_get_device_memory_config( NvS32 *node_id ) { - nv_linux_state_t *nvl = NV_GET_NVL_FROM_NV_STATE(nv); NV_STATUS status = NV_ERR_NOT_SUPPORTED; +#if defined(NVCPU_PPC64LE) + nv_linux_state_t *nvl = NV_GET_NVL_FROM_NV_STATE(nv); + if (!nv_platform_supports_numa(nvl)) { return NV_ERR_NOT_SUPPORTED; } -#if defined(NVCPU_PPC64LE) - nv_npu_numa_info_t *numa_info; - - numa_info = &nvl->npu->numa_info; - if (node_id != NULL) { *node_id = nvl->numa_info.node_id; } - if (compr_addr_sys_phys != NULL) { - *compr_addr_sys_phys = - numa_info->compr_sys_phys_addr; - } + nv_npu_numa_info_t *numa_info; - if (addr_guest_phys != NULL) - { - *addr_guest_phys = - numa_info->guest_phys_addr; + numa_info = &nvl->npu->numa_info; + + if (compr_addr_sys_phys != NULL) + { + *compr_addr_sys_phys = + numa_info->compr_sys_phys_addr; + } + + if (addr_guest_phys != NULL) + { + *addr_guest_phys = + numa_info->guest_phys_addr; + } } if (addr_width != NULL) @@ -4923,6 +5009,8 @@ NV_STATUS NV_API_CALL nv_get_device_memory_config( status = NV_OK; #endif #if defined(NVCPU_AARCH64) + nv_linux_state_t *nvl = NV_GET_NVL_FROM_NV_STATE(nv); + if (node_id != NULL) { *node_id = nvl->numa_info.node_id; @@ -5014,6 +5102,7 @@ NV_STATUS NV_API_CALL nv_indicate_idle( nv_state_t *nv ) { +#if NV_FILESYSTEM_ACCESS_AVAILABLE #if defined(NV_PM_RUNTIME_AVAILABLE) nv_linux_state_t *nvl = NV_GET_NVL_FROM_NV_STATE(nv); struct device *dev = nvl->dev; @@ -5052,6 +5141,9 @@ NV_STATUS NV_API_CALL nv_indicate_idle( #else return NV_ERR_NOT_SUPPORTED; #endif +#else + return NV_ERR_NOT_SUPPORTED; +#endif } NV_STATUS NV_API_CALL nv_indicate_not_idle( @@ -5098,8 +5190,27 @@ NvBool NV_API_CALL nv_dynamic_power_available( } /* caller should hold nv_linux_devices_lock using LOCK_NV_LINUX_DEVICES */ -void nv_linux_add_device_locked(nv_linux_state_t *nvl) +int nv_linux_add_device_locked(nv_linux_state_t *nvl) { + int rc = -1; + int i; + + // look for free a minor number and assign unique minor number to this device + for (i = 0; i <= NV_MINOR_DEVICE_NUMBER_REGULAR_MAX; i++) + { + if (nv_linux_minor_num_table[i] == NULL) + { + nv_linux_minor_num_table[i] = nvl; + nvl->minor_num = i; + rc = 0; + break; + } + } + + // bail if no minor number is free + if (rc != 0) + return rc; + if (nv_linux_devices == NULL) { nv_linux_devices = nvl; } @@ -5109,6 +5220,8 @@ void nv_linux_add_device_locked(nv_linux_state_t *nvl) for (tnvl = nv_linux_devices; tnvl->next != NULL; tnvl = tnvl->next); tnvl->next = nvl; } + + return rc; } /* caller should hold nv_linux_devices_lock using LOCK_NV_LINUX_DEVICES */ @@ -5123,6 +5236,8 @@ void nv_linux_remove_device_locked(nv_linux_state_t *nvl) for (tnvl = nv_linux_devices; tnvl->next != nvl; tnvl = tnvl->next); tnvl->next = nvl->next; } + + nv_linux_minor_num_table[nvl->minor_num] = NULL; } void NV_API_CALL nv_control_soc_irqs(nv_state_t *nv, NvBool bEnable) @@ -5641,3 +5756,91 @@ NV_STATUS NV_API_CALL nv_get_egm_info( NV_DEV_PRINTF(NV_DBG_INFO, nv, "Cannot get EGM info\n"); return NV_ERR_NOT_SUPPORTED; } + + +/* + * nvidia_register_module "extmod" emulation + * + * TODO remove once NVKMS migrates + * + * Emulate nv-frontend's behavior of enabling the use of minor number 254 + * given module->instance == 1 via the file operations provided in the + * nvidia_module_t structure. + * + * This path is only used by NVKMS and will be removed once NVKMS migrates + * to export its own file_operations structure directly. + */ +static struct file_operations nv_extmod_fops; +static struct cdev nv_extmod_cdev; +static nvidia_module_t *nv_extmod; + +static long nv_extmod_unlocked_ioctl( + struct file *file, + unsigned int cmd, + unsigned long i_arg +) +{ + return nv_extmod->ioctl(NV_FILE_INODE(file), file, cmd, i_arg); +} + +int nvidia_register_module(nvidia_module_t *module) +{ + int rc; + + down(&nv_extmod_lock); + if ((nv_extmod != NULL) || (module == NULL) || (module->instance != 1)) + { + nv_printf(NV_DBG_ERRORS, + "NVRM: NVIDIA module (emulated) registration failed.\n"); + up(&nv_extmod_lock); + return -EINVAL; + } + + memset(&nv_extmod_fops, 0, sizeof(nv_extmod_fops)); + nv_extmod_fops.owner = module->owner; + nv_extmod_fops.poll = module->poll; + nv_extmod_fops.unlocked_ioctl = nv_extmod_unlocked_ioctl; +#if NVCPU_IS_X86_64 || NVCPU_IS_AARCH64 + nv_extmod_fops.compat_ioctl = nv_extmod_unlocked_ioctl; +#endif + nv_extmod_fops.mmap = module->mmap; + nv_extmod_fops.open = module->open; + nv_extmod_fops.release = module->close; + + rc = nv_register_chrdev(NV_MINOR_DEVICE_NUMBER_MODESET_DEVICE, 1, + &nv_extmod_cdev, "nvidia-modeset", &nv_extmod_fops); + if (rc < 0) + { + up(&nv_extmod_lock); + return rc; + } + + nv_extmod = module; + up(&nv_extmod_lock); + return rc; +} +EXPORT_SYMBOL(nvidia_register_module); + +int nvidia_unregister_module(nvidia_module_t *module) +{ + down(&nv_extmod_lock); + if (nv_extmod == NULL) + { + nv_printf(NV_DBG_ERRORS, + "NVRM: NVIDIA module (emulated) non-existent de-registration.\n"); + up(&nv_extmod_lock); + return -EINVAL; + } + + nv_unregister_chrdev(NV_MINOR_DEVICE_NUMBER_MODESET_DEVICE, 1, + &nv_extmod_cdev); + + nv_extmod = NULL; + up(&nv_extmod_lock); + return 0; +} +EXPORT_SYMBOL(nvidia_unregister_module); + + +module_init(nvidia_init_module); +module_exit(nvidia_exit_module); diff --git a/kernel-open/nvidia/nv_uvm_interface.c b/kernel-open/nvidia/nv_uvm_interface.c index ce5dfdf9b0..c5638adc6f 100644 --- a/kernel-open/nvidia/nv_uvm_interface.c +++ b/kernel-open/nvidia/nv_uvm_interface.c @@ -209,7 +209,7 @@ NV_STATUS nvUvmInterfaceSessionCreate(uvmGpuSessionHandle *session, memset(platformInfo, 0, sizeof(*platformInfo)); platformInfo->atsSupported = nv_ats_supported; - platformInfo->confComputingEnabled = os_cc_enabled; + platformInfo->sevEnabled = os_cc_enabled; status = rm_gpu_ops_create_session(sp, (gpuSessionHandle *)session); diff --git a/kernel-open/nvidia/nvidia-sources.Kbuild b/kernel-open/nvidia/nvidia-sources.Kbuild index c57a06c621..9bfc307fc1 100644 --- a/kernel-open/nvidia/nvidia-sources.Kbuild +++ b/kernel-open/nvidia/nvidia-sources.Kbuild @@ -30,7 +30,6 @@ NVIDIA_SOURCES += nvidia/nv-report-err.c NVIDIA_SOURCES += nvidia/nv-rsync.c NVIDIA_SOURCES += nvidia/nv-msi.c NVIDIA_SOURCES += nvidia/nv-caps.c -NVIDIA_SOURCES += nvidia/nv-frontend.c NVIDIA_SOURCES += nvidia/nv_uvm_interface.c NVIDIA_SOURCES += nvidia/libspdm_aead.c NVIDIA_SOURCES += nvidia/libspdm_ecc.c diff --git a/kernel-open/nvidia/nvlink_linux.c b/kernel-open/nvidia/nvlink_linux.c index 9546660146..11e798d65b 100644 --- a/kernel-open/nvidia/nvlink_linux.c +++ b/kernel-open/nvidia/nvlink_linux.c @@ -639,3 +639,8 @@ int nvlink_is_admin(void) { return NV_IS_SUSER(); } + +NvU64 nvlink_get_platform_time(void) +{ + return nv_ktime_get_raw_ns(); +} diff --git a/kernel-open/nvidia/nvlink_os.h b/kernel-open/nvidia/nvlink_os.h index 80a2a3abe9..c23242a388 100644 --- a/kernel-open/nvidia/nvlink_os.h +++ b/kernel-open/nvidia/nvlink_os.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -64,6 +64,7 @@ void nvlink_assert(int expression); void nvlink_sleep(unsigned int ms); void nvlink_print(const char *, int, const char *, int, const char *, ...); int nvlink_is_admin(void); +NvU64 nvlink_get_platform_time(void); // Capability functions NvlStatus nvlink_acquire_fabric_mgmt_cap(void *osPrivate, NvU64 capDescriptor); diff --git a/kernel-open/nvidia/os-interface.c b/kernel-open/nvidia/os-interface.c index 588689b74b..524e8c4877 100644 --- a/kernel-open/nvidia/os-interface.c +++ b/kernel-open/nvidia/os-interface.c @@ -782,6 +782,8 @@ inline void NV_API_CALL out_string(const char *str) printk("%s", str); } +#define NV_PRINT_LOCAL_BUFF_LEN_MAX 530 + /* * nv_printf() prints to the kernel log for the driver. * Returns the number of characters written. @@ -790,11 +792,38 @@ int NV_API_CALL nv_printf(NvU32 debuglevel, const char *printf_format, ...) { va_list arglist; int chars_written = 0; + NvBool bForced = (NV_DBG_FORCE_LEVEL(debuglevel) == debuglevel); + debuglevel = debuglevel & 0xff; + + // This function is protected by the "_nv_dbg_lock" lock, so it is still + // thread-safe to store the print buffer in a static variable, thus + // avoiding a problem with kernel stack size. + static char buff[NV_PRINT_LOCAL_BUFF_LEN_MAX]; - if (debuglevel >= ((cur_debuglevel >> 4) & 0x3)) + /* + * Print a message if: + * 1. Caller indicates that filtering should be skipped, or + * 2. debuglevel is at least cur_debuglevel for DBG_MODULE_OS (bits 4:5). Support for print + * modules has been removed with DBG_PRINTF, so this check should be cleaned up. + */ + if (bForced || + (debuglevel >= ((cur_debuglevel >> 4) & 0x3))) { - size_t length; - char *temp; + size_t loglevel_length = 0, format_length = strlen(printf_format); + size_t length = 0; + const char *loglevel = ""; + + switch (debuglevel) + { + case NV_DBG_INFO: loglevel = KERN_DEBUG; break; + case NV_DBG_SETUP: loglevel = KERN_NOTICE; break; + case NV_DBG_WARNINGS: loglevel = KERN_WARNING; break; + case NV_DBG_ERRORS: loglevel = KERN_ERR; break; + case NV_DBG_HW_ERRORS: loglevel = KERN_CRIT; break; + case NV_DBG_FATAL: loglevel = KERN_CRIT; break; + } + + loglevel_length = strlen(loglevel); // When printk is called to extend the output of the previous line // (i.e. when the previous line did not end in \n), the printk call @@ -814,24 +843,19 @@ int NV_API_CALL nv_printf(NvU32 debuglevel, const char *printf_format, ...) // string always contains only one \n (at the end) and NV_PRINTF_EX // is deleted. But that is unlikely to ever happen. - length = strlen(printf_format); + length = loglevel_length + format_length + sizeof(KERN_CONT); if (length < 1) return 0; - temp = kmalloc(length + sizeof(KERN_CONT), GFP_ATOMIC); - if (!temp) - return 0; - // KERN_CONT changed in the 3.6 kernel, so we can't assume its // composition or size. - memcpy(temp, KERN_CONT, sizeof(KERN_CONT) - 1); - memcpy(temp + sizeof(KERN_CONT) - 1, printf_format, length + 1); + memcpy(buff, KERN_CONT, sizeof(KERN_CONT) - 1); + memcpy(buff + sizeof(KERN_CONT) - 1, loglevel, loglevel_length); + memcpy(buff + sizeof(KERN_CONT) - 1 + loglevel_length, printf_format, length + 1); va_start(arglist, printf_format); - chars_written = vprintk(temp, arglist); + chars_written = vprintk(buff, arglist); va_end(arglist); - - kfree(temp); } return chars_written; @@ -1199,10 +1223,10 @@ NvBool NV_API_CALL os_is_efi_enabled(void) void NV_API_CALL os_get_screen_info( NvU64 *pPhysicalAddress, - NvU16 *pFbWidth, - NvU16 *pFbHeight, - NvU16 *pFbDepth, - NvU16 *pFbPitch, + NvU32 *pFbWidth, + NvU32 *pFbHeight, + NvU32 *pFbDepth, + NvU32 *pFbPitch, NvU64 consoleBar1Address, NvU64 consoleBar2Address ) @@ -1807,6 +1831,7 @@ NV_STATUS NV_API_CALL os_open_temporary_file void **ppFile ) { +#if NV_FILESYSTEM_ACCESS_AVAILABLE #if defined(O_TMPFILE) struct file *file; const char *default_path = "/tmp"; @@ -1852,6 +1877,9 @@ NV_STATUS NV_API_CALL os_open_temporary_file #else return NV_ERR_NOT_SUPPORTED; #endif +#else + return NV_ERR_NOT_SUPPORTED; +#endif } void NV_API_CALL os_close_file @@ -1859,7 +1887,9 @@ void NV_API_CALL os_close_file void *pFile ) { +#if NV_FILESYSTEM_ACCESS_AVAILABLE filp_close(pFile, NULL); +#endif } #define NV_MAX_NUM_FILE_IO_RETRIES 10 @@ -1872,6 +1902,7 @@ NV_STATUS NV_API_CALL os_write_file NvU64 offset ) { +#if NV_FILESYSTEM_ACCESS_AVAILABLE loff_t f_pos = offset; ssize_t num_written; int num_retries = NV_MAX_NUM_FILE_IO_RETRIES; @@ -1902,6 +1933,9 @@ NV_STATUS NV_API_CALL os_write_file } return NV_OK; +#else + return NV_ERR_NOT_SUPPORTED; +#endif } NV_STATUS NV_API_CALL os_read_file @@ -1912,6 +1946,7 @@ NV_STATUS NV_API_CALL os_read_file NvU64 offset ) { +#if NV_FILESYSTEM_ACCESS_AVAILABLE loff_t f_pos = offset; ssize_t num_read; int num_retries = NV_MAX_NUM_FILE_IO_RETRIES; @@ -1942,6 +1977,9 @@ NV_STATUS NV_API_CALL os_read_file } return NV_OK; +#else + return NV_ERR_NOT_SUPPORTED; +#endif } NV_STATUS NV_API_CALL os_open_readonly_file @@ -1950,6 +1988,7 @@ NV_STATUS NV_API_CALL os_open_readonly_file void **ppFile ) { +#if NV_FILESYSTEM_ACCESS_AVAILABLE struct file *file; /* @@ -1971,6 +2010,9 @@ NV_STATUS NV_API_CALL os_open_readonly_file *ppFile = (void *)file; return NV_OK; +#else + return NV_ERR_NOT_SUPPORTED; +#endif } NV_STATUS NV_API_CALL os_open_and_read_file diff --git a/src/common/displayport/inc/dp_configcaps.h b/src/common/displayport/inc/dp_configcaps.h index fc570fee00..17ddf03f0b 100644 --- a/src/common/displayport/inc/dp_configcaps.h +++ b/src/common/displayport/inc/dp_configcaps.h @@ -454,6 +454,10 @@ namespace DisplayPort virtual bool getLinkStatusChanged() = 0; virtual void clearLinkStatusChanged() = 0; + virtual bool isPanelReplayErrorSet() = 0; + virtual void clearPanelReplayError() = 0; + virtual void readPanelReplayError() = 0; + virtual bool getHdmiLinkStatusChanged() = 0; virtual void clearHdmiLinkStatusChanged() = 0; @@ -523,6 +527,8 @@ namespace DisplayPort virtual bool readPsrErrorStatus(vesaPsrErrorStatus *psrErr) = 0; virtual bool writePsrEvtIndicator(vesaPsrEventIndicator psrErr) = 0; virtual bool readPsrEvtIndicator(vesaPsrEventIndicator *psrErr) = 0; + virtual bool readPrSinkDebugInfo(panelReplaySinkDebugInfo *prDbgInfo) = 0; + virtual ~DPCDHAL() {} }; diff --git a/src/common/displayport/inc/dp_connector.h b/src/common/displayport/inc/dp_connector.h index 4328397d8e..d26eee763c 100644 --- a/src/common/displayport/inc/dp_connector.h +++ b/src/common/displayport/inc/dp_connector.h @@ -48,6 +48,34 @@ namespace DisplayPort { class EvoInterface; + + typedef enum + { + DP_IMP_ERROR_NONE, + DP_IMP_ERROR_ZERO_VALUE_PARAMS, + DP_IMP_ERROR_AUDIO_BEYOND_48K, + DP_IMP_ERROR_DSC_SYNAPTICS_COLOR_FORMAT, + DP_IMP_ERROR_PPS_DSC_DUAL_FORCE, + DP_IMP_ERROR_DSC_PCON_FRL_BANDWIDTH, + DP_IMP_ERROR_DSC_PCON_HDMI2_BANDWIDTH, + DP_IMP_ERROR_DSC_LAST_HOP_BANDWIDTH, + DP_IMP_ERROR_INSUFFICIENT_BANDWIDTH, + DP_IMP_ERROR_INSUFFICIENT_BANDWIDTH_DSC, + DP_IMP_ERROR_INSUFFICIENT_BANDWIDTH_NO_DSC, + DP_IMP_ERROR_WATERMARK_BLANKING, + DP_IMP_ERROR_PPS_COLOR_FORMAT_NOT_SUPPORTED, + DP_IMP_ERROR_PPS_INVALID_HBLANK, + DP_IMP_ERROR_PPS_INVALID_BPC, + DP_IMP_ERROR_PPS_MAX_LINE_BUFFER_ERROR, + DP_IMP_ERROR_PPS_OVERALL_THROUGHPUT_ERROR, + DP_IMP_ERROR_PPS_DSC_SLICE_ERROR, + DP_IMP_ERROR_PPS_PPS_SLICE_COUNT_ERROR, + DP_IMP_ERROR_PPS_PPS_SLICE_HEIGHT_ERROR, + DP_IMP_ERROR_PPS_PPS_SLICE_WIDTH_ERROR, + DP_IMP_ERROR_PPS_INVALID_PEAK_THROUGHPUT, + DP_IMP_ERROR_PPS_MIN_SLICE_COUNT_ERROR, + DP_IMP_ERROR_PPS_GENERIC_ERROR, + } DP_IMP_ERROR; typedef enum { @@ -125,14 +153,36 @@ namespace DisplayPort ForceDsc forceDsc; // [IN] - Client telling DP Library to force enable/disable DSC DSC_INFO::FORCED_DSC_PARAMS* forcedParams; // [IN] - Client telling DP Library to force certain DSC params. bool bEnableDsc; // [OUT] - DP Library telling client that DSC is needed for this mode. + NvU32 sliceCountMask; // [OUT] - DP Library telling client what all slice counts can be used for the mode. unsigned bitsPerPixelX16; // [IN/OUT] - Bits per pixel value multiplied by 16 DscOutParams *pDscOutParams; // [OUT] - DSC parameters - DscParams() : bCheckWithDsc(false), forceDsc(DSC_DEFAULT), forcedParams(NULL), bEnableDsc(false), bitsPerPixelX16(0), pDscOutParams(NULL) {} + DscParams() : bCheckWithDsc(false), forceDsc(DSC_DEFAULT), forcedParams(NULL), bEnableDsc(false), sliceCountMask(0), bitsPerPixelX16(0), pDscOutParams(NULL) {} }; class Group; + struct DpLinkIsModePossibleParams + { + struct + { + Group * pTarget; + DpModesetParams *pModesetParams; + DP_IMP_ERROR *pErrorStatus; + DscParams *pDscParams; + } head[NV_MAX_HEADS]; + }; + + struct DpPreModesetParams + { + struct + { + Group *pTarget; + const DpModesetParams *pModesetParams; + } head[NV_MAX_HEADS]; + NvU32 headMask; + }; + bool SetConfigSingleHeadMultiStreamMode(Group **targets, // Array of group pointers given for getting configured in single head multistream mode. NvU32 displayIDs[], // Array of displayIDs given for getting configured in single head multistream mode. NvU32 numStreams, // Number of streams driven out from single head. @@ -418,7 +468,7 @@ namespace DisplayPort // Will tell you if you have sufficient bandwidth to operate // two panels at 1920x1080 and 1280x1024 assuming all currently // attached panels are detached. - virtual void beginCompoundQuery() = 0; + virtual void beginCompoundQuery(const bool bForceEnableFEC = false) = 0; // // twoChannelAudioHz @@ -442,14 +492,18 @@ namespace DisplayPort unsigned rasterHeight, unsigned rasterBlankStartX, unsigned rasterBlankEndX, - unsigned depth) = 0; + unsigned depth, + DP_IMP_ERROR *errorStatus = NULL) = 0; virtual bool compoundQueryAttach(Group * target, const DpModesetParams &modesetParams, // Modeset info - DscParams *pDscParams) = 0; // DSC parameters + DscParams *pDscParams, // DSC parameters + DP_IMP_ERROR *errorStatus = NULL) = 0; // Error Status code virtual bool endCompoundQuery() = 0; + virtual bool dpLinkIsModePossible(const DpLinkIsModePossibleParams ¶ms) = 0; + // Interface to indicate if clients need to perform a head shutdown before a modeset virtual bool isHeadShutDownNeeded(Group * target, // Group of panels we're attaching to this head unsigned headIndex, @@ -503,6 +557,9 @@ namespace DisplayPort // Group of panels we're attaching to this head virtual bool notifyAttachBegin(Group * target, const DpModesetParams &modesetParams) = 0; + virtual void dpPreModeset(const DpPreModesetParams &modesetParams) = 0; + virtual void dpPostModeset(void) = 0; + virtual void readRemoteHdcpCaps() = 0; // modeset might be cancelled when NAB failed @@ -674,6 +731,8 @@ namespace DisplayPort virtual bool readPsrEvtIndicator(vesaPsrEventIndicator *psrErr) = 0; virtual bool updatePsrLinkState(bool bTrainLink) = 0; + virtual bool readPrSinkDebugInfo(panelReplaySinkDebugInfo *prDbgInfo) = 0; + protected: virtual ~Connector() {} }; diff --git a/src/common/displayport/inc/dp_connectorimpl.h b/src/common/displayport/inc/dp_connectorimpl.h index 7920a2710e..263ff4d967 100644 --- a/src/common/displayport/inc/dp_connectorimpl.h +++ b/src/common/displayport/inc/dp_connectorimpl.h @@ -76,6 +76,13 @@ namespace DisplayPort DP_TRANSPORT_MODE_MULTI_STREAM = 2, } DP_TRANSPORT_MODE; + // Information required during compound query attach for MST + typedef struct _CompoundQueryAttachMSTInfo + { + ModesetInfo localModesetInfo; + LinkConfiguration lc; + } CompoundQueryAttachMSTInfo; + struct ConnectorImpl : public Connector, DiscoveryManager::DiscoveryManagerEventSink, Timer::TimerCallback, MessageManager::MessageReceiver::MessageReceiverEventSink { // DPCD HAL Layer - We should use this in place of direct register accesses @@ -93,12 +100,14 @@ namespace DisplayPort unsigned cachedSourceOUI; char cachedSourceModelName[NV_DPCD_SOURCE_DEV_ID_STRING__SIZE + 1]; NvU8 cachedSourceChipRevision; + bool bOuiCached; unsigned ouiId; // Sink ouiId char modelName[NV_DPCD_SOURCE_DEV_ID_STRING__SIZE + 1]; // Device Model-name bool bIgnoreSrcOuiHandshake; // Skip writing source OUI - LinkPolicy linkPolicy; + LinkPolicy linkPolicy; + bool linkGuessed; // True when link was "guessed" during HPD in TMDS mode bool isLinkQuiesced; // True when link was set to quiet mode by TMDS modeset @@ -176,11 +185,14 @@ namespace DisplayPort LinkedList addStreamMSTIntransitionGroups; List inactiveGroups; + LinkedList dscEnabledDevices; + // Compound query bool compoundQueryActive; bool compoundQueryResult; unsigned compoundQueryCount; unsigned compoundQueryLocalLinkPBN; + bool compoundQueryForceEnableFEC; unsigned freeSlots, maximumSlots; @@ -334,13 +346,8 @@ namespace DisplayPort // bool bPowerDownPhyBeforeD3; - // - // Reset the MSTM_CTRL registers on Synaptics branch device irrespective of - // IRQ VECTOR register having stale message. Synaptics device needs to reset - // the topology before issue of new LAM message if previous LAM was not finished - // bug 3928070 - // - bool bForceClearPendingMsg; + Group *perHeadAttachedGroup[NV_MAX_HEADS]; + NvU32 inTransitionHeadMask; void sharedInit(); ConnectorImpl(MainLink * main, AuxBus * auxBus, Timer * timer, Connector::EventSink * sink); @@ -386,6 +393,7 @@ namespace DisplayPort } void populateAllDpConfigs(); + virtual LinkRates* importDpLinkRates(); // // Suspend resume API @@ -403,7 +411,7 @@ namespace DisplayPort virtual Device * enumDevices(Device * previousDevice) ; - virtual void beginCompoundQuery() ; + virtual void beginCompoundQuery(const bool bForceEnableFEC = false) ; virtual bool compoundQueryAttach(Group * target, unsigned twoChannelAudioHz, // if you need 192khz stereo specify 192000 here unsigned eightChannelAudioHz, // Same setting for multi channel audio. @@ -413,14 +421,56 @@ namespace DisplayPort unsigned rasterHeight, unsigned rasterBlankStartX, unsigned rasterBlankEndX, - unsigned depth); + unsigned depth, + DP_IMP_ERROR *errorStatus = NULL); virtual bool compoundQueryAttach(Group * target, const DpModesetParams &modesetParams, // Modeset info - DscParams *pDscParams = NULL); // DSC parameters + DscParams *pDscParams = NULL, // DSC parameters + DP_IMP_ERROR *pErrorCode = NULL); // Error Status code virtual bool endCompoundQuery(); + virtual bool dpLinkIsModePossible(const DpLinkIsModePossibleParams ¶ms); + + virtual bool compoundQueryAttachMST(Group * target, + const DpModesetParams &modesetParams, // Modeset info + DscParams *pDscParams = NULL, // DSC parameters + DP_IMP_ERROR *pErrorCode = NULL); // Error Status code + + virtual bool compoundQueryAttachMSTIsDscPossible + ( + Group * target, + const DpModesetParams &modesetParams, // Modeset info + DscParams *pDscParams = NULL // DSC parameters + ); + + // Calculate and Configure SW state based on DSC + virtual bool compoundQueryAttachMSTDsc + ( + Group * target, + const DpModesetParams &modesetParams, // Modeset info + CompoundQueryAttachMSTInfo * info, // local info to update for later use + DscParams *pDscParams = NULL, // DSC parameters + DP_IMP_ERROR *pErrorCode = NULL // Error Status code + ); + + // General part of CQA MST for DSC/non-DSC + virtual bool compoundQueryAttachMSTGeneric + ( + Group * target, + const DpModesetParams &modesetParams, // Modeset info + CompoundQueryAttachMSTInfo * info, // local info with updates for DSC + DscParams *pDscParams = NULL, // DSC parameters + DP_IMP_ERROR *pErrorCode = NULL // Error Status code + ); + + virtual bool compoundQueryAttachSST(Group * target, + const DpModesetParams &modesetParams, // Modeset info + DscParams *pDscParams = NULL, // DSC parameters + DP_IMP_ERROR *pErrorCode = NULL); // Error Status code + + // // Timer callback tags. // (we pass the address of these variables as context to ::expired) @@ -458,6 +508,11 @@ namespace DisplayPort virtual bool notifyAttachBegin(Group * target, // Group of panels we're attaching to this head const DpModesetParams &modesetParams); + bool needToEnableFEC(const DpPreModesetParams ¶ms); + + virtual void dpPreModeset(const DpPreModesetParams &modesetParams); + virtual void dpPostModeset(void); + virtual bool isHeadShutDownNeeded(Group * target, // Group of panels we're attaching to this head unsigned headIndex, unsigned twoChannelAudioHz, // if you need 192khz stereo specify 192000 here @@ -559,6 +614,7 @@ namespace DisplayPort void handleHdmiLinkStatusChanged(); void sortActiveGroups(bool ascending); void configInit(); + void handlePanelReplayError(); virtual DeviceImpl* findDeviceInList(const Address & address); virtual void disconnectDeviceList(); @@ -584,6 +640,7 @@ namespace DisplayPort virtual void setDp11ProtocolForced(); virtual void resetDp11ProtocolForced(); virtual bool isDp11ProtocolForced(); + bool isAcpiInitDone(); virtual void notifyAcpiInitDone(); Group * createFirmwareGroup(); @@ -609,6 +666,8 @@ namespace DisplayPort virtual bool readPsrState(vesaPsrState *psrState); virtual bool updatePsrLinkState(bool bTrainLink); + virtual bool readPrSinkDebugInfo(panelReplaySinkDebugInfo *prDbgInfo); + // for dp test utility. pBuffer is the request buffer of type DP_STATUS_REQUEST_xxxx DP_TESTMESSAGE_STATUS sendDPTestMessage(void *pBuffer, NvU32 requestSize, diff --git a/src/common/displayport/inc/dp_deviceimpl.h b/src/common/displayport/inc/dp_deviceimpl.h index ef2dd0a264..c9964b9337 100644 --- a/src/common/displayport/inc/dp_deviceimpl.h +++ b/src/common/displayport/inc/dp_deviceimpl.h @@ -255,13 +255,13 @@ namespace DisplayPort virtual bool isLoop() { - DP_LOG(("isLoop implementation is pending (bug 791059)")); + // implementation is pending (bug 791059) return false; } virtual bool isRedundant() { - DP_LOG(("isRedundant implementation is pending (bug 791059)")); + // implementation is pending (bug 791059) return false; } diff --git a/src/common/displayport/inc/dp_evoadapter.h b/src/common/displayport/inc/dp_evoadapter.h index 30607f7fb9..478a2758c4 100644 --- a/src/common/displayport/inc/dp_evoadapter.h +++ b/src/common/displayport/inc/dp_evoadapter.h @@ -43,7 +43,6 @@ #define HDCP_DUMMY_CN (0x1) #define HDCP_DUMMY_CKSV (0xFFFFF) - namespace DisplayPort { class EvoInterface @@ -148,8 +147,7 @@ namespace DisplayPort // Bit mask for GPU supported DP versions. // Defines the same as NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS.dpVersionsSupported // - NvU32 _gpuSupportedDpVersions; - + NvU32 _gpuSupportedDpVersions; bool _isStreamCloningEnabled; bool _needForceRmEdid; bool _skipPowerdownEDPPanelWhenHeadDetach; @@ -160,7 +158,6 @@ namespace DisplayPort bool _applyLinkBwOverrideWarRegVal; bool _isDynamicMuxCapable; bool _enableMSAOverrideOverMST; - bool _enableFecCheckForDDS; bool _isLTPhyRepeaterSupported; // @@ -208,7 +205,6 @@ namespace DisplayPort { return _gpuSupportedDpVersions; } - virtual bool isFECSupported() { return _isFECSupported; diff --git a/src/common/displayport/inc/dp_linkconfig.h b/src/common/displayport/inc/dp_linkconfig.h index c3b8823abf..221294b6cc 100644 --- a/src/common/displayport/inc/dp_linkconfig.h +++ b/src/common/displayport/inc/dp_linkconfig.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2010-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -36,40 +36,66 @@ #include "ctrl/ctrl0073/ctrl0073specific.h" // NV0073_CTRL_HDCP_VPRIME_SIZE #include "displayport.h" - namespace DisplayPort { typedef NvU64 LinkRate; class LinkRates : virtual public Object { + public: + NvU8 entries; + + virtual void clear() = 0; + virtual bool import(NvU8 linkBw) + { + DP_ASSERT(0); + return false; + } + + virtual LinkRate getLowerRate(LinkRate rate) = 0; + virtual LinkRate getMaxRate() = 0; + virtual NvU8 getNumElements() = 0; + + NvU8 getNumLinkRates() + { + return entries; + } + + }; + + class LinkRates1x : virtual public LinkRates + { public: // Store link rate in multipler of 270MBPS to save space - NvU8 element[NV_DPCD_SUPPORTED_LINK_RATES__SIZE]; - NvU8 entries; + NvU8 element[NV_SUPPORTED_DP1X_LINK_RATES__SIZE]; - LinkRates() + LinkRates1x() { entries = 0; - - for (int i = 0; i < NV_DPCD_SUPPORTED_LINK_RATES__SIZE; i++) + for (int i = 0; i < NV_SUPPORTED_DP1X_LINK_RATES__SIZE; i++) { element[i] = 0; } } - void clear() + virtual void clear() { entries = 0; - for (int i = 0; i < NV_DPCD_SUPPORTED_LINK_RATES__SIZE; i++) + for (int i = 0; i < NV_SUPPORTED_DP1X_LINK_RATES__SIZE; i++) { element[i] = 0; } } - bool import(NvU8 linkBw) + virtual bool import(NvU8 linkBw) { - if (entries < NV_DPCD_SUPPORTED_LINK_RATES__SIZE) + if (!IS_VALID_LINKBW(linkBw)) + { + DP_ASSERT(0 && "Unsupported Link Bandwidth"); + return false; + } + + if (entries < NV_SUPPORTED_DP1X_LINK_RATES__SIZE) { element[entries] = linkBw; entries++; @@ -79,12 +105,7 @@ namespace DisplayPort return false; } - NvU8 getNumLinkRates() - { - return entries; - } - - LinkRate getLowerRate(LinkRate rate) + virtual LinkRate getLowerRate(LinkRate rate) { int i; NvU8 linkBw = (NvU8)(rate / DP_LINK_BW_FREQ_MULTI_MBPS); @@ -102,24 +123,29 @@ namespace DisplayPort return rate; } - LinkRate getMaxRate() + virtual LinkRate getMaxRate() { LinkRate rate = 0; if ((entries > 0) && - (entries <= NV_DPCD_SUPPORTED_LINK_RATES__SIZE)) + (entries <= NV_SUPPORTED_DP1X_LINK_RATES__SIZE)) { rate = (LinkRate)element[entries - 1] * DP_LINK_BW_FREQ_MULTI_MBPS; } return rate; } + virtual NvU8 getNumElements() + { + return NV_SUPPORTED_DP1X_LINK_RATES__SIZE; + } + }; class LinkPolicy : virtual public Object { - bool bNoFallback; // No fallback when LT fails - LinkRates linkRates; - + protected: + bool bNoFallback; // No fallback when LT fails + LinkRates1x linkRates; public: LinkPolicy() : bNoFallback(false) { @@ -138,13 +164,25 @@ namespace DisplayPort return &linkRates; } }; + enum { totalTimeslots = 64, totalUsableTimeslots = totalTimeslots - 1 }; - // in 10bps + // + // Link Data Rate per DP Lane, in MBPS, + // For 8b/10b channel coding: + // Link Data Rate = link rate * (8 / 10) / 8 + // = link rate * 0.1 + // For 128b/132b channel coding: + // Link Data Rate = link rate * (128 / 132) / 8 + // = link rate * 4 / 33 + // ~= link rate * 0.12 + // + // Link Bandwidth = Lane Count * Link Data Rate + // enum { RBR = 162000000, diff --git a/src/common/displayport/inc/dp_mainlink.h b/src/common/displayport/inc/dp_mainlink.h index 10bec81c67..b3d44a9061 100644 --- a/src/common/displayport/inc/dp_mainlink.h +++ b/src/common/displayport/inc/dp_mainlink.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -172,7 +172,6 @@ namespace DisplayPort virtual bool hasMultistream() = 0; virtual bool isPC2Disabled() = 0; virtual NvU32 getGpuDpSupportedVersions() = 0; - virtual bool isStreamCloningEnabled() = 0; virtual NvU32 maxLinkRateSupported() = 0; virtual bool isLttprSupported() = 0; diff --git a/src/common/displayport/inc/dp_regkeydatabase.h b/src/common/displayport/inc/dp_regkeydatabase.h index ec78f8374c..3d36761b20 100644 --- a/src/common/displayport/inc/dp_regkeydatabase.h +++ b/src/common/displayport/inc/dp_regkeydatabase.h @@ -59,9 +59,6 @@ #define NV_DP_REGKEY_FORCE_EDP_ILR "DP_BYPASS_EDP_ILR_REV_CHECK" -// Regkey to make sure enable FEC only when RM notified sink successfully -#define NV_DP_CHECK_FEC_FOR_DDS_DSC_PANEL "DP_DDS_CHECK_FEC_TO_ENABLE" - // Message to power down video stream before power down link (set D3) #define NV_DP_REGKEY_POWER_DOWN_PHY "DP_POWER_DOWN_PHY" @@ -77,7 +74,6 @@ // #define NV_DP_DSC_MST_CAP_BUG_3143315 "DP_DSC_MST_CAP_BUG_3143315" - // // Data Base used to store all the regkey values. // The actual data base is declared statically in dp_evoadapter.cpp. @@ -110,7 +106,6 @@ struct DP_REGKEY_DATABASE bool bBypassEDPRevCheck; bool bDscMstCapBug3143315; bool bPowerDownPhyBeforeD3; - bool bCheckFECForDynamicMuxDSCPanel; bool bReassessMaxLink; }; diff --git a/src/common/displayport/src/dp_configcaps.cpp b/src/common/displayport/src/dp_configcaps.cpp index ca25affee6..a302a89d87 100644 --- a/src/common/displayport/src/dp_configcaps.cpp +++ b/src/common/displayport/src/dp_configcaps.cpp @@ -142,6 +142,7 @@ struct DPCDHALImpl : DPCDHAL bool mccsIRQ; bool downRepMsgRdy; bool upReqMsgRdy; + bool prErrorStatus; // DPCD offset 2004h[3] bool rxCapChanged; // DPCD offset 2005 bool linkStatusChanged; // DPCD offset 2005 bool streamStatusChanged; // DPCD offset 2005 @@ -642,12 +643,20 @@ struct DPCDHALImpl : DPCDHAL return caps.repeaterCaps.revisionMinor; } - virtual LinkRate getMaxLinkRate() // DPCD offset 1 * 27000000 + // + // Legacy link rates: DPCD offset 1 * 27000000 + // ILRs: DPCD offset: 0x10~0x1F + // + virtual LinkRate getMaxLinkRate() { if (caps.phyRepeaterCount == 0) + { return caps.maxLinkRate; + } else + { return DP_MIN(caps.maxLinkRate, caps.repeaterCaps.maxLinkRate); + } } virtual unsigned getMaxLaneCount() // DPCD offset 2 @@ -1621,6 +1630,51 @@ struct DPCDHALImpl : DPCDHAL bus.write(NV_DPCD_LINK_SERVICE_IRQ_VECTOR_ESI0, &irqVector, sizeof irqVector); } + virtual bool isPanelReplayErrorSet() + { + return interrupts.prErrorStatus; + } + + virtual void readPanelReplayError() + { + NvU8 config = 0U; + bool bRetVal = (AuxRetry::ack == + bus.read(NV_DPCD20_PANEL_REPLAY_ERROR_STATUS, + &config, sizeof(config))); + + if (bRetVal) + { + if (FLD_TEST_DRF(_DPCD20_PANEL_REPLAY, _ERROR_STATUS, + _ACTIVE_FRAME_CRC_ERROR, _YES, config)) + { + DP_LOG(("DPHAL> ERROR! Active Frame CRC Error set in PanelReplay status register")); + } + if (FLD_TEST_DRF(_DPCD20_PANEL_REPLAY, _ERROR_STATUS, + _RFB_STORAGE_ERROR, _YES, config)) + { + DP_LOG(("DPHAL> ERROR! RFB Storage Error set in PanelReplay status register")); + } + if (FLD_TEST_DRF(_DPCD20_PANEL_REPLAY, _ERROR_STATUS, + _VSC_SDP_UNCORRECTABLE_ERROR, _YES, config)) + { + DP_LOG(("DPHAL> ERROR! VSC SDP Uncorrectable Error set in PanelReplay status register")); + } + } + else + { + DP_LOG(("DPHAL> readPanelReplayError: Failed to read PanelReplay error status")); + } + } + + virtual void clearPanelReplayError() + { + NvU8 irqVector = 0U; + irqVector = FLD_SET_DRF(_DPCD, _DEVICE_SERVICE_IRQ_VECTOR_ESI1, + _PANEL_REPLAY_ERROR_STATUS, _YES, irqVector); + bus.write(NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_ESI1, &irqVector, + sizeof irqVector); + } + virtual bool getLinkStatusChanged() { return interrupts.linkStatusChanged; @@ -1727,6 +1781,9 @@ struct DPCDHALImpl : DPCDHAL interrupts.downRepMsgRdy = FLD_TEST_DRF(_DPCD, _DEVICE_SERVICE_IRQ_VECTOR_ESI0, _DOWN_REP_MSG_RDY, _YES, buffer[3]); interrupts.upReqMsgRdy = FLD_TEST_DRF(_DPCD, _DEVICE_SERVICE_IRQ_VECTOR_ESI0, _UP_REQ_MSG_RDY, _YES, buffer[3]); + interrupts.prErrorStatus = FLD_TEST_DRF(_DPCD, + _DEVICE_SERVICE_IRQ_VECTOR_ESI1, _PANEL_REPLAY_ERROR_STATUS, _YES, buffer[4]); + interrupts.rxCapChanged = FLD_TEST_DRF(_DPCD, _LINK_SERVICE_IRQ_VECTOR_ESI0, _RX_CAP_CHANGED, _YES, buffer[5]); interrupts.linkStatusChanged = FLD_TEST_DRF(_DPCD, _LINK_SERVICE_IRQ_VECTOR_ESI0, _LINK_STATUS_CHANGED, _YES, buffer[5]); interrupts.streamStatusChanged = FLD_TEST_DRF(_DPCD, _LINK_SERVICE_IRQ_VECTOR_ESI0, _STREAM_STATUS_CHANGED, _YES, buffer[5]); @@ -1763,6 +1820,11 @@ struct DPCDHALImpl : DPCDHAL this->clearHdmiLinkStatusChanged(); } + if (interrupts.prErrorStatus) + { + this->clearPanelReplayError(); + } + parseAutomatedTestRequest(automatedTestRequest); } @@ -3135,6 +3197,82 @@ struct DPCDHALImpl : DPCDHAL } return retVal; } + + virtual bool readPrSinkDebugInfo(panelReplaySinkDebugInfo *prDbgInfo) + { + NvU8 config = 0U; + bool bRetVal = (AuxRetry::ack == + bus.read(NV_DPCD20_PANEL_REPLAY_ERROR_STATUS, + &config, sizeof(config))); + + if (bRetVal) + { + prDbgInfo->activeFrameCrcError = + FLD_TEST_DRF(_DPCD20_PANEL_REPLAY, _ERROR_STATUS, + _ACTIVE_FRAME_CRC_ERROR, _YES, config); + prDbgInfo->rfbStorageError = + FLD_TEST_DRF(_DPCD20_PANEL_REPLAY, _ERROR_STATUS, + _RFB_STORAGE_ERROR, _YES, config); + prDbgInfo->vscSdpUncorrectableError = + FLD_TEST_DRF(_DPCD20_PANEL_REPLAY, _ERROR_STATUS, + _VSC_SDP_UNCORRECTABLE_ERROR, _YES, config); + prDbgInfo->adaptiveSyncSdpMissing = + FLD_TEST_DRF(_DPCD20_PANEL_REPLAY, _ERROR_STATUS, + _ADAPTIVE_SYNC_SDP_MISSING, _YES, config); + } + else + { + DP_LOG(("DPHAL> readPrSinkDebugInfo: Failed to read PanelReplay error status")); + return bRetVal; + } + + config = 0U; + bRetVal = (AuxRetry::ack == + bus.read(NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS, + &config, sizeof(config))); + if (bRetVal) + { + prDbgInfo->sinkPrStatus = DRF_VAL(_DPCD20, + _PANEL_REPLAY_AND_FRAME_LOCK_STATUS, _PR_STATUS, config); + + prDbgInfo->sinkFramelocked = DRF_VAL(_DPCD20, + _PANEL_REPLAY_AND_FRAME_LOCK_STATUS, _SINK_FRAME_LOCKED, config); + + prDbgInfo->sinkFrameLockedValid = + FLD_TEST_DRF(_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS, + _SINK_FRAME_LOCKED, _VALID, _YES, config); + } + else + { + DP_LOG(("DPHAL> readPanelReplayError: Failed to read PanelReplay frame lock status")); + return bRetVal; + } + + config = 0U; + bRetVal = AuxRetry::ack == + bus.read(NV_DPCD20_PANEL_REPLAY_DEBUG_LAST_VSC_SDP_CARRYING_PR_INFO, + &config, sizeof(config)); + if (bRetVal) + { + prDbgInfo->currentPrState = + FLD_TEST_DRF(_DPCD20_PANEL_REPLAY_DEBUG_LAST, + _VSC_SDP_CARRYING_PR_INFO, _STATE, _ACTIVE, config); + prDbgInfo->crcValid = + FLD_TEST_DRF(_DPCD20_PANEL_REPLAY_DEBUG_LAST, + _VSC_SDP_CARRYING_PR_INFO, _CRC_VALID, _YES, config); + prDbgInfo->suCoordinatesValid = + FLD_TEST_DRF(_DPCD20_PANEL_REPLAY_DEBUG_LAST, + _VSC_SDP_CARRYING_PR_INFO, _SU_COORDINATE_VALID, + _YES, config); + } + else + { + DP_LOG(("DPHAL> readPanelReplayError: Failed to read PanelReplay VSC SDP status")); + return bRetVal; + } + return bRetVal; + } + }; DPCDHAL * DisplayPort::MakeDPCDHAL(AuxBus * bus, Timer * timer) diff --git a/src/common/displayport/src/dp_connectorimpl.cpp b/src/common/displayport/src/dp_connectorimpl.cpp index fce498f37f..646765f6c7 100644 --- a/src/common/displayport/src/dp_connectorimpl.cpp +++ b/src/common/displayport/src/dp_connectorimpl.cpp @@ -48,6 +48,9 @@ #include "ctrl/ctrl0073/ctrl0073dp.h" #include "dp_tracing.h" +#define SET_DP_IMP_ERROR(pErrorCode, errorCode) \ + if (pErrorCode && *pErrorCode == DP_IMP_ERROR_NONE) *pErrorCode = errorCode; + using namespace DisplayPort; ConnectorImpl::ConnectorImpl(MainLink * main, AuxBus * auxBus, Timer * timer, Connector::EventSink * sink) @@ -55,6 +58,7 @@ ConnectorImpl::ConnectorImpl(MainLink * main, AuxBus * auxBus, Timer * timer, Co auxBus(auxBus), timer(timer), sink(sink), + bOuiCached(false), bIgnoreSrcOuiHandshake(false), linkPolicy(), linkGuessed(false), @@ -102,6 +106,7 @@ ConnectorImpl::ConnectorImpl(MainLink * main, AuxBus * auxBus, Timer * timer, Co LT2FecLatencyMs(0), bFECEnable(false), bDscCapBasedOnParent(false), + inTransitionHeadMask(0x0), ResStatus(this) { clearTimeslices(); @@ -707,51 +712,28 @@ void ConnectorImpl::processNewDevice(const DiscoveryManager::Device & device, newDev->applyOUIOverrides(); - if (main->isEDP()) + if (main->isEDP() && !bOuiCached) { // Save Source OUI information for eDP. hal->getOuiSource(cachedSourceOUI, &cachedSourceModelName[0], sizeof(cachedSourceModelName), cachedSourceChipRevision); + bOuiCached = true; } fireEvents(); } -void ConnectorImpl::populateAllDpConfigs() +LinkRates* ConnectorImpl::importDpLinkRates() { LinkRate linkRate; - LinkRates *pConnLinkRates; - unsigned laneCounts[] = {laneCount_1, laneCount_2, laneCount_4}; - unsigned laneSets = sizeof(laneCounts) / sizeof(laneCounts[0]); - - // - // Following sequence is to be followed for saving power by default; - // It may vary with sinks which support link rate table. - // - // Link Config MBPS - // 1*RBR 162 - // 1*HBR 270 - // 2*RBR 324 - // 1*HBR2 540 - // 2*HBR 540 - // 4*RBR 648 - // 1*HBR3 810 - // ... - // - if (numPossibleLnkCfg) - { - DP_LOG(("DP> DPCONN> Rebuild possible link rate confgiurations")); - delete[] allPossibleLinkCfgs; - numPossibleLnkCfg = 0; - } + LinkRates *pConnectorLinkRates = linkPolicy.getLinkRates(); // Attempt to configure link rate table mode if supported - pConnLinkRates = linkPolicy.getLinkRates(); if (hal->isIndexedLinkrateCapable() && - main->configureLinkRateTable(hal->getLinkRateTable(), pConnLinkRates)) + main->configureLinkRateTable(hal->getLinkRateTable(), pConnectorLinkRates)) { // Maximal link rate is limited with link rate table - hal->overrideOptimalLinkRate(pConnLinkRates->getMaxRate()); + hal->overrideOptimalLinkRate(pConnectorLinkRates->getMaxRate()); hal->setIndexedLinkrateEnabled(true); } else @@ -767,26 +749,60 @@ void ConnectorImpl::populateAllDpConfigs() linkRate = main->maxLinkRateSupported(); // Insert by order - pConnLinkRates->clear(); + pConnectorLinkRates->clear(); + if (linkRate >= RBR) - pConnLinkRates->import(linkBW_1_62Gbps); + pConnectorLinkRates->import((NvU8)linkBW_1_62Gbps); if (linkRate >= HBR) - pConnLinkRates->import(linkBW_2_70Gbps); + pConnectorLinkRates->import((NvU8)linkBW_2_70Gbps); if (linkRate >= HBR2) - pConnLinkRates->import(linkBW_5_40Gbps); + pConnectorLinkRates->import((NvU8)linkBW_5_40Gbps); if (linkRate >= HBR3) - pConnLinkRates->import(linkBW_8_10Gbps); + pConnectorLinkRates->import((NvU8)linkBW_8_10Gbps); + } + return pConnectorLinkRates; +} + +void ConnectorImpl::populateAllDpConfigs() +{ + LinkRate linkRate; + LinkRates *pConnectorLinkRates = linkPolicy.getLinkRates(); + + unsigned laneCounts[] = {laneCount_1, laneCount_2, laneCount_4}; + unsigned laneSets = sizeof(laneCounts) / sizeof(laneCounts[0]); + + // + // Following sequence is to be followed for saving power by default; + // It may vary with sinks which support link rate table. + // + // Link Config MBPS + // 1*RBR 162 + // 1*HBR 270 + // 2*RBR 324 + // 1*HBR2 540 + // 2*HBR 540 + // 4*RBR 648 + // 1*HBR3 810 + // ... + // + if (numPossibleLnkCfg) + { + DP_LOG(("DP> DPCONN> Rebuild possible link rate confgiurations")); + delete[] allPossibleLinkCfgs; + numPossibleLnkCfg = 0; } - numPossibleLnkCfg = laneSets * pConnLinkRates->getNumLinkRates(); + importDpLinkRates(); + + numPossibleLnkCfg = laneSets * pConnectorLinkRates->getNumLinkRates(); if (numPossibleLnkCfg == 0) { DP_LOG(("DPCONN> %s: lane count %d or link rates %d!", - pConnLinkRates->getNumLinkRates(), laneSets, __FUNCTION__)); - DP_ASSERT(0 && "Invalid lane count %d or link rates %d!"); + __FUNCTION__, pConnectorLinkRates->getNumLinkRates(), laneSets)); + DP_ASSERT(0 && "Invalid lane count or link rates!"); return; } @@ -801,14 +817,14 @@ void ConnectorImpl::populateAllDpConfigs() } // Populate all possible link configuration - linkRate = pConnLinkRates->getMaxRate(); - for (unsigned i = 0; i < pConnLinkRates->getNumLinkRates(); i++) + linkRate = pConnectorLinkRates->getMaxRate(); + for (unsigned i = 0; i < pConnectorLinkRates->getNumLinkRates(); i++) { for (unsigned j = 0; j < laneSets; j++) { allPossibleLinkCfgs[i * laneSets + j].setLaneRate(linkRate, laneCounts[j]); } - linkRate = pConnLinkRates->getLowerRate(linkRate); + linkRate = pConnectorLinkRates->getLowerRate(linkRate); } // Sort link configurations per bandwidth from low to high @@ -1005,7 +1021,7 @@ LinkConfiguration ConnectorImpl::getActiveLinkConfig() return activeLinkConfig; } -void ConnectorImpl::beginCompoundQuery() +void ConnectorImpl::beginCompoundQuery(const bool bForceEnableFEC) { if (linkGuessed && (main->getSorIndex() != DP_INVALID_SOR_INDEX)) { @@ -1017,6 +1033,7 @@ void ConnectorImpl::beginCompoundQuery() compoundQueryCount = 0; compoundQueryResult = true; compoundQueryLocalLinkPBN = 0; + compoundQueryForceEnableFEC = bForceEnableFEC; for (Device * i = enumDevices(0); i; i=enumDevices(i)) { @@ -1075,6 +1092,37 @@ void ConnectorImpl::beginCompoundQuery() } } +static DP_IMP_ERROR translatePpsErrorToDpImpError(NVT_STATUS ppsErrorCode) +{ + switch (ppsErrorCode) + { + case NVT_STATUS_COLOR_FORMAT_NOT_SUPPORTED: + return DP_IMP_ERROR_PPS_COLOR_FORMAT_NOT_SUPPORTED; + case NVT_STATUS_INVALID_HBLANK: + return DP_IMP_ERROR_PPS_INVALID_HBLANK; + case NVT_STATUS_INVALID_BPC: + return DP_IMP_ERROR_PPS_INVALID_BPC; + case NVT_STATUS_MAX_LINE_BUFFER_ERROR: + return DP_IMP_ERROR_PPS_MAX_LINE_BUFFER_ERROR; + case NVT_STATUS_OVERALL_THROUGHPUT_ERROR: + return DP_IMP_ERROR_PPS_OVERALL_THROUGHPUT_ERROR; + case NVT_STATUS_DSC_SLICE_ERROR: + return DP_IMP_ERROR_PPS_DSC_SLICE_ERROR; + case NVT_STATUS_PPS_SLICE_COUNT_ERROR: + return DP_IMP_ERROR_PPS_PPS_SLICE_COUNT_ERROR; + case NVT_STATUS_PPS_SLICE_HEIGHT_ERROR: + return DP_IMP_ERROR_PPS_PPS_SLICE_HEIGHT_ERROR; + case NVT_STATUS_PPS_SLICE_WIDTH_ERROR: + return DP_IMP_ERROR_PPS_PPS_SLICE_WIDTH_ERROR; + case NVT_STATUS_INVALID_PEAK_THROUGHPUT: + return DP_IMP_ERROR_PPS_INVALID_PEAK_THROUGHPUT; + case NVT_STATUS_MIN_SLICE_COUNT_ERROR: + return DP_IMP_ERROR_PPS_MIN_SLICE_COUNT_ERROR; + default: + return DP_IMP_ERROR_PPS_GENERIC_ERROR; + } +} + // // This call will be deprecated as soon as all clients move to the new API // @@ -1087,23 +1135,25 @@ bool ConnectorImpl::compoundQueryAttach(Group * target, unsigned rasterHeight, unsigned rasterBlankStartX, unsigned rasterBlankEndX, - unsigned depth) + unsigned depth, + DP_IMP_ERROR *pErrorCode) { ModesetInfo modesetInfo(twoChannelAudioHz, eightChannelAudioHz, pixelClockHz, rasterWidth, rasterHeight, (rasterBlankStartX - rasterBlankEndX), 0/*surfaceHeight*/, depth, rasterBlankStartX, rasterBlankEndX); DpModesetParams modesetParams(0, modesetInfo); - return compoundQueryAttach(target, modesetParams); + return compoundQueryAttach(target, modesetParams, NULL, pErrorCode); } bool ConnectorImpl::compoundQueryAttach(Group * target, const DpModesetParams &modesetParams, // Modeset info - DscParams *pDscParams) // DSC parameters + DscParams *pDscParams, // DSC parameters + DP_IMP_ERROR *pErrorCode) { - DP_ASSERT( compoundQueryActive ); - ModesetInfo localModesetInfo = modesetParams.modesetInfo; - NVT_STATUS result; + DP_ASSERT(compoundQueryActive); + if (pErrorCode) + *pErrorCode = DP_IMP_ERROR_NONE; compoundQueryCount++; @@ -1111,6 +1161,7 @@ bool ConnectorImpl::compoundQueryAttach(Group * target, { DP_ASSERT(!"DP-CONN> Params with zero value passed to query!"); compoundQueryResult = false; + SET_DP_IMP_ERROR(pErrorCode, DP_IMP_ERROR_ZERO_VALUE_PARAMS) return false; } @@ -1124,73 +1175,619 @@ bool ConnectorImpl::compoundQueryAttach(Group * target, && !(bEnableAudioBeyond48K)) { compoundQueryResult = false; + SET_DP_IMP_ERROR(pErrorCode, DP_IMP_ERROR_AUDIO_BEYOND_48K) + return false; + } + + if (linkUseMultistream()) + { + compoundQueryResult = compoundQueryAttachMST(target, modesetParams, + pDscParams, pErrorCode); + } + else // SingleStream case + { + compoundQueryResult = compoundQueryAttachSST(target, modesetParams, + pDscParams, pErrorCode); + } + + return compoundQueryResult; +} + +bool ConnectorImpl::dpLinkIsModePossible(const DpLinkIsModePossibleParams ¶ms) +{ + bool bResult; + NvU32 numNonDscStreams; + bool bEnableFEC = false; + +reRunCompoundQuery: + bResult = true; + numNonDscStreams = 0; + + for (NvU32 i = 0; i < NV_MAX_HEADS; i++) + { + if (params.head[i].pDscParams != NULL) + params.head[i].pDscParams->bEnableDsc = false; + + if (params.head[i].pErrorStatus != NULL) + *params.head[i].pErrorStatus = DP_IMP_ERROR_NONE; + } + + this->beginCompoundQuery(bEnableFEC /* bForceEnableFEC */); + + for (NvU32 i = 0; i < NV_MAX_HEADS; i++) + { + if (params.head[i].pTarget == NULL) + continue; + + DP_ASSERT(params.head[i].pModesetParams->headIndex == i); + + bResult = this->compoundQueryAttach(params.head[i].pTarget, + *params.head[i].pModesetParams, + params.head[i].pDscParams, + params.head[i].pErrorStatus); + if (!bResult) + break; + + if ((params.head[i].pDscParams == NULL) || + !params.head[i].pDscParams->bEnableDsc) + { + numNonDscStreams++; + continue; + } + + // + // When DSC is enabled, FEC also need to be enabled. The previously + // attached non-dsc streams needs to consider 3% FEC overhead, + // therefore terminate existing compound query, force enable FEC and + // re-run the compound query. + // + if ((numNonDscStreams > 0) && !bEnableFEC) + { + this->endCompoundQuery(); + bEnableFEC = true; + goto reRunCompoundQuery; + } + + bEnableFEC = true; + } + + if (!this->endCompoundQuery()) + bResult = false; + + return bResult; +} + +bool ConnectorImpl::compoundQueryAttachMST(Group * target, + const DpModesetParams &modesetParams, // Modeset info + DscParams *pDscParams, // DSC parameters + DP_IMP_ERROR *pErrorCode) +{ + CompoundQueryAttachMSTInfo localInfo; + NvBool result = true; + + localInfo.localModesetInfo = modesetParams.modesetInfo; + if (this->preferredLinkConfig.isValid()) + localInfo.lc = preferredLinkConfig; + else + localInfo.lc = highestAssessedLC; + + if (compoundQueryForceEnableFEC) { + localInfo.lc.enableFEC(isFECCapable()); + } + + if (compoundQueryAttachMSTIsDscPossible(target, modesetParams, pDscParams)) + { + result = compoundQueryAttachMSTDsc(target, modesetParams, &localInfo, + pDscParams, pErrorCode); + if (!result) + { + return false; + } + + if (!pDscParams->bEnableDsc) + { + DP_LOG(("CompoundQueryAttach failed with DSC, will try non-DSC path")); + } + } + + return compoundQueryAttachMSTGeneric(target, modesetParams, &localInfo, + pDscParams, pErrorCode); +} + +bool ConnectorImpl::compoundQueryAttachMSTIsDscPossible +( + Group * target, + const DpModesetParams &modesetParams, // Modeset info + DscParams *pDscParams // DSC parameters +) +{ + Device * newDev = target->enumDevices(0); + DeviceImpl * dev = (DeviceImpl *)newDev; + bool bFecCapable = false; + bool bGpuDscSupported; + main->getDscCaps(&bGpuDscSupported); + + if (pDscParams && (pDscParams->forceDsc != DSC_FORCE_DISABLE)) + { + if (dev && dev->isDSCPossible()) + { + if (dev->devDoingDscDecompression != dev) + { + // + // If DSC decoding is going to happen at sink's parent then + // we have to make sure the path from source to sink's parent + // is fec is capable. + // Refer DP 1.4 Spec 5.4.5 + // + if(dev->address.size() == 2) + { + // + // if there is only one branch between source and sink then branch + // should be directly connected to source (sst-case) and dpcd cap + // should already be available. + // + bFecCapable = dev->parent->isFECSupported(); + } + else + { + // + // If there are multiple branches in the path, we have to check + // fecCapability field in epr reply to sink's parent's parent. + // Epr reply for each branch should already be updated with inferLeafLink. + // fecCapability field being true here means up to sink's parent, + // which is "downstream end of path" for sink's parent's parent, + // is fec capable. + // Refer DP 1.4 Spec 2.11.9.4.1 + // + bFecCapable = dev->parent->parent->isFECSupported(); + } + } + else + { + bFecCapable = dev->isFECSupported(); + } + } + } + else + { + return false; + } + // Make sure panel/it's parent & GPU supports DSC and the whole path supports FEC + if (bGpuDscSupported && // If GPU supports DSC + this->isFECSupported() && // If GPU supports FEC + pDscParams && // If client sent DSC info + pDscParams->bCheckWithDsc && // If client wants to check with DSC + (dev && dev->devDoingDscDecompression) && // Either device or it's parent supports DSC + bFecCapable && // If path up to dsc decoding device supports FEC + (modesetParams.modesetInfo.bitsPerComponent != 6)) // DSC doesn't support bpc = 6 + { + return true; + } + else + { return false; } +} + +bool ConnectorImpl::compoundQueryAttachMSTDsc(Group * target, + const DpModesetParams &modesetParams, // Modeset info + CompoundQueryAttachMSTInfo * localInfo, + DscParams *pDscParams, // DSC parameters + DP_IMP_ERROR *pErrorCode) +{ + NVT_STATUS result; + + Device * newDev = target->enumDevices(0); + DeviceImpl * dev = (DeviceImpl *)newDev; bool bGpuDscSupported; main->getDscCaps(&bGpuDscSupported); - if (linkUseMultistream()) + DSC_INFO dscInfo; + MODESET_INFO modesetInfoDSC; + WAR_DATA warData; + NvU64 availableBandwidthBitsPerSecond = 0; + unsigned PPS[DSC_MAX_PPS_SIZE_DWORD]; + unsigned bitsPerPixelX16 = 0; + bool bDscBppForced = false; + + if (!pDscParams->bitsPerPixelX16) { - LinkConfiguration lc; - if (this->preferredLinkConfig.isValid()) - lc = preferredLinkConfig; - else - lc = highestAssessedLC; + // + // For now, we will keep a pre defined value for bitsPerPixel for MST = 10 + // bitsPerPixelX16 = 160 + // + pDscParams->bitsPerPixelX16 = PREDEFINED_DSC_MST_BPPX16; + } + else + { + bDscBppForced = true; + } - if (pDscParams && (pDscParams->forceDsc != DSC_FORCE_DISABLE)) - { - bool bFecCapable = false; + bitsPerPixelX16 = pDscParams->bitsPerPixelX16; + + if (!this->preferredLinkConfig.isValid()) + { + localInfo->lc.enableFEC(true); + } - Device * newDev = target->enumDevices(0); - DeviceImpl * dev = (DeviceImpl *)newDev; + dpMemZero(PPS, sizeof(unsigned) * DSC_MAX_PPS_SIZE_DWORD); + dpMemZero(&dscInfo, sizeof(DSC_INFO)); - if (dev && dev->isDSCPossible()) + // Populate DSC related info for PPS calculations + populateDscCaps(&dscInfo, dev->devDoingDscDecompression, pDscParams->forcedParams); + + // populate modeset related info for PPS calculations + populateDscModesetInfo(&modesetInfoDSC, &modesetParams); + + // checking for DSC v1.1 and YUV combination + if ((dscInfo.sinkCaps.algorithmRevision.versionMajor == 1) && + (dscInfo.sinkCaps.algorithmRevision.versionMinor == 1) && + (modesetParams.colorFormat == dpColorFormat_YCbCr444 )) + { + DP_LOG(("WARNING: DSC v1.2 or higher is recommended for using YUV444")); + DP_LOG(("Current version is 1.1")); + } + + if ((dev->devDoingDscDecompression == dev) && dev->parent) + { + if (dev->parent->bDscPassThroughColorFormatWar) + { + // + // Bug 3692417 + // Color format should only depend on device doing DSC decompression when DSC is enabled according to DP Spec. + // But when Synaptics VMM5320 is the parent of the device doing DSC decompression, if a certain color + // format is not supported by Synaptics Virtual Peer Device decoder(parent), even though it is pass through mode + // and panel supports the color format, panel cannot light up. Once Synaptics fixes this issue, we will modify + // the WAR to be applied only before the firmware version that fixes it. + // + if ((modesetParams.colorFormat == dpColorFormat_RGB && !dev->parent->dscCaps.dscDecoderColorFormatCaps.bRgb) || + (modesetParams.colorFormat == dpColorFormat_YCbCr444 && !dev->parent->dscCaps.dscDecoderColorFormatCaps.bYCbCr444) || + (modesetParams.colorFormat == dpColorFormat_YCbCr422 && !dev->parent->dscCaps.dscDecoderColorFormatCaps.bYCbCrSimple422)) { - if (dev->devDoingDscDecompression != dev) + if ((pDscParams->forceDsc == DSC_FORCE_ENABLE) || + (modesetParams.modesetInfo.mode == DSC_DUAL)) { // - // If DSC decoding is going to happen at sink's parent then - // we have to make sure the path from source to sink's parent - // is fec is capable. - // Refer DP 1.4 Spec 5.4.5 + // If DSC is force enabled or DSC_DUAL mode is requested, + // then return failure here // - if(dev->address.size() == 2) + compoundQueryResult = false; + SET_DP_IMP_ERROR(pErrorCode, DP_IMP_ERROR_DSC_SYNAPTICS_COLOR_FORMAT) + pDscParams->bEnableDsc = false; + return false; + } + else + { + // We should check if mode is possible without DSC. + pDscParams->bEnableDsc = false; + if (!compoundQueryForceEnableFEC) { - // - // if there is only one branch between source and sink then branch - // should be directly connected to source (sst-case) and dpcd cap - // should already be available. - // - bFecCapable = dev->parent->isFECSupported(); + localInfo->lc.enableFEC(false); } - else + return true; + } + } + } + } + + availableBandwidthBitsPerSecond = localInfo->lc.minRate * 8 * localInfo->lc.lanes; + + warData.dpData.linkRateHz = localInfo->lc.peakRate; + warData.dpData.laneCount = localInfo->lc.lanes; + warData.dpData.dpMode = DSC_DP_MST; + warData.dpData.hBlank = modesetParams.modesetInfo.rasterWidth - modesetParams.modesetInfo.surfaceWidth; + warData.connectorType = DSC_DP; + + DSC_GENERATE_PPS_OPAQUE_WORKAREA *pScratchBuffer = nullptr; + pScratchBuffer = (DSC_GENERATE_PPS_OPAQUE_WORKAREA*) dpMalloc(sizeof(DSC_GENERATE_PPS_OPAQUE_WORKAREA)); + + result = DSC_GeneratePPS(&dscInfo, &modesetInfoDSC, + &warData, availableBandwidthBitsPerSecond, + (NvU32*)(PPS), (NvU32*)(&bitsPerPixelX16), + pScratchBuffer); + + // Try max dsc compression bpp = 8 once to check if that can support that mode. + if (result != NVT_STATUS_SUCCESS && !bDscBppForced) + { + pDscParams->bitsPerPixelX16 = MAX_DSC_COMPRESSION_BPPX16; + + bitsPerPixelX16 = pDscParams->bitsPerPixelX16; + + result = DSC_GeneratePPS(&dscInfo, &modesetInfoDSC, + &warData, availableBandwidthBitsPerSecond, + (NvU32*)(PPS), (NvU32*)(&bitsPerPixelX16), + pScratchBuffer); + } + + if (pScratchBuffer) + { + dpFree(pScratchBuffer); + pScratchBuffer = nullptr; + } + + if (result != NVT_STATUS_SUCCESS) + { + // + // If generating PPS failed + // AND + // (DSC is force enabled + // OR + // the requested DSC mode = DUAL) + //then + // return failure here + // Else + // we will check if non DSC path is possible. + // + // If dsc mode = DUAL failed to generate PPS and if we pursue + // non DSC path, DD will still follow 2Head1OR modeset path with + // DSC disabled, eventually leading to HW hang. Bug 3632901 + // + if ((pDscParams->forceDsc == DSC_FORCE_ENABLE) || + (modesetParams.modesetInfo.mode == DSC_DUAL)) + { + compoundQueryResult = false; + SET_DP_IMP_ERROR(pErrorCode, translatePpsErrorToDpImpError(result)) + pDscParams->bEnableDsc = false; + return false; + } + else + { + // If PPS calculation failed then try without DSC + pDscParams->bEnableDsc = false; + if (!compoundQueryForceEnableFEC) + { + localInfo->lc.enableFEC(false); + } + return true; + } + } + else + { + pDscParams->bEnableDsc = true; + compoundQueryResult = true; + localInfo->localModesetInfo.bEnableDsc = true; + localInfo->localModesetInfo.depth = bitsPerPixelX16; + + if (dev->peerDevice == Dongle && dev->connectorType == connectorHDMI) + { + // + // For DP2HDMI PCON, if FRL BW is available in detailed caps, + // we need to check if we have enough BW for the stream on FRL link. + // + if (dev->pconCaps.maxHdmiLinkBandwidthGbps != 0) + { + NvU64 requiredBW = (NvU64)(modesetParams.modesetInfo.pixelClockHz * modesetParams.modesetInfo.depth); + NvU64 availableBw = (NvU64)(dev->pconCaps.maxHdmiLinkBandwidthGbps * 1000000000); + if (requiredBW > availableBw) + { + compoundQueryResult = false; + SET_DP_IMP_ERROR(pErrorCode, DP_IMP_ERROR_DSC_PCON_FRL_BANDWIDTH) + pDscParams->bEnableDsc = false; + return false; + } + } + // + // If DP2HDMI PCON does not support FRL, but advertises TMDS + // Character clock rate on detailed caps, we need to honor that. + // + else if (dev->pconCaps.maxTmdsClkRate != 0) + { + NvU64 maxTmdsClkRateU64 = (NvU64)(dev->pconCaps.maxTmdsClkRate); + NvU64 requireBw = (NvU64)(modesetParams.modesetInfo.pixelClockHz * modesetParams.modesetInfo.depth); + if (modesetParams.colorFormat == dpColorFormat_YCbCr420) + { + if (maxTmdsClkRateU64 < ((requireBw/24)/2)) { - // - // If there are multiple branches in the path, we have to check - // fecCapability field in epr reply to sink's parent's parent. - // Epr reply for each branch should already be updated with inferLeafLink. - // fecCapability field being true here means up to sink's parent, - // which is "downstream end of path" for sink's parent's parent, - // is fec capable. - // Refer DP 1.4 Spec 2.11.9.4.1 - // - bFecCapable = dev->parent->parent->isFECSupported(); + compoundQueryResult = false; + SET_DP_IMP_ERROR(pErrorCode, DP_IMP_ERROR_DSC_PCON_HDMI2_BANDWIDTH) + return false; } } else { - bFecCapable = dev->isFECSupported(); + if (maxTmdsClkRateU64 < (requireBw/24)) + { + compoundQueryResult = false; + SET_DP_IMP_ERROR(pErrorCode, DP_IMP_ERROR_DSC_PCON_HDMI2_BANDWIDTH) + return false; + } } } + } + else if (dev->devDoingDscDecompression != dev) + { + // + // Device's parent is doing DSC decompression so we need to check + // if device's parent can send uncompressed stream to Sink. + // + unsigned mode_pbn; + + mode_pbn = pbnForMode(modesetParams.modesetInfo); + + // + // As Device's Parent is doing DSC decompression, this is leaf device and + // complete available bandwidth at this node is available for requested mode. + // + if (mode_pbn > dev->bandwidth.enum_path.total) + { + compoundQueryResult = false; + SET_DP_IMP_ERROR(pErrorCode, DP_IMP_ERROR_DSC_LAST_HOP_BANDWIDTH) + pDscParams->bEnableDsc = false; + return false; + } + } - // Make sure panel/it's parent & GPU supports DSC and the whole path supports FEC - if (bGpuDscSupported && // If GPU supports DSC + if (pDscParams->pDscOutParams != NULL) + { + // + // If requested then DP Library is supposed to return if mode is + // possible with DSC and calculated PPS and bits per pixel. + // + dpMemCopy(pDscParams->pDscOutParams->PPS, PPS, sizeof(unsigned) * DSC_MAX_PPS_SIZE_DWORD); + pDscParams->bitsPerPixelX16 = bitsPerPixelX16; + } + else + { + // + // Client only wants to know if mode is possible or not but doesn't + // need all calculated PPS parameters in case DSC is required. Do nothing. + // + } + } + return true; +} + +bool ConnectorImpl::compoundQueryAttachMSTGeneric(Group * target, + const DpModesetParams &modesetParams, // Modeset info + CompoundQueryAttachMSTInfo * localInfo, + DscParams *pDscParams, // DSC parameters + DP_IMP_ERROR *pErrorCode) +{ + // I. Evaluate use of local link bandwidth + + // Calculate the PBN required + unsigned base_pbn, slots, slots_pbn; + localInfo->lc.pbnRequired(localInfo->localModesetInfo, base_pbn, slots, slots_pbn); + + // Accumulate the amount of PBN rounded up to nearest timeslot + compoundQueryLocalLinkPBN += slots_pbn; + if (compoundQueryLocalLinkPBN > localInfo->lc.pbnTotal()) + { + compoundQueryResult = false; + SET_DP_IMP_ERROR(pErrorCode, DP_IMP_ERROR_INSUFFICIENT_BANDWIDTH) + } + + // Verify the min blanking, etc + Watermark dpinfo; + + if (this->isFECSupported()) + { + if (!isModePossibleMSTWithFEC(localInfo->lc, localInfo->localModesetInfo, &dpinfo)) + { + compoundQueryResult = false; + SET_DP_IMP_ERROR(pErrorCode, DP_IMP_ERROR_WATERMARK_BLANKING) + } + } + else + { + if (!isModePossibleMST(localInfo->lc, localInfo->localModesetInfo, &dpinfo)) + { + compoundQueryResult = false; + SET_DP_IMP_ERROR(pErrorCode, DP_IMP_ERROR_WATERMARK_BLANKING) + } + } + + for(Device * d = target->enumDevices(0); d; d = target->enumDevices(d)) + { + DeviceImpl * i = (DeviceImpl *)d; + + // Allocate bandwidth for the entire path to the root + // NOTE: Above we're already handle the local link + DeviceImpl * tail = i; + while (tail && tail->getParent()) + { + // Have we already accounted for this stream? + if (!(tail->bandwidth.compound_query_state.bandwidthAllocatedForIndex & (1 << compoundQueryCount))) + { + tail->bandwidth.compound_query_state.bandwidthAllocatedForIndex |= (1 << compoundQueryCount); + + LinkConfiguration * linkConfig = tail->inferLeafLink(NULL); + tail->bandwidth.compound_query_state.timeslots_used_by_query += linkConfig->slotsForPBN(base_pbn); + + if ( tail->bandwidth.compound_query_state.timeslots_used_by_query > tail->bandwidth.compound_query_state.totalTimeSlots) + { + compoundQueryResult = false; + SET_DP_IMP_ERROR(pErrorCode, DP_IMP_ERROR_INSUFFICIENT_BANDWIDTH) + } + } + tail = (DeviceImpl*)tail->getParent(); + } + } + return compoundQueryResult; +} +bool ConnectorImpl::compoundQueryAttachSST(Group * target, + const DpModesetParams &modesetParams, // Modeset info + DscParams *pDscParams, // DSC parameters + DP_IMP_ERROR *pErrorCode) +{ + ModesetInfo localModesetInfo = modesetParams.modesetInfo; + bool bGpuDscSupported; + main->getDscCaps(&bGpuDscSupported); + + DeviceImpl * nativeDev = findDeviceInList(Address()); + + if (compoundQueryCount != 1) + { + compoundQueryResult = false; + return false; + } + + if (nativeDev && (nativeDev->connectorType == connectorHDMI)) + { + if (modesetParams.colorFormat == dpColorFormat_YCbCr420) + { + if ((nativeDev->maxTmdsClkRate) && + (nativeDev->maxTmdsClkRate < + ((modesetParams.modesetInfo.pixelClockHz * modesetParams.modesetInfo.depth /24)/2))) + { + compoundQueryResult = false; + SET_DP_IMP_ERROR(pErrorCode, DP_IMP_ERROR_DSC_PCON_HDMI2_BANDWIDTH) + return false; + } + } + else + { + if ((nativeDev->maxTmdsClkRate) && + (nativeDev->maxTmdsClkRate < + (modesetParams.modesetInfo.pixelClockHz * modesetParams.modesetInfo.depth /24))) + { + compoundQueryResult = false; + SET_DP_IMP_ERROR(pErrorCode, DP_IMP_ERROR_DSC_PCON_HDMI2_BANDWIDTH) + return false; + } + } + } + + LinkConfiguration lc = highestAssessedLC; + + // check if there is a special request from the client + if (this->preferredLinkConfig.isValid()) + { + lc = preferredLinkConfig; + } + else + { + // + // Always check for DP IMP without FEC overhead first before + // trying with DSC/FEC + // + lc.enableFEC(false); + } + + // If do not found valid native device the force lagacy DP IMP + if (!nativeDev) + { + compoundQueryResult = this->willLinkSupportModeSST(lc, modesetParams.modesetInfo); + if (!compoundQueryResult) + { + SET_DP_IMP_ERROR(pErrorCode, DP_IMP_ERROR_WATERMARK_BLANKING) + } + } + else if ((pDscParams && (pDscParams->forceDsc == DSC_FORCE_ENABLE)) || // DD has forced DSC Enable + (modesetParams.modesetInfo.mode == DSC_DUAL) || // DD decided to use 2 Head 1 OR mode + (!this->willLinkSupportModeSST(lc, modesetParams.modesetInfo))) // Mode is not possible without DSC + { + // If DP IMP fails without DSC or client requested to force DSC + if (pDscParams && pDscParams->forceDsc != DSC_FORCE_DISABLE) + { + // Check if panel and GPU both supports DSC or not. Also check if panel supports FEC + if (bGpuDscSupported && // if GPU supports DSC this->isFECSupported() && // If GPU supports FEC - pDscParams && // If client sent DSC info - pDscParams->bCheckWithDsc && // If client wants to check with DSC - (dev && dev->devDoingDscDecompression) && // Either device or it's parent supports DSC - bFecCapable && // If path up to dsc decoding device supports FEC + pDscParams && // if client sent DSC info + pDscParams->bCheckWithDsc && // if client wants to check with DSC + nativeDev->isDSCPossible() && // if device supports DSC decompression + (nativeDev->isFECSupported() || main->isEDP()) && // if device supports FEC decoding or is an DSC capable eDP panel which doesn't support FEC (modesetParams.modesetInfo.bitsPerComponent != 6)) // DSC doesn't support bpc = 6 { DSC_INFO dscInfo; @@ -1198,25 +1795,9 @@ bool ConnectorImpl::compoundQueryAttach(Group * target, WAR_DATA warData; NvU64 availableBandwidthBitsPerSecond = 0; unsigned PPS[DSC_MAX_PPS_SIZE_DWORD]; - unsigned bitsPerPixelX16 = 0; - bool bDscBppForced = false; - - if (!pDscParams->bitsPerPixelX16) - { - // - // For now, we will keep a pre defined value for bitsPerPixel for MST = 10 - // bitsPerPixelX16 = 160 - // - pDscParams->bitsPerPixelX16 = PREDEFINED_DSC_MST_BPPX16; - } - else - { - bDscBppForced = true; - } - - bitsPerPixelX16 = pDscParams->bitsPerPixelX16; + unsigned bitsPerPixelX16 = pDscParams->bitsPerPixelX16; - if (!this->preferredLinkConfig.isValid()) + if (!this->preferredLinkConfig.isValid() && nativeDev->isFECSupported()) { lc.enableFEC(true); } @@ -1225,477 +1806,128 @@ bool ConnectorImpl::compoundQueryAttach(Group * target, dpMemZero(&dscInfo, sizeof(DSC_INFO)); // Populate DSC related info for PPS calculations - populateDscCaps(&dscInfo, dev->devDoingDscDecompression, pDscParams->forcedParams); + populateDscCaps(&dscInfo, nativeDev->devDoingDscDecompression, pDscParams->forcedParams); - // populate modeset related info for PPS calculations + // Populate modeset related info for PPS calculations populateDscModesetInfo(&modesetInfoDSC, &modesetParams); // checking for DSC v1.1 and YUV combination if ( (dscInfo.sinkCaps.algorithmRevision.versionMajor == 1) && - (dscInfo.sinkCaps.algorithmRevision.versionMinor == 1) && - (modesetParams.colorFormat == dpColorFormat_YCbCr444 )) + (dscInfo.sinkCaps.algorithmRevision.versionMinor == 1) && + (modesetParams.colorFormat == dpColorFormat_YCbCr444 )) { DP_LOG(("WARNING: DSC v1.2 or higher is recommended for using YUV444")); DP_LOG(("Current version is 1.1")); } - if ((dev->devDoingDscDecompression == dev) && dev->parent) - { - if (dev->parent->bDscPassThroughColorFormatWar) - { - // - // Bug 3692417 - // Color format should only depend on device doing DSC decompression when DSC is enabled according to DP Spec. - // But when Synaptics VMM5320 is the parent of the device doing DSC decompression, if a certain color - // format is not supported by Synaptics Virtual Peer Device decoder(parent), even though it is pass through mode - // and panel supports the color format, panel cannot light up. Once Synaptics fixes this issue, we will modify - // the WAR to be applied only before the firmware version that fixes it. - // - if ((modesetParams.colorFormat == dpColorFormat_RGB && !dev->parent->dscCaps.dscDecoderColorFormatCaps.bRgb) || - (modesetParams.colorFormat == dpColorFormat_YCbCr444 && !dev->parent->dscCaps.dscDecoderColorFormatCaps.bYCbCr444) || - (modesetParams.colorFormat == dpColorFormat_YCbCr422 && !dev->parent->dscCaps.dscDecoderColorFormatCaps.bYCbCrSimple422)) - { - if ((pDscParams->forceDsc == DSC_FORCE_ENABLE) || - (modesetParams.modesetInfo.mode == DSC_DUAL)) - { - // - // If DSC is force enabled or DSC_DUAL mode is requested, - // then return failure here - // - compoundQueryResult = false; - pDscParams->bEnableDsc = false; - return false; - } - else - { - // We should check if mode is possible without DSC. - pDscParams->bEnableDsc = false; - lc.enableFEC(false); - goto nonDscDpIMP; - } - } - } - } - availableBandwidthBitsPerSecond = lc.minRate * 8 * lc.lanes; warData.dpData.linkRateHz = lc.peakRate; warData.dpData.laneCount = lc.lanes; - warData.dpData.dpMode = DSC_DP_MST; warData.dpData.hBlank = modesetParams.modesetInfo.rasterWidth - modesetParams.modesetInfo.surfaceWidth; + warData.dpData.dpMode = DSC_DP_SST; warData.connectorType = DSC_DP; DSC_GENERATE_PPS_OPAQUE_WORKAREA *pScratchBuffer = nullptr; pScratchBuffer = (DSC_GENERATE_PPS_OPAQUE_WORKAREA*) dpMalloc(sizeof(DSC_GENERATE_PPS_OPAQUE_WORKAREA)); - result = DSC_GeneratePPS(&dscInfo, &modesetInfoDSC, - &warData, availableBandwidthBitsPerSecond, - (NvU32*)(PPS), - (NvU32*)(&bitsPerPixelX16), pScratchBuffer); - - // Try max dsc compression bpp = 8 once to check if that can support that mode. - if (result != NVT_STATUS_SUCCESS && !bDscBppForced) - { - pDscParams->bitsPerPixelX16 = MAX_DSC_COMPRESSION_BPPX16; - - bitsPerPixelX16 = pDscParams->bitsPerPixelX16; - - result = DSC_GeneratePPS(&dscInfo, &modesetInfoDSC, - &warData, availableBandwidthBitsPerSecond, - (NvU32*)(PPS), - (NvU32*)(&bitsPerPixelX16), pScratchBuffer); - } - + NVT_STATUS ppsStatus = DSC_GeneratePPS(&dscInfo, &modesetInfoDSC, + &warData, availableBandwidthBitsPerSecond, + (NvU32*)(PPS), + (NvU32*)(&bitsPerPixelX16), + pScratchBuffer); if (pScratchBuffer) { dpFree(pScratchBuffer); pScratchBuffer = nullptr; } - if (result != NVT_STATUS_SUCCESS) + if (ppsStatus != NVT_STATUS_SUCCESS) { - // - // If generating PPS failed - // AND - // (DSC is force enabled - // OR - // the requested DSC mode = DUAL) - //then - // return failure here - // Else - // we will check if non DSC path is possible. - // - // If dsc mode = DUAL failed to generate PPS and if we pursue - // non DSC path, DD will still follow 2Head1OR modeset path with - // DSC disabled, eventually leading to HW hang. Bug 3632901 - // - if ((pDscParams->forceDsc == DSC_FORCE_ENABLE) || - (modesetParams.modesetInfo.mode == DSC_DUAL)) - { - compoundQueryResult = false; - pDscParams->bEnableDsc = false; - return false; - } - else - { - // If PPS calculation failed then try without DSC - pDscParams->bEnableDsc = false; - lc.enableFEC(false); - goto nonDscDpIMP; - } + compoundQueryResult = false; + SET_DP_IMP_ERROR(pErrorCode, translatePpsErrorToDpImpError(ppsStatus)) + pDscParams->bEnableDsc = false; } else { - pDscParams->bEnableDsc = true; - compoundQueryResult = true; localModesetInfo.bEnableDsc = true; localModesetInfo.depth = bitsPerPixelX16; + LinkConfiguration lowestSelected; + bool bIsModeSupported = false; - if (dev->peerDevice == Dongle && dev->connectorType == connectorHDMI) - { - // - // For DP2HDMI PCON, if FRL BW is available in detailed caps, - // we need to check if we have enough BW for the stream on FRL link. - // - if (dev->pconCaps.maxHdmiLinkBandwidthGbps != 0) - { - NvU64 requiredBW = (NvU64)(modesetParams.modesetInfo.pixelClockHz * modesetParams.modesetInfo.depth); - NvU64 availableBw = (NvU64)(dev->pconCaps.maxHdmiLinkBandwidthGbps * 1000000000); - if (requiredBW > availableBw) - { - compoundQueryResult = false; - pDscParams->bEnableDsc = false; - return false; - } - } - // - // If DP2HDMI PCON does not support FRL, but advertises TMDS - // Character clock rate on detailed caps, we need to honor that. - // - else if (dev->pconCaps.maxTmdsClkRate != 0) - { - NvU64 maxTmdsClkRateU64 = (NvU64)(dev->pconCaps.maxTmdsClkRate); - NvU64 requireBw = (NvU64)(modesetParams.modesetInfo.pixelClockHz * modesetParams.modesetInfo.depth); - if (modesetParams.colorFormat == dpColorFormat_YCbCr420) - { - if (maxTmdsClkRateU64 < ((requireBw/24)/2)) - { - compoundQueryResult = false; - return false; - } - } - else - { - if (maxTmdsClkRateU64 < (requireBw/24)) - { - compoundQueryResult = false; - return false; - } - } - } - } - else if (dev->devDoingDscDecompression != dev) - { - // - // Device's parent is doing DSC decompression so we need to check - // if device's parent can send uncompressed stream to Sink. - // - unsigned mode_pbn; - - mode_pbn = pbnForMode(modesetParams.modesetInfo); - - // - // As Device's Parent is doing DSC decompression, this is leaf device and - // complete available bandwidth at this node is available for requested mode. - // - if (mode_pbn > dev->bandwidth.enum_path.total) - { - compoundQueryResult = false; - pDscParams->bEnableDsc = false; - return false; - } - } - if (pDscParams->pDscOutParams != NULL) + if (this->preferredLinkConfig.isValid()) { - // - // If requested then DP Library is supposed to return if mode is - // possible with DSC and calculated PPS and bits per pixel. - // - dpMemCopy(pDscParams->pDscOutParams->PPS, PPS, sizeof(unsigned) * DSC_MAX_PPS_SIZE_DWORD); - pDscParams->bitsPerPixelX16 = bitsPerPixelX16; + // Check if mode is possible with preferred link config + bIsModeSupported = willLinkSupportModeSST(lc, localModesetInfo); } else { // - // Client only wants to know if mode is possible or not but doesn't - // need all calculated PPS parameters in case DSC is required. Do nothing. + // Check if mode is possible with calculated bits_per_pixel. + // Check with all possible link configs and not just highest + // assessed because with DSC, mode can fail with higher + // link config and pass for lower one. This is because + // if raster parameters are really small and DP bandwidth is + // very high then we may end up with some TU with 0 active + // symbols in SST. This may cause HW hang and so DP IMP rejects + // this mode. Refer Bug 200379426. // - } - } - } - } - -nonDscDpIMP: - // I. Evaluate use of local link bandwidth - - // Calculate the PBN required - unsigned base_pbn, slots, slots_pbn; - lc.pbnRequired(localModesetInfo, base_pbn, slots, slots_pbn); - - // Accumulate the amount of PBN rounded up to nearest timeslot - compoundQueryLocalLinkPBN += slots_pbn; - if (compoundQueryLocalLinkPBN > lc.pbnTotal()) - compoundQueryResult = false; - - // Verify the min blanking, etc - Watermark dpinfo; - - if (this->isFECSupported()) - { - if (!isModePossibleMSTWithFEC(lc, localModesetInfo, &dpinfo)) - { - compoundQueryResult = false; - } - } - else - { - if (!isModePossibleMST(lc, localModesetInfo, &dpinfo)) - { - compoundQueryResult = false; - } - } - - for(Device * d = target->enumDevices(0); d; d = target->enumDevices(d)) - { - DeviceImpl * i = (DeviceImpl *)d; - - // Allocate bandwidth for the entire path to the root - // NOTE: Above we're already handle the local link - DeviceImpl * tail = i; - while (tail && tail->getParent()) - { - // Have we already accounted for this stream? - if (!(tail->bandwidth.compound_query_state.bandwidthAllocatedForIndex & (1 << compoundQueryCount))) - { - tail->bandwidth.compound_query_state.bandwidthAllocatedForIndex |= (1 << compoundQueryCount); - - LinkConfiguration * linkConfig = tail->inferLeafLink(NULL); - tail->bandwidth.compound_query_state.timeslots_used_by_query += linkConfig->slotsForPBN(base_pbn); - - if ( tail->bandwidth.compound_query_state.timeslots_used_by_query > tail->bandwidth.compound_query_state.totalTimeSlots) - compoundQueryResult = false; - } - tail = (DeviceImpl*)tail->getParent(); - } - } - } - else // SingleStream case - { - DeviceImpl * nativeDev = findDeviceInList(Address()); - - if (compoundQueryCount != 1) - { - compoundQueryResult = false; - return false; - } - - if (nativeDev && (nativeDev->connectorType == connectorHDMI)) - { - if (modesetParams.colorFormat == dpColorFormat_YCbCr420) - { - if ((nativeDev->maxTmdsClkRate) && - (nativeDev->maxTmdsClkRate < - ((modesetParams.modesetInfo.pixelClockHz * modesetParams.modesetInfo.depth /24)/2))) - { - compoundQueryResult = false; - return false; - } - } - else - { - if ((nativeDev->maxTmdsClkRate) && - (nativeDev->maxTmdsClkRate < - (modesetParams.modesetInfo.pixelClockHz * modesetParams.modesetInfo.depth /24))) - { - compoundQueryResult = false; - return false; - } - } - } - - LinkConfiguration lc = highestAssessedLC; - - // check if there is a special request from the client - if (this->preferredLinkConfig.isValid()) - { - lc = preferredLinkConfig; - } - else - { - // - // Always check for DP IMP without FEC overhead first before - // trying with DSC/FEC - // - lc.enableFEC(false); - } - - // If do not found valid native device the force lagacy DP IMP - if (!nativeDev) - { - compoundQueryResult = this->willLinkSupportModeSST(lc, modesetParams.modesetInfo); - } - else if ((pDscParams && (pDscParams->forceDsc == DSC_FORCE_ENABLE)) || // DD has forced DSC Enable - (modesetParams.modesetInfo.mode == DSC_DUAL) || // DD decided to use 2 Head 1 OR mode - (!this->willLinkSupportModeSST(lc, modesetParams.modesetInfo))) // Mode is not possible without DSC - { - // If DP IMP fails without DSC or client requested to force DSC - if (pDscParams && pDscParams->forceDsc != DSC_FORCE_DISABLE) - { - // Check if panel and GPU both supports DSC or not. Also check if panel supports FEC - if (bGpuDscSupported && // if GPU supports DSC - this->isFECSupported() && // If GPU supports FEC - pDscParams && // if client sent DSC info - pDscParams->bCheckWithDsc && // if client wants to check with DSC - nativeDev->isDSCPossible() && // if device supports DSC decompression - (nativeDev->isFECSupported() || main->isEDP()) && // if device supports FEC decoding or is an DSC capable eDP panel which doesn't support FEC - (modesetParams.modesetInfo.bitsPerComponent != 6)) // DSC doesn't support bpc = 6 - { - DSC_INFO dscInfo; - MODESET_INFO modesetInfoDSC; - WAR_DATA warData; - NvU64 availableBandwidthBitsPerSecond = 0; - unsigned PPS[DSC_MAX_PPS_SIZE_DWORD]; - unsigned bitsPerPixelX16 = pDscParams->bitsPerPixelX16; - - if (!this->preferredLinkConfig.isValid() && nativeDev->isFECSupported()) - { - lc.enableFEC(true); - } - - dpMemZero(PPS, sizeof(unsigned) * DSC_MAX_PPS_SIZE_DWORD); - dpMemZero(&dscInfo, sizeof(DSC_INFO)); - - // Populate DSC related info for PPS calculations - populateDscCaps(&dscInfo, nativeDev->devDoingDscDecompression, pDscParams->forcedParams); - - // Populate modeset related info for PPS calculations - populateDscModesetInfo(&modesetInfoDSC, &modesetParams); - - // checking for DSC v1.1 and YUV combination - if ( (dscInfo.sinkCaps.algorithmRevision.versionMajor == 1) && - (dscInfo.sinkCaps.algorithmRevision.versionMinor == 1) && - (modesetParams.colorFormat == dpColorFormat_YCbCr444 )) - { - DP_LOG(("WARNING: DSC v1.2 or higher is recommended for using YUV444")); - DP_LOG(("Current version is 1.1")); - } - - availableBandwidthBitsPerSecond = lc.minRate * 8 * lc.lanes; - - warData.dpData.linkRateHz = lc.peakRate; - warData.dpData.laneCount = lc.lanes; - warData.dpData.hBlank = modesetParams.modesetInfo.rasterWidth - modesetParams.modesetInfo.surfaceWidth; - warData.dpData.dpMode = DSC_DP_SST; - warData.connectorType = DSC_DP; - - DSC_GENERATE_PPS_OPAQUE_WORKAREA *pScratchBuffer = nullptr; - pScratchBuffer = (DSC_GENERATE_PPS_OPAQUE_WORKAREA*)dpMalloc(sizeof(DSC_GENERATE_PPS_OPAQUE_WORKAREA)); - - bool bPpsFailure = ((DSC_GeneratePPS(&dscInfo, &modesetInfoDSC, - &warData, availableBandwidthBitsPerSecond, - (NvU32*)(PPS), - (NvU32*)(&bitsPerPixelX16), - pScratchBuffer)) != NVT_STATUS_SUCCESS); - if (pScratchBuffer) - { - dpFree(pScratchBuffer); - pScratchBuffer = nullptr; + bIsModeSupported = getValidLowestLinkConfig(lc, lowestSelected, localModesetInfo); } - if (bPpsFailure) + if (!bIsModeSupported) { - compoundQueryResult = false; pDscParams->bEnableDsc = false; + SET_DP_IMP_ERROR(pErrorCode, DP_IMP_ERROR_INSUFFICIENT_BANDWIDTH_DSC) + compoundQueryResult = false; } else { - localModesetInfo.bEnableDsc = true; - localModesetInfo.depth = bitsPerPixelX16; - LinkConfiguration lowestSelected; - bool bIsModeSupported = false; + pDscParams->bEnableDsc = true; + compoundQueryResult = true; - - if (this->preferredLinkConfig.isValid()) - { - // Check if mode is possible with preferred link config - bIsModeSupported = willLinkSupportModeSST(lc, localModesetInfo); - } - else + if (pDscParams->pDscOutParams != NULL) { // - // Check if mode is possible with calculated bits_per_pixel. - // Check with all possible link configs and not just highest - // assessed because with DSC, mode can fail with higher - // link config and pass for lower one. This is because - // if raster parameters are really small and DP bandwidth is - // very high then we may end up with some TU with 0 active - // symbols in SST. This may cause HW hang and so DP IMP rejects - // this mode. Refer Bug 200379426. + // If requested then DP Library is supposed to return if mode is + // possible with DSC and calculated PPS and bits per pixel. // - bIsModeSupported = getValidLowestLinkConfig(lc, lowestSelected, localModesetInfo); - } - - if (!bIsModeSupported) - { - pDscParams->bEnableDsc = false; - compoundQueryResult = false; + dpMemCopy(pDscParams->pDscOutParams->PPS, PPS, sizeof(unsigned) * DSC_MAX_PPS_SIZE_DWORD); + pDscParams->bitsPerPixelX16 = bitsPerPixelX16; } else { - pDscParams->bEnableDsc = true; - compoundQueryResult = true; - - if (pDscParams->pDscOutParams != NULL) - { - // - // If requested then DP Library is supposed to return if mode is - // possible with DSC and calculated PPS and bits per pixel. - // - dpMemCopy(pDscParams->pDscOutParams->PPS, PPS, sizeof(unsigned) * DSC_MAX_PPS_SIZE_DWORD); - pDscParams->bitsPerPixelX16 = bitsPerPixelX16; - } - else - { - // - // Client only wants to know if mode is possible or not but doesn't - // need all calculated PPS parameters in case DSC is required. Do nothing. - // - } + // + // Client only wants to know if mode is possible or not but doesn't + // need all calculated PPS parameters in case DSC is required. Do nothing. + // } } } - else - { - // Either GPU or Sink doesn't support DSC - compoundQueryResult = false; - } } else { - // Client hasn't sent DSC params info or has asked to force disable DSC. + // Either GPU or Sink doesn't support DSC compoundQueryResult = false; + SET_DP_IMP_ERROR(pErrorCode, DP_IMP_ERROR_INSUFFICIENT_BANDWIDTH_NO_DSC) } } else { - // Mode was successful - compoundQueryResult = true; + // Client hasn't sent DSC params info or has asked to force disable DSC. + compoundQueryResult = false; + SET_DP_IMP_ERROR(pErrorCode, DP_IMP_ERROR_INSUFFICIENT_BANDWIDTH_NO_DSC) } } - + else + { + // Mode was successful + compoundQueryResult = true; + } return compoundQueryResult; } + void ConnectorImpl::populateDscModesetInfo(MODESET_INFO* pModesetInfo, const DpModesetParams* pModesetParams) { pModesetInfo->pixelClockHz = pModesetParams->modesetInfo.pixelClockHz; @@ -2604,14 +2836,24 @@ bool ConnectorImpl::setDeviceDscState(Device * dev, bool bEnableDsc) if (bEnableDsc) { + if (dscEnabledDevices.contains(dev)) + { + DP_LOG(("DP> DSC already enabled on device")); + return true; + } if(!(((DeviceImpl *)dev)->setDscEnable(true /*bEnableDsc*/))) { DP_ASSERT(!"DP-CONN> Failed to configure DSC on Sink!"); return false; } + dscEnabledDevices.insertFront(dev); } else { + if (!dscEnabledDevices.contains(dev)) + { + return true; + } bool bCurrDscEnable = false; // Get Current DSC Enable State if (!((DeviceImpl *)dev)->getDscEnable(&bCurrDscEnable)) @@ -2621,31 +2863,95 @@ bool ConnectorImpl::setDeviceDscState(Device * dev, bool bEnableDsc) if (bCurrDscEnable) { - // Before disabling DSC check if any active device with same parent has DSC enabled or not + bool bDisableDsc = true; - for (Device * i = enumDevices(0); i; i = enumDevices(i)) + // Before disabling DSC check if other device with same parent has DSC enabled or not + for (Device * i = dscEnabledDevices.next(NULL); i != NULL; i = dscEnabledDevices.next(i)) { - if((dev != i) && (((DeviceImpl *)i)->parent == ((DeviceImpl *)dev)->parent) && - (((DeviceImpl *)i)->activeGroup) && - (((DeviceImpl *)i)->activeGroup->isHeadAttached()) && - (((DeviceImpl *)i)->activeGroup->lastModesetInfo.bEnableDsc)) + if ((i != dev) && (((DeviceImpl *)i)->parent == ((DeviceImpl *)dev)->parent)) { - DP_LOG(("Parent is shared among devices and other device is active so we can't disable DSC")); + DP_LOG(("Parent is shared among devices and other device has DSC enabled so we can't disable DSC")); bDisableDsc = false; break; } } - if(bDisableDsc && !((DeviceImpl *)dev)->setDscEnable(false /*bEnableDsc*/)) { DP_ASSERT(!"DP-CONN> Failed to configure DSC on Sink!"); return false; } } + dscEnabledDevices.remove(dev); } return true; } +bool ConnectorImpl::needToEnableFEC(const DpPreModesetParams ¶ms) +{ + for (NvU32 i = 0; i < NV_MAX_HEADS; i++) + { + if ((params.headMask & NVBIT(i)) == 0x0) + continue; + + if ((params.head[i].pTarget == NULL) || + !params.head[i].pModesetParams->modesetInfo.bEnableDsc) + continue; + + // eDP can support DSC with and without FEC + DeviceImpl * nativeDev = this->findDeviceInList(Address()); + if (this->main->isEDP() && nativeDev) + return nativeDev->getFECSupport(); + else + return true; + } + + return false; +} + +void ConnectorImpl::dpPreModeset(const DpPreModesetParams ¶ms) +{ + this->bFECEnable |= this->needToEnableFEC(params); + + DP_ASSERT(this->inTransitionHeadMask == 0x0); + this->inTransitionHeadMask = 0x0; + + for (NvU32 i = 0; i < NV_MAX_HEADS; i++) + { + if ((params.headMask & NVBIT(i)) == 0x0) + continue; + + this->inTransitionHeadMask |= NVBIT(i); + + if (params.head[i].pTarget != NULL) + { + DP_ASSERT(params.head[i].pModesetParams->headIndex == i); + this->notifyAttachBegin(params.head[i].pTarget, + *params.head[i].pModesetParams); + } + else + { + this->notifyDetachBegin(this->perHeadAttachedGroup[i]); + } + this->perHeadAttachedGroup[i] = params.head[i].pTarget; + } +} + +void ConnectorImpl::dpPostModeset(void) +{ + for (NvU32 i = 0; i < NV_MAX_HEADS; i++) + { + if ((this->inTransitionHeadMask & NVBIT(i)) == 0x0) + continue; + + if (this->perHeadAttachedGroup[i] != NULL) + this->notifyAttachEnd(false); + else + this->notifyDetachEnd(); + + this->inTransitionHeadMask &= ~NVBIT(i); + } +} + // // Notify library before/after modeset (update) // Here is what NAB essentially does: @@ -2789,9 +3095,17 @@ bool ConnectorImpl::notifyAttachBegin(Group * target, // Gr if (main->isEDP()) { - main->configurePowerState(true); - hal->setOuiSource(cachedSourceOUI, &cachedSourceModelName[0], 6 /* string length of ieeeOuiDevId */, - cachedSourceChipRevision); + main->configurePowerState(true); + if (bOuiCached) + { + hal->setOuiSource(cachedSourceOUI, &cachedSourceModelName[0], + 6 /* string length of ieeeOuiDevId */, + cachedSourceChipRevision); + } + else + { + DP_ASSERT("eDP Source OUI is not cached!"); + } } // if failed, we're guaranteed that assessed link rate didn't meet the mode requirements @@ -3498,6 +3812,7 @@ void ConnectorImpl::assessLink(LinkTrainingType trainType) { this->bSkipLt = false; // Assesslink should never skip LT, so let's reset it in case it was set. bool bLinkStateToggle = false; + LinkConfiguration _maxLinkConfig = getMaxLinkConfig(); if (bSkipAssessLinkForPCon) { @@ -3511,11 +3826,11 @@ void ConnectorImpl::assessLink(LinkTrainingType trainType) return; } + if (isLinkQuiesced || (firmwareGroup && ((GroupImpl *)firmwareGroup)->headInFirmware)) { - highestAssessedLC = getMaxLinkConfig(); - + highestAssessedLC = _maxLinkConfig; if (bIsUefiSystem && !hal->getSupportsMultistream()) { // @@ -3554,7 +3869,7 @@ void ConnectorImpl::assessLink(LinkTrainingType trainType) linkGuessed = true; } - if ((getMaxLinkConfig().peakRate == HBR3) && + if ((highestAssessedLC.peakRate == HBR3) && (linkRate != HBR3)) { // @@ -3646,6 +3961,9 @@ void ConnectorImpl::assessLink(LinkTrainingType trainType) linkState = DP_TRANSPORT_MODE_INIT; } + // linkState might be different from beginning, update _maxLinkConfig to keep it in sync. + _maxLinkConfig.multistream = this->linkUseMultistream(); + // // Bug 1545352: This is done to avoid shutting down a display for freeing up a SOR for LT, // when no SOR is assigned properly to the connector. It can happen when more @@ -3655,14 +3973,14 @@ void ConnectorImpl::assessLink(LinkTrainingType trainType) // if (main->getSorIndex() == DP_INVALID_SOR_INDEX) { - highestAssessedLC = getMaxLinkConfig(); + highestAssessedLC = _maxLinkConfig; linkGuessed = true; return; } - LinkConfiguration lConfig = getMaxLinkConfig(); + LinkConfiguration lConfig = _maxLinkConfig; - LinkConfiguration preFlushModeActiveLinkConfig = activeLinkConfig; + LinkConfiguration preFlushModeActiveLinkConfig = activeLinkConfig; if (main->isInternalPanelDynamicMuxCapable()) { @@ -3915,6 +4233,11 @@ void ConnectorImpl::handleMCCSIRQ() } } +void ConnectorImpl::handlePanelReplayError() +{ + hal->readPanelReplayError(); +} + // // Checks if the link is still trained. // Note that these hal registers are ONLY re-read in response to an IRQ. @@ -4462,7 +4785,8 @@ bool ConnectorImpl::getValidLowestLinkConfig for (i = 0; i < numPossibleLnkCfg; i++) { - if ((this->allPossibleLinkCfgs[i].lanes > lConfig.lanes) || (this->allPossibleLinkCfgs[i].peakRate > lConfig.peakRate)) + if ((this->allPossibleLinkCfgs[i].lanes > lConfig.lanes) || + (this->allPossibleLinkCfgs[i].peakRate > lConfig.peakRate)) { continue; } @@ -5856,7 +6180,7 @@ void ConnectorImpl::notifyLongPulseInternal(bool statusConnected) discoveryManager = new DiscoveryManager(messageManager, this, timer, hal); // Check and clear if any pending message here - if (hal->clearPendingMsg() || bForceClearPendingMsg) + if (hal->clearPendingMsg()) { DP_LOG(("DP> Stale MSG found: set branch to D3 and back to D0...")); if (hal->isAtLeastVersion(1, 4)) @@ -6351,6 +6675,13 @@ void ConnectorImpl::notifyShortPulse() handleHdmiLinkStatusChanged(); } + if (hal->isPanelReplayErrorSet()) + { + DP_LOG(("DP> Sink set Panel replay error")); + handlePanelReplayError(); + hal->clearPanelReplayError(); + } + // // Check to make sure sink is not in D3 low power mode // and interlane alignment is good, etc @@ -6486,6 +6817,7 @@ bool ConnectorImpl::setPreferredLinkConfig(LinkConfiguration & lc, bool commit, bool ConnectorImpl::resetPreferredLinkConfig(bool force) { preferredLinkConfig = LinkConfiguration(); + if (force) assessLink(); return true; @@ -6730,7 +7062,6 @@ Connector * DisplayPort::createConnector main->retrieveRingBuffer(LOG_CALL, MAX_RECORD_COUNT); main->retrieveRingBuffer(ASSERT_HIT, MAX_RECORD_COUNT); } - return connector; } @@ -6940,6 +7271,11 @@ bool ConnectorImpl::updatePsrLinkState(bool bTrainLink) return bRet; } +bool ConnectorImpl::readPrSinkDebugInfo(panelReplaySinkDebugInfo *prDbgInfo) +{ + return hal->readPrSinkDebugInfo(prDbgInfo); +} + bool ConnectorImpl::handlePhyPatternRequest() { @@ -7081,6 +7417,5 @@ void ConnectorImpl::configInit() bNoFallbackInPostLQA = 0; LT2FecLatencyMs = 0; bDscCapBasedOnParent = false; - bForceClearPendingMsg = false; } diff --git a/src/common/displayport/src/dp_evoadapter.cpp b/src/common/displayport/src/dp_evoadapter.cpp index f380248ab5..9dee4985c8 100644 --- a/src/common/displayport/src/dp_evoadapter.cpp +++ b/src/common/displayport/src/dp_evoadapter.cpp @@ -40,6 +40,7 @@ #include #include #include + using namespace DisplayPort; // @@ -93,7 +94,6 @@ const struct {NV_DP_REGKEY_KEEP_OPT_LINK_ALIVE_SST, &dpRegkeyDatabase.bOptLinkKeptAliveSst, DP_REG_VAL_BOOL}, {NV_DP_REGKEY_FORCE_EDP_ILR, &dpRegkeyDatabase.bBypassEDPRevCheck, DP_REG_VAL_BOOL}, {NV_DP_DSC_MST_CAP_BUG_3143315, &dpRegkeyDatabase.bDscMstCapBug3143315, DP_REG_VAL_BOOL}, - {NV_DP_CHECK_FEC_FOR_DDS_DSC_PANEL, &dpRegkeyDatabase.bCheckFECForDynamicMuxDSCPanel, DP_REG_VAL_BOOL}, {NV_DP_REGKEY_POWER_DOWN_PHY, &dpRegkeyDatabase.bPowerDownPhyBeforeD3, DP_REG_VAL_BOOL}, {NV_DP_REGKEY_REASSESS_MAX_LINK, &dpRegkeyDatabase.bReassessMaxLink, DP_REG_VAL_BOOL} }; @@ -893,7 +893,6 @@ void EvoMainLink::applyRegkeyOverrides() _skipPowerdownEDPPanelWhenHeadDetach = dpRegkeyDatabase.bPoweroffEdpInHeadDetachSkipped; _applyLinkBwOverrideWarRegVal = dpRegkeyDatabase.bLinkBwOverrideWarApplied; _enableMSAOverrideOverMST = dpRegkeyDatabase.bMsaOverMstEnabled; - _enableFecCheckForDDS = dpRegkeyDatabase.bCheckFECForDynamicMuxDSCPanel; } NvU32 EvoMainLink::getRegkeyValue(const char *key) @@ -1236,14 +1235,10 @@ bool EvoMainLink::train(const LinkConfiguration & link, bool force, retLink->setLaneRate(requestRmLC.peakRate, result ? requestRmLC.lanes : 0); retLink->setLTCounter(ltCounter); - // For release branch only, check FEC return values and update to "retLink" - if (_enableFecCheckForDDS) + if (requestRmLC.bEnableFEC && (FLD_TEST_DRF(0073_CTRL_DP, _ERR, _ENABLE_FEC, _ERR, err))) { - if (requestRmLC.bEnableFEC && (FLD_TEST_DRF(0073_CTRL_DP, _ERR, _ENABLE_FEC, _ERR, err))) - { - retLink->bEnableFEC = false; - DP_ASSERT(0); - } + retLink->bEnableFEC = false; + DP_ASSERT(0); } NV_DPTRACE_INFO(LINK_TRAINING_DONE, status, requestRmLC.peakRate, requestRmLC.lanes); @@ -1345,7 +1340,17 @@ void EvoMainLink::getLinkConfig(unsigned &laneCount, NvU64 & linkRate) if (code == NVOS_STATUS_SUCCESS) { laneCount = params.laneCount; - linkRate = (NvU64)27000000 * params.linkBW; // BUG: Beware, turbo mode need to be taken into account + + if (params.linkBW != 0) + { + // BUG: Beware, turbo mode need to be taken into account + linkRate = ((NvU64)params.linkBW) * DP_LINK_BW_FREQ_MULTI_MBPS; + } + else + { + // No link rate available. + linkRate = 0; + } } else { @@ -1418,6 +1423,7 @@ bool EvoMainLink::queryAndUpdateDfpParams() break; } + _isDynamicMuxCapable = FLD_TEST_DRF(0073, _CTRL_DFP_FLAGS, _DYNAMIC_MUX_CAPABLE, _TRUE, dfpFlags); return true; @@ -1770,8 +1776,8 @@ bool EvoMainLink::dscCrcTransaction(NvBool bEnable, gpuDscCrc *data, NvU16 *head // bool EvoMainLink::configureLinkRateTable ( - const NvU16 *pLinkRateTable, - LinkRates *pLinkRates + const NvU16 *pLinkRateTable, + LinkRates *pLinkRates ) { NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES_PARAMS params; @@ -1809,9 +1815,8 @@ bool EvoMainLink::configureLinkRateTable case linkBW_4_32Gbps: case linkBW_5_40Gbps: case linkBW_8_10Gbps: - pLinkRates->import(params.linkBwTbl[i]); + pLinkRates->import((NvU8)params.linkBwTbl[i]); break; - default: DP_LOG(("DP_EVO> %s: Unsupported link rate received", __FUNCTION__)); diff --git a/src/common/displayport/src/dp_groupimpl.cpp b/src/common/displayport/src/dp_groupimpl.cpp index 35944b7dee..d6c54e39f3 100644 --- a/src/common/displayport/src/dp_groupimpl.cpp +++ b/src/common/displayport/src/dp_groupimpl.cpp @@ -196,7 +196,6 @@ void GroupImpl::destroy() if (group == this) { parent->activeGroups.remove(this); - DP_LOG(("DP-GRP> Deleted group 0x%x from active group!", this)); break; } } @@ -211,7 +210,6 @@ void GroupImpl::destroy() if (group == this) { parent->inactiveGroups.remove(this); - DP_LOG(("DP-GRP> Deleted group 0x%x from inactive group!", this)); break; } } @@ -220,13 +218,11 @@ void GroupImpl::destroy() if (parent->intransitionGroups.contains(this)) { parent->intransitionGroups.remove(this); - DP_LOG(("DP-GRP> Deleted group 0x%x from intransition group!", this)); } if (parent->addStreamMSTIntransitionGroups.contains(this)) { parent->addStreamMSTIntransitionGroups.remove(this); - DP_LOG(("DP-GRP> Deleted group 0x%x from addStreamMSTIntransitionGroups group!", this)); } } diff --git a/src/common/displayport/src/dp_messages.cpp b/src/common/displayport/src/dp_messages.cpp index 9f79d2535a..e8012b1ae1 100644 --- a/src/common/displayport/src/dp_messages.cpp +++ b/src/common/displayport/src/dp_messages.cpp @@ -39,7 +39,13 @@ using namespace DisplayPort; namespace DisplayPort { GenericMessageCompletion::GenericMessageCompletion() : - failed(false), completed(false) {} + failed(false), completed(false) + { + // Initialize nakData seperately. + nakData.reason = NakUndefined; + nakData.nak_data = 0; + // nakData.guid is initalized in its own constructor. + } void GenericMessageCompletion::messageFailed(MessageManager::Message * from, NakData * data) { nakData = *data; @@ -73,6 +79,7 @@ bool MessageManager::send(MessageManager::Message * message, NakData & nakData) { DP_LOG(("DP-MM> Device went offline while waiting for reply and so ignoring message %p (ID = %02X, target = %s)", message, message->requestIdentifier, ((message->state).target).toString(sb))); + completion.nakData.reason = NakDpcdFail; nakData = completion.nakData; completion.failed = true; break; diff --git a/src/common/displayport/src/dp_wardatabase.cpp b/src/common/displayport/src/dp_wardatabase.cpp index 6ad8c947c6..f4e6c483ef 100644 --- a/src/common/displayport/src/dp_wardatabase.cpp +++ b/src/common/displayport/src/dp_wardatabase.cpp @@ -84,17 +84,6 @@ void ConnectorImpl::applyOuiWARs() // LT2FecLatencyMs = 57; - // - // This is to reset the MSTM control bit on the branch device. On this - // device, if continuous LAM message are sent very close then IRQ vector - // will fail to see stale/pending message and will not reset the MSTM_CTRL - // register. Currently making this specific to linux so as to have minimum - // effect on windows. Later proper fix for this will be generic. - // -#if defined(NV_UNIX) - bForceClearPendingMsg = true; -#endif - if (bDscMstCapBug3143315) { // diff --git a/src/common/inc/displayport/displayport.h b/src/common/inc/displayport/displayport.h index 393a3e8c13..b258d1c367 100644 --- a/src/common/inc/displayport/displayport.h +++ b/src/common/inc/displayport/displayport.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -36,6 +36,12 @@ * * \***************************************************************************/ +// +// 4 Legacy Link Rates: RBR, HBR, HBR2, HBR3 +// 4 ILRs: 2.16G, 2.43G, 3.24G, 4.32G +// +#define NV_SUPPORTED_DP1X_LINK_RATES__SIZE 8 + // Displayport interoperability with HDMI dongle i2c addr #define DP2HDMI_DONGLE_I2C_ADDR 0x80 #define DP2HDMI_DONGLE_DDC_BUFFER_ID_LEN 16 @@ -467,6 +473,21 @@ typedef enum PanelReplay_Undefined = 7 } PanelReplayState; +// PR Sink debug info +typedef struct PanelReplaySinkDebugInfo +{ + NvU8 activeFrameCrcError : 1; + NvU8 rfbStorageError : 1; + NvU8 vscSdpUncorrectableError: 1; + NvU8 adaptiveSyncSdpMissing : 1; + NvU8 sinkPrStatus : 3; + NvU8 sinkFramelocked : 2; + NvU8 sinkFrameLockedValid : 1; + NvU8 currentPrState : 1; + NvU8 crcValid: 1; + NvU8 suCoordinatesValid: 1; +} panelReplaySinkDebugInfo; + typedef struct { PanelReplayState prState; diff --git a/src/common/inc/displayport/dpcd.h b/src/common/inc/displayport/dpcd.h index 50bd544a7c..cdedffc77d 100644 --- a/src/common/inc/displayport/dpcd.h +++ b/src/common/inc/displayport/dpcd.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -452,12 +452,12 @@ number of Downstream ports will be limited to 32. #define NV_DPCD_DOWNSPREAD_CTRL_MSA_TIMING_PAR_IGNORED_TRUE (0x00000001) /* RWXUV */ #define NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET (0x00000108) /* RWXUR */ -#define NV_DPCD_MAIN_LINK_CNANNEL_CODING_SET_ANSI_8B_10B 0:0 /* RWXUF */ -#define NV_DPCD_MAIN_LINK_CNANNEL_CODING_SET_ANSI_8B_10B_FALSE (0x00000000) /* RWXUV */ -#define NV_DPCD_MAIN_LINK_CNANNEL_CODING_SET_ANSI_8B_10B_TRUE (0x00000001) /* RWXUV */ -#define NV_DPCD_MAIN_LINK_CNANNEL_CODING_SET_ANSI_128B_132B 1:1 /* RWXUF */ -#define NV_DPCD_MAIN_LINK_CNANNEL_CODING_SET_ANSI_128B_132B_FALSE (0x00000000) /* RWXUV */ -#define NV_DPCD_MAIN_LINK_CNANNEL_CODING_SET_ANSI_128B_132B_TRUE (0x00000001) /* RWXUV */ +#define NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET_ANSI_8B_10B 0:0 /* RWXUF */ +#define NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET_ANSI_8B_10B_FALSE (0x00000000) /* RWXUV */ +#define NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET_ANSI_8B_10B_TRUE (0x00000001) /* RWXUV */ +#define NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET_ANSI_128B_132B 1:1 /* RWXUF */ +#define NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET_ANSI_128B_132B_FALSE (0x00000000) /* RWXUV */ +#define NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET_ANSI_128B_132B_TRUE (0x00000001) /* RWXUV */ #define NV_DPCD_I2C_CTRL_SET (0x00000109) /* RWXUR */ #define NV_DPCD_I2C_CTRL_SET_SPEED 7:0 /* RWXUF */ @@ -1000,6 +1000,8 @@ number of Downstream ports will be limited to 32. #define NV_DPCD_EDP_REV_VAL_1_4 (0x00000003) /* R-XUV */ #define NV_DPCD_EDP_REV_VAL_1_4A (0x00000004) /* R-XUV */ #define NV_DPCD_EDP_REV_VAL_1_4B (0x00000005) /* R-XUV */ +#define NV_DPCD_EDP_REV_VAL_1_5 (0x00000006) /* R-XUV */ +#define NV_DPCD_EDP_REV_VAL_1_5A (0x00000006) /* R-XUV */ #define NV_DPCD_EDP_GENERAL_CAP1 (0x00000701) /* R-XUR */ #define NV_DPCD_EDP_GENERAL_CAP1_TCON_BKLGHT_ADJUST_CAP 0:0 /* R-XUF */ #define NV_DPCD_EDP_GENERAL_CAP1_TCON_BKLGHT_ADJUST_CAP_YES (0x00000001) /* R-XUV */ @@ -1061,6 +1063,9 @@ number of Downstream ports will be limited to 32. #define NV_DPCD_EDP_GENERAL_CAP2_OVERDRIVE_CONTROL_CAP 3:3 /* R-XUF */ #define NV_DPCD_EDP_GENERAL_CAP2_OVERDRIVE_CONTROL_CAP_NO (0x00000000) /* R-XUV */ #define NV_DPCD_EDP_GENERAL_CAP2_OVERDRIVE_CONTROL_CAP_YES (0x00000001) /* R-XUV */ +#define NV_DPCD_EDP_GENERAL_CAP2_PANEL_LUMINANCE_CONTROL_CAP 4:4 /* R-XUF */ +#define NV_DPCD_EDP_GENERAL_CAP2_PANEL_LUMINANCE_CONTROL_CAP_NO (0x00000000) /* R-XUV */ +#define NV_DPCD_EDP_GENERAL_CAP2_PANEL_LUMINANCE_CONTROL_CAP_YES (0x00000001) /* R-XUV */ #define NV_DPCD_EDP_GENERAL_CAP3 (0x00000704) /* R-XUV */ #define NV_DPCD_EDP_GENERAL_CAP3_X_REGION_CAP 3:0 /* R-XUF */ #define NV_DPCD_EDP_GENERAL_CAP3_X_REGION_CAP_NOT_SUPPORTED (0x00000000) /* R-XUV */ @@ -1115,6 +1120,9 @@ number of Downstream ports will be limited to 32. #define NV_DPCD_EDP_BKLGHT_MODE_SET_UPDATE_REGION_BRIGHTNESS 6:6 /* RWXUF */ #define NV_DPCD_EDP_BKLGHT_MODE_SET_UPDATE_REGION_BRIGHTNESS_ENABLED (0x00000001) /* RWXUV */ #define NV_DPCD_EDP_BKLGHT_MODE_SET_UPDATE_REGION_BRIGHTNESS_DISABLED (0x00000000) /* RWXUV */ +#define NV_DPCD_EDP_BKLGHT_MODE_SET_PANEL_LUMINANCE_CONTROL_ENABLE 7:7 /* RWXUF */ +#define NV_DPCD_EDP_BKLGHT_MODE_SET_PANEL_LUMINANCE_CONTROL_ENABLE_YES (0x00000001) /* RWXUV */ +#define NV_DPCD_EDP_BKLGHT_MODE_SET_PANEL_LUMINANCE_CONTROL_ENABLE_NO (0x00000000) /* RWXUV */ #define NV_DPCD_EDP_BKLGHT_BRIGHTNESS_MSB (0x00000722) /* RWXUR */ #define NV_DPCD_EDP_BKLGHT_BRIGHTNESS_MSB_VAL 7:0 /* RWXUF */ #define NV_DPCD_EDP_BKLGHT_BRIGHTNESS_MSB_VAL_INIT (0x00000000) /* RWXUV */ @@ -1162,6 +1170,15 @@ number of Downstream ports will be limited to 32. #define NV_DPCD_EDP_DBC_MAXIMUM_BRIGHTNESS_SET (0x00000733) /* RWXUR */ #define NV_DPCD_EDP_DBC_MAXIMUM_BRIGHTNESS_CAP_VAL 4:0 /* RWXUF */ #define NV_DPCD_EDP_DBC_MAXIMUM_BRIGHTNESS_CAP_VAL_INIT (0x00000000) /* RWXUV */ +#define NV_DPCD_PANEL_TARGET_LUMINANCE_LSB (0x00000734) /* RWXUR */ +#define NV_DPCD_PANEL_TARGET_LUMINANCE_LSB_VAL 7:0 /* RWXUF */ +#define NV_DPCD_PANEL_TARGET_LUMINANCE_LSB_VAL_INIT (0x00000000) /* RWXUV */ +#define NV_DPCD_PANEL_TARGET_LUMINANCE_MID (0x00000735) /* RWXUR */ +#define NV_DPCD_PANEL_TARGET_LUMINANCE_MID_VAL 7:0 /* RWXUF */ +#define NV_DPCD_PANEL_TARGET_LUMINANCE_MID_VAL_INIT 0x00000000) /* RWXUV */ +#define NV_DPCD_PANEL_TARGET_LUMINANCE_MSB (0x00000736) /* RWXUR */ +#define NV_DPCD_PANEL_TARGET_LUMINANCE_MSB_VAL 7:0 /* RWXUF */ +#define NV_DPCD_PANEL_TARGET_LUMINANCE_MSB_VAL_INIT 0x00000000) /* RWXUV */ #define NV_DPCD_EDP_REGIONAL_BKLGHT_BASE (0x00000740) /* RWXUR */ #define NV_DPCD_EDP_REGIONAL_BKLGHT_BASE_INDEX_OFFSET_VAL 7:0 /* RWXUF */ #define NV_DPCD_EDP_REGIONAL_BKLGHT_BASE_INDEX_OFFSET_VAL_INIT (0x00000000) /* RWXUV */ @@ -1262,6 +1279,10 @@ number of Downstream ports will be limited to 32. #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_ESI1_RX_GTC_MSTR_REQ_STATUS_CHANGE 0:0 /* R-XUF */ #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_ESI1_RX_GTC_MSTR_REQ_STATUS_CHANGE_NO (0x00000000) /* R-XUV */ #define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_ESI1_RX_GTC_MSTR_REQ_STATUS_CHANGE_YES (0x00000001) /* R-XUV */ +#define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_ESI1_PANEL_REPLAY_ERROR_STATUS 3:3 /* R-XUF */ +#define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_ESI1_PANEL_REPLAY_ERROR_STATUS_NO (0x00000000) /* R-XUV */ +#define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_ESI1_PANEL_REPLAY_ERROR_STATUS_YES (0x00000001) /* R-XUV */ + #define NV_DPCD_LINK_SERVICE_IRQ_VECTOR_ESI0 (0x00002005) /* R-XUR */ #define NV_DPCD_LINK_SERVICE_IRQ_VECTOR_ESI0_RX_CAP_CHANGED 0:0 /* R-XUF */ diff --git a/src/common/inc/displayport/dpcd14.h b/src/common/inc/displayport/dpcd14.h index 3b57df8f13..ea649b46d1 100644 --- a/src/common/inc/displayport/dpcd14.h +++ b/src/common/inc/displayport/dpcd14.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -358,9 +358,6 @@ #define NV_DPCD14_EXTENDED_MAIN_LINK_CHANNEL_CODING_ANSI_8B_10B 0:0 /* R-XUF */ #define NV_DPCD14_EXTENDED_MAIN_LINK_CHANNEL_CODING_ANSI_8B_10B_NO (0x00000000) /* R-XUV */ #define NV_DPCD14_EXTENDED_MAIN_LINK_CHANNEL_CODING_ANSI_8B_10B_YES (0x00000001) /* R-XUV */ -#define NV_DPCD14_EXTENDED_MAIN_LINK_CHANNEL_CODING_ANSI_128B_132B 1:1 /* R-XUF */ -#define NV_DPCD14_EXTENDED_MAIN_LINK_CHANNEL_CODING_ANSI_128B_132B_NO (0x00000000) /* R-XUV */ -#define NV_DPCD14_EXTENDED_MAIN_LINK_CHANNEL_CODING_ANSI_128B_132B_YES (0x00000001) /* R-XUV */ #define NV_DPCD14_EXTENDED_DOWN_STREAM_PORT (0x00002207) /* R-XUR */ #define NV_DPCD14_EXTENDED_DOWN_STREAM_PORT_COUNT 3:0 /* R-XUF */ @@ -632,22 +629,6 @@ #define NV_DPCD14_PHY_REPEATER_EXTENDED_WAKE_TIMEOUT_REQ 6:0 /* R-XUF */ #define NV_DPCD14_PHY_REPEATER_EXTENDED_WAKE_TIMEOUT_GRANT 7:7 /* RWXUF */ -#define NV_DPCD14_PHY_REPEATER_MAIN_LINK_CHANNEL_CODING (0x000F0006) /* RWXUR */ -#define NV_DPCD14_PHY_REPEATER_MAIN_LINK_CHANNEL_CODING_128B_132B_SUPPORTED 0:0 /* R-XUF */ -#define NV_DPCD14_PHY_REPEATER_MAIN_LINK_CHANNEL_CODING_128B_132B_SUPPORTED_NO (0x00000000) /* RWXUF */ -#define NV_DPCD14_PHY_REPEATER_MAIN_LINK_CHANNEL_CODING_128B_132B_SUPPORTED_YES (0x00000001) /* RWXUF */ - -#define NV_DPCD14_PHY_REPEATER_128B_132B_RATES (0x000F0007) /* R-XUR */ -#define NV_DPCD14_PHY_REPEATER_128B_132B_RATES_10G_SUPPORTED 0:0 /* R-XUF */ -#define NV_DPCD14_PHY_REPEATER_128B_132B_RATES_10G_SUPPORTED_NO (0x00000000) /* R-XUF */ -#define NV_DPCD14_PHY_REPEATER_128B_132B_RATES_10G_SUPPORTED_YES (0x00000001) /* R-XUF */ -#define NV_DPCD14_PHY_REPEATER_128B_132B_RATES_20G_SUPPORTED 1:1 /* R-XUF */ -#define NV_DPCD14_PHY_REPEATER_128B_132B_RATES_20G_SUPPORTED_NO (0x00000000) /* R-XUF */ -#define NV_DPCD14_PHY_REPEATER_128B_132B_RATES_20G_SUPPORTED_YES (0x00000001) /* R-XUF */ -#define NV_DPCD14_PHY_REPEATER_128B_132B_RATES_13_5G_SUPPORTED 2:2 /* R-XUF */ -#define NV_DPCD14_PHY_REPEATER_128B_132B_RATES_13_5G_SUPPORTED_NO (0x00000000) /* R-XUF */ -#define NV_DPCD14_PHY_REPEATER_128B_132B_RATES_13_5G_SUPPORTED_YES (0x00000001) /* R-XUF */ - #define NV_DPCD14_PHY_REPEATER_EQ_DONE (0x000F0008) /* R-XUR */ #define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR(i) (i):(i) /* R-XUF */ #define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_NO (0x00000000) /* R-XUF */ diff --git a/src/common/inc/displayport/dpcd20.h b/src/common/inc/displayport/dpcd20.h index a6c49a3c2e..4387e5308d 100644 --- a/src/common/inc/displayport/dpcd20.h +++ b/src/common/inc/displayport/dpcd20.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -20,7 +20,8 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ - +#ifndef _DISPLAYPORT20_H_ +#define _DISPLAYPORT20_H_ #include "nvcfg_sdk.h" // DSC Pass Through related DPCD. New bits in DPCD 0x0060h defined in DPCD2.0. @@ -46,6 +47,20 @@ #define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_PR_MODE_NO (0x00000000) #define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_PR_MODE_YES (0x00000001) +#define NV_DPCD20_PANEL_REPLAY_ERROR_STATUS (0x00002020) +#define NV_DPCD20_PANEL_REPLAY_ERROR_STATUS_ACTIVE_FRAME_CRC_ERROR 0:0 +#define NV_DPCD20_PANEL_REPLAY_ERROR_STATUS_ACTIVE_FRAME_CRC_ERROR_NO (0x00000000) +#define NV_DPCD20_PANEL_REPLAY_ERROR_STATUS_ACTIVE_FRAME_CRC_ERROR_YES (0x00000001) +#define NV_DPCD20_PANEL_REPLAY_ERROR_STATUS_RFB_STORAGE_ERROR 1:1 +#define NV_DPCD20_PANEL_REPLAY_ERROR_STATUS_RFB_STORAGE_ERROR_NO (0x00000000) +#define NV_DPCD20_PANEL_REPLAY_ERROR_STATUS_RFB_STORAGE_ERROR_YES (0x00000001) +#define NV_DPCD20_PANEL_REPLAY_ERROR_STATUS_VSC_SDP_UNCORRECTABLE_ERROR 2:2 +#define NV_DPCD20_PANEL_REPLAY_ERROR_STATUS_VSC_SDP_UNCORRECTABLE_ERROR_NO (0x00000000) +#define NV_DPCD20_PANEL_REPLAY_ERROR_STATUS_VSC_SDP_UNCORRECTABLE_ERROR_YES (0x00000001) +#define NV_DPCD20_PANEL_REPLAY_ERROR_STATUS_ADAPTIVE_SYNC_SDP_MISSING 3:3 +#define NV_DPCD20_PANEL_REPLAY_ERROR_STATUS_ADAPTIVE_SYNC_SDP_MISSING_NO (0x00000000) +#define NV_DPCD20_PANEL_REPLAY_ERROR_STATUS_ADAPTIVE_SYNC_SDP_MISSING_YES (0x00000001) + #define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS (0x00002022) #define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_PR_STATUS 2:0 #define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_PR_STATUS_STATE_0 (0x00000000) @@ -57,4 +72,19 @@ #define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_SINK_FRAME_LOCKED_COASTING (0x00000001) #define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_SINK_FRAME_LOCKED_GOVERNING (0x00000002) #define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_SINK_FRAME_LOCKED_RELOCKING (0x00000003) +#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_SINK_FRAME_LOCKED_VALID 5:5 +#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_SINK_FRAME_LOCKED_VALID_NO (0x00000000) +#define NV_DPCD20_PANEL_REPLAY_AND_FRAME_LOCK_STATUS_SINK_FRAME_LOCKED_VALID_YES (0x00000001) + +#define NV_DPCD20_PANEL_REPLAY_DEBUG_LAST_VSC_SDP_CARRYING_PR_INFO (0x00002024) +#define NV_DPCD20_PANEL_REPLAY_DEBUG_LAST_VSC_SDP_CARRYING_PR_INFO_STATE 0:0 +#define NV_DPCD20_PANEL_REPLAY_DEBUG_LAST_VSC_SDP_CARRYING_PR_INFO_STATE_INACTIVE (0x00000000) +#define NV_DPCD20_PANEL_REPLAY_DEBUG_LAST_VSC_SDP_CARRYING_PR_INFO_STATE_ACTIVE (0x00000001) +#define NV_DPCD20_PANEL_REPLAY_DEBUG_LAST_VSC_SDP_CARRYING_PR_INFO_CRC_VALID 2:2 +#define NV_DPCD20_PANEL_REPLAY_DEBUG_LAST_VSC_SDP_CARRYING_PR_INFO_CRC_VALID_NO (0x00000000) +#define NV_DPCD20_PANEL_REPLAY_DEBUG_LAST_VSC_SDP_CARRYING_PR_INFO_CRC_VALID_YES (0x00000001) +#define NV_DPCD20_PANEL_REPLAY_DEBUG_LAST_VSC_SDP_CARRYING_PR_INFO_SU_COORDINATE_VALID 3:3 +#define NV_DPCD20_PANEL_REPLAY_DEBUG_LAST_VSC_SDP_CARRYING_PR_INFO_SU_COORDINATE_VALID_NO (0x00000000) +#define NV_DPCD20_PANEL_REPLAY_DEBUG_LAST_VSC_SDP_CARRYING_PR_INFO_SU_COORDINATE_VALID_YES (0x00000001) +#endif // #ifndef _DISPLAYPORT20_H_ diff --git a/src/common/inc/nvBldVer.h b/src/common/inc/nvBldVer.h index f6b497fdc7..6f0c0c1165 100644 --- a/src/common/inc/nvBldVer.h +++ b/src/common/inc/nvBldVer.h @@ -36,26 +36,26 @@ // and then checked back in. You cannot make changes to these sections without // corresponding changes to the buildmeister script #ifndef NV_BUILD_BRANCH - #define NV_BUILD_BRANCH r537_41 + #define NV_BUILD_BRANCH r545_74 #endif #ifndef NV_PUBLIC_BRANCH - #define NV_PUBLIC_BRANCH r537_41 + #define NV_PUBLIC_BRANCH r545_74 #endif #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) -#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r535/r537_41-286" -#define NV_BUILD_CHANGELIST_NUM (33292694) +#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r545/r545_74-96" +#define NV_BUILD_CHANGELIST_NUM (33409679) #define NV_BUILD_TYPE "Official" -#define NV_BUILD_NAME "rel/gpu_drv/r535/r537_41-286" -#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33292694) +#define NV_BUILD_NAME "rel/gpu_drv/r545/r545_74-96" +#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33409679) #else /* Windows builds */ -#define NV_BUILD_BRANCH_VERSION "r537_41-1" -#define NV_BUILD_CHANGELIST_NUM (33292694) +#define NV_BUILD_BRANCH_VERSION "r545_74-8" +#define NV_BUILD_CHANGELIST_NUM (33409679) #define NV_BUILD_TYPE "Official" -#define NV_BUILD_NAME "537.42" -#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33292694) -#define NV_BUILD_BRANCH_BASE_VERSION R535 +#define NV_BUILD_NAME "545.87" +#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33409679) +#define NV_BUILD_BRANCH_BASE_VERSION R545 #endif // End buildmeister python edited section diff --git a/src/common/inc/nvCpuIntrinsics.h b/src/common/inc/nvCpuIntrinsics.h index e1829af5b7..e417ef7457 100644 --- a/src/common/inc/nvCpuIntrinsics.h +++ b/src/common/inc/nvCpuIntrinsics.h @@ -91,7 +91,7 @@ // Not implemented yet #define NV_SPIN_LOOP_HINT() -#elif defined(NVCPU_FAMILY_ARM) || defined(NVCPU_PPC64LE) +#elif defined(NVCPU_FAMILY_ARM) || defined(NVCPU_PPC64LE) || defined(NVCPU_RISCV64) // Not implemented yet #define NV_SPIN_LOOP_HINT() diff --git a/src/common/inc/nvUnixVersion.h b/src/common/inc/nvUnixVersion.h index 50fad90692..749384cee1 100644 --- a/src/common/inc/nvUnixVersion.h +++ b/src/common/inc/nvUnixVersion.h @@ -4,7 +4,7 @@ #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \ (defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1) -#define NV_VERSION_STRING "535.113.01" +#define NV_VERSION_STRING "545.23.06" #else diff --git a/src/common/inc/nv_speculation_barrier.h b/src/common/inc/nv_speculation_barrier.h index 70c96517a6..8f9121bcfa 100644 --- a/src/common/inc/nv_speculation_barrier.h +++ b/src/common/inc/nv_speculation_barrier.h @@ -82,7 +82,7 @@ /* aarch64(ARMv8) mode */ #define NV_SPECULATION_BARRIER_ARM_COMMON #define NV_SPEC_BARRIER_CSDB "HINT #20\n" -#elif defined(NVCPU_NVRISCV64) && NVOS_IS_LIBOS +#elif defined(NVCPU_IS_RISCV64) # define nv_speculation_barrier() #else #error "Unknown compiler/chip family" diff --git a/src/common/inc/nveGPUConfig.h b/src/common/inc/nveGPUConfig.h index 751e0736b8..25b6f42776 100644 --- a/src/common/inc/nveGPUConfig.h +++ b/src/common/inc/nveGPUConfig.h @@ -71,6 +71,25 @@ extern "C" { #define BUS_DEVICE_ID_TIGERLAKE_TB3_09 0x9A2B #define BUS_DEVICE_ID_TIGERLAKE_TB3_10 0x9A2D +// Meteor Lake ThunderBolt Device IDs +#define BUS_DEVICE_ID_METEOR_TB3_01 0x7EB2 +#define BUS_DEVICE_ID_METEOR_TB3_02 0x7EC2 +#define BUS_DEVICE_ID_METEOR_TB3_03 0x7EC3 +#define BUS_DEVICE_ID_METEOR_TB3_04 0x7EB4 +#define BUS_DEVICE_ID_METEOR_TB3_05 0x7EC4 +#define BUS_DEVICE_ID_METEOR_TB3_06 0x7EB5 +#define BUS_DEVICE_ID_METEOR_TB3_07 0x7EC5 +#define BUS_DEVICE_ID_METEOR_TB3_08 0x7EC6 +#define BUS_DEVICE_ID_METEOR_TB3_09 0x7EC7 + +// Raptor Lake ThunderBolt Device IDs +#define BUS_DEVICE_ID_RAPTOR_TB3_01 0xA73E +#define BUS_DEVICE_ID_RAPTOR_TB3_02 0xA76D +#define BUS_DEVICE_ID_RAPTOR_TB3_03 0x466E +#define BUS_DEVICE_ID_RAPTOR_TB3_04 0x463F +#define BUS_DEVICE_ID_RAPTOR_TB3_05 0x462F +#define BUS_DEVICE_ID_RAPTOR_TB3_06 0x461F + //#define BUS_DEVICE_ID_TB2_FALCON_RIDGE_DSL5520_01 0X156C // obsolete #define BUS_DEVICE_ID_TB2_FALCON_RIDGE_DSL5520_02 0X156D #define BUS_DEVICE_ID_TB2_03 0x157E @@ -128,7 +147,22 @@ EGPU_INLINE NvBool isTB3DeviceID(NvU16 deviceID) BUS_DEVICE_ID_TIGERLAKE_TB3_07, BUS_DEVICE_ID_TIGERLAKE_TB3_08, BUS_DEVICE_ID_TIGERLAKE_TB3_09, - BUS_DEVICE_ID_TIGERLAKE_TB3_10 + BUS_DEVICE_ID_TIGERLAKE_TB3_10, + BUS_DEVICE_ID_METEOR_TB3_01, + BUS_DEVICE_ID_METEOR_TB3_02, + BUS_DEVICE_ID_METEOR_TB3_03, + BUS_DEVICE_ID_METEOR_TB3_04, + BUS_DEVICE_ID_METEOR_TB3_05, + BUS_DEVICE_ID_METEOR_TB3_06, + BUS_DEVICE_ID_METEOR_TB3_07, + BUS_DEVICE_ID_METEOR_TB3_08, + BUS_DEVICE_ID_METEOR_TB3_09, + BUS_DEVICE_ID_RAPTOR_TB3_01, + BUS_DEVICE_ID_RAPTOR_TB3_02, + BUS_DEVICE_ID_RAPTOR_TB3_03, + BUS_DEVICE_ID_RAPTOR_TB3_04, + BUS_DEVICE_ID_RAPTOR_TB3_05, + BUS_DEVICE_ID_RAPTOR_TB3_06 }; for (index = 0; index < (sizeof(tb3DeviceIDList)/sizeof(NvU16)); index++) { diff --git a/src/common/inc/nvlog_defs.h b/src/common/inc/nvlog_defs.h index 86da458ea3..f7bcb0ba82 100644 --- a/src/common/inc/nvlog_defs.h +++ b/src/common/inc/nvlog_defs.h @@ -151,7 +151,7 @@ extern NVLOG_LOGGER NvLogLogger; * from certain RmCtrl handlers. * * Historically in most contexts obtaining RMAPI lock would suffice, and mainLock would optionally - * be used for certain buffers. Ioctl NV_ESC_RM_NVLOG_CTRL cannot touch RMAPI lock and needs + * be used for certain buffers. Ioctl NV_ESC_RM_LOCKLESS_DIAGNOSTIC cannot touch RMAPI lock and needs * to access NvLog. The latter operation might race if called at an inopportune time: e.g. if the * ioctl is called during RM init when KGSP creates/deletes GSP NvLog buffers. Using buffersLock is * thus necessary to resolve the potential race. diff --git a/src/common/inc/swref/published/ampere/ga100/dev_nv_xve.h b/src/common/inc/swref/published/ampere/ga100/dev_nv_xve.h index 181c5b8344..a5bdd018fe 100644 --- a/src/common/inc/swref/published/ampere/ga100/dev_nv_xve.h +++ b/src/common/inc/swref/published/ampere/ga100/dev_nv_xve.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES + * SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -26,4 +26,12 @@ #define NV_PCFG 0x00088FFF:0x00088000 /* RW--D */ #define NV_XVE_LINK_CONTROL_STATUS 0x00000088 /* RW-4R */ #define NV_XVE_LINK_CONTROL_STATUS_LINK_SPEED 19:16 /* R--VF */ +#define NV_XVE_DBG_CYA_0 0x00000898 /* RW-4R */ +#define NV_XVE_DBG_CYA_0_BAR0_ADDR_WIDTH 19:19 /* RWCVF */ +#define NV_XVE_DBG_CYA_0_BAR0_ADDR_WIDTH_32BIT 0x00000000 /* RWC-V */ +#define NV_XVE_DBG_CYA_0_BAR0_ADDR_WIDTH_64BIT 0x00000001 /* RW--V */ +#define NV_XVE_RESIZE_BAR1_CTRL 0x00000BC0 /* RW-4R */ +#define NV_XVE_RESIZE_BAR1_CTRL_BAR_SIZE 12:8 /* RWIVF */ +#define NV_XVE_RESIZE_BAR1_CTRL_BAR_SIZE_MIN 0x00000006 /* ----V */ +#define NV_XVE_RESIZE_BAR1_CTRL_BAR_SIZE_MAX 0x00000013 /* ----V */ #endif diff --git a/src/common/inc/swref/published/ampere/ga100/dev_nv_xve_addendum.h b/src/common/inc/swref/published/ampere/ga100/dev_nv_xve_addendum.h index 2933606f5b..00e6f3cd45 100644 --- a/src/common/inc/swref/published/ampere/ga100/dev_nv_xve_addendum.h +++ b/src/common/inc/swref/published/ampere/ga100/dev_nv_xve_addendum.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -49,4 +49,21 @@ // #define NV_XVE_PASSTHROUGH_EMULATED_CONFIG_RELAXED_ORDERING_ENABLE 4:4 +// +// While the following defines are not register addresses/bit fields, the BAR +// indices(currently arranged in serial fashion) could be changed for future +// chips and therefore keeping it chip specific +// +#define NV_XVE_BAR0_LO_INDEX 0x0 +#define NV_XVE_BAR0_HI_INDEX 0x1 +#define NV_XVE_BAR1_LO_INDEX 0x2 +#define NV_XVE_BAR1_HI_INDEX 0x3 +#define NV_XVE_BAR2_LO_INDEX 0x4 +#define NV_XVE_BAR2_HI_INDEX 0x5 +#define NV_XVE_BAR3_INDEX 0x6 + + +#define NV_PCFG 0x00088FFF:0x00088000 /* RW--D */ +#define NV_XVE_DEV_CTRL 0x00000004 /* RW-4R */ + #endif diff --git a/src/common/inc/swref/published/ampere/ga102/dev_nv_pcfg_xve_regmap.h b/src/common/inc/swref/published/ampere/ga102/dev_nv_pcfg_xve_regmap.h new file mode 100644 index 0000000000..10462f928b --- /dev/null +++ b/src/common/inc/swref/published/ampere/ga102/dev_nv_pcfg_xve_regmap.h @@ -0,0 +1,71 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __dev_nv_pcfg_xve_regmap_h__ +#define __dev_nv_pcfg_xve_regmap_h__ + +#define NV_PCFG_XVE_REGISTER_MAP_START_OFFSET 0x00088000 + +/* + * _MAP has 1 bit set for each dword register. + * _COUNT has total number of set bits in _MAP. + */ +#define NV_PCFG_XVE_REGISTER_VALID_COUNT 472 +#define NV_PCFG_XVE_REGISTER_VALID_MAP { \ + /* 0x00088000 */ 0xFFF1FFFF, 0x101FFF9F, \ + /* 0x00088100 */ 0x3FFA3C7F, 0x00000000, \ + /* 0x00088200 */ 0x03F00000, 0x00000000, \ + /* 0x00088300 */ 0x00000000, 0x00000000, \ + /* 0x00088400 */ 0x8007FFC0, 0x3F3F5807, \ + /* 0x00088500 */ 0x000000BF, 0x00000000, \ + /* 0x00088600 */ 0x0140AA1F, 0x00000000, \ + /* 0x00088700 */ 0x00013FFF, 0x00000000, \ + /* 0x00088800 */ 0xFFEFDFD7, 0x1EDAFFFF, \ + /* 0x00088900 */ 0xFFFFFFFF, 0x002FFFFF, \ + /* 0x00088A00 */ 0xFF7FFFFF, 0x0007FFFF, \ + /* 0x00088B00 */ 0x00000000, 0xFFFFF000, \ + /* 0x00088C00 */ 0x0007BFE7, 0xFFC003FC, \ + /* 0x00088D00 */ 0xFFFFFFFF, 0x7C1F3FFF, \ + /* 0x00088E00 */ 0xFFFFFFFF, 0x00FFFFFF, \ + /* 0x00088F00 */ 0x00000000, 0xFE000000 } + +#define NV_PCFG_XVE_REGISTER_WR_COUNT 350 +#define NV_PCFG_XVE_REGISTER_WR_MAP { \ + /* 0x00088000 */ 0x3EF193FA, 0x1007C505, \ + /* 0x00088100 */ 0x3FFA0828, 0x00000000, \ + /* 0x00088200 */ 0x03200000, 0x00000000, \ + /* 0x00088300 */ 0x00000000, 0x00000000, \ + /* 0x00088400 */ 0x80007EC0, 0x3F075007, \ + /* 0x00088500 */ 0x000000BF, 0x00000000, \ + /* 0x00088600 */ 0x0140AA10, 0x00000000, \ + /* 0x00088700 */ 0x00013FFF, 0x00000000, \ + /* 0x00088800 */ 0x004C5FC3, 0x1C5AFFC0, \ + /* 0x00088900 */ 0xFFFC7804, 0x002FFFFF, \ + /* 0x00088A00 */ 0xFF7FFDFD, 0x00007FFF, \ + /* 0x00088B00 */ 0x00000000, 0xF8A54000, \ + /* 0x00088C00 */ 0x00003C01, 0x3FC003FC, \ + /* 0x00088D00 */ 0xFFFFFFFC, 0x701B2C3F, \ + /* 0x00088E00 */ 0xFFFFFFF8, 0x00FFBFFF, \ + /* 0x00088F00 */ 0x00000000, 0xFE000000 } + +#endif // {__dev_nv_pcfg_xve_regmap_h__} diff --git a/src/common/inc/swref/published/disp/v02_04/dev_disp.h b/src/common/inc/swref/published/disp/v02_04/dev_disp.h new file mode 100644 index 0000000000..5eb42179eb --- /dev/null +++ b/src/common/inc/swref/published/disp/v02_04/dev_disp.h @@ -0,0 +1,31 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __v02_04_dev_disp_h__ +#define __v02_04_dev_disp_h__ +#define NV_PDISP_PIPE_IN_LOADV_COUNTER(i) (0x00616118+(i)*2048) /* RW-4A */ +#define NV_PDISP_PIPE_IN_LOADV_COUNTER__SIZE_1 4 /* */ +#define NV_PDISP_PIPE_IN_LOADV_COUNTER_VALUE 31:0 /* RWIUF */ +#define NV_PDISP_PIPE_IN_LOADV_COUNTER_VALUE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_PIPE_IN_LOADV_COUNTER_VALUE_ZERO 0x00000000 /* RW--V */ +#endif // __v02_04_dev_disp_h__ diff --git a/src/common/inc/swref/published/disp/v03_00/dev_disp.h b/src/common/inc/swref/published/disp/v03_00/dev_disp.h index 79cf7a2c86..9049edb7ac 100644 --- a/src/common/inc/swref/published/disp/v03_00/dev_disp.h +++ b/src/common/inc/swref/published/disp/v03_00/dev_disp.h @@ -74,4 +74,11 @@ #define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_AWAKEN 8:8 /* R-IVF */ #define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_AWAKEN_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_AWAKEN_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_POSTCOMP_HEAD_LOADV_COUNTER(i) (0x0061611C+(i)*2048) /* RW-4A */ +#define NV_PDISP_POSTCOMP_HEAD_LOADV_COUNTER__SIZE_1 8 /* */ +#define NV_PDISP_POSTCOMP_HEAD_LOADV_COUNTER_VALUE 31:0 /* RWIUF */ +#define NV_PDISP_POSTCOMP_HEAD_LOADV_COUNTER_VALUE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_POSTCOMP_HEAD_LOADV_COUNTER_VALUE_ZERO 0x00000000 /* RW--V */ +#define NV_PDISP_POSTCOMP_HEAD_LOADV_COUNTER_VALUE_HW 0x00000000 /* R---V */ +#define NV_PDISP_POSTCOMP_HEAD_LOADV_COUNTER_VALUE_SW 0x00000000 /* -W--V */ #endif // __v03_00_dev_disp_h__ diff --git a/src/common/inc/swref/published/disp/v05_01/dev_disp.h b/src/common/inc/swref/published/disp/v05_01/dev_disp.h new file mode 100644 index 0000000000..497920170b --- /dev/null +++ b/src/common/inc/swref/published/disp/v05_01/dev_disp.h @@ -0,0 +1,33 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __v05_01_dev_disp_h__ +#define __v05_01_dev_disp_h__ +#define NV_PDISP_POSTCOMP_LOADV_COUNTER(i) (0x0061A11C+(i)*1024) /* RW-4A */ +#define NV_PDISP_POSTCOMP_LOADV_COUNTER__SIZE_1 8 /* */ +#define NV_PDISP_POSTCOMP_LOADV_COUNTER_VALUE 31:0 /* RWIUF */ +#define NV_PDISP_POSTCOMP_LOADV_COUNTER_VALUE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_POSTCOMP_LOADV_COUNTER_VALUE_ZERO 0x00000000 /* RW--V */ +#define NV_PDISP_POSTCOMP_LOADV_COUNTER_VALUE_HW 0x00000000 /* R---V */ +#define NV_PDISP_POSTCOMP_LOADV_COUNTER_VALUE_SW 0x00000000 /* -W--V */ +#endif // __v05_01_dev_disp_h__ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_vm.h b/src/common/inc/swref/published/hopper/gh100/dev_vm.h index 396debdfeb..64c6379b0a 100644 --- a/src/common/inc/swref/published/hopper/gh100/dev_vm.h +++ b/src/common/inc/swref/published/hopper/gh100/dev_vm.h @@ -46,6 +46,11 @@ #define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR__SIZE_1 16 /* */ #define NV_VIRTUAL_FUNCTION_PRIV_TIMER(i) (0x2300+(i)*4) /* RW-4A */ #define NV_VIRTUAL_FUNCTION_PRIV_TIMER__SIZE_1 2 /* */ +#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO(i) (0x00010000+(i)*16) /* RW-4A */ +#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_HI(i) (0x00010004+(i)*16) /* RW-4A */ +#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_DATA(i) (0x00010008+(i)*16) /* RW-4A */ +#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL(i) (0x0001000C+(i)*16) /* RW-4A */ +#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL__SIZE_1 9 /* */ #define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO 0x00003108 /* RW-4R */ #define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO_BASE 31:12 /* RWXVF */ #define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_HI 0x0000310C /* RW-4R */ @@ -60,5 +65,4 @@ #define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR_VALUE 31:0 /* RWIVF */ #define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_VIRTUAL_FUNCTION_PRIV_MMU_PAGE_FAULT_CTRL 0x00003070 /* RW-4R */ - #endif // __gh100_dev_vm_h__ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_xtl_ep_pcfg_gpu.h b/src/common/inc/swref/published/hopper/gh100/dev_xtl_ep_pcfg_gpu.h index d0abbb4e16..e7ab802c14 100644 --- a/src/common/inc/swref/published/hopper/gh100/dev_xtl_ep_pcfg_gpu.h +++ b/src/common/inc/swref/published/hopper/gh100/dev_xtl_ep_pcfg_gpu.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -50,16 +50,21 @@ #define NV_EP_PCFG_GPU_MSI_64_HEADER_MSI_ENABLE 16:16 /* RWIVF */ #define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES 0x00000064 /* R--4R */ #define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_EXTENDED_TAG_FIELD_SUPPORTED 5:5 /* R-IVF */ +#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_FUNCTION_LEVEL_RESET_CAPABILITY 28:28 /* R-IVF */ +#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_FUNCTION_LEVEL_RESET_CAPABILITY_NOT_SUPPORTED 0x00000000 /* R-I-V */ +#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_FUNCTION_LEVEL_RESET_CAPABILITY_SUPPORTED 0x00000001 /* R---V */ #define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS 0x00000068 /* RW-4R */ #define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_ENABLE_RELAXED_ORDERING 4:4 /* RWIVF */ #define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_ENABLE_RELAXED_ORDERING_INIT 0x00000001 /* RWI-V */ #define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_EXTENDED_TAG_FIELD_ENABLE 8:8 /* RWIVF */ #define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_EXTENDED_TAG_FIELD_ENABLE_INIT 0x00000001 /* RWI-V */ #define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_ENABLE_NO_SNOOP 11:11 /* RWIVF */ +#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_INITIATE_FN_LVL_RST 15:15 /* RWIVF */ #define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_CORR_ERROR_DETECTED 16:16 /* RWIVF */ #define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_DETECTED 17:17 /* RWIVF */ #define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_FATAL_ERROR_DETECTED 18:18 /* RWIVF */ #define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_UNSUPP_REQUEST_DETECTED 19:19 /* RWIVF */ +#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_TRANSACTIONS_PENDING 21:21 /* R-IVF */ #define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_2 0x00000088 /* RW-4R */ #define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_2_ATOMIC_OP_REQUESTER_ENABLE 6:6 /* RWIVF */ #define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_2_ATOMIC_OP_REQUESTER_ENABLE_DEFAULT 0x00000000 /* RWI-V */ @@ -69,6 +74,9 @@ #define NV_EP_PCFG_GPU_MSIX_CAP_HEADER 0x000000B0 /* RW-4R */ #define NV_EP_PCFG_GPU_MSIX_CAP_HEADER_ENABLE 31:31 /* RWIVF */ #define NV_EP_PCFG_GPU_MSIX_CAP_HEADER_ENABLE_ENABLED 0x00000001 /* RW--V */ +#define NV_EP_PCFG_GPU_PF_RESIZE_BAR_CTRL 0x0000013C /* RW-4R */ +#define NV_EP_PCFG_GPU_PF_RESIZE_BAR_CTRL_BAR_SIZE 13:8 /* RWIVF */ +#define NV_EP_PCFG_GPU_PF_RESIZE_BAR_CTRL_BAR_SIZE_MIN 0x00000006 /* RW--V */ #define NV_EP_PCFG_GPU_UNCORRECTABLE_ERROR_STATUS 0x000001BC /* RW-4R */ #define NV_EP_PCFG_GPU_UNCORRECTABLE_ERROR_STATUS_DL_PROTOCOL_ERROR 4:4 /* RWCVF */ #define NV_EP_PCFG_GPU_UNCORRECTABLE_ERROR_STATUS_POISONED_TLP_RCVD 12:12 /* RWCVF */ diff --git a/src/common/inc/swref/published/maxwell/gm107/dev_nv_pcfg_xve1_addendum.h b/src/common/inc/swref/published/maxwell/gm107/dev_nv_pcfg_xve1_addendum.h new file mode 100644 index 0000000000..7b516474df --- /dev/null +++ b/src/common/inc/swref/published/maxwell/gm107/dev_nv_pcfg_xve1_addendum.h @@ -0,0 +1,55 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __dev_nv_pcfg_xve1_addendum_h__ +#define __dev_nv_pcfg_xve1_addendum_h__ + +#define NV_PCFG_XVE1_REGISTER_MAP_START_OFFSET 0x0008A000 + +/* + * _MAP has 1 bit set for each dword register. + * _COUNT has total number of set bits in _MAP. + */ +#define NV_PCFG_XVE1_REGISTER_VALID_COUNT 79 +#define NV_PCFG_XVE1_REGISTER_VALID_MAP { \ + /* 0x0008A000 */ 0xFFC1FFFF, 0x00001F9F, \ + /* 0x0008A100 */ 0x00FC07FF, 0x00000000, \ + /* 0x0008A200 */ 0x00000000, 0x00000000, \ + /* 0x0008A300 */ 0x00000000, 0x00000000, \ + /* 0x0008A400 */ 0x00000080, 0x00007808, \ + /* 0x0008A500 */ 0x00000000, 0x00000000, \ + /* 0x0008A600 */ 0x00000000, 0x00000000, \ + /* 0x0008A700 */ 0x0007FFFE } + +#define NV_PCFG_XVE1_REGISTER_WR_COUNT 34 +#define NV_PCFG_XVE1_REGISTER_WR_MAP { \ + /* 0x0008A000 */ 0x3EC1801A, 0x00000115, \ + /* 0x0008A100 */ 0x00FC007E, 0x00000000, \ + /* 0x0008A200 */ 0x00000000, 0x00000000, \ + /* 0x0008A300 */ 0x00000000, 0x00000000, \ + /* 0x0008A400 */ 0x00000080, 0x00006008, \ + /* 0x0008A500 */ 0x00000000, 0x00000000, \ + /* 0x0008A600 */ 0x00000000, 0x00000000, \ + /* 0x0008A700 */ 0x00000006 } + +#endif // {__dev_nv_pcfg_xve1_addendum_h__} diff --git a/src/common/inc/swref/published/maxwell/gm107/dev_nv_pcfg_xve_addendum.h b/src/common/inc/swref/published/maxwell/gm107/dev_nv_pcfg_xve_addendum.h new file mode 100644 index 0000000000..c9c83c136a --- /dev/null +++ b/src/common/inc/swref/published/maxwell/gm107/dev_nv_pcfg_xve_addendum.h @@ -0,0 +1,61 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __dev_nv_pcfg_xve_addendum_h__ +#define __dev_nv_pcfg_xve_addendum_h__ + +#define NV_PCFG_XVE_REGISTER_MAP_START_OFFSET 0x00088000 + +/* + * _MAP has 1 bit set for each dword register. + * _COUNT has total number of set bits in _MAP. + */ +#define NV_PCFG_XVE_REGISTER_VALID_COUNT 242 +#define NV_PCFG_XVE_REGISTER_VALID_MAP { \ + /* 0x00088000 */ 0xFFF1FFFF, 0x1003FF9F, \ + /* 0x00088100 */ 0x1FBA3C7F, 0x00000000, \ + /* 0x00088200 */ 0x03F00000, 0x00000000, \ + /* 0x00088300 */ 0x00000000, 0x00000000, \ + /* 0x00088400 */ 0x8007FFC0, 0x3F1F5807, \ + /* 0x00088500 */ 0x000000BF, 0x00000000, \ + /* 0x00088600 */ 0x0140AA1F, 0x00000000, \ + /* 0x00088700 */ 0x00000FFF, 0x00000000, \ + /* 0x00088800 */ 0xFFEFDF97, 0x02DAEDFF, \ + /* 0x00088900 */ 0xFFFFFFFF, 0x0000000F, \ + /* 0x00088A00 */ 0x077FFFFB } + +#define NV_PCFG_XVE_REGISTER_WR_COUNT 166 +#define NV_PCFG_XVE_REGISTER_WR_MAP { \ + /* 0x00088000 */ 0x3EF193FA, 0x1003C515, \ + /* 0x00088100 */ 0x1FBA0828, 0x00000000, \ + /* 0x00088200 */ 0x03200000, 0x00000000, \ + /* 0x00088300 */ 0x00000000, 0x00000000, \ + /* 0x00088400 */ 0x80007EC0, 0x3F075007, \ + /* 0x00088500 */ 0x000000BF, 0x00000000, \ + /* 0x00088600 */ 0x0140AA10, 0x00000000, \ + /* 0x00088700 */ 0x00000FFF, 0x00000000, \ + /* 0x00088800 */ 0x00445F83, 0x005AEDC0, \ + /* 0x00088900 */ 0xFFFC7806, 0x0000000F, \ + /* 0x00088A00 */ 0x077FFDFB } + +#endif // {__dev_nv_pcfg_xve_addendum_h__} diff --git a/src/common/inc/swref/published/maxwell/gm107/dev_nv_xve.h b/src/common/inc/swref/published/maxwell/gm107/dev_nv_xve.h index c4342f1677..b5610c4240 100644 --- a/src/common/inc/swref/published/maxwell/gm107/dev_nv_xve.h +++ b/src/common/inc/swref/published/maxwell/gm107/dev_nv_xve.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -43,6 +43,11 @@ #define NV_XVE_BAR0 0x00000010 /* RW-4R */ #define NV_XVE_BAR0_BASE_ADDRESS 31:24 /* RWIVF */ #define NV_XVE_BAR0_BASE_ADDRESS_INIT 0x00000000 /* RWI-V */ +#define NV_XVE_BAR1_LO 0x00000014 /* RW-4R */ +#define NV_XVE_BAR1_HI 0x00000018 /* RW-4R */ +#define NV_XVE_BAR2_LO 0x0000001C /* RW-4R */ +#define NV_XVE_BAR2_HI 0x00000020 /* RW-4R */ +#define NV_XVE_BAR3 0x00000024 /* RW-4R */ #define NV_XVE_SUBSYSTEM 0x0000002C /* R--4R */ #define NV_XVE_MSI_CTRL 0x00000068 /* RW-4R */ #define NV_XVE_MSI_CTRL_MSI 16:16 /* RWIVF */ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_nvlipt_lnk_ip.h b/src/common/inc/swref/published/nvswitch/ls10/dev_nvlipt_lnk_ip.h index 2117acae71..a4ac4bf5de 100644 --- a/src/common/inc/swref/published/nvswitch/ls10/dev_nvlipt_lnk_ip.h +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_nvlipt_lnk_ip.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -635,7 +635,4 @@ #define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_ALI_SUPPORT 28:28 /* RWIVF */ #define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_ALI_SUPPORT_SUPPORTED 0x00000001 /* RWI-V */ #define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_ALI_SUPPORT_NOT_SUPPORTED 0x00000000 /* RW--V */ -#define NV_NVLIPT_LNK_SCRATCH_WARM 0x000007c0 /* RW-4R */ -#define NV_NVLIPT_LNK_SCRATCH_WARM_DATA 31:0 /* RWEVF */ -#define NV_NVLIPT_LNK_SCRATCH_WARM_DATA_INIT 0xdeadbaad /* RWE-V */ #endif // __ls10_dev_nvlipt_lnk_ip_h__ diff --git a/src/common/inc/swref/published/pascal/gp100/dev_ctxsw_prog.h b/src/common/inc/swref/published/pascal/gp100/dev_ctxsw_prog.h new file mode 100644 index 0000000000..3eb91acb0f --- /dev/null +++ b/src/common/inc/swref/published/pascal/gp100/dev_ctxsw_prog.h @@ -0,0 +1,48 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gp100_dev_ctxsw_prog_h__ +#define __gp100_dev_ctxsw_prog_h__ +#define NV_CTXSW_GFXP_POOL_CTRL_BLK_PREEMPT_OFFSET 0x00000000 /* RW-4R */ +#define NV_CTXSW_GFXP_POOL_CTRL_BLK_SPILL_OFFSET 0x00000004 /* RW-4R */ +#define NV_CTXSW_GFXP_POOL_CTRL_BLK_CB_OFFSET 0x00000008 /* RW-4R */ +#define NV_CTXSW_GFXP_POOL_CTRL_BLK_PAGEPOOL_OFFSET 0x0000000c /* RW-4R */ +#define NV_CTXSW_GFXP_POOL_CTRL_BLK_SLICE_STRIDE 0x00000010 /* RW-4R */ +#define NV_CTXSW_GFXP_POOL_CTRL_BLK_GLOBAL_BETA_SIZE 0x00000014 /* RW-4R */ +#define NV_CTXSW_GFXP_POOL_CTRL_BLK_GLOBAL_ALPHA_SIZE 0x00000018 /* RW-4R */ +#define NV_CTXSW_GFXP_POOL_CTRL_BLK_GLOBAL_PAGEPOOL_SIZE 0x0000001c /* RW-4R */ +#define NV_CTXSW_GFXP_POOL_CTRL_BLK_GFXP_BETA_SIZE 0x00000020 /* RW-4R */ +#define NV_CTXSW_GFXP_POOL_CTRL_BLK_GFXP_ALPHA_SIZE 0x00000024 /* RW-4R */ +#define NV_CTXSW_GFXP_POOL_CTRL_BLK_GFXP_PAGEPOOL_SIZE 0x00000028 /* RW-4R */ +#define NV_CTXSW_GFXP_POOL_CTRL_BLK_GFXP_SPILL_SIZE 0x0000002c /* RW-4R */ +#define NV_CTXSW_GFXP_POOL_CTRL_BLK_NUM_SLICES 0x00000030 /* RW-4R */ +#define NV_CTXSW_GFXP_POOL_CTRL_BLK_SLICE_ARRAY1 0x00000034 /* RW-4R */ +#define NV_CTXSW_GFXP_POOL_CTRL_BLK_SLICE_ARRAY2 0x00000038 /* RW-4R */ +#define NV_CTXSW_GFXP_POOL_CTRL_BLK_SLICE_ARRAY3 0x0000003c /* RW-4R */ +#define NV_CTXSW_GFXP_POOL_CTRL_BLK_SLICE_ARRAY4 0x00000040 /* RW-4R */ +#define NV_CTXSW_GFXP_POOL_CTRL_BLK_RM_SLICE_ARRAY1 0x00000044 /* RW-4R */ +#define NV_CTXSW_GFXP_POOL_CTRL_BLK_RM_SLICE_ARRAY2 0x00000048 /* RW-4R */ +#define NV_CTXSW_GFXP_POOL_CTRL_BLK_RM_SLICE_ARRAY3 0x0000004c /* RW-4R */ +#define NV_CTXSW_GFXP_POOL_CTRL_BLK_RM_SLICE_ARRAY4 0x00000050 /* RW-4R */ +#define NV_CTXSW_GFXP_POOL_CTRL_BLK_MAX_SLICES 0x00000054 /* RW-4R */ +#endif // __gp100_dev_ctxsw_prog_h__ diff --git a/src/common/inc/swref/published/turing/tu102/dev_ctxsw_prog.h b/src/common/inc/swref/published/turing/tu102/dev_ctxsw_prog.h new file mode 100644 index 0000000000..e89e842a8d --- /dev/null +++ b/src/common/inc/swref/published/turing/tu102/dev_ctxsw_prog.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __tu102_dev_ctxsw_prog_h__ +#define __tu102_dev_ctxsw_prog_h__ +#define NV_CTXSW_GFXP_POOL_CTRL_BLK_GFXP_RTV_SIZE 0x00000058 /* RW-4R */ +#define NV_CTXSW_GFXP_POOL_CTRL_BLK_GLOBAL_RTV_SIZE 0x0000005c /* RW-4R */ +#define NV_CTXSW_GFXP_POOL_CTRL_BLK_RTV_OFFSET 0x00000060 /* RW-4R */ +#endif // __tu102_dev_ctxsw_prog_h__ diff --git a/src/common/inc/swref/published/turing/tu102/dev_nv_pcfg_xve_regmap.h b/src/common/inc/swref/published/turing/tu102/dev_nv_pcfg_xve_regmap.h new file mode 100644 index 0000000000..01288807e6 --- /dev/null +++ b/src/common/inc/swref/published/turing/tu102/dev_nv_pcfg_xve_regmap.h @@ -0,0 +1,69 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __dev_nv_pcfg_xve_regmap_h__ +#define __dev_nv_pcfg_xve_regmap_h__ + +#define NV_PCFG_XVE_REGISTER_MAP_START_OFFSET 0x00088000 + +/* + * _MAP has 1 bit set for each dword register. + * _COUNT has total number of set bits in _MAP. + */ +#define NV_PCFG_XVE_REGISTER_VALID_COUNT 424 +#define NV_PCFG_XVE_REGISTER_VALID_MAP { \ + /* 0x00088000 */ 0xFFF1FFFF, 0x139FFF9F, \ + /* 0x00088100 */ 0x1FBA3C7F, 0x00000000, \ + /* 0x00088200 */ 0x03F00000, 0x00000000, \ + /* 0x00088300 */ 0x00000000, 0x00000000, \ + /* 0x00088400 */ 0x8007FFC0, 0x3F1F5807, \ + /* 0x00088500 */ 0x000000BF, 0x00000000, \ + /* 0x00088600 */ 0x0140AA1F, 0x00000000, \ + /* 0x00088700 */ 0x0000FFFF, 0x00000000, \ + /* 0x00088800 */ 0xFFEFDFD7, 0x1EDAFFFF, \ + /* 0x00088900 */ 0xFFFFFFFF, 0x000FFFFF, \ + /* 0x00088A00 */ 0xFF7FFFFF, 0x0007FFFF, \ + /* 0x00088B00 */ 0x00000000, 0xFFFFF000, \ + /* 0x00088C00 */ 0x0007BFE7, 0xFFFFFFFC, \ + /* 0x00088D00 */ 0xFFFFFFFF, 0x03FF3FFF, \ + /* 0x00088E00 */ 0x00000007 } + +#define NV_PCFG_XVE_REGISTER_WR_COUNT 301 +#define NV_PCFG_XVE_REGISTER_WR_MAP { \ + /* 0x00088000 */ 0x3EF193FA, 0x1187C505, \ + /* 0x00088100 */ 0x1FBA0828, 0x00000000, \ + /* 0x00088200 */ 0x03200000, 0x00000000, \ + /* 0x00088300 */ 0x00000000, 0x00000000, \ + /* 0x00088400 */ 0x80007EC0, 0x3F075007, \ + /* 0x00088500 */ 0x000000BF, 0x00000000, \ + /* 0x00088600 */ 0x0140AA10, 0x00000000, \ + /* 0x00088700 */ 0x0000FFFF, 0x00000000, \ + /* 0x00088800 */ 0x00445FC3, 0x1C5AFFC0, \ + /* 0x00088900 */ 0xFFFC7804, 0x000FFFFF, \ + /* 0x00088A00 */ 0xFF7FFDFC, 0x00007FFF, \ + /* 0x00088B00 */ 0x00000000, 0xF8A54000, \ + /* 0x00088C00 */ 0x00003C01, 0x3FFFFFFC, \ + /* 0x00088D00 */ 0xFFFFFFFC, 0x039B2C3F, \ + /* 0x00088E00 */ 0x00000000 } + +#endif // {__dev_nv_pcfg_xve_regmap_h__} diff --git a/src/common/inc/swref/published/turing/tu102/dev_nv_xve.h b/src/common/inc/swref/published/turing/tu102/dev_nv_xve.h index 701cb2da8e..a5c43d5eba 100644 --- a/src/common/inc/swref/published/turing/tu102/dev_nv_xve.h +++ b/src/common/inc/swref/published/turing/tu102/dev_nv_xve.h @@ -23,18 +23,25 @@ #ifndef __tu102_dev_nv_xve_h__ #define __tu102_dev_nv_xve_h__ -#define NV_PCFG 0x00088FFF:0x00088000 /* RW--D */ -#define NV_XVE_MSIX_CAP_HDR 0x000000C8 /* RW-4R */ -#define NV_XVE_MSIX_CAP_HDR_ENABLE 31:31 /* RWIVF */ -#define NV_XVE_MSIX_CAP_HDR_ENABLE_ENABLED 0x00000001 /* RW--V */ -#define NV_XVE_MSIX_CAP_HDR_ENABLE_DISABLED 0x00000000 /* RWI-V */ -#define NV_XVE_SRIOV_CAP_HDR3 0x00000BD8 /* R--4R */ -#define NV_XVE_SRIOV_CAP_HDR3_TOTAL_VFS 31:16 /* R-EVF */ -#define NV_XVE_SRIOV_CAP_HDR5 0x00000BE0 /* R--4R */ -#define NV_XVE_SRIOV_CAP_HDR5_FIRST_VF_OFFSET 15:0 /* R-IVF */ -#define NV_XVE_SRIOV_CAP_HDR9 0x00000BF0 /* RW-4R */ -#define NV_XVE_SRIOV_CAP_HDR10 0x00000BF4 /* RW-4R */ -#define NV_XVE_SRIOV_CAP_HDR11_VF_BAR1_HI 0x00000BF8 /* RW-4R */ -#define NV_XVE_SRIOV_CAP_HDR12 0x00000BFC /* RW-4R */ -#define NV_XVE_SRIOV_CAP_HDR13_VF_BAR2_HI 0x00000C00 /* RW-4R */ +#define NV_PCFG 0x00088FFF:0x00088000 /* RW--D */ +#define NV_XVE_DEVICE_CAPABILITY 0x0000007C /* R--4R */ +#define NV_XVE_DEVICE_CAPABILITY_FUNCTION_LEVEL_RESET 28:28 /* R-XVF */ +#define NV_XVE_DEVICE_CAPABILITY_FUNCTION_LEVEL_RESET_NOT_SUPPORTED 0x00000000 /* R---V */ +#define NV_XVE_DEVICE_CAPABILITY_FUNCTION_LEVEL_RESET_SUPPORTED 0x00000001 /* R---V */ +#define NV_XVE_DEVICE_CONTROL_STATUS 0x00000080 /* RW-4R */ +#define NV_XVE_DEVICE_CONTROL_STATUS_INITIATE_FN_LVL_RST 15:15 /* RWIVF */ +#define NV_XVE_DEVICE_CONTROL_STATUS_TRANSACTIONS_PENDING 21:21 /* R-IVF */ +#define NV_XVE_MSIX_CAP_HDR 0x000000C8 /* RW-4R */ +#define NV_XVE_MSIX_CAP_HDR_ENABLE 31:31 /* RWIVF */ +#define NV_XVE_MSIX_CAP_HDR_ENABLE_ENABLED 0x00000001 /* RW--V */ +#define NV_XVE_MSIX_CAP_HDR_ENABLE_DISABLED 0x00000000 /* RWI-V */ +#define NV_XVE_SRIOV_CAP_HDR3 0x00000BD8 /* R--4R */ +#define NV_XVE_SRIOV_CAP_HDR3_TOTAL_VFS 31:16 /* R-EVF */ +#define NV_XVE_SRIOV_CAP_HDR5 0x00000BE0 /* R--4R */ +#define NV_XVE_SRIOV_CAP_HDR5_FIRST_VF_OFFSET 15:0 /* R-IVF */ +#define NV_XVE_SRIOV_CAP_HDR9 0x00000BF0 /* RW-4R */ +#define NV_XVE_SRIOV_CAP_HDR10 0x00000BF4 /* RW-4R */ +#define NV_XVE_SRIOV_CAP_HDR11_VF_BAR1_HI 0x00000BF8 /* RW-4R */ +#define NV_XVE_SRIOV_CAP_HDR12 0x00000BFC /* RW-4R */ +#define NV_XVE_SRIOV_CAP_HDR13_VF_BAR2_HI 0x00000C00 /* RW-4R */ #endif // __tu102_dev_nv_xve_h__ diff --git a/src/common/inc/swref/published/turing/tu102/dev_vm.h b/src/common/inc/swref/published/turing/tu102/dev_vm.h index bad7834450..d444ce272b 100644 --- a/src/common/inc/swref/published/turing/tu102/dev_vm.h +++ b/src/common/inc/swref/published/turing/tu102/dev_vm.h @@ -210,4 +210,5 @@ #define NV_VIRTUAL_FUNCTION_PRIV_DOORBELL 0x2200 /* -W-4R */ #define NV_VIRTUAL_FUNCTION_DOORBELL 0x30090 /* -W-4R */ #define NV_VIRTUAL_FUNCTION_ERR_CONT 0x30094 /* R--4R */ +#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL__SIZE_1 6 /* */ #endif // __tu102_dev_vm_h__ diff --git a/src/common/modeset/hdmipacket/nvhdmipkt.c b/src/common/modeset/hdmipacket/nvhdmipkt.c index c209711db2..4960430c4d 100644 --- a/src/common/modeset/hdmipacket/nvhdmipkt.c +++ b/src/common/modeset/hdmipacket/nvhdmipkt.c @@ -49,6 +49,8 @@ #include "class/clc67d.h" #include "class/clc770.h" +#include "hdmi_spec.h" + // Class hierarchy structure typedef struct tagNVHDMIPKT_CLASS_HIERARCHY { @@ -85,7 +87,7 @@ typedef struct tagNVHDMIPKT_CLASS_HIERARCHY ************************************************************************************************/ static const NVHDMIPKT_CLASS_HIERARCHY hierarchy[] = { - {// Index 0==NVHDMIPKT_0073_CLASS + [NVHDMIPKT_0073_CLASS] = {// Index 0==NVHDMIPKT_0073_CLASS NVHDMIPKT_0073_CLASS, // classId NVHDMIPKT_0073_CLASS, // parentClassId NV_TRUE, // isRootClass @@ -95,7 +97,7 @@ static const NVHDMIPKT_CLASS_HIERARCHY hierarchy[] = 0, // displayClass 0 // coreDmaClass }, - {// Index 1==NVHDMIPKT_9171_CLASS + [NVHDMIPKT_9171_CLASS] = {// Index 1==NVHDMIPKT_9171_CLASS NVHDMIPKT_9171_CLASS, // classId NVHDMIPKT_9171_CLASS, // parentClassId NV_TRUE, // isRootClass @@ -105,7 +107,7 @@ static const NVHDMIPKT_CLASS_HIERARCHY hierarchy[] = NV9170_DISPLAY, // displayClass NV917D_CORE_CHANNEL_DMA // coreDmaClass }, - {// Index 2==NVHDMIPKT_9271_CLASS + [NVHDMIPKT_9271_CLASS] = {// Index 2==NVHDMIPKT_9271_CLASS NVHDMIPKT_9271_CLASS, // classId NVHDMIPKT_9171_CLASS, // parentClassId NV_FALSE, // isRootClass @@ -115,7 +117,7 @@ static const NVHDMIPKT_CLASS_HIERARCHY hierarchy[] = NV9270_DISPLAY, // displayClass NV927D_CORE_CHANNEL_DMA // coreDmaClass }, - {// Index 3==NVHDMIPKT_9471_CLASS + [NVHDMIPKT_9471_CLASS] = {// Index 3==NVHDMIPKT_9471_CLASS NVHDMIPKT_9471_CLASS, // classId NVHDMIPKT_9171_CLASS, // parentClassId NV_FALSE, // isRootClass @@ -125,7 +127,7 @@ static const NVHDMIPKT_CLASS_HIERARCHY hierarchy[] = NV9470_DISPLAY, // displayClass NV947D_CORE_CHANNEL_DMA // coreDmaClass }, - {// Index 4==NVHDMIPKT_9571_CLASS + [NVHDMIPKT_9571_CLASS] = {// Index 4==NVHDMIPKT_9571_CLASS NVHDMIPKT_9571_CLASS, // classId NVHDMIPKT_9171_CLASS, // parentClassId NV_FALSE, // isRootClass @@ -135,7 +137,7 @@ static const NVHDMIPKT_CLASS_HIERARCHY hierarchy[] = NV9570_DISPLAY, // displayClass NV957D_CORE_CHANNEL_DMA // coreDmaClass }, - {// Index 5==NVHDMIPKT_C371_CLASS + [NVHDMIPKT_C371_CLASS] = {// Index 5==NVHDMIPKT_C371_CLASS NVHDMIPKT_C371_CLASS, // classId NVHDMIPKT_9171_CLASS, // parentClassId NV_FALSE, // isRootClass @@ -145,7 +147,7 @@ static const NVHDMIPKT_CLASS_HIERARCHY hierarchy[] = NVC370_DISPLAY, // displayClass NVC37D_CORE_CHANNEL_DMA // coreDmaClass }, - {// Index 6==NVHDMIPKT_C571_CLASS + [NVHDMIPKT_C571_CLASS] = {// Index 6==NVHDMIPKT_C571_CLASS // Note that Turing (C57x) has a distinct displayClass and coreDmaClass, // but it inherits the _DISP_SF_USER class from Volta (C37x). We call this // NVHDMIPKT_C571_CLASS, but reuse initInterface()/constructor()/destructor() @@ -159,7 +161,7 @@ static const NVHDMIPKT_CLASS_HIERARCHY hierarchy[] = NVC570_DISPLAY, // displayClass NVC57D_CORE_CHANNEL_DMA // coreDmaClass }, - {// Index 7==NVHDMIPKT_C671_CLASS + [NVHDMIPKT_C671_CLASS] = {// Index 7==NVHDMIPKT_C671_CLASS NVHDMIPKT_C671_CLASS, // classId NVHDMIPKT_9171_CLASS, // parentClassId NV_FALSE, // isRootClass @@ -169,7 +171,7 @@ static const NVHDMIPKT_CLASS_HIERARCHY hierarchy[] = NVC670_DISPLAY, // displayClass NVC67D_CORE_CHANNEL_DMA // coreDmaClass }, - {// Index 8==NVHDMIPKT_C771_CLASS + [NVHDMIPKT_C771_CLASS] = {// Index 8==NVHDMIPKT_C771_CLASS NVHDMIPKT_C771_CLASS, // classId NVHDMIPKT_C671_CLASS, // parentClassId NV_FALSE, // isRootClass @@ -233,6 +235,23 @@ NvHdmiPkt_PacketWrite(NvHdmiPkt_Handle libHandle, return NVHDMIPKT_INVALID_ARG; } + HDMI_PACKET_TYPE infoframeType = pPacket[0]; // header byte 0 is packet type + // Lower bound check. Since actual infoframe size varies depending on the infoframe packet being sent, + // check all supported infoframe types and their expected sizes. This is not a strict == check becuase they may/may not need + // additional checksum byte (library clients take care of adding checksum byte if needed) + if (((infoframeType == hdmi_pktType_GeneralControl) && (packetLen < 6)) || + ((infoframeType == hdmi_pktType_GamutMetadata) && (packetLen < sizeof(NVT_GAMUT_METADATA))) || + ((infoframeType == hdmi_pktType_ExtendedMetadata) && (packetLen < sizeof(NVT_EXTENDED_METADATA_PACKET_INFOFRAME)))|| + ((infoframeType == hdmi_pktType_VendorSpecInfoFrame) && (packetLen < 8)) || + ((infoframeType == hdmi_pktType_AviInfoFrame) && (packetLen < sizeof(NVT_VIDEO_INFOFRAME))) || + ((infoframeType == hdmi_pktType_SrcProdDescInfoFrame) && (packetLen < sizeof(NVT_SPD_INFOFRAME))) || + ((infoframeType == hdmi_pktType_DynamicRangeMasteringInfoFrame) && (packetLen < sizeof(NVT_HDR_INFOFRAME)))) + // Unused: hdmi_pktType_AudioClkRegeneration + // Unused: hdmi_pktType_MpegSrcInfoFrame + { + NvHdmiPkt_Print(pClass, "WARNING - packet length too small for infoframe type %d check payload ", infoframeType); + } + return pClass->hdmiPacketWrite(pClass, subDevice, displayId, diff --git a/src/common/modeset/hdmipacket/nvhdmipkt.h b/src/common/modeset/hdmipacket/nvhdmipkt.h index 8371b6402c..deb9908572 100644 --- a/src/common/modeset/hdmipacket/nvhdmipkt.h +++ b/src/common/modeset/hdmipacket/nvhdmipkt.h @@ -56,7 +56,7 @@ typedef enum NVHDMIPKT_TIMEOUT = 4, NVHDMIPKT_ERR_GENERAL = 5, NVHDMIPKT_INSUFFICIENT_BANDWIDTH = 6, - NVHDMIPKT_RETRY = 7 + NVHDMIPKT_RETRY = 7, } NVHDMIPKT_RESULT; // NVHDMIPKT_TYPE: HDMI Packet Enums @@ -69,14 +69,13 @@ typedef enum _NVHDMIPKT_TYPE NVHDMIPKT_TYPE_GENERAL_CONTROL = 3, // GCP NVHDMIPKT_TYPE_VENDOR_SPECIFIC_INFOFRAME = 4, // VSI NVHDMIPKT_TYPE_AUDIO_INFOFRAME = 5, // Audio InfoFrame - NVHDMIPKT_TYPE_EXTENDED_METADATA_PACKET = 6, // Extended Metadata Packet (HDMI 2.1) - NVHDMIPKT_TYPE_SHARED_GENERIC1 = 7, // ADA+ Specifc shared generic infoframe 1~6 - NVHDMIPKT_TYPE_SHARED_GENERIC2 = 8, - NVHDMIPKT_TYPE_SHARED_GENERIC3 = 9, - NVHDMIPKT_TYPE_SHARED_GENERIC4 = 10, - NVHDMIPKT_TYPE_SHARED_GENERIC5 = 11, - NVHDMIPKT_TYPE_SHARED_GENERIC6 = 12, - NVHDMIPKT_INVALID_PKT_TYPE = 13 + NVHDMIPKT_TYPE_SHARED_GENERIC1 = 6, // ADA+ Specifc shared generic infoframe 1~6 + NVHDMIPKT_TYPE_SHARED_GENERIC2 = 7, + NVHDMIPKT_TYPE_SHARED_GENERIC3 = 8, + NVHDMIPKT_TYPE_SHARED_GENERIC4 = 9, + NVHDMIPKT_TYPE_SHARED_GENERIC5 = 10, + NVHDMIPKT_TYPE_SHARED_GENERIC6 = 11, + NVHDMIPKT_INVALID_PKT_TYPE = 12 } NVHDMIPKT_TYPE; // Hdmi packet TransmitControl defines. These definitions reflect the diff --git a/src/common/modeset/hdmipacket/nvhdmipkt_0073.c b/src/common/modeset/hdmipacket/nvhdmipkt_0073.c index 07cfc7b224..cad6bec3d0 100644 --- a/src/common/modeset/hdmipacket/nvhdmipkt_0073.c +++ b/src/common/modeset/hdmipacket/nvhdmipkt_0073.c @@ -337,10 +337,10 @@ hdmiQueryFRLConfigDummy(NVHDMIPKT_CLASS *pThis, NVHDMIPKT_RESULT hdmiSetFRLConfigDummy(NVHDMIPKT_CLASS *pThis, - NvU32 subDevice, - NvU32 displayId, - NvBool bFakeLt, - HDMI_FRL_CONFIG *pFRLConfig) + NvU32 subDevice, + NvU32 displayId, + NvBool bFakeLt, + HDMI_FRL_CONFIG *pFRLConfig) { NvHdmiPkt_Print(pThis, "ERROR - Dummy function hdmiSetFRLConfigDummy called. " "Should never be called."); @@ -350,8 +350,8 @@ hdmiSetFRLConfigDummy(NVHDMIPKT_CLASS *pThis, NVHDMIPKT_RESULT hdmiClearFRLConfigDummy(NVHDMIPKT_CLASS *pThis, - NvU32 subDevice, - NvU32 displayId) + NvU32 subDevice, + NvU32 displayId) { NvHdmiPkt_Print(pThis, "ERROR - Dummy function hdmiClearFRLConfigDummy called. " "Should never be called."); diff --git a/src/common/modeset/hdmipacket/nvhdmipkt_9171.c b/src/common/modeset/hdmipacket/nvhdmipkt_9171.c index 86ac625e6f..46537360b0 100644 --- a/src/common/modeset/hdmipacket/nvhdmipkt_9171.c +++ b/src/common/modeset/hdmipacket/nvhdmipkt_9171.c @@ -36,6 +36,9 @@ #include "ctrl/ctrl0073/ctrl0073specific.h" #define NVHDMIPKT_9171_INVALID_PKT_TYPE ((NV9171_SF_HDMI_INFO_IDX_VSI) + 1) +#define NVHDMIPKT_CTAIF_MAX_PKT_BYTES 31 // 3 bytes header + 28 bytes data (CTA infoframe max payload size) +#define NVHDMIPKT_9171_MAX_PKT_BYTES_AVI 17 // 3 bytes header + 14 bytes data + NVHDMIPKT_RESULT hdmiPacketWrite9171(NVHDMIPKT_CLASS* pThis, NvU32 subDevice, @@ -53,6 +56,14 @@ hdmiPacketCtrl9171(NVHDMIPKT_CLASS* pThis, NvU32 head, NVHDMIPKT_TYPE packetType, NVHDMIPKT_TC transmitControl); + +void +hdmiWriteAviPacket9171(NVHDMIPKT_CLASS* pThis, + NvU32* pBaseReg, + NvU32 head, + NvU32 packetLen, + NvU8 const *const pPacket); + /* * hdmiReadPacketStatus9171 */ @@ -135,7 +146,7 @@ hdmiWritePacketCtrl9171(NVHDMIPKT_CLASS* pThis, /* * hdmiWriteAviPacket9171 */ -static void +void hdmiWriteAviPacket9171(NVHDMIPKT_CLASS* pThis, NvU32* pBaseReg, NvU32 head, @@ -144,6 +155,12 @@ hdmiWriteAviPacket9171(NVHDMIPKT_CLASS* pThis, { NvU32 data = 0; + if (packetLen > NVHDMIPKT_9171_MAX_PKT_BYTES_AVI) + { + NvHdmiPkt_Print(pThis, "ERROR - input AVI packet length incorrect. Write will be capped to max allowable bytes"); + NvHdmiPkt_Assert(0); + } + data = REG_RD32(pBaseReg, NV9171_SF_HDMI_AVI_INFOFRAME_HEADER(head)); data = FLD_SET_DRF_NUM(9171, _SF_HDMI_AVI_INFOFRAME_HEADER, _HB0, pPacket[0], data); data = FLD_SET_DRF_NUM(9171, _SF_HDMI_AVI_INFOFRAME_HEADER, _HB1, pPacket[1], data); @@ -512,41 +529,6 @@ checkPacketStatus(NVHDMIPKT_CLASS* pThis, return result; } -static NVHDMIPKT_RESULT -validateInputPacketLength(NvU32 pktType9171, - NvU32 packetLen, - NvU8 const *const pPacketIn) -{ - NVHDMIPKT_RESULT result = NVHDMIPKT_SUCCESS; - HDMI_PACKET_TYPE infoframeType = pPacketIn[0]; - - // Lower bound check. Since actual infoframe size varies depending on the infoframe packet being sent, - // check all supported infoframe types and their expected sizes. This is not a strict == check becuase they may/may not need - // additional checksum byte (library clients take care of adding checksum byte if needed) - if (((infoframeType == hdmi_pktType_GeneralControl) && (packetLen < 6)) || - ((infoframeType == hdmi_pktType_GamutMetadata) && (packetLen < sizeof(NVT_GAMUT_METADATA))) || - ((infoframeType == hdmi_pktType_ExtendedMetadata) && (packetLen < sizeof(NVT_EXTENDED_METADATA_PACKET_INFOFRAME)))|| - ((infoframeType == hdmi_pktType_VendorSpecInfoFrame) && (packetLen < 8)) || - ((infoframeType == hdmi_pktType_AviInfoFrame) && (packetLen < sizeof(NVT_VIDEO_INFOFRAME))) || - ((infoframeType == hdmi_pktType_SrcProdDescInfoFrame) && (packetLen < sizeof(NVT_SPD_INFOFRAME))) || - ((infoframeType == hdmi_pktType_DynamicRangeMasteringInfoFrame) && (packetLen < sizeof(NVT_HDR_INFOFRAME)))) - // Unused: hdmi_pktType_AudioClkRegeneration - // Unused: hdmi_pktType_MpegSrcInfoFrame - { - result = NVHDMIPKT_INVALID_ARG; - } - - // Upper bound check. Check against number of bytes possible on the hw infoframe unit - if (((pktType9171 == NV9171_SF_HDMI_INFO_IDX_AVI_INFOFRAME) && (packetLen > 17)) || // 3 bytes header + 14 bytes data - ((pktType9171 == NV9171_SF_HDMI_INFO_IDX_GENERIC_INFOFRAME) && (packetLen > 31)) || // 3 bytes header + 28 bytes data - ((pktType9171 == NV9171_SF_HDMI_INFO_IDX_VSI) && (packetLen > 31))) // 3 bytes header + 28 bytes data - { - result = NVHDMIPKT_INVALID_ARG; - } - - return result; -} - /* * hdmiPacketWrite9171 */ @@ -567,7 +549,7 @@ hdmiPacketWrite9171(NVHDMIPKT_CLASS* pThis, NV0073_CTRL_SPECIFIC_CTRL_HDMI_PARAMS params = {0}; // packetIn can be of varying size. Use a fixed max size buffer for programing hw units to prevent out of bounds access - NvU8 pPacket[31] = {0}; + NvU8 pPacket[NVHDMIPKT_CTAIF_MAX_PKT_BYTES] = {0}; if (pBaseReg == 0 || head >= NV9171_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1 || packetLen == 0 || pPacketIn == 0 || pktType9171 == NVHDMIPKT_9171_INVALID_PKT_TYPE) @@ -577,11 +559,11 @@ hdmiPacketWrite9171(NVHDMIPKT_CLASS* pThis, goto hdmiPacketWrite9171_exit; } - if ((result = validateInputPacketLength(pktType9171, packetLen, pPacketIn)) != NVHDMIPKT_SUCCESS) + if (packetLen > NVHDMIPKT_CTAIF_MAX_PKT_BYTES) { - NvHdmiPkt_Print(pThis, "ERROR - input packet length incorrect %d", packetLen); + NvHdmiPkt_Print(pThis, "ERROR - input packet length incorrect %d Packet write will be capped to max allowable bytes", packetLen); + packetLen = NVHDMIPKT_CTAIF_MAX_PKT_BYTES; NvHdmiPkt_Assert(0); - goto hdmiPacketWrite9171_exit; } // input packet looks ok to use, copy over the bytes diff --git a/src/common/modeset/hdmipacket/nvhdmipkt_C771.c b/src/common/modeset/hdmipacket/nvhdmipkt_C771.c index 34064caa5c..0fabffa445 100644 --- a/src/common/modeset/hdmipacket/nvhdmipkt_C771.c +++ b/src/common/modeset/hdmipacket/nvhdmipkt_C771.c @@ -32,6 +32,8 @@ #include "class/clc771.h" +#define NVHDMIPKT_C771_MAX_PKT_BYTES_AVI 21 // 3 bytes header + 18 bytes payload + extern NVHDMIPKT_RESULT hdmiPacketWrite9171(NVHDMIPKT_CLASS* pThis, NvU32 subDevice, NvU32 displayId, diff --git a/src/common/modeset/timing/displayid20.h b/src/common/modeset/timing/displayid20.h index 1bfcace0f5..823a1bc73f 100644 --- a/src/common/modeset/timing/displayid20.h +++ b/src/common/modeset/timing/displayid20.h @@ -65,7 +65,7 @@ typedef struct _tagDISPLAYID_2_0_SECTION_HEADER NvU8 product_type:4; // Display Product Primary Use Case NvU8 reserved:4; // RESERVED NvU8 extension_count; // Total extension count. -} DISPLAYID_2_0_SECTION_HEADER; +} DISPLAYID_2_0_SECTION_HEADER; typedef struct _tagDISPLAYID_2_0_SECTION { @@ -79,7 +79,7 @@ typedef struct _tagDISPLAYID_2_0_SECTION #define DISPLAYID_2_0_PROD_EXTENSION 0 // Extension (same primary use case as base section) #define DISPLAYID_2_0_PROD_TEST 1 // Test Structure/Test Equipment -#define DISPLAYID_2_0_PROD_GENERIC_DISPLAY 2 // None of the listed primary use cases; generic display +#define DISPLAYID_2_0_PROD_GENERIC_DISPLAY 2 // None of the listed primary use cases; generic display #define DISPLAYID_2_0_PROD_TELEVISION 3 // Television (TV) display #define DISPLAYID_2_0_PROD_DESKTOP_PRODUCTIVITY_DISPLAY 4 // Desktop productivity display #define DISPLAYID_2_0_PROD_DESKTOP_GAMING_DISPLAY 5 // Desktop gaming display @@ -95,25 +95,26 @@ typedef struct _tagDISPLAYID_2_0_DATA_BLOCK_HEADER NvU8 data_bytes; // number of payload bytes in Block [ 0, 248] } DISPLAYID_2_0_DATA_BLOCK_HEADER; -#define DISPLAYID_2_0_BLOCK_TYPE_PRODUCT_IDENTITY 0x20 -#define DISPLAYID_2_0_BLOCK_TYPE_DISPLAY_PARAM 0x21 -#define DISPLAYID_2_0_BLOCK_TYPE_TIMING_7 0x22 -#define DISPLAYID_2_0_BLOCK_TYPE_TIMING_8 0x23 -#define DISPLAYID_2_0_BLOCK_TYPE_TIMING_9 0x24 -#define DISPLAYID_2_0_BLOCK_TYPE_RANGE_LIMITS 0x25 -#define DISPLAYID_2_0_BLOCK_TYPE_INTERFACE_FEATURES 0x26 -#define DISPLAYID_2_0_BLOCK_TYPE_STEREO 0x27 -#define DISPLAYID_2_0_BLOCK_TYPE_TILED_DISPLAY 0x28 -#define DISPLAYID_2_0_BLOCK_TYPE_CONTAINER_ID 0x29 -#define DISPLAYID_2_0_BLOCK_TYPE_TIMING_10 0x2A -#define DISPLAYID_2_0_BLOCK_TYPE_ADAPTIVE_SYNC 0x2B -#define DISPLAYID_2_0_BLOCK_TYPE_ARVR_HMD 0x2C -#define DISPLAYID_2_0_BLOCK_TYPE_ARVR_LAYER 0x2D -// 0x7D - 0x2E RESERVED for Additional VESA-defined Data Blocks +#define DISPLAYID_2_0_BLOCK_TYPE_PRODUCT_IDENTITY 0x20 +#define DISPLAYID_2_0_BLOCK_TYPE_DISPLAY_PARAM 0x21 +#define DISPLAYID_2_0_BLOCK_TYPE_TIMING_7 0x22 +#define DISPLAYID_2_0_BLOCK_TYPE_TIMING_8 0x23 +#define DISPLAYID_2_0_BLOCK_TYPE_TIMING_9 0x24 +#define DISPLAYID_2_0_BLOCK_TYPE_RANGE_LIMITS 0x25 +#define DISPLAYID_2_0_BLOCK_TYPE_INTERFACE_FEATURES 0x26 +#define DISPLAYID_2_0_BLOCK_TYPE_STEREO 0x27 +#define DISPLAYID_2_0_BLOCK_TYPE_TILED_DISPLAY 0x28 +#define DISPLAYID_2_0_BLOCK_TYPE_CONTAINER_ID 0x29 +#define DISPLAYID_2_0_BLOCK_TYPE_TIMING_10 0x2A +#define DISPLAYID_2_0_BLOCK_TYPE_ADAPTIVE_SYNC 0x2B +#define DISPLAYID_2_0_BLOCK_TYPE_ARVR_HMD 0x2C +#define DISPLAYID_2_0_BLOCK_TYPE_ARVR_LAYER 0x2D +#define DISPLAYID_2_0_BLOCK_TYPE_BRIGHTNESS_LUMINANCE_RANGE 0x2E +// 0x7D - 0x2F RESERVED for Additional VESA-defined Data Blocks #define DISPLAYID_2_0_BLOCK_TYPE_VENDOR_SPEC 0x7E // 0x80 - 0x7F RESERVED #define DISPLAYID_2_0_BLOCK_TYPE_CTA_DATA 0x81 -// 0xFF - 0x82 RESERVED for additional data blocks related to external standards organization(s). +// 0xFF - 0x82 RESERVED for additional data blocks related to external standards organization(s). #define DISPLAYID_2_0_PRODUCT_NAME_STRING_MAX_LEN ((0xFB - 0xF) + 1) @@ -184,7 +185,7 @@ typedef struct _tagDISPLAYID_2_0_DISPLAY_PARAM_BLOCK DISPLAYID_2_0_COLOR_CHROMATICITY primary_color_3_chromaticity; DISPLAYID_2_0_COLOR_CHROMATICITY white_point_chromaticity; NvU8 max_luminance_full_coverage[2]; - NvU8 max_luminance_1_percent_rectangular_coverage[2]; + NvU8 max_luminance_10_percent_rectangular_coverage[2]; NvU8 min_luminance[2]; struct { @@ -525,7 +526,7 @@ typedef struct _tagDISPLAYID_2_0_STEREO_INTERFACE_BLOCK_HEADER NvU8 type; NvU8 revision:3; NvU8 reserved:3; - NvU8 stereo_timing_support:2; + NvU8 stereo_timing_support:2; } DISPLAYID_2_0_STEREO_INTERFACE_BLOCK_HEADER; typedef struct _tagDISPLAYID_2_0_STEREO_TIMING_DESCRIPTOR @@ -692,7 +693,7 @@ typedef struct _tagDISPLAYID_2_0_ADAPTIVE_SYNC_DESCRIPTOR NvU8 successive_frame_dec_tolerance : 1; NvU8 reserved : 2; } operation_range_info; - + // 6.2 format (six integer bits and two fractional bits) // six integer bits == 0 - 63ms // two fractional bits == 0.00(00), 0.25(01b),0.50(10), 0.75(11b) @@ -704,9 +705,9 @@ typedef struct _tagDISPLAYID_2_0_ADAPTIVE_SYNC_DESCRIPTOR NvU8 max_rr_9_8 : 2; NvU8 reserved : 6; } max_refresh_rate; - + // same as max_single_frame_inc expression - NvU8 max_single_frame_dec; + NvU8 max_single_frame_dec; } DISPLAYID_2_0_ADAPTIVE_SYNC_DESCRIPTOR; typedef struct _tagDISPLAYID_2_0_ADAPTIVE_SYNC_BLOCK @@ -715,6 +716,16 @@ typedef struct _tagDISPLAYID_2_0_ADAPTIVE_SYNC_BLOCK DISPLAYID_2_0_ADAPTIVE_SYNC_DESCRIPTOR descriptors[DISPLAYID_2_0_ADAPTIVE_SYNC_DETAILED_TIMING_COUNT]; } DISPLAYID_2_0_ADAPTIVE_SYNC_BLOCK; +// Payload value as defined in DID2.1 spec +#define DISPLAYID_2_0_BRIGHTNESS_LUMINANCE_RANGE_BLOCK_PAYLOAD_LENGTH 6 +typedef struct _tagDISPLAYID_2_0_BRIGHTNESS_LUMINANCE_RANGE_BLOCK +{ + DISPLAYID_2_0_DATA_BLOCK_HEADER header; + NvU16 min_sdr_luminance; // 0x03 ~ 0x04 + NvU16 max_sdr_luminance; // 0x05 ~ 0x06 + NvU16 max_boost_sdr_luminance; // 0x07 ~ 0x08 +} DISPLAYID_2_0_BRIGHTNESS_LUMINANCE_RANGE_BLOCK; + typedef struct _tagDISPLAYID_2_0_VENDOR_SPECIFIC_BLOCK { DISPLAYID_2_0_DATA_BLOCK_HEADER header; @@ -732,8 +743,43 @@ typedef struct _tagDISPLAYID_2_0_CTA_BLOCK #pragma pack() #endif +#ifdef __cplusplus +extern "C" { +#endif + // Entry point functions both used in DID20 and DID20ext NVT_STATUS parseDisplayId20DataBlock(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); NvU8 computeDisplayId20SectionCheckSum(const NvU8 *pSectionBytes, NvU32 length); -#endif // __DISPLAYID20_H_ +// DisplayID20 as EDID extension entry point function +NVT_STATUS parseDisplayId20EDIDExtSection(DISPLAYID_2_0_SECTION *section, NVT_EDID_INFO *pEdidInfo); + +// DisplayID20 Entry point functions +NVT_STATUS parseDisplayId20BaseSection(const DISPLAYID_2_0_SECTION *pSection, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); +NVT_STATUS parseDisplayId20SectionDataBlocks(const DISPLAYID_2_0_SECTION *pSection, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); +NVT_STATUS parseDisplayId20ExtensionSection(const DISPLAYID_2_0_SECTION *pSection, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); + +// DisplayID20 Data Block Tag Allocation +NVT_STATUS parseDisplayId20ProductIdentity(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x20 Product Identificaton +NVT_STATUS parseDisplayId20DisplayParam(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x21 Display Parameters +NVT_STATUS parseDisplayId20Timing7(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x22 Type VII Timing - Detailed Timing +NVT_STATUS parseDisplayId20Timing8(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x23 Type VIII Timing - Enumerated Timing +NVT_STATUS parseDisplayId20Timing9(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x24 Type IX Timing - Formula-based +NVT_STATUS parseDisplayId20RangeLimit(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x25 Dynamic Video Timing Range Limits +NVT_STATUS parseDisplayId20DisplayInterfaceFeatures(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x26 Display Interface Features +NVT_STATUS parseDisplayId20Stereo(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x27 Stereo Display Interface +NVT_STATUS parseDisplayId20TiledDisplay(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x28 Tiled Display Topology +NVT_STATUS parseDisplayId20ContainerId(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x29 ContainerID +NVT_STATUS parseDisplayId20Timing10(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x2A Type X Timing - Formula-based Timing +NVT_STATUS parseDisplayId20AdaptiveSync(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x2B Adaptive-Sync +NVT_STATUS parseDisplayId20ARVRHMD(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x2C ARVR HMD +NVT_STATUS parseDisplayId20ARVRLayer(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x2D ARVR Layer +NVT_STATUS parseDisplayId20BrightnessLuminanceRange(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x2E Brightness Luminance Range +NVT_STATUS parseDisplayId20VendorSpecific(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x7E Vendor-specific +NVT_STATUS parseDisplayId20CtaData(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x81 CTA DisplayID + +#ifdef __cplusplus +} +#endif +#endif // __DISPLAYID20_H_1 + diff --git a/src/common/modeset/timing/dpsdp.h b/src/common/modeset/timing/dpsdp.h index a29dc87790..ee987703e1 100644 --- a/src/common/modeset/timing/dpsdp.h +++ b/src/common/modeset/timing/dpsdp.h @@ -260,6 +260,7 @@ typedef struct tagDPSDP_DP_PR_VSC_SDP_DESCRIPTOR NvU8 db6; NvU8 db7; // DB8 - DB15 are undefined in DP 1.3 spec. + NvU8 db8; NvU8 db9; NvU8 db10; NvU8 db11; diff --git a/src/common/modeset/timing/nvt_displayid20.c b/src/common/modeset/timing/nvt_displayid20.c index c97b9e88fc..38ea670e0b 100644 --- a/src/common/modeset/timing/nvt_displayid20.c +++ b/src/common/modeset/timing/nvt_displayid20.c @@ -30,38 +30,13 @@ #include "nvBinSegment.h" #include "nvmisc.h" -#include "nvtiming.h" #include "nvtiming_pvt.h" #include "displayid20.h" PUSH_SEGMENTS -// DisplayID20 Entry point functions -static NVT_STATUS parseDisplayId20BaseSection(const DISPLAYID_2_0_SECTION *pSection, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); -static NVT_STATUS parseDisplayId20SectionDataBlocks(const DISPLAYID_2_0_SECTION *pSection, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); -static NVT_STATUS parseDisplayId20ExtensionSection(const DISPLAYID_2_0_SECTION *pSection, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); - -// DisplayID20 Data Block Tag Alloction -static NVT_STATUS parseDisplayId20ProductIdentity(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x20 Product Identificaton -static NVT_STATUS parseDisplayId20DisplayParam(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x21 Display Parameters -static NVT_STATUS parseDisplayId20Timing7(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x22 Type VII Timing - Detailed Timing -static NVT_STATUS parseDisplayId20Timing8(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x23 Type VIII Timing - Enumerated Timing -static NVT_STATUS parseDisplayId20Timing9(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x24 Type IX Timing - Formula-based -static NVT_STATUS parseDisplayId20RangeLimit(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x25 Dynamic Video Timing Range Limits -static NVT_STATUS parseDisplayId20DisplayInterfaceFeatures(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x26 Display Interface Features -static NVT_STATUS parseDisplayId20Stereo(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x27 Stereo Display Interface -static NVT_STATUS parseDisplayId20TiledDisplay(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x28 Tiled Display Topology -static NVT_STATUS parseDisplayId20ContainerId(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x29 ContainerID -static NVT_STATUS parseDisplayId20Timing10(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x2A Type X Timing - Formula-based Timing -static NVT_STATUS parseDisplayId20AdaptiveSync(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x2B Adaptive-Sync -static NVT_STATUS parseDisplayId20ARVRHMD(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x2C ARVR HMD -static NVT_STATUS parseDisplayId20ARVRLayer(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x2D ARVR Layer -static NVT_STATUS parseDisplayId20VendorSpecific(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x7E Vendor-specific -static NVT_STATUS parseDisplayId20CtaData(const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo); // 0x81 CTA DisplayID - // Helper function static NVT_STATUS getPrimaryUseCase(NvU8 product_type, NVT_DISPLAYID_PRODUCT_PRIMARY_USE_CASE *primary_use_case); -static NVT_STATUS parseDisplayId20Timing9Descriptor(const DISPLAYID_2_0_TIMING_9_DESCRIPTOR *pDescriptor, NVT_TIMING *pTiming, NvU8 count); static NvU32 greatestCommonDenominator(NvU32 x, NvU32 y); static NvU8 getExistedTimingSeqNumber(NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo, enum NVT_TIMING_TYPE); @@ -141,7 +116,9 @@ NvTiming_parseDisplayId20Info( return status; } -NvU32 NvTiming_DisplayID2ValidationMask( +CODE_SEGMENT(PAGE_DD_CODE) +NvU32 +NvTiming_DisplayID2ValidationMask( NVT_DISPLAYID_2_0_INFO *pDisplayId20Info, NvBool bIsStrongValidation) { @@ -215,7 +192,7 @@ NvTiming_DisplayID2ValidationDataBlocks( // DisplayID20 Entry point functions CODE_SEGMENT(PAGE_DD_CODE) -static NVT_STATUS +NVT_STATUS parseDisplayId20BaseSection( const DISPLAYID_2_0_SECTION *pSection, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo) @@ -245,7 +222,7 @@ parseDisplayId20BaseSection( } CODE_SEGMENT(PAGE_DD_CODE) -static NVT_STATUS +NVT_STATUS parseDisplayId20ExtensionSection( const DISPLAYID_2_0_SECTION *pSection, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo) @@ -269,7 +246,7 @@ parseDisplayId20ExtensionSection( } CODE_SEGMENT(PAGE_DD_CODE) -static NVT_STATUS +NVT_STATUS parseDisplayId20SectionDataBlocks( const DISPLAYID_2_0_SECTION *pSection, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo) @@ -355,31 +332,34 @@ parseDisplayId20SectionDataBlocks( } break; case DISPLAYID_2_0_BLOCK_TYPE_STEREO: - pDisplayIdInfo->valid_data_blocks.stereo_interface_present = NV_TRUE; + pDisplayIdInfo->valid_data_blocks.stereo_interface_present = NV_TRUE; break; case DISPLAYID_2_0_BLOCK_TYPE_TILED_DISPLAY: - pDisplayIdInfo->valid_data_blocks.tiled_display_present = NV_TRUE; + pDisplayIdInfo->valid_data_blocks.tiled_display_present = NV_TRUE; break; case DISPLAYID_2_0_BLOCK_TYPE_CONTAINER_ID: - pDisplayIdInfo->valid_data_blocks.container_id_present = NV_TRUE; + pDisplayIdInfo->valid_data_blocks.container_id_present = NV_TRUE; break; case DISPLAYID_2_0_BLOCK_TYPE_TIMING_10: - pDisplayIdInfo->valid_data_blocks.type10Timing_present = NV_TRUE; + pDisplayIdInfo->valid_data_blocks.type10Timing_present = NV_TRUE; break; case DISPLAYID_2_0_BLOCK_TYPE_ADAPTIVE_SYNC: - pDisplayIdInfo->valid_data_blocks.adaptive_sync_present = NV_TRUE; + pDisplayIdInfo->valid_data_blocks.adaptive_sync_present = NV_TRUE; break; case DISPLAYID_2_0_BLOCK_TYPE_ARVR_HMD: - pDisplayIdInfo->valid_data_blocks.arvr_hmd_present = NV_TRUE; + pDisplayIdInfo->valid_data_blocks.arvr_hmd_present = NV_TRUE; break; case DISPLAYID_2_0_BLOCK_TYPE_ARVR_LAYER: - pDisplayIdInfo->valid_data_blocks.arvr_layer_present = NV_TRUE; + pDisplayIdInfo->valid_data_blocks.arvr_layer_present = NV_TRUE; + break; + case DISPLAYID_2_0_BLOCK_TYPE_BRIGHTNESS_LUMINANCE_RANGE: + pDisplayIdInfo->valid_data_blocks.brightness_luminance_range_present = NV_TRUE; break; case DISPLAYID_2_0_BLOCK_TYPE_VENDOR_SPEC: - pDisplayIdInfo->valid_data_blocks.vendor_specific_present = NV_TRUE; + pDisplayIdInfo->valid_data_blocks.vendor_specific_present = NV_TRUE; break; case DISPLAYID_2_0_BLOCK_TYPE_CTA_DATA: - pDisplayIdInfo->valid_data_blocks.cta_data_present = NV_TRUE; + pDisplayIdInfo->valid_data_blocks.cta_data_present = NV_TRUE; break; default: status = NVT_STATUS_ERR; @@ -444,6 +424,9 @@ parseDisplayId20DataBlock( case DISPLAYID_2_0_BLOCK_TYPE_ARVR_LAYER: status = parseDisplayId20ARVRLayer(pDataBlock, pDisplayIdInfo); break; + case DISPLAYID_2_0_BLOCK_TYPE_BRIGHTNESS_LUMINANCE_RANGE: + status = parseDisplayId20BrightnessLuminanceRange(pDataBlock, pDisplayIdInfo); + break; case DISPLAYID_2_0_BLOCK_TYPE_VENDOR_SPEC: status = parseDisplayId20VendorSpecific(pDataBlock, pDisplayIdInfo); break; @@ -503,7 +486,7 @@ parseDisplayId20ProductIdentity( CODE_SEGMENT(PAGE_DD_CODE) -static NVT_STATUS +NVT_STATUS parseDisplayId20DisplayParam( const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo) @@ -561,8 +544,8 @@ parseDisplayId20DisplayParam( // IEEE 754 half-precision binary floating-point format pDisplayParam->native_max_luminance_full_coverage = pDisplayParamBlock->max_luminance_full_coverage[1] << 8 | pDisplayParamBlock->max_luminance_full_coverage[0]; - pDisplayParam->native_max_luminance_1_percent_rect_coverage = pDisplayParamBlock->max_luminance_1_percent_rectangular_coverage[1] << 8 | - pDisplayParamBlock->max_luminance_1_percent_rectangular_coverage[0]; + pDisplayParam->native_max_luminance_10_percent_rect_coverage = pDisplayParamBlock->max_luminance_10_percent_rectangular_coverage[1] << 8 | + pDisplayParamBlock->max_luminance_10_percent_rectangular_coverage[0]; pDisplayParam->native_min_luminance = pDisplayParamBlock->min_luminance[1] << 8 | pDisplayParamBlock->min_luminance[0]; @@ -598,7 +581,7 @@ parseDisplayId20DisplayParam( } CODE_SEGMENT(PAGE_DD_CODE) -static NVT_STATUS +NVT_STATUS parseDisplayId20Timing7( const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo) @@ -687,7 +670,7 @@ parseDisplayId20Timing7( } CODE_SEGMENT(PAGE_DD_CODE) -static NVT_STATUS +NVT_STATUS parseDisplayId20Timing8( const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo) @@ -751,7 +734,7 @@ parseDisplayId20Timing8( } CODE_SEGMENT(PAGE_DD_CODE) -static NVT_STATUS +NVT_STATUS parseDisplayId20Timing9( const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo) @@ -798,7 +781,7 @@ parseDisplayId20Timing9( } CODE_SEGMENT(PAGE_DD_CODE) -static NVT_STATUS +NVT_STATUS parseDisplayId20Timing10( const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo) @@ -909,7 +892,7 @@ parseDisplayId20Timing10( } CODE_SEGMENT(PAGE_DD_CODE) -static NVT_STATUS +NVT_STATUS parseDisplayId20RangeLimit( const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo) @@ -970,7 +953,7 @@ parseDisplayId20RangeLimit( } while(0) CODE_SEGMENT(PAGE_DD_CODE) -static NVT_STATUS +NVT_STATUS parseDisplayId20DisplayInterfaceFeatures( const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo) @@ -1088,7 +1071,7 @@ parseDisplayId20DisplayInterfaceFeatures( } CODE_SEGMENT(PAGE_DD_CODE) -static NVT_STATUS +NVT_STATUS parseDisplayId20Stereo( const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo) @@ -1103,7 +1086,7 @@ parseDisplayId20Stereo( } CODE_SEGMENT(PAGE_DD_CODE) -static NVT_STATUS +NVT_STATUS parseDisplayId20TiledDisplay( const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo) @@ -1166,7 +1149,7 @@ parseDisplayId20TiledDisplay( } CODE_SEGMENT(PAGE_DD_CODE) -static NVT_STATUS +NVT_STATUS parseDisplayId20ContainerId( const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo) @@ -1207,7 +1190,7 @@ parseDisplayId20ContainerId( } CODE_SEGMENT(PAGE_DD_CODE) -static NVT_STATUS +NVT_STATUS parseDisplayId20AdaptiveSync( const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo) @@ -1279,7 +1262,7 @@ parseDisplayId20AdaptiveSync( } CODE_SEGMENT(PAGE_DD_CODE) -static NVT_STATUS +NVT_STATUS parseDisplayId20ARVRHMD( const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo) @@ -1294,7 +1277,7 @@ parseDisplayId20ARVRHMD( } CODE_SEGMENT(PAGE_DD_CODE) -static NVT_STATUS +NVT_STATUS parseDisplayId20ARVRLayer( const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo) @@ -1308,10 +1291,36 @@ parseDisplayId20ARVRLayer( return status; } +CODE_SEGMENT(PAGE_DD_CODE) +NVT_STATUS +parseDisplayId20BrightnessLuminanceRange( + const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, + NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo) +{ + NVT_STATUS status = NVT_STATUS_SUCCESS; + const DISPLAYID_2_0_BRIGHTNESS_LUMINANCE_RANGE_BLOCK *pBrightnessLuminanceRangeBlock = NULL; + NVT_DISPLAYID_BRIGHTNESS_LUMINANCE_RANGE *pluminanceRanges = NULL; + + if ((pDataBlock == NULL) || pDataBlock->data_bytes != DISPLAYID_2_0_BRIGHTNESS_LUMINANCE_RANGE_BLOCK_PAYLOAD_LENGTH) + { + return NVT_STATUS_ERR; + } + + if (pDisplayIdInfo == NULL) return status; + pBrightnessLuminanceRangeBlock = (const DISPLAYID_2_0_BRIGHTNESS_LUMINANCE_RANGE_BLOCK *)pDataBlock; + pluminanceRanges = &pDisplayIdInfo->luminance_ranges; + + pluminanceRanges->revision = pDataBlock->revision; + pluminanceRanges->min_sdr_luminance = pBrightnessLuminanceRangeBlock->min_sdr_luminance; + pluminanceRanges->max_sdr_luminance = pBrightnessLuminanceRangeBlock->max_sdr_luminance; + pluminanceRanges->max_boost_sdr_luminance = pBrightnessLuminanceRangeBlock->max_boost_sdr_luminance; + + return status; +} CODE_SEGMENT(PAGE_DD_CODE) -static NVT_STATUS +NVT_STATUS parseDisplayId20VendorSpecific( const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo) @@ -1365,7 +1374,7 @@ parseDisplayId20VendorSpecific( } CODE_SEGMENT(PAGE_DD_CODE) -static NVT_STATUS +NVT_STATUS parseDisplayId20CtaData( const DISPLAYID_2_0_DATA_BLOCK_HEADER *pDataBlock, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo) @@ -1399,6 +1408,8 @@ parseDisplayId20CtaData( p861Info = &(pDisplayIdInfo->cta.cta861_info); parseCta861VsdbBlocks(p861Info, pDisplayIdInfo, FROM_DISPLAYID_20_DATA_BLOCK); + parseCta861VsvdbBlocks(p861Info, pDisplayIdInfo, FROM_DISPLAYID_20_DATA_BLOCK); + parseCta861HfScdb(p861Info, pDisplayIdInfo, FROM_DISPLAYID_20_DATA_BLOCK); // This CTA 861 function to parse 861 part parse861bShortTiming(p861Info, pDisplayIdInfo, FROM_DISPLAYID_20_DATA_BLOCK); @@ -1406,8 +1417,6 @@ parseDisplayId20CtaData( parse861bShortYuv420Timing(p861Info, pDisplayIdInfo, FROM_DISPLAYID_20_DATA_BLOCK); parseCea861HdrStaticMetadataDataBlock(p861Info, pDisplayIdInfo, FROM_DISPLAYID_20_DATA_BLOCK); - parseCea861DvStaticMetadataDataBlock(p861Info, pDisplayIdInfo, FROM_DISPLAYID_20_DATA_BLOCK); - parseCea861Hdr10PlusDataBlock(p861Info, pDisplayIdInfo, FROM_DISPLAYID_20_DATA_BLOCK); // CEA861-F at 7.5.12 section about VFPDB block. if (p861Info->total_svr > 0) @@ -1694,17 +1703,20 @@ parseDisplayId20Timing8Descriptor( } CODE_SEGMENT(PAGE_DD_CODE) -static NVT_STATUS +NVT_STATUS parseDisplayId20Timing9Descriptor( - const DISPLAYID_2_0_TIMING_9_DESCRIPTOR *pDescriptor, + const void *pVoidDescriptor, NVT_TIMING *pTiming, NvU8 count) { NVT_STATUS status = NVT_STATUS_SUCCESS; + const DISPLAYID_2_0_TIMING_9_DESCRIPTOR* pDescriptor = NULL; NvU32 width = 0; NvU32 height = 0; NvU32 rr = 0; + pDescriptor = (const DISPLAYID_2_0_TIMING_9_DESCRIPTOR *)pVoidDescriptor; + width = (pDescriptor->horizontal_active_pixels[1] << 8 | pDescriptor->horizontal_active_pixels[0]) + 1; height = (pDescriptor->vertical_active_lines[1] << 8 | pDescriptor->vertical_active_lines[0]) + 1; rr = pDescriptor->refresh_rate + 1; diff --git a/src/common/modeset/timing/nvt_dsc_pps.c b/src/common/modeset/timing/nvt_dsc_pps.c index bd0fce9882..3cd00ef629 100644 --- a/src/common/modeset/timing/nvt_dsc_pps.c +++ b/src/common/modeset/timing/nvt_dsc_pps.c @@ -1219,6 +1219,45 @@ DSC_GetPeakThroughputMps(NvU32 peak_throughput) return peak_throughput_mps; } +/* + * @brief Get slice count mask upto max slice count. + * + * @param[in] max_slice_num max slice number to be considered while generating mask + * @param[in] bInclusive maximum slice number should be included in mask or not + * + * @returns slice count mask of all slice counts up to max slice count + */ +static NvU32 +DSC_GetSliceCountMask +( + NvU32 maxSliceNum, + NvBool bInclusive +) +{ + // Below are the valid slice counts according to DP2.0 spec. + NvU32 validSliceNum[] = {1,2,4,6,8,10,12,16,20,24}; + NvU32 sliceCountMask = 0; + NvU32 sliceArrayCount; + NvU32 i; + + sliceArrayCount = sizeof(validSliceNum)/sizeof(NvU32); + + if (maxSliceNum == 0) + return 0; + + for(i = 0; ((i < sliceArrayCount) && (validSliceNum[i] < maxSliceNum)); i++) + { + sliceCountMask |= NVBIT(validSliceNum[i] - 1); + } + + if (bInclusive && (i < sliceArrayCount)) + { + sliceCountMask |= NVBIT(validSliceNum[i] - 1); + } + + return sliceCountMask; +} + /* * @brief Get the next higher valid slice count. * @@ -1304,39 +1343,30 @@ DSC_PpsCalcSliceParams NvU32 min_slice_num; NvU32 slicew; NvU32 peak_throughput_mps; - // - // Bits 0,1,3,4,5 represents slice counts 1,2,4,6,8. - // Bit 2 is reserved and Slice count = 6 is not supported - // by GPU, so that is not required to be set. - // - NvU32 gpu_slice_count_mask = DSC_DECODER_SLICES_PER_SINK_1 | - DSC_DECODER_SLICES_PER_SINK_2 | - DSC_DECODER_SLICES_PER_SINK_4; + NvU32 common_slice_count_mask; + NvU32 gpu_slice_count_mask; + + gpu_slice_count_mask = DSC_GetSliceCountMask(max_slice_num, NV_TRUE /*bInclusive*/); - NvU32 gpu_slice_count_mask_dual = DSC_DECODER_SLICES_PER_SINK_2 | - DSC_DECODER_SLICES_PER_SINK_4 | - DSC_DECODER_SLICES_PER_SINK_8; + if (dual_mode) + { + // remove slice count 1 as it is not valid for 2Head1OR case. + gpu_slice_count_mask &= ~(0x1); + } - NvU32 common_slice_count_mask = dual_mode? gpu_slice_count_mask_dual & slice_count_mask : - gpu_slice_count_mask & slice_count_mask; + common_slice_count_mask = gpu_slice_count_mask & slice_count_mask; if (!common_slice_count_mask) { DSC_Print("DSC cannot be supported since no common supported slice count\n"); - return NVT_STATUS_ERR; + return NVT_STATUS_DSC_SLICE_ERROR; } peak_throughput_mps = DSC_GetPeakThroughputMps(peak_throughput); if (!peak_throughput_mps) { DSC_Print("Peak throughput cannot be zero.\n"); - return NVT_STATUS_ERR; - } - - if (max_slice_width > MAX_WIDTH_PER_SLICE) - { - DSC_Print("GPU can support only a max of 5120 pixels across all slices\n"); - max_slice_width = MAX_WIDTH_PER_SLICE; + return NVT_STATUS_INVALID_PEAK_THROUGHPUT; } if (out->slice_num == 0 && out->slice_width == 0) @@ -1349,7 +1379,7 @@ DSC_PpsCalcSliceParams if (max_slice_num < min_slice_num) { DSC_Print("Requested mode cannot be supported with DSC\n"); - return NVT_STATUS_ERR; + return NVT_STATUS_MIN_SLICE_COUNT_ERROR; } if (!(DSC_SliceCountMaskforSliceNum(min_slice_num) & common_slice_count_mask)) @@ -1357,7 +1387,7 @@ DSC_PpsCalcSliceParams if (DSC_GetHigherSliceCount(common_slice_count_mask, min_slice_num, dual_mode, &new_slice_num) == NVT_STATUS_ERR) { DSC_Print("DSC cannot be enabled for this mode\n"); - return NVT_STATUS_ERR; + return NVT_STATUS_MIN_SLICE_COUNT_ERROR; } else { @@ -1376,14 +1406,14 @@ DSC_PpsCalcSliceParams if (out->slice_width > max_slice_width) { DSC_Print("Error! Max Supported Slice Width = %u\n", max_slice_width); - return NVT_STATUS_ERR; + return NVT_STATUS_PPS_SLICE_WIDTH_ERROR; } out->slice_num = (out->pic_width + out->slice_width - 1) / out->slice_width; if (!(DSC_SliceCountMaskforSliceNum(out->slice_num) & common_slice_count_mask)) { DSC_Print("Slice count corresponding to requested slice_width is not supported\n"); - return NVT_STATUS_ERR; + return NVT_STATUS_PPS_SLICE_COUNT_ERROR; } } else if (out->slice_width == 0) @@ -1391,7 +1421,7 @@ DSC_PpsCalcSliceParams if (!(DSC_SliceCountMaskforSliceNum(out->slice_num) & common_slice_count_mask)) { DSC_Print("Slice count requested is not supported\n"); - return NVT_STATUS_ERR; + return NVT_STATUS_PPS_SLICE_COUNT_ERROR; } out->slice_width = (out->pic_width + out->slice_num - 1) / out->slice_num; @@ -1404,7 +1434,7 @@ DSC_PpsCalcSliceParams if (out->slice_width > max_slice_width) { DSC_Print("Slice width corresponding to the requested slice count is not supported\n"); - return NVT_STATUS_ERR; + return NVT_STATUS_PPS_SLICE_WIDTH_ERROR; } } else @@ -1412,19 +1442,19 @@ DSC_PpsCalcSliceParams if (!(DSC_SliceCountMaskforSliceNum(out->slice_num) & common_slice_count_mask)) { DSC_Print("Requested slice count is not supported\n"); - return NVT_STATUS_ERR; + return NVT_STATUS_PPS_SLICE_COUNT_ERROR; } if (out->slice_width > max_slice_width) { DSC_Print("Requested slice width cannot be supported\n"); - return NVT_STATUS_ERR; + return NVT_STATUS_PPS_SLICE_WIDTH_ERROR; } if (out->slice_width != (out->pic_width + out->slice_num - 1) / out->slice_num) { DSC_Print("slice_width must equal CEIL(pic_width/slice_num) \n"); - return NVT_STATUS_ERR; + return NVT_STATUS_PPS_SLICE_WIDTH_ERROR; } } @@ -1442,7 +1472,7 @@ DSC_PpsCalcSliceParams if (out->slice_width < 32) { DSC_Print("slice_width must >= 32\n"); - return NVT_STATUS_ERR; + return NVT_STATUS_PPS_SLICE_WIDTH_ERROR; } slicew = out->slice_width >> (out->native_420 || out->native_422); // /2 in 4:2:0 mode @@ -1509,7 +1539,7 @@ Dsc_PpsCalcHeight(DSC_OUTPUT_PARAMS *out) return NVT_STATUS_SUCCESS; } DSC_Print("Error! can't find valid slice_height"); - return NVT_STATUS_ERR; + return NVT_STATUS_PPS_SLICE_HEIGHT_ERROR; } RANGE_CHECK("slice_height", out->slice_height, 8, out->pic_height); @@ -1517,13 +1547,13 @@ Dsc_PpsCalcHeight(DSC_OUTPUT_PARAMS *out) if (out->pic_height % out->slice_height != 0) { DSC_Print("Error! pic_height %% slice_height must be 0"); - return NVT_STATUS_ERR; + return NVT_STATUS_PPS_SLICE_HEIGHT_ERROR; } if(DSC_PpsCheckSliceHeight(out) != NVT_STATUS_SUCCESS) { DSC_Print("Error! slice_height not valid"); - return NVT_STATUS_ERR; + return NVT_STATUS_PPS_SLICE_HEIGHT_ERROR; } return NVT_STATUS_SUCCESS; } @@ -1711,26 +1741,26 @@ _validateInput if (pDscInfo->forcedDscParams.sliceCount > pDscInfo->sinkCaps.maxNumHztSlices) { DSC_Print("ERROR - Client can't specify forced slice count greater than what sink supports."); - return NVT_STATUS_INVALID_PARAMETER; + return NVT_STATUS_DSC_SLICE_ERROR; } if ((pDscInfo->forcedDscParams.sliceCount / (pModesetInfo->bDualMode ? 2 : 1)) > pDscInfo->gpuCaps.maxNumHztSlices) { DSC_Print("ERROR - Client can't specify forced slice count greater than what GPU supports."); - return NVT_STATUS_INVALID_PARAMETER; + return NVT_STATUS_DSC_SLICE_ERROR; } if (pDscInfo->forcedDscParams.sliceWidth > pDscInfo->sinkCaps.maxSliceWidth) { DSC_Print("ERROR - Client can't specify forced slice width greater than what sink supports."); - return NVT_STATUS_INVALID_PARAMETER; + return NVT_STATUS_DSC_SLICE_ERROR; } if ((pDscInfo->forcedDscParams.sliceCount > 0) && (pDscInfo->forcedDscParams.sliceWidth != 0)) { DSC_Print("ERROR - Client can't specify both forced slice count and slice width."); - return NVT_STATUS_INVALID_PARAMETER; + return NVT_STATUS_DSC_SLICE_ERROR; } if ((pDscInfo->forcedDscParams.sliceCount != 0) && @@ -1740,19 +1770,19 @@ _validateInput (pDscInfo->forcedDscParams.sliceCount != 8)) { DSC_Print("ERROR - Forced Slice Count has to be 1/2/4/8."); - return NVT_STATUS_INVALID_PARAMETER; + return NVT_STATUS_DSC_SLICE_ERROR; } if (pDscInfo->forcedDscParams.sliceWidth > pModesetInfo->activeWidth) { DSC_Print("ERROR - Forced Slice Width can't be more than Active Width."); - return NVT_STATUS_INVALID_PARAMETER; + return NVT_STATUS_DSC_SLICE_ERROR; } if (pDscInfo->forcedDscParams.sliceHeight > pModesetInfo->activeHeight) { DSC_Print("ERROR - Forced Slice Height can't be more than Active Height."); - return NVT_STATUS_INVALID_PARAMETER; + return NVT_STATUS_DSC_SLICE_ERROR; } if (pDscInfo->forcedDscParams.dscRevision.versionMinor > @@ -1778,7 +1808,7 @@ _validateInput (pModesetInfo->pixelClockHz > pDscInfo->branchCaps.overallThroughputMode0 * MHZ_TO_HZ)) { DSC_Print("ERROR - Pixel clock cannot be greater than Branch DSC Overall Throughput Mode 0"); - return NVT_STATUS_INVALID_PARAMETER; + return NVT_STATUS_OVERALL_THROUGHPUT_ERROR; } if (pModesetInfo->activeWidth == 0) @@ -1791,7 +1821,7 @@ _validateInput pModesetInfo->activeWidth > pDscInfo->branchCaps.maxLineBufferWidth) { DSC_Print("ERROR - Active width cannot be greater than DSC Decompressor max line buffer width"); - return NVT_STATUS_INVALID_PARAMETER; + return NVT_STATUS_MAX_LINE_BUFFER_ERROR; } if (pModesetInfo->activeHeight == 0) @@ -1824,7 +1854,7 @@ _validateInput (pDscInfo->sinkCaps.decoderColorFormatMask & DSC_DECODER_COLOR_FORMAT_Y_CB_CR_NATIVE_422)))) { DSC_Print("ERROR - Can't enable YCbCr422 with current GPU and Sink DSC config."); - return NVT_STATUS_INVALID_PARAMETER; + return NVT_STATUS_COLOR_FORMAT_NOT_SUPPORTED; } } @@ -1837,7 +1867,7 @@ _validateInput (pDscInfo->sinkCaps.decoderColorFormatMask & DSC_DECODER_COLOR_FORMAT_Y_CB_CR_NATIVE_420))) { DSC_Print("ERROR - Can't enable YCbCr420 with current GPU and Sink DSC config."); - return NVT_STATUS_INVALID_PARAMETER; + return NVT_STATUS_COLOR_FORMAT_NOT_SUPPORTED; } } @@ -1863,21 +1893,21 @@ _validateInput if (!(pDscInfo->sinkCaps.decoderColorDepthMask & DSC_DECODER_COLOR_DEPTH_CAPS_12_BITS)) { DSC_Print("ERROR - Sink DSC Decoder does not support 12 bpc"); - return NVT_STATUS_INVALID_PARAMETER; + return NVT_STATUS_INVALID_BPC; } break; case 10: if (!(pDscInfo->sinkCaps.decoderColorDepthMask & DSC_DECODER_COLOR_DEPTH_CAPS_10_BITS)) { DSC_Print("ERROR - Sink DSC Decoder does not support 10 bpc"); - return NVT_STATUS_INVALID_PARAMETER; + return NVT_STATUS_INVALID_BPC; } break; case 8: if (!(pDscInfo->sinkCaps.decoderColorDepthMask & DSC_DECODER_COLOR_DEPTH_CAPS_8_BITS)) { DSC_Print("ERROR - Sink DSC Decoder does not support 8 bpc"); - return NVT_STATUS_INVALID_PARAMETER; + return NVT_STATUS_INVALID_BPC; } break; @@ -1917,7 +1947,7 @@ _validateInput if (pWARData->dpData.hBlank > MAX_HBLANK_PIXELS) { DSC_Print("ERROR - Incorrect DP HBlank info sent with WAR data"); - return NVT_STATUS_INVALID_PARAMETER; + return NVT_STATUS_INVALID_HBLANK; } if ((pWARData->dpData.dpMode != DSC_DP_SST) && (pWARData->dpData.dpMode != DSC_DP_MST)) @@ -2016,7 +2046,7 @@ DSC_GeneratePPS else { DSC_Print("ERROR - YCbCr422 is not possible with current config."); - ret = NVT_STATUS_INVALID_PARAMETER; + ret = NVT_STATUS_COLOR_FORMAT_NOT_SUPPORTED; goto done; } break; @@ -2031,14 +2061,14 @@ DSC_GeneratePPS else { DSC_Print("ERROR - YCbCr420 is not possible with current config."); - ret = NVT_STATUS_INVALID_PARAMETER; + ret = NVT_STATUS_COLOR_FORMAT_NOT_SUPPORTED; goto done; } break; default: DSC_Print("ERROR - Invalid color Format specified."); - ret = NVT_STATUS_INVALID_PARAMETER; + ret = NVT_STATUS_COLOR_FORMAT_NOT_SUPPORTED; goto done; } @@ -2145,7 +2175,7 @@ DSC_GeneratePPS (*pBitsPerPixelX16 > in->bits_per_pixel)) { DSC_Print("ERROR - Invalid bits per pixel value specified."); - ret = NVT_STATUS_INVALID_PARAMETER; + ret = NVT_STATUS_INVALID_BPP; goto done; } else @@ -2157,14 +2187,14 @@ DSC_GeneratePPS if (pModesetInfo->bDualMode && (in->bits_per_pixel > 256 /*bits_per_pixel = 16*/)) { DSC_Print("ERROR - DSC Dual Mode, because of architectural limitation we can't use bits_per_pixel more than 16."); - ret = NVT_STATUS_INVALID_PARAMETER; + ret = NVT_STATUS_INVALID_BPP; goto done; } if ((pDscInfo->sinkCaps.maxBitsPerPixelX16 != 0) && (*pBitsPerPixelX16 > pDscInfo->sinkCaps.maxBitsPerPixelX16)) { DSC_Print("ERROR - bits per pixel value specified by user is greater than what DSC decompressor can support."); - ret = NVT_STATUS_INVALID_PARAMETER; + ret = NVT_STATUS_INVALID_BPP; goto done; } } @@ -2195,6 +2225,13 @@ DSC_GeneratePPS } } + if (pModesetInfo->bDualMode && (pDscInfo->gpuCaps.maxNumHztSlices > 4U)) + { + DSC_Print("ERROR - Dual Mode should not be set when GPU can support more than 4 slices per head."); + ret = NVT_STATUS_INVALID_PARAMETER; + goto done; + } + in->dsc_version_minor = pDscInfo->forcedDscParams.dscRevision.versionMinor ? pDscInfo->forcedDscParams.dscRevision.versionMinor : pDscInfo->sinkCaps.algorithmRevision.versionMinor; in->pic_width = pModesetInfo->activeWidth; @@ -2204,7 +2241,8 @@ DSC_GeneratePPS in->slice_num = pDscInfo->forcedDscParams.sliceCount; in->max_slice_num = MIN(pDscInfo->sinkCaps.maxNumHztSlices, pModesetInfo->bDualMode ? pDscInfo->gpuCaps.maxNumHztSlices * 2 : pDscInfo->gpuCaps.maxNumHztSlices); - in->max_slice_width = pDscInfo->sinkCaps.maxSliceWidth; + // lineBufferSize is reported in 1024 units by HW, so need to multiply by 1024 to get pixels. + in->max_slice_width = MIN(pDscInfo->sinkCaps.maxSliceWidth, pDscInfo->gpuCaps.lineBufferSize * 1024); in->pixel_clkMHz = (NvU32)(pModesetInfo->pixelClockHz / 1000000L); in->dual_mode = pModesetInfo->bDualMode; in->drop_mode = pModesetInfo->bDropMode; @@ -2217,7 +2255,7 @@ DSC_GeneratePPS if (in->dsc_version_minor == 1) { DSC_Print("Error! DSC1.1 can't support native422!\n"); - ret = NVT_STATUS_INVALID_PARAMETER; + ret = NVT_STATUS_COLOR_FORMAT_NOT_SUPPORTED; goto done; } //the bpp in native 422 mode is doubled. @@ -2226,7 +2264,7 @@ DSC_GeneratePPS { DSC_Print("bits_per_pixelx16 (=%u) needs to be between %u and %u", in->bits_per_pixel, 2*6*BPP_UNIT, 2*32*BPP_UNIT-1); - ret = NVT_STATUS_INVALID_PARAMETER; + ret = NVT_STATUS_INVALID_BPP; goto done; } } @@ -2237,7 +2275,7 @@ DSC_GeneratePPS { DSC_Print("bits_per_pixelx16 (=%u) needs to be between %u and %u", in->bits_per_pixel, 8*BPP_UNIT, 32*BPP_UNIT); - ret = NVT_STATUS_INVALID_PARAMETER; + ret = NVT_STATUS_INVALID_BPP; goto done; } } diff --git a/src/common/modeset/timing/nvt_edid.c b/src/common/modeset/timing/nvt_edid.c index 681b3104ae..7501117e34 100644 --- a/src/common/modeset/timing/nvt_edid.c +++ b/src/common/modeset/timing/nvt_edid.c @@ -1053,16 +1053,11 @@ NVT_STATUS NV_STDCALL NvTiming_ParseEDIDInfo(NvU8 *pEdid, NvU32 length, NVT_EDID // parseCta861VsdbBlocks() uses hfScdb info so need to be parsed first parseCta861HfScdb(p861Info, pInfo, FROM_CTA861_EXTENSION); parseCta861VsdbBlocks(p861Info, pInfo, FROM_CTA861_EXTENSION); + parseCta861VsvdbBlocks(p861Info, pInfo, FROM_CTA861_EXTENSION); // parse HDR related information from the HDR static metadata data block parseCea861HdrStaticMetadataDataBlock(p861Info, pInfo, FROM_CTA861_EXTENSION); - // parse Dolby Vision related information from the DV vendor specific video data block - parseCea861DvStaticMetadataDataBlock(p861Info, pInfo, FROM_CTA861_EXTENSION); - - // parse HDR10+ related information from the HDR10+ LLC Vendor Specific Video Data Block - parseCea861Hdr10PlusDataBlock(p861Info, pInfo, FROM_CTA861_EXTENSION); - // Timings are listed (or shall) be listed in priority order // So read SVD, yuv420 SVDs first before reading detailed timings @@ -1443,6 +1438,7 @@ NVT_STATUS NvTiming_Get18ByteLongDescriptorIndex(NVT_EDID_INFO *pEdidInfo, NvU8 CODE_SEGMENT(PAGE_DD_CODE) NVT_STATUS NvTiming_GetEdidTimingEx(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_EDID_INFO *pEdidInfo, NVT_TIMING *pT, NvU32 rrx1k) { + NvU8 kth = 0; NvU32 i, j; NvU32 native_cta, preferred_cta, preferred_displayid_dtd, preferred_dtd1, dtd1, map0, map1, map2, map3, map4, ceaIndex, max, cvt; NVT_TIMING *pEdidTiming; @@ -1474,6 +1470,12 @@ NVT_STATUS NvTiming_GetEdidTimingEx(NvU32 width, NvU32 height, NvU32 rr, NvU32 f // max - the timing with the max visible area native_cta = preferred_cta = preferred_displayid_dtd = preferred_dtd1 = dtd1 = map0 = map1 = map2 = map3 = map4 = ceaIndex = pEdidInfo->total_timings; max = cvt = 0; + + if (pEdidInfo->ext861.total_svr > 1) + { + kth = getHighestPrioritySVRIdx(pEdidInfo->ext861.svr_vfpdb[0]); + } + for (i = 0; i < pEdidInfo->total_timings; i++) { // if the client prefers _NATIVE timing, then don't select custom timing @@ -1542,7 +1544,25 @@ NVT_STATUS NvTiming_GetEdidTimingEx(NvU32 width, NvU32 height, NvU32 rr, NvU32 f if (preferred_cta == pEdidInfo->total_timings && NVT_PREFERRED_TIMING_IS_CTA(pEdidTiming[i].etc.flag)) { - preferred_cta = i; + if (pEdidInfo->ext861.total_svr > 1) + { + if (kth != 0) + { + // svr == vic + if (NVT_IS_CTA861(pEdidTiming[i].etc.status) && (NVT_GET_CEA_FORMAT(pEdidTiming[i].etc.status) == kth)) + { + preferred_cta = i; + } + else if (NVT_GET_TIMING_STATUS_SEQ(pEdidTiming[i].etc.status) == kth) + { + preferred_cta = i; + } + } + } + else + { + preferred_cta = i; + } } // find out the preferred timing just in case @@ -2165,7 +2185,7 @@ NvU32 NvTiming_EDIDValidationMask(NvU8 *pEdid, NvU32 length, NvBool bIsStrongVal // validate DTD blocks pDTD = (DETAILEDTIMINGDESCRIPTOR *)&pExt[((EIA861EXTENSION *)pExt)->offset]; while ((pDTD->wDTPixelClock != 0) && - (((NvU8 *)pDTD - pExt + sizeof(DETAILEDTIMINGDESCRIPTOR)) < ((NvU8)sizeof(EIA861EXTENSION) - 1))) + (((NvU8 *)pDTD - pExt + sizeof(DETAILEDTIMINGDESCRIPTOR)) < ((NvU8)sizeof(EIA861EXTENSION)))) { if (parseEdidDetailedTimingDescriptor((NvU8 *)pDTD, NULL) != NVT_STATUS_SUCCESS) { @@ -2413,7 +2433,7 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length) // validate DTD blocks pDTD = (DETAILEDTIMINGDESCRIPTOR *)&pExt[((EIA861EXTENSION *)pExt)->offset]; while ((pDTD->wDTPixelClock != 0) && - (((NvU8 *)pDTD - pExt + sizeof(DETAILEDTIMINGDESCRIPTOR)) < ((NvU8)sizeof(EIA861EXTENSION) -1))) + (((NvU8 *)pDTD - pExt + sizeof(DETAILEDTIMINGDESCRIPTOR)) < ((NvU8)sizeof(EIA861EXTENSION)))) { if (parseEdidDetailedTimingDescriptor((NvU8 *)pDTD, NULL) != NVT_STATUS_SUCCESS) ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_DTD); @@ -2463,8 +2483,8 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length) // Sanity check every data blocks while (((pDID2Header->type >= DISPLAYID_2_0_BLOCK_TYPE_PRODUCT_IDENTITY && - pDID2Header->type <= DISPLAYID_2_0_BLOCK_TYPE_ARVR_LAYER) || - pDID2Header->type == DISPLAYID_2_0_BLOCK_TYPE_VENDOR_SPEC || + pDID2Header->type <= DISPLAYID_2_0_BLOCK_TYPE_BRIGHTNESS_LUMINANCE_RANGE) || + pDID2Header->type == DISPLAYID_2_0_BLOCK_TYPE_VENDOR_SPEC || pDID2Header->type == DISPLAYID_2_0_BLOCK_TYPE_CTA_DATA) && pDID2Header->data_bytes != 0 && (pData_collection - pExt < (int)sizeof(DIDEXTENSION))) { @@ -2497,8 +2517,8 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length) // if the first tag failed, ignore all the tags afterward then if (!bAllZero && (pDID2Header->type < DISPLAYID_2_0_BLOCK_TYPE_PRODUCT_IDENTITY || - (pDID2Header->type > DISPLAYID_2_0_BLOCK_TYPE_ARVR_LAYER && - pDID2Header->type != DISPLAYID_2_0_BLOCK_TYPE_VENDOR_SPEC && + (pDID2Header->type > DISPLAYID_2_0_BLOCK_TYPE_BRIGHTNESS_LUMINANCE_RANGE && + pDID2Header->type != DISPLAYID_2_0_BLOCK_TYPE_VENDOR_SPEC && pDID2Header->type != DISPLAYID_2_0_BLOCK_TYPE_CTA_DATA)) && (pData_collection - pExt < (int)sizeof(DIDEXTENSION))) { @@ -2793,6 +2813,32 @@ NvBool assignNextAvailableTiming(NVT_EDID_INFO *pInfo, return NV_TRUE; } +/** + * @brief Return the first high priority nth index based on the different SVR + * @param svr Short Video Reference + */ +CODE_SEGMENT(PAGE_DD_CODE) +NvU8 getHighestPrioritySVRIdx(NvU8 svr) +{ + // In general sink shall define the first one timing sequence + NvU8 kth = 1; + + // Reserved + if (svr == 0 || svr == 128 || (svr >= 176 && svr <= 192) || svr == 255) + return 0; + + if (svr >= 129 && svr <= 144) return svr - 128; // Interpret as the Kth 18-byte DTD in both base0 and CTA block (for N = 1 to 16) + else if (svr >= 145 && svr <= 160) return svr - 144; // Interpret as the Nth 20-byte DTD or 6- or 7-byte CVT-based descriptor. (for N = 1 to 16) + else if (svr >= 161 && svr <= 175) return svr - 160; // Interpret as the video format indicated by the first VFD of the first VFDB with Frame Rates of Rate Index N (for N = 1 to 15) + else if (svr == 254) return kth; // Interpret as the timing format indicated by the first code of the first T8VTDB (for N = 1) + else // assign corresponding CTA format's timing from pre-defined CE timing table, EIA861B + { + // ( SVR >= 1 and SVR <= 127) and (SVR >= 193 and SVR <= 253) needs to handle it by client + return svr; + } + return 0; +} + CODE_SEGMENT(PAGE_DD_CODE) NVT_STATUS NvTiming_GetProductName(const NVT_EDID_INFO *pEdidInfo, NvU8 *pProductName, diff --git a/src/common/modeset/timing/nvt_edidext_861.c b/src/common/modeset/timing/nvt_edidext_861.c index ee16907d38..d369c0f670 100644 --- a/src/common/modeset/timing/nvt_edidext_861.c +++ b/src/common/modeset/timing/nvt_edidext_861.c @@ -968,60 +968,41 @@ void parseCea861HdrStaticMetadataDataBlock(NVT_EDID_CEA861_INFO *pExt861, } CODE_SEGMENT(PAGE_DD_CODE) -void parseCea861DvStaticMetadataDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag) +void parseCta861DvStaticMetadataDataBlock(VSVDB_DATA* pVsvdb, NVT_DV_STATIC_METADATA *pDvInfo) { NvU32 vsvdbVersion = 0; + NVT_DV_STATIC_METADATA_TYPE0 *pDvType0 = NULL; NVT_DV_STATIC_METADATA_TYPE1 *pDvType1 = NULL; NVT_DV_STATIC_METADATA_TYPE1_1 *pvDvType1_1 = NULL; NVT_DV_STATIC_METADATA_TYPE2 *pDvType2 = NULL; - NVT_EDID_INFO *pInfo = NULL; - NVT_DISPLAYID_2_0_INFO *pDisplayID20 = NULL; - NVT_DV_STATIC_METADATA *pDvInfo = NULL; - - if (pExt861 == NULL || pRawInfo == NULL) - { - return; - } - - if (flag == FROM_CTA861_EXTENSION || flag == FROM_DISPLAYID_13_DATA_BLOCK) - { - pInfo = (NVT_EDID_INFO *)pRawInfo; - pDvInfo = &pInfo->dv_static_metadata_info; - } - else if (flag == FROM_DISPLAYID_20_DATA_BLOCK) - { - pDisplayID20 = (NVT_DISPLAYID_2_0_INFO *)pRawInfo; - pDvInfo = &pDisplayID20->cta.dvInfo; - } - else + if (pVsvdb == NULL || pDvInfo == NULL) { return; } - if(pExt861->vsvdb.ieee_id != NVT_CEA861_DV_IEEE_ID) + if(pVsvdb->ieee_id != NVT_CEA861_DV_IEEE_ID) { return; } - //init NVMISC_MEMSET(pDvInfo, 0, sizeof(NVT_DV_STATIC_METADATA)); // copy ieee id - pDvInfo->ieee_id = pExt861->vsvdb.ieee_id; + pDvInfo->ieee_id = pVsvdb->ieee_id; - vsvdbVersion = (pExt861->vsvdb.vendor_data[0] & NVT_CEA861_VSVDB_VERSION_MASK) >> NVT_CEA861_VSVDB_VERSION_MASK_SHIFT; + vsvdbVersion = (pVsvdb->vendor_data[0] & NVT_CEA861_VSVDB_VERSION_MASK) >> NVT_CEA861_VSVDB_VERSION_MASK_SHIFT; switch (vsvdbVersion) { case 0: - if (pExt861->vsvdb.vendor_data_size < sizeof(NVT_DV_STATIC_METADATA_TYPE0)) + if (pVsvdb->vendor_data_size < sizeof(NVT_DV_STATIC_METADATA_TYPE0)) { return; } - pDvType0 = (NVT_DV_STATIC_METADATA_TYPE0 *)(&pExt861->vsvdb.vendor_data); + pDvType0 = (NVT_DV_STATIC_METADATA_TYPE0 *)(&pVsvdb->vendor_data); // copy the data pDvInfo->VSVDB_version = pDvType0->VSVDB_version; pDvInfo->supports_2160p60hz = pDvType0->supports_2160p60hz; @@ -1045,9 +1026,9 @@ void parseCea861DvStaticMetadataDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *p pDvInfo->supports_10b_12b_444 = 0; break; case 1: - if (pExt861->vsvdb.vendor_data_size == sizeof(NVT_DV_STATIC_METADATA_TYPE1)) + if (pVsvdb->vendor_data_size == sizeof(NVT_DV_STATIC_METADATA_TYPE1)) { - pDvType1 = (NVT_DV_STATIC_METADATA_TYPE1 *)(&pExt861->vsvdb.vendor_data); + pDvType1 = (NVT_DV_STATIC_METADATA_TYPE1 *)(&pVsvdb->vendor_data); // copy the data pDvInfo->VSVDB_version = pDvType1->VSVDB_version; pDvInfo->supports_2160p60hz = pDvType1->supports_2160p60hz; @@ -1070,9 +1051,9 @@ void parseCea861DvStaticMetadataDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *p pDvInfo->cc_white_x = 0; pDvInfo->cc_white_y = 0; } - else if (pExt861->vsvdb.vendor_data_size == sizeof(NVT_DV_STATIC_METADATA_TYPE1_1)) + else if (pVsvdb->vendor_data_size == sizeof(NVT_DV_STATIC_METADATA_TYPE1_1)) { - pvDvType1_1 = (NVT_DV_STATIC_METADATA_TYPE1_1 *)(&pExt861->vsvdb.vendor_data); + pvDvType1_1 = (NVT_DV_STATIC_METADATA_TYPE1_1 *)(&pVsvdb->vendor_data); // copy the data pDvInfo->VSVDB_version = pvDvType1_1->VSVDB_version; pDvInfo->supports_2160p60hz = pvDvType1_1->supports_2160p60hz; @@ -1102,11 +1083,11 @@ void parseCea861DvStaticMetadataDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *p break; case 2: - if (pExt861->vsvdb.vendor_data_size < sizeof(NVT_DV_STATIC_METADATA_TYPE2)) + if (pVsvdb->vendor_data_size < sizeof(NVT_DV_STATIC_METADATA_TYPE2)) { return; } - pDvType2 = (NVT_DV_STATIC_METADATA_TYPE2 *)(&pExt861->vsvdb.vendor_data); + pDvType2 = (NVT_DV_STATIC_METADATA_TYPE2 *)(&pVsvdb->vendor_data); // copy the data pDvInfo->VSVDB_version = pDvType2->VSVDB_version; pDvInfo->supports_backlight_control = pDvType2->supports_backlight_control; @@ -1234,6 +1215,67 @@ void parseCta861VsdbBlocks(NVT_EDID_CEA861_INFO *pExt861, } +// parse vendor specific video data block (VSVDB) information +CODE_SEGMENT(PAGE_DD_CODE) +void parseCta861VsvdbBlocks(NVT_EDID_CEA861_INFO *pExt861, + void *pRawInfo, + NVT_CTA861_ORIGIN flag + ) +{ + NvU32 i; + + NVT_EDID_INFO *pInfo = NULL; + NVT_DISPLAYID_2_0_INFO *pDisplayID20 = NULL; + NVT_DV_STATIC_METADATA *pDvInfo = NULL; + NVT_HDR10PLUS_INFO *pHdr10PlusInfo = NULL; + + if (pExt861 == NULL || pRawInfo == NULL) + { + return; + } + + if (flag == FROM_CTA861_EXTENSION || flag == FROM_DISPLAYID_13_DATA_BLOCK) + { + pInfo = (NVT_EDID_INFO *)pRawInfo; + pDvInfo = &pInfo->dv_static_metadata_info; + pHdr10PlusInfo = &pInfo->hdr10PlusInfo; + } + else if (flag == FROM_DISPLAYID_20_DATA_BLOCK) + { + pDisplayID20 = (NVT_DISPLAYID_2_0_INFO *)pRawInfo; + pDvInfo = &pDisplayID20->cta.dvInfo; + pHdr10PlusInfo = &pDisplayID20->cta.hdr10PlusInfo; + } + else + { + return; + } + + if (pDvInfo == NULL || pHdr10PlusInfo == NULL || (pExt861->total_vsvdb == 0)) + { + return; + } + + for (i = 0; i < pExt861->total_vsvdb; i++) + { + // Assumes each vsvdb is unique for this CEA block, e.g., no two HDMI_IEEE_ID + switch (pExt861->vsvdb[i].ieee_id) + { + case NVT_CEA861_DV_IEEE_ID: + // parse Dolby Vision related information from the DV vendor specific video data block + parseCta861DvStaticMetadataDataBlock(&pExt861->vsvdb[i], pDvInfo); + pExt861->valid.dv_static_metadata = 1; + break; + + case NVT_CEA861_HDR10PLUS_IEEE_ID: + // parse HDR10+ related information from the HDR10+ LLC Vendor Specific Video Data Block + parseCta861Hdr10PlusDataBlock(&pExt861->vsvdb[i], pHdr10PlusInfo); + pExt861->valid.hdr10Plus = 1; + break; + } + } +} + CODE_SEGMENT(PAGE_DD_CODE) void parseCta861HfEeodb(NVT_EDID_CEA861_INFO *pExt861, NvU32 *pTotalEdidExtensions) @@ -1378,6 +1420,7 @@ NVT_STATUS parseCta861DataBlockInfo(NvU8 *p, NvU32 audio_index = 0; NvU32 speaker_index = 0; NvU32 vendor_index = 0; + NvU32 vsvdb_index = 0; NvU32 yuv420vdb_index = 0; NvU32 yuv420cmdb_index = 0; NvU8 didT7_index = 0; @@ -1638,42 +1681,48 @@ NVT_STATUS parseCta861DataBlockInfo(NvU8 *p, } else if(ext_tag == NVT_CEA861_EXT_TAG_VENDOR_SPECIFIC_VIDEO) { - ieee_id = p[i + 1]; //IEEE ID low byte - ieee_id |= (p[i + 2]) << 8; //IEEE ID middle byte - ieee_id |= (p[i + 3]) << 16; //IEEE ID high byte - - if ((ieee_id == NVT_CEA861_DV_IEEE_ID) || (ieee_id == NVT_CEA861_HDR10PLUS_IEEE_ID)) + if (vsvdb_index < NVT_CEA861_VSVDB_MAX_BLOCKS) { - // exclude the extended tag - i++; payload--; + ieee_id = p[i + 1]; //IEEE ID low byte + ieee_id |= (p[i + 2]) << 8; //IEEE ID middle byte + ieee_id |= (p[i + 3]) << 16; //IEEE ID high byte - p861info->vsvdb.ieee_id = ieee_id; - p861info->vsvdb.vendor_data_size = payload - 3; + if ((ieee_id == NVT_CEA861_DV_IEEE_ID) || (ieee_id == NVT_CEA861_HDR10PLUS_IEEE_ID)) + { + // exclude the extended tag + i++; payload--; - // move the pointer to the payload - i += 3; + p861info->vsvdb[vsvdb_index].ieee_id = ieee_id; + p861info->vsvdb[vsvdb_index].vendor_data_size = payload - 3; - // get the other vendor specific video data - for (j = 0; j < payload - 3; j++, i++) - { - if (j < NVT_CEA861_VSVDB_PAYLOAD_MAX_LENGTH) + // move the pointer to the payload + i += 3; + + // get the other vendor specific video data + for (j = 0; j < payload - 3; j++, i++) { - p861info->vsvdb.vendor_data[j] = p[i]; + if (j < NVT_CEA861_VSVDB_PAYLOAD_MAX_LENGTH) + { + p861info->vsvdb[vsvdb_index].vendor_data[j] = p[i]; + } } + + vsvdb_index++; + + p861info->total_vsvdb = (NvU8)vsvdb_index; + } - - if (p861info->vsvdb.ieee_id == NVT_CEA861_DV_IEEE_ID) - { - p861info->valid.dv_static_metadata = 1; - } - else if (p861info->vsvdb.ieee_id == NVT_CEA861_HDR10PLUS_IEEE_ID) + else { - p861info->valid.hdr10Plus = 1; + // skip the unsupported extended block + i += payload; } } else { - // skip the unsupported extended block + // skip the extended block that we don't have a room for, + // the NVT_CEA861_VSVDB_MAX_BLOCKS should be incremented for new VSVDB types + nvt_assert(vsvdb_index >= NVT_CEA861_VSVDB_MAX_BLOCKS); i += payload; } } @@ -2509,7 +2558,7 @@ NVT_STATUS NvTiming_ConstructExtendedMetadataPacketInfoframe( pInfoFrame->Header.firstLast = NVT_EMP_HEADER_FIRST_LAST; pInfoFrame->Header.sequenceIndex = 0x00; - if (pCtrl->EnableQMS) + if (pCtrl->Sync) { nvt_nvu8_set_bits(pInfoFrame->Data.byte1, NVT_HDMI_EMP_BYTE1_SYNC_ENABLE, NVT_HDMI_EMP_BYTE1_SYNC_MASK, @@ -2579,6 +2628,14 @@ NVT_STATUS NvTiming_ConstructExtendedMetadataPacketInfoframe( NVT_HDMI_EMP_BYTE8_MD2_RB_SHIFT); } + if (pCtrl->version == NVT_EXTENDED_METADATA_PACKET_INFOFRAME_VER_HDMI21A && pCtrl->EnableQMS) + { + nvt_nvu8_set_bits(pInfoFrame->Data.metadataBytes[2], + pCtrl->NextTFR, + NVT_HDMI_EMP_BYTE8_MD2_NEXT_TFR_MASK, + NVT_HDMI_EMP_BYTE8_MD2_NEXT_TFR_SHIFT); + } + // MSB for Base Refresh Rate nvt_nvu8_set_bits(pInfoFrame->Data.metadataBytes[2], pCtrl->BaseRefreshRate >> 8, @@ -3354,39 +3411,20 @@ void parseEdidHdmiForumVSDB(VSDB_DATA *pVsdb, NVT_HDMI_FORUM_INFO *pHdmiInfo) } CODE_SEGMENT(PAGE_DD_CODE) -void parseCea861Hdr10PlusDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag) +void parseCta861Hdr10PlusDataBlock(VSVDB_DATA* pVsvdb, NVT_HDR10PLUS_INFO* pHdr10PlusInfo) { - NVT_EDID_INFO *pInfo = NULL; - NVT_DISPLAYID_2_0_INFO *pDisplayID20 = NULL; - NVT_HDR10PLUS_INFO *pHdr10PlusInfo = NULL; - - if (pExt861 == NULL || pRawInfo == NULL) + if (pVsvdb == NULL || pHdr10PlusInfo == NULL) return; - if(pExt861->vsvdb.ieee_id != NVT_CEA861_HDR10PLUS_IEEE_ID) + if(pVsvdb->ieee_id != NVT_CEA861_HDR10PLUS_IEEE_ID) return; - if (flag == FROM_CTA861_EXTENSION || flag == FROM_DISPLAYID_13_DATA_BLOCK) - { - pInfo = (NVT_EDID_INFO *)pRawInfo; - pHdr10PlusInfo = &pInfo->hdr10PlusInfo; - } - else if (flag == FROM_DISPLAYID_20_DATA_BLOCK) - { - pDisplayID20 = (NVT_DISPLAYID_2_0_INFO *)pRawInfo; - pHdr10PlusInfo = &pDisplayID20->cta.hdr10PlusInfo; - } - else - { - return; - } - NVMISC_MEMSET(pHdr10PlusInfo, 0, sizeof(NVT_HDR10PLUS_INFO)); - if (pExt861->vsvdb.vendor_data_size < sizeof(NVT_HDR10PLUS_INFO)) + if (pVsvdb->vendor_data_size < sizeof(NVT_HDR10PLUS_INFO)) return; - NVMISC_MEMCPY(pHdr10PlusInfo, &pExt861->vsvdb.vendor_data, sizeof(NVT_HDR10PLUS_INFO)); + NVMISC_MEMCPY(pHdr10PlusInfo, &pVsvdb->vendor_data, sizeof(NVT_HDR10PLUS_INFO)); } CODE_SEGMENT(PAGE_DD_CODE) diff --git a/src/common/modeset/timing/nvt_edidext_displayid20.c b/src/common/modeset/timing/nvt_edidext_displayid20.c index fb4f15fb27..b2fbc383b2 100644 --- a/src/common/modeset/timing/nvt_edidext_displayid20.c +++ b/src/common/modeset/timing/nvt_edidext_displayid20.c @@ -34,9 +34,6 @@ PUSH_SEGMENTS -// DisplayId2 as EDID extension entry point functions -static NVT_STATUS parseDisplayId20EDIDExtSection(DISPLAYID_2_0_SECTION *section, NVT_EDID_INFO *pEdidInfo); - /** * * @brief Parses a displayId20 EDID Extension block, with timings stored in p and @@ -183,6 +180,8 @@ parseDisplayId20EDIDExtDataBlocks( NVT_STATUS status = NVT_STATUS_SUCCESS; NVT_DISPLAYID_2_0_INFO *pDisplayId20Info = NULL; + NvU8 i; + // size sanity checking if ((pDataBlock == NULL || RemainSectionLength <= NVT_DISPLAYID_DATABLOCK_HEADER_LEN) || (block_header->data_bytes > RemainSectionLength - NVT_DISPLAYID_DATABLOCK_HEADER_LEN)) @@ -195,7 +194,7 @@ parseDisplayId20EDIDExtDataBlocks( if (pEdidInfo != NULL) { - pDisplayId20Info = &(pEdidInfo->ext_displayid20); + pDisplayId20Info = &pEdidInfo->ext_displayid20; } *pCurrentDBLength = block_header->data_bytes + NVT_DISPLAYID_DATABLOCK_HEADER_LEN; @@ -234,6 +233,24 @@ parseDisplayId20EDIDExtDataBlocks( pDisplayId20Info->basic_caps |= NVT_DISPLAY_2_0_CAP_BASIC_AUDIO; } + for (i = 0; i < pDisplayId20Info->interface_features.combination_count; i++) + { + if (pDisplayId20Info->interface_features.colorspace_eotf_combination[i].eotf == INTERFACE_EOTF_SMPTE_ST2084 && + pDisplayId20Info->interface_features.colorspace_eotf_combination[i].color_space == INTERFACE_COLOR_SPACE_BT2020) + { + pEdidInfo->hdr_static_metadata_info.static_metadata_type = 1; + pEdidInfo->hdr_static_metadata_info.supported_eotf.smpte_st_2084_eotf = 1; + + pEdidInfo->ext861.hdr_static_metadata.byte1 |= NVT_CEA861_EOTF_SMPTE_ST2084; + pEdidInfo->ext861.colorimetry.byte1 |= NVT_CEA861_COLORIMETRY_BT2020RGB; + + if (IS_BPC_SUPPORTED_COLORFORMAT(pDisplayId20Info->interface_features.yuv444.bpcs) || + IS_BPC_SUPPORTED_COLORFORMAT(pDisplayId20Info->interface_features.yuv422.bpcs)) + { + pEdidInfo->ext861.colorimetry.byte1 |= NVT_CEA861_COLORIMETRY_BT2020YCC; + } + } + } break; // DisplayID_v2.0 E5 defined @@ -241,7 +258,7 @@ parseDisplayId20EDIDExtDataBlocks( // * support for 420 pixel encoding is limited to the timings exposed in the restricted set exposed in the CTA data block. // * field of "Mini Pixel Rate at YCbCr420" shall be set 00h case DISPLAYID_2_0_BLOCK_TYPE_CTA_DATA: - pDisplayId20Info->valid_data_blocks.cta_data_present = NV_TRUE; + pDisplayId20Info->valid_data_blocks.cta_data_present = NV_TRUE; // copy all the vendor specific data block from DisplayId20 to pEdidInfo // NOTE: mixed CTA extension block and DID2.0 extension block are not handled @@ -268,7 +285,7 @@ parseDisplayId20EDIDExtDataBlocks( pDisplayId20Info->basic_caps = pEdidInfo->ext861.basic_caps; } - // this is the DisplayID20 Extension, so we need to copy from what is the CTA raw data in DID20 to Edid's CTA block + // this is the DisplayID20 Extension, so we need to copy the data from the CTA in DID20 to CTA section if (pEdidInfo->ext861.revision == 0) NVMISC_MEMCPY(&pEdidInfo->ext861, &pDisplayId20Info->cta.cta861_info, sizeof(NVT_EDID_CEA861_INFO)); else if (pEdidInfo->ext861_2.revision == 0) @@ -276,9 +293,9 @@ parseDisplayId20EDIDExtDataBlocks( break; case DISPLAYID_2_0_BLOCK_TYPE_DISPLAY_PARAM: - pDisplayId20Info->valid_data_blocks.parameters_present = NV_TRUE; + pDisplayId20Info->valid_data_blocks.parameters_present = NV_TRUE; - // EDID only supported 10bits chromaitcity to match the OS D3DKMDT_2DOFFSET 10bits, so we don't need to transfer it here. + // EDID only supported 10bits chromaticity to match the OS D3DKMDT_2DOFFSET 10bits, so we don't need to transfer it here. pEdidInfo->input.u.digital.bpc = NVT_COLORDEPTH_HIGHEST_BPC(pDisplayId20Info->display_param.native_color_depth); pEdidInfo->gamma = pDisplayId20Info->display_param.gamma_x100; @@ -288,36 +305,43 @@ parseDisplayId20EDIDExtDataBlocks( pDisplayId20Info->basic_caps |= NVT_DISPLAY_2_0_CAP_BASIC_AUDIO; } + if (pDisplayId20Info->display_param.gamma_x100 != 0) + { + pEdidInfo->hdr_static_metadata_info.supported_eotf.trad_gamma_sdr_eotf = 1; + } break; case DISPLAYID_2_0_BLOCK_TYPE_STEREO: - pDisplayId20Info->valid_data_blocks.stereo_interface_present = NV_TRUE; + pDisplayId20Info->valid_data_blocks.stereo_interface_present = NV_TRUE; break; case DISPLAYID_2_0_BLOCK_TYPE_TILED_DISPLAY: - pDisplayId20Info->valid_data_blocks.tiled_display_present = NV_TRUE; + pDisplayId20Info->valid_data_blocks.tiled_display_present = NV_TRUE; break; case DISPLAYID_2_0_BLOCK_TYPE_CONTAINER_ID: - pDisplayId20Info->valid_data_blocks.container_id_present = NV_TRUE; + pDisplayId20Info->valid_data_blocks.container_id_present = NV_TRUE; break; case DISPLAYID_2_0_BLOCK_TYPE_TIMING_7: - pDisplayId20Info->valid_data_blocks.type7Timing_present = NV_TRUE; + pDisplayId20Info->valid_data_blocks.type7Timing_present = NV_TRUE; break; case DISPLAYID_2_0_BLOCK_TYPE_TIMING_8: - pDisplayId20Info->valid_data_blocks.type8Timing_present = NV_TRUE; + pDisplayId20Info->valid_data_blocks.type8Timing_present = NV_TRUE; break; case DISPLAYID_2_0_BLOCK_TYPE_TIMING_9: - pDisplayId20Info->valid_data_blocks.type9Timing_present = NV_TRUE; + pDisplayId20Info->valid_data_blocks.type9Timing_present = NV_TRUE; break; case DISPLAYID_2_0_BLOCK_TYPE_TIMING_10: - pDisplayId20Info->valid_data_blocks.type10Timing_present = NV_TRUE; + pDisplayId20Info->valid_data_blocks.type10Timing_present = NV_TRUE; break; case DISPLAYID_2_0_BLOCK_TYPE_RANGE_LIMITS: - pDisplayId20Info->valid_data_blocks.dynamic_range_limit_present = NV_TRUE; + pDisplayId20Info->valid_data_blocks.dynamic_range_limit_present = NV_TRUE; break; case DISPLAYID_2_0_BLOCK_TYPE_ADAPTIVE_SYNC: - pDisplayId20Info->valid_data_blocks.adaptive_sync_present = NV_TRUE; - break; + pDisplayId20Info->valid_data_blocks.adaptive_sync_present = NV_TRUE; + break; + case DISPLAYID_2_0_BLOCK_TYPE_BRIGHTNESS_LUMINANCE_RANGE: + pDisplayId20Info->valid_data_blocks.brightness_luminance_range_present = NV_TRUE; + break; case DISPLAYID_2_0_BLOCK_TYPE_VENDOR_SPEC: - pDisplayId20Info->valid_data_blocks.vendor_specific_present = NV_TRUE; + pDisplayId20Info->valid_data_blocks.vendor_specific_present = NV_TRUE; break; default: break; diff --git a/src/common/modeset/timing/nvt_ovt.c b/src/common/modeset/timing/nvt_ovt.c new file mode 100644 index 0000000000..df81d44a8e --- /dev/null +++ b/src/common/modeset/timing/nvt_ovt.c @@ -0,0 +1,30 @@ +//***************************************************************************** +// +// SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +// SPDX-License-Identifier: MIT +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +// DEALINGS IN THE SOFTWARE. +// +// File: nvt_ovt.c +// +// Purpose: calculate Optimized Video Timing (OVT) timing +// +//***************************************************************************** + + diff --git a/src/common/modeset/timing/nvtiming.h b/src/common/modeset/timing/nvtiming.h index dc7d142108..d818493381 100644 --- a/src/common/modeset/timing/nvtiming.h +++ b/src/common/modeset/timing/nvtiming.h @@ -806,7 +806,7 @@ typedef enum NVT_TV_FORMAT #define NVT_CEA861_SPEAKER_ALLOC_RLC_RRC 0x40 // speaker allocation : Rear Left Center + Rear Right Center //*********************** -// vendor specific data +// vendor specific data block (VSDB) //*********************** #define NVT_CEA861_VSDB_HEADER_SIZE 4 #define NVT_CEA861_VSDB_PAYLOAD_MAX_LENGTH 28 // max allowed vendor specific data block payload (in byte) @@ -829,8 +829,9 @@ typedef struct VSDB_DATA } VSDB_DATA; //******************************* -// vendor specific video data +// vendor specific video data block (VSVDB) //******************************* +#define NVT_CEA861_VSVDB_MAX_BLOCKS 2 // Dolby Vision, HDR10+ VSVDBs #define NVT_CEA861_DV_IEEE_ID 0x00D046 #define NVT_CEA861_HDR10PLUS_IEEE_ID 0x90848B #define NVT_CEA861_VSVDB_PAYLOAD_MAX_LENGTH 25 // max allowed vendor specific video data block payload (in byte) @@ -1287,7 +1288,8 @@ typedef struct tagEDID_CEA861_INFO VSDB_DATA vsdb[NVT_CEA861_VSDB_MAX_BLOCKS]; // vendor specific video data - VSVDB_DATA vsvdb; + NvU8 total_vsvdb; + VSVDB_DATA vsvdb[NVT_CEA861_VSVDB_MAX_BLOCKS]; // indicates which of the extended data blocks below contain valid data excluding extended blocks with total count NVT_VALID_EXTENDED_BLOCKS valid; @@ -2514,7 +2516,7 @@ typedef struct _tagNVT_DISPLAYID_DISPLAY_PARAMETERS NVT_COLOR_POINT white; NVT_NATIVE_LUMINANCE_INFO native_luminance_info; NvU16 native_max_luminance_full_coverage; - NvU16 native_max_luminance_1_percent_rect_coverage; + NvU16 native_max_luminance_10_percent_rect_coverage; NvU16 native_min_luminance; NVT_COLORDEPTH native_color_depth; NvU16 gamma_x100; @@ -2592,6 +2594,14 @@ typedef struct _tagNVT_DISPLAYID_CTA NVT_HDR10PLUS_INFO hdr10PlusInfo; } NVT_DISPLAYID_CTA; +typedef struct _tagNVT_DISPLAYID_BRIGHTNESS_LUMINANCE_RANGE +{ + NvU32 revision; + NvU16 min_sdr_luminance; + NvU16 max_sdr_luminance; + NvU16 max_boost_sdr_luminance; +} NVT_DISPLAYID_BRIGHTNESS_LUMINANCE_RANGE; + typedef struct _tagNVT_VALID_DATA_BLOCKS { NvBool product_id_present; @@ -2608,6 +2618,7 @@ typedef struct _tagNVT_VALID_DATA_BLOCKS NvBool adaptive_sync_present; NvBool arvr_hmd_present; NvBool arvr_layer_present; + NvBool brightness_luminance_range_present; NvBool vendor_specific_present; NvBool cta_data_present; } NVT_VALID_DATA_BLOCKS; @@ -2615,60 +2626,63 @@ typedef struct _tagNVT_VALID_DATA_BLOCKS #define NVT_DISPLAYID_MAX_TOTAL_TIMING NVT_MAX_TOTAL_TIMING typedef struct _tagNVT_DISPLAYID_2_0_INFO { - NvU8 revision; - NvU8 version; + NvU8 revision; + NvU8 version; // support audio/yuv444/yuv422 color for CTA861 compatible - NvU8 basic_caps; + NvU8 basic_caps; // the all extensions that may appear following the base section - NvU32 extension_count; + NvU32 extension_count; // this displayID20 is EDID extension or not - NvBool as_edid_extension; + NvBool as_edid_extension; // data blocks present or not - NVT_VALID_DATA_BLOCKS valid_data_blocks; + NVT_VALID_DATA_BLOCKS valid_data_blocks; - NVT_DISPLAYID_PRODUCT_PRIMARY_USE_CASE primary_use_case; + NVT_DISPLAYID_PRODUCT_PRIMARY_USE_CASE primary_use_case; // Product Identification Data Block (Mandatory) - NVT_DISPLAYID_PRODUCT_IDENTITY product_identity; + NVT_DISPLAYID_PRODUCT_IDENTITY product_identity; // Display Parameter Data Block (Mandatory for Display Use) - NVT_DISPLAYID_DISPLAY_PARAMETERS display_param; + NVT_DISPLAYID_DISPLAY_PARAMETERS display_param; // Detailed Timing Data Block (Mandatory for Display Use) - NvU32 total_timings; - NVT_TIMING timing[NVT_DISPLAYID_MAX_TOTAL_TIMING]; + NvU32 total_timings; + NVT_TIMING timing[NVT_DISPLAYID_MAX_TOTAL_TIMING]; // Enumerated Timing Code Data Block (Not Mandatory) // Formula-based Timing Data Block (Not Mandatory) // Dynamic Video Timing Range Limits Data Block (Not Mandatory) - NVT_DISPLAYID_RANGE_LIMITS range_limits; + NVT_DISPLAYID_RANGE_LIMITS range_limits; // Display Interface Features Data Block (Mandatory) - NVT_DISPLAYID_INTERFACE_FEATURES interface_features; + NVT_DISPLAYID_INTERFACE_FEATURES interface_features; // Stereo Display Interface Data Block (Not Mandatory) // Tiled Display Topology Data Block (Not Mandatory) - NVT_DISPLAYID_TILED_DISPLAY_TOPOLOGY tile_topo; + NVT_DISPLAYID_TILED_DISPLAY_TOPOLOGY tile_topo; // ContainerID Data Block (Mandatory for Multi-function Device) - NVT_DISPLAYID_CONTAINERID container_id; + NVT_DISPLAYID_CONTAINERID container_id; // Adaptive-Sync Data Block (Mandatory for display device supports Adaptive-Sync) - NvU32 total_adaptive_sync_descriptor; - NVT_DISPLAYID_ADAPTIVE_SYNC adaptive_sync_descriptor[NVT_ADAPTIVE_SYNC_DESCRIPTOR_MAX_COUNT]; + NvU32 total_adaptive_sync_descriptor; + NVT_DISPLAYID_ADAPTIVE_SYNC adaptive_sync_descriptor[NVT_ADAPTIVE_SYNC_DESCRIPTOR_MAX_COUNT]; + // Brightness Luminance Range Data Block (Mandatory for display device supports Nits based brightness control) + NVT_DISPLAYID_BRIGHTNESS_LUMINANCE_RANGE luminance_ranges; + // Vendor-specific Data Block (Not Mandatory) - NVT_DISPLAYID_VENDOR_SPECIFIC vendor_specific; + NVT_DISPLAYID_VENDOR_SPECIFIC vendor_specific; // CTA DisplayID Data Block (Not Mandatory) - NVT_DISPLAYID_CTA cta; + NVT_DISPLAYID_CTA cta; } NVT_DISPLAYID_2_0_INFO; #define NVT_EDID_PRIMARY_COLOR_FP2INT_FACTOR 1024 // Per EDID 1.4, 10bit color primary is encoded in floating point as (bit9/2 + bit8/4 + bi7/8 + ... + bit0) @@ -2934,6 +2948,8 @@ typedef struct tagNVT_EXTENDED_METADATA_PACKET_INFOFRAME_CTRL NvU32 ReducedBlanking; NvU32 BaseRefreshRate; NvU32 EnableQMS; + NvU32 NextTFR; + NvU32 Sync; } NVT_EXTENDED_METADATA_PACKET_INFOFRAME_CTRL; typedef struct tagNVT_ADAPTIVE_SYNC_SDP_CTRL @@ -3777,6 +3793,9 @@ typedef struct tagNVT_EXTENDED_METADATA_PACKET_INFOFRAME #define NVT_HDMI_EMP_BYTE8_MD2_RB_DISABLE 0 #define NVT_HDMI_EMP_BYTE8_MD2_RB_ENABLE 1 +#define NVT_HDMI_EMP_BYTE8_MD2_NEXT_TFR_MASK 0x1f +#define NVT_HDMI_EMP_BYTE8_MD2_NEXT_TFR_SHIFT 3 + #define NVT_HDMI_EMP_BYTE8_MD2_BASE_RR_MSB_MASK 0x03 #define NVT_HDMI_EMP_BYTE8_MD2_BASE_RR_MSB_SHIFT 0 @@ -5492,6 +5511,18 @@ typedef enum NVT_STATUS_ERR = 0x80000000, // generic get timing error NVT_STATUS_INVALID_PARAMETER, // passed an invalid parameter NVT_STATUS_NO_MEMORY, // memory allocation failed + NVT_STATUS_COLOR_FORMAT_NOT_SUPPORTED, + NVT_STATUS_INVALID_HBLANK, + NVT_STATUS_INVALID_BPC, + NVT_STATUS_INVALID_BPP, + NVT_STATUS_MAX_LINE_BUFFER_ERROR, + NVT_STATUS_OVERALL_THROUGHPUT_ERROR, + NVT_STATUS_DSC_SLICE_ERROR, + NVT_STATUS_PPS_SLICE_COUNT_ERROR, + NVT_STATUS_PPS_SLICE_HEIGHT_ERROR, + NVT_STATUS_PPS_SLICE_WIDTH_ERROR, + NVT_STATUS_INVALID_PEAK_THROUGHPUT, + NVT_STATUS_MIN_SLICE_COUNT_ERROR, } NVT_STATUS; //************************************* diff --git a/src/common/modeset/timing/nvtiming_pvt.h b/src/common/modeset/timing/nvtiming_pvt.h index 37ffa9f084..ce044da407 100644 --- a/src/common/modeset/timing/nvtiming_pvt.h +++ b/src/common/modeset/timing/nvtiming_pvt.h @@ -46,6 +46,10 @@ #include // NULL +#ifdef __cplusplus +extern "C" { +#endif + // EDID related private functions NvU32 getEdidVersion(NvU8 *pData, NvU32 *pVer); NvBool assignNextAvailableTiming(NVT_EDID_INFO *pInfo, const NVT_TIMING *pTiming); @@ -70,6 +74,7 @@ void parse861bShortTiming(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, N void parse861bShortYuv420Timing(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag); void parseCta861NativeOrPreferredTiming(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag); void parseCta861VsdbBlocks(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag); +void parseCta861VsvdbBlocks(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag); void parseCta861HfScdb(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag); void parseCta861HfEeodb(NVT_EDID_CEA861_INFO *pExt861, NvU32 *pTotalEdidExtensions); void parseEdidMsftVsdbBlock(VSDB_DATA *pVsdb, MSFT_VSDB_PARSED_INFO *vsdbInfo); @@ -79,8 +84,8 @@ void getEdidHDM1_4bVsdbTiming(NVT_EDID_INFO *pInfo); void parseEdidHDMILLCTiming(NVT_EDID_INFO *pInfo, VSDB_DATA *pVsdb, NvU32 *pSupported, HDMI3DSUPPORTMAP * pM); void parseEdidNvidiaVSDBBlock(VSDB_DATA *pVsdb, NVDA_VSDB_PARSED_INFO *vsdbInfo); void parseCea861HdrStaticMetadataDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag); -void parseCea861DvStaticMetadataDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag); -void parseCea861Hdr10PlusDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag); +void parseCta861DvStaticMetadataDataBlock(VSVDB_DATA* pVsvdb, NVT_DV_STATIC_METADATA* pDvInfo); +void parseCta861Hdr10PlusDataBlock(VSVDB_DATA* pVsvdb, NVT_HDR10PLUS_INFO* pHdr10PlusInfo); void parseCta861DIDType7VideoTimingDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo); void parseCta861DIDType8VideoTimingDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo); void parseCta861DIDType10VideoTimingDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo); @@ -89,6 +94,7 @@ NvBool isMatchedStandardTiming(NVT_EDID_INFO *pInfo, NVT_TIMING *pT); NvBool isMatchedEstablishedTiming(NVT_EDID_INFO *pInfo, NVT_TIMING *pT); NvU32 isHdmi3DStereoType(NvU8 StereoStructureType); NvU32 getCEA861TimingAspectRatio(NvU32 vic); +NvU8 getHighestPrioritySVRIdx(NvU8 svr); void SetActiveSpaceForHDMI3DStereo(const NVT_TIMING *pTiming, NVT_EXT_TIMING *pExtTiming); void AddModeToSupportMap(HDMI3DSUPPORTMAP * pMap, NvU8 vic, NvU8 structure, NvU8 Detail); void getMonitorDescriptorString(NvU8 *pEdid, NvU8 tag, char *str, int onceOnly); @@ -102,12 +108,16 @@ NVT_STATUS getDisplayId20EDIDExtInfo(NvU8* pDisplayid, NvU32 edidSize, NVT_EDID_ NVT_STATUS parseDisplayId20EDIDExtDataBlocks(NvU8* pDataBlock, NvU8 remainSectionLength, NvU8* pCurrentDBLength, NVT_EDID_INFO* pEdidInfo); NVT_STATUS parseDisplayId20Timing7Descriptor(const void *pDescriptor, NVT_TIMING *pTiming, NvU8 count); NVT_STATUS parseDisplayId20Timing8Descriptor(const void *pDescriptor, NVT_TIMING *pTiming, NvU8 codeType, NvU8 codeSize, NvU8 index, NvU8 count); +NVT_STATUS parseDisplayId20Timing9Descriptor(const void *pDescriptor, NVT_TIMING *pTiming, NvU8 count); NVT_STATUS parseDisplayId20Timing10Descriptor(const void *pDescriptor, NVT_TIMING *pTiming, NvU8 payloadBytes, NvU8 count); void updateColorFormatForDisplayIdExtnTimings(NVT_EDID_INFO* pInfo, NvU32 timingIdx); void updateColorFormatForDisplayId20ExtnTimings(NVT_EDID_INFO* pInfo, NvU32 timingIdx); NvBool assignNextAvailableDisplayId20Timing(NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo, const NVT_TIMING *pTiming); void updateColorFormatForDisplayId20Timings(NVT_DISPLAYID_2_0_INFO* pDisplayId2Info, NvU32 timingIdx); // End DisplayID +#ifdef __cplusplus +} +#endif NvU32 axb_div_c_old(NvU32 a, NvU32 b, NvU32 c); @@ -151,3 +161,4 @@ NvU32 axb_div_c_old(NvU32 a, NvU32 b, NvU32 c); #define NVT_TIMING_SENTINEL {0,0,0,0,0,0,0,0,0,0,0,0,0,0,NVT_TIMINGEXT_SENTINEL} #endif //__NVTIMING_PVT_H_ + diff --git a/src/common/nvlink/inband/interface/nvlink_inband_msg.h b/src/common/nvlink/inband/interface/nvlink_inband_msg.h index f58c390edb..26e71a4a3f 100644 --- a/src/common/nvlink/inband/interface/nvlink_inband_msg.h +++ b/src/common/nvlink/inband/interface/nvlink_inband_msg.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -59,7 +59,8 @@ #define NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_REQ 2 #define NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_RSP 3 #define NVLINK_INBAND_MSG_TYPE_MC_TEAM_RELEASE_REQ 4 -#define NVLINK_INBAND_MSG_TYPE_MAX 5 +#define NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_REQ_V2 5 +#define NVLINK_INBAND_MSG_TYPE_MAX 6 /* Nvlink Inband message packet header */ typedef struct @@ -106,6 +107,7 @@ typedef struct #define NVLINK_INBAND_FM_CAPS_BW_MODE_MIN NVBIT64(2) #define NVLINK_INBAND_FM_CAPS_BW_MODE_HALF NVBIT64(3) #define NVLINK_INBAND_FM_CAPS_BW_MODE_3QUARTER NVBIT64(4) +#define NVLINK_INBAND_FM_CAPS_MC_TEAM_SETUP_V2 NVBIT64(5) typedef struct { @@ -119,7 +121,8 @@ typedef struct NvU64 flaAddress; /* FLA starting address for the GPU */ NvU64 flaAddressRange; /* GPU FLA address range */ NvU32 linkMaskToBeReduced; /* bit mask of unused NVLink ports for P2P */ - NvU8 reserved[28]; /* For future use. Must be initialized to zero */ + NvU32 cliqueId; /* Fabric Clique Id */ + NvU8 reserved[24]; /* For future use. Must be initialized to zero */ } nvlink_inband_gpu_probe_rsp_t; typedef struct @@ -143,13 +146,42 @@ typedef struct nvlink_inband_mc_team_setup_req_t mcTeamSetupReq; } nvlink_inband_mc_team_setup_req_msg_t; +typedef struct +{ + NvU64 mcAllocSize; /* Multicast allocation size requested */ + NvU32 flags; /* For future use. Must be initialized to zero */ + NvU8 reserved[8]; /* For future use. Must be initialized to zero */ + NvU16 numGpuHandles; /* Number of GPUs in this team */ + NvU16 numKeys; /* Number of keys (a.k.a request ID) used by FM to send response */ + NvU64 gpuHandlesAndKeys[]; /* Array of probed handles and keys, should be last */ + + /* + * The array will be grouped and ordered as: . The first group of gpuHandles will belong to the exporter node, + * which will be followed by the importer nodes. + * + * Test case: If the exporter and importer nodes are same, then the message will + * have multiple keys belonging to the same node as: . Even though all gpuHandles belong to the same node, the + * first key should be considered from the exporter node and the rest from the importer + * nodes. + */ +} nvlink_inband_mc_team_setup_req_v2_t; + +typedef struct +{ + nvlink_inband_msg_header_t msgHdr; + nvlink_inband_mc_team_setup_req_v2_t mcTeamSetupReq; +} nvlink_inband_mc_team_setup_req_v2_msg_t; + typedef struct { NvU64 mcTeamHandle; /* Unique handle assigned for this Multicast team */ + /* Should be zero if the response is sent to the importer nodes */ NvU32 flags; /* For future use. Must be initialized to zero */ NvU8 reserved[8]; /* For future use. Must be initialized to zero */ NvU64 mcAddressBase; /* FLA starting address assigned for the Multicast slot */ - NvU64 mcAddressSize; /* Size of FLA assigned to the Multicast slot */ + NvU64 mcAddressSize; /* Should be same as mcAllocSize */ } nvlink_inband_mc_team_setup_rsp_t; typedef struct @@ -173,6 +205,27 @@ typedef struct #pragma pack(pop) -/* Don't add any code after this line */ +/********************* Don't add any message structs after this line ******************************/ + +/* Helpers */ +static NV_INLINE void nvlinkInitInbandMsgHdr +( + nvlink_inband_msg_header_t *pMsgHdr, + NvU16 type, + NvU32 len, + NvU64 requestId +) +{ + NvU8 i; + + pMsgHdr->requestId = requestId; + pMsgHdr->magicId = NVLINK_INBAND_MSG_MAGIC_ID_FM; + pMsgHdr->type = type; + pMsgHdr->length = len; + pMsgHdr->status = NV_OK; + + for (i = 0; i < sizeof(pMsgHdr->reserved); i++) + pMsgHdr->reserved[i] = 0; +} #endif diff --git a/src/common/nvlink/interface/nvlink.h b/src/common/nvlink/interface/nvlink.h index b93480a26f..404836136c 100644 --- a/src/common/nvlink/interface/nvlink.h +++ b/src/common/nvlink/interface/nvlink.h @@ -445,6 +445,18 @@ NvlStatus nvlink_lib_unregister_link(nvlink_link *link); NvlStatus nvlink_lib_return_device_count_by_type(NvU32 deviceType, NvU32 *numDevices); +/************************************************************************************************/ +/***************************** NVLink device management functions ******************************/ +/************************************************************************************************/ + +/* + * Update UUID and deviceName in core library + */ +NvlStatus nvlink_lib_update_uuid_and_device_name(nvlink_device_info *devInfo, + NvU8 *uuid, + char *deviceName); + + /************************************************************************************************/ /******************************* NVLink link management functions *******************************/ /************************************************************************************************/ diff --git a/src/common/nvlink/interface/nvlink_lib_ctrl.h b/src/common/nvlink/interface/nvlink_lib_ctrl.h index 0f20ac31c0..d77fbb04ca 100644 --- a/src/common/nvlink/interface/nvlink_lib_ctrl.h +++ b/src/common/nvlink/interface/nvlink_lib_ctrl.h @@ -1114,6 +1114,7 @@ typedef struct NvlStatus status; nvlink_link_state endStates[NVLINK_MAX_DEVICE_CONN]; NvU32 endStatesCount; + NvU64 time; } nvlink_get_device_link_states; /* diff --git a/src/common/nvlink/interface/nvlink_os.h b/src/common/nvlink/interface/nvlink_os.h index 80a2a3abe9..c23242a388 100644 --- a/src/common/nvlink/interface/nvlink_os.h +++ b/src/common/nvlink/interface/nvlink_os.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -64,6 +64,7 @@ void nvlink_assert(int expression); void nvlink_sleep(unsigned int ms); void nvlink_print(const char *, int, const char *, int, const char *, ...); int nvlink_is_admin(void); +NvU64 nvlink_get_platform_time(void); // Capability functions NvlStatus nvlink_acquire_fabric_mgmt_cap(void *osPrivate, NvU64 capDescriptor); diff --git a/src/common/nvlink/kernel/nvlink/core/nvlink_ioctl.c b/src/common/nvlink/kernel/nvlink/core/nvlink_ioctl.c index ad5a9cc9fc..029bb638aa 100644 --- a/src/common/nvlink/kernel/nvlink/core/nvlink_ioctl.c +++ b/src/common/nvlink/kernel/nvlink/core/nvlink_ioctl.c @@ -347,7 +347,7 @@ nvlink_core_get_device_by_devinfo { nvlink_device *tmpDev = NULL; - if ((devInfo == NULL) || (devInfo == NULL)) + if ((devInfo == NULL) || (dev == NULL)) { return; } diff --git a/src/common/nvlink/kernel/nvlink/core/nvlink_shutdown.c b/src/common/nvlink/kernel/nvlink/core/nvlink_shutdown.c index ea5fc0b40e..c4ff10bec8 100644 --- a/src/common/nvlink/kernel/nvlink/core/nvlink_shutdown.c +++ b/src/common/nvlink/kernel/nvlink/core/nvlink_shutdown.c @@ -965,6 +965,7 @@ nvlink_core_powerdown_floorswept_conns_to_off if (visitedConns == NULL) { + nvlink_free(connsToShutdown); return NVL_NO_MEM; } diff --git a/src/common/nvlink/kernel/nvlink/interface/nvlink_ioctl_entry.c b/src/common/nvlink/kernel/nvlink/interface/nvlink_ioctl_entry.c index b19e4b6f57..14f176eedf 100644 --- a/src/common/nvlink/kernel/nvlink/interface/nvlink_ioctl_entry.c +++ b/src/common/nvlink/kernel/nvlink/interface/nvlink_ioctl_entry.c @@ -2333,6 +2333,12 @@ nvlink_lib_ctrl_train_intranode_conns_parallel NvU32 i; NvU32 count = 0; + // sanity check endPointPairsCount + if (trainParams->endPointPairsCount > NVLINK_MAX_PARALLEL_CONNS_TRAIN_COUNT) + { + return NVL_BAD_ARGS; + } + // // sanity check the input parms // make sure that this call is for single node systems @@ -3688,10 +3694,14 @@ nvlink_lib_ctrl_get_device_link_states NvlStatus status = NVL_SUCCESS; NvU32 numLinks = 0; NvU32 i = 0; - NvU8 linkNumber; + NvU8 linkNumber; nvlink_link **links = (nvlink_link **)nvlink_malloc( sizeof(nvlink_link *) * NVLINK_MAX_DEVICE_CONN); + + // Get current monotonic time in seconds.nanoseconds + params->time = nvlink_get_platform_time(); + if (links == NULL) { return NVL_NO_MEM; diff --git a/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_device_mgmt_entry.c b/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_device_mgmt_entry.c new file mode 100644 index 0000000000..23685aa623 --- /dev/null +++ b/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_device_mgmt_entry.c @@ -0,0 +1,95 @@ +/******************************************************************************* + Copyright (c) 2023 NVidia Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. +*******************************************************************************/ + +#include "nvlink.h" +#include "nvlink_export.h" +#include "nvlink_os.h" +#include "../nvlink_ctx.h" +#include "../nvlink_helper.h" + +#include "nvlink_lock.h" + +/** + * Update UUID and deviceName in the Nvlink Core library + * + * @param[in] devInfo NVLink Device Info pointer + * @param[in] uuid Device UUID pointer + * @param[in] deviceName DeviceName pointer + * + * return NVL_SUCCESS if the update was successful + */ +NvlStatus +nvlink_lib_update_uuid_and_device_name +( + nvlink_device_info *devInfo, + NvU8 *uuid, + char *deviceName +) +{ + NvlStatus lock_status = NVL_SUCCESS; + nvlink_device *dev = NULL; + + if (devInfo == NULL || uuid == NULL || deviceName == NULL) + { + NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, + "%s: Bad input arguments!\n", + __FUNCTION__)); + return NVL_BAD_ARGS; + } + + // Acquire top-level lock + lock_status = nvlink_lib_top_lock_acquire(); + if (lock_status != NVL_SUCCESS) + { + NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, + "%s: Failed to acquire top-level lock\n", + __FUNCTION__)); + + return lock_status; + } + + // Top-level lock is now acquired + + devInfo->nodeId = nvlinkLibCtx.nodeId; + + // Get the Corelib device pointer and store it in nvlink_device struct + nvlink_core_get_device_by_devinfo(devInfo, &dev); + if (dev == NULL) + { + NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS, + "%s: Device not registered in corelib\n", __FUNCTION__)); + + // Release top-level lock + nvlink_lib_top_lock_release(); + + return NVL_NOT_FOUND; + } + + // Update the UUID and device name cached in Corelib for the correct device + dev->uuid = uuid; + dev->deviceName = deviceName; + + // Release top-level lock + nvlink_lib_top_lock_release(); + + return NVL_SUCCESS; +} diff --git a/src/common/nvlink/kernel/nvlink/nvlink_lib_mgmt.c b/src/common/nvlink/kernel/nvlink/nvlink_lib_mgmt.c index 9f1a66488a..9925329316 100644 --- a/src/common/nvlink/kernel/nvlink/nvlink_lib_mgmt.c +++ b/src/common/nvlink/kernel/nvlink/nvlink_lib_mgmt.c @@ -169,9 +169,9 @@ nvlink_lib_is_device_list_empty(void) NvBool nvlink_lib_is_registerd_device_with_reduced_config(void) { - NvlStatus lock_status = NVL_SUCCESS; - nvlink_device *dev = NULL; - NvBool bIsReducedConfg = NV_FALSE; + NvlStatus lock_status = NVL_SUCCESS; + nvlink_device *dev = NULL; + NvBool bIsReducedConfig = NV_FALSE; // Acquire top-level lock lock_status = nvlink_lib_top_lock_acquire(); @@ -186,9 +186,13 @@ nvlink_lib_is_registerd_device_with_reduced_config(void) FOR_EACH_DEVICE_REGISTERED(dev, nvlinkLibCtx.nv_devicelist_head, node) { + // + // If the device is a reduced config set bIsReducedConfig to NV_TRUE + // and break to ensure that top level lock is released below + // if (dev->bReducedNvlinkConfig == NV_TRUE) { - bIsReducedConfg = NV_TRUE; + bIsReducedConfig = NV_TRUE; break; } } @@ -196,7 +200,7 @@ nvlink_lib_is_registerd_device_with_reduced_config(void) // Release top-level lock nvlink_lib_top_lock_release(); - return bIsReducedConfg; + return bIsReducedConfig; } /* diff --git a/src/common/nvlink/kernel/nvlink/nvlink_lock.c b/src/common/nvlink/kernel/nvlink/nvlink_lock.c index 7e2f0d986e..ab902ba229 100644 --- a/src/common/nvlink/kernel/nvlink/nvlink_lock.c +++ b/src/common/nvlink/kernel/nvlink/nvlink_lock.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2020-2023 NVidia Corporation + Copyright (c) 2020 NVidia Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the @@ -296,9 +296,9 @@ nvlink_lib_link_locks_acquire "%s: Acquire link lock for dom:%d bus:%d dev:%d fun:%d link:%d\n", __FUNCTION__, - links[i]->dev->pciInfo.domain, links[i]->dev->pciInfo.bus, - links[i]->dev->pciInfo.device, links[i]->dev->pciInfo.function, - links[i]->linkNumber)); + links[i]->dev->pciInfo.domain, links[i]->dev->pciInfo.bus, + links[i]->dev->pciInfo.device, links[i]->dev->pciInfo.function, + links[i]->linkNumber)); } link_prev = links[i]; @@ -358,9 +358,9 @@ nvlink_lib_link_locks_release "%s: Release link lock for dom:%d bus:%d dev:%d fun:%d link:%d\n", __FUNCTION__, - links[i]->dev->pciInfo.domain, links[i]->dev->pciInfo.bus, - links[i]->dev->pciInfo.device, links[i]->dev->pciInfo.function, - links[i]->linkNumber)); + links[i]->dev->pciInfo.domain, links[i]->dev->pciInfo.bus, + links[i]->dev->pciInfo.device, links[i]->dev->pciInfo.function, + links[i]->linkNumber)); } link_prev = links[i]; diff --git a/src/common/nvswitch/common/inc/soe/soeifcore.h b/src/common/nvswitch/common/inc/soe/soeifcore.h index 354b20d829..976dc2163e 100644 --- a/src/common/nvswitch/common/inc/soe/soeifcore.h +++ b/src/common/nvswitch/common/inc/soe/soeifcore.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/common/nvswitch/common/inc/soe/soeififr.h b/src/common/nvswitch/common/inc/soe/soeififr.h index b7504ce3fc..4fb67c03a1 100644 --- a/src/common/nvswitch/common/inc/soe/soeififr.h +++ b/src/common/nvswitch/common/inc/soe/soeififr.h @@ -37,6 +37,17 @@ enum RM_SOE_IFR_BBX_SHUTDOWN, RM_SOE_IFR_BBX_SXID_ADD, RM_SOE_IFR_BBX_SXID_GET, + RM_SOE_IFR_BBX_DATA_GET, +}; + +enum +{ + RM_SOE_IFR_BBX_GET_NONE, + RM_SOE_IFR_BBX_GET_SXID, + RM_SOE_IFR_BBX_GET_SYS_INFO, + RM_SOE_IFR_BBX_GET_TIME_INFO, + RM_SOE_IFR_BBX_GET_TEMP_DATA, + RM_SOE_IFR_BBX_GET_TEMP_SAMPLES, }; typedef struct @@ -75,6 +86,14 @@ typedef struct RM_FLCN_U64 dmaHandle; } RM_SOE_IFR_CMD_BBX_SXID_GET_PARAMS; +typedef struct +{ + NvU8 cmdType; + NvU32 sizeInBytes; + RM_FLCN_U64 dmaHandle; + NvU8 dataType; +} RM_SOE_IFR_CMD_BBX_GET_DATA_PARAMS; + typedef union { NvU8 cmdType; @@ -82,6 +101,7 @@ typedef union RM_SOE_IFR_CMD_BBX_INIT_PARAMS bbxInit; RM_SOE_IFR_CMD_BBX_SXID_ADD_PARAMS bbxSxidAdd; RM_SOE_IFR_CMD_BBX_SXID_GET_PARAMS bbxSxidGet; + RM_SOE_IFR_CMD_BBX_GET_DATA_PARAMS bbxDataGet; } RM_SOE_IFR_CMD; // entry of getSxid @@ -99,4 +119,81 @@ typedef struct RM_SOE_BBX_SXID_ENTRY sxidLast[INFOROM_BBX_OBJ_XID_ENTRIES]; } RM_SOE_BBX_GET_SXID_DATA; +// NVSwitch system version information returning with the command GET_SYS_INFO +typedef struct +{ + NvU32 driverLo; //Driver Version Low 32 bits + NvU16 driverHi; //Driver Version High 16 bits + NvU32 vbiosVersion; //VBIOS Version + NvU8 vbiosVersionOem; //VBIOS OEM Version byte + NvU8 osType; //OS Type (UNIX/WIN/WIN2K/WIN9x/OTHER) + NvU32 osVersion; //OS Version (Build|MINOR|MAJOR) +} RM_SOE_BBX_GET_SYS_INFO_DATA; + +// NVSwitch time information returning with the command GET_TIME_INFO +typedef struct +{ + NvU32 timeStart; //Timestamp (EPOCH) when the driver was loaded on the GPU for the first time + NvU32 timeEnd; //Timestamp (EPOCH) when the data was last flushed + NvU32 timeRun; //Amount of time (in seconds) driver was loaded, and GPU has run + NvU32 time24Hours; //Timestamp (EPOCH) of when the first 24 operational hours is hit + NvU32 time100Hours; //Timestamp (EPOCH) of when the first 100 operational hours is hit +} RM_SOE_BBX_GET_TIME_INFO_DATA; + +#define RM_SOE_BBX_TEMP_DAY_ENTRIES 5 +#define RM_SOE_BBX_TEMP_WEEK_ENTRIES 5 +#define RM_SOE_BBX_TEMP_MNT_ENTRIES 5 +#define RM_SOE_BBX_TEMP_ALL_ENTRIES 5 +#define RM_SOE_BBX_TEMP_SUM_HOUR_ENTRIES 23 +#define RM_SOE_BBX_TEMP_SUM_DAY_ENTRIES 5 +#define RM_SOE_BBX_TEMP_SUM_MNT_ENTRIES 3 +#define RM_SOE_BBX_TEMP_HISTOGRAM_THLD_ENTRIES 20 +#define RM_SOE_BBX_TEMP_HISTOGRAM_TIME_ENTRIES 21 +#define RM_SOE_BBX_TEMP_HOURLY_MAX_ENTRIES 168 +#define RM_SOE_BBX_TEMP_COMPRESS_BUFFER_ENTRIES 1096 +#define RM_SOE_BBX_NUM_COMPRESSION_PERIODS 8 + +// NVSwitch Temperature Entry +typedef struct +{ + NvU16 value; //Temperature (SFXP 9.7 format in Celsius) + NvU32 timestamp; //Timestamp (EPOCH) of when the entry is recorded +} RM_SOE_BBX_TEMP_ENTRY; + +// NVSwitch Temperature Data returning with the command GET_TEMP_DATA +typedef struct +{ + NvU32 tempMaxDayIdx; + RM_SOE_BBX_TEMP_ENTRY tempMaxDay[RM_SOE_BBX_TEMP_DAY_ENTRIES]; + NvU32 tempMaxWeekIdx; + RM_SOE_BBX_TEMP_ENTRY tempMaxWeek[RM_SOE_BBX_TEMP_WEEK_ENTRIES]; + NvU32 tempMaxMntIdx; + RM_SOE_BBX_TEMP_ENTRY tempMaxMnt[RM_SOE_BBX_TEMP_MNT_ENTRIES]; + NvU32 tempMaxAllIdx; + RM_SOE_BBX_TEMP_ENTRY tempMaxAll[RM_SOE_BBX_TEMP_ALL_ENTRIES]; + NvU32 tempMinDayIdx; + RM_SOE_BBX_TEMP_ENTRY tempMinDay[RM_SOE_BBX_TEMP_DAY_ENTRIES]; + NvU32 tempMinWeekIdx; + RM_SOE_BBX_TEMP_ENTRY tempMinWeek[RM_SOE_BBX_TEMP_WEEK_ENTRIES]; + NvU32 tempMinMntIdx; + RM_SOE_BBX_TEMP_ENTRY tempMinMnt[RM_SOE_BBX_TEMP_MNT_ENTRIES]; + NvU32 tempMinAllIdx; + RM_SOE_BBX_TEMP_ENTRY tempMinAll[RM_SOE_BBX_TEMP_ALL_ENTRIES]; + NvU32 tempSumDelta; + NvU32 tempSumHour[RM_SOE_BBX_TEMP_SUM_HOUR_ENTRIES]; + NvU32 tempSumDay[RM_SOE_BBX_TEMP_SUM_DAY_ENTRIES]; + NvU32 tempSumMnt[RM_SOE_BBX_TEMP_SUM_MNT_ENTRIES]; + NvU32 tempHistogramThld[RM_SOE_BBX_TEMP_HISTOGRAM_THLD_ENTRIES]; + NvU32 tempHistogramTime[RM_SOE_BBX_TEMP_HISTOGRAM_TIME_ENTRIES]; + RM_SOE_BBX_TEMP_ENTRY tempHourlyMaxSample[RM_SOE_BBX_TEMP_HOURLY_MAX_ENTRIES]; +} RM_SOE_BBX_GET_TEMP_DATA; + +// NVSwitch Temperature Compressed Samples returning with the command GET_TEMP_SAMPLES +typedef struct +{ + NvU32 compressionPeriodIdx; + NvU32 compressionPeriod[RM_SOE_BBX_NUM_COMPRESSION_PERIODS]; + RM_SOE_BBX_TEMP_ENTRY tempCompressionBuffer[RM_SOE_BBX_TEMP_COMPRESS_BUFFER_ENTRIES]; +} RM_SOE_BBX_GET_TEMP_SAMPLES; + #endif // _SOEIFIFR_H_ diff --git a/src/common/nvswitch/interface/ctrl_dev_nvswitch.h b/src/common/nvswitch/interface/ctrl_dev_nvswitch.h index 7234bb3114..fd9a6aa1b0 100644 --- a/src/common/nvswitch/interface/ctrl_dev_nvswitch.h +++ b/src/common/nvswitch/interface/ctrl_dev_nvswitch.h @@ -1323,6 +1323,57 @@ typedef struct nvswitch_get_errors NVSWITCH_ERROR error[NVSWITCH_ERROR_COUNT_SIZE]; } NVSWITCH_GET_ERRORS_PARAMS; +/* +* CTRL_NVSWITCH_GET_PORT_EVENTS +* +* Control for querying port up and port down event information +* +* Parameters: +* +* portEventIndex [IN/OUT] +* On input: The index of the first port event at which to start reading out of the driver. +* +* On output: The index of the first port event that wasn't reported through the 'port event' array +* in this call to CTRL_NVSWITCH_GET_PORT_EVENTS. +* +* nextPortEventIndex[OUT] +* The index that will be assigned to the next port event to occur. +* Users of the GET_PORT_EVENTS control call may set 'portEventIndex' to this field on initialization +* to bypass port events that have already occurred without making multiple control calls. +* +* portEventCount [OUT] +* Number of port events returned by the call. Currently, portEventCount is limited +* by NVSWITCH_PORT_EVENT_COUNT_SIZE. In order to query all the port events, a +* client needs to keep calling the control till portEventCount is zero. +* +* bOverflow [OUT] +* True when the port event log is overflowed and no longer contains all the port +* events that have occurred, false otherwise. +* +* portEvent [OUT] +* The port event entires. +*/ +#define NVSWITCH_PORT_EVENT_COUNT_SIZE 64 +#define NVSWITCH_PORT_EVENT_TYPE_UP 0 +#define NVSWITCH_PORT_EVENT_TYPE_DOWN 1 +#define NVSWITCH_PORT_EVENT_TYPE_INVALID 2 + +typedef struct +{ + NvU8 port_event_type; /* NVSWITCH_PORT_EVENT_TYPE* */ + NvU32 link_id; /* Link # that event occurred on */ + NV_DECLARE_ALIGNED(NvU64 time, 8); /* Platform time (nsec) when event occurred */ +} NVSWITCH_PORT_EVENT; + +typedef struct nvswitch_get_port_events +{ + NvU64 portEventIndex; + NvU64 nextPortEventIndex; + NvU32 portEventCount; + NvBool bOverflow; + NVSWITCH_PORT_EVENT portEvent[NVSWITCH_PORT_EVENT_COUNT_SIZE]; +} NVSWITCH_GET_PORT_EVENTS_PARAMS; + /* * CTRL_NVSWITCH_GET_INTERNAL_LATENCY * @@ -2973,6 +3024,197 @@ typedef struct NVSWITCH_SXID_ENTRY sxidLast[NVSWITCH_SXID_ENTRIES_NUM]; } NVSWITCH_GET_SXIDS_PARAMS; +/* + * CTRL_NVSWITCH_GET_SYS_INFO + * + * Control to get the NVSwitch system version information from inforom cache + * + * Parameters: + * driverLo [OUT] + * The driver version low 32 bits. Example: driverLo = 54531 (Driver 545.31) + * driverHi [OUT] + * The driver version high 16 bits + * vbiosVersion [OUT] + * The vbios version number. Example: vbiosVersion=0x96104100 (release 96.10.41.00) + * vbiosVersionOem [OUT] + * The vbios OEM version byte. + * osType [OUT] + * The OS type. Example: osType=0x05 (UNIX) + * osVersion [OUT] + * The OS version number. [BUILD[31:16]|MINOR[15:8]|MAJOR[7:0]] + */ + +typedef struct +{ + NvU32 driverLo; + NvU16 driverHi; + NvU32 vbiosVersion; + NvU8 vbiosVersionOem; + NvU8 osType; + NvU32 osVersion; +} NVSWITCH_GET_SYS_INFO_PARAMS; + +/* + * CTRL_NVSWITCH_GET_TIME_INFO + * + * Control to get the NVSwitch time information from inforom cache + * + * Parameters: + * timeStart [OUT] + * The timestamp (EPOCH) when driver load onto the NVSwitch for the 1st time + * timeEnd [OUT] + * The timestamp (EPOCH) when the data was last flushed + * timeRun [OUT] + * The amount of time (in seconds) driver was loaded/running + * time24Hours [OUT] + * The timestamp (EPOCH) when the first 24 operational hours is hit + * time100Hours [OUT] + * The timestamp (EPOCH) when the first 100 operational hours is hit + */ + +typedef struct +{ + NvU32 timeStart; + NvU32 timeEnd; + NvU32 timeRun; + NvU32 time24Hours; + NvU32 time100Hours; +} NVSWITCH_GET_TIME_INFO_PARAMS; + +#define NVSWITCH_TEMP_DAY_ENTRIES 5 +#define NVSWITCH_TEMP_WEEK_ENTRIES 5 +#define NVSWITCH_TEMP_MNT_ENTRIES 5 +#define NVSWITCH_TEMP_ALL_ENTRIES 5 +#define NVSWITCH_TEMP_SUM_HOUR_ENTRIES 23 +#define NVSWITCH_TEMP_SUM_DAY_ENTRIES 5 +#define NVSWITCH_TEMP_SUM_MNT_ENTRIES 3 +#define NVSWITCH_TEMP_HISTOGRAM_THLD_ENTRIES 20 +#define NVSWITCH_TEMP_HISTOGRAM_TIME_ENTRIES 21 +#define NVSWITCH_TEMP_HOURLY_MAX_ENTRIES 168 + +/* + * NVSWITCH_TEMP_ENTRY + * + * This structure represents the NVSwitch TEMP with its timestamp. + * + * value + * This parameter specifies the NVSwitch Temperature + * (SFXP 9.7 format in Celsius). + * + * timestamp + * This parameter specifies the timestamp (EPOCH) of the entry. + */ +typedef struct +{ + NvU16 value; + NvU32 timestamp; +} NVSWITCH_TEMP_ENTRY; + +/* + * CTRL_NVSWITCH_GET_TEMP_DATA + * + * Control to get the NVSwitch device historical temperature information from inforom cache + * + * Parameters: + * tempMaxDayIdx [OUT] + * The current index to the maximum day temperature array + * tempMaxDay[] [OUT] + * The maximum temperature array for last NVSWITCH_TEMP_DAY_ENTRIES days + * tempMaxWeekIdx [OUT] + * The current index to the maximum week temperature array + * tempMaxWeek[] [OUT] + * The maximum temperature array for last NVSWITCH_TEMP_WEEK_ENTRIES weeks + * tempMaxMntIdx [OUT] + * The current index to the maximum month temperature array + * tempMaxMnt[] [OUT] + * The maximum temperature array for last NVSWITCH_TEMP_MNT_ENTRIES months + * tempMaxAllIdx [OUT] + * The current index to the maximum temperature array + * tempMaxAll[] [OUT] + * The maximum temperature array for the device + * tempMinDayIdx [OUT] + * The current index to the minimum day temperature array + * tempMinDay[] [OUT] + * The minimum temperature array for last NVSWITCH_TEMP_DAY_ENTRIES days + * tempMinWeekIdx [OUT] + * The current index to the minimum week temperature array + * tempMinWeek[] [OUT] + * The minimum temperature array for last NVSWITCH_TEMP_WEEK_ENTRIES weeks + * tempMinMntIdx [OUT] + * The current index to the minimum month temperature array + * tempMinMnt[] [OUT] + * The minimum temperature array for last NVSWITCH_TEMP_MNT_ENTRIES months + * tempMinAllIdx [OUT] + * The current index to the minimum temperature array + * tempMinAll[] [OUT] + * The minimum temperature array for the device + * tempSumDelta [OUT] + * The total sum of temperature change in 0.1C granularity + * tempSumHour[] [OUT] + * The moving average of temperature per hour, for last NVSWITCH_TEMP_SUM_HOUR_ENTRIES hours + * tempSumDay[] [OUT] + * The moving average of temperature per day, for last NVSWITCH_TEMP_SUM_DAY_ENTRIES days + * tempSumMnt[] [OUT] + * The moving average of temperature per month, for last NVSWITCH_TEMP_SUM_MNT_ENTRIES months + * tempHistogramThld[] [OUT] + * The histogram of temperature crossing various thresholds (5/10/15/.../95/100) + * tempHistogramTime[] [OUT] + * The histogram of time was in various temperature ranges (0..5/5..10/.../100..) + * tempHourlyMaxSample[] [OUT] + * The maximum hourly temperature array for the device + */ + +typedef struct +{ + NvU32 tempMaxDayIdx; + NVSWITCH_TEMP_ENTRY tempMaxDay[NVSWITCH_TEMP_DAY_ENTRIES]; + NvU32 tempMaxWeekIdx; + NVSWITCH_TEMP_ENTRY tempMaxWeek[NVSWITCH_TEMP_WEEK_ENTRIES]; + NvU32 tempMaxMntIdx; + NVSWITCH_TEMP_ENTRY tempMaxMnt[NVSWITCH_TEMP_MNT_ENTRIES]; + NvU32 tempMaxAllIdx; + NVSWITCH_TEMP_ENTRY tempMaxAll[NVSWITCH_TEMP_ALL_ENTRIES]; + NvU32 tempMinDayIdx; + NVSWITCH_TEMP_ENTRY tempMinDay[NVSWITCH_TEMP_DAY_ENTRIES]; + NvU32 tempMinWeekIdx; + NVSWITCH_TEMP_ENTRY tempMinWeek[NVSWITCH_TEMP_WEEK_ENTRIES]; + NvU32 tempMinMntIdx; + NVSWITCH_TEMP_ENTRY tempMinMnt[NVSWITCH_TEMP_MNT_ENTRIES]; + NvU32 tempMinAllIdx; + NVSWITCH_TEMP_ENTRY tempMinAll[NVSWITCH_TEMP_ALL_ENTRIES]; + NvU32 tempSumDelta; + NvU32 tempSumHour[NVSWITCH_TEMP_SUM_HOUR_ENTRIES]; + NvU32 tempSumDay[NVSWITCH_TEMP_SUM_DAY_ENTRIES]; + NvU32 tempSumMnt[NVSWITCH_TEMP_SUM_MNT_ENTRIES]; + NvU32 tempHistogramThld[NVSWITCH_TEMP_HISTOGRAM_THLD_ENTRIES]; + NvU32 tempHistogramTime[NVSWITCH_TEMP_HISTOGRAM_TIME_ENTRIES]; + NVSWITCH_TEMP_ENTRY tempHourlyMaxSample[NVSWITCH_TEMP_HOURLY_MAX_ENTRIES]; +} NVSWITCH_GET_TEMP_DATA_PARAMS; + +#define NVSWITCH_TEMP_COMPRESS_BUFFER_ENTRIES 1096 +#define NVSWITCH_NUM_COMPRESSION_PERIODS 8 + +/* + * CTRL_NVSWITCH_GET_TEMP_DATA + * + * Control to get the NVSwitch device temperature information from inforom cache + * + * Parameters: + * compressionPeriodIdx [OUT] + * The current index to the sample period array + * compressionPeriod[] [OUT] + * The samples period array (seconds) + * tempCompressionBuffer[] [OUT] + * The temperature array sampling at a specific period in compressionPeriod[] + */ + +typedef struct +{ + NvU32 compressionPeriodIdx; + NvU32 compressionPeriod[NVSWITCH_NUM_COMPRESSION_PERIODS]; + NVSWITCH_TEMP_ENTRY tempCompressionBuffer[NVSWITCH_TEMP_COMPRESS_BUFFER_ENTRIES]; +} NVSWITCH_GET_TEMP_SAMPLES_PARAMS; + /* * CTRL_NVSWITCH_GET_FOM_VALUES * This command gives the FOM values to MODS @@ -3848,6 +4090,11 @@ typedef struct #define CTRL_NVSWITCH_RESERVED_11 0x55 #define CTRL_NVSWITCH_GET_BOARD_PART_NUMBER 0x56 #define CTRL_NVSWITCH_GET_POWER 0x57 +#define CTRL_NVSWITCH_GET_PORT_EVENTS 0x58 +#define CTRL_NVSWITCH_GET_SYS_INFO 0x59 +#define CTRL_NVSWITCH_GET_TIME_INFO 0x60 +#define CTRL_NVSWITCH_GET_TEMP_DATA 0x61 +#define CTRL_NVSWITCH_GET_TEMP_SAMPLES 0x62 #ifdef __cplusplus } diff --git a/src/common/nvswitch/interface/export_nvswitch.h b/src/common/nvswitch/interface/export_nvswitch.h index 275faa06a0..2c083a9a0d 100644 --- a/src/common/nvswitch/interface/export_nvswitch.h +++ b/src/common/nvswitch/interface/export_nvswitch.h @@ -50,10 +50,11 @@ extern "C" { #define NVSWITCH_NSEC_PER_SEC 1000000000ULL #define NVSWITCH_DBG_LEVEL_MMIO 0x0 -#define NVSWITCH_DBG_LEVEL_INFO 0x1 -#define NVSWITCH_DBG_LEVEL_SETUP 0x2 -#define NVSWITCH_DBG_LEVEL_WARN 0x3 -#define NVSWITCH_DBG_LEVEL_ERROR 0x4 +#define NVSWITCH_DBG_LEVEL_NOISY 0x1 +#define NVSWITCH_DBG_LEVEL_INFO 0x2 +#define NVSWITCH_DBG_LEVEL_SETUP 0x3 +#define NVSWITCH_DBG_LEVEL_WARN 0x4 +#define NVSWITCH_DBG_LEVEL_ERROR 0x5 #define NVSWITCH_LOG_BUFFER_SIZE 512 @@ -337,7 +338,7 @@ nvswitch_lib_service_interrupts ); /* - * @Brief : Get depth of error logs + * @Brief : Get depth of error logs and port event log * * @Description : * @@ -345,6 +346,7 @@ nvswitch_lib_service_interrupts * * @param[out] fatal Count of fatal errors * @param[out] nonfatal Count of non-fatal errors + * @param[out] portEvent Count of port events * * @returns NVL_SUCCESS if there were no errors and interrupts were handled * -NVL_NOT_FOUND if bad arguments provided @@ -353,7 +355,7 @@ NvlStatus nvswitch_lib_get_log_count ( nvswitch_device *device, - NvU32 *fatal, NvU32 *nonfatal + NvU32 *fatal, NvU32 *nonfatal, NvU32 *portEvent ); /* diff --git a/src/common/nvswitch/kernel/inc/common_nvswitch.h b/src/common/nvswitch/kernel/inc/common_nvswitch.h index 370dc28748..d654bda7b1 100644 --- a/src/common/nvswitch/kernel/inc/common_nvswitch.h +++ b/src/common/nvswitch/kernel/inc/common_nvswitch.h @@ -94,12 +94,12 @@ static NV_INLINE void nvswitch_clear_flags(NvU32 *val, NvU32 flags) #endif #define NV_ARRAY_ELEMENTS(x) ((sizeof(x)/sizeof((x)[0]))) - -#define NVSWITCH_DBG_LEVEL NVSWITCH_DBG_LEVEL_INFO + +#define NVSWITCH_DBG_LEVEL(_d) (_d == NULL ? NVSWITCH_DBG_LEVEL_INFO : ((nvswitch_device *)_d)->regkeys.debug_level) #if defined(DEVELOP) || defined(DEBUG) || defined(NV_MODS) #define NVSWITCH_PRINT(_d, _lvl, _fmt, ...) \ - ((NVSWITCH_DBG_LEVEL <= NVSWITCH_DBG_LEVEL_ ## _lvl) ? \ + ((NVSWITCH_DBG_LEVEL(_d) <= NVSWITCH_DBG_LEVEL_ ## _lvl) ? \ nvswitch_os_print(NVSWITCH_DBG_LEVEL_ ## _lvl, \ "%s[%-5s]: " _fmt, \ ((_d == NULL) ? \ @@ -271,6 +271,7 @@ typedef struct NvU32 surpress_link_errors_for_gpu_reset; NvU32 block_code_mode; NvU32 reference_clock_mode; + NvU32 debug_level; } NVSWITCH_REGKEY_TYPE; // @@ -341,6 +342,30 @@ struct NVSWITCH_CLIENT_EVENT void *private_driver_data; }; +typedef struct +{ + NvU8 port_event_type; // 0 = port up, 1 = port down, 2 = error invalid entry + NvU64 local_port_event_num; // Count of preceding port events (local port event log) + NvU64 global_port_event_num; // Count of preceding port events (globally) + NvU32 link_id; // Link that event occured on + NvU64 time; // Platform time, in ns +} NVSWITCH_PORT_EVENT_TYPE; + +#define NVSWITCH_PORT_EVENT_LOG_SIZE 1024 + +typedef struct +{ + NvU32 port_event_start; // Start index within CB (circular buffer) + NvU32 port_event_count; // Count of current port events in CB + NvU64 port_event_total; // Count of total port events logged + NvU32 port_event_log_size; // CB size + NVSWITCH_PORT_EVENT_TYPE *port_event_log; + NvBool overwritable; // Old entries can be overwritten + NvBool bOverflow; // True when log has been overflowed and no + // longer contains all port events that occurred +} NVSWITCH_PORT_EVENT_LOG_TYPE; + + // // common device information // @@ -369,6 +394,9 @@ struct nvswitch_device NVSWITCH_ERROR_LOG_TYPE log_FATAL_ERRORS; NVSWITCH_ERROR_LOG_TYPE log_NONFATAL_ERRORS; + // Port Events + NVSWITCH_PORT_EVENT_LOG_TYPE log_PORT_EVENTS; + NVSWITCH_FIRMWARE firmware; // HAL connectivity @@ -582,4 +610,7 @@ void nvswitch_apply_recal_settings(nvswitch_device *device, nvlink_link *li void nvswitch_init_buffer_ready(nvswitch_device *device, nvlink_link *link, NvBool bNportBufferReady); NvBool nvswitch_does_link_need_termination_enabled(nvswitch_device *device, nvlink_link *link); NvlStatus nvswitch_link_termination_setup(nvswitch_device *device, nvlink_link* link); +void nvswitch_record_port_event(nvswitch_device *device, NVSWITCH_PORT_EVENT_LOG_TYPE *port_events, NvU32 link_id, NvU8 port_event_type); +NvlStatus nvswitch_ctrl_get_port_events(nvswitch_device *device, NVSWITCH_GET_PORT_EVENTS_PARAMS *p); + #endif //_COMMON_NVSWITCH_H_ diff --git a/src/common/nvswitch/kernel/inc/haldef_nvswitch.h b/src/common/nvswitch/kernel/inc/haldef_nvswitch.h index 7610856724..756e7f238f 100644 --- a/src/common/nvswitch/kernel/inc/haldef_nvswitch.h +++ b/src/common/nvswitch/kernel/inc/haldef_nvswitch.h @@ -158,6 +158,7 @@ _op(NvlStatus, nvswitch_bbx_unload, (nvswitch_device *device), _arch) \ _op(NvlStatus, nvswitch_bbx_load, (nvswitch_device *device, NvU64 time_ns, NvU8 osType, NvU32 osVersion), _arch) \ _op(NvlStatus, nvswitch_bbx_get_sxid, (nvswitch_device *device, NVSWITCH_GET_SXIDS_PARAMS * params), _arch) \ + _op(NvlStatus, nvswitch_bbx_get_data, (nvswitch_device *device, NvU8 dataType, void * params), _arch) \ _op(NvlStatus, nvswitch_smbpbi_alloc, (nvswitch_device *device), _arch) \ _op(NvlStatus, nvswitch_smbpbi_post_init_hal, (nvswitch_device *device), _arch) \ _op(void, nvswitch_smbpbi_destroy_hal, (nvswitch_device *device), _arch) \ @@ -213,7 +214,6 @@ _op(void, nvswitch_reset_persistent_link_hw_state, (nvswitch_device *device, NvU32 linkNumber), _arch)\ _op(void, nvswitch_store_topology_information, (nvswitch_device *device, nvlink_link *link), _arch) \ _op(void, nvswitch_init_lpwr_regs, (nvlink_link *link), _arch) \ - _op(void, nvswitch_program_l1_scratch_reg, (nvswitch_device *device, NvU32 linkNumber), _arch) \ _op(NvlStatus, nvswitch_set_training_mode, (nvswitch_device *device), _arch) \ _op(NvU32, nvswitch_get_sublink_width, (nvswitch_device *device, NvU32 linkNumber), _arch) \ _op(NvBool, nvswitch_i2c_is_device_access_allowed, (nvswitch_device *device, NvU32 port, NvU8 addr, NvBool bIsRead), _arch) \ diff --git a/src/common/nvswitch/kernel/inc/inforom/inforom_nvswitch.h b/src/common/nvswitch/kernel/inc/inforom/inforom_nvswitch.h index 7ca5dd415a..eb4b2176e5 100644 --- a/src/common/nvswitch/kernel/inc/inforom/inforom_nvswitch.h +++ b/src/common/nvswitch/kernel/inc/inforom/inforom_nvswitch.h @@ -184,6 +184,7 @@ NvlStatus nvswitch_inforom_bbx_add_sxid(nvswitch_device *device, NvU32 data1, NvU32 data2); NvlStatus nvswitch_inforom_bbx_get_sxid(nvswitch_device *device, NVSWITCH_GET_SXIDS_PARAMS *params); +NvlStatus nvswitch_inforom_bbx_get_data(nvswitch_device *device, NvU8 dataType, void *params); // InfoROM DEM APIs NvlStatus nvswitch_inforom_dem_load(nvswitch_device *device); diff --git a/src/common/nvswitch/kernel/inc/lr10/inforom_lr10.h b/src/common/nvswitch/kernel/inc/lr10/inforom_lr10.h index bf12d836f5..7e1400d38c 100644 --- a/src/common/nvswitch/kernel/inc/lr10/inforom_lr10.h +++ b/src/common/nvswitch/kernel/inc/lr10/inforom_lr10.h @@ -169,4 +169,12 @@ nvswitch_bbx_get_sxid_lr10 NVSWITCH_GET_SXIDS_PARAMS * params ); +NvlStatus +nvswitch_bbx_get_data_lr10 +( + nvswitch_device *device, + NvU8 dataType, + void *params +); + #endif //_INFOROM_LR10_H_ diff --git a/src/common/nvswitch/kernel/inc/lr10/lr10.h b/src/common/nvswitch/kernel/inc/lr10/lr10.h index c08071f862..5b7d9b486b 100644 --- a/src/common/nvswitch/kernel/inc/lr10/lr10.h +++ b/src/common/nvswitch/kernel/inc/lr10/lr10.h @@ -652,7 +652,6 @@ void nvswitch_setup_link_loopback_mode_lr10(nvswitch_device *device, NvU32 void nvswitch_reset_persistent_link_hw_state_lr10(nvswitch_device *device, NvU32 linkNumber); void nvswitch_store_topology_information_lr10(nvswitch_device *device, nvlink_link *link); void nvswitch_init_lpwr_regs_lr10(nvlink_link *link); -void nvswitch_program_l1_scratch_reg_lr10(nvswitch_device *device, NvU32 linkNumber); NvlStatus nvswitch_set_training_mode_lr10(nvswitch_device *device); NvBool nvswitch_i2c_is_device_access_allowed_lr10(nvswitch_device *device, NvU32 port, NvU8 addr, NvBool bIsRead); NvU32 nvswitch_get_sublink_width_lr10(nvswitch_device *device,NvU32 linkNumber); diff --git a/src/common/nvswitch/kernel/inc/ls10/inforom_ls10.h b/src/common/nvswitch/kernel/inc/ls10/inforom_ls10.h index 7ce0e5c73f..dcd7328f4e 100644 --- a/src/common/nvswitch/kernel/inc/ls10/inforom_ls10.h +++ b/src/common/nvswitch/kernel/inc/ls10/inforom_ls10.h @@ -154,4 +154,11 @@ nvswitch_bbx_get_sxid_ls10 NVSWITCH_GET_SXIDS_PARAMS * params ); +NvlStatus +nvswitch_bbx_get_data_ls10 +( + nvswitch_device *device, + NvU8 dataType, + void *params +); #endif //_INFOROM_LS10_H_ diff --git a/src/common/nvswitch/kernel/inc/ls10/ls10.h b/src/common/nvswitch/kernel/inc/ls10/ls10.h index 6b8f64b952..0abd4bcd50 100644 --- a/src/common/nvswitch/kernel/inc/ls10/ls10.h +++ b/src/common/nvswitch/kernel/inc/ls10/ls10.h @@ -938,7 +938,6 @@ void nvswitch_corelib_clear_link_state_lr10(nvlink_link *link); NvlStatus nvswitch_corelib_set_dl_link_mode_ls10(nvlink_link *link, NvU64 mode, NvU32 flags); NvlStatus nvswitch_corelib_set_tx_mode_ls10(nvlink_link *link, NvU64 mode, NvU32 flags); void nvswitch_init_lpwr_regs_ls10(nvlink_link *link); -void nvswitch_program_l1_scratch_reg_ls10(nvswitch_device *device, NvU32 linkNumber); NvlStatus nvswitch_minion_service_falcon_interrupts_ls10(nvswitch_device *device, NvU32 instance); diff --git a/src/common/nvswitch/kernel/inc/regkey_nvswitch.h b/src/common/nvswitch/kernel/inc/regkey_nvswitch.h index d80ccd0f0f..7d7dc483f0 100644 --- a/src/common/nvswitch/kernel/inc/regkey_nvswitch.h +++ b/src/common/nvswitch/kernel/inc/regkey_nvswitch.h @@ -620,4 +620,21 @@ #define NV_SWITCH_REGKEY_REFERENCE_CLOCK_MODE_NON_COMMON_NO_SS 0x2 #define NV_SWITCH_REGKEY_REFERENCE_CLOCK_MODE_NON_COMMON_SS 0x3 +/* + * NV_SWITCH_REGKEY_DBG_LEVEL - Adjusts the amount of debug prints that will be generated + * + * Prints will be generated at the specified level and above. Eg. Debug level 0 will + * enable all prints + * + * Private: Debug use only + */ +#define NV_SWITCH_REGKEY_DBG_LEVEL "DebugLevel" +#define NV_SWITCH_REGKEY_DBG_LEVEL_DEFAULT NV_SWITCH_REGKEY_DBG_LEVEL_INFO +#define NV_SWITCH_REGKEY_DBG_LEVEL_MMIO 0x0 +#define NV_SWITCH_REGKEY_DBG_LEVEL_NOISY 0x1 +#define NV_SWITCH_REGKEY_DBG_LEVEL_INFO 0x2 +#define NV_SWITCH_REGKEY_DBG_LEVEL_SETUP 0x3 +#define NV_SWITCH_REGKEY_DBG_LEVEL_WARN 0x4 +#define NV_SWITCH_REGKEY_DBG_LEVEL_ERROR 0x5 + #endif //_REGKEY_NVSWITCH_H_ diff --git a/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h b/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h index c60b1525e9..c306f08bde 100644 --- a/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h +++ b/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h @@ -33,7 +33,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { - 0x00fec0d0, 0x0004fe00, 0x0017167e, 0x08f802f8, 0xa4b300f8, 0x8c890a00, 0x9abf000f, 0x1100a0b3, + 0x00fec0d0, 0x0004fe00, 0x0017167e, 0x08f802f8, 0xa4b300f8, 0x9c890a00, 0x9abf000f, 0x1100a0b3, 0x0d00b0b3, 0xa001aa98, 0xf8a43dba, 0x0a02f800, 0xbd00f8ff, 0xfc30f494, 0x40fe02f9, 0x04009001, 0x0db209a0, 0x0003237e, 0xa4b3afb2, 0x0dbf1601, 0x0a01d4b3, 0x002e8989, 0xa43d9d20, 0x00006b3e, 0xfc09040a, 0x0bf4f9a6, 0xfbff0a05, 0x337e0405, 0xa0330000, 0xa0330a04, 0x02f80600, 0xb37e00f8, @@ -72,57 +72,57 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x3e00000e, 0xb2000491, 0x01147e1a, 0x092e7e00, 0x0a747e00, 0x0e1f9800, 0x000f1998, 0xf4f9a6fc, 0x1ab22a18, 0x4cb25bb2, 0x0002f47e, 0xb3091998, 0xb2180090, 0x05f57e8a, 0xb3a0b200, 0x7e0c01a4, 0x3e00000e, 0x000004c9, 0x0a9b7e01, 0xa6fc0f00, 0x251bf40f, 0x90b339bf, 0x6ab22000, 0xee023bb2, - 0x0005397e, 0x3400a9b3, 0x04f63eff, 0x3eef0000, 0x400004f6, 0x0ab2fe0c, 0x890c85fb, 0xbf000f98, - 0x8900f89a, 0xbf000f8c, 0x8900f89a, 0xbf000f9c, 0x0096b099, 0xf00bacf0, 0x00f801a6, 0x000fa089, - 0xa9a099bf, 0x000f9889, 0xa9b599bf, 0x0f00f801, 0x0fa48901, 0xf89fa000, 0xb222f900, 0x7eb2b2a0, - 0x89000a74, 0xbf000fa0, 0xa609bf9f, 0x110bf4f9, 0x000f9889, 0x09989fbf, 0xf4f9a601, 0x988d3318, - 0x0e98000f, 0xbfd9bf01, 0x029ebb2f, 0x18f49fa6, 0xbdd9bf20, 0x92e9bc14, 0xa0909fbc, 0x0fa08929, - 0xa099bf00, 0xb5d9bf09, 0x903e0109, 0x01010005, 0x000a9b7e, 0x21fb1ab2, 0x000a747e, 0x000f9c8f, - 0x9990f9bf, 0x7ef9a001, 0xf8000a9b, 0x8002f900, 0xbf000fac, 0x0196b009, 0x7e070df4, 0x7e00000e, - 0x3e000a8f, 0x8e0005b3, 0x18001060, 0xefbf41a9, 0x9ac4abb2, 0xf4afa6ff, 0xeaa0050d, 0xb604a994, - 0xa9bc02a4, 0x0fac89a0, 0x10bb9000, 0x7ea0a9bc, 0xf8000bee, 0x9812f900, 0x909803a9, 0x24019003, - 0x517e1ab2, 0x9c89000c, 0x99bf000f, 0x150094b3, 0x7e100a90, 0xb2000c51, 0x05c77e0a, 0x062b3e00, - 0x8a1bb200, 0x7e001064, 0x89000bee, 0xbf000f8c, 0x410f1899, 0x9918a4bd, 0xf4f92641, 0x010a050d, - 0x22f911fb, 0x000f8c82, 0xb0b229bf, 0x000f9881, 0x7e249b90, 0xbf000c0f, 0xbc2abf19, 0xaa900009, - 0x0c517e10, 0xb529bf00, 0x19bf0490, 0x18f409a6, 0x1078890b, 0x067d3e00, 0x107c8900, 0xbf9abf00, - 0x10bb902b, 0x000c0f7e, 0x30f421fb, 0x0f9c89fc, 0xbf82f900, 0x0090b399, 0x89010f10, 0xa0000fa4, - 0x08453e9f, 0x0f8c8900, 0x0148fe00, 0x95bf91b2, 0x343d243d, 0x608064bd, 0x94870010, 0x9084000f, - 0x8890000f, 0x06d23e24, 0x3d09bf00, 0x01999224, 0x09bf09a0, 0x000fac8e, 0xb6049f94, 0x9fbc0294, + 0x0005397e, 0x3400a9b3, 0x04f63eff, 0x3eef0000, 0x400004f6, 0x0ab2fe0c, 0x890c85fb, 0xbf000fa8, + 0x8900f89a, 0xbf000f9c, 0x8900f89a, 0xbf000fac, 0x0096b099, 0xf00bacf0, 0x00f801a6, 0x000fb089, + 0xa9a099bf, 0x000fa889, 0xa9b599bf, 0x0f00f801, 0x0fb48901, 0xf89fa000, 0xb222f900, 0x7eb2b2a0, + 0x89000a74, 0xbf000fb0, 0xa609bf9f, 0x110bf4f9, 0x000fa889, 0x09989fbf, 0xf4f9a601, 0xa88d3318, + 0x0e98000f, 0xbfd9bf01, 0x029ebb2f, 0x18f49fa6, 0xbdd9bf20, 0x92e9bc14, 0xa0909fbc, 0x0fb08929, + 0xa099bf00, 0xb5d9bf09, 0x903e0109, 0x01010005, 0x000a9b7e, 0x21fb1ab2, 0x000a747e, 0x000fac8f, + 0x9990f9bf, 0x7ef9a001, 0xf8000a9b, 0x8002f900, 0xbf000fbc, 0x0196b009, 0x7e070df4, 0x7e00000e, + 0x3e000a8f, 0x8e0005b3, 0x18001070, 0xefbf41a9, 0x9ac4abb2, 0xf4afa6ff, 0xeaa0050d, 0xb604a994, + 0xa9bc02a4, 0x0fbc89a0, 0x10bb9000, 0x7ea0a9bc, 0xf8000bee, 0x9812f900, 0x909803a9, 0x24019003, + 0x517e1ab2, 0xac89000c, 0x99bf000f, 0x150094b3, 0x7e100a90, 0xb2000c51, 0x05c77e0a, 0x062b3e00, + 0x8a1bb200, 0x7e001074, 0x89000bee, 0xbf000f9c, 0x410f1899, 0x9918a4bd, 0xf4f92641, 0x010a050d, + 0x22f911fb, 0x000f9c82, 0xb0b229bf, 0x000fa881, 0x7e249b90, 0xbf000c0f, 0xbc2abf19, 0xaa900009, + 0x0c517e10, 0xb529bf00, 0x19bf0490, 0x18f409a6, 0x1088890b, 0x067d3e00, 0x108c8900, 0xbf9abf00, + 0x10bb902b, 0x000c0f7e, 0x30f421fb, 0x0fac89fc, 0xbf82f900, 0x0090b399, 0x89010f10, 0xa0000fb4, + 0x08453e9f, 0x0f9c8900, 0x0148fe00, 0x95bf91b2, 0x343d243d, 0x708064bd, 0xa4870010, 0xa084000f, + 0x8890000f, 0x06d23e24, 0x3d09bf00, 0x01999224, 0x09bf09a0, 0x000fbc8e, 0xb6049f94, 0x9fbc0294, 0x909ebc90, 0x99b399bf, 0xbf013d00, 0xb949bf7f, 0xf9a60099, 0xbf0f0bf4, 0x7eec0b1a, 0x3e000a95, - 0xbf000742, 0x0090b349, 0x0859983d, 0xfe940fbf, 0x02f4b604, 0x8ef0febc, 0xbc000fac, 0x9fa6f0fe, + 0xbf000742, 0x0090b349, 0x0859983d, 0xfe940fbf, 0x02f4b604, 0x8ef0febc, 0xbc000fbc, 0x9fa6f0fe, 0xbf221bf4, 0x92b4bd49, 0x49a00199, 0x99b949bf, 0xa079a000, 0x7e1abf15, 0xb0000a89, 0x1ff500a6, - 0x0fbf00f9, 0xfd9409bf, 0x049e9404, 0xbc0294b6, 0xac8e909e, 0x9ebc000f, 0x01999890, 0xbc02f4b6, + 0x0fbf00f9, 0xfd9409bf, 0x049e9404, 0xbc0294b6, 0xbc8e909e, 0x9ebc000f, 0x01999890, 0xbc02f4b6, 0xfebcf0fd, 0x019998f0, 0xbf01f9b5, 0x049f9409, 0xbc0294b6, 0x9ebc909f, 0x019e9890, 0x9f9409bf, - 0x0294b604, 0x8f909fbc, 0xbc000fb4, 0xe9a6909f, 0xbf2c1bf4, 0x9409bf0f, 0x9e9404fd, 0x0294b604, - 0x8e909ebc, 0xbc000fac, 0x9998909e, 0x02f4b601, 0xbcf0fdbc, 0x9998f0fe, 0x01f9b501, 0x9f9409bf, - 0x0294b604, 0x8f909fbc, 0xbc000fac, 0x9998909f, 0x03999801, 0x1abf19a0, 0x000a617e, 0x1000a4b3, + 0x0294b604, 0x8f909fbc, 0xbc000fc4, 0xe9a6909f, 0xbf2c1bf4, 0x9409bf0f, 0x9e9404fd, 0x0294b604, + 0x8e909ebc, 0xbc000fbc, 0x9998909e, 0x02f4b601, 0xbcf0fdbc, 0x9998f0fe, 0x01f9b501, 0x9f9409bf, + 0x0294b604, 0x8f909fbc, 0xbc000fbc, 0x9998909f, 0x03999801, 0x1abf19a0, 0x000a617e, 0x1000a4b3, 0xeb0b1abf, 0x000a957e, 0x0007fa3e, 0x8bb21abf, 0x000a897e, 0xf400a6b0, 0x2210401f, 0x01331001, - 0x06013433, 0x09bf06bf, 0x94ff2ec4, 0x94b6049f, 0x909fbc02, 0x000fac8f, 0xbf909fbc, 0xf5e9a699, - 0xbffeb31b, 0x009db309, 0x1abffea4, 0x7efe0b4b, 0x3e000a95, 0x330006d2, 0x890a0030, 0xa0001060, - 0x0ad07e96, 0x0485fb00, 0x9c8922f9, 0x99bf000f, 0xcd009db3, 0x10948900, 0x899fbf00, 0xbf000f98, - 0x0099b999, 0x0bf4f9a6, 0x0f8c890f, 0x0b9abf00, 0x0a957eec, 0x0f988e00, 0x8fe9bf00, 0x90001094, - 0xe9a00199, 0x99b9e9bf, 0xbff9a000, 0x0094b3e9, 0x107c8f1f, 0x10788e00, 0xbffcbf00, 0x0fa08de9, - 0xa0f9a000, 0x90d9bfec, 0xd9a00199, 0x00107c8f, 0x99bff9bf, 0x0a0094b3, 0x003e04bd, 0xf9bf0009, + 0x06013433, 0x09bf06bf, 0x94ff2ec4, 0x94b6049f, 0x909fbc02, 0x000fbc8f, 0xbf909fbc, 0xf5e9a699, + 0xbffeb31b, 0x009db309, 0x1abffea4, 0x7efe0b4b, 0x3e000a95, 0x330006d2, 0x890a0030, 0xa0001070, + 0x0ad07e96, 0x0485fb00, 0xac8922f9, 0x99bf000f, 0xcd009db3, 0x10a48900, 0x899fbf00, 0xbf000fa8, + 0x0099b999, 0x0bf4f9a6, 0x0f9c890f, 0x0b9abf00, 0x0a957eec, 0x0fa88e00, 0x8fe9bf00, 0x900010a4, + 0xe9a00199, 0x99b9e9bf, 0xbff9a000, 0x0094b3e9, 0x108c8f1f, 0x10888e00, 0xbffcbf00, 0x0fb08de9, + 0xa0f9a000, 0x90d9bfec, 0xd9a00199, 0x00108c8f, 0x99bff9bf, 0x0a0094b3, 0x003e04bd, 0xf9bf0009, 0x98039998, 0x003e0390, 0x2fbf0009, 0xa6040998, 0x3e08f4f9, 0x000c517e, 0x900d0998, 0x90b3240a, 0x517e0800, 0x0ab2000c, 0x0005c77e, 0x99bf19bf, 0x1f0090b3, 0x999819bf, 0x03909803, 0x0009083e, - 0x000f9882, 0x00107c81, 0xb3100a90, 0x89bf0004, 0xbf001098, 0x0094b399, 0x09283e17, 0x10988f00, - 0x90f9bf00, 0xf9a00199, 0x000a877e, 0x32f921fb, 0x000f9c81, 0xe90019bf, 0xc00099b3, 0x0a747e00, - 0x9219bf00, 0x19a00199, 0x9db319bf, 0x8900a800, 0xbf00109c, 0x0099b399, 0x648f009d, 0xf9bf0010, - 0x0a0094b3, 0x703e04bd, 0xf9980009, 0x03909803, 0x8c8314bd, 0x6482000f, 0xaa3e0010, 0x517e0009, + 0x000fa882, 0x00108c81, 0xb3100a90, 0x89bf0004, 0xbf0010a8, 0x0094b399, 0x09283e17, 0x10a88f00, + 0x90f9bf00, 0xf9a00199, 0x000a877e, 0x32f921fb, 0x000fac81, 0xe90019bf, 0xc00099b3, 0x0a747e00, + 0x9219bf00, 0x19a00199, 0x9db319bf, 0x8900a800, 0xbf0010ac, 0x0099b399, 0x748f009d, 0xf9bf0010, + 0x0a0094b3, 0x703e04bd, 0xf9980009, 0x03909803, 0x9c8314bd, 0x7482000f, 0xaa3e0010, 0x517e0009, 0x0a90000c, 0x0c517e10, 0x7e0ab200, 0xbf0005c7, 0x410f1839, 0x99182ebf, 0xf4f92641, 0x0101050d, - 0x1100e0b3, 0x98032998, 0x0a900390, 0x0004b324, 0x10988fd1, 0xb3f9bf00, 0xb21b0090, 0x08487ef0, - 0x9209bf00, 0x09a00199, 0x94b309bf, 0xe03ef300, 0x10b30009, 0xa4890e01, 0x99bf000f, 0x160194b3, - 0xa489f4bd, 0x0100000f, 0x0e7e9fa0, 0xf43e0000, 0x04bd0009, 0x000a9b7e, 0x31fb0ab2, 0x9c8932f9, - 0x99bf000f, 0xf70fa3b2, 0x550094b3, 0x4b00a0b3, 0x0005987e, 0x000f9881, 0x000f8c82, 0x2abf10bf, - 0x900030bc, 0x517e10aa, 0x29bf000c, 0xbf0490b5, 0xf409a619, 0x78890b18, 0x423e0010, 0x7c89000a, + 0x1100e0b3, 0x98032998, 0x0a900390, 0x0004b324, 0x10a88fd1, 0xb3f9bf00, 0xb21b0090, 0x08487ef0, + 0x9209bf00, 0x09a00199, 0x94b309bf, 0xe03ef300, 0x10b30009, 0xb4890e01, 0x99bf000f, 0x160194b3, + 0xb489f4bd, 0x0100000f, 0x0e7e9fa0, 0xf43e0000, 0x04bd0009, 0x000a9b7e, 0x31fb0ab2, 0xac8932f9, + 0x99bf000f, 0xf70fa3b2, 0x550094b3, 0x4b00a0b3, 0x0005987e, 0x000fa881, 0x000f9c82, 0x2abf10bf, + 0x900030bc, 0x517e10aa, 0x29bf000c, 0xbf0490b5, 0xf409a619, 0x88890b18, 0x423e0010, 0x8c89000a, 0x9abf0010, 0xbb902bbf, 0x0c0f7e10, 0x092e7e00, 0xb3010f00, 0x7e0a00a4, 0x0f00000e, 0xfbfab201, - 0x00a0b331, 0x03a99811, 0x99b9afbf, 0xf0f9a600, 0x00f80bac, 0xf41032f4, 0x5c8f1132, 0xf9bf0005, - 0xa0019990, 0xf800f8f9, 0x10107e00, 0x7e00f800, 0xf8001842, 0x184a7e00, 0x8f00f800, 0xbf00055c, + 0x00a0b331, 0x03a99811, 0x99b9afbf, 0xf0f9a600, 0x00f80bac, 0xf41032f4, 0x608f1132, 0xf9bf0005, + 0xa0019990, 0xf800f8f9, 0x10107e00, 0x7e00f800, 0xf8001842, 0x184a7e00, 0x8f00f800, 0xbf000560, 0x0094b3f9, 0x1032f41a, 0xbd1132f4, 0x7eee0ba4, 0xf4000a95, 0x31f41031, 0xbf00f811, 0x019992f9, 0xf9bff9a0, 0x0a0094b3, 0xf41031f4, 0x00f81131, 0x0038a77e, 0xc9fe00f8, 0x1495b601, 0x3c089033, 0xf4089630, 0x9033130c, 0x90332002, 0x90333403, 0x1c3e1800, 0x9033000b, 0x9033280f, 0x94331810, 0x0c3e1e0a, 0x8a7e000b, 0x00f80006, 0x0013bc7e, 0xb07e00f8, 0x00f80013, 0x00f802f8, 0x00f802f8, - 0x0038bc7e, 0x000ad67e, 0x0038a77e, 0x02f900f8, 0x0038bc7e, 0xcf020049, 0xc8800099, 0x0fbf0010, + 0x0038bc7e, 0x000ad67e, 0x0038a77e, 0x02f900f8, 0x0038bc7e, 0xcf020049, 0xd8800099, 0x0fbf0010, 0xf4049ffd, 0x487e170b, 0x8a7e0008, 0x0fbf0006, 0xfa010049, 0x623e009f, 0xa4bd000b, 0x957eda0b, 0xa77e000a, 0x01fb0038, 0x0038bc7e, 0x0018397e, 0x0800a0b3, 0x00068a7e, 0x0038a77e, 0x94bd00f8, 0x000b8d3e, 0x3cf8b93c, 0x999099af, 0xf49ca601, 0x00f8f508, 0xa23ea9b2, 0x9b20000b, 0x9001cc92, @@ -144,8 +144,8 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0xfd1094b6, 0x39fa059e, 0x024fbb06, 0xbc303fbc, 0x44b3505f, 0xaffe9d00, 0x00b7fe00, 0xf800cbfe, 0x7e170003, 0x3300186b, 0x3d0600a4, 0x0a9b7e04, 0x0ddd7e00, 0xfb0a3200, 0xf4010971, 0xe43dfc30, 0x7e009130, 0xf4000c82, 0x00f80430, 0x0efc30f4, 0x00e13001, 0x000c827e, 0xf80430f4, 0x0a747e00, - 0x10cc8f00, 0xb3f9bf00, 0xbf0f0090, 0x019992f9, 0x003ef9a0, 0xea7e000e, 0x030b0000, 0x00184a7e, - 0x000a9b7e, 0x747e00f8, 0xcc8e000a, 0xefbf0010, 0xf9a6ff09, 0xbf0e0bf4, 0x019990e9, 0x2c3ee9a0, + 0x10dc8f00, 0xb3f9bf00, 0xbf0f0090, 0x019992f9, 0x003ef9a0, 0xea7e000e, 0x030b0000, 0x00184a7e, + 0x000a9b7e, 0x747e00f8, 0xdc8e000a, 0xefbf0010, 0xf9a6ff09, 0xbf0e0bf4, 0x019990e9, 0x2c3ee9a0, 0xea7e000e, 0x030b0000, 0x00184a7e, 0x000a9b7e, 0x12f900f8, 0xafbfb9b2, 0xa0b29e3f, 0xb204d192, 0x18fe20cb, 0x1cb2019e, 0x1801fe35, 0xfe35029e, 0x03991802, 0xbf03f935, 0x04aa90aa, 0x7e7e0aa0, 0x09bf000b, 0xa09091bc, 0xf411fb09, 0x62f9f430, 0xb2b2a3b2, 0xd532c6b2, 0x0c00b4b3, 0x043d09f8, @@ -156,20 +156,20 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x040dc4bd, 0x3998e5f9, 0x9849a001, 0x1db20639, 0x2bb26cb2, 0x900140fe, 0x0ab22000, 0x41fe95f9, 0x0142fe01, 0x90271190, 0x1ab22622, 0x5e7e2bb2, 0x020a0038, 0x787eab32, 0x0abf0038, 0x00043998, 0x3f95f901, 0x7e2b3f1a, 0xbf003878, 0x009b7e3a, 0xfb0a3200, 0x5d330c65, 0x3dff5c00, 0x0f4b3e04, - 0x3dbcb200, 0x8aabb2d4, 0x7e0010d0, 0xf8000e6b, 0x0dbcb200, 0x8aabb201, 0x7e0010d0, 0xf8000e6b, + 0x3dbcb200, 0x8aabb2d4, 0x7e0010e0, 0xf8000e6b, 0x0dbcb200, 0x8aabb201, 0x7e0010e0, 0xf8000e6b, 0xb212f900, 0xb3b132a0, 0xf80a00a4, 0x100e3e09, 0x2e808900, 0x0b9abf00, 0x00de7eff, 0xff19c400, 0x0301008f, 0xbc099e94, 0xefcfe0ef, 0x8099b800, 0x94b60001, 0x009dcf09, 0xf0020918, 0x09352095, 0xf40fa602, 0xf63e411b, 0xf918000f, 0x2094f002, 0x3f340bf4, 0x009433f9, 0xf8cbbc0b, 0x000fef3e, 0xf001f918, 0x9990ff94, 0x049afd03, 0xf6f0f9bc, 0xff3e00ef, 0x1bc4000f, 0x8cfc0aff, 0xa6002e68, - 0xc91bf4fd, 0x002e8089, 0x9b7e9abf, 0x11fb0000, 0xfc8b02f9, 0x127e0010, 0xa0320000, 0x0f00a033, - 0x0000ea7e, 0x7eff0bc4, 0x8900184a, 0xbf0010fc, 0x11008990, 0x899fbf00, 0x180010ec, 0x9e35180e, + 0xc91bf4fd, 0x002e8089, 0x9b7e9abf, 0x11fb0000, 0x0c8b02f9, 0x127e0011, 0xa0320000, 0x0f00a033, + 0x0000ea7e, 0x7eff0bc4, 0x8900184a, 0xbf00110c, 0x11108990, 0x899fbf00, 0x180010fc, 0x9e35180e, 0xf40fa60e, 0x0918101b, 0x00943319, 0x3ea4bd0a, 0x1800107a, 0xb4331d0b, 0xa4bd0a00, 0x00106f3e, - 0x3d200a90, 0x13607ec4, 0x00a6b000, 0x3d0e1ef4, 0x19093594, 0x00110089, 0x01fb90a0, 0x89ffa4f0, + 0x3d200a90, 0x13607ec4, 0x00a6b000, 0x3d0e1ef4, 0x19093594, 0x00111089, 0x01fb90a0, 0x89ffa4f0, 0x8c003131, 0xbc003124, 0xacbcd0a9, 0x3fdf3fa0, 0x31318cae, 0xffe9c400, 0x20909cbc, 0x3124899f, 0xfff4f000, 0x20f0f9bc, 0x20943dfe, 0xf900f8d9, 0x31318922, 0xffa0c400, 0x3f2009bc, 0x33a1322e, - 0x7e0c00e0, 0x3e00107c, 0x8f0010e0, 0x3f001104, 0xf4a926f9, 0x947d0d1b, 0xf975fe20, 0x01f97502, + 0x7e0c00e0, 0x3e00107c, 0x8f0010e0, 0x3f001114, 0xf4a926f9, 0x947d0d1b, 0xf975fe20, 0x01f97502, 0x00313189, 0x91209f3f, 0x00312489, 0x3d0009bc, 0x20092094, 0x3124892f, 0xfff4f000, 0x20f0f9bc, - 0xf921fbf1, 0x11048f52, 0x32943d00, 0xb2c332b4, 0x35f5b2a2, 0x143d01f9, 0x00113a3e, 0x1110203f, + 0xf921fbf1, 0x11148f52, 0x32943d00, 0xb2c332b4, 0x35f5b2a2, 0x143d01f9, 0x00113a3e, 0x1110203f, 0x01229001, 0x16000033, 0x3b320a32, 0x0010af7e, 0x33015918, 0x35070094, 0x14260150, 0xfbe008f4, 0xfc30f451, 0xb13212f9, 0x900140fe, 0x0bb20800, 0x0000127e, 0x0e1800bf, 0x0014331d, 0x4f02f806, 0xf3f1000b, 0x19c40000, 0xf49fa6ff, 0xed320b0c, 0x9f3ef43d, 0x02f80011, 0xed32f43d, 0x00119f3e, @@ -179,7 +179,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x0a747eb1, 0xfe0ab200, 0x00900140, 0x7e0bb208, 0xbf000012, 0x18f43d00, 0x163e1d0d, 0xe9180012, 0x01ff1020, 0x2620ee90, 0x0d1bf491, 0x0100943d, 0x233ee920, 0xf9c40012, 0xe009bcff, 0x08f4fd26, 0x7e043de0, 0x32000a9b, 0x0415fb0a, 0x0011d87e, 0x0600a433, 0x00f802f8, 0xa4f082f9, 0x31008fff, - 0x31188e00, 0x58fa7c00, 0xb298ea3c, 0xbdc632b7, 0xff94f034, 0x00056088, 0x8120597c, 0x3e001104, + 0x31188e00, 0x58fa7c00, 0xb298ea3c, 0xbdc632b7, 0xff94f034, 0x00056488, 0x8120597c, 0x3e001114, 0x52001354, 0x29e40122, 0x9494ffff, 0x034ffe08, 0xb31ff995, 0xd0100190, 0x03000000, 0xf594f0ff, 0xbf00d51b, 0x01008e89, 0x089f9500, 0xfffff9e4, 0x18f59ea6, 0x99900010, 0x0894b601, 0x473e89a0, 0x1f580013, 0x02195801, 0x1bf4f966, 0x000b4945, 0x000093f1, 0x0031248f, 0x18909fbc, 0x19180190, @@ -208,36 +208,36 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x0c004d81, 0xcf0b004c, 0xcecf00df, 0x00d9cf00, 0x1bf4f9a6, 0xb5aea0f5, 0x00f801af, 0xcf0b0049, 0xaabf0099, 0xf8a29abc, 0xb242f900, 0xb2b3b2a0, 0x00c0b3c1, 0x0b004929, 0xb20092cf, 0x0000b394, 0xf93ab212, 0x00a03305, 0x3e010a0a, 0xcf0015e8, 0x92bb0049, 0xf491a602, 0x04b3e608, 0xa43d0a00, - 0x0015e83e, 0x05f93ab2, 0x000041fb, 0xd24e0041, 0x0000055c, 0x90fc00f8, 0x0015ea7e, 0xf90188fe, - 0x00289880, 0x8cd880f9, 0x9800000f, 0x47fe0088, 0xbd87a001, 0x0387b570, 0xfe0010f7, 0xb7b600a4, + 0x0015e83e, 0x05f93ab2, 0x000041fb, 0xd24e0041, 0x00000560, 0x90fc00f8, 0x0015ea7e, 0xf90188fe, + 0x00289880, 0x9cd880f9, 0x9800000f, 0x47fe0088, 0xbd87a001, 0x0387b570, 0xfe0010f7, 0xb7b600a4, 0x1fb9f002, 0xf9001bf7, 0x7e00f890, 0x3e0015ea, 0xf9001647, 0x3550daf2, 0x50db0000, 0x7e000033, - 0x7e0015f6, 0xf7000b68, 0x8cd80010, 0x9800000f, 0x87980088, 0x0074fe00, 0xb6028798, 0x79f00277, + 0x7e0015f6, 0xf7000b68, 0x9cd80010, 0x9800000f, 0x87980088, 0x0074fe00, 0xb6028798, 0x79f00277, 0x0017f71f, 0x28a080fc, 0x88fe80fc, 0xf8f0fb00, 0xdaf2f901, 0x00003550, 0x003350db, 0x15f67e00, 0x0b2e7e00, 0x16473e00, 0x1832f400, 0x50daf2f9, 0xdb000033, 0x00003150, 0x0015f67e, 0x000b207e, 0x0016473e, 0xf91832f4, 0x0188fef2, 0xa27e80f9, 0x80fc0037, 0xfb0088fe, 0xb201f8f0, 0xb0afb2a9, 0x1ef400a6, 0xb0bab22b, 0x1ef400b6, 0xacfaff13, 0xf496b9ff, 0x00f8051e, 0xf801aab9, 0x01bab900, 0xffacfaff, 0x1ff496b9, 0x16d83ef0, 0x01afb900, 0xb6b0bab2, 0xd81ff400, 0x0016dd3e, 0x95e0abff, - 0xbf9510a9, 0x01b9fd10, 0xbb01affd, 0xa4b600ab, 0x00aebb10, 0x62f900f8, 0x0005dcdf, 0xd9ffbf00, - 0x000005e0, 0xf4bd9fa0, 0x01010089, 0x4f009ff6, 0x99b87fff, 0xf6003f00, 0x00df009f, 0xb803ff00, + 0xbf9510a9, 0x01b9fd10, 0xbb01affd, 0xa4b600ab, 0x00aebb10, 0x62f900f8, 0x0005ecdf, 0xd9ffbf00, + 0x000005f0, 0xf4bd9fa0, 0x01010089, 0x4f009ff6, 0x99b87fff, 0xf6003f00, 0x00df009f, 0xb803ff00, 0x00010099, 0x8f009ff6, 0xb800ff80, 0x000a0099, 0x4f009ff6, 0x99b81000, 0xf6024a00, 0x00d6009f, - 0x85400000, 0xd0011c00, 0x000005f0, 0x01020084, 0x10000083, 0xefaaa0d2, 0x0afd01be, 0x1a277e08, - 0x04a6fd00, 0x00280bf5, 0xfd0049cf, 0x0bf50493, 0xf0de001e, 0xbd000005, 0x95f2fff4, 0xff90e9a0, + 0x85400000, 0xd0011c00, 0x00000600, 0x01020084, 0x10000083, 0xefaaa0d2, 0x0afd01be, 0x1a277e08, + 0x04a6fd00, 0x00280bf5, 0xfd0049cf, 0x0bf50493, 0x00de001e, 0xbd000006, 0x95f2fff4, 0xff90e9a0, 0x04ee9001, 0xf504f4b3, 0x0017e33e, 0xf00059cf, 0x1bf40194, 0x1f3cf4fa, 0x93f009b2, 0x0699fa05, 0x3cf503f8, 0x3cf59004, 0x3cf59003, 0x3cf5ac54, 0x3cf5c404, 0x09b2d033, 0xfa0393f0, 0x03f80599, 0xbf003cf4, 0x01e9920e, 0x0df491a6, 0x010e9825, 0xa601e992, 0x1a0df491, 0x92020e98, 0x91a601e9, - 0x980f0df4, 0xe992030e, 0xf591a601, 0xbdff700c, 0x05f0df94, 0xdcd00000, 0xb5000005, 0xf9a003f9, - 0xb501f9b5, 0x0ea002f9, 0x004a6c7e, 0x0005e0d9, 0xbd99bf00, 0xfb09a0a4, 0x18957e61, 0xffa4f000, + 0x980f0df4, 0xe992030e, 0xf591a601, 0xbdff700c, 0x0600df94, 0xecd00000, 0xb5000005, 0xf9a003f9, + 0xb501f9b5, 0x0ea002f9, 0x004a6c7e, 0x0005f0d9, 0xbd99bf00, 0xfb09a0a4, 0x18957e61, 0xffa4f000, 0x31f400f8, 0x0028f400, 0x02f800f8, 0x477e00f8, 0x00f80019, 0x001434d9, 0x0d9b1800, 0x7e0c9a18, 0xf8001a12, 0x1a127e00, 0x7e00f800, 0xf80019cd, 0x14008900, 0x0099cf02, 0xf40194f0, 0xf17e160b, - 0x008f003c, 0xf9ce0213, 0x0195f000, 0xf800f9f7, 0xf802f800, 0xf830f400, 0x0005dcdf, 0xbf02f900, + 0x008f003c, 0xf9ce0213, 0x0195f000, 0xf800f9f7, 0xf802f800, 0xf830f400, 0x0005ecdf, 0xbf02f900, 0x0149feff, 0xa0089990, 0xd9f43d9f, 0x00002e89, 0x004f9f20, 0x00ffcf06, 0xcf07004e, 0x004900ee, 0x0099cf02, 0x95049ffd, 0xeeb910ef, 0x049efd00, 0xff00ffb9, 0x09c4049f, 0x070bf401, 0x003b797e, 0x100009e4, 0x0f2f0bf4, 0x0149fe01, 0x0289008e, 0x20079990, 0x00e9ce9f, 0x9ffdfe0f, 0x00e9f704, 0x001408d9, 0xfe9abf00, 0x010c014b, 0x7e07bb90, 0xe400006e, 0x73800009, 0x7e080090, 0x49001871, - 0x90f70100, 0x0149fe00, 0xbf089990, 0x05dcd99e, 0x9fbf0000, 0x002e89d9, 0xa69a3f00, 0x070bf4ef, + 0x90f70100, 0x0149fe00, 0xbf089990, 0x05ecd99e, 0x9fbf0000, 0x002e89d9, 0xa69a3f00, 0x070bf4ef, 0x003a317e, 0x0a0805fb, 0xf900f801, 0x03a99802, 0x94f0a0b2, 0x0d0bf401, 0x277eaabf, 0x673e001a, 0xa9bf0019, 0x98009acf, 0x0998030f, 0x020e9801, 0xff02f4f0, 0x9ea694a9, 0x320b9cf0, 0x00f0b39a, - 0x0096300c, 0x320b9cf0, 0xf401fb9a, 0x12f9ec30, 0x900149fe, 0xdcd10899, 0xa0000005, 0x019bb59a, + 0x0096300c, 0x320b9cf0, 0xf401fb9a, 0x12f9ec30, 0x900149fe, 0xecd10899, 0xa0000005, 0x019bb59a, 0xb5029cb5, 0x9bb2039e, 0xdcb219bf, 0xda0140fe, 0x0000194b, 0xa0180090, 0x15a97e09, 0xbf0fbf00, 0xf4f9a619, 0x317e070b, 0x15fb003a, 0xb8008e14, 0x00efcf00, 0xf404f9c4, 0xa43d071b, 0xf9c500f8, 0x00e9f604, 0x00f8010a, 0x00900089, 0xf00099ce, 0x0bf40194, 0xf1008f1e, 0x00f9ce00, 0xf71095f0, @@ -272,7 +272,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0xa6b0001d, 0x240cf409, 0x001da03e, 0x0049190f, 0x009ff711, 0x00f802f8, 0xb50294b6, 0x00f804b9, 0xb602af92, 0xb9bc0294, 0xf400f8f9, 0x82f9d430, 0x301590b4, 0xc1b027e1, 0x0ad1b00b, 0x94b6f4bd, 0x0c91b002, 0x900149fe, 0x9fa04499, 0x20079990, 0x0b99929f, 0x95b29fa0, 0xa0049992, 0x9297b29f, - 0x9fa00499, 0x0005dcdf, 0x90ffbf00, 0x4efe1499, 0xa0a6b201, 0x34ee909f, 0xb4b20209, 0x84bde9a0, + 0x9fa00499, 0x0005ecdf, 0x90ffbf00, 0x4efe1499, 0xa0a6b201, 0x34ee909f, 0xb4b20209, 0x84bde9a0, 0x14bd34bd, 0x001eef3e, 0x277e6ab2, 0x49bf001a, 0x4bfea2b2, 0x014cfe01, 0x9044bb90, 0x95f94bcc, 0xb31100b4, 0x008e0209, 0x9e0309b3, 0x010db300, 0x499800a8, 0xb27cb201, 0xfe5bb22a, 0xdd90014d, 0x3295f938, 0x0be0b40c, 0xa53ed4bd, 0x5fbf001e, 0xf9a6e9bf, 0x34381bf4, 0xe89827b0, 0x987fbf01, @@ -281,7 +281,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0xee9001dd, 0x0ab0b40c, 0x08f4dba6, 0x1ed53ea4, 0x02499800, 0x4dfe5cbf, 0xb22ab201, 0x34dd901b, 0xd53e95f9, 0x10b3001e, 0x49980f00, 0xb25cbf03, 0xf91bb22a, 0x4b903495, 0x11009433, 0x14bdff09, 0xa00e91b0, 0xa094bd79, 0x01339059, 0xb4046690, 0x39a60d90, 0xff1408f5, 0x900149fe, 0x9fbf4c99, - 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xf92c85fb, 0x2924d062, 0x093f0000, 0xb2fc30f4, + 0x0005ecd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xf92c85fb, 0x2924d062, 0x093f0000, 0xb2fc30f4, 0xb2b4b2a5, 0x33d3b2c2, 0x0111009d, 0xe44cb4bd, 0x1444da14, 0x947e0000, 0x94bd000b, 0x91b006b2, 0xc0008a00, 0x01fcdb02, 0x0cdc0000, 0x0d000002, 0xd0e43d1a, 0x00001444, 0x001dab7e, 0x09bf14bd, 0x1f1394b3, 0x98020998, 0xccdb040a, 0xdc000001, 0x00000344, 0x0d0091b0, 0x7e010e08, 0xbf001dab, @@ -295,10 +295,10 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x01943308, 0x0120b321, 0x0126b014, 0x0a0d08f4, 0x0224b3ff, 0x20803e11, 0x03fa9800, 0x0020823e, 0xff90dabf, 0x20dd9020, 0x1bf4fea6, 0xa6ff09c5, 0x0d1bf4a9, 0x0049190f, 0x009ff711, 0x30f402f8, 0xbd61fb04, 0xb5caa094, 0xc9b501cb, 0x140cd902, 0x9fbf0000, 0xfef830f4, 0x9bb50149, 0xb69aa001, - 0xfab811b5, 0x7e0002d8, 0xf4001a87, 0x00f80830, 0xf9e830f4, 0x05dcd252, 0x29bf0000, 0x900140fe, + 0xfab811b5, 0x7e0002d8, 0xf4001a87, 0x00f80830, 0xf9e830f4, 0x05ecd252, 0x29bf0000, 0x900140fe, 0x0ba01800, 0xb2010cb5, 0xb2d4b2e5, 0x0141fea3, 0xa02c1190, 0x0e067e19, 0x0a747e00, 0x010b9800, 0x40fe0abf, 0x20009001, 0xa37e0cb2, 0x0bb20020, 0x5db24cb2, 0xcc7e3ab2, 0xa032000d, 0x000a9b7e, - 0x000ddd7e, 0x29bf1fbf, 0xf9a60a32, 0x7e070bf4, 0xfb003a31, 0x30f41855, 0xd252f9e8, 0x000005dc, + 0x000ddd7e, 0x29bf1fbf, 0xf9a60a32, 0x7e070bf4, 0xfb003a31, 0x30f41855, 0xd252f9e8, 0x000005ec, 0x40fe29bf, 0x18009001, 0x0cb50ba0, 0xb2e5b201, 0xfea3b2d4, 0x11900141, 0x7e19a02c, 0x7e000e06, 0x98000a74, 0x0abf010b, 0x900140fe, 0x0cb22000, 0x0020a37e, 0x4cb20bb2, 0x3ab25db2, 0x000db97e, 0x9b7ea032, 0xdd7e000a, 0x1fbf000d, 0x0a3229bf, 0x0bf4f9a6, 0x3a317e07, 0x1855fb00, 0x3d7e040a, @@ -349,7 +349,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0xf9cf01c0, 0x4c99c700, 0x220090b3, 0xf60190b3, 0x223e02f8, 0xf9cf0027, 0x4c99c700, 0x390090b3, 0xf60190b3, 0x363e02f8, 0xa48f0027, 0x008901ad, 0x9ff601c1, 0xb8f4bd00, 0x00010099, 0xdf009ff6, 0x800000f2, 0x020099b8, 0x009ff602, 0xb2009fcf, 0x27363e9f, 0xe400f800, 0xc7ff00bf, 0xaeb2f0b9, - 0xdfd59fff, 0x00000564, 0x0027ab3e, 0x1bf49b26, 0x01f9581a, 0x1bf49d66, 0x3df97f12, 0x08e975a4, + 0xdfd59fff, 0x00000568, 0x0027ab3e, 0x1bf49b26, 0x01f9581a, 0x1bf49d66, 0x3df97f12, 0x08e975a4, 0x7501ff58, 0x00f809ef, 0x3f04ff90, 0x009433f9, 0xf8010adf, 0x0aa9b200, 0x00b0b302, 0x3db92008, 0xf900f8a4, 0xb3a0b202, 0x986500a0, 0x90b305a9, 0x0cd95e00, 0xbf000014, 0xe8aab89a, 0x277e0004, 0xa9e7001a, 0x9ab30168, 0xb34c0fff, 0xb6470090, 0xaab314a5, 0xb3400fff, 0x983b00a0, 0x94b6050e, @@ -359,7 +359,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x22f900f8, 0xb132a0b2, 0x350ac2b2, 0x690000b3, 0x94b309bf, 0x09986100, 0x0094b301, 0xe2048a5a, 0x1a277e00, 0xff1ec400, 0xa601a9c4, 0x091bf49e, 0xc73e943d, 0x0f180028, 0xf0f30908, 0xabc501e4, 0x01f4f002, 0xb604b9fd, 0xfe0902f4, 0x8a05bffd, 0xfd00e204, 0xbefd04b9, 0x1a877e05, 0xe2048a00, - 0x1a277e00, 0xb3010900, 0x20060020, 0x3ea43d29, 0x0a0028d5, 0xf421fb01, 0xdcdff830, 0xf9000005, + 0x1a277e00, 0xb3010900, 0x20060020, 0x3ea43d29, 0x0a0028d5, 0xf421fb01, 0xecdff830, 0xf9000005, 0xfeffbf52, 0x99900149, 0xa0a3b21c, 0x72b0b29f, 0x0ad4b2c2, 0x0039b335, 0xc97300c7, 0xb300ba00, 0x00b500d9, 0x9db339bf, 0x9800b400, 0x9db30139, 0x8a00ac00, 0x7e00e208, 0xc4001a27, 0x0bf401a9, 0xa2a9e70d, 0x0294b602, 0xfe0209bb, 0x3ab2014c, 0xcc90b43d, 0x28627e1b, 0x00ad3300, 0x00890083, @@ -367,16 +367,16 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x1df4f9a6, 0xff2fe407, 0xbdfe32ff, 0x29833ef4, 0x90913c00, 0xb60394f0, 0xa9bc0394, 0xf9493c95, 0x3201ff90, 0xf4fe26f9, 0xe9c4ea08, 0x040090ff, 0x7302297b, 0xbc0d0020, 0x143d4049, 0x0029503e, 0x900149fe, 0x9b3f1b99, 0xc4bd3ab2, 0x0028627e, 0x0029bc3e, 0xbc3e020a, 0x010a0029, 0x900149fe, - 0x9fbf1c99, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xf90855fb, 0xb2350902, 0x00a0b3a0, - 0xbdb43d1a, 0x28627ec4, 0x33a93200, 0xb20c00a4, 0x28367e0a, 0x32a93200, 0xf401fb9a, 0xdcd9f430, + 0x9fbf1c99, 0x0005ecd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xf90855fb, 0xb2350902, 0x00a0b3a0, + 0xbdb43d1a, 0x28627ec4, 0x33a93200, 0xb20c00a4, 0x28367e0a, 0x32a93200, 0xf401fb9a, 0xecd9f430, 0xf9000005, 0xfe99bf12, 0xff90014f, 0x03e84b10, 0xfc7ef9a0, 0xa0b20016, 0x90014afe, 0xa1b208aa, 0x0015817e, 0x00e5a08a, 0x001a277e, 0xf400a6b0, 0x1ab21c1f, 0x00159c7e, 0x0df4a0a6, 0x3e040a09, - 0x7e002a4d, 0x3e00000e, 0x3d002a24, 0x0149fea4, 0xbf109990, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, + 0x7e002a4d, 0x3e00000e, 0x3d002a24, 0x0149fea4, 0xbf109990, 0x05ecd99f, 0x99bf0000, 0x0bf4f9a6, 0x3a317e07, 0x0c15fb00, 0xad5802f9, 0x58af3f01, 0xb0b202a9, 0xffffdce4, 0xf003f4f0, 0xf4b60093, 0x909cbc12, 0x000000de, 0x01999280, 0xf005fefd, 0xf9ffff94, 0x00d073b5, 0x01cf9218, 0x01000089, 0xff08f4b6, 0xf4f195b9, 0x9fffffff, 0x01aa18b5, 0xf401a9c4, 0x00890a0b, 0xb9fd0200, 0xffa4f005, 0xf410a9c4, 0x00d90b0b, 0xfd080000, 0xa9c405b9, 0x0b0bf404, 0x000000d9, 0x05b9fd20, 0x00e5a08a, - 0x001a877e, 0xfb7e0ab2, 0x01fb0029, 0xdff830f4, 0x000005dc, 0xffbf42f9, 0x900149fe, 0xa3b21899, + 0x001a877e, 0xfb7e0ab2, 0x01fb0029, 0xdff830f4, 0x000005ec, 0xffbf42f9, 0x900149fe, 0xa3b21899, 0xb1729fa0, 0x2000c073, 0x09ffdfc4, 0x029fbb40, 0xffffcfe4, 0xbb0294b6, 0xbfe4029f, 0xf9a6ffff, 0x00b60cf5, 0x09ffdac4, 0xff12e440, 0x029abbff, 0xa60294b6, 0xa10cf529, 0x00c07300, 0xa2c9e756, 0x03c0c401, 0xb8409abc, 0x0039284a, 0x7e02a4b6, 0xf0001a27, 0x0994ff04, 0x05a9bb03, 0x900149fe, @@ -384,18 +384,18 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0xbb903039, 0x00c3f014, 0x000b7e7e, 0xb8014a90, 0x003928a9, 0x940144fe, 0x44900292, 0x2bcc3e14, 0x70107200, 0x0df40416, 0xb2040005, 0x1a277e2a, 0xff09e400, 0x7b4aa0ff, 0x3ab20210, 0xbc042290, 0x4bb23039, 0xffff0ce4, 0x000b7e7e, 0xd5001473, 0xd83ea43d, 0x020a002b, 0x900149fe, 0x9fbf1899, - 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xf40845fb, 0xdcdff830, 0xf9000005, 0xfeffbf52, + 0x0005ecd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xf40845fb, 0xecdff830, 0xf9000005, 0xfeffbf52, 0x99900149, 0xa0a3b21c, 0x0ab1729f, 0x00b67102, 0x450cf401, 0x820144fe, 0x9000e4a0, 0x54bd1844, 0x002c503e, 0x107245a0, 0xf4041670, 0x0400050d, 0x0ce43bb2, 0x4ab2ffff, 0x000b7e7e, 0x2ab24bbf, - 0x9002107b, 0x03f00422, 0x1a877e00, 0x3030bc00, 0xd4001473, 0x49fea43d, 0x1c999001, 0xdcd99fbf, + 0x9002107b, 0x03f00422, 0x1a877e00, 0x3030bc00, 0xd4001473, 0x49fea43d, 0x1c999001, 0xecd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x55fb003a, 0xb252f908, 0x58c5b2b1, 0xb25802b4, 0x00a0b301, 0xff43e454, 0xff20e4ff, 0x0034b3ff, 0x0004b30c, 0x2cd13e0c, 0x0000b300, 0x72dab210, 0x2bf37e2b, 0x00a43300, 0x8b1ab232, 0x7e07a120, 0x33002a68, 0xb32400a4, 0xb0200030, 0xdcf00006, 0x01d6f00b, - 0x4b725ab2, 0xd4362c72, 0x2aec7e05, 0x2cd33e00, 0xfb350a00, 0xf830f451, 0x0005dcdf, 0xbf12f900, + 0x4b725ab2, 0xd4362c72, 0x2aec7e05, 0x2cd33e00, 0xfb350a00, 0xf830f451, 0x0005ecdf, 0xbf12f900, 0x0149feff, 0xfe0c9990, 0x9fa00140, 0xb2080090, 0x7e0cb2b1, 0xbf004526, 0x02f9580f, 0xf003ff98, 0x94b60093, 0x2d163e0c, 0xf491a600, 0xff98150b, 0x0099b806, 0xf4b30010, 0x350af300, 0x002d353e, - 0x9802fe98, 0xffbf05f9, 0xa6909fbc, 0x089cf09e, 0x320196f0, 0x0149fe9a, 0xbf0c9990, 0x05dcd99f, - 0x99bf0000, 0x0bf4f9a6, 0x3a317e07, 0x0815fb00, 0xdfe030f4, 0x000005dc, 0xffbf82f9, 0xfe09b1b0, + 0x9802fe98, 0xffbf05f9, 0xa6909fbc, 0x089cf09e, 0x320196f0, 0x0149fe9a, 0xbf0c9990, 0x05ecd99f, + 0x99bf0000, 0x0bf4f9a6, 0x3a317e07, 0x0815fb00, 0xdfe030f4, 0x000005ec, 0xffbf82f9, 0xfe09b1b0, 0x99900149, 0x0140fe40, 0x00909fa0, 0xb2a4b23c, 0x45267e0c, 0x5803bf00, 0x31980239, 0x0093f003, 0x3e0c94b6, 0xb4002d97, 0x9ea609e0, 0x98130bf4, 0x99b80611, 0xb3001000, 0x3ef00014, 0x98002f69, 0x1f980519, 0x041e9803, 0xbc0395b6, 0x2ea6209f, 0xfe4f0cf4, 0x4ab20143, 0xb2383390, 0xb2010c2b, @@ -412,12 +412,12 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x00de943e, 0xfdff0000, 0x9ffd04fe, 0x9879a005, 0x4ab2012c, 0x040d7bb2, 0x00406b7e, 0x7500a433, 0x1b9823a0, 0x0c4ab203, 0x928db204, 0xd77e04bb, 0xa4330028, 0x2c985f00, 0xb24ab203, 0x92040d8b, 0x6b7e04cc, 0xa4330040, 0x1f984b00, 0xb594bd02, 0x66b80529, 0xb5001000, 0x2298022f, 0x06119806, - 0x6f001db3, 0x2f6b3eff, 0xfe350000, 0x99900149, 0xd99fbf40, 0x000005dc, 0x0a3299bf, 0x0bf4f9a6, + 0x6f001db3, 0x2f6b3eff, 0xfe350000, 0x99900149, 0xd99fbf40, 0x000005ec, 0x0a3299bf, 0x0bf4f9a6, 0x2f973e1d, 0x0141fe00, 0x1190fea0, 0x2e3e3e3c, 0x3ea03200, 0x7e002f6b, 0xfb003a31, 0x02f92085, 0xa0b3a0b2, 0xa9985100, 0x0090b306, 0x140cd94a, 0x9abf0000, 0x04e0aab8, 0x1a277e00, 0xffa9e400, 0xff9ab30f, 0x90b3380f, 0xaae73300, 0xaab3016c, 0xb32b0fff, 0x982600a0, 0x94b6060e, 0x0caf940c, 0xe9a0a43d, 0xbf060e98, 0xf0f9bce9, 0x3e01efb5, 0x0a002ffb, 0x2ffb3e35, 0xfb2e0a00, 0xd830f401, - 0x0005dcdf, 0xbf82f900, 0x0149feff, 0xb2489990, 0xb39fa0a6, 0x982100a0, 0xfd0906a0, 0xbf920bbf, + 0x0005ecdf, 0xbf82f900, 0x0149feff, 0xb2489990, 0xb39fa0a6, 0x982100a0, 0xfd0906a0, 0xbf920bbf, 0xf4f9a601, 0x0f98110c, 0xa6ff0901, 0x070bf4f9, 0x1100f4b3, 0x020502f8, 0x7d006db3, 0x32c23e02, 0x10bb9200, 0x7cdd100c, 0x7e000029, 0x320028d7, 0x00ad33a5, 0x7cda0264, 0xdb000029, 0x00000068, 0xa87e080c, 0xadb3000b, 0x98027e00, 0x0fbf0109, 0x18f5f9a6, 0xfee40278, 0x1bf50fff, 0x6f980270, @@ -439,31 +439,31 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x0b0094b3, 0x3e0331b5, 0xb4003271, 0xf1b50df0, 0x01771006, 0xde0d11b0, 0x0000297c, 0x260de918, 0xca08f579, 0x04e998fe, 0x0b0094b3, 0x3e04e3b5, 0xb4003299, 0xf3b50bf0, 0x01881004, 0xde0b31b0, 0x0000297c, 0x260ce918, 0xf008f589, 0x32c23efd, 0x00503300, 0x06699811, 0x9fa0ff0f, 0xb5066998, - 0x49fe019f, 0x48999001, 0xdcd99fbf, 0xbf000005, 0xa65a3299, 0x1f0bf4f9, 0x0032f03e, 0x0532a032, - 0x0032b13e, 0xb53e3505, 0x02050032, 0x0032b53e, 0x003a317e, 0xf42885fb, 0xdcdff430, 0xf9000005, + 0x49fe019f, 0x48999001, 0xecd99fbf, 0xbf000005, 0xa65a3299, 0x1f0bf4f9, 0x0032f03e, 0x0532a032, + 0x0032b13e, 0xb53e3505, 0x02050032, 0x0032b53e, 0x003a317e, 0xf42885fb, 0xecdff430, 0xf9000005, 0xfeffbf22, 0x99900149, 0x0142fe14, 0x94bd9fa0, 0xa00c2290, 0x3da37e29, 0x00a03300, 0xda040b56, 0x00002944, 0x2db2bcb2, 0x0042d77e, 0xa433a032, 0x41fe4300, 0x10119001, 0x8e7e1ab2, 0xa0320033, 0x3100a433, 0x2bbf1cbf, 0x24d1a4bd, 0x7e000014, 0xa000b06d, 0x00a0b31a, 0x7eb43d1a, 0xb300b105, - 0xbf1200a0, 0x7eff001a, 0x3e00b63f, 0x00003371, 0x0149feff, 0xbf149990, 0x05dcd99f, 0x99bf0000, - 0xf9a60a32, 0x7e070bf4, 0xfb003a31, 0x0e090c25, 0xa43da9a0, 0x30f400f8, 0x05dcdfd8, 0x62f90000, + 0xbf1200a0, 0x7eff001a, 0x3e00b63f, 0x00003371, 0x0149feff, 0xbf149990, 0x05ecd99f, 0x99bf0000, + 0xf9a60a32, 0x7e070bf4, 0xfb003a31, 0x0e090c25, 0xa43da9a0, 0x30f400f8, 0x05ecdfd8, 0x62f90000, 0x30f4ffbf, 0x0149fef4, 0xa04c9990, 0xb2a93f9f, 0x01a398a6, 0x0d019033, 0x60489d33, 0x35a33e03, - 0x04301800, 0x1b010d33, 0x03329801, 0x3d043198, 0x10dc4ba4, 0xd501004c, 0x00000644, 0x0038327e, + 0x04301800, 0x1b010d33, 0x03329801, 0x3d043198, 0x10dc4ba4, 0xd501004c, 0x00000654, 0x0038327e, 0xa4b35aa0, 0x02f80c00, 0x1a3e0501, 0x49fe0037, 0x28999001, 0x00299cd4, 0xb51cb200, 0x91b50741, 0x352bb201, 0x42b51540, 0xbd92a006, 0x10dc4ed4, 0x0020d07e, 0xad33a132, 0xbf015900, 0x33993f59, - 0x980d0090, 0x95f00149, 0x0149b508, 0x000644d9, 0x1899bf00, 0x90336999, 0x9cdf1300, 0x98000029, + 0x980d0090, 0x95f00149, 0x0149b508, 0x000654d9, 0x1899bf00, 0x90336999, 0x9cdf1300, 0x98000029, 0x95f101f9, 0xf9b54000, 0x299cda01, 0x037e0000, 0x3098009c, 0x01027e02, 0x8aa3d900, 0xacb20000, 0xb20091b0, 0xbdb4bd0d, 0x2e70da04, 0x01b00000, 0x08013001, 0xc87e010e, 0x9cd90013, 0xdf000029, 0x1e000000, 0xfe509035, 0x99900149, 0x0142fe34, 0x22909fa0, 0xb2010a38, 0x94ef7e2b, 0x1fa43300, 0xc42bbf1b, 0x1bf401b9, 0x01b5f014, 0x2ba0010a, 0x00950a7e, 0x061fa033, 0xb4bd09f8, 0x0a7e020a, 0x9cda0095, 0x7e000029, 0xfe009ab2, 0xb4bd014a, 0x010dc4bd, 0x7e34aa90, 0x3e0075b0, 0x33003574, - 0xd9320204, 0x00000644, 0xa0b39abf, 0xb4d97f00, 0x98000029, 0x9bbf019c, 0x9cd9f43d, 0xbd000029, + 0xd9320204, 0x00000654, 0xa0b39abf, 0xb4d97f00, 0x98000029, 0x9bbf019c, 0x9cd9f43d, 0xbd000029, 0x159f35d4, 0x7e10dc4e, 0x320020d0, 0x356f3ea1, 0x030d3300, 0x0e7e0207, 0x39180001, 0x00903308, 0x033e9824, 0x002a3cd9, 0x2a44df00, 0x9ea00000, 0xb5043e98, 0x3998019e, 0x98f9a005, 0xfeb5063e, 0x1c391801, 0x21009033, 0x00299cdf, 0x08399800, 0x982dfe98, 0x9efd2efd, 0x2df9b505, 0xfd093998, 0xf9b5059d, 0x01087e2e, 0x3e143d00, 0x33003574, 0x01ab001d, 0xb2016b18, 0x0f817e3a, 0xfe020900, 0xff90014f, 0x3df92048, 0x02f93594, 0x09033318, 0xb2b4bd04, 0x03f335fa, 0x7e01f935, 0x3e000f71, 0xfe00371a, 0x41fe0140, 0x44009001, 0xfe401190, 0x0ab20142, 0xb23c2290, 0x3d2cb21b, 0x75b07ed4, - 0x02399800, 0x010a0fbf, 0x1bf4f9a6, 0x052cde3c, 0xe93f0000, 0x0e009033, 0x1e0a943d, 0x063ee920, + 0x02399800, 0x010a0fbf, 0x1bf4f9a6, 0x0530de3c, 0xe93f0000, 0x0e009033, 0x1e0a943d, 0x063ee920, 0xffd90036, 0xff200000, 0x94b394f9, 0x0ab2121c, 0x2cb21bb2, 0x0098b97e, 0x0036063e, 0x1bb20ab2, 0x3e7e2cb2, 0x4bfe008d, 0x44bb9001, 0xa9c4bebf, 0xffffdf1f, 0x94b6e0ff, 0x04effd18, 0xa0e59eff, 0x0000d9be, 0xe9ff4000, 0x6b0bf494, 0x681fa433, 0x900149fe, 0x9dbf4099, 0xbf049992, 0x1ee4339c, @@ -474,7 +474,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x48991800, 0x0a009433, 0xd23e02f8, 0x90330036, 0x4efe1e01, 0x38ee9001, 0xffdfe9bf, 0xfde0ffff, 0x00df049f, 0xfd010000, 0xe9a0059f, 0x9cd9f43d, 0x0d000029, 0x489f3501, 0xfe014bfe, 0xbb90014c, 0x30cc9034, 0x90014afe, 0xb07e38aa, 0x9b7e0075, 0x143d000a, 0x00371a3e, 0x49fee401, 0x4c999001, - 0xdcd99fbf, 0xbf000005, 0xa61a3299, 0x070bf4f9, 0x003a317e, 0xfb0c30f4, 0xa9922865, 0x929ba004, + 0xecd99fbf, 0xbf000005, 0xa61a3299, 0x070bf4f9, 0x003a317e, 0xfb0c30f4, 0xa9922865, 0x929ba004, 0xecb548ae, 0x00008906, 0xb2e9a030, 0x9294bdaf, 0xfab24cff, 0x00f8f9a0, 0x8f7e02f9, 0xa4b3005c, 0x04bd0a00, 0x00379e3e, 0x00168989, 0x890093fe, 0xfe001633, 0x71890090, 0x91fe0016, 0xbda4bd00, 0x0a897eb4, 0xb0a0b200, 0x1ff400a6, 0x4ba4bd0c, 0x957efe0b, 0xa77e000a, 0x2b3e0038, 0x0ab20016, @@ -483,10 +483,10 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x46899abf, 0x0fc20031, 0x799b7f0f, 0xd95201ff, 0x90907c01, 0x66c4f9ff, 0x2108f4cd, 0xe4d0c17c, 0xa6ffffd9, 0x1508f491, 0x0cf4db66, 0xffc9e410, 0xbc2d60ff, 0x1c3e009a, 0x04bd0038, 0x000a9b7e, 0x0038263e, 0x0ab204bd, 0x040c21fb, 0x0037a87e, 0x12f900f8, 0xa87eb1b2, 0xa0b20037, 0x0c00a0b3, - 0xb4bd1cb2, 0x000b947e, 0x11fb0ab2, 0x327e040c, 0x00f80038, 0xa43dabb2, 0x00384c7e, 0xfc8f00f8, - 0xf9bf0010, 0x361b9918, 0xa9200695, 0x9918f9bf, 0x2499c71b, 0x00f8b920, 0x0010fc8c, 0xaf14cdbf, + 0xb4bd1cb2, 0x000b947e, 0x11fb0ab2, 0x327e040c, 0x00f80038, 0xa43dabb2, 0x00384c7e, 0x0c8f00f8, + 0xf9bf0011, 0x361b9918, 0xa9200695, 0x9918f9bf, 0x2499c71b, 0x00f8b920, 0x00110c8c, 0xaf14cdbf, 0x03bec406, 0x1804e436, 0x94f01bd9, 0x05f9fd3f, 0xbf1bdf35, 0x1bf918cf, 0xfdcf94f0, 0xfe3505e9, - 0x18657e1b, 0x8900f800, 0xbf0010fc, 0x1b9a1899, 0x3624abc7, 0x657e06a5, 0x00f80018, 0x0018547e, + 0x18657e1b, 0x8900f800, 0xbf00110c, 0x1b9a1899, 0x3624abc7, 0x657e06a5, 0x00f80018, 0x0018547e, 0x30f400f8, 0xe482f9e0, 0x95ffffc1, 0xc5b210c2, 0xffffa0e4, 0xb210a395, 0x0148fea4, 0x900147fe, 0x77903c88, 0x018bb534, 0xa0017db5, 0xa00bb27c, 0x7e1ab28a, 0xb20016fc, 0xb2a6b20b, 0x16fc7e2a, 0xb23bb200, 0x7e1ab2a0, 0xb20016fc, 0xb2a1b23b, 0x16fc7e2a, 0x0010bc00, 0xb2106995, 0x0009bcad, @@ -499,9 +499,9 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x029cbb20, 0xf40096b0, 0xbcbc211d, 0x014efef4, 0xfd95a9bc, 0xacbc059f, 0x01e9b5f4, 0xeb98efa0, 0xf4eabf01, 0x00f81030, 0xb9014efe, 0x94bd019f, 0xa0f4afbc, 0x01efb5e9, 0xeb98eabf, 0x3a033e01, 0x1430d900, 0x00df0000, 0x3d000000, 0xf89fa0a4, 0x49180f00, 0x9ff71100, 0xf802f800, 0xf430f400, - 0x0005dcdf, 0xbf12f900, 0x0149feff, 0xb2109990, 0x8a9fa0ab, 0x7e12004c, 0xfe001a87, 0x3f80014a, + 0x0005ecdf, 0xbf12f900, 0x0149feff, 0xb2109990, 0x8a9fa0ab, 0x7e12004c, 0xfe001a87, 0x3f80014a, 0xaa904c4b, 0x7ea1b208, 0x8a001581, 0x7e12004c, 0xf0001a27, 0x1bf43fa4, 0x3e010a09, 0xb2003a8e, - 0x159c7e1a, 0xf4a0a600, 0x02f8e40d, 0x49fea43d, 0x10999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, + 0x159c7e1a, 0xf4a0a600, 0x02f8e40d, 0x49fea43d, 0x10999001, 0xecd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x15fb003a, 0xb212f90c, 0xb2b1b2a9, 0x0190b3ca, 0x0196b021, 0x0a0e08f4, 0x029db3ff, 0x473e00ba, 0x020f003b, 0xf60a0049, 0x553e009f, 0x0049003b, 0x009fcf0a, 0xfefdfe0e, 0x009ff604, 0x2b00d033, 0xcf08004f, 0x94bd00f9, 0x4000f9f6, 0x09cf0900, 0x03e84b00, 0x0016fc7e, 0x0200aab8, @@ -526,35 +526,35 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x9ff60202, 0x009fcf00, 0x153e9fb2, 0x00f8003d, 0x01c0008f, 0xc700f9cf, 0x90b34c99, 0x90b32200, 0x02f8f601, 0x003d543e, 0xc700f9cf, 0x90b34c99, 0x90b33300, 0x02f8f601, 0x003d683e, 0x01c10089, 0xb8009af6, 0x00010099, 0xdf009bf6, 0x800000f2, 0x020099b8, 0x009ff602, 0xb2009fcf, 0x3d683e9f, - 0xd900f800, 0x0000110a, 0x00f89a3f, 0xf9f030f4, 0x05dcd442, 0x49bf0000, 0x0601a2b2, 0x1cb2b4bd, + 0xd900f800, 0x0000111a, 0x00f89a3f, 0xf9f030f4, 0x05ecd442, 0x49bf0000, 0x0601a2b2, 0x1cb2b4bd, 0xfe0140fe, 0x00900143, 0x20339016, 0x39a00ab2, 0x000b947e, 0x4dfe94bd, 0x1cdd9001, 0xd120d9a0, 0x18020975, 0x2ab20429, 0xc4bd0bb2, 0x18090920, 0x09010935, 0x01097501, 0x002c717e, 0x49bf3fbf, - 0x0bf4f9a6, 0x3a317e07, 0x1045fb00, 0xdfec30f4, 0x000005dc, 0xffbf22f9, 0x900149fe, 0xa1b21c99, + 0x0bf4f9a6, 0x3a317e07, 0x1045fb00, 0xdfec30f4, 0x000005ec, 0xffbf22f9, 0x900149fe, 0xa1b21c99, 0x060c9fa0, 0x40feb2b2, 0x90b4bd01, 0x0ab20e00, 0x000b947e, 0x4ffe94bd, 0x18ff9001, 0x1e18f9a0, 0xfe1ab204, 0x11900141, 0x0919a014, 0x02097501, 0x09010975, 0x09f92005, 0xb20e2019, 0x0109350b, - 0x1cb2fdb2, 0x002c717e, 0xa433a032, 0x1abf0c00, 0xb57e2bb2, 0x49fe0027, 0x1c999001, 0xdcd99fbf, - 0xbf000005, 0xa60a3299, 0x070bf4f9, 0x003a317e, 0xf41425fb, 0xdcd9f030, 0xf9000005, 0xfe99bf42, + 0x1cb2fdb2, 0x002c717e, 0xa433a032, 0x1abf0c00, 0xb57e2bb2, 0x49fe0027, 0x1c999001, 0xecd99fbf, + 0xbf000005, 0xa60a3299, 0x070bf4f9, 0x003a317e, 0xf41425fb, 0xecd9f030, 0xf9000005, 0xfe99bf42, 0xff90014f, 0xa0a3b220, 0x4bbab2f9, 0xfc7e03e8, 0x42fe0016, 0xbda1b201, 0x014afe04, 0x901c2290, 0xa4b214aa, 0x0015817e, 0x003ed83e, 0x9c7e4ab2, 0xa0b20015, 0x00000e7e, 0x2bb23ab2, 0x003e0c7e, 0x1600a433, 0x94f029bf, 0x00903301, 0xf401a60d, 0x013edd08, 0x01a6003f, 0x3d0918f4, 0x3f033ea4, - 0xfe040a00, 0x99900149, 0xd99fbf20, 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, 0x30f41045, - 0x05dcdff0, 0x22f90000, 0x49feffbf, 0x18999001, 0xa2b2b032, 0xac7e9fa0, 0xa433003d, 0x04336400, + 0xfe040a00, 0x99900149, 0xd99fbf20, 0x000005ec, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, 0x30f41045, + 0x05ecdff0, 0x22f90000, 0x49feffbf, 0x18999001, 0xa2b2b032, 0xac7e9fa0, 0xa433003d, 0x04336400, 0x143d0a00, 0x003f513e, 0xf0112918, 0x91140f94, 0x0cb4bd02, 0x0140fe06, 0xb20e0090, 0x0b947e0a, 0xfe94bd00, 0xff90014f, 0x35f9a014, 0x097501f1, 0x04291802, 0xfdb20bb2, 0x09202ab2, 0xf9200109, 0x09351809, 0xbd020901, 0x010975c4, 0x002c717e, 0x0e00a433, 0xa08b2ab2, 0x937e0186, 0x49fe003e, - 0x18999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x25fb003a, 0xf030f410, 0x0005dcd9, + 0x18999001, 0xecd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x25fb003a, 0xf030f410, 0x0005ecd9, 0xbf22f900, 0x014ffe99, 0xb218ff90, 0xb2f9a0a1, 0xbd060cb2, 0x014afeb4, 0x7e0eaa90, 0xbd000b94, 0x0140fe94, 0x00901ab2, 0x7e09a014, 0x33003dac, 0x186100a4, 0x99c71119, 0x0094b304, 0x3e20090a, 0x09004005, 0x180920d7, 0x4efe0419, 0x0eee9001, 0x20014ffe, 0x102995e9, 0x3514ff90, 0x299501f9, 0x02f93508, 0xe9351809, 0x75040901, 0x947d01e9, 0xf235ebb2, 0x75fdb203, 0x1ab202e9, 0x717ec4bd, - 0xa433002c, 0x1ab20e00, 0x07a1208b, 0x003e937e, 0x900149fe, 0x9fbf1899, 0x0005dcd9, 0xa699bf00, - 0x070bf4f9, 0x003a317e, 0xf41025fb, 0xdcdfec30, 0xf9000005, 0xfeffbf72, 0x99900149, 0xa0a1b230, + 0xa433002c, 0x1ab20e00, 0x07a1208b, 0x003e937e, 0x900149fe, 0x9fbf1899, 0x0005ecd9, 0xa699bf00, + 0x070bf4f9, 0x003a317e, 0xf41025fb, 0xecdfec30, 0xf9000005, 0xfeffbf72, 0x99900149, 0xa0a1b230, 0xb2b7b29f, 0xb3d672c3, 0x009e00a9, 0x0100d671, 0x00950cf5, 0xb4bd54bd, 0x40fe060c, 0x0142fe01, 0x90200090, 0x05a02c22, 0xa0020575, 0x0144fe25, 0xb2264490, 0x0b947e4a, 0x7e1ab200, 0x33003dac, 0x356800a4, 0x19180323, 0x750bb204, 0x2db20205, 0x02090920, 0x39952920, 0x01293510, 0x35083995, 0x08090229, 0x09010935, 0x751ab204, 0xc4bd0109, 0x002c717e, 0x3300a433, 0x75014675, 0x19180245, 0xb24bb204, 0x201ab27d, 0xbd100949, 0x014935c4, 0x002c717e, 0x1300a433, 0x004b1ab2, 0x3e937e32, - 0x41273e00, 0xfe350a00, 0x99900149, 0xd99fbf30, 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, + 0x41273e00, 0xfe350a00, 0x99900149, 0xd99fbf30, 0x000005ec, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, 0x52f91475, 0xaa98a2b2, 0xb2c3b205, 0xbffd09d5, 0x10bebcae, 0xa601ef92, 0x230cf4f9, 0x0901af98, 0xf4f9a6ff, 0xf0b3190b, 0x1ea61600, 0xbc1008f4, 0x91a690c1, 0xa60808f4, 0x050df49f, 0x291802f8, 0xc7010a11, 0x94b30599, 0x2ab23f00, 0x0029d77e, 0xa433a432, 0x04bd3100, 0x0041be3e, 0xb1d230bc, @@ -573,8 +573,8 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x853e0101, 0x42bc0043, 0x0096b192, 0x060df401, 0x90010049, 0x96ff0399, 0x0b947e04, 0xb23bb200, 0xdd0c725a, 0x00001200, 0x7e3030bc, 0x320028d7, 0x00a433a1, 0x08b0b434, 0xb209c0b4, 0x1200da2d, 0x20bc0000, 0x01004e20, 0x0021367e, 0x0a00a033, 0x853e02f8, 0x00da0043, 0xbd000012, 0x01004cb4, - 0x08f424a6, 0xfb1a32a4, 0xf4f0fc60, 0xf4f90430, 0xdfe430f4, 0x000005dc, 0xffbf42f9, 0x900149fe, - 0xa1b22c99, 0x0ad99fa0, 0x3f000011, 0x00903399, 0x3e043d0a, 0xbd0044ff, 0x0149fef4, 0xa0249990, + 0x08f424a6, 0xfb1a32a4, 0xf4f0fc60, 0xf4f90430, 0xdfe430f4, 0x000005ec, 0xffbf42f9, 0x900149fe, + 0xa1b22c99, 0x1ad99fa0, 0x3f000011, 0x00903399, 0x3e043d0a, 0xbd0044ff, 0x0149fef4, 0xa0249990, 0x0499929f, 0x99929fa0, 0x05a29804, 0xa006a498, 0x27c37e9f, 0x33a03200, 0x330800a0, 0xbf6b2ea4, 0x0129982b, 0x18f5b9a6, 0xb9e40133, 0x1bf50fff, 0x43fe012b, 0x901ab201, 0x040c1c33, 0xd77e3db2, 0xa0320028, 0x4200a433, 0x35003fbf, 0x46464ad9, 0xf4f9a653, 0x1ab2331b, 0x002f9e7e, 0x3600a433, @@ -584,19 +584,19 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x09200104, 0xf9209f09, 0x09351909, 0x75030901, 0x09750104, 0x0142fe02, 0x22901ab2, 0x7e2cb224, 0x32002c71, 0x00a433a0, 0xb22bbf5a, 0x27777e1a, 0x33a03200, 0x184c00a4, 0x29c71112, 0x0094b305, 0x0143fe39, 0x33901ab2, 0x7e3bb220, 0x33003e0c, 0xbf1500a4, 0x0229943f, 0xfd3c94f0, 0x0bf4049f, - 0x20143506, 0xb43d1ab2, 0x003f1e7e, 0x0a00a033, 0xff3ea032, 0x010f0044, 0x00110ad9, 0xfe9f2000, - 0x99900149, 0xd99fbf2c, 0x000005dc, 0x0a3299bf, 0x0bf4f9a6, 0x451f3e11, 0x3e020000, 0x7e004446, + 0x20143506, 0xb43d1ab2, 0x003f1e7e, 0x0a00a033, 0xff3ea032, 0x010f0044, 0x00111ad9, 0xfe9f2000, + 0x99900149, 0xd99fbf2c, 0x000005ec, 0x0a3299bf, 0x0bf4f9a6, 0x451f3e11, 0x3e020000, 0x7e004446, 0xfb003a31, 0xa0b31c45, 0xaa982100, 0xbffd0f06, 0x019992a9, 0x0cf49fa6, 0x01aa9811, 0xa9a6ff09, 0xb3070bf4, 0xf80a00a4, 0xf8020a02, 0xffb9e400, 0xf4020a0f, 0x7cd9451b, 0x98000029, 0x903e049f, 0xf9180045, 0x00903308, 0x09f91828, 0x21009033, 0x5802f958, 0x93f003fe, 0x0c94b600, 0x08f4b9a6, - 0xffe9e40f, 0x0c94b6ff, 0x0df4b9a6, 0x04ff980a, 0xd200f4b3, 0x350acfa0, 0x30f400f8, 0x05dcdff8, + 0xffe9e40f, 0x0c94b6ff, 0x0df4b9a6, 0x04ff980a, 0xd200f4b3, 0x350acfa0, 0x30f400f8, 0x05ecdff8, 0x52f90000, 0xa4b2ffbf, 0xfe0149fe, 0x99900142, 0xb2b0b21c, 0xa0d5b2c3, 0x0a14bd9f, 0x18229035, 0x0046513e, 0x0bb24ab2, 0x2db2040c, 0x0028d77e, 0x8900ad33, 0xb329bf00, 0x900e0094, 0x00902011, 0x46513e04, 0x019eb900, 0x8904e9fd, 0xffff0000, 0xfcf094e9, 0x01f6f00b, 0x00ff00d9, 0x94e9ffff, 0xf00bbcf0, 0xf0d901b6, 0xfff0f0f0, 0xccf094e9, 0x01c6f00b, 0xccccccd9, 0x94e9ffcc, 0xf00bdcf0, 0xaad901d6, 0xb6aaaaaa, 0xb4b604f4, 0x02c4b603, 0xfd01d4b6, 0x9cf004e9, 0x0196f00b, 0xfd05f9fd, 0xfcfd05fb, 0x05fdfd05, 0x1fbc2fa0, 0x46573e10, 0xf503a600, 0xa0ff710d, 0x0149fe51, 0xbf1c9990, - 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x3a317e07, 0x0855fb00, 0xc4b252f9, 0xe3b2d1b2, 0xb5b2a2b2, + 0x05ecd99f, 0x99bf0000, 0x0bf4f9a6, 0x3a317e07, 0x0855fb00, 0xc4b252f9, 0xe3b2d1b2, 0xb5b2a2b2, 0xc4bdedb2, 0x0046e33e, 0x3f90eebc, 0x909abcbf, 0xbc01bb90, 0x9e929090, 0x03ea9430, 0xb207f0c2, 0x30f912bd, 0xf4099630, 0xe4b3e10d, 0x010e0600, 0x2d64f033, 0x0064f631, 0x330b1cf4, 0x3e2862f4, 0x330046cf, 0x330c73f0, 0x3e1c77f4, 0xbc0046d6, 0xe33ec0ce, 0xeebc0046, 0x46e03e90, 0x02e99400, @@ -609,17 +609,17 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0xfd4c0090, 0xeb3e05f4, 0xa9180047, 0x90af3f01, 0x94f002ad, 0xfff4f0ff, 0xff0894b6, 0xeb3ef59f, 0xad180047, 0x02af1803, 0xa918ae3f, 0x18d4b601, 0xb6fff4f0, 0xe4f010f4, 0xff94f0ff, 0xfd0894b6, 0x9ffd059e, 0xf59dff05, 0xa004ad90, 0x01cc920f, 0xb2040090, 0xb302b2da, 0xff7000cd, 0xb0333b3f, - 0x3f900f00, 0x3ec4bd01, 0x0100474a, 0xfb1a32ff, 0xf830f451, 0xdcd222f9, 0xbf000005, 0xfebcb229, + 0x3f900f00, 0x3ec4bd01, 0x0100474a, 0xfb1a32ff, 0xf830f451, 0xecd222f9, 0xbf000005, 0xfebcb229, 0x40fe0141, 0x10119001, 0xa00c0090, 0xb2d4bd19, 0x0074de0b, 0x747e0000, 0x1fbf0046, 0x0a7f29bf, - 0x0bf4f9a6, 0x3a317e07, 0x0825fb00, 0xf9f830f4, 0x05dcd222, 0x29bf0000, 0x41febcb2, 0x0140fe01, + 0x0bf4f9a6, 0x3a317e07, 0x0825fb00, 0xf9f830f4, 0x05ecd222, 0x29bf0000, 0x41febcb2, 0x0140fe01, 0x90101190, 0x19a00c00, 0x0bb2d4bd, 0x000076de, 0x46747e00, 0xbf1fbf00, 0xa60abf29, 0x070bf4f9, - 0x003a317e, 0xf40825fb, 0x22f9f830, 0x0005dcd2, 0xb229bf00, 0x0141febc, 0x900140fe, 0x00901011, + 0x003a317e, 0xf40825fb, 0x22f9f830, 0x0005ecd2, 0xb229bf00, 0x0141febc, 0x900140fe, 0x00901011, 0xbd19a00c, 0xde0bb2d4, 0x00000078, 0x0046747e, 0x29bf1fbf, 0xf9a60a3f, 0x7e070bf4, 0xfb003a31, - 0x30f40825, 0x05dcdff0, 0x62f90000, 0x49feffbf, 0x0143fe01, 0xfe289990, 0x9fa00142, 0x001404d6, + 0x30f40825, 0x05ecdff0, 0x62f90000, 0x49feffbf, 0x0143fe01, 0xfe289990, 0x9fa00142, 0x001404d6, 0x1c339000, 0x05242290, 0xbf040402, 0x0d080c6a, 0x7e3bb2ff, 0x330000c1, 0x98f400a4, 0x193f0131, 0xeb079433, 0x3d041918, 0x2944da04, 0x94330000, 0x907e0a00, 0xa0320043, 0xb2013b18, 0x0f817e1a, 0x00043300, 0x022035ca, 0x11182520, 0x352ab203, 0xb4bd0124, 0x7e032135, 0x3e000f71, 0xf40048eb, - 0xdcdff430, 0xf9000005, 0xbdffbf22, 0x0140fe94, 0xb50c0090, 0x09a00109, 0x900149fe, 0x7cd21499, + 0xecdff430, 0xf9000005, 0xbdffbf22, 0x0140fe94, 0xb50c0090, 0x09a00109, 0x900149fe, 0x7cd21499, 0xa000002e, 0x7e01b29f, 0x3e0074f8, 0x9800497e, 0x993f0119, 0x0a099433, 0x967e0ab2, 0x70da0033, 0x7e00002e, 0xb2001475, 0xb22abfad, 0x7e080c0b, 0x330000c1, 0xdadc00a0, 0x00002e70, 0x0014b57e, 0x00497e3e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -633,22 +633,22 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x667e0050, 0x307e004d, 0x7e7e0052, 0xdf7e0052, 0xe77e004d, 0x897e0052, 0x9c7e0053, 0xbf7e0053, 0xd47e0053, 0xe97e0053, 0xfe7e0053, 0x857e0053, 0x4f7e0070, 0xfa7e0054, 0xf57e0058, 0x3a7e0051, 0xc74c0054, 0x00c3f161, 0x01943d00, 0x28913002, 0x30009130, 0x91300891, 0x14913010, 0x30189130, - 0x91301c91, 0x24913020, 0x300111b0, 0xc0da0c11, 0xdb000005, 0x0000018c, 0x804e010d, 0x5d0a7e00, + 0x91301c91, 0x24913020, 0x300111b0, 0xd0da0c11, 0xdb000005, 0x0000018c, 0x804e010d, 0x5d0a7e00, 0x00ad3300, 0x08da023e, 0x0b000014, 0x7e010c04, 0x33005937, 0x022c00ad, 0xf168444c, 0x000000c3, 0x28a13001, 0x3000a130, 0xa13008a1, 0x10a1300c, 0x3014a130, 0xa13018a1, 0x24a13020, 0x000168db, - 0x0101b000, 0x0d1c0130, 0x00804e03, 0x0005c4da, 0x5d0a7e00, 0x1400da00, 0x040b0000, 0x377e080c, + 0x0101b000, 0x0d1c0130, 0x00804e03, 0x0005d4da, 0x5d0a7e00, 0x1400da00, 0x040b0000, 0x377e080c, 0xad330059, 0x4c01dd00, 0xc3f16f6b, 0x44db0000, 0x30000001, 0xa13028a1, 0x10a13000, 0x3014a130, - 0xa13018a1, 0x24a13020, 0x300101b0, 0x11300811, 0x1c01300c, 0x804e080d, 0x05c8da00, 0x0a7e0000, + 0xa13018a1, 0x24a13020, 0x300101b0, 0x11300811, 0x1c01300c, 0x804e080d, 0x05d8da00, 0x0a7e0000, 0x20da005d, 0x0b000014, 0x7e080c04, 0x33005937, 0x019000ad, 0xf1493f4c, 0xdb0000c3, 0x00000120, 0x3028a130, 0xa13000a1, 0x14a13010, 0x3018a130, 0xa13020a1, 0x0101b024, 0x30081130, 0x01300c11, - 0x4e070d1c, 0xccda0100, 0x7e000005, 0xda005d0a, 0x00002e7c, 0x080c1bb2, 0x0059377e, 0x4300ad33, + 0x4e070d1c, 0xdcda0100, 0x7e000005, 0xda005d0a, 0x00002e7c, 0x080c1bb2, 0x0059377e, 0x4300ad33, 0x48c24c01, 0x0000c3f1, 0x0000fcdb, 0x28a13000, 0x3000a130, 0xa13010a1, 0x18a13014, 0x3020a130, - 0x01b024a1, 0x08113001, 0x300c1130, 0x050d1c01, 0xda00c04e, 0x000005d0, 0x005d0a7e, 0x001404da, + 0x01b024a1, 0x08113001, 0x300c1130, 0x050d1c01, 0xda00c04e, 0x000005e0, 0x005d0a7e, 0x001404da, 0x0c040b00, 0x59377e08, 0x00ad3300, 0x4d4c00f6, 0x00c3f171, 0x00d8db00, 0xa1300000, 0x00a13028, 0x3010a130, 0xa13014a1, 0x20a13018, 0xb024a130, 0x11300101, 0x0c113008, 0x0d1c0130, 0x00804e09, - 0x0005d4da, 0x5d0a7e00, 0x1428da00, 0x040b0000, 0x377e080c, 0xad330059, 0x4c00a900, 0xc3f1b7cb, + 0x0005e4da, 0x5d0a7e00, 0x1428da00, 0x040b0000, 0x377e080c, 0xad330059, 0x4c00a900, 0xc3f1b7cb, 0xb4db0000, 0x30000000, 0xa13028a1, 0x10a13000, 0x3014a130, 0xa13018a1, 0x24a13020, 0x300c1130, - 0x01b01c01, 0x08113001, 0xc04e0a0d, 0x05d8da00, 0x0a7e0000, 0x1cda005d, 0x0b000014, 0x7e080c04, + 0x01b01c01, 0x08113001, 0xc04e0a0d, 0x05e8da00, 0x0a7e0000, 0x1cda005d, 0x0b000014, 0x7e080c04, 0x33005937, 0x7e5c00a4, 0x7e005c97, 0x7e004db4, 0x7e005931, 0x7e000a74, 0x7e003cf7, 0x7e005249, 0x7e004d7d, 0x7e004df2, 0x7e005208, 0x7e005216, 0x7e0053af, 0x7e0053d2, 0x7e0053e7, 0x7e0053fc, 0x7e005438, 0x7e00544d, 0x7e00591d, 0x7e00706d, 0x7e005462, 0x7e004ea6, 0x330059ae, 0xf80600a0, @@ -692,7 +692,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x11999800, 0x00f895f9, 0xc4bdb4bd, 0xa4bdd43d, 0x003aa97e, 0x30da00f8, 0x3d000029, 0x5e7f7eb4, 0x2930d900, 0x99bf0000, 0x060094b3, 0x00f802f8, 0x001430d9, 0x3d9fbf00, 0x2e8bda94, 0xa9200000, 0xf910f998, 0xf8a43d95, 0x140cd900, 0x9abf0000, 0xb803034b, 0x0002dcaa, 0x001a877e, 0x066f448a, - 0x001a277e, 0x000600d9, 0xffa4f100, 0x42408f3f, 0xd99aa00f, 0x00000604, 0x9fa0a43d, 0x30d900f8, + 0x001a277e, 0x000610d9, 0xffa4f100, 0x42408f3f, 0xd99aa00f, 0x00000614, 0x9fa0a43d, 0x30d900f8, 0xbf000014, 0xda943d9f, 0x00002e8c, 0xf9bfa920, 0xa43d95f9, 0x02f900f8, 0xd4bdc4bd, 0x110ab4bd, 0x001f137e, 0x0484a0b8, 0x7e0ab200, 0xc5001a27, 0x0ab201ab, 0x001a877e, 0x08b8c08a, 0x001a277e, 0xa9fffb09, 0xb8c08ab4, 0x1a877e08, 0xb9408a00, 0x1a277e08, 0xffe00900, 0x408ab4a9, 0xb5f008b9, @@ -708,7 +708,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0xbf000014, 0x2978da99, 0x99980000, 0xdf95f90f, 0x00002970, 0x002944d9, 0x069fb500, 0x002968df, 0x059fb500, 0x9f35f4bd, 0xb59fa009, 0x9f35019f, 0xb5320f08, 0x00f8039f, 0x30d900f8, 0xbf000014, 0x2e94da99, 0x99980000, 0xf895f906, 0xd900f800, 0x00001430, 0x98da99bf, 0x98000029, 0x95f90199, - 0x30f500f8, 0xdcdfff18, 0xf9000005, 0xfeffbf82, 0x99b80149, 0x0a000108, 0x7e9fa008, 0xb2001a27, + 0x30f500f8, 0xecdfff18, 0xf9000005, 0xfeffbf82, 0x99b80149, 0x0a000108, 0x7e9fa008, 0xb2001a27, 0x7e080aa0, 0xd9001a27, 0x40000000, 0xf50409fd, 0x95044d1b, 0x99b31fa9, 0x3d044601, 0x01dc4ba4, 0xa87e040c, 0xa4b20037, 0x4500a9b3, 0x76a0b503, 0xb571a0b5, 0xa0b572a0, 0x74a0b573, 0xd975a0b5, 0x00002990, 0x90014ffe, 0x44dae8ff, 0xb5000029, 0xc37e019f, 0xa2320027, 0x0900a033, 0x112ead33, @@ -744,41 +744,41 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0xb8001a87, 0x00061c00, 0x277e0ab2, 0xabc5001a, 0x7e0ab204, 0x90001a87, 0x33950144, 0x01229d01, 0xf59523ff, 0x3eff641b, 0xfe0058dc, 0x90da0140, 0x90000029, 0xd4bd6000, 0x98de0bb2, 0x7e000000, 0x33004674, 0xff2a00ad, 0xfe0142fe, 0x03b20145, 0x2290143d, 0x24559098, 0x0056a03e, 0xb80149fe, - 0x00010899, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x83fb003a, 0xb4bd00e8, 0xda00c04c, - 0x0000299c, 0x000b947e, 0x001430d9, 0xda99bf00, 0x00002a58, 0xf90d9998, 0xf8a43d95, 0x05ccd900, + 0x00010899, 0xecd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x83fb003a, 0xb4bd00e8, 0xda00c04c, + 0x0000299c, 0x000b947e, 0x001430d9, 0xda99bf00, 0x00002a58, 0xf90d9998, 0xf8a43d95, 0x05dcd900, 0x9abf0000, 0x002e70db, 0x7e010c00, 0xf8005e25, 0x5c877e00, 0x3d00f800, 0x5e937ed4, 0xf400f800, 0x12f9e430, 0xb0b2a1b2, 0x6100b0b3, 0xb004b998, 0x0cf40896, 0x0ba43d57, 0x384c7e44, 0x0aafb200, 0x00f0b305, 0x0a09584a, 0x90014afe, 0xafb508aa, 0x010f9801, 0xb60093f0, 0xa9b50294, 0x02afb503, 0xb2100918, 0x18a9351b, 0xb5020f98, 0x099804af, 0x05a9b503, 0xa0a000bf, 0x005b0b7e, 0xf001a6b0, 0x9a120b9c, 0x59ab3e01, 0xfb020a00, 0xe27e1c15, 0x943d0059, 0xf001a6b0, 0xa6f00bac, 0xa29a3c01, - 0x548900f8, 0x9ebf0005, 0xb5019f98, 0x9ea0019f, 0x005a267e, 0x0801a4b3, 0x00f8a43d, 0xff0a02f8, - 0x12f900f8, 0x000f8c89, 0xf20a99bf, 0x380090b3, 0x000fa881, 0xf10a10bf, 0x2c0004b3, 0x000a747e, - 0x19a00109, 0x000f9889, 0x948990a0, 0xff0f0010, 0x90899fa0, 0x90a0000f, 0x000f9489, 0x587e9fa0, - 0x10a00037, 0x12f911fb, 0x000f8c89, 0xb4bd04bd, 0xb44c90a0, 0x0fac8a00, 0x0b947e00, 0x0cb4bd00, - 0x10a08a14, 0x0b947e00, 0x0cb4bd00, 0x10b48a14, 0x0b947e00, 0x107c8900, 0x8990a000, 0xbd001078, - 0x0c90a0b4, 0x10648a14, 0x0b947e00, 0x10808a00, 0x0cb4bd00, 0x0b947e14, 0x109c8900, 0x8990a000, - 0xa0000f98, 0x10948990, 0x8990a000, 0xa0001060, 0x0fa88990, 0x8990a000, 0xa0000f9c, 0x10988990, - 0x8990a000, 0xa0000fa4, 0x0fa08990, 0x8990a000, 0xa0000f90, 0x10608190, 0x0f948900, 0x8090a000, - 0xb2000fac, 0x1400900a, 0x000bd07e, 0x1bf401a6, 0x10a08af5, 0x0bd07e00, 0x10b48a00, 0x0bd07e00, - 0x10648a00, 0x0bd07e00, 0x10808a00, 0x0bd07e00, 0x107c8900, 0x10a08f00, 0x899fa000, 0x8f001078, - 0xa00010b4, 0x5c727e9f, 0xf911fb00, 0xb2a0b232, 0x00a9b3b3, 0xa9bf00c7, 0x94b30101, 0xf8010600, + 0x588900f8, 0x9ebf0005, 0xb5019f98, 0x9ea0019f, 0x005a267e, 0x0801a4b3, 0x00f8a43d, 0xff0a02f8, + 0x12f900f8, 0x000f9c89, 0xf20a99bf, 0x380090b3, 0x000fb881, 0xf10a10bf, 0x2c0004b3, 0x000a747e, + 0x19a00109, 0x000fa889, 0xa48990a0, 0xff0f0010, 0xa0899fa0, 0x90a0000f, 0x000fa489, 0x587e9fa0, + 0x10a00037, 0x12f911fb, 0x000f9c89, 0xb4bd04bd, 0xb44c90a0, 0x0fbc8a00, 0x0b947e00, 0x0cb4bd00, + 0x10b08a14, 0x0b947e00, 0x0cb4bd00, 0x10c48a14, 0x0b947e00, 0x108c8900, 0x8990a000, 0xbd001088, + 0x0c90a0b4, 0x10748a14, 0x0b947e00, 0x10908a00, 0x0cb4bd00, 0x0b947e14, 0x10ac8900, 0x8990a000, + 0xa0000fa8, 0x10a48990, 0x8990a000, 0xa0001070, 0x0fb88990, 0x8990a000, 0xa0000fac, 0x10a88990, + 0x8990a000, 0xa0000fb4, 0x0fb08990, 0x8990a000, 0xa0000fa0, 0x10708190, 0x0fa48900, 0x8090a000, + 0xb2000fbc, 0x1400900a, 0x000bd07e, 0x1bf401a6, 0x10b08af5, 0x0bd07e00, 0x10c48a00, 0x0bd07e00, + 0x10748a00, 0x0bd07e00, 0x10908a00, 0x0bd07e00, 0x108c8900, 0x10b08f00, 0x899fa000, 0x8f001088, + 0xa00010c4, 0x5c727e9f, 0xf911fb00, 0xb2a0b232, 0x00a9b3b3, 0xa9bf00c7, 0x94b30101, 0xf8010600, 0x30180918, 0x0df40896, 0x98fe0105, 0xf9c4020f, 0x050bf403, 0x0998fb01, 0x0394f003, 0x01050bf4, 0x00f4b3fb, 0x98fa0106, 0x99b30109, 0xb3008e00, 0x0085011d, 0xde7e0ab2, 0xa1b2005b, 0x7801a4b3, - 0x02980ab2, 0x5bf97e01, 0x0a747e00, 0x109c8900, 0x909fbf00, 0x9fa001ff, 0x94b399bf, 0x8c890e01, - 0x92a0000f, 0x005ba53e, 0x000fa889, 0x94b399bf, 0x8c8e1700, 0xe9bf000f, 0x18180f18, 0x9f264199, - 0xa0050cf4, 0x7e2ab2e2, 0xb30005c7, 0xa0060030, 0x0a9b7e32, 0x0fa88900, 0xb399bf00, 0x89190090, - 0xbf000f8c, 0x180f1899, 0x26419918, 0x0718f49f, 0x00000e7e, 0x31fb1ab2, 0xd43efa01, 0xa998005b, + 0x02980ab2, 0x5bf97e01, 0x0a747e00, 0x10ac8900, 0x909fbf00, 0x9fa001ff, 0x94b399bf, 0x9c890e01, + 0x92a0000f, 0x005ba53e, 0x000fb889, 0x94b399bf, 0x9c8e1700, 0xe9bf000f, 0x18180f18, 0x9f264199, + 0xa0050cf4, 0x7e2ab2e2, 0xb30005c7, 0xa0060030, 0x0a9b7e32, 0x0fb88900, 0xb399bf00, 0x89190090, + 0xbf000f9c, 0x180f1899, 0x26419918, 0x0718f49f, 0x00000e7e, 0x31fb1ab2, 0xd43efa01, 0xa998005b, 0x0aafb205, 0x0090b3fa, 0x03f99812, 0x96b1e80a, 0x0df400ff, 0xf8010a05, 0xb212f900, 0x03ac98a1, 0x9802aa98, 0xa5db0110, 0x7ea5a5a5, 0x98000b94, 0x1a980319, 0xa0a9bc02, 0x1bbf0aa0, 0x7e041c98, 0xa000373a, 0x00aab90a, 0x98030ab5, 0x0a900519, 0x0109b510, 0x35181918, 0x19984109, 0x0209b502, 0x09b519bf, 0x1819180e, 0x98400935, 0x09b50319, 0x0be77e0f, 0x240a9000, 0x000be77e, 0x180700b5, 0x0909181f, 0xf00c00b5, 0x9fbbfff4, 0x0909b502, 0xa48911fb, 0x93fe0016, 0x05ad8a00, 0x7eb43d00, - 0x0a005dd4, 0x8900f801, 0xa00010c8, 0x8900f89a, 0xbf0010c8, 0x8a00f89a, 0x3d002e80, 0x5e7f7eb4, - 0x00a03300, 0xf809f808, 0x10d08a00, 0x7eb43d00, 0x33005e89, 0xf80600a0, 0xf000f809, 0x94bd00b3, - 0xa5a5a5df, 0x5cd13ea5, 0x90afa000, 0xaa900199, 0xf49ba604, 0x00f8f608, 0x00335089, 0x0010ec8f, + 0x0a005dd4, 0x8900f801, 0xa00010d8, 0x8900f89a, 0xbf0010d8, 0x8a00f89a, 0x3d002e80, 0x5e7f7eb4, + 0x00a03300, 0xf809f808, 0x10e08a00, 0x7eb43d00, 0x33005e89, 0xf80600a0, 0xf000f809, 0x94bd00b3, + 0xa5a5a5df, 0x5cd13ea5, 0x90afa000, 0xaa900199, 0xf49ba604, 0x00f8f608, 0x00335089, 0x0010fc8f, 0xf9b59ab2, 0x35508b01, 0x02b9bb00, 0x7502b5b6, 0xbb7e04fb, 0x00f8005c, 0x0059c27e, 0x0c00a433, 0x005cd87e, 0x005e217e, 0x30f400f8, 0xb262f9e4, 0xb2a5b2c4, 0x72d332b0, 0x44c034e2, 0xb3546034, - 0x00ae00a9, 0xa900b9b3, 0x10ec8900, 0x149fbf00, 0x2ae406ce, 0x0501ffff, 0xf034bfa0, 0xc49ba048, + 0x00ae00a9, 0xa900b9b3, 0x10fc8900, 0x149fbf00, 0x2ae406ce, 0x0501ffff, 0xf034bfa0, 0xc49ba048, 0x943603c9, 0x03f4f002, 0xfd04fd14, 0x9efd059f, 0x059dfd05, 0x3502a4b6, 0x547e1bb9, 0xa0b30038, 0x90347100, 0x1d09354c, 0xb564f034, 0x0275010a, 0x1803350a, 0xb41a0f35, 0x49fe10f0, 0x1c999001, 0xb5019ab5, 0x9fb50390, 0x7594a004, 0x93350a92, 0x35f43d16, 0xf4bd1e0f, 0x9fb59bb2, 0x0140fe02, @@ -796,15 +796,15 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0xbd014efe, 0x18ee90f4, 0x005f163e, 0xff90e9bf, 0x9049bc01, 0xf3a6e9a0, 0xbff408f4, 0x549990e9, 0x0bf459a6, 0xb3e80105, 0x009e0029, 0x990009b3, 0x011db300, 0x02a00096, 0x000a747e, 0xe9980ebf, 0xb9efbf14, 0xf9a60099, 0x01091bf4, 0x5fbd3ed1, 0x54299000, 0x0ebfe9a0, 0xbc545f92, 0xff0cd2f4, - 0x888be9bf, 0x9fbc000f, 0x01e9b590, 0x94bd0fbf, 0xbf0ef9b5, 0xb59fbf09, 0x0fbf029f, 0x9dbcf9bf, + 0x988be9bf, 0x9fbc000f, 0x01e9b590, 0x94bd0fbf, 0xbf0ef9b5, 0xb59fbf09, 0x0fbf029f, 0x9dbcf9bf, 0x03f9b590, 0x93b509bf, 0xb509bf0f, 0x09bf1094, 0xbf119cb5, 0x129cb509, 0xbfbf09bf, 0xbf139fb5, 0x90baa00a, 0xd07e10aa, 0x0abf000b, 0x7e24aa90, 0xbf000bd0, 0xb9f9bf0f, 0xf9b50099, 0x0a9b7e14, 0x5fc73e00, 0xb2fa0100, 0x0455fb1a, 0xa1b242f9, 0xc2b2b4b2, 0xde00d3b2, 0x0cf4baa6, 0x0a747e27, 0xb22ab200, 0xbd540b1c, 0x7e3eb2d4, 0xb2005ed7, 0x01a4b3a0, 0xb23abf0c, 0x5ed27e4b, 0x0a9b7e00, 0xfb0ab200, 0x89008f41, 0x00f9ce02, 0xf70195f0, 0x00f800f9, 0x0089010f, 0x9ff60280, 0xb800f800, 0x000180aa, 0xf609a4b6, 0x00f800ab, 0x03210089, 0xb8009af6, 0x02010099, 0xf8009af6, 0xf030f400, - 0x0005dcdf, 0xbf82f900, 0x0149feff, 0x32309990, 0x7e9fa0a1, 0xc4006014, 0x43feff1a, 0x1ae87e01, - 0x0142fe00, 0xb2ff16c4, 0x0f84d4a5, 0x33900000, 0x2c229024, 0x001400d8, 0x2e68d700, 0x9c3e0000, + 0x0005ecdf, 0xbf82f900, 0x0149feff, 0x32309990, 0x7e9fa0a1, 0xc4006014, 0x43feff1a, 0x1ae87e01, + 0x0142fe00, 0xb2ff16c4, 0x0f94d4a5, 0x33900000, 0x2c229024, 0x001400d8, 0x2e68d700, 0x9c3e0000, 0x093f0061, 0x1e009433, 0xb2987ebc, 0xe949bc6a, 0x001ae87e, 0xa5b21b32, 0x817e0ab2, 0x9c3e000f, 0x09180061, 0x20010f01, 0x35fc0f3f, 0x30b50131, 0xff94f001, 0xfd039990, 0x09bc049f, 0xe949bc90, 0xf0330f3f, 0xf6307307, 0x150cf407, 0x9104f933, 0x05f03300, 0x02fd3355, 0xfe3e00c7, 0xf0330060, @@ -814,60 +814,60 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x3e000014, 0xd9006157, 0x00001428, 0x903e9abf, 0x1cdf0061, 0xbf000014, 0x61903efa, 0x3d2f2000, 0x350ab294, 0x00180229, 0x351b3203, 0x2035012f, 0x0f817e03, 0xb2b4bd00, 0x0f717e2a, 0x0a747e00, 0x19e87e00, 0x0028f400, 0x000a9b7e, 0x00619c3e, 0x0c00a0b3, 0x080c3bb2, 0x0000a77e, 0xbcff1ec4, - 0x05a6084e, 0xfede1bf5, 0x0060057e, 0x900149fe, 0x9fbf3099, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, - 0x003a317e, 0xf41085fb, 0xdcdfb830, 0xf9000005, 0xfeffbf62, 0x99900149, 0xa03c0c60, 0x0140fe9f, - 0x0090b4bd, 0x7e0ab224, 0xd9000b94, 0x01000000, 0x002e68d1, 0xa09bb200, 0x0f84d919, 0xa4bd0000, + 0x05a6084e, 0xfede1bf5, 0x0060057e, 0x900149fe, 0x9fbf3099, 0x0005ecd9, 0xa699bf00, 0x070bf4f9, + 0x003a317e, 0xf41085fb, 0xecdfb830, 0xf9000005, 0xfeffbf62, 0x99900149, 0xa03c0c60, 0x0140fe9f, + 0x0090b4bd, 0x7e0ab224, 0xd9000b94, 0x01000000, 0x002e68d1, 0xa09bb200, 0x0f94d919, 0xa4bd0000, 0xf57e9ba0, 0x1bbf001a, 0x343da4bd, 0x7e008046, 0xbf00601f, 0x75020911, 0x09350406, 0x0101b501, 0x350a0335, 0xb4bd0b03, 0xda00804c, 0x01000000, 0x000b947e, 0xbd00804c, 0x0080dab4, 0x947e0100, - 0x057e000b, 0x80df0060, 0xd4010000, 0x00002e6c, 0x4fa0fab2, 0x00602c7e, 0xd0d24fbf, 0x75000010, + 0x057e000b, 0x80df0060, 0xd4010000, 0x00002e6c, 0x4fa0fab2, 0x00602c7e, 0xe0d24fbf, 0x75000010, 0x03350806, 0x80f99012, 0xd90229b5, 0x00001b04, 0xb5030fb5, 0x1dd90329, 0xfe00001b, 0x29b50145, - 0x1f559005, 0x53350109, 0x35592003, 0xecd91309, 0xb5000010, 0x0975012f, 0x1b0ddf01, 0x04090000, + 0x1f559005, 0x53350109, 0x35592003, 0xfcd91309, 0xb5000010, 0x0975012f, 0x1b0ddf01, 0x04090000, 0x35042fb5, 0x32df0259, 0x0900000e, 0x062fb540, 0x20015935, 0x0a747e03, 0x7e2abf00, 0xb200009b, 0x7e5ab20b, 0x7e000f71, 0x0f000a9b, 0x11004907, 0xd1009ff7, 0x00001408, 0x900140fe, 0x1abf2300, 0x010c0bb2, 0xc17eff0d, 0xa4330000, 0x093ff400, 0xee019433, 0x00603d7e, 0x0062de3e, 0x00140cd9, 0x8e9fbf00, 0xcf01c000, 0x99c700e9, 0x0090b34c, 0x0190b32e, 0x3e02f8f6, 0xcf006307, 0x99c700f9, 0x0090b34c, 0x0190b30e, 0x3e02f8f6, 0x8a00631b, 0xcf01c200, 0xa4f000aa, 0x9000f801, 0x008960ff, - 0x9ff601c1, 0x00f1df00, 0x99b88000, 0xf7020100, 0x9fcf009f, 0x3e9fb200, 0xf900631b, 0x0604d002, + 0x9ff601c1, 0x00f1df00, 0x99b88000, 0xf7020100, 0x9fcf009f, 0x3e9fb200, 0xf900631b, 0x0614d002, 0xa0330000, 0x0ba02400, 0x066f448a, 0x001a277e, 0xffc00049, 0x448ab4a9, 0xb5f1066f, 0x877e2000, - 0xb03e001a, 0x448a0063, 0x277e066f, 0x00d9001a, 0xbf000006, 0xc000499b, 0x8a94a9ff, 0xf1066f44, + 0xb03e001a, 0x448a0063, 0x277e066f, 0x10d9001a, 0xbf000006, 0xc000499b, 0x8a94a9ff, 0xf1066f44, 0xff3fffb4, 0x877eb59b, 0x4089001a, 0x09a00f42, 0x01fba43d, 0xa0b212f9, 0x448ab1b2, 0x277e066f, 0xa9b2001a, 0x0c0104b3, 0x01b0aae7, 0x0063da3e, 0x04b3ff0a, 0x9ae42300, 0xa9e43fff, 0x1bf42000, 0x3ef4bd09, 0x8f0063eb, 0x94fe0000, 0xa43d03a9, 0xa095f9ff, 0x8a11fb19, 0x7e066f40, 0xe4001a27, - 0xf12000a9, 0xb33fffa4, 0x89080090, 0xb6fe0000, 0x9aff03a4, 0xdf00f8a5, 0x00000608, 0xf9f430f4, - 0xfef0b232, 0x99900149, 0x019fb510, 0x0005dcdf, 0xbdffbf00, 0x3591a014, 0x01020191, 0x99909220, + 0xf12000a9, 0xb33fffa4, 0x89080090, 0xb6fe0000, 0x9aff03a4, 0xdf00f8a5, 0x00000618, 0xf9f430f4, + 0xfef0b232, 0x99900149, 0x019fb510, 0x0005ecdf, 0xbdffbf00, 0x3591a014, 0x01020191, 0x99909220, 0xa03c0308, 0xbd0ab29f, 0x7e3cb2b4, 0x09000b94, 0x08023505, 0x35030135, 0x01350103, 0x04023502, 0x008f0920, 0xf9cf01c0, 0x4c99c700, 0x610099b3, 0x0190b301, 0x3e02f8f5, 0xcf006466, 0x99c700f9, - 0x0099b34c, 0x90b30134, 0x02f8f501, 0x00647b3e, 0xfe00008f, 0xff0394b6, 0x08df95f9, 0xb5000006, + 0x0099b34c, 0x90b30134, 0x02f8f501, 0x00647b3e, 0xfe00008f, 0xff0394b6, 0x18df95f9, 0xb5000006, 0x008f03f9, 0xf9cf01c0, 0x4c99c700, 0xe80099b3, 0x0190b300, 0x3e02f8f5, 0xcf0064a6, 0x99c700f9, 0x0099b34c, 0x90b300b8, 0x02f8f501, 0x0064bb3e, 0xfe00008f, 0x00140cd9, 0x949dbf00, 0xf9ff03e9, - 0x0608df95, 0xf9b50000, 0xc0008f04, 0x00f9cf01, 0xb34c99c7, 0xb3660090, 0xf8f60190, 0x64ed3e02, + 0x0618df95, 0xf9b50000, 0xc0008f04, 0x00f9cf01, 0xb34c99c7, 0xb3660090, 0xf8f60190, 0x64ed3e02, 0x00f9cf00, 0xb34c99c7, 0xb30e0090, 0xf8f60190, 0x65013e02, 0xc2008f00, 0x00ffcf01, 0x001400d9, - 0xde9abf00, 0x00000608, 0xc711f9c7, 0xe93519ff, 0x14ef3515, 0x0c014bfe, 0x10bb9008, 0x00006e7e, - 0x900149fe, 0x9fbf1899, 0x0005dcd9, 0xa699bf00, 0xa10bf5f9, 0x65ee3e00, 0x60df9000, 0x01c10089, + 0xde9abf00, 0x00000618, 0xc711f9c7, 0xe93519ff, 0x14ef3515, 0x0c014bfe, 0x10bb9008, 0x00006e7e, + 0x900149fe, 0x9fbf1899, 0x0005ecd9, 0xa699bf00, 0xa10bf5f9, 0x65ee3e00, 0x60df9000, 0x01c10089, 0xdf009ff6, 0x800000f1, 0x010099b8, 0x009ff702, 0xb2009fcf, 0x65013e9f, 0xc2008900, 0x0099cf01, 0xe41095b6, 0xe420009f, 0xb33fff9e, 0xff4500fd, 0x0064d43e, 0x066f448f, 0x01c10089, 0xdf009ff6, 0x800000f1, 0x010099b8, 0x009ff702, 0xb2009fcf, 0x64bb3e9f, 0xc2008900, 0x0099cf01, 0x20009fe4, 0x3fff94f1, 0xcc00fdb3, 0x64943efe, 0x6f408f00, 0xc1008906, 0x009ff601, 0x0000f1df, 0x0099b880, 0x9ff70201, 0x009fcf00, 0x7b3e9fb2, 0x317e0064, 0x35fb003a, 0x64177e0c, 0x3cd97e00, 0xdf00f800, - 0x00000608, 0xf9f430f4, 0xfef0b242, 0x99900149, 0x019fb514, 0x0005dcdf, 0xbdffbf00, 0x3591a014, + 0x00000618, 0xf9f430f4, 0xfef0b242, 0x99900149, 0x019fb514, 0x0005ecdf, 0xbdffbf00, 0x3591a014, 0x01030191, 0x99909320, 0xa0a43208, 0xb23c029f, 0xb2b4bd0a, 0x0b947e2c, 0x35050900, 0x03350102, 0x08013504, 0x35090435, 0x01350201, 0x8f092003, 0xcf01c000, 0x99c700f9, 0x0099b34c, 0x90b30166, 0x02f8f501, 0x0066533e, 0xc700f9cf, 0x99b34c99, 0xb3013900, 0xf8f50190, 0x66683e02, 0x00008f00, - 0x0394b6fe, 0xdf95f9ff, 0x00000608, 0x8f03f9b5, 0xcf01c000, 0x99c700f9, 0x0099b34c, 0x90b300ed, + 0x0394b6fe, 0xdf95f9ff, 0x00000618, 0x8f03f9b5, 0xcf01c000, 0x99c700f9, 0x0099b34c, 0x90b300ed, 0x02f8f501, 0x0066933e, 0xc700f9cf, 0x99b34c99, 0xb300c000, 0xf8f50190, 0x66a83e02, 0x00008f00, - 0x0394b6fe, 0xdf95f9ff, 0x00000608, 0x3304f9b5, 0xd9370040, 0x0000140c, 0x008e9fbf, 0xe9cf01c0, + 0x0394b6fe, 0xdf95f9ff, 0x00000618, 0x3304f9b5, 0xd9370040, 0x0000140c, 0x008e9fbf, 0xe9cf01c0, 0x4c99c700, 0x6a0090b3, 0xf60190b3, 0xde3e02f8, 0xf9cf0066, 0x4c99c700, 0x3a0090b3, 0xf60190b3, 0xf23e02f8, 0x00d90066, 0xbf000014, 0x014bfe9a, 0xbb90080c, 0x006e7e14, 0x0149fe00, 0xbf1c9990, - 0x05dcd99f, 0x99bf0000, 0x0bf5f9a6, 0xe03e00ba, 0x00890067, 0x99cf01c2, 0x0608de00, 0x9fc70000, + 0x05ecd99f, 0x99bf0000, 0x0bf5f9a6, 0xe03e00ba, 0x00890067, 0x99cf01c2, 0x0618de00, 0x9fc70000, 0x1899c710, 0x3516ef35, 0x063e15e9, 0xff900067, 0xc1008960, 0x009ff601, 0x0000f1df, 0x0099b880, 0x9ff70201, 0x009fcf00, 0xf23e9fb2, 0x00890066, 0x99cf01c2, 0x009fe400, 0xff94f120, 0x00fdb33f, 0xc13eff40, 0x448f0066, 0x0089066f, 0x9ff601c1, 0x00f1df00, 0x99b88000, 0xf7020100, 0x9fcf009f, 0x3e9fb200, 0x890066a8, 0xcf01c200, 0x9fe40099, 0x94f12000, 0xfdb33fff, 0x3efec700, 0x8f006681, 0x89066f40, 0xf601c100, 0xf1df009f, 0xb8800000, 0x02010099, 0xcf009ff7, 0x9fb2009f, 0x0066683e, - 0x003a317e, 0xf90c45fb, 0x0604d902, 0x90bf0000, 0x003cdf7e, 0xf07e010a, 0x010a0024, 0x0065ff7e, + 0x003a317e, 0xf90c45fb, 0x0614d902, 0x90bf0000, 0x003cdf7e, 0xf07e010a, 0x010a0024, 0x0065ff7e, 0x0cb2010a, 0xabb2d43d, 0x003aa97e, 0x0600a033, 0x01fb02f8, 0x0062fc7e, 0x2600a433, 0xc4bdb4bd, 0x020ad43d, 0x003aa97e, 0xf07ea43d, 0xa43d0024, 0x0065ff7e, 0x00221d7e, 0x003ce57e, 0xf07e00f8, - 0x00f80024, 0xdfcc30f4, 0x000005dc, 0xffbf82f9, 0x900149fe, 0x48fe5499, 0xfe9fa001, 0x99920144, + 0x00f80024, 0xdfcc30f4, 0x000005ec, 0xffbf82f9, 0x900149fe, 0x48fe5499, 0xfe9fa001, 0x99920144, 0xfef4bd10, 0x46fe0147, 0x019fb501, 0x88909fa0, 0x4c449050, 0x90347790, 0x00d92466, 0xbf000014, 0x014bfe9a, 0xbb90080c, 0x7eff0d44, 0x320000c1, 0x00a433a5, 0x1200b4e9, 0x3433033f, 0x0918e005, 0x45203404, 0x0f009033, 0x9d33e301, 0x3e008701, 0x180068c3, 0x0b98050a, 0x635b7e02, 0x3ea13200, @@ -896,16 +896,16 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x3d001a87, 0xf401fba4, 0x62f9fc30, 0x900149fe, 0xa4321f99, 0x96b29c20, 0xb2c4d3b2, 0x7e080aff, 0xd9001a27, 0x40000000, 0x010504bd, 0x3e14a9ff, 0xbc006bdd, 0x5abca002, 0x6b617ea4, 0x0014b300, 0x3b8fda1d, 0x6bb20000, 0xa97e3cb2, 0xa4330015, 0x09f80c00, 0xe43e040a, 0x0090006b, 0xf4402601, - 0xa43dd40c, 0xf40465fb, 0xdcdff830, 0xf9000005, 0xfeffbf12, 0x99900149, 0xa0b1b20c, 0x8aabb29f, + 0xa43dd40c, 0xf40465fb, 0xecdff830, 0xf9000005, 0xfeffbf12, 0x99900149, 0xa0b1b20c, 0x8aabb29f, 0x7e08c040, 0xda001a87, 0x00006b48, 0x00dcb4bd, 0x7e01312d, 0x0e0015a9, 0x00a03304, 0x0140fe1f, 0xb2080090, 0x6aff7e0a, 0x33ae3200, 0xbf0d00a4, 0xf491a609, 0x3e0e050b, 0x900149fe, 0x9fbf0c99, - 0x0005dcd9, 0x3299bf00, 0xf4f9a6ea, 0x317e070b, 0x15fb003a, 0xb212f908, 0x8aa1b2b0, 0x7e08d100, + 0x0005ecd9, 0x3299bf00, 0xf4f9a6ea, 0x317e070b, 0x15fb003a, 0xb212f908, 0x8aa1b2b0, 0x7e08d100, 0x89001a27, 0xf1ff0000, 0xffffff04, 0x008ab4a9, 0x0bff08d1, 0x1a877eb5, 0xd1708a00, 0xff14f108, 0x0000db03, 0x14b6c000, 0xb51bff10, 0x001a877e, 0x08d1748a, 0x001a277e, 0x02010089, 0xf700a3f0, 0xa43d009a, 0x12f911fb, 0x08d1708a, 0xb032c132, 0x290000db, 0x1a877ec2, 0xd1748a00, 0x1a277e08, 0xf8a4f100, 0x0002dbff, 0xabffa229, 0xd1708ab5, 0x1a877e08, 0x0f14f000, 0x94ff04f0, 0x0994081f, 0xff94f10c, 0xd1708aff, 0x0404b608, 0x2a0000db, 0xff04f0a2, 0xfd0509fd, 0x0ffd0501, 0xb50bff05, - 0x001a877e, 0x11fba43d, 0xdfdc30f4, 0x000005dc, 0xffbf72f9, 0x900149fe, 0xa2324099, 0xb4329fa0, + 0x001a877e, 0x11fba43d, 0xdfdc30f4, 0x000005ec, 0xffbf72f9, 0x900149fe, 0xa2324099, 0xb4329fa0, 0xd632c532, 0xe4b3e3b2, 0x243d0a00, 0x006e433e, 0x143dff00, 0x0e32f4bd, 0xf0953fbc, 0x0bf40194, 0xf40e260d, 0xf032051b, 0x90011110, 0xf4b301ff, 0x1630ea10, 0x120cf410, 0xc4ff1fc4, 0xf9bcff09, 0x1076b070, 0xf80b0df4, 0x3e020209, 0xb2006e43, 0x6b617e3a, 0x325c3200, 0x324b326d, 0x6ca67e2a, @@ -915,16 +915,16 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x006b617e, 0x08d1148a, 0x001a277e, 0xfebf7f49, 0xa9ff0143, 0x8a0132b4, 0x9008d114, 0x877e2033, 0x0104001a, 0x006e253e, 0x7ea440bc, 0x8a006b61, 0x7e08d114, 0xbc001a27, 0xa5b69000, 0x9039bc10, 0x60011110, 0xff10c49a, 0x1ef407a6, 0x12b0b4de, 0xb213c0b4, 0x0ed4bd3a, 0x21367e20, 0x00a03300, - 0xfe02f806, 0x99900149, 0xd99fbf40, 0x000005dc, 0x2a3299bf, 0x0bf4f9a6, 0x3a317e07, 0x2475fb00, - 0xd9e830f4, 0x000005dc, 0x99bf52f9, 0x90014ffe, 0xa2b22cff, 0xc08af9a0, 0x277e08b8, 0xa5b2001a, + 0xfe02f806, 0x99900149, 0xd99fbf40, 0x000005ec, 0x2a3299bf, 0x0bf4f9a6, 0x3a317e07, 0x2475fb00, + 0xd9e830f4, 0x000005ec, 0x99bf52f9, 0x90014ffe, 0xa2b22cff, 0xc08af9a0, 0x277e08b8, 0xa5b2001a, 0x08b8c08a, 0x7e045bc5, 0xda001a87, 0x00006b38, 0x408cb4bd, 0x0400030d, 0x0015a97e, 0xa800a933, 0xc0408a00, 0x1a277e08, 0x0141fe00, 0x11902bb2, 0xb21aa028, 0x69607e1a, 0x33a03200, 0x008900ad, 0xf00f19bf, 0x4afe13b2, 0x049ffd01, 0x900195f0, 0x19a018aa, 0x7fd1a4b2, 0x7e02faf0, 0xbf001581, 0x7e2bb23a, 0x32006be7, 0x3ea433a0, 0x7e4ab221, 0xa600159c, 0xea0df4a1, 0x2bb23abf, 0x006be77e, 0xdf3ea433, 0x0e3e0400, 0xa033006f, 0x49fe3a00, 0x28999001, 0x41fe99bf, 0x0142fe01, 0x90241190, 0x19a02022, 0xff7e2ab2, 0xa433006a, 0x2bbf1a00, 0x607e1ab2, 0xa4330069, 0x1bbf0e00, 0x08c0408a, - 0x001a877e, 0x08b8c08a, 0x877e5bb2, 0x49fe001a, 0x2c999001, 0xdcd99fbf, 0xbf000005, 0xa60a3299, - 0x070bf4f9, 0x003a317e, 0xf41855fb, 0xdcdfdc30, 0xf9000005, 0xf4ffbf82, 0x49fef830, 0x4c999001, + 0x001a877e, 0x08b8c08a, 0x877e5bb2, 0x49fe001a, 0x2c999001, 0xecd99fbf, 0xbf000005, 0xa60a3299, + 0x070bf4f9, 0x003a317e, 0xf41855fb, 0xecdfdc30, 0xf9000005, 0xf4ffbf82, 0x49fef830, 0x4c999001, 0x40fe9fa0, 0x0c999201, 0x0090f4bd, 0x0142fe2c, 0x9fb593b2, 0xd89fa001, 0x00001420, 0x07482290, 0x90040602, 0x8abf0c05, 0x080c3bb2, 0xc17eff0d, 0xa4330000, 0x3198f400, 0x33193f01, 0x98eb0a94, 0x1f180119, 0x01341804, 0x199009a0, 0x019e9804, 0x98010eb5, 0x0eb5029e, 0x039e9802, 0x98030eb5, @@ -932,14 +932,14 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x020c1803, 0x7e040d18, 0x3e006ca6, 0x98007046, 0x0b98010a, 0x6c557e02, 0x70463e00, 0x010a9800, 0x006e607e, 0x0070463e, 0x0a1859bf, 0x030b1801, 0x18020c18, 0x0e98040d, 0x0091b002, 0xb0015998, 0x087e0191, 0xad33006d, 0x35ff6000, 0x2720022a, 0x32031e18, 0x351ab24b, 0x2e350126, 0x0f817e03, - 0xbd2ab200, 0x0f717eb4, 0x6fa63e00, 0x05d4d900, 0x9abf0000, 0x001410db, 0x7e010c00, 0x7e005e25, + 0xbd2ab200, 0x0f717eb4, 0x6fa63e00, 0x05e4d900, 0x9abf0000, 0x001410db, 0x7e010c00, 0x7e005e25, 0xf800709e, 0x1430d900, 0x9fbf0000, 0x8dda943d, 0x2000002e, 0x02f998a9, 0xa43d95f9, 0xa17e00f8, 0xaa7e003c, 0x00f8003b, 0xf9f830f4, 0xf4a1b222, 0xb2b2fc30, 0x900140fe, 0x0ca01000, 0x7e010db5, 0x09003da3, 0x00a033ff, 0x0109981e, 0x002944da, 0xb21cb200, 0x0091b02d, 0xab980ebf, 0x42ea7e07, - 0x32a93200, 0x0430f49a, 0xdf0825fb, 0x000005dc, 0x30f4ffbf, 0x0149fef0, 0xa00c9990, 0x2944d99f, + 0x32a93200, 0x0430f49a, 0xdf0825fb, 0x000005ec, 0x30f4ffbf, 0x0149fef0, 0xa00c9990, 0x2944d99f, 0x9f980000, 0x0149fe07, 0x9bb59aa0, 0x98febf01, 0x999001ff, 0xbdbcb208, 0x02febbd4, 0x9fa0abb2, - 0x040e9ab2, 0x0021367e, 0x0800a033, 0x010a02f8, 0x900149fe, 0x9fbf0c99, 0x0005dcd9, 0xa699bf00, - 0x070bf4f9, 0x003a317e, 0xf81030f4, 0xc030f400, 0x0005dcd9, 0xbf82f900, 0x014ffe99, 0xfe60ff90, + 0x040e9ab2, 0x0021367e, 0x0800a033, 0x010a02f8, 0x900149fe, 0x9fbf0c99, 0x0005ecd9, 0xa699bf00, + 0x070bf4f9, 0x003a317e, 0xf81030f4, 0xc030f400, 0x0005ecd9, 0xbf82f900, 0x014ffe99, 0xfe60ff90, 0xf9a00146, 0x669094bd, 0x1691b02c, 0xfe1591b0, 0x48fe0144, 0x04699001, 0x90404490, 0x91b05c88, 0x72cb3e09, 0x1650b400, 0x9d33593f, 0x9801410b, 0x5f18015e, 0x04599004, 0xe0344ea0, 0x2be13055, 0xb5019e98, 0x9e98014e, 0x024eb502, 0xb5039e98, 0x9998034e, 0x0449b504, 0x2d01f033, 0xf401f630, @@ -956,16 +956,16 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x19bf0000, 0x9ab8a2b2, 0x7e0004e8, 0xb2001a27, 0xf01abfa0, 0xaab80104, 0x7e0004e0, 0x09001a27, 0x0004b301, 0x18a9c707, 0x21fb2920, 0x0cd902f9, 0xbf000014, 0xb8a0b299, 0x0005109a, 0x001a277e, 0xa0f3aac7, 0xf901fb0a, 0x140cd922, 0x99bf0000, 0xb1b2a0b2, 0x9ab8c2b2, 0x7e000510, 0xc7001a27, - 0x096049a9, 0x6046a9c7, 0x81aac719, 0x21fb2a60, 0xf9ec30f4, 0x140cd142, 0x19bf0000, 0xdcd3a4b2, + 0x096049a9, 0x6046a9c7, 0x81aac719, 0x21fb2a60, 0xf9ec30f4, 0x140cd142, 0x19bf0000, 0xecd3a4b2, 0xfe000005, 0x9ab80142, 0xbf000500, 0x24229039, 0x900140fe, 0x29a01400, 0x001a277e, 0x0aa019bf, 0x05049ab8, 0x1a277e00, 0xb519bf00, 0x9ab8010a, 0x7e000508, 0xbf001a27, 0x020ab519, 0x050c9ab8, 0x1a277e00, 0xb50bb200, 0x100c030a, 0x7e7e4ab2, 0x2fbf000b, 0xf9a639bf, 0x7e070bf4, 0xfb003a31, - 0x30f41445, 0x05dcdff0, 0x22f90000, 0x00140cd0, 0xbfffbf00, 0x0149fe0e, 0xb2189990, 0xb89fa0a2, + 0x30f41445, 0x05ecdff0, 0x22f90000, 0x00140cd0, 0xbfffbf00, 0x0149fe0e, 0xb2189990, 0xb89fa0a2, 0x0004f8ea, 0x001a277e, 0x0abfa9b2, 0x94189e95, 0x9f94089d, 0x0895b618, 0xff0094f1, 0xfd05fefd, 0x00d905f9, 0xfd00ff00, 0xfdfd04d9, 0x0141fe05, 0x04fcaab8, 0x0c119000, 0xa00140fe, 0x1400901f, 0x277e0fa0, 0x2eb2001a, 0xbd011ab5, 0x00a1dbd4, 0x2e010000, 0x35f80d3c, 0xdd9002e1, 0x00a1dc01, 0xf9c40000, 0x64ffc70f, 0x3c98b93c, 0xe935f8bf, 0x90ef2001, 0xd4b303ee, 0xa9c4de04, 0x98c93c0f, - 0xc70d2935, 0xc93c64a9, 0x0c293598, 0x900149fe, 0x9fbf1899, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, + 0xc70d2935, 0xc93c64a9, 0x0c293598, 0x900149fe, 0x9fbf1899, 0x0005ecd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xf91025fb, 0x29ccdb02, 0xcedc0000, 0xdd000029, 0x000029d0, 0x0029cada, 0x69c67e00, 0x299cd000, 0x09980000, 0x29bcda01, 0x95f10000, 0x09b51e00, 0x73e27e01, 0x01099800, 0x0029d2da, 0x0095f100, 0x0109b501, 0x0073707e, 0xf1010998, 0xb5200095, 0x01fb0109, 0x00299cdd, 0x98dcbf00, @@ -978,25 +978,25 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x0660e08a, 0x001a277e, 0x00b31aa0, 0xe48a0e00, 0x277e0660, 0x0aa0001a, 0x480020b3, 0x0660e88a, 0x001a277e, 0x203e2aa0, 0x020a0076, 0x3601d433, 0x0e00b0b3, 0xe48abbbf, 0x877e0660, 0x20b3001a, 0x2bbf0e00, 0x0660e88a, 0x001a877e, 0x140010b3, 0x5c7e1ab2, 0x1bbf008c, 0x0660e08a, 0x001a877e, - 0x21fba43d, 0x0005dcdf, 0xf4ffbf00, 0x49fef430, 0x08999001, 0x008f9fa0, 0xf9cf01c0, 0x4c99c700, + 0x21fba43d, 0x0005ecdf, 0xf4ffbf00, 0x49fef430, 0x08999001, 0x008f9fa0, 0xf9cf01c0, 0x4c99c700, 0x4c0099b3, 0x0190b301, 0x3e02f8f5, 0xcf00763a, 0x99c700f9, 0x0099b34c, 0x90b30125, 0x02f8f501, 0x00764f3e, 0xffffffd9, 0xc4f9ff7f, 0x01c0008f, 0xc700f9cf, 0x99b34c99, 0xb300db00, 0xf8f50190, 0x76703e02, 0x00f9cf00, 0xb34c99c7, 0xb30e0090, 0xf8f60190, 0x76853e02, 0xc0008f00, 0x00f9cf01, 0xb34c99c7, 0x008d0099, 0xf50190b3, 0x9d3e02f8, 0xf9cf0076, 0x4c9dc700, 0x5e00d0b3, 0xf601d0b3, - 0xb23e02f8, 0xf9100076, 0x48e93501, 0xe100fd33, 0x0648d900, 0x4ffe0000, 0x01f9b501, 0x002e7cd9, - 0xa09abf00, 0x204809fd, 0xde0909f9, 0x00000648, 0x0409e920, 0x3502ecb5, 0x4bfe01fd, 0x03ed3501, + 0xb23e02f8, 0xf9100076, 0x48e93501, 0xe100fd33, 0x0658d900, 0x4ffe0000, 0x01f9b501, 0x002e7cd9, + 0xa09abf00, 0x204809fd, 0xde0909f9, 0x00000658, 0x0409e920, 0x3502ecb5, 0x4bfe01fd, 0x03ed3501, 0x3502ed35, 0x080c01e9, 0x00006e7e, 0x0077ad3e, 0xad3e09f8, 0x00890077, 0x99cf01c2, 0x299cde00, 0xef180000, 0x26ff0948, 0x9d1bf4f9, 0x0077ad3e, 0x0660e08f, 0x01c10089, 0xdf009ff6, 0x800000f1, 0x010099b8, 0x009ff702, 0xb2009fcf, 0x76b23e9f, 0x60e08f00, 0xc1008906, 0x009ff601, 0x010099b8, 0x009cf600, 0x0000f2df, 0x0099b880, 0x9ff60202, 0x009fcf00, 0x853e9fb2, 0x00890076, 0x9fcf01c2, 0x1ff99500, 0x8c0194b3, 0x0076643e, 0x0660e08f, 0x01c10089, 0xdf009ff6, 0x800000f1, 0x010099b8, - 0x009ff702, 0xb2009fcf, 0x764f3e9f, 0x0149fe00, 0xbf089990, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, - 0x3a317e07, 0x0c30f400, 0x30f400f8, 0x05dcdff4, 0x22f90000, 0x49feffbf, 0x14999001, 0x9fa0c1b2, + 0x009ff702, 0xb2009fcf, 0x764f3e9f, 0x0149fe00, 0xbf089990, 0x05ecd99f, 0x99bf0000, 0x0bf4f9a6, + 0x3a317e07, 0x0c30f400, 0x30f400f8, 0x05ecdff4, 0x22f90000, 0x49feffbf, 0x14999001, 0x9fa0c1b2, 0x00299cd9, 0x019f9800, 0x00d9d2b2, 0x0e400000, 0x04f9fd08, 0x33750bf4, 0x0e1000a0, 0x01a43303, 0x3ea0326c, 0x3d007809, 0x33040e04, 0x7e5e00b4, 0x33008a7a, 0x4b2400a0, 0x04330080, 0x884b0700, - 0x014afe00, 0xaa90080c, 0x8b2e7e0c, 0x33060e00, 0x3e3a00a4, 0xd9007883, 0x00000644, 0x080e99bf, + 0x014afe00, 0xaa90080c, 0x8b2e7e0c, 0x33060e00, 0x3e3a00a4, 0xd9007883, 0x00000654, 0x080e99bf, 0x290090b3, 0x90014ffe, 0x00330cff, 0x9e981000, 0x98fea020, 0x623e2199, 0x9e980078, 0x98fea022, - 0xf9b52399, 0x78833e01, 0x0149fe00, 0xbf149990, 0x05dcd99f, 0x99bf0000, 0xf9a6ea32, 0x3e200bf4, + 0xf9b52399, 0x78833e01, 0x0149fe00, 0xbf149990, 0x05ecd99f, 0x99bf0000, 0xf9a6ea32, 0x3e200bf4, 0xfe007898, 0x99900149, 0x0e9fbf0c, 0x981fa01f, 0x29a00199, 0x0078693e, 0x003a317e, 0x090c25fb, 0x0aa9a024, 0xd900f81f, 0x0000299c, 0xf9e830f4, 0x2d9f9882, 0x98289298, 0x90982b91, 0x0df1b029, 0x980bc1b0, 0xd1b02a9f, 0x09e1b00a, 0xbf2e9998, 0x64f2ffcc, 0xb07410ff, 0xc1b00e91, 0x0da0330c, @@ -1017,37 +1017,37 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x7aa73e1f, 0x32060900, 0x1885fb9a, 0x010000d9, 0xffa4f001, 0xb6ffb4f0, 0xb4b614a4, 0xa0a9bc0f, 0xabbc22f9, 0xb2c0b220, 0x242ab8d1, 0x277e0020, 0x0309001a, 0xb364aac7, 0x090c00a0, 0x04a0b301, 0x20943d06, 0x142ab809, 0x277e0030, 0x0309001a, 0xb364aac7, 0x090c00a0, 0x04a0b301, 0x20943d06, - 0xf421fb19, 0xdcdff030, 0xf9000005, 0xf4ffbf32, 0x49fefc30, 0x20999001, 0x41fe9fa0, 0x9094bd01, + 0xf421fb19, 0xecdff030, 0xf9000005, 0xf4ffbf32, 0x49fefc30, 0x20999001, 0x41fe9fa0, 0x9094bd01, 0x4efe1c11, 0x9019a001, 0xe9a018ee, 0xd3b2c2b2, 0xb926ff09, 0xfe201bf4, 0x240b0140, 0xb2140090, 0x87d77e0c, 0xffa4f000, 0x3c1fa4b3, 0x10a000bf, 0x007b6e3e, 0xf000e1b0, 0xb4f0ffa4, 0x0c1eb2ff, 0x7e240d05, 0xf0008850, 0xa4b3ffa4, 0x49fe1a1f, 0x1c999001, 0x1f0a99bf, 0x49fe29a0, 0x18999001, - 0x39a099bf, 0x900149fe, 0x9fbf2099, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xfb0430f4, - 0x30f41035, 0x05dcdff0, 0x32f90000, 0x30f4ffbf, 0x0149fefc, 0xa0209990, 0x0141fe9f, 0x119094bd, + 0x39a099bf, 0x900149fe, 0x9fbf2099, 0x0005ecd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xfb0430f4, + 0x30f41035, 0x05ecdff0, 0x32f90000, 0x30f4ffbf, 0x0149fefc, 0xa0209990, 0x0141fe9f, 0x119094bd, 0x014efe18, 0xee9019a0, 0xb2e9a014, 0x09d3b2c2, 0xf4b926ff, 0x40fe1d1b, 0x90240b01, 0x0cb21c00, 0x0087d77e, 0x391fa433, 0x10a000bf, 0x007c073e, 0xf000e1b0, 0xb4f0ffa4, 0x0c1eb2ff, 0x7e240d08, 0x33008850, 0xfe1a1fa4, 0x99900149, 0x0a99bf18, 0xfe29a01f, 0x99900149, 0xa099bf14, 0x0149fe39, - 0xbf209990, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x3a317e07, 0x0430f400, 0xf41035fb, 0xdcdff430, + 0xbf209990, 0x05ecd99f, 0x99bf0000, 0x0bf4f9a6, 0x3a317e07, 0x0430f400, 0xf41035fb, 0xecdff430, 0xf9000005, 0xf4ffbf22, 0x49fefc30, 0x18999001, 0x4efe9fa0, 0x9094bd01, 0x40fe14ee, 0x90e9a001, 0x09a01000, 0xd2b2c1b2, 0xb926ff09, 0xb20f1bf4, 0x7e240bec, 0x3e0087d7, 0xb0007c8c, 0xa4f00001, 0xffb4f0ff, 0x240d010c, 0x0088507e, 0x201fa433, 0x900149fe, 0x99bf1499, 0x90014ffe, 0xffbf10ff, - 0x038199e7, 0xffe719a0, 0x2fa00381, 0x900149fe, 0x9fbf1899, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, - 0x003a317e, 0xfb0430f4, 0x30f40c25, 0x05dcdff4, 0x22f90000, 0x30f4ffbf, 0x0149fefc, 0xa0189990, + 0x038199e7, 0xffe719a0, 0x2fa00381, 0x900149fe, 0x9fbf1899, 0x0005ecd9, 0xa699bf00, 0x070bf4f9, + 0x003a317e, 0xfb0430f4, 0x30f40c25, 0x05ecdff4, 0x22f90000, 0x30f4ffbf, 0x0149fefc, 0xa0189990, 0x014efe9f, 0xee9094bd, 0x0140fe14, 0x0090e9a0, 0xb209a010, 0x09d2b2c1, 0xf4b926ff, 0xecb20f1b, 0xd77e240b, 0x1b3e0087, 0x01b0007d, 0xffa4f000, 0x0cffb4f0, 0x7e240d20, 0x33008850, 0xfe181fa4, - 0x99900149, 0xa099bf14, 0x0149fe19, 0xbf109990, 0xfe29a099, 0x99900149, 0xd99fbf18, 0x000005dc, - 0xf9a699bf, 0x7e070bf4, 0xf4003a31, 0x25fb0430, 0xf430f40c, 0x0005dcdf, 0xbf52f900, 0x0149feff, + 0x99900149, 0xa099bf14, 0x0149fe19, 0xbf109990, 0xfe29a099, 0x99900149, 0xd99fbf18, 0x000005ec, + 0xf9a699bf, 0x7e070bf4, 0xf4003a31, 0x25fb0430, 0xf430f40c, 0x0005ecdf, 0xbf52f900, 0x0149feff, 0x32209990, 0xb29fa0b0, 0xb00405c4, 0x0cf523a6, 0x34bd00bb, 0xfe0142fe, 0x22900141, 0x1c119018, 0x13a023a0, 0x2cb21bb2, 0x0084407e, 0xad33a532, 0xbf009b1f, 0x7e2bbf1a, 0x330084fc, 0xa00a00a4, 0x7e293e43, 0xbf2fbf00, 0x0ff4b619, 0xbc1494b6, 0x00df90f9, 0xbc010100, 0x0033909f, 0x06302e04, 0x0b0cf404, 0x65030433, 0x007dd83e, 0x2d050033, 0x59060433, 0x007e093e, 0x22889ab8, 0x1a277e00, 0x10a5b600, 0x007df33e, 0x7e8c9a90, 0xf1001a27, 0xa003ffa4, 0x7e293e4a, 0x889ab800, 0x277e0032, 0xa3f0001a, 0x7df33e00, 0x8c9ab800, 0x277e0032, 0xae95001a, 0xe8a9c718, 0xf0f0afc7, 0x9fbcffa4, - 0x909abc90, 0xa0909ebc, 0x0149fe49, 0xbf209990, 0x05dcd99f, 0x99bf0000, 0xf9a65a32, 0x7e070bf4, - 0xfb003a31, 0x30f40c55, 0x05dcdff4, 0x42f90000, 0x49feffbf, 0x1c999001, 0xa0014efe, 0x18ee909f, + 0x909abc90, 0xa0909ebc, 0x0149fe49, 0xbf209990, 0x05ecd99f, 0x99bf0000, 0xf9a65a32, 0x7e070bf4, + 0xfb003a31, 0x30f40c55, 0x05ecdff4, 0x42f90000, 0x49feffbf, 0x1c999001, 0xa0014efe, 0x18ee909f, 0x4ffe94bd, 0x90e9a001, 0xf9a014ff, 0xc4b2a132, 0xb926ff09, 0xb22b1bf4, 0xbdf2b2e3, 0x320ab204, 0x7e3cb21b, 0x33007d51, 0xbf311fa4, 0x9039bf2f, 0x9fbc0100, 0xb329a090, 0x3ee62404, 0xc4007eae, 0xfcb2ffba, 0x517e1b32, 0xa433007d, 0x49fe0e1f, 0x14999001, 0x49a099bf, 0x900149fe, 0x9fbf1c99, - 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xf40c45fb, 0xdcdfb830, 0xf9000005, 0xfeffbf82, + 0x0005ecd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xf40c45fb, 0xecdfb830, 0xf9000005, 0xfeffbf82, 0x99900149, 0xa0010568, 0x11c1b09f, 0xb049b130, 0xe1b010d1, 0x33c4bf0f, 0x30180aa0, 0x08f40aa6, 0x3302050f, 0x050c0ba0, 0x0ca03303, 0xbd543d06, 0x014ffe94, 0xff9064bd, 0xb504bd60, 0xf9a001f9, 0xff9274bd, 0xb2f92008, 0xb20ab2f1, 0x860e7e1b, 0x1fad3300, 0x193f0480, 0x1c009033, 0xb4bd010a, @@ -1062,10 +1062,10 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0xe9b5049b, 0x17f99801, 0xb5049cfd, 0xd99817f9, 0x049bfd01, 0x3e01d9b5, 0xf00083b1, 0x9cdbff54, 0xb2000029, 0x0394b659, 0x98909bbc, 0x9998209f, 0x1451b01f, 0xfd04f1fd, 0x90a60490, 0xa6081bf4, 0x100bf4f1, 0x44bd010e, 0xbd4ae130, 0x80db3e54, 0xb244bd00, 0xbd0cb21d, 0x3eb43d54, 0xc40080d0, - 0x0bf401c9, 0x14f0b425, 0x0006a4de, 0xffb9c400, 0xbc0394b6, 0x94b6909f, 0x909ebc03, 0x9f989ebf, + 0x0bf401c9, 0x14f0b425, 0x0006b4de, 0xffb9c400, 0xbc0394b6, 0x94b6909f, 0x909ebc03, 0x9f989ebf, 0x404ebc01, 0x10515fbc, 0xdd9501bb, 0x01cc9d01, 0xf495cdff, 0xf43dcc1b, 0xb44af130, 0x9cdb1490, 0xb6000029, 0x9bbc0394, 0x189f9890, 0xfd179998, 0x90fd04f1, 0xf490a604, 0xf1a6091b, 0x01200bf5, - 0xe43d94bd, 0xb01791b0, 0xe1301691, 0x81dc3e4b, 0x0169c400, 0x00b90bf5, 0x344b9034, 0x84df4bc0, + 0xe43d94bd, 0xb01791b0, 0xe1301691, 0x81dc3e4b, 0x0169c400, 0x00b90bf5, 0x344b9034, 0x94df4bc0, 0x0a000006, 0xff94f001, 0x9894b4bd, 0xffc4f006, 0x7e808fbc, 0xd20039cd, 0x000029f8, 0xb000b9b9, 0xa1b00db1, 0x00abb90e, 0xb00b91b0, 0x8db20cb1, 0xa034343d, 0x09d1b04b, 0x4cfe3b32, 0x58cc9001, 0x0089ca7e, 0x2c9829bf, 0x09d0b401, 0x351fa033, 0xdea0e4bd, 0xb401deb5, 0x2f980cb0, 0x092e9808, @@ -1075,7 +1075,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x34ff321b, 0xff0949f0, 0x0bf4f926, 0x1490b429, 0x00299cdb, 0x0394b600, 0x98909bbc, 0x9998189f, 0x04f1fd17, 0xa60490fd, 0xd71bf590, 0xf5f1a601, 0xb401d11b, 0xe5f013e0, 0x13e1b004, 0x900149fe, 0x96bf6099, 0xb4019798, 0x9cdf1490, 0x3d000029, 0xb624bde4, 0x34bd0394, 0x30909fbc, 0x9b9057e1, - 0x5c98907c, 0x3e0ab1b0, 0xc40082cf, 0x0bf40109, 0x14f0b472, 0xde579034, 0x00000684, 0x0006a4db, + 0x5c98907c, 0x3e0ab1b0, 0xc40082cf, 0x0bf40109, 0x14f0b472, 0xde579034, 0x00000694, 0x0006b4db, 0xf0010a00, 0x94b6ff94, 0x909fbc03, 0xb6039f94, 0xfbbc0394, 0x909ebcf0, 0x979896bf, 0x01f7b501, 0xc034f6a0, 0xbcb4bd57, 0x37bc2026, 0xffc4f031, 0x0039cd7e, 0xbf018f98, 0x00b9b98e, 0xb904f9fd, 0x8fb500a9, 0x04e9fd01, 0xf0b48ea0, 0x98f9bf0a, 0x9afd01ff, 0x05fbfd05, 0xa00ab0b4, 0x01bfb5b9, @@ -1086,7 +1086,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0xa60ffffe, 0x190df4c9, 0x950aaf95, 0xb9940abd, 0x059ffd16, 0x9eb2dfb2, 0xfdb2ecb2, 0xb0b4030f, 0x03f4f013, 0xb9fffc09, 0xe5f9ff94, 0x0d00d4b3, 0x0fffff89, 0x0df4c9a6, 0x08e9c50a, 0x0083a03e, 0xb694c9ff, 0x0fdf0494, 0xffff0000, 0xf9fdf4ef, 0xfff70905, 0xa03e94f9, 0x90b40083, 0x0895f013, - 0x0a10e0b4, 0xb4e2a01f, 0xf3a00ff0, 0xa011b0b4, 0x0149feb9, 0xbf689990, 0x05dcd99f, 0x99bf0000, + 0x0a10e0b4, 0xb4e2a01f, 0xf3a00ff0, 0xa011b0b4, 0x0149feb9, 0xbf689990, 0x05ecd99f, 0x99bf0000, 0x0bf4f9a6, 0x83e63e28, 0x49e03400, 0x73b262b2, 0xe926ff09, 0xfb8b1bf5, 0x71b260b2, 0x007f7d3e, 0xb13e090a, 0x317e0083, 0x85fb003a, 0xc0008f48, 0x00f9cf01, 0xb34c99c7, 0xb3220090, 0xf8f60190, 0x83f13e02, 0x00f9cf00, 0xb34c99c7, 0xb3330090, 0xf8f60190, 0x84053e02, 0xc1008900, 0x009af601, @@ -1099,16 +1099,16 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x05f9bbff, 0xbb94f0ff, 0x9ebb04fe, 0x00ffb904, 0xfd04fdfd, 0xcfa005f9, 0x01fb1f0a, 0xb1b212f9, 0xeb7ea0b2, 0xa033003c, 0xa43d0a00, 0x00853e3e, 0xdf0f1994, 0x01017000, 0xbc1404b6, 0x09bc000f, 0x000ab800, 0x277e0006, 0xa1b2001a, 0x03800ab8, 0x1a277e00, 0x05a1fd00, 0xf001a6f0, 0x11fb01a4, - 0xdff430f4, 0x000005dc, 0xffbf32f9, 0x900149fe, 0xb2b21899, 0x06039fa0, 0xf523a6b0, 0xfe00960c, + 0xdff430f4, 0x000005ec, 0xffbf32f9, 0x900149fe, 0xb2b21899, 0x06039fa0, 0xf523a6b0, 0xfe00960c, 0x40fe0141, 0x14119001, 0xb2100090, 0x7e0cb21b, 0x32008440, 0x1fa433a3, 0xbf1abf7c, 0x84fc7e0b, 0x00a03300, 0xbf19bf5a, 0x1494b60a, 0xbc0fa4b6, 0x00d9a0a9, 0xbc010100, 0x277ea0a9, 0xa4f0001a, 0x04a0b3ff, 0x04a6b04c, 0xb0130cf4, 0x0cf402a6, 0x01a6b039, 0x3e2d18f4, 0xb30085db, 0xb02c08a0, 0x0cf408a6, 0x05a4b30b, 0x85db3e10, 0x0aa0b300, 0x0ba0b31a, 0x3e060310, 0xbd0085f1, 0x85ef3e94, - 0x3e010900, 0x090085ef, 0x85ef3e02, 0xa0030900, 0x0149fe29, 0xbf189990, 0x05dcd99f, 0x99bf0000, - 0xf9a63a32, 0x7e070bf4, 0xfb003a31, 0x30f40c35, 0x05dcd9f8, 0x12f90000, 0x4ffe99bf, 0x0cff9001, + 0x3e010900, 0x090085ef, 0x85ef3e02, 0xa0030900, 0x0149fe29, 0xbf189990, 0x05ecd99f, 0x99bf0000, + 0xf9a63a32, 0x7e070bf4, 0xfb003a31, 0x30f40c35, 0x05ecd9f8, 0x12f90000, 0x4ffe99bf, 0x0cff9001, 0xf9a0b1b2, 0x40feff09, 0x08009001, 0x0bb209a0, 0x0085407e, 0x0e1fa433, 0x96b009bf, 0x0b9cf002, - 0x49fe1920, 0x0c999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x15fb003a, 0xe830f408, - 0x0005dcdf, 0xbf42f900, 0x0149feff, 0xb2289990, 0xb29fa0b0, 0x02a033c3, 0x02a63045, 0x330c0cf4, + 0x49fe1920, 0x0c999001, 0xecd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x15fb003a, 0xe830f408, + 0x0005ecdf, 0xbf42f900, 0x0149feff, 0xb2289990, 0xb29fa0b0, 0x02a033c3, 0x02a63045, 0x330c0cf4, 0x00a601ad, 0x0086963e, 0xb407a933, 0x08ad3300, 0x4a3e0098, 0xbab20087, 0x900140fe, 0x0bb22700, 0x00860e7e, 0xad33a232, 0x3f01141f, 0x00963009, 0xf00b9cf0, 0xb83e0196, 0x04020087, 0xf523b630, 0xc400fb0c, 0x44feffba, 0x0141fe01, 0x90204490, 0x4bb21c11, 0x407e1cb2, 0xa2320084, 0xde1fad33, @@ -1119,51 +1119,51 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0xb21bb214, 0x84407e4c, 0x33a23200, 0xc44f1fa4, 0x40feff0a, 0x20009001, 0x0e7e0bb2, 0xa2320086, 0x3a1fa433, 0x9433093f, 0x3f090a00, 0x0087b83e, 0x4b3f1a3f, 0xfe0141fe, 0x11900140, 0x1c009027, 0x0db21cb2, 0x007aac7e, 0x1f3f093f, 0xf00794f0, 0x94b607f4, 0x059ffd03, 0x49fe39a0, 0x28999001, - 0xdcd99fbf, 0xbf000005, 0xa62a3299, 0x070bf4f9, 0x003a317e, 0xf41845fb, 0xdcdff830, 0xf9000005, + 0xecd99fbf, 0xbf000005, 0xa62a3299, 0x070bf4f9, 0x003a317e, 0xf41845fb, 0xecdff830, 0xf9000005, 0xfeffbf62, 0xff010149, 0xfe209990, 0xa5320142, 0xc4b2b3b2, 0x04bd9fa0, 0xb21c2290, 0x882a3e16, 0xb25a3200, 0x7e2cb20b, 0x3300865d, 0xbf2a1fa4, 0xf416a629, 0x91b2091b, 0x0088273e, 0x0bf419a6, - 0x3e090a09, 0x90008835, 0x03a60100, 0xbfd508f4, 0xa01f0a22, 0x0149fe42, 0xbf209990, 0x05dcd99f, - 0x99bf0000, 0x0bf4f9a6, 0x3a317e07, 0x0865fb00, 0xdff830f4, 0x000005dc, 0xffbf82f9, 0x900149fe, + 0x3e090a09, 0x90008835, 0x03a60100, 0xbfd508f4, 0xa01f0a22, 0x0149fe42, 0xbf209990, 0x05ecd99f, + 0x99bf0000, 0x0bf4f9a6, 0x3a317e07, 0x0865fb00, 0xdff830f4, 0x000005ec, 0xffbf82f9, 0x900149fe, 0xc2b22899, 0xd5b2b0b2, 0x9fa0cbb2, 0xa4b2e7b2, 0x7ea000bc, 0xb20016fc, 0xbca3b25b, 0x0ab2c022, 0x7e6032bc, 0x01008458, 0x0c80b404, 0x7500a033, 0x43fe30b2, 0x24339001, 0x0088bb3e, 0x0bb24a32, 0x5d7e3cb2, 0xa1320086, 0x591fa433, 0x0bb23cbf, 0x00904ab2, 0x7e7db201, 0xa600846b, 0x4218f405, 0x08f406a6, 0x88f13eda, 0xb24a3200, 0x7e3cb20b, 0x3200865d, 0x1fa433a1, 0xb23cbf2c, 0x904ab20b, 0x8db20100, 0x00846b7e, 0x08f405a6, 0x89013e10, 0x0143fe00, 0x902062bc, 0x02a62433, 0x01cd08f4, - 0x0149fe1f, 0xbf289990, 0x05dcd99f, 0x99bf0000, 0xf9a61a32, 0x7e070bf4, 0xfb003a31, 0x30f40885, - 0x05dcdff4, 0x62f90000, 0x94bdffbf, 0xfe0141fe, 0x11900140, 0x1c009020, 0x09a019a0, 0x900149fe, + 0x0149fe1f, 0xbf289990, 0x05ecd99f, 0x99bf0000, 0xf9a61a32, 0x7e070bf4, 0xfb003a31, 0x30f40885, + 0x05ecdff4, 0x62f90000, 0x94bdffbf, 0xfe0141fe, 0x11900140, 0x1c009020, 0x09a019a0, 0x900149fe, 0xb2b22499, 0xd5b2c6b2, 0x1bb29fa0, 0x407e0cb2, 0xa3320084, 0x591fa433, 0x0bbf1abf, 0x0084fc7e, 0x0a00a433, 0xad3e0903, 0x19bf0089, 0x94b600bf, 0x0f04b614, 0x7e0009bc, 0xd900010e, 0x01015000, 0xbc0009bc, 0x60bc4002, 0x7e1ab210, 0xb2001a27, 0x7e4ab2a0, 0xb2001a27, 0x7e1ab2a2, 0xa6001a27, - 0xe81bf40a, 0x0001087e, 0xa00150b5, 0x0149fe52, 0xbf249990, 0x05dcd99f, 0x99bf0000, 0xf9a63a32, - 0x7e070bf4, 0xfb003a31, 0x30f40c65, 0x05dcdff4, 0x02f90000, 0x49feffbf, 0x0c999001, 0x9fa0c0b2, + 0xe81bf40a, 0x0001087e, 0xa00150b5, 0x0149fe52, 0xbf249990, 0x05ecd99f, 0x99bf0000, 0xf9a63a32, + 0x7e070bf4, 0xfb003a31, 0x30f40c65, 0x05ecdff4, 0x02f90000, 0x49feffbf, 0x0c999001, 0x9fa0c0b2, 0x040aaf32, 0xf423f630, 0x94bd780c, 0x90014dfe, 0xd9b504dd, 0x33d9a001, 0x302501b0, 0x08f401b6, 0x02b03311, 0x331f0a28, 0x3e3c03b4, 0xc4008a36, 0x4c4bfffa, 0x15504c15, 0x008a3f3e, 0x4bfffac4, 0x504c1d4c, 0x8a3f3e1d, 0xfffac400, 0x4c15f44b, 0x3f3e15f8, 0xfac4008a, 0x1df44bff, 0x7e1df84c, 0xfe00891e, 0x99900149, 0x989ebf04, 0xe5b60199, 0x069f9506, 0xb51a94b6, 0xe9fd010f, 0xfe0ea005, - 0x99900149, 0xd99fbf0c, 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, 0x9cd90c05, 0x18000029, + 0x99900149, 0xd99fbf0c, 0x000005ec, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, 0x9cd90c05, 0x18000029, 0x00f8159a, 0xa033080f, 0x1f0f1901, 0xf401a630, 0xa9121008, 0x30060f30, 0x0cf40496, 0x32070f05, - 0xf400f8fa, 0x22f9f830, 0x0005dcd2, 0xfe29bf00, 0x11900141, 0x0140fe10, 0x0e7e19a0, 0x00900001, + 0xf400f8fa, 0x22f9f830, 0x0005ecd2, 0xfe29bf00, 0x11900141, 0x0140fe10, 0x0e7e19a0, 0x00900001, 0x7e0ab20c, 0xdf00732c, 0x0000299c, 0xf9980ebf, 0x15feb515, 0x9cf09ea6, 0x58f9350b, 0x0001087e, 0x29bf1fbf, 0x0bf4f9a6, 0x3a317e07, 0x0825fb00, 0x00299cd9, 0x15991800, 0xbeb2adb2, 0x9033cfb2, - 0xb4d91a00, 0x98000029, 0x9bbf019c, 0x367efab2, 0x847e0021, 0x00f8008a, 0x000644d9, 0xb29abf00, + 0xb4d91a00, 0x98000029, 0x9bbf019c, 0x367efab2, 0x847e0021, 0x00f8008a, 0x000654d9, 0xb29abf00, 0xbcecb2cb, 0x7e7ea0ad, 0x1f0a000b, 0xbdb200f8, 0xa0b3ceb2, 0xb6b13800, 0x0cf423bf, 0x23c04930, 0xa6029bbb, 0x250cf4c9, 0x00299cd9, 0x15991800, 0x9033010f, 0xb4d91a00, 0x98000029, 0x9bbf019c, - 0x0020d07e, 0x6c3eaf32, 0x020f008b, 0x00f8fa32, 0xdfd830f4, 0x000005dc, 0xffbf72f9, 0x900149fe, + 0x0020d07e, 0x6c3eaf32, 0x020f008b, 0x00f8fa32, 0xdfd830f4, 0x000005ec, 0xffbf72f9, 0x900149fe, 0x46fe4499, 0xb29fa001, 0xb2b1b2a0, 0x246690c4, 0x23c0a6b1, 0xb17d0cf4, 0xf423c0b6, 0xbabc760c, 0xc096b190, 0x6c0cf423, 0x000e067e, 0xd50302c4, 0x000029b4, 0x07ff29c4, 0x3209bc20, 0x008c033e, 0x5c985bbf, 0xb26ab201, 0x7e200e3d, 0x330020d0, 0x000a00a0, 0x8c093e06, 0xff29c400, 0xa60279bc, 0x050df401, 0x2bc410b2, 0xff0cc4ff, 0x04f04ab2, 0xb06bbcff, 0xbb203390, 0x7e7e0210, 0x40bc000b, - 0xb3243d40, 0x00bd0014, 0x0ddd7e1f, 0x8c133e00, 0xfe060000, 0x99900149, 0xd99fbf44, 0x000005dc, + 0xb3243d40, 0x00bd0014, 0x0ddd7e1f, 0x8c133e00, 0xfe060000, 0x99900149, 0xd99fbf44, 0x000005ec, 0x0a3299bf, 0x0bf4f9a6, 0x3a317e07, 0x2875fb00, 0x00299cd9, 0x15991800, 0xbeb2adb2, 0x0a009033, - 0x008b707e, 0x44d900f8, 0xbf000006, 0xb2cab29b, 0xb0bdbcec, 0x000b7e7e, 0x00f81f0a, 0xdff430f4, - 0x000005dc, 0xffbf32f9, 0x900149fe, 0xa2b21899, 0xa9bf9fa0, 0xb39899c7, 0x00aa1d99, 0x00299cd9, + 0x008b707e, 0x54d900f8, 0xbf000006, 0xb2cab29b, 0xb0bdbcec, 0x000b7e7e, 0x00f81f0a, 0xdff430f4, + 0x000005ec, 0xffbf32f9, 0x900149fe, 0xa2b21899, 0xa9bf9fa0, 0xb39899c7, 0x00aa1d99, 0x00299cd9, 0x02999800, 0xb34299c7, 0x009a0099, 0x0a0140fe, 0x14009001, 0xef7e0bb2, 0xa4330094, 0x4bfe551f, 0x90020a01, 0xef7e10bb, 0xa4330094, 0x09bf451f, 0x04bd0103, 0xbc1493ff, 0x94f09530, 0x121bf401, 0x0f0204b3, 0x009a457e, 0x0700a033, 0x900415f0, 0x04b30100, 0x49fee50a, 0x14999001, 0x19a699bf, 0x0a150bf4, 0x7e1bb201, 0x3300950a, 0xf80a1fa0, 0x8d233e09, 0xfe2ebf00, 0x99900149, 0xdf99bf10, 0xbfffffff, 0xeffd1f0a, 0x0099b904, 0xf09419ff, 0x96f00b9c, 0x1e94b601, 0xa0059efd, 0x8d233e29, - 0xfe1f0a00, 0x99900149, 0xd99fbf18, 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, 0x30f40c35, - 0x05dcdfe4, 0x52f90000, 0x49feffbf, 0x30999001, 0x9fa0a3b2, 0xc5b2afbf, 0xfdc7b4b2, 0x00ddb31d, + 0xfe1f0a00, 0x99900149, 0xd99fbf18, 0x000005ec, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, 0x30f40c35, + 0x05ecdfe4, 0x52f90000, 0x49feffbf, 0x30999001, 0x9fa0a3b2, 0xc5b2afbf, 0xfdc7b4b2, 0x00ddb31d, 0xfa95075d, 0x10f99508, 0xa132f032, 0xf9339232, 0x3000d515, 0x0cf415f6, 0x05f93346, 0xf63005fc, 0x1c0cf405, 0x8701f933, 0x301f0a00, 0x08f501f6, 0xf630073a, 0x250cf503, 0x8e283e07, 0x10f93300, 0xf630041b, 0x0e0cf410, 0xf50df630, 0x3e070f08, 0x33009156, 0x070711fd, 0x0091603e, 0x431df933, @@ -1212,18 +1212,18 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x0093513e, 0xffc7ff49, 0x95f194f9, 0x1c3e0800, 0xff490093, 0x94f9ffc7, 0x100095f1, 0xfe3fff8f, 0xe5049ffd, 0x3ec0009f, 0x49009351, 0xf9ffc7ff, 0x0095f194, 0x93433e08, 0xc7ff4900, 0xf194f9ff, 0x8f100095, 0xfdfe3fff, 0x008f049f, 0x9fff0100, 0x299cd9f5, 0x99180000, 0x00903350, 0x0000890f, - 0x95f9ff02, 0x00936f3e, 0xfdffff89, 0xa094f9ff, 0x94313e49, 0x16a63000, 0x01480cf5, 0xd9ffafc4, + 0x95f9ff02, 0x00936f3e, 0xfdffff89, 0xa094f9ff, 0x94313e49, 0x17a63000, 0x01480cf5, 0xd9ffafc4, 0x000004d0, 0xd9e89fbc, 0x0000299c, 0xefc7080a, 0x989fbc3b, 0xbb96efc7, 0x94f0059f, 0x2b0bf501, 0xff29c401, 0x010defe7, 0x0a029b54, 0xf5bf6604, 0xf0011918, 0xb9e400f3, 0xf9bcffff, 0x04c6b0c2, 0x0c090df4, 0x93cb3e04, 0xe44da000, 0xc4ffffba, 0xebe703e9, 0x94330142, 0xbabc1200, 0x29bcd9b0, - 0x4ab20000, 0x0093f43e, 0x000644d9, 0xbc99bf00, 0x4ab2b0ba, 0x7eb09bbc, 0x3e000b7e, 0x32009431, + 0x4ab20000, 0x0093f43e, 0x000654d9, 0xbc99bf00, 0x4ab2b0ba, 0x7eb09bbc, 0x3e000b7e, 0x32009431, 0x9acb7e9b, 0x94c83e00, 0x00a03300, 0x33080a0f, 0x00b1011d, 0x0094c83e, 0x900140fe, 0x0ab22400, 0x0072fb7e, 0xa54f093f, 0x00943300, 0xa05a0f06, 0x3e1f0a4f, 0xd90094c8, 0x0000299c, 0x33159918, 0x00870099, 0x3802a033, 0xf402a630, 0xa0330f0c, 0xa4331800, 0x703e6e01, 0xa0330094, 0xa4332c03, 0x903e6204, 0x3ab20094, 0x009d827e, 0x0094c83e, 0xcbb2bab2, 0x009ffc7e, 0x0094c83e, 0x0b7e2a32, 0xc83e009d, 0x2a320094, 0x00a2127e, 0x0094c83e, 0xa67e2a32, 0xc83e00a1, 0x9cd90094, 0x18000029, 0x90331599, 0xfbc72400, 0xb22c326c, 0xf05eb24d, 0xac7e0fa4, 0xc83e009e, 0x020a0094, 0x0094c83e, - 0xc83e030a, 0x090a0094, 0x900149fe, 0x9fbf3099, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, + 0xc83e030a, 0x090a0094, 0x900149fe, 0x9fbf3099, 0x0005ecd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xf01c55fb, 0xa4b6ffa4, 0x0acaa002, 0x3200f81f, 0x30040aaf, 0x0cf402f6, 0xfff4f012, 0x002a5cd9, 0xf89fbc00, 0xbfa01f0a, 0xaf3200f8, 0xf630040a, 0x100cf402, 0xd9fff4f0, 0x00002a5c, 0x9bbc1f0a, 0xf900f8f9, 0x10af9512, 0xae95b1b2, 0x299cd008, 0xff090000, 0x1bf4e926, 0x4909183d, 0x1bf5f926, @@ -1241,20 +1241,20 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0xf49ba632, 0x9ea60808, 0xa62008f4, 0x080df4b9, 0x08f4bfa6, 0x2a68df16, 0x9fbc0000, 0xb0bfbca0, 0x000b7e7e, 0x00966e3e, 0xd03e040a, 0x030a0096, 0xc9b221fb, 0x0fffa6b1, 0xbc2b0cf4, 0x96b1909a, 0x0cf41000, 0x2a68de21, 0xaebc0000, 0x00d03390, 0x3e9ab20a, 0xb20096fb, 0x7e9bb2ba, 0x0a000b7e, - 0x0a00f81f, 0xf400f804, 0xdcdfe430, 0xf9000005, 0xfeffbf12, 0x99900149, 0xa0a0b220, 0xf0d1b29f, + 0x0a00f81f, 0xf400f804, 0xecdfe430, 0xf9000005, 0xfeffbf12, 0x99900149, 0xa0a0b220, 0xf0d1b29f, 0xedb2ffb4, 0xb40aa0b4, 0x09c40be0, 0xf49ba607, 0x0fc7751b, 0x0149fe2f, 0xa0089990, 0x029eb59d, 0xbc019ab5, 0x94bdb89f, 0x90014ffe, 0xf9a014ff, 0xb501fcb5, 0x09c702f1, 0xbcbabf23, 0x0fc7c8f9, 0x8a09c785, 0xf0e09f3c, 0x0dc71ff4, 0x05cfbb91, 0xb990d93c, 0xd4f000ee, 0x1fe4f01f, 0xbc0099b9, 0x94f0e0ef, 0xbcff0f1f, 0xf9bc909d, 0x05febb95, 0xfd049dbb, 0x99b904fc, 0x04fdbb00, 0xfd049afd, - 0xb9a0059f, 0x900149fe, 0x9fbf2099, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xf41c15fb, - 0xdcd9f430, 0xf9000005, 0xb299bf82, 0x014ffed1, 0xa02cff90, 0x92dd3ff9, 0x1f0003ff, 0xf0351709, - 0x02f03501, 0xb6b2f920, 0xa5b2e3b2, 0x1900d433, 0x000530db, 0x7e240c00, 0x09000b7e, 0x200a3209, + 0xb9a0059f, 0x900149fe, 0x9fbf2099, 0x0005ecd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xf41c15fb, + 0xecd9f430, 0xf9000005, 0xb299bf82, 0x014ffed1, 0xa02cff90, 0x92dd3ff9, 0x1f0003ff, 0xf0351709, + 0x02f03501, 0xb6b2f920, 0xa5b2e3b2, 0x1900d433, 0x000534db, 0x7e240c00, 0x09000b7e, 0x200a3209, 0x98823e19, 0x30030a00, 0x0cf409d6, 0x0147fe78, 0xb2ffc4c4, 0x90043df8, 0x793e2477, 0x09c40098, 0x947bb2ff, 0x040c0292, 0x3da026bc, 0x96d27ed4, 0x1fa43300, 0xc47fbf6b, 0x94a607f9, 0xc75e18f4, 0x991223f9, 0x01963001, 0xc7520cf4, 0xe9c42ffe, 0xc8893cff, 0xc78afdc7, 0xd93c85f9, 0xf49c2690, 0xe0333b0c, 0xf9c73803, 0x909d3c91, 0x0cf49c26, 0x9052bc2c, 0xa0010010, 0x26193f9f, 0xa108f409, - 0x49fe1f0a, 0x2c999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0xb23e230b, 0x0d0a0098, 0x0fc439bf, - 0x0000deff, 0x9efdff00, 0x05f9fd04, 0x823e3fa0, 0x317e0098, 0x85fb003a, 0xa830f40c, 0x0005dcd9, + 0x49fe1f0a, 0x2c999001, 0xecd99fbf, 0xbf000005, 0xf4f9a699, 0xb23e230b, 0x0d0a0098, 0x0fc439bf, + 0x0000deff, 0x9efdff00, 0x05f9fd04, 0x823e3fa0, 0x317e0098, 0x85fb003a, 0xa830f40c, 0x0005ecd9, 0xbf82f900, 0xf830f499, 0x4ffea7b2, 0x80ff9001, 0xaabff9a0, 0xb00eb1b0, 0xa6c70dc1, 0x01691268, 0xf5039630, 0xc7013b0c, 0x96306ca9, 0x310cf50a, 0x0141fe01, 0x900140fe, 0x00905711, 0x10a5b650, 0xb4bd1920, 0xe37e0cb2, 0xad330094, 0xbf011d1f, 0x0142fe09, 0x90ff6bc4, 0xb4b65822, 0xbc2ab204, @@ -1266,12 +1266,12 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x0433009a, 0x043d3f1f, 0x0099f53e, 0x98ff09c4, 0x1d98021c, 0x0de0b403, 0x90014ffe, 0xf9bc58ff, 0x0e90b4a8, 0x1001e1b0, 0x3b320100, 0xb20091b0, 0x97077e7e, 0x57903400, 0x08f40926, 0x9a083ed2, 0x3d19bf00, 0x1f929584, 0x90013310, 0x36261055, 0xff4208f5, 0x80331b0a, 0x243e1100, 0x030a009a, - 0x009a273e, 0xfe3fa034, 0x99900149, 0xd99fbf80, 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xf4003a31, - 0x85fb0830, 0xf430f458, 0x0005dcdf, 0xbf12f900, 0x0149feff, 0xfe109990, 0x9fa00141, 0x4a0c1190, + 0x009a273e, 0xfe3fa034, 0x99900149, 0xd99fbf80, 0x000005ec, 0xf9a699bf, 0x7e070bf4, 0xf4003a31, + 0x85fb0830, 0xf430f458, 0x0005ecdf, 0xbf12f900, 0x0149feff, 0xfe109990, 0x9fa00141, 0x4a0c1190, 0x040b00b8, 0x307e1cb2, 0xa433008c, 0x40fe2b1f, 0x00b44a01, 0x0b080090, 0x7e0cb204, 0x33008c30, 0xbf161fa4, 0xa60fbf19, 0x0b9cf09f, 0x320196f0, 0x9a973e9a, 0xfea43d00, 0x99900149, 0xd99fbf10, - 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, 0xa9980c15, 0x90afb204, 0x010b59ac, 0x4a2095f0, - 0xf9b50090, 0x8c307e04, 0xf400f800, 0xdcd99030, 0xf9000005, 0xfe99bf52, 0xff90014f, 0xa0030e84, + 0x000005ec, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, 0xa9980c15, 0x90afb204, 0x010b59ac, 0x4a2095f0, + 0xf9b50090, 0x8c307e04, 0xf400f800, 0xecd99030, 0xf9000005, 0xfe99bf52, 0xff90014f, 0xa0030e84, 0x00ad33f9, 0x9cd90105, 0x18000029, 0x99335999, 0x3200f600, 0x014cfeba, 0xcc90b4bd, 0x94e37e20, 0x33ae3200, 0x00e31fad, 0x4a0144fe, 0x449000b8, 0xb2040b1c, 0x8c307e4c, 0x33ae3200, 0x00cb1fad, 0x4a0140fe, 0x009000b4, 0xb2040b18, 0x8c307e0c, 0x33ae3200, 0x00b31fad, 0x4abf09bf, 0x0bf5a9a6, @@ -1280,20 +1280,20 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x90b0729b, 0xb3f0bcaa, 0x7e2cb200, 0xe4008c30, 0x32ffff0f, 0x1fa433ae, 0x7b39bf51, 0x2fbc0210, 0x90f9bc20, 0x0fff94f1, 0x147339a0, 0x49fec700, 0x20999001, 0x99909abf, 0xfe9c3f07, 0x010d014b, 0xf028bb90, 0xc4b6ffc4, 0x96d27e02, 0x33ae3200, 0xb2171fa4, 0x00b84a4c, 0xf07e040b, 0xae32008a, - 0x009be63e, 0x49fe090e, 0x84999001, 0xdcd99fbf, 0xbf000005, 0xa6ea3299, 0x070bf4f9, 0x003a317e, + 0x009be63e, 0x49fe090e, 0x84999001, 0xecd99fbf, 0xbf000005, 0xa6ea3299, 0x070bf4f9, 0x003a317e, 0x987055fb, 0x008f04a9, 0x9ffd3ff0, 0x04a9b505, 0xaeb200f8, 0x0a10bf12, 0x26ee0904, 0x2e0df4f9, 0x0a00c433, 0x2d3eea7f, 0xea58009c, 0x00a07301, 0x26ff0918, 0x140bf4b9, 0xffffa9e4, 0xf0059bbb, - 0x1bf40194, 0xf8090a07, 0xf81f0a00, 0xf830f400, 0x0005dcdf, 0xbf32f900, 0x0149feff, 0x900140fe, + 0x1bf40194, 0xf8090a07, 0xf81f0a00, 0xf830f400, 0x0005ecdf, 0xbf32f900, 0x0149feff, 0x900140fe, 0x43fe1499, 0xb29fa001, 0x90b1b2a2, 0x33901300, 0x10ec4a12, 0x0cb2010b, 0x008b707e, 0x741fa433, 0xa6300a3f, 0x690cf401, 0x210020b3, 0x94ffa4f0, 0x240b05a9, 0xb202a4b6, 0xa0a9bc2c, 0x10eeaab8, 0x8b707e00, 0x1fa43300, 0x0010b34b, 0x0b0a3f23, 0xf01cb204, 0xa994ffa4, 0x02a4b605, 0xb8a0a9bc, 0x0010eeaa, 0x008b707e, 0x281fa433, 0x0b10ec4a, 0x7e3cb201, 0x33008b70, 0x3f191fa4, 0x01f6303f, - 0x3f0e0cf4, 0xf49f2609, 0xf03e8a1b, 0x050a009c, 0x900149fe, 0x9fbf1499, 0x0005dcd9, 0xa699bf00, - 0x070bf4f9, 0x003a317e, 0xf40835fb, 0xdcdfd830, 0xf9000005, 0xfeffbf22, 0x99900149, 0xa0a13230, + 0x3f0e0cf4, 0xf49f2609, 0xf03e8a1b, 0x050a009c, 0x900149fe, 0x9fbf1499, 0x0005ecd9, 0xa699bf00, + 0x070bf4f9, 0x003a317e, 0xf40835fb, 0xecdfd830, 0xf9000005, 0xfeffbf22, 0x99900149, 0xa0a13230, 0x299cd99f, 0x99980000, 0x0ab2b204, 0x0094f108, 0x360bf440, 0xbd0140fe, 0x0c0090b4, 0x4d7e0ab2, 0xa433009c, 0x0ab2251f, 0x010c1b32, 0x009c127e, 0x171fa433, 0x90ff19c4, 0x99bc0299, 0x9009bc90, - 0x92f0997f, 0xfe29a00f, 0x99900149, 0xd99fbf30, 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, - 0x30f42825, 0x05dcdfd8, 0x62f90000, 0x49feffbf, 0x40999001, 0x9fa0b2b2, 0x00299cd9, 0x04999800, + 0x92f0997f, 0xfe29a00f, 0x99900149, 0xd99fbf30, 0x000005ec, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, + 0x30f42825, 0x05ecdfd8, 0x62f90000, 0x49feffbf, 0x40999001, 0x9fa0b2b2, 0x00299cd9, 0x04999800, 0xc3b2a6b2, 0x94f1080b, 0x0bf51000, 0xb4bd00e5, 0x900141fe, 0x1ab21c11, 0x009c4d7e, 0xad33ab32, 0x0b00d11f, 0x0c1ab2ff, 0x9c127e01, 0x33ab3200, 0x00c01fad, 0x1ab2ff0b, 0x127ec43d, 0xab32009c, 0xaf1fad33, 0x01145800, 0x29a094bd, 0x109039a0, 0x72157f04, 0x4da47d4c, 0xe4bd8000, 0x323e0101, @@ -1301,8 +1301,8 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x9e273e05, 0x90df7200, 0xc57601ee, 0x02009001, 0xc473fd72, 0x6ebfd000, 0xc400d3f0, 0xffdfffa9, 0xb6ff00ff, 0xeffd1094, 0x00008c04, 0x059efdff, 0xfd049cfd, 0x69a0059d, 0x4ee429bf, 0xafc7ffff, 0x10ed94e8, 0xff0094f1, 0xfd059dfd, 0x2fa005f9, 0xffff59e4, 0xff00eeb9, 0x0bf4a4e9, 0xfd39bf15, - 0x9afd049c, 0xbf39a005, 0x0095f129, 0xfe29a001, 0x99900149, 0xd99fbf40, 0x000005dc, 0xba3299bf, - 0x0bf4f9a6, 0x3a317e07, 0x2865fb00, 0xdff030f4, 0x000005dc, 0xffbf62f9, 0x900149fe, 0xa1322899, + 0x9afd049c, 0xbf39a005, 0x0095f129, 0xfe29a001, 0x99900149, 0xd99fbf40, 0x000005ec, 0xba3299bf, + 0x0bf4f9a6, 0x3a317e07, 0x2865fb00, 0xdff030f4, 0x000005ec, 0xffbf62f9, 0x900149fe, 0xa1322899, 0xb0329fa0, 0xd5b2c432, 0xb630e6b2, 0x120cf504, 0x299cd901, 0x9e980000, 0xffb9c404, 0xc4119990, 0x080a1f9f, 0xb905efbb, 0x94f00099, 0x909fbc1f, 0xf9bbff0f, 0x34feff05, 0xe9013db3, 0xfe94bd00, 0xff90014f, 0x0142fe20, 0x9001f9b5, 0xf9a01c22, 0x2bb2a4bd, 0x009c4d7e, 0xc91fad33, 0x322ab200, @@ -1312,27 +1312,27 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x009fa53e, 0xf1ff19c4, 0x0f012690, 0x5a9eb802, 0xa53e0011, 0x19c4009f, 0x2690f1ff, 0x01004f01, 0x115c9eb8, 0x03499400, 0x9cc4040a, 0xf4cfa6f8, 0xc9903218, 0xa6080b08, 0x060df49f, 0xbcb2fcbc, 0x40fea0ec, 0x20009001, 0x707e0cb2, 0xa433008b, 0x09bf131f, 0x009859a0, 0x3e60a001, 0x0a009fe1, - 0x0149fe03, 0xbf289990, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x3a317e07, 0x1065fb00, 0xdfe830f4, - 0x000005dc, 0xffbf52f9, 0x900149fe, 0xa3b22c99, 0x9cd99fa0, 0x98000029, 0xb2b20499, 0x94f1080a, + 0x0149fe03, 0xbf289990, 0x05ecd99f, 0x99bf0000, 0x0bf4f9a6, 0x3a317e07, 0x1065fb00, 0xdfe830f4, + 0x000005ec, 0xffbf52f9, 0x900149fe, 0xa3b22c99, 0x9cd99fa0, 0x98000029, 0xb2b20499, 0x94f1080a, 0x0bf52000, 0x40fe00ca, 0x90a4bd01, 0x0bb21800, 0x009c4d7e, 0xb81fad33, 0x0b0ab200, 0x7ec43dff, 0x33009c12, 0x00a91fad, 0x7f0141fe, 0x1c119000, 0x0b10dc4a, 0x7e1cb210, 0x33008b70, 0x00911fad, 0x15b20b72, 0x04bdc4bd, 0xff04e001, 0x00a0e83e, 0xf401b9c4, 0xc6b0690b, 0x350cf407, 0x5c3c3dbf, 0x1f0ec4f8, 0xb9030990, 0xf4f00099, 0x1f94f0ff, 0xbc909ebc, 0x9fff9549, 0x049ebbf4, 0xb904febb, 0x9dfd0099, 0x059ffd04, 0xdc3e39a0, 0x2dbf00a0, 0xc4f85c3c, 0x09921f1e, 0x0099b91d, 0xf0fff4f0, 0x9ebc1f94, 0x9549bc90, 0xbbf49fff, 0xfebb049e, 0x0099b904, 0xfd049dfd, 0x29a0059f, 0x7601cc90, - 0x009001b5, 0x04119004, 0x8800b473, 0x900149fe, 0x9fbf2c99, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, - 0x003a317e, 0xf41855fb, 0xdcdfd430, 0xf9000005, 0xfeffbf22, 0x99900149, 0xfea23234, 0x9fa00141, + 0x009001b5, 0x04119004, 0x8800b473, 0x900149fe, 0x9fbf2c99, 0x0005ecd9, 0xa699bf00, 0x070bf4f9, + 0x003a317e, 0xf41855fb, 0xecdfd430, 0xf9000005, 0xfeffbf22, 0x99900149, 0xfea23234, 0x9fa00141, 0x4a0c1190, 0x280b2398, 0x707e1cb2, 0xa433008b, 0x10985d1f, 0xbc19bf01, 0x90a6f290, 0xb01008f4, 0x9cf001f6, 0x0196f00b, 0x00a1563e, 0xf9a6e109, 0xf00b9cf0, 0x0b0a0196, 0x33009033, 0x0029b4d9, 0x019c9800, 0x4ffe9bbf, 0x0cff9001, 0x4d90f0bc, 0x9235239c, 0x90240e08, 0x94f00109, 0x04fa901f, - 0x7e01f9b5, 0x7e002136, 0xfe008a84, 0x99900149, 0xd99fbf34, 0x000005dc, 0xf9a699bf, 0x7e070bf4, - 0xfb003a31, 0x30f42c25, 0x05dcdff8, 0x12f90000, 0x49feffbf, 0x0c999001, 0x9fa0a132, 0x00299cd9, + 0x7e01f9b5, 0x7e002136, 0xfe008a84, 0x99900149, 0xd99fbf34, 0x000005ec, 0xf9a699bf, 0x7e070bf4, + 0xfb003a31, 0x30f42c25, 0x05ecdff8, 0x12f90000, 0x49feffbf, 0x0c999001, 0x9fa0a132, 0x00299cd9, 0x049f9800, 0x0089080a, 0xf9fd0100, 0x2a0bf404, 0xbd0140fe, 0x080090a4, 0x4d7e0bb2, 0xa433009c, 0x0ab2191f, 0xc43d1b32, 0x009c127e, 0x0b1fa433, 0x7e1f1ac4, 0xfe00a107, 0x99900149, 0xd99fbf0c, - 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, 0x30f40815, 0x05dcdff8, 0x12f90000, 0x49feffbf, + 0x000005ec, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, 0x30f40815, 0x05ecdff8, 0x12f90000, 0x49feffbf, 0x0c999001, 0x9fa0a132, 0x00299cd9, 0x04999800, 0x94f1080a, 0x90738000, 0x40fe2e00, 0x90a4bd01, 0x0bb20800, 0x009c4d7e, 0x1c1fa433, 0x1b320ab2, 0x127ec43d, 0xa433009c, 0x1ac40e1f, 0x20a5f01f, - 0x00a1077e, 0x900149fe, 0x9fbf0c99, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xf90815fb, + 0x00a1077e, 0x900149fe, 0x9fbf0c99, 0x0005ecd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xf90815fb, 0x06b99552, 0x94b6c4b2, 0xbcd5b203, 0xb0c430a9, 0xa2e03e3f, 0x9831bf00, 0x54b30132, 0x010a1800, 0x0cb2b4bd, 0x0039cd7e, 0xfd052bfd, 0xc83e051a, 0x0cb200a2, 0xb4bd010a, 0x0039cd7e, 0xb900b9b9, 0x29fd00aa, 0x041afd04, 0xb3014492, 0x900b0040, 0x04b30100, 0x31a0c840, 0xbd0132b5, 0x08339004, @@ -1347,14 +1347,14 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x00409631, 0x31251df4, 0xf4005a96, 0xd0331e1c, 0xefc41b00, 0x04f9c4ff, 0xc4151bf4, 0x94b30af9, 0xa9180b02, 0x00903307, 0xf8060a08, 0xf8a4bd00, 0x0f12f900, 0xb2b1b202, 0x00a0b3a0, 0xf0a93f22, 0x1bf40894, 0xa3107e17, 0x0010b300, 0x181a2006, 0x060f0809, 0x1bf4a926, 0xb2f4bd05, 0xb211fbfa, - 0xb3020aa9, 0xbf1200c0, 0xb6cdb29a, 0x804c07b4, 0xb7627e00, 0xf400f800, 0xdcdff830, 0xf9000005, + 0xb3020aa9, 0xbf1200c0, 0xb6cdb29a, 0x804c07b4, 0xb7627e00, 0xf400f800, 0xecdff830, 0xf9000005, 0xfeffbf22, 0x99900149, 0xa0a0b210, 0xb3020a9f, 0xbf340000, 0x94943d0a, 0x41fe07b2, 0x902bb201, 0x010c0f11, 0x1db21920, 0x00b7797e, 0x1700a4b3, 0x0abf193f, 0x1db22bb2, 0x0cfd94f0, 0x7e192001, - 0xfe00b762, 0x99900149, 0xd99fbf10, 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, 0x30f40825, - 0x05dcdff8, 0x42f90000, 0x49feffbf, 0x18999001, 0x9fa0a1b2, 0xc0b2b4b2, 0xa0b3d3b2, 0xc0b35600, + 0xfe00b762, 0x99900149, 0xd99fbf10, 0x000005ec, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, 0x30f40825, + 0x05ecdff8, 0x42f90000, 0x49feffbf, 0x18999001, 0x9fa0a1b2, 0xc0b2b4b2, 0xa0b3d3b2, 0xc0b35600, 0xcf185200, 0xfe94bd07, 0x22900142, 0x01ff1014, 0xcf3529a0, 0x7ecab207, 0xb200a310, 0x080a352b, 0xb27e1ab2, 0xa4b300a7, 0x2bbf2c00, 0x1ab20cb2, 0x00a43f7e, 0x1e00a4b3, 0x4bb21ab2, 0x00a4577e, - 0x1200a4b3, 0x0e0030b3, 0x32a022bf, 0x00a5323e, 0x49fe020a, 0x18999001, 0xdcd99fbf, 0xbf000005, + 0x1200a4b3, 0x0e0030b3, 0x32a022bf, 0x00a5323e, 0x49fe020a, 0x18999001, 0xecd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x45fb003a, 0xb202f908, 0x00a0b3c0, 0x00c0b324, 0xb6aabf20, 0x804c07b4, 0x7e0db200, 0xb300b779, 0xb21000a4, 0xa3307e0a, 0xa5773e00, 0xfb020a00, 0x00a0b301, 0x00c0b317, 0xb2aabf13, 0x07b4b6cd, 0x797e100c, 0x00f800b7, 0x00f8020a, 0xb3b242f9, 0xa2b2c4b2, 0xa0b30200, @@ -1368,30 +1368,30 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x909dbc90, 0xb80394b6, 0x00014099, 0x269009bc, 0x0b1bf4ef, 0xa4bd29a0, 0x00a6a83e, 0x9001dd90, 0xd4b318cc, 0x040ab314, 0xabbf21fb, 0xf009acb2, 0x0bf4b9a6, 0x03aa980d, 0x7e01cbb5, 0xf800b65f, 0xb232f900, 0xbdb2b2a1, 0x3ef00304, 0xbf00a6f0, 0x01009019, 0x93a61ab2, 0x0a090df4, 0xa6f73e03, - 0xf493a600, 0x020a091b, 0x00a6f73e, 0x00a6aa7e, 0x08f402a6, 0xfba4bddd, 0xf830f431, 0x0005dcdf, + 0xf493a600, 0x020a091b, 0x00a6f73e, 0x00a6aa7e, 0x08f402a6, 0xfba4bddd, 0xf830f431, 0x0005ecdf, 0xbf82f900, 0x0149feff, 0xb2289990, 0xb29fa0a3, 0x00a9b3b8, 0xb0b30084, 0x47fe7f00, 0x05a49801, - 0x54bd24bd, 0x779014bd, 0xa7613e24, 0x0c3a9800, 0x02bc94bd, 0xb279a0b0, 0xb65f7e7c, 0x0f79bf00, + 0x14bd54bd, 0x779024bd, 0xa7613e24, 0x0c3a9800, 0x02bc94bd, 0xb279a0b0, 0xb65f7e7c, 0x0f79bf00, 0xf49fa6ff, 0x643d090b, 0x00a74f3e, 0x90015590, 0x04a60100, 0x33d908f4, 0x90070060, 0x24bc0111, 0x03399820, 0x18f429a6, 0xbd01060b, 0xa7523e04, 0xb24bb200, 0x16fc7e1a, 0xf45aa600, 0x1190060d, 0x06399801, 0x19a6f43d, 0x0f050cf4, 0xbd8f2001, 0xa7973ea4, 0xfe020a00, 0x99900149, 0xd99fbf28, - 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, 0x30f40885, 0x05dcdff0, 0x82f90000, 0x49feffbf, + 0x000005ec, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, 0x30f40885, 0x05ecdff0, 0x82f90000, 0x49feffbf, 0x30999001, 0xa00147fe, 0x08a9989f, 0xb1b0a6b2, 0xb0f10509, 0x843d0a91, 0x779090b2, 0x0369982c, 0x7fa0f4bd, 0x08f409a6, 0x0804bd07, 0x0a90b401, 0x1bf409a6, 0x00803335, 0xa85a3e32, 0x0c6a9800, 0xb24010bc, 0x7e4bb27c, 0xbf00b65f, 0xa6ff0f79, 0x0f1bf49f, 0x09012290, 0xf439a6f1, 0x43b2051b, 0x3e011190, 0xbd00a82d, 0xbdf10314, 0x05699824, 0x08f419a6, 0x0020b3cb, 0xf429a61e, 0x60b50f18, 0x09f0b408, 0x6b3ef3a0, 0xf10f00a8, 0x1bf45fa6, 0xbc05b205, 0xdd3e0009, 0x1a0a00a7, 0x59a6f109, - 0xb50d0bf4, 0x90b40865, 0xbd95a009, 0x0149fea4, 0xbf309990, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, - 0x3a317e07, 0x1085fb00, 0xd9f830f4, 0x000005dc, 0x99bf82f9, 0x90014ffe, 0xa3b228ff, 0xb4b2f9a0, + 0xb50d0bf4, 0x90b40865, 0xbd95a009, 0x0149fea4, 0xbf309990, 0x05ecd99f, 0x99bf0000, 0x0bf4f9a6, + 0x3a317e07, 0x1085fb00, 0xd9f830f4, 0x000005ec, 0x99bf82f9, 0x90014ffe, 0xa3b228ff, 0xb4b2f9a0, 0xc033d0b2, 0xdab20e00, 0x140cb43d, 0x00b7907e, 0xbd0142fe, 0x24229014, 0xff07fe08, 0xfb05fc06, 0x00a93a3e, 0xbd0c3a98, 0xb014bc94, 0x2cb229a0, 0x00b65f7e, 0xf00f29bf, 0x0df49fa6, 0xa6fd0f56, 0x110cf49f, 0x18f496a6, 0xf495a630, 0x093e451b, 0x98a600a9, 0xa62f0bf4, 0x371bf497, 0x90010998, 0x09b50199, 0xa9373e01, 0x04099800, 0xb5019990, 0x373e0409, 0x099800a9, 0x01999002, 0x3e0209b5, 0x9800a937, 0x99900309, 0x0309b501, 0x00a9373e, 0x999009bf, 0x9009a001, 0x39980111, 0xf419a605, - 0x49fe8508, 0x28999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x85fb003a, 0xf830f408, - 0x0005dcdf, 0xb222f900, 0xb2ffbfa1, 0x03aa98b2, 0x49fe1bbf, 0x10999001, 0xa00140fe, 0x0c00909f, + 0x49fe8508, 0x28999001, 0xecd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x85fb003a, 0xf830f408, + 0x0005ecdf, 0xb222f900, 0xb2ffbfa1, 0x03aa98b2, 0x49fe1bbf, 0x10999001, 0xa00140fe, 0x0c00909f, 0x5f7e0cb2, 0x0cbf00b6, 0xb2031a98, 0xb6767e2b, 0x011b9800, 0xb9a6ff09, 0x98101bf4, 0x12b50419, 0x0292b502, 0x00a9b13e, 0xb2031a98, 0xb6767e2c, 0x031a9800, 0xfd0c1bbf, 0x00b6767e, 0x900149fe, - 0x12a01099, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x25fb003a, 0xc830f408, 0x0005dcdf, + 0x12a01099, 0xecd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x25fb003a, 0xc830f408, 0x0005ecdf, 0xbf82f900, 0xf830f4ff, 0x900149fe, 0x9fa06099, 0x18049992, 0xf4bd1cae, 0xa9989fa0, 0x0aa2b205, 0x0b91b005, 0x1a00e933, 0x0c2b9802, 0xfe092c98, 0xf100014a, 0xfe44aa90, 0xa6b20144, 0x8b7e2001, 0x05b200b6, 0x4490a3b2, 0xaa723e30, 0x08299800, 0x0bf439a6, 0xb22ab231, 0xb2010c3b, 0xa8887e4d, @@ -1410,8 +1410,8 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x0111b05c, 0x00a5e47e, 0xbf042c98, 0x048bb22a, 0xb74b7efb, 0x981ebf00, 0xa0b2042c, 0x2ab2b4bd, 0xe67e0db2, 0x04b300a5, 0xff040600, 0x013e04bd, 0x2a9800ac, 0xb003bc0c, 0x00904cb2, 0xb6767e01, 0x0b90b400, 0x08f409a6, 0x032f98ec, 0xb59039bc, 0x9fa60929, 0xbd0808f4, 0x0929b594, 0x49fea4bd, - 0x60999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x30f4003a, 0x3885fb08, 0xd9cc30f4, - 0x000005dc, 0x99bf82f9, 0xfef830f4, 0xff90014f, 0xb0f9a05c, 0xc8b20be1, 0xa3b2d6b2, 0x8400b9b3, + 0x60999001, 0xecd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x30f4003a, 0x3885fb08, 0xd9cc30f4, + 0x000005ec, 0x99bf82f9, 0xfef830f4, 0xff90014f, 0xb0f9a05c, 0xc8b20be1, 0xa3b2d6b2, 0x8400b9b3, 0x00e9b302, 0xaf18027f, 0x0141fe2c, 0x119094bd, 0x0019a054, 0x00f93303, 0xc43d026d, 0x407e1db2, 0xa0b200a6, 0x5e00adb3, 0xbc17bf02, 0x7998f068, 0xf59fa601, 0x98024d08, 0x94b30479, 0x05000a01, 0x00aee23e, 0x3e0069b3, 0x027f9802, 0xf9a6f009, 0x022a0bf5, 0xea7e3ab2, 0xa2b200a5, 0x1e00a9b3, @@ -1420,7 +1420,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x070b943a, 0xb200804c, 0xb7797e2d, 0x0ca1b000, 0xb600adb3, 0x05291801, 0x76042f18, 0xf4f00894, 0xe59fffff, 0xe966ff09, 0x01980bf5, 0xffffe9e4, 0x08f589a6, 0xf4bd018e, 0x18902fbc, 0x9d330999, 0x90018200, 0xf4b301ff, 0xfc3ef207, 0x8e3c00ae, 0xf59f26f2, 0xc4016d08, 0x94f0fffd, 0x529dbcff, - 0x0df456a6, 0x9065b205, 0xe4bd10d9, 0x3db029bc, 0x3ec43da4, 0xb100ada7, 0xf5006fd6, 0xb401450c, + 0x0df456a6, 0x9065b205, 0xa43d10d9, 0x3db029bc, 0x3ee4bdc4, 0xb100ada7, 0xf5006fd6, 0xb401450c, 0xbe3c0b10, 0xf81e3c98, 0x0bf4f926, 0xff94f017, 0xfd009939, 0x9033049f, 0x010a0600, 0x0ce9bf3c, 0x01ee9001, 0xa601dd90, 0xce08f4e5, 0xed00c933, 0xf0293f00, 0x0bf40894, 0x00a93308, 0x94bd00d0, 0x91b03ab2, 0x1391b014, 0x301291b0, 0x4bfe5b91, 0x5bbb9001, 0x00a6f97e, 0xadb3a0b2, 0x3400ef00, @@ -1432,8 +1432,8 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x49b5029f, 0xae993e01, 0xb20bb200, 0x7e2cb23a, 0xb200a43f, 0x00a4b3a0, 0x0265bb34, 0x90014afe, 0xaa7e34aa, 0x60b300a6, 0x90b42000, 0x8085bc0b, 0xb09095bc, 0xe53e0b91, 0x020000ac, 0x00aec93e, 0xc93e0300, 0x00b400ae, 0xb23ab20c, 0xa60c7e2b, 0xb594bd00, 0xe23e0579, 0x030000ae, 0x00aee23e, - 0x49fe0200, 0x5c999001, 0xdcd99fbf, 0xbf000005, 0xa60ab299, 0x170bf4f9, 0x00af083e, 0x33062918, - 0xfe4f009d, 0x00aec03e, 0x003a317e, 0xfb0830f4, 0x30f43485, 0x05dcdfdc, 0x82f90000, 0x30f4ffbf, + 0x49fe0200, 0x5c999001, 0xecd99fbf, 0xbf000005, 0xa60ab299, 0x170bf4f9, 0x00af083e, 0x33062918, + 0xfe4f009d, 0x00aec03e, 0x003a317e, 0xfb0830f4, 0x30f43485, 0x05ecdfdc, 0x82f90000, 0x30f4ffbf, 0x0149fef8, 0xa04c9990, 0x0bb1b09f, 0xd4b2c2b2, 0xa5b2e6b2, 0x1700b9b3, 0x00e9b301, 0x94bd0112, 0x3d0141fe, 0x481190c4, 0x1db219a0, 0x00a6407e, 0xadb3a0b2, 0xbf00fb00, 0xf042bc19, 0xa6019998, 0xea08f59f, 0x005ab200, 0xa5ea7e03, 0xb3a3b200, 0x00de00a9, 0x5c981bbf, 0x0140fe0c, 0xb2300090, @@ -1443,13 +1443,13 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x2cb20bb2, 0x797e3db2, 0x7ebf00b7, 0x3bb2a0b2, 0x2cb25ab2, 0xe67e0db2, 0x04b300a5, 0x3ab24500, 0x117eb4bd, 0xa0b200a4, 0x3700a4b3, 0x01bb7000, 0xf404a602, 0x40b2050d, 0xb2101b90, 0xb03bbc6a, 0x997e0cb2, 0x4afe00b7, 0x0240bb01, 0xbc30aa90, 0xaa7e6060, 0x14bd00a6, 0x6d004db3, 0xb280b2ff, - 0x7e3bb25a, 0x3e00a60c, 0x0000b04d, 0x0149fe02, 0xbf4c9990, 0x05dcd99f, 0x99bf0000, 0xf9a60ab2, - 0x7e070bf4, 0xf4003a31, 0x85fb0830, 0xf830f424, 0x0005dcd9, 0xbf32f900, 0x014ffe99, 0xb214ff90, + 0x7e3bb25a, 0x3e00a60c, 0x0000b04d, 0x0149fe02, 0xbf4c9990, 0x05ecd99f, 0x99bf0000, 0xf9a60ab2, + 0x7e070bf4, 0xf4003a31, 0x85fb0830, 0xf830f424, 0x0005ecd9, 0xbf32f900, 0x014ffe99, 0xb214ff90, 0xbdf9a0a1, 0xb2b2b294, 0x0140fec3, 0x9003204b, 0x09a01000, 0x9f7e0ab2, 0x09bf00b7, 0x4c0090b3, 0x4800a4b3, 0x09bf91a0, 0xbf0192b5, 0x1000490f, 0xbf04f9b5, 0xb520090f, 0x09bf05f9, 0xbf0693b5, 0x3501090f, 0x09bf1cf9, 0xbf2c9a35, 0xb5f0090f, 0x0fbf0af9, 0xb540f990, 0x0fbf0ef9, 0xb5c0f990, - 0x0abf0ff9, 0x00b0ea3e, 0x49fea4bd, 0x14999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, - 0x35fb003a, 0xd030f408, 0x0005dcdf, 0xbf82f900, 0x0149feff, 0xb2509990, 0x059fa0a3, 0x00a9b302, + 0x0abf0ff9, 0x00b0ea3e, 0x49fea4bd, 0x14999001, 0xecd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, + 0x35fb003a, 0xd030f408, 0x0005ecdf, 0xbf82f900, 0x0149feff, 0xb2509990, 0x059fa0a3, 0x00a9b302, 0xb63004fb, 0x0b9cf000, 0xbd2ca935, 0x0ca9b594, 0x00a5ea7e, 0x3abfa0b2, 0x804cb4bd, 0x7e0db200, 0xb200b779, 0x00adb3a5, 0x093f04b1, 0xa24a9d33, 0x01091804, 0x9a469d33, 0x02091804, 0x92469d33, 0x03091804, 0x8a539d33, 0x040e1804, 0x18050918, 0x0d18060f, 0xffe4f007, 0xf0ff94f0, 0x94b6fff4, @@ -1490,20 +1490,20 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0xf0f9bcff, 0x3e517fb5, 0x0a00b5d3, 0x3ea5b203, 0x9000b5de, 0x77900188, 0x148db318, 0x49fefd90, 0x3c999001, 0x497e9abf, 0xf43e00b7, 0x030500b5, 0x00b5f63e, 0x0bb204bd, 0x0c7e3ab2, 0x50b300a6, 0x3a981a00, 0x7e04bd0c, 0x9800b6c8, 0x30b50d3a, 0xb7497e0c, 0x0d30b500, 0x900149fe, 0x9fbf5099, - 0x0005dcd9, 0xb299bf00, 0xf4f9a65a, 0x383e110b, 0x010500b6, 0x00b5f43e, 0x003a317e, 0xf93085fb, + 0x0005ecd9, 0xb299bf00, 0xf4f9a65a, 0x383e110b, 0x010500b6, 0x00b5f43e, 0x003a317e, 0xf93085fb, 0x7ea0b202, 0x9800a5e8, 0xc87e0c0a, 0x0a9800b6, 0xb7497e0d, 0x7e0ab200, 0xbd00b749, 0xbf01fba4, 0x0aafb2a9, 0xf4b9a602, 0xb9900d18, 0x98f9bc01, 0xc9a0a4bd, 0xa9bf00f8, 0x020aafb2, 0x18f4b9a6, 0x01b9900b, 0xfcbca4bd, 0xbf00f899, 0xb2afb2b9, 0xf4c9a6ca, 0xf10a0708, 0xfbb500f8, 0xb5fca002, 0x00f801fc, 0xaf98a9bf, 0x90b9bc02, 0xfbbfa9a0, 0x08f49ba6, 0x029bbb08, 0xa998a9a0, 0xa6aabf01, - 0x051bf4a9, 0x00f8f10a, 0x0800a0b3, 0x00b7497e, 0x30f400f8, 0x05dcdff8, 0x32f90000, 0x49feffbf, + 0x051bf4a9, 0x00f8f10a, 0x0800a0b3, 0x00b7497e, 0x30f400f8, 0x05ecdff8, 0x32f90000, 0x49feffbf, 0x14999001, 0x9fa0a0b2, 0xa0b3b3b2, 0xfd024200, 0x0cf4a2a6, 0x01ab903a, 0xb60141fe, 0x119002b4, 0x7e1ab210, 0xb300b7b5, 0xbf2700a4, 0xb21db219, 0xa0e4bd2c, 0x90dfbf90, 0x9eb201e9, 0xa699fcbc, - 0xf408f490, 0x3da0ddbf, 0x00b72e3e, 0x49fe020a, 0x14999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, + 0xf408f490, 0x3da0ddbf, 0x00b72e3e, 0x49fe020a, 0x14999001, 0xecd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x35fb003a, 0xda00f808, 0x00002944, 0x0041c77e, 0xf000a630, 0xa6f00bac, 0x01aab901, 0x44da00f8, 0x7e000029, 0x30004142, 0xacf000a6, 0x01a6f00b, 0xf801aab9, 0x2944da00, 0xd77e0000, 0xa6300042, 0x0bacf000, 0xb901a6f0, 0x00f801aa, 0x7effb4f0, 0xf8000b94, 0x0b7e7e00, 0xf900f800, 0x3da0b202, 0x384c7ea4, 0x00a6b000, 0xa00b9cf0, 0xfb9ab20a, 0xb202f901, 0x7ea43da0, 0xb000382a, - 0x9cf000a6, 0xb20aa00b, 0xf401fb9a, 0xdcdfe430, 0xf9000005, 0xfeffbf82, 0x45fe0149, 0x3c999001, + 0x9cf000a6, 0xb20aa00b, 0xf401fb9a, 0xecdfe430, 0xf9000005, 0xfeffbf82, 0x45fe0149, 0x3c999001, 0xa00147fe, 0x2455909f, 0xd9347790, 0x0000141c, 0x4bfe9abf, 0x90080c01, 0xff0d2cbb, 0x0000c17e, 0xeb00a433, 0x3f0c30b4, 0x0c943339, 0x043118e2, 0x0f001033, 0xb0011933, 0x3e043d00, 0x9800b971, 0x2cd9023f, 0x98000014, 0x34580431, 0x3f5fa00a, 0x0339989f, 0xb5183690, 0xff090159, 0xf43379a0, @@ -1570,11 +1570,11 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x00000000, 0x00000001, 0x0000000e, 0x00000000, 0x08000000, 0x08400000, 0x08800000, 0x08c300a7, 0x09000000, 0x09400000, 0x09800000, 0x09c00000, 0x0a01c000, 0x0a404038, 0x0a804040, 0x0ac04048, 0x0b004050, 0x0b420058, 0x0b8201ab, 0x11800000, 0x11c00000, 0x12000000, 0x12400000, 0x12800000, - 0x12c00000, 0x00000000, 0x00000000, 0x00000001, 0x00001c08, 0x00101c09, 0x00201c0a, 0x0000bd08, - 0x00209d09, 0x00309d0a, 0x00011f08, 0x00113e09, 0x00311e0a, 0x00010309, 0x00000000, 0x0000ffff, - 0x00003b00, 0x46020f1f, 0x43010f1f, 0x44020f1f, 0x45020f1f, 0x601207ef, 0x601307ef, 0x601407ef, - 0x601507ef, 0x801607ef, 0x253207c2, 0x25330fc2, 0x25340fc2, 0x25350fc2, 0x1152079d, 0x1253079d, - 0x7014079d, 0x7015079d, 0x601203c8, 0x601307c8, 0x601407c8, 0xbb150720, 0x02172701, 0x00000000, + 0x12c00000, 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00001c08, 0x00101c09, 0x00201c0a, + 0x0000bd08, 0x00209d09, 0x00309d0a, 0x00011f08, 0x00113e09, 0x00311e0a, 0x00010309, 0x00000000, + 0x0000ffff, 0x00003b00, 0x46020f1f, 0x43010f1f, 0x44020f1f, 0x45020f1f, 0x601207ef, 0x601307ef, + 0x601407ef, 0x601507ef, 0x801607ef, 0x253207c2, 0x25330fc2, 0x25340fc2, 0x25350fc2, 0x1152079d, + 0x1253079d, 0x7014079d, 0x7015079d, 0x601203c8, 0x601307c8, 0x601407c8, 0xbb150720, 0x02172701, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -2269,8 +2269,8 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0xf0cc97fc, 0xc5e27e17, 0x63cc4ffc, 0xc48564fa, 0x176bd707, 0x7693db62, 0xcee1dbf7, 0x0ec5a1fa, - 0x956b7a40, 0x90bcaaf7, 0xdea25edb, 0x9aaef423, 0x930f31b1, 0x6ce8df20, 0xa1e5e4d9, 0xc55f48a9, + 0x69e9060c, 0xe6ca2d91, 0xac20edf2, 0xeafeafcc, 0xfb3a453a, 0x7158de23, 0xaef7305e, 0xd220040f, + 0x30867660, 0xbc4af25f, 0xbc09e1ed, 0xab87e0fc, 0x8db5cb00, 0x30cfe9a4, 0xc1a3eea2, 0x79a1340e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, diff --git a/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h b/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h index 106ffe9e18..61230d1040 100644 --- a/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h +++ b/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h @@ -33,7 +33,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = { - 0x00fec0d0, 0x0004fe00, 0x0017167e, 0x08f802f8, 0xa4b300f8, 0x8c890a00, 0x9abf000f, 0x1100a0b3, + 0x00fec0d0, 0x0004fe00, 0x0017167e, 0x08f802f8, 0xa4b300f8, 0x9c890a00, 0x9abf000f, 0x1100a0b3, 0x0d00b0b3, 0xa001aa98, 0xf8a43dba, 0x0a02f800, 0xbd00f8ff, 0xfc30f494, 0x40fe02f9, 0x04009001, 0x0db209a0, 0x0003237e, 0xa4b3afb2, 0x0dbf1601, 0x0a01d4b3, 0x002e8989, 0xa43d9d20, 0x00006b3e, 0xfc09040a, 0x0bf4f9a6, 0xfbff0a05, 0x337e0405, 0xa0330000, 0xa0330a04, 0x02f80600, 0xb37e00f8, @@ -72,57 +72,57 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x3e00000e, 0xb2000491, 0x01147e1a, 0x092e7e00, 0x0a747e00, 0x0e1f9800, 0x000f1998, 0xf4f9a6fc, 0x1ab22a18, 0x4cb25bb2, 0x0002f47e, 0xb3091998, 0xb2180090, 0x05f57e8a, 0xb3a0b200, 0x7e0c01a4, 0x3e00000e, 0x000004c9, 0x0a9b7e01, 0xa6fc0f00, 0x251bf40f, 0x90b339bf, 0x6ab22000, 0xee023bb2, - 0x0005397e, 0x3400a9b3, 0x04f63eff, 0x3eef0000, 0x400004f6, 0x0ab2fe0c, 0x890c85fb, 0xbf000f98, - 0x8900f89a, 0xbf000f8c, 0x8900f89a, 0xbf000f9c, 0x0096b099, 0xf00bacf0, 0x00f801a6, 0x000fa089, - 0xa9a099bf, 0x000f9889, 0xa9b599bf, 0x0f00f801, 0x0fa48901, 0xf89fa000, 0xb222f900, 0x7eb2b2a0, - 0x89000a74, 0xbf000fa0, 0xa609bf9f, 0x110bf4f9, 0x000f9889, 0x09989fbf, 0xf4f9a601, 0x988d3318, - 0x0e98000f, 0xbfd9bf01, 0x029ebb2f, 0x18f49fa6, 0xbdd9bf20, 0x92e9bc14, 0xa0909fbc, 0x0fa08929, - 0xa099bf00, 0xb5d9bf09, 0x903e0109, 0x01010005, 0x000a9b7e, 0x21fb1ab2, 0x000a747e, 0x000f9c8f, - 0x9990f9bf, 0x7ef9a001, 0xf8000a9b, 0x8002f900, 0xbf000fac, 0x0196b009, 0x7e070df4, 0x7e00000e, - 0x3e000a8f, 0x8e0005b3, 0x18001060, 0xefbf41a9, 0x9ac4abb2, 0xf4afa6ff, 0xeaa0050d, 0xb604a994, - 0xa9bc02a4, 0x0fac89a0, 0x10bb9000, 0x7ea0a9bc, 0xf8000bee, 0x9812f900, 0x909803a9, 0x24019003, - 0x517e1ab2, 0x9c89000c, 0x99bf000f, 0x150094b3, 0x7e100a90, 0xb2000c51, 0x05c77e0a, 0x062b3e00, - 0x8a1bb200, 0x7e001064, 0x89000bee, 0xbf000f8c, 0x410f1899, 0x9918a4bd, 0xf4f92641, 0x010a050d, - 0x22f911fb, 0x000f8c82, 0xb0b229bf, 0x000f9881, 0x7e249b90, 0xbf000c0f, 0xbc2abf19, 0xaa900009, - 0x0c517e10, 0xb529bf00, 0x19bf0490, 0x18f409a6, 0x1078890b, 0x067d3e00, 0x107c8900, 0xbf9abf00, - 0x10bb902b, 0x000c0f7e, 0x30f421fb, 0x0f9c89fc, 0xbf82f900, 0x0090b399, 0x89010f10, 0xa0000fa4, - 0x08453e9f, 0x0f8c8900, 0x0148fe00, 0x95bf91b2, 0x343d243d, 0x608064bd, 0x94870010, 0x9084000f, - 0x8890000f, 0x06d23e24, 0x3d09bf00, 0x01999224, 0x09bf09a0, 0x000fac8e, 0xb6049f94, 0x9fbc0294, + 0x0005397e, 0x3400a9b3, 0x04f63eff, 0x3eef0000, 0x400004f6, 0x0ab2fe0c, 0x890c85fb, 0xbf000fa8, + 0x8900f89a, 0xbf000f9c, 0x8900f89a, 0xbf000fac, 0x0096b099, 0xf00bacf0, 0x00f801a6, 0x000fb089, + 0xa9a099bf, 0x000fa889, 0xa9b599bf, 0x0f00f801, 0x0fb48901, 0xf89fa000, 0xb222f900, 0x7eb2b2a0, + 0x89000a74, 0xbf000fb0, 0xa609bf9f, 0x110bf4f9, 0x000fa889, 0x09989fbf, 0xf4f9a601, 0xa88d3318, + 0x0e98000f, 0xbfd9bf01, 0x029ebb2f, 0x18f49fa6, 0xbdd9bf20, 0x92e9bc14, 0xa0909fbc, 0x0fb08929, + 0xa099bf00, 0xb5d9bf09, 0x903e0109, 0x01010005, 0x000a9b7e, 0x21fb1ab2, 0x000a747e, 0x000fac8f, + 0x9990f9bf, 0x7ef9a001, 0xf8000a9b, 0x8002f900, 0xbf000fbc, 0x0196b009, 0x7e070df4, 0x7e00000e, + 0x3e000a8f, 0x8e0005b3, 0x18001070, 0xefbf41a9, 0x9ac4abb2, 0xf4afa6ff, 0xeaa0050d, 0xb604a994, + 0xa9bc02a4, 0x0fbc89a0, 0x10bb9000, 0x7ea0a9bc, 0xf8000bee, 0x9812f900, 0x909803a9, 0x24019003, + 0x517e1ab2, 0xac89000c, 0x99bf000f, 0x150094b3, 0x7e100a90, 0xb2000c51, 0x05c77e0a, 0x062b3e00, + 0x8a1bb200, 0x7e001074, 0x89000bee, 0xbf000f9c, 0x410f1899, 0x9918a4bd, 0xf4f92641, 0x010a050d, + 0x22f911fb, 0x000f9c82, 0xb0b229bf, 0x000fa881, 0x7e249b90, 0xbf000c0f, 0xbc2abf19, 0xaa900009, + 0x0c517e10, 0xb529bf00, 0x19bf0490, 0x18f409a6, 0x1088890b, 0x067d3e00, 0x108c8900, 0xbf9abf00, + 0x10bb902b, 0x000c0f7e, 0x30f421fb, 0x0fac89fc, 0xbf82f900, 0x0090b399, 0x89010f10, 0xa0000fb4, + 0x08453e9f, 0x0f9c8900, 0x0148fe00, 0x95bf91b2, 0x343d243d, 0x708064bd, 0xa4870010, 0xa084000f, + 0x8890000f, 0x06d23e24, 0x3d09bf00, 0x01999224, 0x09bf09a0, 0x000fbc8e, 0xb6049f94, 0x9fbc0294, 0x909ebc90, 0x99b399bf, 0xbf013d00, 0xb949bf7f, 0xf9a60099, 0xbf0f0bf4, 0x7eec0b1a, 0x3e000a95, - 0xbf000742, 0x0090b349, 0x0859983d, 0xfe940fbf, 0x02f4b604, 0x8ef0febc, 0xbc000fac, 0x9fa6f0fe, + 0xbf000742, 0x0090b349, 0x0859983d, 0xfe940fbf, 0x02f4b604, 0x8ef0febc, 0xbc000fbc, 0x9fa6f0fe, 0xbf221bf4, 0x92b4bd49, 0x49a00199, 0x99b949bf, 0xa079a000, 0x7e1abf15, 0xb0000a89, 0x1ff500a6, - 0x0fbf00f9, 0xfd9409bf, 0x049e9404, 0xbc0294b6, 0xac8e909e, 0x9ebc000f, 0x01999890, 0xbc02f4b6, + 0x0fbf00f9, 0xfd9409bf, 0x049e9404, 0xbc0294b6, 0xbc8e909e, 0x9ebc000f, 0x01999890, 0xbc02f4b6, 0xfebcf0fd, 0x019998f0, 0xbf01f9b5, 0x049f9409, 0xbc0294b6, 0x9ebc909f, 0x019e9890, 0x9f9409bf, - 0x0294b604, 0x8f909fbc, 0xbc000fb4, 0xe9a6909f, 0xbf2c1bf4, 0x9409bf0f, 0x9e9404fd, 0x0294b604, - 0x8e909ebc, 0xbc000fac, 0x9998909e, 0x02f4b601, 0xbcf0fdbc, 0x9998f0fe, 0x01f9b501, 0x9f9409bf, - 0x0294b604, 0x8f909fbc, 0xbc000fac, 0x9998909f, 0x03999801, 0x1abf19a0, 0x000a617e, 0x1000a4b3, + 0x0294b604, 0x8f909fbc, 0xbc000fc4, 0xe9a6909f, 0xbf2c1bf4, 0x9409bf0f, 0x9e9404fd, 0x0294b604, + 0x8e909ebc, 0xbc000fbc, 0x9998909e, 0x02f4b601, 0xbcf0fdbc, 0x9998f0fe, 0x01f9b501, 0x9f9409bf, + 0x0294b604, 0x8f909fbc, 0xbc000fbc, 0x9998909f, 0x03999801, 0x1abf19a0, 0x000a617e, 0x1000a4b3, 0xeb0b1abf, 0x000a957e, 0x0007fa3e, 0x8bb21abf, 0x000a897e, 0xf400a6b0, 0x2210401f, 0x01331001, - 0x06013433, 0x09bf06bf, 0x94ff2ec4, 0x94b6049f, 0x909fbc02, 0x000fac8f, 0xbf909fbc, 0xf5e9a699, - 0xbffeb31b, 0x009db309, 0x1abffea4, 0x7efe0b4b, 0x3e000a95, 0x330006d2, 0x890a0030, 0xa0001060, - 0x0ad07e96, 0x0485fb00, 0x9c8922f9, 0x99bf000f, 0xcd009db3, 0x10948900, 0x899fbf00, 0xbf000f98, - 0x0099b999, 0x0bf4f9a6, 0x0f8c890f, 0x0b9abf00, 0x0a957eec, 0x0f988e00, 0x8fe9bf00, 0x90001094, - 0xe9a00199, 0x99b9e9bf, 0xbff9a000, 0x0094b3e9, 0x107c8f1f, 0x10788e00, 0xbffcbf00, 0x0fa08de9, - 0xa0f9a000, 0x90d9bfec, 0xd9a00199, 0x00107c8f, 0x99bff9bf, 0x0a0094b3, 0x003e04bd, 0xf9bf0009, + 0x06013433, 0x09bf06bf, 0x94ff2ec4, 0x94b6049f, 0x909fbc02, 0x000fbc8f, 0xbf909fbc, 0xf5e9a699, + 0xbffeb31b, 0x009db309, 0x1abffea4, 0x7efe0b4b, 0x3e000a95, 0x330006d2, 0x890a0030, 0xa0001070, + 0x0ad07e96, 0x0485fb00, 0xac8922f9, 0x99bf000f, 0xcd009db3, 0x10a48900, 0x899fbf00, 0xbf000fa8, + 0x0099b999, 0x0bf4f9a6, 0x0f9c890f, 0x0b9abf00, 0x0a957eec, 0x0fa88e00, 0x8fe9bf00, 0x900010a4, + 0xe9a00199, 0x99b9e9bf, 0xbff9a000, 0x0094b3e9, 0x108c8f1f, 0x10888e00, 0xbffcbf00, 0x0fb08de9, + 0xa0f9a000, 0x90d9bfec, 0xd9a00199, 0x00108c8f, 0x99bff9bf, 0x0a0094b3, 0x003e04bd, 0xf9bf0009, 0x98039998, 0x003e0390, 0x2fbf0009, 0xa6040998, 0x3e08f4f9, 0x000c517e, 0x900d0998, 0x90b3240a, 0x517e0800, 0x0ab2000c, 0x0005c77e, 0x99bf19bf, 0x1f0090b3, 0x999819bf, 0x03909803, 0x0009083e, - 0x000f9882, 0x00107c81, 0xb3100a90, 0x89bf0004, 0xbf001098, 0x0094b399, 0x09283e17, 0x10988f00, - 0x90f9bf00, 0xf9a00199, 0x000a877e, 0x32f921fb, 0x000f9c81, 0xe90019bf, 0xc00099b3, 0x0a747e00, - 0x9219bf00, 0x19a00199, 0x9db319bf, 0x8900a800, 0xbf00109c, 0x0099b399, 0x648f009d, 0xf9bf0010, - 0x0a0094b3, 0x703e04bd, 0xf9980009, 0x03909803, 0x8c8314bd, 0x6482000f, 0xaa3e0010, 0x517e0009, + 0x000fa882, 0x00108c81, 0xb3100a90, 0x89bf0004, 0xbf0010a8, 0x0094b399, 0x09283e17, 0x10a88f00, + 0x90f9bf00, 0xf9a00199, 0x000a877e, 0x32f921fb, 0x000fac81, 0xe90019bf, 0xc00099b3, 0x0a747e00, + 0x9219bf00, 0x19a00199, 0x9db319bf, 0x8900a800, 0xbf0010ac, 0x0099b399, 0x748f009d, 0xf9bf0010, + 0x0a0094b3, 0x703e04bd, 0xf9980009, 0x03909803, 0x9c8314bd, 0x7482000f, 0xaa3e0010, 0x517e0009, 0x0a90000c, 0x0c517e10, 0x7e0ab200, 0xbf0005c7, 0x410f1839, 0x99182ebf, 0xf4f92641, 0x0101050d, - 0x1100e0b3, 0x98032998, 0x0a900390, 0x0004b324, 0x10988fd1, 0xb3f9bf00, 0xb21b0090, 0x08487ef0, - 0x9209bf00, 0x09a00199, 0x94b309bf, 0xe03ef300, 0x10b30009, 0xa4890e01, 0x99bf000f, 0x160194b3, - 0xa489f4bd, 0x0100000f, 0x0e7e9fa0, 0xf43e0000, 0x04bd0009, 0x000a9b7e, 0x31fb0ab2, 0x9c8932f9, - 0x99bf000f, 0xf70fa3b2, 0x550094b3, 0x4b00a0b3, 0x0005987e, 0x000f9881, 0x000f8c82, 0x2abf10bf, - 0x900030bc, 0x517e10aa, 0x29bf000c, 0xbf0490b5, 0xf409a619, 0x78890b18, 0x423e0010, 0x7c89000a, + 0x1100e0b3, 0x98032998, 0x0a900390, 0x0004b324, 0x10a88fd1, 0xb3f9bf00, 0xb21b0090, 0x08487ef0, + 0x9209bf00, 0x09a00199, 0x94b309bf, 0xe03ef300, 0x10b30009, 0xb4890e01, 0x99bf000f, 0x160194b3, + 0xb489f4bd, 0x0100000f, 0x0e7e9fa0, 0xf43e0000, 0x04bd0009, 0x000a9b7e, 0x31fb0ab2, 0xac8932f9, + 0x99bf000f, 0xf70fa3b2, 0x550094b3, 0x4b00a0b3, 0x0005987e, 0x000fa881, 0x000f9c82, 0x2abf10bf, + 0x900030bc, 0x517e10aa, 0x29bf000c, 0xbf0490b5, 0xf409a619, 0x88890b18, 0x423e0010, 0x8c89000a, 0x9abf0010, 0xbb902bbf, 0x0c0f7e10, 0x092e7e00, 0xb3010f00, 0x7e0a00a4, 0x0f00000e, 0xfbfab201, - 0x00a0b331, 0x03a99811, 0x99b9afbf, 0xf0f9a600, 0x00f80bac, 0xf41032f4, 0x5c8f1132, 0xf9bf0005, - 0xa0019990, 0xf800f8f9, 0x10107e00, 0x7e00f800, 0xf8001842, 0x184a7e00, 0x8f00f800, 0xbf00055c, + 0x00a0b331, 0x03a99811, 0x99b9afbf, 0xf0f9a600, 0x00f80bac, 0xf41032f4, 0x608f1132, 0xf9bf0005, + 0xa0019990, 0xf800f8f9, 0x10107e00, 0x7e00f800, 0xf8001842, 0x184a7e00, 0x8f00f800, 0xbf000560, 0x0094b3f9, 0x1032f41a, 0xbd1132f4, 0x7eee0ba4, 0xf4000a95, 0x31f41031, 0xbf00f811, 0x019992f9, 0xf9bff9a0, 0x0a0094b3, 0xf41031f4, 0x00f81131, 0x0038a77e, 0xc9fe00f8, 0x1495b601, 0x3c089033, 0xf4089630, 0x9033130c, 0x90332002, 0x90333403, 0x1c3e1800, 0x9033000b, 0x9033280f, 0x94331810, 0x0c3e1e0a, 0x8a7e000b, 0x00f80006, 0x0013bc7e, 0xb07e00f8, 0x00f80013, 0x00f802f8, 0x00f802f8, - 0x0038bc7e, 0x000ad67e, 0x0038a77e, 0x02f900f8, 0x0038bc7e, 0xcf020049, 0xc8800099, 0x0fbf0010, + 0x0038bc7e, 0x000ad67e, 0x0038a77e, 0x02f900f8, 0x0038bc7e, 0xcf020049, 0xd8800099, 0x0fbf0010, 0xf4049ffd, 0x487e170b, 0x8a7e0008, 0x0fbf0006, 0xfa010049, 0x623e009f, 0xa4bd000b, 0x957eda0b, 0xa77e000a, 0x01fb0038, 0x0038bc7e, 0x0018397e, 0x0800a0b3, 0x00068a7e, 0x0038a77e, 0x94bd00f8, 0x000b8d3e, 0x3cf8b93c, 0x999099af, 0xf49ca601, 0x00f8f508, 0xa23ea9b2, 0x9b20000b, 0x9001cc92, @@ -144,8 +144,8 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0xfd1094b6, 0x39fa059e, 0x024fbb06, 0xbc303fbc, 0x44b3505f, 0xaffe9d00, 0x00b7fe00, 0xf800cbfe, 0x7e170003, 0x3300186b, 0x3d0600a4, 0x0a9b7e04, 0x0ddd7e00, 0xfb0a3200, 0xf4010971, 0xe43dfc30, 0x7e009130, 0xf4000c82, 0x00f80430, 0x0efc30f4, 0x00e13001, 0x000c827e, 0xf80430f4, 0x0a747e00, - 0x10cc8f00, 0xb3f9bf00, 0xbf0f0090, 0x019992f9, 0x003ef9a0, 0xea7e000e, 0x030b0000, 0x00184a7e, - 0x000a9b7e, 0x747e00f8, 0xcc8e000a, 0xefbf0010, 0xf9a6ff09, 0xbf0e0bf4, 0x019990e9, 0x2c3ee9a0, + 0x10dc8f00, 0xb3f9bf00, 0xbf0f0090, 0x019992f9, 0x003ef9a0, 0xea7e000e, 0x030b0000, 0x00184a7e, + 0x000a9b7e, 0x747e00f8, 0xdc8e000a, 0xefbf0010, 0xf9a6ff09, 0xbf0e0bf4, 0x019990e9, 0x2c3ee9a0, 0xea7e000e, 0x030b0000, 0x00184a7e, 0x000a9b7e, 0x12f900f8, 0xafbfb9b2, 0xa0b29e3f, 0xb204d192, 0x18fe20cb, 0x1cb2019e, 0x1801fe35, 0xfe35029e, 0x03991802, 0xbf03f935, 0x04aa90aa, 0x7e7e0aa0, 0x09bf000b, 0xa09091bc, 0xf411fb09, 0x62f9f430, 0xb2b2a3b2, 0xd532c6b2, 0x0c00b4b3, 0x043d09f8, @@ -156,20 +156,20 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x040dc4bd, 0x3998e5f9, 0x9849a001, 0x1db20639, 0x2bb26cb2, 0x900140fe, 0x0ab22000, 0x41fe95f9, 0x0142fe01, 0x90271190, 0x1ab22622, 0x5e7e2bb2, 0x020a0038, 0x787eab32, 0x0abf0038, 0x00043998, 0x3f95f901, 0x7e2b3f1a, 0xbf003878, 0x009b7e3a, 0xfb0a3200, 0x5d330c65, 0x3dff5c00, 0x0f4b3e04, - 0x3dbcb200, 0x8aabb2d4, 0x7e0010d0, 0xf8000e6b, 0x0dbcb200, 0x8aabb201, 0x7e0010d0, 0xf8000e6b, + 0x3dbcb200, 0x8aabb2d4, 0x7e0010e0, 0xf8000e6b, 0x0dbcb200, 0x8aabb201, 0x7e0010e0, 0xf8000e6b, 0xb212f900, 0xb3b132a0, 0xf80a00a4, 0x100e3e09, 0x2e808900, 0x0b9abf00, 0x00de7eff, 0xff19c400, 0x0301008f, 0xbc099e94, 0xefcfe0ef, 0x8099b800, 0x94b60001, 0x009dcf09, 0xf0020918, 0x09352095, 0xf40fa602, 0xf63e411b, 0xf918000f, 0x2094f002, 0x3f340bf4, 0x009433f9, 0xf8cbbc0b, 0x000fef3e, 0xf001f918, 0x9990ff94, 0x049afd03, 0xf6f0f9bc, 0xff3e00ef, 0x1bc4000f, 0x8cfc0aff, 0xa6002e68, - 0xc91bf4fd, 0x002e8089, 0x9b7e9abf, 0x11fb0000, 0xfc8b02f9, 0x127e0010, 0xa0320000, 0x0f00a033, - 0x0000ea7e, 0x7eff0bc4, 0x8900184a, 0xbf0010fc, 0x11008990, 0x899fbf00, 0x180010ec, 0x9e35180e, + 0xc91bf4fd, 0x002e8089, 0x9b7e9abf, 0x11fb0000, 0x0c8b02f9, 0x127e0011, 0xa0320000, 0x0f00a033, + 0x0000ea7e, 0x7eff0bc4, 0x8900184a, 0xbf00110c, 0x11108990, 0x899fbf00, 0x180010fc, 0x9e35180e, 0xf40fa60e, 0x0918101b, 0x00943319, 0x3ea4bd0a, 0x1800107a, 0xb4331d0b, 0xa4bd0a00, 0x00106f3e, - 0x3d200a90, 0x13607ec4, 0x00a6b000, 0x3d0e1ef4, 0x19093594, 0x00110089, 0x01fb90a0, 0x89ffa4f0, + 0x3d200a90, 0x13607ec4, 0x00a6b000, 0x3d0e1ef4, 0x19093594, 0x00111089, 0x01fb90a0, 0x89ffa4f0, 0x8c003131, 0xbc003124, 0xacbcd0a9, 0x3fdf3fa0, 0x31318cae, 0xffe9c400, 0x20909cbc, 0x3124899f, 0xfff4f000, 0x20f0f9bc, 0x20943dfe, 0xf900f8d9, 0x31318922, 0xffa0c400, 0x3f2009bc, 0x33a1322e, - 0x7e0c00e0, 0x3e00107c, 0x8f0010e0, 0x3f001104, 0xf4a926f9, 0x947d0d1b, 0xf975fe20, 0x01f97502, + 0x7e0c00e0, 0x3e00107c, 0x8f0010e0, 0x3f001114, 0xf4a926f9, 0x947d0d1b, 0xf975fe20, 0x01f97502, 0x00313189, 0x91209f3f, 0x00312489, 0x3d0009bc, 0x20092094, 0x3124892f, 0xfff4f000, 0x20f0f9bc, - 0xf921fbf1, 0x11048f52, 0x32943d00, 0xb2c332b4, 0x35f5b2a2, 0x143d01f9, 0x00113a3e, 0x1110203f, + 0xf921fbf1, 0x11148f52, 0x32943d00, 0xb2c332b4, 0x35f5b2a2, 0x143d01f9, 0x00113a3e, 0x1110203f, 0x01229001, 0x16000033, 0x3b320a32, 0x0010af7e, 0x33015918, 0x35070094, 0x14260150, 0xfbe008f4, 0xfc30f451, 0xb13212f9, 0x900140fe, 0x0bb20800, 0x0000127e, 0x0e1800bf, 0x0014331d, 0x4f02f806, 0xf3f1000b, 0x19c40000, 0xf49fa6ff, 0xed320b0c, 0x9f3ef43d, 0x02f80011, 0xed32f43d, 0x00119f3e, @@ -179,7 +179,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x0a747eb1, 0xfe0ab200, 0x00900140, 0x7e0bb208, 0xbf000012, 0x18f43d00, 0x163e1d0d, 0xe9180012, 0x01ff1020, 0x2620ee90, 0x0d1bf491, 0x0100943d, 0x233ee920, 0xf9c40012, 0xe009bcff, 0x08f4fd26, 0x7e043de0, 0x32000a9b, 0x0415fb0a, 0x0011d87e, 0x0600a433, 0x00f802f8, 0xa4f082f9, 0x31008fff, - 0x31188e00, 0x58fa7c00, 0xb298ea3c, 0xbdc632b7, 0xff94f034, 0x00056088, 0x8120597c, 0x3e001104, + 0x31188e00, 0x58fa7c00, 0xb298ea3c, 0xbdc632b7, 0xff94f034, 0x00056488, 0x8120597c, 0x3e001114, 0x52001354, 0x29e40122, 0x9494ffff, 0x034ffe08, 0xb31ff995, 0xd0100190, 0x03000000, 0xf594f0ff, 0xbf00d51b, 0x01008e89, 0x089f9500, 0xfffff9e4, 0x18f59ea6, 0x99900010, 0x0894b601, 0x473e89a0, 0x1f580013, 0x02195801, 0x1bf4f966, 0x000b4945, 0x000093f1, 0x0031248f, 0x18909fbc, 0x19180190, @@ -208,36 +208,36 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x0c004d81, 0xcf0b004c, 0xcecf00df, 0x00d9cf00, 0x1bf4f9a6, 0xb5aea0f5, 0x00f801af, 0xcf0b0049, 0xaabf0099, 0xf8a29abc, 0xb242f900, 0xb2b3b2a0, 0x00c0b3c1, 0x0b004929, 0xb20092cf, 0x0000b394, 0xf93ab212, 0x00a03305, 0x3e010a0a, 0xcf0015e8, 0x92bb0049, 0xf491a602, 0x04b3e608, 0xa43d0a00, - 0x0015e83e, 0x05f93ab2, 0x000041fb, 0xd24e0041, 0x0000055c, 0x90fc00f8, 0x0015ea7e, 0xf90188fe, - 0x00289880, 0x8cd880f9, 0x9800000f, 0x47fe0088, 0xbd87a001, 0x0387b570, 0xfe0010f7, 0xb7b600a4, + 0x0015e83e, 0x05f93ab2, 0x000041fb, 0xd24e0041, 0x00000560, 0x90fc00f8, 0x0015ea7e, 0xf90188fe, + 0x00289880, 0x9cd880f9, 0x9800000f, 0x47fe0088, 0xbd87a001, 0x0387b570, 0xfe0010f7, 0xb7b600a4, 0x1fb9f002, 0xf9001bf7, 0x7e00f890, 0x3e0015ea, 0xf9001647, 0x3550daf2, 0x50db0000, 0x7e000033, - 0x7e0015f6, 0xf7000b68, 0x8cd80010, 0x9800000f, 0x87980088, 0x0074fe00, 0xb6028798, 0x79f00277, + 0x7e0015f6, 0xf7000b68, 0x9cd80010, 0x9800000f, 0x87980088, 0x0074fe00, 0xb6028798, 0x79f00277, 0x0017f71f, 0x28a080fc, 0x88fe80fc, 0xf8f0fb00, 0xdaf2f901, 0x00003550, 0x003350db, 0x15f67e00, 0x0b2e7e00, 0x16473e00, 0x1832f400, 0x50daf2f9, 0xdb000033, 0x00003150, 0x0015f67e, 0x000b207e, 0x0016473e, 0xf91832f4, 0x0188fef2, 0xa27e80f9, 0x80fc0037, 0xfb0088fe, 0xb201f8f0, 0xb0afb2a9, 0x1ef400a6, 0xb0bab22b, 0x1ef400b6, 0xacfaff13, 0xf496b9ff, 0x00f8051e, 0xf801aab9, 0x01bab900, 0xffacfaff, 0x1ff496b9, 0x16d83ef0, 0x01afb900, 0xb6b0bab2, 0xd81ff400, 0x0016dd3e, 0x95e0abff, - 0xbf9510a9, 0x01b9fd10, 0xbb01affd, 0xa4b600ab, 0x00aebb10, 0x62f900f8, 0x0005dcdf, 0xd9ffbf00, - 0x000005e0, 0xf4bd9fa0, 0x01010089, 0x4f009ff6, 0x99b87fff, 0xf6003f00, 0x00df009f, 0xb803ff00, + 0xbf9510a9, 0x01b9fd10, 0xbb01affd, 0xa4b600ab, 0x00aebb10, 0x62f900f8, 0x0005ecdf, 0xd9ffbf00, + 0x000005f0, 0xf4bd9fa0, 0x01010089, 0x4f009ff6, 0x99b87fff, 0xf6003f00, 0x00df009f, 0xb803ff00, 0x00010099, 0x8f009ff6, 0xb800ff80, 0x000a0099, 0x4f009ff6, 0x99b81000, 0xf6024a00, 0x00d6009f, - 0x85400000, 0xd0011c00, 0x000005f0, 0x01020084, 0x10000083, 0xefaaa0d2, 0x0afd01be, 0x1a277e08, - 0x04a6fd00, 0x00280bf5, 0xfd0049cf, 0x0bf50493, 0xf0de001e, 0xbd000005, 0x95f2fff4, 0xff90e9a0, + 0x85400000, 0xd0011c00, 0x00000600, 0x01020084, 0x10000083, 0xefaaa0d2, 0x0afd01be, 0x1a277e08, + 0x04a6fd00, 0x00280bf5, 0xfd0049cf, 0x0bf50493, 0x00de001e, 0xbd000006, 0x95f2fff4, 0xff90e9a0, 0x04ee9001, 0xf504f4b3, 0x0017e33e, 0xf00059cf, 0x1bf40194, 0x1f3cf4fa, 0x93f009b2, 0x0699fa05, 0x3cf503f8, 0x3cf59004, 0x3cf59003, 0x3cf5ac54, 0x3cf5c404, 0x09b2d033, 0xfa0393f0, 0x03f80599, 0xbf003cf4, 0x01e9920e, 0x0df491a6, 0x010e9825, 0xa601e992, 0x1a0df491, 0x92020e98, 0x91a601e9, - 0x980f0df4, 0xe992030e, 0xf591a601, 0xbdff700c, 0x05f0df94, 0xdcd00000, 0xb5000005, 0xf9a003f9, - 0xb501f9b5, 0x0ea002f9, 0x004a6c7e, 0x0005e0d9, 0xbd99bf00, 0xfb09a0a4, 0x18957e61, 0xffa4f000, + 0x980f0df4, 0xe992030e, 0xf591a601, 0xbdff700c, 0x0600df94, 0xecd00000, 0xb5000005, 0xf9a003f9, + 0xb501f9b5, 0x0ea002f9, 0x004a6c7e, 0x0005f0d9, 0xbd99bf00, 0xfb09a0a4, 0x18957e61, 0xffa4f000, 0x31f400f8, 0x0028f400, 0x02f800f8, 0x477e00f8, 0x00f80019, 0x001434d9, 0x0d9b1800, 0x7e0c9a18, 0xf8001a12, 0x1a127e00, 0x7e00f800, 0xf80019cd, 0x14008900, 0x0099cf02, 0xf40194f0, 0xf17e160b, - 0x008f003c, 0xf9ce0213, 0x0195f000, 0xf800f9f7, 0xf802f800, 0xf830f400, 0x0005dcdf, 0xbf02f900, + 0x008f003c, 0xf9ce0213, 0x0195f000, 0xf800f9f7, 0xf802f800, 0xf830f400, 0x0005ecdf, 0xbf02f900, 0x0149feff, 0xa0089990, 0xd9f43d9f, 0x00002e89, 0x004f9f20, 0x00ffcf06, 0xcf07004e, 0x004900ee, 0x0099cf02, 0x95049ffd, 0xeeb910ef, 0x049efd00, 0xff00ffb9, 0x09c4049f, 0x070bf401, 0x003b797e, 0x100009e4, 0x0f2f0bf4, 0x0149fe01, 0x0289008e, 0x20079990, 0x00e9ce9f, 0x9ffdfe0f, 0x00e9f704, 0x001408d9, 0xfe9abf00, 0x010c014b, 0x7e07bb90, 0xe400006e, 0x73800009, 0x7e080090, 0x49001871, - 0x90f70100, 0x0149fe00, 0xbf089990, 0x05dcd99e, 0x9fbf0000, 0x002e89d9, 0xa69a3f00, 0x070bf4ef, + 0x90f70100, 0x0149fe00, 0xbf089990, 0x05ecd99e, 0x9fbf0000, 0x002e89d9, 0xa69a3f00, 0x070bf4ef, 0x003a317e, 0x0a0805fb, 0xf900f801, 0x03a99802, 0x94f0a0b2, 0x0d0bf401, 0x277eaabf, 0x673e001a, 0xa9bf0019, 0x98009acf, 0x0998030f, 0x020e9801, 0xff02f4f0, 0x9ea694a9, 0x320b9cf0, 0x00f0b39a, - 0x0096300c, 0x320b9cf0, 0xf401fb9a, 0x12f9ec30, 0x900149fe, 0xdcd10899, 0xa0000005, 0x019bb59a, + 0x0096300c, 0x320b9cf0, 0xf401fb9a, 0x12f9ec30, 0x900149fe, 0xecd10899, 0xa0000005, 0x019bb59a, 0xb5029cb5, 0x9bb2039e, 0xdcb219bf, 0xda0140fe, 0x0000194b, 0xa0180090, 0x15a97e09, 0xbf0fbf00, 0xf4f9a619, 0x317e070b, 0x15fb003a, 0xb8008e14, 0x00efcf00, 0xf404f9c4, 0xa43d071b, 0xf9c500f8, 0x00e9f604, 0x00f8010a, 0x00900089, 0xf00099ce, 0x0bf40194, 0xf1008f1e, 0x00f9ce00, 0xf71095f0, @@ -272,7 +272,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0xa6b0001d, 0x240cf409, 0x001da03e, 0x0049190f, 0x009ff711, 0x00f802f8, 0xb50294b6, 0x00f804b9, 0xb602af92, 0xb9bc0294, 0xf400f8f9, 0x82f9d430, 0x301590b4, 0xc1b027e1, 0x0ad1b00b, 0x94b6f4bd, 0x0c91b002, 0x900149fe, 0x9fa04499, 0x20079990, 0x0b99929f, 0x95b29fa0, 0xa0049992, 0x9297b29f, - 0x9fa00499, 0x0005dcdf, 0x90ffbf00, 0x4efe1499, 0xa0a6b201, 0x34ee909f, 0xb4b20209, 0x84bde9a0, + 0x9fa00499, 0x0005ecdf, 0x90ffbf00, 0x4efe1499, 0xa0a6b201, 0x34ee909f, 0xb4b20209, 0x84bde9a0, 0x14bd34bd, 0x001eef3e, 0x277e6ab2, 0x49bf001a, 0x4bfea2b2, 0x014cfe01, 0x9044bb90, 0x95f94bcc, 0xb31100b4, 0x008e0209, 0x9e0309b3, 0x010db300, 0x499800a8, 0xb27cb201, 0xfe5bb22a, 0xdd90014d, 0x3295f938, 0x0be0b40c, 0xa53ed4bd, 0x5fbf001e, 0xf9a6e9bf, 0x34381bf4, 0xe89827b0, 0x987fbf01, @@ -281,7 +281,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0xee9001dd, 0x0ab0b40c, 0x08f4dba6, 0x1ed53ea4, 0x02499800, 0x4dfe5cbf, 0xb22ab201, 0x34dd901b, 0xd53e95f9, 0x10b3001e, 0x49980f00, 0xb25cbf03, 0xf91bb22a, 0x4b903495, 0x11009433, 0x14bdff09, 0xa00e91b0, 0xa094bd79, 0x01339059, 0xb4046690, 0x39a60d90, 0xff1408f5, 0x900149fe, 0x9fbf4c99, - 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xf92c85fb, 0x2924d062, 0x093f0000, 0xb2fc30f4, + 0x0005ecd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xf92c85fb, 0x2924d062, 0x093f0000, 0xb2fc30f4, 0xb2b4b2a5, 0x33d3b2c2, 0x0111009d, 0xe44cb4bd, 0x1444da14, 0x947e0000, 0x94bd000b, 0x91b006b2, 0xc0008a00, 0x01fcdb02, 0x0cdc0000, 0x0d000002, 0xd0e43d1a, 0x00001444, 0x001dab7e, 0x09bf14bd, 0x1f1394b3, 0x98020998, 0xccdb040a, 0xdc000001, 0x00000344, 0x0d0091b0, 0x7e010e08, 0xbf001dab, @@ -295,10 +295,10 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x01943308, 0x0120b321, 0x0126b014, 0x0a0d08f4, 0x0224b3ff, 0x20803e11, 0x03fa9800, 0x0020823e, 0xff90dabf, 0x20dd9020, 0x1bf4fea6, 0xa6ff09c5, 0x0d1bf4a9, 0x0049190f, 0x009ff711, 0x30f402f8, 0xbd61fb04, 0xb5caa094, 0xc9b501cb, 0x140cd902, 0x9fbf0000, 0xfef830f4, 0x9bb50149, 0xb69aa001, - 0xfab811b5, 0x7e0002d8, 0xf4001a87, 0x00f80830, 0xf9e830f4, 0x05dcd252, 0x29bf0000, 0x900140fe, + 0xfab811b5, 0x7e0002d8, 0xf4001a87, 0x00f80830, 0xf9e830f4, 0x05ecd252, 0x29bf0000, 0x900140fe, 0x0ba01800, 0xb2010cb5, 0xb2d4b2e5, 0x0141fea3, 0xa02c1190, 0x0e067e19, 0x0a747e00, 0x010b9800, 0x40fe0abf, 0x20009001, 0xa37e0cb2, 0x0bb20020, 0x5db24cb2, 0xcc7e3ab2, 0xa032000d, 0x000a9b7e, - 0x000ddd7e, 0x29bf1fbf, 0xf9a60a32, 0x7e070bf4, 0xfb003a31, 0x30f41855, 0xd252f9e8, 0x000005dc, + 0x000ddd7e, 0x29bf1fbf, 0xf9a60a32, 0x7e070bf4, 0xfb003a31, 0x30f41855, 0xd252f9e8, 0x000005ec, 0x40fe29bf, 0x18009001, 0x0cb50ba0, 0xb2e5b201, 0xfea3b2d4, 0x11900141, 0x7e19a02c, 0x7e000e06, 0x98000a74, 0x0abf010b, 0x900140fe, 0x0cb22000, 0x0020a37e, 0x4cb20bb2, 0x3ab25db2, 0x000db97e, 0x9b7ea032, 0xdd7e000a, 0x1fbf000d, 0x0a3229bf, 0x0bf4f9a6, 0x3a317e07, 0x1855fb00, 0x3d7e040a, @@ -349,7 +349,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0xf9cf01c0, 0x4c99c700, 0x220090b3, 0xf60190b3, 0x223e02f8, 0xf9cf0027, 0x4c99c700, 0x390090b3, 0xf60190b3, 0x363e02f8, 0xa48f0027, 0x008901ad, 0x9ff601c1, 0xb8f4bd00, 0x00010099, 0xdf009ff6, 0x800000f2, 0x020099b8, 0x009ff602, 0xb2009fcf, 0x27363e9f, 0xe400f800, 0xc7ff00bf, 0xaeb2f0b9, - 0xdfd59fff, 0x00000564, 0x0027ab3e, 0x1bf49b26, 0x01f9581a, 0x1bf49d66, 0x3df97f12, 0x08e975a4, + 0xdfd59fff, 0x00000568, 0x0027ab3e, 0x1bf49b26, 0x01f9581a, 0x1bf49d66, 0x3df97f12, 0x08e975a4, 0x7501ff58, 0x00f809ef, 0x3f04ff90, 0x009433f9, 0xf8010adf, 0x0aa9b200, 0x00b0b302, 0x3db92008, 0xf900f8a4, 0xb3a0b202, 0x986500a0, 0x90b305a9, 0x0cd95e00, 0xbf000014, 0xe8aab89a, 0x277e0004, 0xa9e7001a, 0x9ab30168, 0xb34c0fff, 0xb6470090, 0xaab314a5, 0xb3400fff, 0x983b00a0, 0x94b6050e, @@ -359,7 +359,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x22f900f8, 0xb132a0b2, 0x350ac2b2, 0x690000b3, 0x94b309bf, 0x09986100, 0x0094b301, 0xe2048a5a, 0x1a277e00, 0xff1ec400, 0xa601a9c4, 0x091bf49e, 0xc73e943d, 0x0f180028, 0xf0f30908, 0xabc501e4, 0x01f4f002, 0xb604b9fd, 0xfe0902f4, 0x8a05bffd, 0xfd00e204, 0xbefd04b9, 0x1a877e05, 0xe2048a00, - 0x1a277e00, 0xb3010900, 0x20060020, 0x3ea43d29, 0x0a0028d5, 0xf421fb01, 0xdcdff830, 0xf9000005, + 0x1a277e00, 0xb3010900, 0x20060020, 0x3ea43d29, 0x0a0028d5, 0xf421fb01, 0xecdff830, 0xf9000005, 0xfeffbf52, 0x99900149, 0xa0a3b21c, 0x72b0b29f, 0x0ad4b2c2, 0x0039b335, 0xc97300c7, 0xb300ba00, 0x00b500d9, 0x9db339bf, 0x9800b400, 0x9db30139, 0x8a00ac00, 0x7e00e208, 0xc4001a27, 0x0bf401a9, 0xa2a9e70d, 0x0294b602, 0xfe0209bb, 0x3ab2014c, 0xcc90b43d, 0x28627e1b, 0x00ad3300, 0x00890083, @@ -367,16 +367,16 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x1df4f9a6, 0xff2fe407, 0xbdfe32ff, 0x29833ef4, 0x90913c00, 0xb60394f0, 0xa9bc0394, 0xf9493c95, 0x3201ff90, 0xf4fe26f9, 0xe9c4ea08, 0x040090ff, 0x7302297b, 0xbc0d0020, 0x143d4049, 0x0029503e, 0x900149fe, 0x9b3f1b99, 0xc4bd3ab2, 0x0028627e, 0x0029bc3e, 0xbc3e020a, 0x010a0029, 0x900149fe, - 0x9fbf1c99, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xf90855fb, 0xb2350902, 0x00a0b3a0, - 0xbdb43d1a, 0x28627ec4, 0x33a93200, 0xb20c00a4, 0x28367e0a, 0x32a93200, 0xf401fb9a, 0xdcd9f430, + 0x9fbf1c99, 0x0005ecd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xf90855fb, 0xb2350902, 0x00a0b3a0, + 0xbdb43d1a, 0x28627ec4, 0x33a93200, 0xb20c00a4, 0x28367e0a, 0x32a93200, 0xf401fb9a, 0xecd9f430, 0xf9000005, 0xfe99bf12, 0xff90014f, 0x03e84b10, 0xfc7ef9a0, 0xa0b20016, 0x90014afe, 0xa1b208aa, 0x0015817e, 0x00e5a08a, 0x001a277e, 0xf400a6b0, 0x1ab21c1f, 0x00159c7e, 0x0df4a0a6, 0x3e040a09, - 0x7e002a4d, 0x3e00000e, 0x3d002a24, 0x0149fea4, 0xbf109990, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, + 0x7e002a4d, 0x3e00000e, 0x3d002a24, 0x0149fea4, 0xbf109990, 0x05ecd99f, 0x99bf0000, 0x0bf4f9a6, 0x3a317e07, 0x0c15fb00, 0xad5802f9, 0x58af3f01, 0xb0b202a9, 0xffffdce4, 0xf003f4f0, 0xf4b60093, 0x909cbc12, 0x000000de, 0x01999280, 0xf005fefd, 0xf9ffff94, 0x00d073b5, 0x01cf9218, 0x01000089, 0xff08f4b6, 0xf4f195b9, 0x9fffffff, 0x01aa18b5, 0xf401a9c4, 0x00890a0b, 0xb9fd0200, 0xffa4f005, 0xf410a9c4, 0x00d90b0b, 0xfd080000, 0xa9c405b9, 0x0b0bf404, 0x000000d9, 0x05b9fd20, 0x00e5a08a, - 0x001a877e, 0xfb7e0ab2, 0x01fb0029, 0xdff830f4, 0x000005dc, 0xffbf42f9, 0x900149fe, 0xa3b21899, + 0x001a877e, 0xfb7e0ab2, 0x01fb0029, 0xdff830f4, 0x000005ec, 0xffbf42f9, 0x900149fe, 0xa3b21899, 0xb1729fa0, 0x2000c073, 0x09ffdfc4, 0x029fbb40, 0xffffcfe4, 0xbb0294b6, 0xbfe4029f, 0xf9a6ffff, 0x00b60cf5, 0x09ffdac4, 0xff12e440, 0x029abbff, 0xa60294b6, 0xa10cf529, 0x00c07300, 0xa2c9e756, 0x03c0c401, 0xb8409abc, 0x0039284a, 0x7e02a4b6, 0xf0001a27, 0x0994ff04, 0x05a9bb03, 0x900149fe, @@ -384,18 +384,18 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0xbb903039, 0x00c3f014, 0x000b7e7e, 0xb8014a90, 0x003928a9, 0x940144fe, 0x44900292, 0x2bcc3e14, 0x70107200, 0x0df40416, 0xb2040005, 0x1a277e2a, 0xff09e400, 0x7b4aa0ff, 0x3ab20210, 0xbc042290, 0x4bb23039, 0xffff0ce4, 0x000b7e7e, 0xd5001473, 0xd83ea43d, 0x020a002b, 0x900149fe, 0x9fbf1899, - 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xf40845fb, 0xdcdff830, 0xf9000005, 0xfeffbf52, + 0x0005ecd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xf40845fb, 0xecdff830, 0xf9000005, 0xfeffbf52, 0x99900149, 0xa0a3b21c, 0x0ab1729f, 0x00b67102, 0x450cf401, 0x820144fe, 0x9000e4a0, 0x54bd1844, 0x002c503e, 0x107245a0, 0xf4041670, 0x0400050d, 0x0ce43bb2, 0x4ab2ffff, 0x000b7e7e, 0x2ab24bbf, - 0x9002107b, 0x03f00422, 0x1a877e00, 0x3030bc00, 0xd4001473, 0x49fea43d, 0x1c999001, 0xdcd99fbf, + 0x9002107b, 0x03f00422, 0x1a877e00, 0x3030bc00, 0xd4001473, 0x49fea43d, 0x1c999001, 0xecd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x55fb003a, 0xb252f908, 0x58c5b2b1, 0xb25802b4, 0x00a0b301, 0xff43e454, 0xff20e4ff, 0x0034b3ff, 0x0004b30c, 0x2cd13e0c, 0x0000b300, 0x72dab210, 0x2bf37e2b, 0x00a43300, 0x8b1ab232, 0x7e07a120, 0x33002a68, 0xb32400a4, 0xb0200030, 0xdcf00006, 0x01d6f00b, - 0x4b725ab2, 0xd4362c72, 0x2aec7e05, 0x2cd33e00, 0xfb350a00, 0xf830f451, 0x0005dcdf, 0xbf12f900, + 0x4b725ab2, 0xd4362c72, 0x2aec7e05, 0x2cd33e00, 0xfb350a00, 0xf830f451, 0x0005ecdf, 0xbf12f900, 0x0149feff, 0xfe0c9990, 0x9fa00140, 0xb2080090, 0x7e0cb2b1, 0xbf004526, 0x02f9580f, 0xf003ff98, 0x94b60093, 0x2d163e0c, 0xf491a600, 0xff98150b, 0x0099b806, 0xf4b30010, 0x350af300, 0x002d353e, - 0x9802fe98, 0xffbf05f9, 0xa6909fbc, 0x089cf09e, 0x320196f0, 0x0149fe9a, 0xbf0c9990, 0x05dcd99f, - 0x99bf0000, 0x0bf4f9a6, 0x3a317e07, 0x0815fb00, 0xdfe030f4, 0x000005dc, 0xffbf82f9, 0xfe09b1b0, + 0x9802fe98, 0xffbf05f9, 0xa6909fbc, 0x089cf09e, 0x320196f0, 0x0149fe9a, 0xbf0c9990, 0x05ecd99f, + 0x99bf0000, 0x0bf4f9a6, 0x3a317e07, 0x0815fb00, 0xdfe030f4, 0x000005ec, 0xffbf82f9, 0xfe09b1b0, 0x99900149, 0x0140fe40, 0x00909fa0, 0xb2a4b23c, 0x45267e0c, 0x5803bf00, 0x31980239, 0x0093f003, 0x3e0c94b6, 0xb4002d97, 0x9ea609e0, 0x98130bf4, 0x99b80611, 0xb3001000, 0x3ef00014, 0x98002f69, 0x1f980519, 0x041e9803, 0xbc0395b6, 0x2ea6209f, 0xfe4f0cf4, 0x4ab20143, 0xb2383390, 0xb2010c2b, @@ -412,12 +412,12 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x00de943e, 0xfdff0000, 0x9ffd04fe, 0x9879a005, 0x4ab2012c, 0x040d7bb2, 0x00406b7e, 0x7500a433, 0x1b9823a0, 0x0c4ab203, 0x928db204, 0xd77e04bb, 0xa4330028, 0x2c985f00, 0xb24ab203, 0x92040d8b, 0x6b7e04cc, 0xa4330040, 0x1f984b00, 0xb594bd02, 0x66b80529, 0xb5001000, 0x2298022f, 0x06119806, - 0x6f001db3, 0x2f6b3eff, 0xfe350000, 0x99900149, 0xd99fbf40, 0x000005dc, 0x0a3299bf, 0x0bf4f9a6, + 0x6f001db3, 0x2f6b3eff, 0xfe350000, 0x99900149, 0xd99fbf40, 0x000005ec, 0x0a3299bf, 0x0bf4f9a6, 0x2f973e1d, 0x0141fe00, 0x1190fea0, 0x2e3e3e3c, 0x3ea03200, 0x7e002f6b, 0xfb003a31, 0x02f92085, 0xa0b3a0b2, 0xa9985100, 0x0090b306, 0x140cd94a, 0x9abf0000, 0x04e0aab8, 0x1a277e00, 0xffa9e400, 0xff9ab30f, 0x90b3380f, 0xaae73300, 0xaab3016c, 0xb32b0fff, 0x982600a0, 0x94b6060e, 0x0caf940c, 0xe9a0a43d, 0xbf060e98, 0xf0f9bce9, 0x3e01efb5, 0x0a002ffb, 0x2ffb3e35, 0xfb2e0a00, 0xd830f401, - 0x0005dcdf, 0xbf82f900, 0x0149feff, 0xb2489990, 0xb39fa0a6, 0x982100a0, 0xfd0906a0, 0xbf920bbf, + 0x0005ecdf, 0xbf82f900, 0x0149feff, 0xb2489990, 0xb39fa0a6, 0x982100a0, 0xfd0906a0, 0xbf920bbf, 0xf4f9a601, 0x0f98110c, 0xa6ff0901, 0x070bf4f9, 0x1100f4b3, 0x020502f8, 0x7d006db3, 0x32c23e02, 0x10bb9200, 0x7cdd100c, 0x7e000029, 0x320028d7, 0x00ad33a5, 0x7cda0264, 0xdb000029, 0x00000068, 0xa87e080c, 0xadb3000b, 0x98027e00, 0x0fbf0109, 0x18f5f9a6, 0xfee40278, 0x1bf50fff, 0x6f980270, @@ -439,31 +439,31 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x0b0094b3, 0x3e0331b5, 0xb4003271, 0xf1b50df0, 0x01771006, 0xde0d11b0, 0x0000297c, 0x260de918, 0xca08f579, 0x04e998fe, 0x0b0094b3, 0x3e04e3b5, 0xb4003299, 0xf3b50bf0, 0x01881004, 0xde0b31b0, 0x0000297c, 0x260ce918, 0xf008f589, 0x32c23efd, 0x00503300, 0x06699811, 0x9fa0ff0f, 0xb5066998, - 0x49fe019f, 0x48999001, 0xdcd99fbf, 0xbf000005, 0xa65a3299, 0x1f0bf4f9, 0x0032f03e, 0x0532a032, - 0x0032b13e, 0xb53e3505, 0x02050032, 0x0032b53e, 0x003a317e, 0xf42885fb, 0xdcdff430, 0xf9000005, + 0x49fe019f, 0x48999001, 0xecd99fbf, 0xbf000005, 0xa65a3299, 0x1f0bf4f9, 0x0032f03e, 0x0532a032, + 0x0032b13e, 0xb53e3505, 0x02050032, 0x0032b53e, 0x003a317e, 0xf42885fb, 0xecdff430, 0xf9000005, 0xfeffbf22, 0x99900149, 0x0142fe14, 0x94bd9fa0, 0xa00c2290, 0x3da37e29, 0x00a03300, 0xda040b56, 0x00002944, 0x2db2bcb2, 0x0042d77e, 0xa433a032, 0x41fe4300, 0x10119001, 0x8e7e1ab2, 0xa0320033, 0x3100a433, 0x2bbf1cbf, 0x24d1a4bd, 0x7e000014, 0xa000b06d, 0x00a0b31a, 0x7eb43d1a, 0xb300b105, - 0xbf1200a0, 0x7eff001a, 0x3e00b63f, 0x00003371, 0x0149feff, 0xbf149990, 0x05dcd99f, 0x99bf0000, - 0xf9a60a32, 0x7e070bf4, 0xfb003a31, 0x0e090c25, 0xa43da9a0, 0x30f400f8, 0x05dcdfd8, 0x62f90000, + 0xbf1200a0, 0x7eff001a, 0x3e00b63f, 0x00003371, 0x0149feff, 0xbf149990, 0x05ecd99f, 0x99bf0000, + 0xf9a60a32, 0x7e070bf4, 0xfb003a31, 0x0e090c25, 0xa43da9a0, 0x30f400f8, 0x05ecdfd8, 0x62f90000, 0x30f4ffbf, 0x0149fef4, 0xa04c9990, 0xb2a93f9f, 0x01a398a6, 0x0d019033, 0x60489d33, 0x35a33e03, - 0x04301800, 0x1b010d33, 0x03329801, 0x3d043198, 0x10dc4ba4, 0xd501004c, 0x00000644, 0x0038327e, + 0x04301800, 0x1b010d33, 0x03329801, 0x3d043198, 0x10dc4ba4, 0xd501004c, 0x00000654, 0x0038327e, 0xa4b35aa0, 0x02f80c00, 0x1a3e0501, 0x49fe0037, 0x28999001, 0x00299cd4, 0xb51cb200, 0x91b50741, 0x352bb201, 0x42b51540, 0xbd92a006, 0x10dc4ed4, 0x0020d07e, 0xad33a132, 0xbf015900, 0x33993f59, - 0x980d0090, 0x95f00149, 0x0149b508, 0x000644d9, 0x1899bf00, 0x90336999, 0x9cdf1300, 0x98000029, + 0x980d0090, 0x95f00149, 0x0149b508, 0x000654d9, 0x1899bf00, 0x90336999, 0x9cdf1300, 0x98000029, 0x95f101f9, 0xf9b54000, 0x299cda01, 0x037e0000, 0x3098009c, 0x01027e02, 0x8aa3d900, 0xacb20000, 0xb20091b0, 0xbdb4bd0d, 0x2e70da04, 0x01b00000, 0x08013001, 0xc87e010e, 0x9cd90013, 0xdf000029, 0x1e000000, 0xfe509035, 0x99900149, 0x0142fe34, 0x22909fa0, 0xb2010a38, 0x94ef7e2b, 0x1fa43300, 0xc42bbf1b, 0x1bf401b9, 0x01b5f014, 0x2ba0010a, 0x00950a7e, 0x061fa033, 0xb4bd09f8, 0x0a7e020a, 0x9cda0095, 0x7e000029, 0xfe009ab2, 0xb4bd014a, 0x010dc4bd, 0x7e34aa90, 0x3e0075b0, 0x33003574, - 0xd9320204, 0x00000644, 0xa0b39abf, 0xb4d97f00, 0x98000029, 0x9bbf019c, 0x9cd9f43d, 0xbd000029, + 0xd9320204, 0x00000654, 0xa0b39abf, 0xb4d97f00, 0x98000029, 0x9bbf019c, 0x9cd9f43d, 0xbd000029, 0x159f35d4, 0x7e10dc4e, 0x320020d0, 0x356f3ea1, 0x030d3300, 0x0e7e0207, 0x39180001, 0x00903308, 0x033e9824, 0x002a3cd9, 0x2a44df00, 0x9ea00000, 0xb5043e98, 0x3998019e, 0x98f9a005, 0xfeb5063e, 0x1c391801, 0x21009033, 0x00299cdf, 0x08399800, 0x982dfe98, 0x9efd2efd, 0x2df9b505, 0xfd093998, 0xf9b5059d, 0x01087e2e, 0x3e143d00, 0x33003574, 0x01ab001d, 0xb2016b18, 0x0f817e3a, 0xfe020900, 0xff90014f, 0x3df92048, 0x02f93594, 0x09033318, 0xb2b4bd04, 0x03f335fa, 0x7e01f935, 0x3e000f71, 0xfe00371a, 0x41fe0140, 0x44009001, 0xfe401190, 0x0ab20142, 0xb23c2290, 0x3d2cb21b, 0x75b07ed4, - 0x02399800, 0x010a0fbf, 0x1bf4f9a6, 0x052cde3c, 0xe93f0000, 0x0e009033, 0x1e0a943d, 0x063ee920, + 0x02399800, 0x010a0fbf, 0x1bf4f9a6, 0x0530de3c, 0xe93f0000, 0x0e009033, 0x1e0a943d, 0x063ee920, 0xffd90036, 0xff200000, 0x94b394f9, 0x0ab2121c, 0x2cb21bb2, 0x0098b97e, 0x0036063e, 0x1bb20ab2, 0x3e7e2cb2, 0x4bfe008d, 0x44bb9001, 0xa9c4bebf, 0xffffdf1f, 0x94b6e0ff, 0x04effd18, 0xa0e59eff, 0x0000d9be, 0xe9ff4000, 0x6b0bf494, 0x681fa433, 0x900149fe, 0x9dbf4099, 0xbf049992, 0x1ee4339c, @@ -474,7 +474,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x48991800, 0x0a009433, 0xd23e02f8, 0x90330036, 0x4efe1e01, 0x38ee9001, 0xffdfe9bf, 0xfde0ffff, 0x00df049f, 0xfd010000, 0xe9a0059f, 0x9cd9f43d, 0x0d000029, 0x489f3501, 0xfe014bfe, 0xbb90014c, 0x30cc9034, 0x90014afe, 0xb07e38aa, 0x9b7e0075, 0x143d000a, 0x00371a3e, 0x49fee401, 0x4c999001, - 0xdcd99fbf, 0xbf000005, 0xa61a3299, 0x070bf4f9, 0x003a317e, 0xfb0c30f4, 0xa9922865, 0x929ba004, + 0xecd99fbf, 0xbf000005, 0xa61a3299, 0x070bf4f9, 0x003a317e, 0xfb0c30f4, 0xa9922865, 0x929ba004, 0xecb548ae, 0x00008906, 0xb2e9a030, 0x9294bdaf, 0xfab24cff, 0x00f8f9a0, 0x8f7e02f9, 0xa4b3005c, 0x04bd0a00, 0x00379e3e, 0x00168989, 0x890093fe, 0xfe001633, 0x71890090, 0x91fe0016, 0xbda4bd00, 0x0a897eb4, 0xb0a0b200, 0x1ff400a6, 0x4ba4bd0c, 0x957efe0b, 0xa77e000a, 0x2b3e0038, 0x0ab20016, @@ -483,10 +483,10 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x46899abf, 0x0fc20031, 0x799b7f0f, 0xd95201ff, 0x90907c01, 0x66c4f9ff, 0x2108f4cd, 0xe4d0c17c, 0xa6ffffd9, 0x1508f491, 0x0cf4db66, 0xffc9e410, 0xbc2d60ff, 0x1c3e009a, 0x04bd0038, 0x000a9b7e, 0x0038263e, 0x0ab204bd, 0x040c21fb, 0x0037a87e, 0x12f900f8, 0xa87eb1b2, 0xa0b20037, 0x0c00a0b3, - 0xb4bd1cb2, 0x000b947e, 0x11fb0ab2, 0x327e040c, 0x00f80038, 0xa43dabb2, 0x00384c7e, 0xfc8f00f8, - 0xf9bf0010, 0x361b9918, 0xa9200695, 0x9918f9bf, 0x2499c71b, 0x00f8b920, 0x0010fc8c, 0xaf14cdbf, + 0xb4bd1cb2, 0x000b947e, 0x11fb0ab2, 0x327e040c, 0x00f80038, 0xa43dabb2, 0x00384c7e, 0x0c8f00f8, + 0xf9bf0011, 0x361b9918, 0xa9200695, 0x9918f9bf, 0x2499c71b, 0x00f8b920, 0x00110c8c, 0xaf14cdbf, 0x03bec406, 0x1804e436, 0x94f01bd9, 0x05f9fd3f, 0xbf1bdf35, 0x1bf918cf, 0xfdcf94f0, 0xfe3505e9, - 0x18657e1b, 0x8900f800, 0xbf0010fc, 0x1b9a1899, 0x3624abc7, 0x657e06a5, 0x00f80018, 0x0018547e, + 0x18657e1b, 0x8900f800, 0xbf00110c, 0x1b9a1899, 0x3624abc7, 0x657e06a5, 0x00f80018, 0x0018547e, 0x30f400f8, 0xe482f9e0, 0x95ffffc1, 0xc5b210c2, 0xffffa0e4, 0xb210a395, 0x0148fea4, 0x900147fe, 0x77903c88, 0x018bb534, 0xa0017db5, 0xa00bb27c, 0x7e1ab28a, 0xb20016fc, 0xb2a6b20b, 0x16fc7e2a, 0xb23bb200, 0x7e1ab2a0, 0xb20016fc, 0xb2a1b23b, 0x16fc7e2a, 0x0010bc00, 0xb2106995, 0x0009bcad, @@ -499,9 +499,9 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x029cbb20, 0xf40096b0, 0xbcbc211d, 0x014efef4, 0xfd95a9bc, 0xacbc059f, 0x01e9b5f4, 0xeb98efa0, 0xf4eabf01, 0x00f81030, 0xb9014efe, 0x94bd019f, 0xa0f4afbc, 0x01efb5e9, 0xeb98eabf, 0x3a033e01, 0x1430d900, 0x00df0000, 0x3d000000, 0xf89fa0a4, 0x49180f00, 0x9ff71100, 0xf802f800, 0xf430f400, - 0x0005dcdf, 0xbf12f900, 0x0149feff, 0xb2109990, 0x8a9fa0ab, 0x7e12004c, 0xfe001a87, 0x3f80014a, + 0x0005ecdf, 0xbf12f900, 0x0149feff, 0xb2109990, 0x8a9fa0ab, 0x7e12004c, 0xfe001a87, 0x3f80014a, 0xaa904c4b, 0x7ea1b208, 0x8a001581, 0x7e12004c, 0xf0001a27, 0x1bf43fa4, 0x3e010a09, 0xb2003a8e, - 0x159c7e1a, 0xf4a0a600, 0x02f8e40d, 0x49fea43d, 0x10999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, + 0x159c7e1a, 0xf4a0a600, 0x02f8e40d, 0x49fea43d, 0x10999001, 0xecd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x15fb003a, 0xb212f90c, 0xb2b1b2a9, 0x0190b3ca, 0x0196b021, 0x0a0e08f4, 0x029db3ff, 0x473e00ba, 0x020f003b, 0xf60a0049, 0x553e009f, 0x0049003b, 0x009fcf0a, 0xfefdfe0e, 0x009ff604, 0x2b00d033, 0xcf08004f, 0x94bd00f9, 0x4000f9f6, 0x09cf0900, 0x03e84b00, 0x0016fc7e, 0x0200aab8, @@ -526,35 +526,35 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x9ff60202, 0x009fcf00, 0x153e9fb2, 0x00f8003d, 0x01c0008f, 0xc700f9cf, 0x90b34c99, 0x90b32200, 0x02f8f601, 0x003d543e, 0xc700f9cf, 0x90b34c99, 0x90b33300, 0x02f8f601, 0x003d683e, 0x01c10089, 0xb8009af6, 0x00010099, 0xdf009bf6, 0x800000f2, 0x020099b8, 0x009ff602, 0xb2009fcf, 0x3d683e9f, - 0xd900f800, 0x0000110a, 0x00f89a3f, 0xf9f030f4, 0x05dcd442, 0x49bf0000, 0x0601a2b2, 0x1cb2b4bd, + 0xd900f800, 0x0000111a, 0x00f89a3f, 0xf9f030f4, 0x05ecd442, 0x49bf0000, 0x0601a2b2, 0x1cb2b4bd, 0xfe0140fe, 0x00900143, 0x20339016, 0x39a00ab2, 0x000b947e, 0x4dfe94bd, 0x1cdd9001, 0xd120d9a0, 0x18020975, 0x2ab20429, 0xc4bd0bb2, 0x18090920, 0x09010935, 0x01097501, 0x002c717e, 0x49bf3fbf, - 0x0bf4f9a6, 0x3a317e07, 0x1045fb00, 0xdfec30f4, 0x000005dc, 0xffbf22f9, 0x900149fe, 0xa1b21c99, + 0x0bf4f9a6, 0x3a317e07, 0x1045fb00, 0xdfec30f4, 0x000005ec, 0xffbf22f9, 0x900149fe, 0xa1b21c99, 0x060c9fa0, 0x40feb2b2, 0x90b4bd01, 0x0ab20e00, 0x000b947e, 0x4ffe94bd, 0x18ff9001, 0x1e18f9a0, 0xfe1ab204, 0x11900141, 0x0919a014, 0x02097501, 0x09010975, 0x09f92005, 0xb20e2019, 0x0109350b, - 0x1cb2fdb2, 0x002c717e, 0xa433a032, 0x1abf0c00, 0xb57e2bb2, 0x49fe0027, 0x1c999001, 0xdcd99fbf, - 0xbf000005, 0xa60a3299, 0x070bf4f9, 0x003a317e, 0xf41425fb, 0xdcd9f030, 0xf9000005, 0xfe99bf42, + 0x1cb2fdb2, 0x002c717e, 0xa433a032, 0x1abf0c00, 0xb57e2bb2, 0x49fe0027, 0x1c999001, 0xecd99fbf, + 0xbf000005, 0xa60a3299, 0x070bf4f9, 0x003a317e, 0xf41425fb, 0xecd9f030, 0xf9000005, 0xfe99bf42, 0xff90014f, 0xa0a3b220, 0x4bbab2f9, 0xfc7e03e8, 0x42fe0016, 0xbda1b201, 0x014afe04, 0x901c2290, 0xa4b214aa, 0x0015817e, 0x003ed83e, 0x9c7e4ab2, 0xa0b20015, 0x00000e7e, 0x2bb23ab2, 0x003e0c7e, 0x1600a433, 0x94f029bf, 0x00903301, 0xf401a60d, 0x013edd08, 0x01a6003f, 0x3d0918f4, 0x3f033ea4, - 0xfe040a00, 0x99900149, 0xd99fbf20, 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, 0x30f41045, - 0x05dcdff0, 0x22f90000, 0x49feffbf, 0x18999001, 0xa2b2b032, 0xac7e9fa0, 0xa433003d, 0x04336400, + 0xfe040a00, 0x99900149, 0xd99fbf20, 0x000005ec, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, 0x30f41045, + 0x05ecdff0, 0x22f90000, 0x49feffbf, 0x18999001, 0xa2b2b032, 0xac7e9fa0, 0xa433003d, 0x04336400, 0x143d0a00, 0x003f513e, 0xf0112918, 0x91140f94, 0x0cb4bd02, 0x0140fe06, 0xb20e0090, 0x0b947e0a, 0xfe94bd00, 0xff90014f, 0x35f9a014, 0x097501f1, 0x04291802, 0xfdb20bb2, 0x09202ab2, 0xf9200109, 0x09351809, 0xbd020901, 0x010975c4, 0x002c717e, 0x0e00a433, 0xa08b2ab2, 0x937e0186, 0x49fe003e, - 0x18999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x25fb003a, 0xf030f410, 0x0005dcd9, + 0x18999001, 0xecd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x25fb003a, 0xf030f410, 0x0005ecd9, 0xbf22f900, 0x014ffe99, 0xb218ff90, 0xb2f9a0a1, 0xbd060cb2, 0x014afeb4, 0x7e0eaa90, 0xbd000b94, 0x0140fe94, 0x00901ab2, 0x7e09a014, 0x33003dac, 0x186100a4, 0x99c71119, 0x0094b304, 0x3e20090a, 0x09004005, 0x180920d7, 0x4efe0419, 0x0eee9001, 0x20014ffe, 0x102995e9, 0x3514ff90, 0x299501f9, 0x02f93508, 0xe9351809, 0x75040901, 0x947d01e9, 0xf235ebb2, 0x75fdb203, 0x1ab202e9, 0x717ec4bd, - 0xa433002c, 0x1ab20e00, 0x07a1208b, 0x003e937e, 0x900149fe, 0x9fbf1899, 0x0005dcd9, 0xa699bf00, - 0x070bf4f9, 0x003a317e, 0xf41025fb, 0xdcdfec30, 0xf9000005, 0xfeffbf72, 0x99900149, 0xa0a1b230, + 0xa433002c, 0x1ab20e00, 0x07a1208b, 0x003e937e, 0x900149fe, 0x9fbf1899, 0x0005ecd9, 0xa699bf00, + 0x070bf4f9, 0x003a317e, 0xf41025fb, 0xecdfec30, 0xf9000005, 0xfeffbf72, 0x99900149, 0xa0a1b230, 0xb2b7b29f, 0xb3d672c3, 0x009e00a9, 0x0100d671, 0x00950cf5, 0xb4bd54bd, 0x40fe060c, 0x0142fe01, 0x90200090, 0x05a02c22, 0xa0020575, 0x0144fe25, 0xb2264490, 0x0b947e4a, 0x7e1ab200, 0x33003dac, 0x356800a4, 0x19180323, 0x750bb204, 0x2db20205, 0x02090920, 0x39952920, 0x01293510, 0x35083995, 0x08090229, 0x09010935, 0x751ab204, 0xc4bd0109, 0x002c717e, 0x3300a433, 0x75014675, 0x19180245, 0xb24bb204, 0x201ab27d, 0xbd100949, 0x014935c4, 0x002c717e, 0x1300a433, 0x004b1ab2, 0x3e937e32, - 0x41273e00, 0xfe350a00, 0x99900149, 0xd99fbf30, 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, + 0x41273e00, 0xfe350a00, 0x99900149, 0xd99fbf30, 0x000005ec, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, 0x52f91475, 0xaa98a2b2, 0xb2c3b205, 0xbffd09d5, 0x10bebcae, 0xa601ef92, 0x230cf4f9, 0x0901af98, 0xf4f9a6ff, 0xf0b3190b, 0x1ea61600, 0xbc1008f4, 0x91a690c1, 0xa60808f4, 0x050df49f, 0x291802f8, 0xc7010a11, 0x94b30599, 0x2ab23f00, 0x0029d77e, 0xa433a432, 0x04bd3100, 0x0041be3e, 0xb1d230bc, @@ -573,8 +573,8 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x853e0101, 0x42bc0043, 0x0096b192, 0x060df401, 0x90010049, 0x96ff0399, 0x0b947e04, 0xb23bb200, 0xdd0c725a, 0x00001200, 0x7e3030bc, 0x320028d7, 0x00a433a1, 0x08b0b434, 0xb209c0b4, 0x1200da2d, 0x20bc0000, 0x01004e20, 0x0021367e, 0x0a00a033, 0x853e02f8, 0x00da0043, 0xbd000012, 0x01004cb4, - 0x08f424a6, 0xfb1a32a4, 0xf4f0fc60, 0xf4f90430, 0xdfe430f4, 0x000005dc, 0xffbf42f9, 0x900149fe, - 0xa1b22c99, 0x0ad99fa0, 0x3f000011, 0x00903399, 0x3e043d0a, 0xbd0044ff, 0x0149fef4, 0xa0249990, + 0x08f424a6, 0xfb1a32a4, 0xf4f0fc60, 0xf4f90430, 0xdfe430f4, 0x000005ec, 0xffbf42f9, 0x900149fe, + 0xa1b22c99, 0x1ad99fa0, 0x3f000011, 0x00903399, 0x3e043d0a, 0xbd0044ff, 0x0149fef4, 0xa0249990, 0x0499929f, 0x99929fa0, 0x05a29804, 0xa006a498, 0x27c37e9f, 0x33a03200, 0x330800a0, 0xbf6b2ea4, 0x0129982b, 0x18f5b9a6, 0xb9e40133, 0x1bf50fff, 0x43fe012b, 0x901ab201, 0x040c1c33, 0xd77e3db2, 0xa0320028, 0x4200a433, 0x35003fbf, 0x46464ad9, 0xf4f9a653, 0x1ab2331b, 0x002f9e7e, 0x3600a433, @@ -584,19 +584,19 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x09200104, 0xf9209f09, 0x09351909, 0x75030901, 0x09750104, 0x0142fe02, 0x22901ab2, 0x7e2cb224, 0x32002c71, 0x00a433a0, 0xb22bbf5a, 0x27777e1a, 0x33a03200, 0x184c00a4, 0x29c71112, 0x0094b305, 0x0143fe39, 0x33901ab2, 0x7e3bb220, 0x33003e0c, 0xbf1500a4, 0x0229943f, 0xfd3c94f0, 0x0bf4049f, - 0x20143506, 0xb43d1ab2, 0x003f1e7e, 0x0a00a033, 0xff3ea032, 0x010f0044, 0x00110ad9, 0xfe9f2000, - 0x99900149, 0xd99fbf2c, 0x000005dc, 0x0a3299bf, 0x0bf4f9a6, 0x451f3e11, 0x3e020000, 0x7e004446, + 0x20143506, 0xb43d1ab2, 0x003f1e7e, 0x0a00a033, 0xff3ea032, 0x010f0044, 0x00111ad9, 0xfe9f2000, + 0x99900149, 0xd99fbf2c, 0x000005ec, 0x0a3299bf, 0x0bf4f9a6, 0x451f3e11, 0x3e020000, 0x7e004446, 0xfb003a31, 0xa0b31c45, 0xaa982100, 0xbffd0f06, 0x019992a9, 0x0cf49fa6, 0x01aa9811, 0xa9a6ff09, 0xb3070bf4, 0xf80a00a4, 0xf8020a02, 0xffb9e400, 0xf4020a0f, 0x7cd9451b, 0x98000029, 0x903e049f, 0xf9180045, 0x00903308, 0x09f91828, 0x21009033, 0x5802f958, 0x93f003fe, 0x0c94b600, 0x08f4b9a6, - 0xffe9e40f, 0x0c94b6ff, 0x0df4b9a6, 0x04ff980a, 0xd200f4b3, 0x350acfa0, 0x30f400f8, 0x05dcdff8, + 0xffe9e40f, 0x0c94b6ff, 0x0df4b9a6, 0x04ff980a, 0xd200f4b3, 0x350acfa0, 0x30f400f8, 0x05ecdff8, 0x52f90000, 0xa4b2ffbf, 0xfe0149fe, 0x99900142, 0xb2b0b21c, 0xa0d5b2c3, 0x0a14bd9f, 0x18229035, 0x0046513e, 0x0bb24ab2, 0x2db2040c, 0x0028d77e, 0x8900ad33, 0xb329bf00, 0x900e0094, 0x00902011, 0x46513e04, 0x019eb900, 0x8904e9fd, 0xffff0000, 0xfcf094e9, 0x01f6f00b, 0x00ff00d9, 0x94e9ffff, 0xf00bbcf0, 0xf0d901b6, 0xfff0f0f0, 0xccf094e9, 0x01c6f00b, 0xccccccd9, 0x94e9ffcc, 0xf00bdcf0, 0xaad901d6, 0xb6aaaaaa, 0xb4b604f4, 0x02c4b603, 0xfd01d4b6, 0x9cf004e9, 0x0196f00b, 0xfd05f9fd, 0xfcfd05fb, 0x05fdfd05, 0x1fbc2fa0, 0x46573e10, 0xf503a600, 0xa0ff710d, 0x0149fe51, 0xbf1c9990, - 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x3a317e07, 0x0855fb00, 0xc4b252f9, 0xe3b2d1b2, 0xb5b2a2b2, + 0x05ecd99f, 0x99bf0000, 0x0bf4f9a6, 0x3a317e07, 0x0855fb00, 0xc4b252f9, 0xe3b2d1b2, 0xb5b2a2b2, 0xc4bdedb2, 0x0046e33e, 0x3f90eebc, 0x909abcbf, 0xbc01bb90, 0x9e929090, 0x03ea9430, 0xb207f0c2, 0x30f912bd, 0xf4099630, 0xe4b3e10d, 0x010e0600, 0x2d64f033, 0x0064f631, 0x330b1cf4, 0x3e2862f4, 0x330046cf, 0x330c73f0, 0x3e1c77f4, 0xbc0046d6, 0xe33ec0ce, 0xeebc0046, 0x46e03e90, 0x02e99400, @@ -609,17 +609,17 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0xfd4c0090, 0xeb3e05f4, 0xa9180047, 0x90af3f01, 0x94f002ad, 0xfff4f0ff, 0xff0894b6, 0xeb3ef59f, 0xad180047, 0x02af1803, 0xa918ae3f, 0x18d4b601, 0xb6fff4f0, 0xe4f010f4, 0xff94f0ff, 0xfd0894b6, 0x9ffd059e, 0xf59dff05, 0xa004ad90, 0x01cc920f, 0xb2040090, 0xb302b2da, 0xff7000cd, 0xb0333b3f, - 0x3f900f00, 0x3ec4bd01, 0x0100474a, 0xfb1a32ff, 0xf830f451, 0xdcd222f9, 0xbf000005, 0xfebcb229, + 0x3f900f00, 0x3ec4bd01, 0x0100474a, 0xfb1a32ff, 0xf830f451, 0xecd222f9, 0xbf000005, 0xfebcb229, 0x40fe0141, 0x10119001, 0xa00c0090, 0xb2d4bd19, 0x0074de0b, 0x747e0000, 0x1fbf0046, 0x0a7f29bf, - 0x0bf4f9a6, 0x3a317e07, 0x0825fb00, 0xf9f830f4, 0x05dcd222, 0x29bf0000, 0x41febcb2, 0x0140fe01, + 0x0bf4f9a6, 0x3a317e07, 0x0825fb00, 0xf9f830f4, 0x05ecd222, 0x29bf0000, 0x41febcb2, 0x0140fe01, 0x90101190, 0x19a00c00, 0x0bb2d4bd, 0x000076de, 0x46747e00, 0xbf1fbf00, 0xa60abf29, 0x070bf4f9, - 0x003a317e, 0xf40825fb, 0x22f9f830, 0x0005dcd2, 0xb229bf00, 0x0141febc, 0x900140fe, 0x00901011, + 0x003a317e, 0xf40825fb, 0x22f9f830, 0x0005ecd2, 0xb229bf00, 0x0141febc, 0x900140fe, 0x00901011, 0xbd19a00c, 0xde0bb2d4, 0x00000078, 0x0046747e, 0x29bf1fbf, 0xf9a60a3f, 0x7e070bf4, 0xfb003a31, - 0x30f40825, 0x05dcdff0, 0x62f90000, 0x49feffbf, 0x0143fe01, 0xfe289990, 0x9fa00142, 0x001404d6, + 0x30f40825, 0x05ecdff0, 0x62f90000, 0x49feffbf, 0x0143fe01, 0xfe289990, 0x9fa00142, 0x001404d6, 0x1c339000, 0x05242290, 0xbf040402, 0x0d080c6a, 0x7e3bb2ff, 0x330000c1, 0x98f400a4, 0x193f0131, 0xeb079433, 0x3d041918, 0x2944da04, 0x94330000, 0x907e0a00, 0xa0320043, 0xb2013b18, 0x0f817e1a, 0x00043300, 0x022035ca, 0x11182520, 0x352ab203, 0xb4bd0124, 0x7e032135, 0x3e000f71, 0xf40048eb, - 0xdcdff430, 0xf9000005, 0xbdffbf22, 0x0140fe94, 0xb50c0090, 0x09a00109, 0x900149fe, 0x7cd21499, + 0xecdff430, 0xf9000005, 0xbdffbf22, 0x0140fe94, 0xb50c0090, 0x09a00109, 0x900149fe, 0x7cd21499, 0xa000002e, 0x7e01b29f, 0x3e0074f8, 0x9800497e, 0x993f0119, 0x0a099433, 0x967e0ab2, 0x70da0033, 0x7e00002e, 0xb2001475, 0xb22abfad, 0x7e080c0b, 0x330000c1, 0xdadc00a0, 0x00002e70, 0x0014b57e, 0x00497e3e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -633,22 +633,22 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x667e0050, 0x307e004d, 0x7e7e0052, 0xdf7e0052, 0xe77e004d, 0x897e0052, 0x9c7e0053, 0xbf7e0053, 0xd47e0053, 0xe97e0053, 0xfe7e0053, 0x857e0053, 0x4f7e0070, 0xfa7e0054, 0xf57e0058, 0x3a7e0051, 0xc74c0054, 0x00c3f161, 0x01943d00, 0x28913002, 0x30009130, 0x91300891, 0x14913010, 0x30189130, - 0x91301c91, 0x24913020, 0x300111b0, 0xc0da0c11, 0xdb000005, 0x0000018c, 0x804e010d, 0x5d0a7e00, + 0x91301c91, 0x24913020, 0x300111b0, 0xd0da0c11, 0xdb000005, 0x0000018c, 0x804e010d, 0x5d0a7e00, 0x00ad3300, 0x08da023e, 0x0b000014, 0x7e010c04, 0x33005937, 0x022c00ad, 0xf168444c, 0x000000c3, 0x28a13001, 0x3000a130, 0xa13008a1, 0x10a1300c, 0x3014a130, 0xa13018a1, 0x24a13020, 0x000168db, - 0x0101b000, 0x0d1c0130, 0x00804e03, 0x0005c4da, 0x5d0a7e00, 0x1400da00, 0x040b0000, 0x377e080c, + 0x0101b000, 0x0d1c0130, 0x00804e03, 0x0005d4da, 0x5d0a7e00, 0x1400da00, 0x040b0000, 0x377e080c, 0xad330059, 0x4c01dd00, 0xc3f16f6b, 0x44db0000, 0x30000001, 0xa13028a1, 0x10a13000, 0x3014a130, - 0xa13018a1, 0x24a13020, 0x300101b0, 0x11300811, 0x1c01300c, 0x804e080d, 0x05c8da00, 0x0a7e0000, + 0xa13018a1, 0x24a13020, 0x300101b0, 0x11300811, 0x1c01300c, 0x804e080d, 0x05d8da00, 0x0a7e0000, 0x20da005d, 0x0b000014, 0x7e080c04, 0x33005937, 0x019000ad, 0xf1493f4c, 0xdb0000c3, 0x00000120, 0x3028a130, 0xa13000a1, 0x14a13010, 0x3018a130, 0xa13020a1, 0x0101b024, 0x30081130, 0x01300c11, - 0x4e070d1c, 0xccda0100, 0x7e000005, 0xda005d0a, 0x00002e7c, 0x080c1bb2, 0x0059377e, 0x4300ad33, + 0x4e070d1c, 0xdcda0100, 0x7e000005, 0xda005d0a, 0x00002e7c, 0x080c1bb2, 0x0059377e, 0x4300ad33, 0x48c24c01, 0x0000c3f1, 0x0000fcdb, 0x28a13000, 0x3000a130, 0xa13010a1, 0x18a13014, 0x3020a130, - 0x01b024a1, 0x08113001, 0x300c1130, 0x050d1c01, 0xda00c04e, 0x000005d0, 0x005d0a7e, 0x001404da, + 0x01b024a1, 0x08113001, 0x300c1130, 0x050d1c01, 0xda00c04e, 0x000005e0, 0x005d0a7e, 0x001404da, 0x0c040b00, 0x59377e08, 0x00ad3300, 0x4d4c00f6, 0x00c3f171, 0x00d8db00, 0xa1300000, 0x00a13028, 0x3010a130, 0xa13014a1, 0x20a13018, 0xb024a130, 0x11300101, 0x0c113008, 0x0d1c0130, 0x00804e09, - 0x0005d4da, 0x5d0a7e00, 0x1428da00, 0x040b0000, 0x377e080c, 0xad330059, 0x4c00a900, 0xc3f1b7cb, + 0x0005e4da, 0x5d0a7e00, 0x1428da00, 0x040b0000, 0x377e080c, 0xad330059, 0x4c00a900, 0xc3f1b7cb, 0xb4db0000, 0x30000000, 0xa13028a1, 0x10a13000, 0x3014a130, 0xa13018a1, 0x24a13020, 0x300c1130, - 0x01b01c01, 0x08113001, 0xc04e0a0d, 0x05d8da00, 0x0a7e0000, 0x1cda005d, 0x0b000014, 0x7e080c04, + 0x01b01c01, 0x08113001, 0xc04e0a0d, 0x05e8da00, 0x0a7e0000, 0x1cda005d, 0x0b000014, 0x7e080c04, 0x33005937, 0x7e5c00a4, 0x7e005c97, 0x7e004db4, 0x7e005931, 0x7e000a74, 0x7e003cf7, 0x7e005249, 0x7e004d7d, 0x7e004df2, 0x7e005208, 0x7e005216, 0x7e0053af, 0x7e0053d2, 0x7e0053e7, 0x7e0053fc, 0x7e005438, 0x7e00544d, 0x7e00591d, 0x7e00706d, 0x7e005462, 0x7e004ea6, 0x330059ae, 0xf80600a0, @@ -692,7 +692,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x11999800, 0x00f895f9, 0xc4bdb4bd, 0xa4bdd43d, 0x003aa97e, 0x30da00f8, 0x3d000029, 0x5e7f7eb4, 0x2930d900, 0x99bf0000, 0x060094b3, 0x00f802f8, 0x001430d9, 0x3d9fbf00, 0x2e8bda94, 0xa9200000, 0xf910f998, 0xf8a43d95, 0x140cd900, 0x9abf0000, 0xb803034b, 0x0002dcaa, 0x001a877e, 0x066f448a, - 0x001a277e, 0x000600d9, 0xffa4f100, 0x42408f3f, 0xd99aa00f, 0x00000604, 0x9fa0a43d, 0x30d900f8, + 0x001a277e, 0x000610d9, 0xffa4f100, 0x42408f3f, 0xd99aa00f, 0x00000614, 0x9fa0a43d, 0x30d900f8, 0xbf000014, 0xda943d9f, 0x00002e8c, 0xf9bfa920, 0xa43d95f9, 0x02f900f8, 0xd4bdc4bd, 0x110ab4bd, 0x001f137e, 0x0484a0b8, 0x7e0ab200, 0xc5001a27, 0x0ab201ab, 0x001a877e, 0x08b8c08a, 0x001a277e, 0xa9fffb09, 0xb8c08ab4, 0x1a877e08, 0xb9408a00, 0x1a277e08, 0xffe00900, 0x408ab4a9, 0xb5f008b9, @@ -708,7 +708,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0xbf000014, 0x2978da99, 0x99980000, 0xdf95f90f, 0x00002970, 0x002944d9, 0x069fb500, 0x002968df, 0x059fb500, 0x9f35f4bd, 0xb59fa009, 0x9f35019f, 0xb5320f08, 0x00f8039f, 0x30d900f8, 0xbf000014, 0x2e94da99, 0x99980000, 0xf895f906, 0xd900f800, 0x00001430, 0x98da99bf, 0x98000029, 0x95f90199, - 0x30f500f8, 0xdcdfff18, 0xf9000005, 0xfeffbf82, 0x99b80149, 0x0a000108, 0x7e9fa008, 0xb2001a27, + 0x30f500f8, 0xecdfff18, 0xf9000005, 0xfeffbf82, 0x99b80149, 0x0a000108, 0x7e9fa008, 0xb2001a27, 0x7e080aa0, 0xd9001a27, 0x40000000, 0xf50409fd, 0x95044d1b, 0x99b31fa9, 0x3d044601, 0x01dc4ba4, 0xa87e040c, 0xa4b20037, 0x4500a9b3, 0x76a0b503, 0xb571a0b5, 0xa0b572a0, 0x74a0b573, 0xd975a0b5, 0x00002990, 0x90014ffe, 0x44dae8ff, 0xb5000029, 0xc37e019f, 0xa2320027, 0x0900a033, 0x112ead33, @@ -744,41 +744,41 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0xb8001a87, 0x00061c00, 0x277e0ab2, 0xabc5001a, 0x7e0ab204, 0x90001a87, 0x33950144, 0x01229d01, 0xf59523ff, 0x3eff641b, 0xfe0058dc, 0x90da0140, 0x90000029, 0xd4bd6000, 0x98de0bb2, 0x7e000000, 0x33004674, 0xff2a00ad, 0xfe0142fe, 0x03b20145, 0x2290143d, 0x24559098, 0x0056a03e, 0xb80149fe, - 0x00010899, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x83fb003a, 0xb4bd00e8, 0xda00c04c, - 0x0000299c, 0x000b947e, 0x001430d9, 0xda99bf00, 0x00002a58, 0xf90d9998, 0xf8a43d95, 0x05ccd900, + 0x00010899, 0xecd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x83fb003a, 0xb4bd00e8, 0xda00c04c, + 0x0000299c, 0x000b947e, 0x001430d9, 0xda99bf00, 0x00002a58, 0xf90d9998, 0xf8a43d95, 0x05dcd900, 0x9abf0000, 0x002e70db, 0x7e010c00, 0xf8005e25, 0x5c877e00, 0x3d00f800, 0x5e937ed4, 0xf400f800, 0x12f9e430, 0xb0b2a1b2, 0x6100b0b3, 0xb004b998, 0x0cf40896, 0x0ba43d57, 0x384c7e44, 0x0aafb200, 0x00f0b305, 0x0a09584a, 0x90014afe, 0xafb508aa, 0x010f9801, 0xb60093f0, 0xa9b50294, 0x02afb503, 0xb2100918, 0x18a9351b, 0xb5020f98, 0x099804af, 0x05a9b503, 0xa0a000bf, 0x005b0b7e, 0xf001a6b0, 0x9a120b9c, 0x59ab3e01, 0xfb020a00, 0xe27e1c15, 0x943d0059, 0xf001a6b0, 0xa6f00bac, 0xa29a3c01, - 0x548900f8, 0x9ebf0005, 0xb5019f98, 0x9ea0019f, 0x005a267e, 0x0801a4b3, 0x00f8a43d, 0xff0a02f8, - 0x12f900f8, 0x000f8c89, 0xf20a99bf, 0x380090b3, 0x000fa881, 0xf10a10bf, 0x2c0004b3, 0x000a747e, - 0x19a00109, 0x000f9889, 0x948990a0, 0xff0f0010, 0x90899fa0, 0x90a0000f, 0x000f9489, 0x587e9fa0, - 0x10a00037, 0x12f911fb, 0x000f8c89, 0xb4bd04bd, 0xb44c90a0, 0x0fac8a00, 0x0b947e00, 0x0cb4bd00, - 0x10a08a14, 0x0b947e00, 0x0cb4bd00, 0x10b48a14, 0x0b947e00, 0x107c8900, 0x8990a000, 0xbd001078, - 0x0c90a0b4, 0x10648a14, 0x0b947e00, 0x10808a00, 0x0cb4bd00, 0x0b947e14, 0x109c8900, 0x8990a000, - 0xa0000f98, 0x10948990, 0x8990a000, 0xa0001060, 0x0fa88990, 0x8990a000, 0xa0000f9c, 0x10988990, - 0x8990a000, 0xa0000fa4, 0x0fa08990, 0x8990a000, 0xa0000f90, 0x10608190, 0x0f948900, 0x8090a000, - 0xb2000fac, 0x1400900a, 0x000bd07e, 0x1bf401a6, 0x10a08af5, 0x0bd07e00, 0x10b48a00, 0x0bd07e00, - 0x10648a00, 0x0bd07e00, 0x10808a00, 0x0bd07e00, 0x107c8900, 0x10a08f00, 0x899fa000, 0x8f001078, - 0xa00010b4, 0x5c727e9f, 0xf911fb00, 0xb2a0b232, 0x00a9b3b3, 0xa9bf00c7, 0x94b30101, 0xf8010600, + 0x588900f8, 0x9ebf0005, 0xb5019f98, 0x9ea0019f, 0x005a267e, 0x0801a4b3, 0x00f8a43d, 0xff0a02f8, + 0x12f900f8, 0x000f9c89, 0xf20a99bf, 0x380090b3, 0x000fb881, 0xf10a10bf, 0x2c0004b3, 0x000a747e, + 0x19a00109, 0x000fa889, 0xa48990a0, 0xff0f0010, 0xa0899fa0, 0x90a0000f, 0x000fa489, 0x587e9fa0, + 0x10a00037, 0x12f911fb, 0x000f9c89, 0xb4bd04bd, 0xb44c90a0, 0x0fbc8a00, 0x0b947e00, 0x0cb4bd00, + 0x10b08a14, 0x0b947e00, 0x0cb4bd00, 0x10c48a14, 0x0b947e00, 0x108c8900, 0x8990a000, 0xbd001088, + 0x0c90a0b4, 0x10748a14, 0x0b947e00, 0x10908a00, 0x0cb4bd00, 0x0b947e14, 0x10ac8900, 0x8990a000, + 0xa0000fa8, 0x10a48990, 0x8990a000, 0xa0001070, 0x0fb88990, 0x8990a000, 0xa0000fac, 0x10a88990, + 0x8990a000, 0xa0000fb4, 0x0fb08990, 0x8990a000, 0xa0000fa0, 0x10708190, 0x0fa48900, 0x8090a000, + 0xb2000fbc, 0x1400900a, 0x000bd07e, 0x1bf401a6, 0x10b08af5, 0x0bd07e00, 0x10c48a00, 0x0bd07e00, + 0x10748a00, 0x0bd07e00, 0x10908a00, 0x0bd07e00, 0x108c8900, 0x10b08f00, 0x899fa000, 0x8f001088, + 0xa00010c4, 0x5c727e9f, 0xf911fb00, 0xb2a0b232, 0x00a9b3b3, 0xa9bf00c7, 0x94b30101, 0xf8010600, 0x30180918, 0x0df40896, 0x98fe0105, 0xf9c4020f, 0x050bf403, 0x0998fb01, 0x0394f003, 0x01050bf4, 0x00f4b3fb, 0x98fa0106, 0x99b30109, 0xb3008e00, 0x0085011d, 0xde7e0ab2, 0xa1b2005b, 0x7801a4b3, - 0x02980ab2, 0x5bf97e01, 0x0a747e00, 0x109c8900, 0x909fbf00, 0x9fa001ff, 0x94b399bf, 0x8c890e01, - 0x92a0000f, 0x005ba53e, 0x000fa889, 0x94b399bf, 0x8c8e1700, 0xe9bf000f, 0x18180f18, 0x9f264199, - 0xa0050cf4, 0x7e2ab2e2, 0xb30005c7, 0xa0060030, 0x0a9b7e32, 0x0fa88900, 0xb399bf00, 0x89190090, - 0xbf000f8c, 0x180f1899, 0x26419918, 0x0718f49f, 0x00000e7e, 0x31fb1ab2, 0xd43efa01, 0xa998005b, + 0x02980ab2, 0x5bf97e01, 0x0a747e00, 0x10ac8900, 0x909fbf00, 0x9fa001ff, 0x94b399bf, 0x9c890e01, + 0x92a0000f, 0x005ba53e, 0x000fb889, 0x94b399bf, 0x9c8e1700, 0xe9bf000f, 0x18180f18, 0x9f264199, + 0xa0050cf4, 0x7e2ab2e2, 0xb30005c7, 0xa0060030, 0x0a9b7e32, 0x0fb88900, 0xb399bf00, 0x89190090, + 0xbf000f9c, 0x180f1899, 0x26419918, 0x0718f49f, 0x00000e7e, 0x31fb1ab2, 0xd43efa01, 0xa998005b, 0x0aafb205, 0x0090b3fa, 0x03f99812, 0x96b1e80a, 0x0df400ff, 0xf8010a05, 0xb212f900, 0x03ac98a1, 0x9802aa98, 0xa5db0110, 0x7ea5a5a5, 0x98000b94, 0x1a980319, 0xa0a9bc02, 0x1bbf0aa0, 0x7e041c98, 0xa000373a, 0x00aab90a, 0x98030ab5, 0x0a900519, 0x0109b510, 0x35181918, 0x19984109, 0x0209b502, 0x09b519bf, 0x1819180e, 0x98400935, 0x09b50319, 0x0be77e0f, 0x240a9000, 0x000be77e, 0x180700b5, 0x0909181f, 0xf00c00b5, 0x9fbbfff4, 0x0909b502, 0xa48911fb, 0x93fe0016, 0x05ad8a00, 0x7eb43d00, - 0x0a005dd4, 0x8900f801, 0xa00010c8, 0x8900f89a, 0xbf0010c8, 0x8a00f89a, 0x3d002e80, 0x5e7f7eb4, - 0x00a03300, 0xf809f808, 0x10d08a00, 0x7eb43d00, 0x33005e89, 0xf80600a0, 0xf000f809, 0x94bd00b3, - 0xa5a5a5df, 0x5cd13ea5, 0x90afa000, 0xaa900199, 0xf49ba604, 0x00f8f608, 0x00335089, 0x0010ec8f, + 0x0a005dd4, 0x8900f801, 0xa00010d8, 0x8900f89a, 0xbf0010d8, 0x8a00f89a, 0x3d002e80, 0x5e7f7eb4, + 0x00a03300, 0xf809f808, 0x10e08a00, 0x7eb43d00, 0x33005e89, 0xf80600a0, 0xf000f809, 0x94bd00b3, + 0xa5a5a5df, 0x5cd13ea5, 0x90afa000, 0xaa900199, 0xf49ba604, 0x00f8f608, 0x00335089, 0x0010fc8f, 0xf9b59ab2, 0x35508b01, 0x02b9bb00, 0x7502b5b6, 0xbb7e04fb, 0x00f8005c, 0x0059c27e, 0x0c00a433, 0x005cd87e, 0x005e217e, 0x30f400f8, 0xb262f9e4, 0xb2a5b2c4, 0x72d332b0, 0x44c034e2, 0xb3546034, - 0x00ae00a9, 0xa900b9b3, 0x10ec8900, 0x149fbf00, 0x2ae406ce, 0x0501ffff, 0xf034bfa0, 0xc49ba048, + 0x00ae00a9, 0xa900b9b3, 0x10fc8900, 0x149fbf00, 0x2ae406ce, 0x0501ffff, 0xf034bfa0, 0xc49ba048, 0x943603c9, 0x03f4f002, 0xfd04fd14, 0x9efd059f, 0x059dfd05, 0x3502a4b6, 0x547e1bb9, 0xa0b30038, 0x90347100, 0x1d09354c, 0xb564f034, 0x0275010a, 0x1803350a, 0xb41a0f35, 0x49fe10f0, 0x1c999001, 0xb5019ab5, 0x9fb50390, 0x7594a004, 0x93350a92, 0x35f43d16, 0xf4bd1e0f, 0x9fb59bb2, 0x0140fe02, @@ -796,15 +796,15 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0xbd014efe, 0x18ee90f4, 0x005f163e, 0xff90e9bf, 0x9049bc01, 0xf3a6e9a0, 0xbff408f4, 0x549990e9, 0x0bf459a6, 0xb3e80105, 0x009e0029, 0x990009b3, 0x011db300, 0x02a00096, 0x000a747e, 0xe9980ebf, 0xb9efbf14, 0xf9a60099, 0x01091bf4, 0x5fbd3ed1, 0x54299000, 0x0ebfe9a0, 0xbc545f92, 0xff0cd2f4, - 0x888be9bf, 0x9fbc000f, 0x01e9b590, 0x94bd0fbf, 0xbf0ef9b5, 0xb59fbf09, 0x0fbf029f, 0x9dbcf9bf, + 0x988be9bf, 0x9fbc000f, 0x01e9b590, 0x94bd0fbf, 0xbf0ef9b5, 0xb59fbf09, 0x0fbf029f, 0x9dbcf9bf, 0x03f9b590, 0x93b509bf, 0xb509bf0f, 0x09bf1094, 0xbf119cb5, 0x129cb509, 0xbfbf09bf, 0xbf139fb5, 0x90baa00a, 0xd07e10aa, 0x0abf000b, 0x7e24aa90, 0xbf000bd0, 0xb9f9bf0f, 0xf9b50099, 0x0a9b7e14, 0x5fc73e00, 0xb2fa0100, 0x0455fb1a, 0xa1b242f9, 0xc2b2b4b2, 0xde00d3b2, 0x0cf4baa6, 0x0a747e27, 0xb22ab200, 0xbd540b1c, 0x7e3eb2d4, 0xb2005ed7, 0x01a4b3a0, 0xb23abf0c, 0x5ed27e4b, 0x0a9b7e00, 0xfb0ab200, 0x89008f41, 0x00f9ce02, 0xf70195f0, 0x00f800f9, 0x0089010f, 0x9ff60280, 0xb800f800, 0x000180aa, 0xf609a4b6, 0x00f800ab, 0x03210089, 0xb8009af6, 0x02010099, 0xf8009af6, 0xf030f400, - 0x0005dcdf, 0xbf82f900, 0x0149feff, 0x32309990, 0x7e9fa0a1, 0xc4006014, 0x43feff1a, 0x1ae87e01, - 0x0142fe00, 0xb2ff16c4, 0x0f84d4a5, 0x33900000, 0x2c229024, 0x001400d8, 0x2e68d700, 0x9c3e0000, + 0x0005ecdf, 0xbf82f900, 0x0149feff, 0x32309990, 0x7e9fa0a1, 0xc4006014, 0x43feff1a, 0x1ae87e01, + 0x0142fe00, 0xb2ff16c4, 0x0f94d4a5, 0x33900000, 0x2c229024, 0x001400d8, 0x2e68d700, 0x9c3e0000, 0x093f0061, 0x1e009433, 0xb2987ebc, 0xe949bc6a, 0x001ae87e, 0xa5b21b32, 0x817e0ab2, 0x9c3e000f, 0x09180061, 0x20010f01, 0x35fc0f3f, 0x30b50131, 0xff94f001, 0xfd039990, 0x09bc049f, 0xe949bc90, 0xf0330f3f, 0xf6307307, 0x150cf407, 0x9104f933, 0x05f03300, 0x02fd3355, 0xfe3e00c7, 0xf0330060, @@ -814,60 +814,60 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x3e000014, 0xd9006157, 0x00001428, 0x903e9abf, 0x1cdf0061, 0xbf000014, 0x61903efa, 0x3d2f2000, 0x350ab294, 0x00180229, 0x351b3203, 0x2035012f, 0x0f817e03, 0xb2b4bd00, 0x0f717e2a, 0x0a747e00, 0x19e87e00, 0x0028f400, 0x000a9b7e, 0x00619c3e, 0x0c00a0b3, 0x080c3bb2, 0x0000a77e, 0xbcff1ec4, - 0x05a6084e, 0xfede1bf5, 0x0060057e, 0x900149fe, 0x9fbf3099, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, - 0x003a317e, 0xf41085fb, 0xdcdfb830, 0xf9000005, 0xfeffbf62, 0x99900149, 0xa03c0c60, 0x0140fe9f, - 0x0090b4bd, 0x7e0ab224, 0xd9000b94, 0x01000000, 0x002e68d1, 0xa09bb200, 0x0f84d919, 0xa4bd0000, + 0x05a6084e, 0xfede1bf5, 0x0060057e, 0x900149fe, 0x9fbf3099, 0x0005ecd9, 0xa699bf00, 0x070bf4f9, + 0x003a317e, 0xf41085fb, 0xecdfb830, 0xf9000005, 0xfeffbf62, 0x99900149, 0xa03c0c60, 0x0140fe9f, + 0x0090b4bd, 0x7e0ab224, 0xd9000b94, 0x01000000, 0x002e68d1, 0xa09bb200, 0x0f94d919, 0xa4bd0000, 0xf57e9ba0, 0x1bbf001a, 0x343da4bd, 0x7e008046, 0xbf00601f, 0x75020911, 0x09350406, 0x0101b501, 0x350a0335, 0xb4bd0b03, 0xda00804c, 0x01000000, 0x000b947e, 0xbd00804c, 0x0080dab4, 0x947e0100, - 0x057e000b, 0x80df0060, 0xd4010000, 0x00002e6c, 0x4fa0fab2, 0x00602c7e, 0xd0d24fbf, 0x75000010, + 0x057e000b, 0x80df0060, 0xd4010000, 0x00002e6c, 0x4fa0fab2, 0x00602c7e, 0xe0d24fbf, 0x75000010, 0x03350806, 0x80f99012, 0xd90229b5, 0x00001b04, 0xb5030fb5, 0x1dd90329, 0xfe00001b, 0x29b50145, - 0x1f559005, 0x53350109, 0x35592003, 0xecd91309, 0xb5000010, 0x0975012f, 0x1b0ddf01, 0x04090000, + 0x1f559005, 0x53350109, 0x35592003, 0xfcd91309, 0xb5000010, 0x0975012f, 0x1b0ddf01, 0x04090000, 0x35042fb5, 0x32df0259, 0x0900000e, 0x062fb540, 0x20015935, 0x0a747e03, 0x7e2abf00, 0xb200009b, 0x7e5ab20b, 0x7e000f71, 0x0f000a9b, 0x11004907, 0xd1009ff7, 0x00001408, 0x900140fe, 0x1abf2300, 0x010c0bb2, 0xc17eff0d, 0xa4330000, 0x093ff400, 0xee019433, 0x00603d7e, 0x0062de3e, 0x00140cd9, 0x8e9fbf00, 0xcf01c000, 0x99c700e9, 0x0090b34c, 0x0190b32e, 0x3e02f8f6, 0xcf006307, 0x99c700f9, 0x0090b34c, 0x0190b30e, 0x3e02f8f6, 0x8a00631b, 0xcf01c200, 0xa4f000aa, 0x9000f801, 0x008960ff, - 0x9ff601c1, 0x00f1df00, 0x99b88000, 0xf7020100, 0x9fcf009f, 0x3e9fb200, 0xf900631b, 0x0604d002, + 0x9ff601c1, 0x00f1df00, 0x99b88000, 0xf7020100, 0x9fcf009f, 0x3e9fb200, 0xf900631b, 0x0614d002, 0xa0330000, 0x0ba02400, 0x066f448a, 0x001a277e, 0xffc00049, 0x448ab4a9, 0xb5f1066f, 0x877e2000, - 0xb03e001a, 0x448a0063, 0x277e066f, 0x00d9001a, 0xbf000006, 0xc000499b, 0x8a94a9ff, 0xf1066f44, + 0xb03e001a, 0x448a0063, 0x277e066f, 0x10d9001a, 0xbf000006, 0xc000499b, 0x8a94a9ff, 0xf1066f44, 0xff3fffb4, 0x877eb59b, 0x4089001a, 0x09a00f42, 0x01fba43d, 0xa0b212f9, 0x448ab1b2, 0x277e066f, 0xa9b2001a, 0x0c0104b3, 0x01b0aae7, 0x0063da3e, 0x04b3ff0a, 0x9ae42300, 0xa9e43fff, 0x1bf42000, 0x3ef4bd09, 0x8f0063eb, 0x94fe0000, 0xa43d03a9, 0xa095f9ff, 0x8a11fb19, 0x7e066f40, 0xe4001a27, - 0xf12000a9, 0xb33fffa4, 0x89080090, 0xb6fe0000, 0x9aff03a4, 0xdf00f8a5, 0x00000608, 0xf9f430f4, - 0xfef0b232, 0x99900149, 0x019fb510, 0x0005dcdf, 0xbdffbf00, 0x3591a014, 0x01020191, 0x99909220, + 0xf12000a9, 0xb33fffa4, 0x89080090, 0xb6fe0000, 0x9aff03a4, 0xdf00f8a5, 0x00000618, 0xf9f430f4, + 0xfef0b232, 0x99900149, 0x019fb510, 0x0005ecdf, 0xbdffbf00, 0x3591a014, 0x01020191, 0x99909220, 0xa03c0308, 0xbd0ab29f, 0x7e3cb2b4, 0x09000b94, 0x08023505, 0x35030135, 0x01350103, 0x04023502, 0x008f0920, 0xf9cf01c0, 0x4c99c700, 0x610099b3, 0x0190b301, 0x3e02f8f5, 0xcf006466, 0x99c700f9, - 0x0099b34c, 0x90b30134, 0x02f8f501, 0x00647b3e, 0xfe00008f, 0xff0394b6, 0x08df95f9, 0xb5000006, + 0x0099b34c, 0x90b30134, 0x02f8f501, 0x00647b3e, 0xfe00008f, 0xff0394b6, 0x18df95f9, 0xb5000006, 0x008f03f9, 0xf9cf01c0, 0x4c99c700, 0xe80099b3, 0x0190b300, 0x3e02f8f5, 0xcf0064a6, 0x99c700f9, 0x0099b34c, 0x90b300b8, 0x02f8f501, 0x0064bb3e, 0xfe00008f, 0x00140cd9, 0x949dbf00, 0xf9ff03e9, - 0x0608df95, 0xf9b50000, 0xc0008f04, 0x00f9cf01, 0xb34c99c7, 0xb3660090, 0xf8f60190, 0x64ed3e02, + 0x0618df95, 0xf9b50000, 0xc0008f04, 0x00f9cf01, 0xb34c99c7, 0xb3660090, 0xf8f60190, 0x64ed3e02, 0x00f9cf00, 0xb34c99c7, 0xb30e0090, 0xf8f60190, 0x65013e02, 0xc2008f00, 0x00ffcf01, 0x001400d9, - 0xde9abf00, 0x00000608, 0xc711f9c7, 0xe93519ff, 0x14ef3515, 0x0c014bfe, 0x10bb9008, 0x00006e7e, - 0x900149fe, 0x9fbf1899, 0x0005dcd9, 0xa699bf00, 0xa10bf5f9, 0x65ee3e00, 0x60df9000, 0x01c10089, + 0xde9abf00, 0x00000618, 0xc711f9c7, 0xe93519ff, 0x14ef3515, 0x0c014bfe, 0x10bb9008, 0x00006e7e, + 0x900149fe, 0x9fbf1899, 0x0005ecd9, 0xa699bf00, 0xa10bf5f9, 0x65ee3e00, 0x60df9000, 0x01c10089, 0xdf009ff6, 0x800000f1, 0x010099b8, 0x009ff702, 0xb2009fcf, 0x65013e9f, 0xc2008900, 0x0099cf01, 0xe41095b6, 0xe420009f, 0xb33fff9e, 0xff4500fd, 0x0064d43e, 0x066f448f, 0x01c10089, 0xdf009ff6, 0x800000f1, 0x010099b8, 0x009ff702, 0xb2009fcf, 0x64bb3e9f, 0xc2008900, 0x0099cf01, 0x20009fe4, 0x3fff94f1, 0xcc00fdb3, 0x64943efe, 0x6f408f00, 0xc1008906, 0x009ff601, 0x0000f1df, 0x0099b880, 0x9ff70201, 0x009fcf00, 0x7b3e9fb2, 0x317e0064, 0x35fb003a, 0x64177e0c, 0x3cd97e00, 0xdf00f800, - 0x00000608, 0xf9f430f4, 0xfef0b242, 0x99900149, 0x019fb514, 0x0005dcdf, 0xbdffbf00, 0x3591a014, + 0x00000618, 0xf9f430f4, 0xfef0b242, 0x99900149, 0x019fb514, 0x0005ecdf, 0xbdffbf00, 0x3591a014, 0x01030191, 0x99909320, 0xa0a43208, 0xb23c029f, 0xb2b4bd0a, 0x0b947e2c, 0x35050900, 0x03350102, 0x08013504, 0x35090435, 0x01350201, 0x8f092003, 0xcf01c000, 0x99c700f9, 0x0099b34c, 0x90b30166, 0x02f8f501, 0x0066533e, 0xc700f9cf, 0x99b34c99, 0xb3013900, 0xf8f50190, 0x66683e02, 0x00008f00, - 0x0394b6fe, 0xdf95f9ff, 0x00000608, 0x8f03f9b5, 0xcf01c000, 0x99c700f9, 0x0099b34c, 0x90b300ed, + 0x0394b6fe, 0xdf95f9ff, 0x00000618, 0x8f03f9b5, 0xcf01c000, 0x99c700f9, 0x0099b34c, 0x90b300ed, 0x02f8f501, 0x0066933e, 0xc700f9cf, 0x99b34c99, 0xb300c000, 0xf8f50190, 0x66a83e02, 0x00008f00, - 0x0394b6fe, 0xdf95f9ff, 0x00000608, 0x3304f9b5, 0xd9370040, 0x0000140c, 0x008e9fbf, 0xe9cf01c0, + 0x0394b6fe, 0xdf95f9ff, 0x00000618, 0x3304f9b5, 0xd9370040, 0x0000140c, 0x008e9fbf, 0xe9cf01c0, 0x4c99c700, 0x6a0090b3, 0xf60190b3, 0xde3e02f8, 0xf9cf0066, 0x4c99c700, 0x3a0090b3, 0xf60190b3, 0xf23e02f8, 0x00d90066, 0xbf000014, 0x014bfe9a, 0xbb90080c, 0x006e7e14, 0x0149fe00, 0xbf1c9990, - 0x05dcd99f, 0x99bf0000, 0x0bf5f9a6, 0xe03e00ba, 0x00890067, 0x99cf01c2, 0x0608de00, 0x9fc70000, + 0x05ecd99f, 0x99bf0000, 0x0bf5f9a6, 0xe03e00ba, 0x00890067, 0x99cf01c2, 0x0618de00, 0x9fc70000, 0x1899c710, 0x3516ef35, 0x063e15e9, 0xff900067, 0xc1008960, 0x009ff601, 0x0000f1df, 0x0099b880, 0x9ff70201, 0x009fcf00, 0xf23e9fb2, 0x00890066, 0x99cf01c2, 0x009fe400, 0xff94f120, 0x00fdb33f, 0xc13eff40, 0x448f0066, 0x0089066f, 0x9ff601c1, 0x00f1df00, 0x99b88000, 0xf7020100, 0x9fcf009f, 0x3e9fb200, 0x890066a8, 0xcf01c200, 0x9fe40099, 0x94f12000, 0xfdb33fff, 0x3efec700, 0x8f006681, 0x89066f40, 0xf601c100, 0xf1df009f, 0xb8800000, 0x02010099, 0xcf009ff7, 0x9fb2009f, 0x0066683e, - 0x003a317e, 0xf90c45fb, 0x0604d902, 0x90bf0000, 0x003cdf7e, 0xf07e010a, 0x010a0024, 0x0065ff7e, + 0x003a317e, 0xf90c45fb, 0x0614d902, 0x90bf0000, 0x003cdf7e, 0xf07e010a, 0x010a0024, 0x0065ff7e, 0x0cb2010a, 0xabb2d43d, 0x003aa97e, 0x0600a033, 0x01fb02f8, 0x0062fc7e, 0x2600a433, 0xc4bdb4bd, 0x020ad43d, 0x003aa97e, 0xf07ea43d, 0xa43d0024, 0x0065ff7e, 0x00221d7e, 0x003ce57e, 0xf07e00f8, - 0x00f80024, 0xdfcc30f4, 0x000005dc, 0xffbf82f9, 0x900149fe, 0x48fe5499, 0xfe9fa001, 0x99920144, + 0x00f80024, 0xdfcc30f4, 0x000005ec, 0xffbf82f9, 0x900149fe, 0x48fe5499, 0xfe9fa001, 0x99920144, 0xfef4bd10, 0x46fe0147, 0x019fb501, 0x88909fa0, 0x4c449050, 0x90347790, 0x00d92466, 0xbf000014, 0x014bfe9a, 0xbb90080c, 0x7eff0d44, 0x320000c1, 0x00a433a5, 0x1200b4e9, 0x3433033f, 0x0918e005, 0x45203404, 0x0f009033, 0x9d33e301, 0x3e008701, 0x180068c3, 0x0b98050a, 0x635b7e02, 0x3ea13200, @@ -896,16 +896,16 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x3d001a87, 0xf401fba4, 0x62f9fc30, 0x900149fe, 0xa4321f99, 0x96b29c20, 0xb2c4d3b2, 0x7e080aff, 0xd9001a27, 0x40000000, 0x010504bd, 0x3e14a9ff, 0xbc006bdd, 0x5abca002, 0x6b617ea4, 0x0014b300, 0x3b8fda1d, 0x6bb20000, 0xa97e3cb2, 0xa4330015, 0x09f80c00, 0xe43e040a, 0x0090006b, 0xf4402601, - 0xa43dd40c, 0xf40465fb, 0xdcdff830, 0xf9000005, 0xfeffbf12, 0x99900149, 0xa0b1b20c, 0x8aabb29f, + 0xa43dd40c, 0xf40465fb, 0xecdff830, 0xf9000005, 0xfeffbf12, 0x99900149, 0xa0b1b20c, 0x8aabb29f, 0x7e08c040, 0xda001a87, 0x00006b48, 0x00dcb4bd, 0x7e01312d, 0x0e0015a9, 0x00a03304, 0x0140fe1f, 0xb2080090, 0x6aff7e0a, 0x33ae3200, 0xbf0d00a4, 0xf491a609, 0x3e0e050b, 0x900149fe, 0x9fbf0c99, - 0x0005dcd9, 0x3299bf00, 0xf4f9a6ea, 0x317e070b, 0x15fb003a, 0xb212f908, 0x8aa1b2b0, 0x7e08d100, + 0x0005ecd9, 0x3299bf00, 0xf4f9a6ea, 0x317e070b, 0x15fb003a, 0xb212f908, 0x8aa1b2b0, 0x7e08d100, 0x89001a27, 0xf1ff0000, 0xffffff04, 0x008ab4a9, 0x0bff08d1, 0x1a877eb5, 0xd1708a00, 0xff14f108, 0x0000db03, 0x14b6c000, 0xb51bff10, 0x001a877e, 0x08d1748a, 0x001a277e, 0x02010089, 0xf700a3f0, 0xa43d009a, 0x12f911fb, 0x08d1708a, 0xb032c132, 0x290000db, 0x1a877ec2, 0xd1748a00, 0x1a277e08, 0xf8a4f100, 0x0002dbff, 0xabffa229, 0xd1708ab5, 0x1a877e08, 0x0f14f000, 0x94ff04f0, 0x0994081f, 0xff94f10c, 0xd1708aff, 0x0404b608, 0x2a0000db, 0xff04f0a2, 0xfd0509fd, 0x0ffd0501, 0xb50bff05, - 0x001a877e, 0x11fba43d, 0xdfdc30f4, 0x000005dc, 0xffbf72f9, 0x900149fe, 0xa2324099, 0xb4329fa0, + 0x001a877e, 0x11fba43d, 0xdfdc30f4, 0x000005ec, 0xffbf72f9, 0x900149fe, 0xa2324099, 0xb4329fa0, 0xd632c532, 0xe4b3e3b2, 0x243d0a00, 0x006e433e, 0x143dff00, 0x0e32f4bd, 0xf0953fbc, 0x0bf40194, 0xf40e260d, 0xf032051b, 0x90011110, 0xf4b301ff, 0x1630ea10, 0x120cf410, 0xc4ff1fc4, 0xf9bcff09, 0x1076b070, 0xf80b0df4, 0x3e020209, 0xb2006e43, 0x6b617e3a, 0x325c3200, 0x324b326d, 0x6ca67e2a, @@ -915,16 +915,16 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x006b617e, 0x08d1148a, 0x001a277e, 0xfebf7f49, 0xa9ff0143, 0x8a0132b4, 0x9008d114, 0x877e2033, 0x0104001a, 0x006e253e, 0x7ea440bc, 0x8a006b61, 0x7e08d114, 0xbc001a27, 0xa5b69000, 0x9039bc10, 0x60011110, 0xff10c49a, 0x1ef407a6, 0x12b0b4de, 0xb213c0b4, 0x0ed4bd3a, 0x21367e20, 0x00a03300, - 0xfe02f806, 0x99900149, 0xd99fbf40, 0x000005dc, 0x2a3299bf, 0x0bf4f9a6, 0x3a317e07, 0x2475fb00, - 0xd9e830f4, 0x000005dc, 0x99bf52f9, 0x90014ffe, 0xa2b22cff, 0xc08af9a0, 0x277e08b8, 0xa5b2001a, + 0xfe02f806, 0x99900149, 0xd99fbf40, 0x000005ec, 0x2a3299bf, 0x0bf4f9a6, 0x3a317e07, 0x2475fb00, + 0xd9e830f4, 0x000005ec, 0x99bf52f9, 0x90014ffe, 0xa2b22cff, 0xc08af9a0, 0x277e08b8, 0xa5b2001a, 0x08b8c08a, 0x7e045bc5, 0xda001a87, 0x00006b38, 0x408cb4bd, 0x0400030d, 0x0015a97e, 0xa800a933, 0xc0408a00, 0x1a277e08, 0x0141fe00, 0x11902bb2, 0xb21aa028, 0x69607e1a, 0x33a03200, 0x008900ad, 0xf00f19bf, 0x4afe13b2, 0x049ffd01, 0x900195f0, 0x19a018aa, 0x7fd1a4b2, 0x7e02faf0, 0xbf001581, 0x7e2bb23a, 0x32006be7, 0x3ea433a0, 0x7e4ab221, 0xa600159c, 0xea0df4a1, 0x2bb23abf, 0x006be77e, 0xdf3ea433, 0x0e3e0400, 0xa033006f, 0x49fe3a00, 0x28999001, 0x41fe99bf, 0x0142fe01, 0x90241190, 0x19a02022, 0xff7e2ab2, 0xa433006a, 0x2bbf1a00, 0x607e1ab2, 0xa4330069, 0x1bbf0e00, 0x08c0408a, - 0x001a877e, 0x08b8c08a, 0x877e5bb2, 0x49fe001a, 0x2c999001, 0xdcd99fbf, 0xbf000005, 0xa60a3299, - 0x070bf4f9, 0x003a317e, 0xf41855fb, 0xdcdfdc30, 0xf9000005, 0xf4ffbf82, 0x49fef830, 0x4c999001, + 0x001a877e, 0x08b8c08a, 0x877e5bb2, 0x49fe001a, 0x2c999001, 0xecd99fbf, 0xbf000005, 0xa60a3299, + 0x070bf4f9, 0x003a317e, 0xf41855fb, 0xecdfdc30, 0xf9000005, 0xf4ffbf82, 0x49fef830, 0x4c999001, 0x40fe9fa0, 0x0c999201, 0x0090f4bd, 0x0142fe2c, 0x9fb593b2, 0xd89fa001, 0x00001420, 0x07482290, 0x90040602, 0x8abf0c05, 0x080c3bb2, 0xc17eff0d, 0xa4330000, 0x3198f400, 0x33193f01, 0x98eb0a94, 0x1f180119, 0x01341804, 0x199009a0, 0x019e9804, 0x98010eb5, 0x0eb5029e, 0x039e9802, 0x98030eb5, @@ -932,14 +932,14 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x020c1803, 0x7e040d18, 0x3e006ca6, 0x98007046, 0x0b98010a, 0x6c557e02, 0x70463e00, 0x010a9800, 0x006e607e, 0x0070463e, 0x0a1859bf, 0x030b1801, 0x18020c18, 0x0e98040d, 0x0091b002, 0xb0015998, 0x087e0191, 0xad33006d, 0x35ff6000, 0x2720022a, 0x32031e18, 0x351ab24b, 0x2e350126, 0x0f817e03, - 0xbd2ab200, 0x0f717eb4, 0x6fa63e00, 0x05d4d900, 0x9abf0000, 0x001410db, 0x7e010c00, 0x7e005e25, + 0xbd2ab200, 0x0f717eb4, 0x6fa63e00, 0x05e4d900, 0x9abf0000, 0x001410db, 0x7e010c00, 0x7e005e25, 0xf800709e, 0x1430d900, 0x9fbf0000, 0x8dda943d, 0x2000002e, 0x02f998a9, 0xa43d95f9, 0xa17e00f8, 0xaa7e003c, 0x00f8003b, 0xf9f830f4, 0xf4a1b222, 0xb2b2fc30, 0x900140fe, 0x0ca01000, 0x7e010db5, 0x09003da3, 0x00a033ff, 0x0109981e, 0x002944da, 0xb21cb200, 0x0091b02d, 0xab980ebf, 0x42ea7e07, - 0x32a93200, 0x0430f49a, 0xdf0825fb, 0x000005dc, 0x30f4ffbf, 0x0149fef0, 0xa00c9990, 0x2944d99f, + 0x32a93200, 0x0430f49a, 0xdf0825fb, 0x000005ec, 0x30f4ffbf, 0x0149fef0, 0xa00c9990, 0x2944d99f, 0x9f980000, 0x0149fe07, 0x9bb59aa0, 0x98febf01, 0x999001ff, 0xbdbcb208, 0x02febbd4, 0x9fa0abb2, - 0x040e9ab2, 0x0021367e, 0x0800a033, 0x010a02f8, 0x900149fe, 0x9fbf0c99, 0x0005dcd9, 0xa699bf00, - 0x070bf4f9, 0x003a317e, 0xf81030f4, 0xc030f400, 0x0005dcd9, 0xbf82f900, 0x014ffe99, 0xfe60ff90, + 0x040e9ab2, 0x0021367e, 0x0800a033, 0x010a02f8, 0x900149fe, 0x9fbf0c99, 0x0005ecd9, 0xa699bf00, + 0x070bf4f9, 0x003a317e, 0xf81030f4, 0xc030f400, 0x0005ecd9, 0xbf82f900, 0x014ffe99, 0xfe60ff90, 0xf9a00146, 0x669094bd, 0x1691b02c, 0xfe1591b0, 0x48fe0144, 0x04699001, 0x90404490, 0x91b05c88, 0x72cb3e09, 0x1650b400, 0x9d33593f, 0x9801410b, 0x5f18015e, 0x04599004, 0xe0344ea0, 0x2be13055, 0xb5019e98, 0x9e98014e, 0x024eb502, 0xb5039e98, 0x9998034e, 0x0449b504, 0x2d01f033, 0xf401f630, @@ -956,16 +956,16 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x19bf0000, 0x9ab8a2b2, 0x7e0004e8, 0xb2001a27, 0xf01abfa0, 0xaab80104, 0x7e0004e0, 0x09001a27, 0x0004b301, 0x18a9c707, 0x21fb2920, 0x0cd902f9, 0xbf000014, 0xb8a0b299, 0x0005109a, 0x001a277e, 0xa0f3aac7, 0xf901fb0a, 0x140cd922, 0x99bf0000, 0xb1b2a0b2, 0x9ab8c2b2, 0x7e000510, 0xc7001a27, - 0x096049a9, 0x6046a9c7, 0x81aac719, 0x21fb2a60, 0xf9ec30f4, 0x140cd142, 0x19bf0000, 0xdcd3a4b2, + 0x096049a9, 0x6046a9c7, 0x81aac719, 0x21fb2a60, 0xf9ec30f4, 0x140cd142, 0x19bf0000, 0xecd3a4b2, 0xfe000005, 0x9ab80142, 0xbf000500, 0x24229039, 0x900140fe, 0x29a01400, 0x001a277e, 0x0aa019bf, 0x05049ab8, 0x1a277e00, 0xb519bf00, 0x9ab8010a, 0x7e000508, 0xbf001a27, 0x020ab519, 0x050c9ab8, 0x1a277e00, 0xb50bb200, 0x100c030a, 0x7e7e4ab2, 0x2fbf000b, 0xf9a639bf, 0x7e070bf4, 0xfb003a31, - 0x30f41445, 0x05dcdff0, 0x22f90000, 0x00140cd0, 0xbfffbf00, 0x0149fe0e, 0xb2189990, 0xb89fa0a2, + 0x30f41445, 0x05ecdff0, 0x22f90000, 0x00140cd0, 0xbfffbf00, 0x0149fe0e, 0xb2189990, 0xb89fa0a2, 0x0004f8ea, 0x001a277e, 0x0abfa9b2, 0x94189e95, 0x9f94089d, 0x0895b618, 0xff0094f1, 0xfd05fefd, 0x00d905f9, 0xfd00ff00, 0xfdfd04d9, 0x0141fe05, 0x04fcaab8, 0x0c119000, 0xa00140fe, 0x1400901f, 0x277e0fa0, 0x2eb2001a, 0xbd011ab5, 0x00a1dbd4, 0x2e010000, 0x35f80d3c, 0xdd9002e1, 0x00a1dc01, 0xf9c40000, 0x64ffc70f, 0x3c98b93c, 0xe935f8bf, 0x90ef2001, 0xd4b303ee, 0xa9c4de04, 0x98c93c0f, - 0xc70d2935, 0xc93c64a9, 0x0c293598, 0x900149fe, 0x9fbf1899, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, + 0xc70d2935, 0xc93c64a9, 0x0c293598, 0x900149fe, 0x9fbf1899, 0x0005ecd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xf91025fb, 0x29ccdb02, 0xcedc0000, 0xdd000029, 0x000029d0, 0x0029cada, 0x69c67e00, 0x299cd000, 0x09980000, 0x29bcda01, 0x95f10000, 0x09b51e00, 0x73e27e01, 0x01099800, 0x0029d2da, 0x0095f100, 0x0109b501, 0x0073707e, 0xf1010998, 0xb5200095, 0x01fb0109, 0x00299cdd, 0x98dcbf00, @@ -978,25 +978,25 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x0660e08a, 0x001a277e, 0x00b31aa0, 0xe48a0e00, 0x277e0660, 0x0aa0001a, 0x480020b3, 0x0660e88a, 0x001a277e, 0x203e2aa0, 0x020a0076, 0x3601d433, 0x0e00b0b3, 0xe48abbbf, 0x877e0660, 0x20b3001a, 0x2bbf0e00, 0x0660e88a, 0x001a877e, 0x140010b3, 0x5c7e1ab2, 0x1bbf008c, 0x0660e08a, 0x001a877e, - 0x21fba43d, 0x0005dcdf, 0xf4ffbf00, 0x49fef430, 0x08999001, 0x008f9fa0, 0xf9cf01c0, 0x4c99c700, + 0x21fba43d, 0x0005ecdf, 0xf4ffbf00, 0x49fef430, 0x08999001, 0x008f9fa0, 0xf9cf01c0, 0x4c99c700, 0x4c0099b3, 0x0190b301, 0x3e02f8f5, 0xcf00763a, 0x99c700f9, 0x0099b34c, 0x90b30125, 0x02f8f501, 0x00764f3e, 0xffffffd9, 0xc4f9ff7f, 0x01c0008f, 0xc700f9cf, 0x99b34c99, 0xb300db00, 0xf8f50190, 0x76703e02, 0x00f9cf00, 0xb34c99c7, 0xb30e0090, 0xf8f60190, 0x76853e02, 0xc0008f00, 0x00f9cf01, 0xb34c99c7, 0x008d0099, 0xf50190b3, 0x9d3e02f8, 0xf9cf0076, 0x4c9dc700, 0x5e00d0b3, 0xf601d0b3, - 0xb23e02f8, 0xf9100076, 0x48e93501, 0xe100fd33, 0x0648d900, 0x4ffe0000, 0x01f9b501, 0x002e7cd9, - 0xa09abf00, 0x204809fd, 0xde0909f9, 0x00000648, 0x0409e920, 0x3502ecb5, 0x4bfe01fd, 0x03ed3501, + 0xb23e02f8, 0xf9100076, 0x48e93501, 0xe100fd33, 0x0658d900, 0x4ffe0000, 0x01f9b501, 0x002e7cd9, + 0xa09abf00, 0x204809fd, 0xde0909f9, 0x00000658, 0x0409e920, 0x3502ecb5, 0x4bfe01fd, 0x03ed3501, 0x3502ed35, 0x080c01e9, 0x00006e7e, 0x0077ad3e, 0xad3e09f8, 0x00890077, 0x99cf01c2, 0x299cde00, 0xef180000, 0x26ff0948, 0x9d1bf4f9, 0x0077ad3e, 0x0660e08f, 0x01c10089, 0xdf009ff6, 0x800000f1, 0x010099b8, 0x009ff702, 0xb2009fcf, 0x76b23e9f, 0x60e08f00, 0xc1008906, 0x009ff601, 0x010099b8, 0x009cf600, 0x0000f2df, 0x0099b880, 0x9ff60202, 0x009fcf00, 0x853e9fb2, 0x00890076, 0x9fcf01c2, 0x1ff99500, 0x8c0194b3, 0x0076643e, 0x0660e08f, 0x01c10089, 0xdf009ff6, 0x800000f1, 0x010099b8, - 0x009ff702, 0xb2009fcf, 0x764f3e9f, 0x0149fe00, 0xbf089990, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, - 0x3a317e07, 0x0c30f400, 0x30f400f8, 0x05dcdff4, 0x22f90000, 0x49feffbf, 0x14999001, 0x9fa0c1b2, + 0x009ff702, 0xb2009fcf, 0x764f3e9f, 0x0149fe00, 0xbf089990, 0x05ecd99f, 0x99bf0000, 0x0bf4f9a6, + 0x3a317e07, 0x0c30f400, 0x30f400f8, 0x05ecdff4, 0x22f90000, 0x49feffbf, 0x14999001, 0x9fa0c1b2, 0x00299cd9, 0x019f9800, 0x00d9d2b2, 0x0e400000, 0x04f9fd08, 0x33750bf4, 0x0e1000a0, 0x01a43303, 0x3ea0326c, 0x3d007809, 0x33040e04, 0x7e5e00b4, 0x33008a7a, 0x4b2400a0, 0x04330080, 0x884b0700, - 0x014afe00, 0xaa90080c, 0x8b2e7e0c, 0x33060e00, 0x3e3a00a4, 0xd9007883, 0x00000644, 0x080e99bf, + 0x014afe00, 0xaa90080c, 0x8b2e7e0c, 0x33060e00, 0x3e3a00a4, 0xd9007883, 0x00000654, 0x080e99bf, 0x290090b3, 0x90014ffe, 0x00330cff, 0x9e981000, 0x98fea020, 0x623e2199, 0x9e980078, 0x98fea022, - 0xf9b52399, 0x78833e01, 0x0149fe00, 0xbf149990, 0x05dcd99f, 0x99bf0000, 0xf9a6ea32, 0x3e200bf4, + 0xf9b52399, 0x78833e01, 0x0149fe00, 0xbf149990, 0x05ecd99f, 0x99bf0000, 0xf9a6ea32, 0x3e200bf4, 0xfe007898, 0x99900149, 0x0e9fbf0c, 0x981fa01f, 0x29a00199, 0x0078693e, 0x003a317e, 0x090c25fb, 0x0aa9a024, 0xd900f81f, 0x0000299c, 0xf9e830f4, 0x2d9f9882, 0x98289298, 0x90982b91, 0x0df1b029, 0x980bc1b0, 0xd1b02a9f, 0x09e1b00a, 0xbf2e9998, 0x64f2ffcc, 0xb07410ff, 0xc1b00e91, 0x0da0330c, @@ -1017,37 +1017,37 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x7aa73e1f, 0x32060900, 0x1885fb9a, 0x010000d9, 0xffa4f001, 0xb6ffb4f0, 0xb4b614a4, 0xa0a9bc0f, 0xabbc22f9, 0xb2c0b220, 0x242ab8d1, 0x277e0020, 0x0309001a, 0xb364aac7, 0x090c00a0, 0x04a0b301, 0x20943d06, 0x142ab809, 0x277e0030, 0x0309001a, 0xb364aac7, 0x090c00a0, 0x04a0b301, 0x20943d06, - 0xf421fb19, 0xdcdff030, 0xf9000005, 0xf4ffbf32, 0x49fefc30, 0x20999001, 0x41fe9fa0, 0x9094bd01, + 0xf421fb19, 0xecdff030, 0xf9000005, 0xf4ffbf32, 0x49fefc30, 0x20999001, 0x41fe9fa0, 0x9094bd01, 0x4efe1c11, 0x9019a001, 0xe9a018ee, 0xd3b2c2b2, 0xb926ff09, 0xfe201bf4, 0x240b0140, 0xb2140090, 0x87d77e0c, 0xffa4f000, 0x3c1fa4b3, 0x10a000bf, 0x007b6e3e, 0xf000e1b0, 0xb4f0ffa4, 0x0c1eb2ff, 0x7e240d05, 0xf0008850, 0xa4b3ffa4, 0x49fe1a1f, 0x1c999001, 0x1f0a99bf, 0x49fe29a0, 0x18999001, - 0x39a099bf, 0x900149fe, 0x9fbf2099, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xfb0430f4, - 0x30f41035, 0x05dcdff0, 0x32f90000, 0x30f4ffbf, 0x0149fefc, 0xa0209990, 0x0141fe9f, 0x119094bd, + 0x39a099bf, 0x900149fe, 0x9fbf2099, 0x0005ecd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xfb0430f4, + 0x30f41035, 0x05ecdff0, 0x32f90000, 0x30f4ffbf, 0x0149fefc, 0xa0209990, 0x0141fe9f, 0x119094bd, 0x014efe18, 0xee9019a0, 0xb2e9a014, 0x09d3b2c2, 0xf4b926ff, 0x40fe1d1b, 0x90240b01, 0x0cb21c00, 0x0087d77e, 0x391fa433, 0x10a000bf, 0x007c073e, 0xf000e1b0, 0xb4f0ffa4, 0x0c1eb2ff, 0x7e240d08, 0x33008850, 0xfe1a1fa4, 0x99900149, 0x0a99bf18, 0xfe29a01f, 0x99900149, 0xa099bf14, 0x0149fe39, - 0xbf209990, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x3a317e07, 0x0430f400, 0xf41035fb, 0xdcdff430, + 0xbf209990, 0x05ecd99f, 0x99bf0000, 0x0bf4f9a6, 0x3a317e07, 0x0430f400, 0xf41035fb, 0xecdff430, 0xf9000005, 0xf4ffbf22, 0x49fefc30, 0x18999001, 0x4efe9fa0, 0x9094bd01, 0x40fe14ee, 0x90e9a001, 0x09a01000, 0xd2b2c1b2, 0xb926ff09, 0xb20f1bf4, 0x7e240bec, 0x3e0087d7, 0xb0007c8c, 0xa4f00001, 0xffb4f0ff, 0x240d010c, 0x0088507e, 0x201fa433, 0x900149fe, 0x99bf1499, 0x90014ffe, 0xffbf10ff, - 0x038199e7, 0xffe719a0, 0x2fa00381, 0x900149fe, 0x9fbf1899, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, - 0x003a317e, 0xfb0430f4, 0x30f40c25, 0x05dcdff4, 0x22f90000, 0x30f4ffbf, 0x0149fefc, 0xa0189990, + 0x038199e7, 0xffe719a0, 0x2fa00381, 0x900149fe, 0x9fbf1899, 0x0005ecd9, 0xa699bf00, 0x070bf4f9, + 0x003a317e, 0xfb0430f4, 0x30f40c25, 0x05ecdff4, 0x22f90000, 0x30f4ffbf, 0x0149fefc, 0xa0189990, 0x014efe9f, 0xee9094bd, 0x0140fe14, 0x0090e9a0, 0xb209a010, 0x09d2b2c1, 0xf4b926ff, 0xecb20f1b, 0xd77e240b, 0x1b3e0087, 0x01b0007d, 0xffa4f000, 0x0cffb4f0, 0x7e240d20, 0x33008850, 0xfe181fa4, - 0x99900149, 0xa099bf14, 0x0149fe19, 0xbf109990, 0xfe29a099, 0x99900149, 0xd99fbf18, 0x000005dc, - 0xf9a699bf, 0x7e070bf4, 0xf4003a31, 0x25fb0430, 0xf430f40c, 0x0005dcdf, 0xbf52f900, 0x0149feff, + 0x99900149, 0xa099bf14, 0x0149fe19, 0xbf109990, 0xfe29a099, 0x99900149, 0xd99fbf18, 0x000005ec, + 0xf9a699bf, 0x7e070bf4, 0xf4003a31, 0x25fb0430, 0xf430f40c, 0x0005ecdf, 0xbf52f900, 0x0149feff, 0x32209990, 0xb29fa0b0, 0xb00405c4, 0x0cf523a6, 0x34bd00bb, 0xfe0142fe, 0x22900141, 0x1c119018, 0x13a023a0, 0x2cb21bb2, 0x0084407e, 0xad33a532, 0xbf009b1f, 0x7e2bbf1a, 0x330084fc, 0xa00a00a4, 0x7e293e43, 0xbf2fbf00, 0x0ff4b619, 0xbc1494b6, 0x00df90f9, 0xbc010100, 0x0033909f, 0x06302e04, 0x0b0cf404, 0x65030433, 0x007dd83e, 0x2d050033, 0x59060433, 0x007e093e, 0x22889ab8, 0x1a277e00, 0x10a5b600, 0x007df33e, 0x7e8c9a90, 0xf1001a27, 0xa003ffa4, 0x7e293e4a, 0x889ab800, 0x277e0032, 0xa3f0001a, 0x7df33e00, 0x8c9ab800, 0x277e0032, 0xae95001a, 0xe8a9c718, 0xf0f0afc7, 0x9fbcffa4, - 0x909abc90, 0xa0909ebc, 0x0149fe49, 0xbf209990, 0x05dcd99f, 0x99bf0000, 0xf9a65a32, 0x7e070bf4, - 0xfb003a31, 0x30f40c55, 0x05dcdff4, 0x42f90000, 0x49feffbf, 0x1c999001, 0xa0014efe, 0x18ee909f, + 0x909abc90, 0xa0909ebc, 0x0149fe49, 0xbf209990, 0x05ecd99f, 0x99bf0000, 0xf9a65a32, 0x7e070bf4, + 0xfb003a31, 0x30f40c55, 0x05ecdff4, 0x42f90000, 0x49feffbf, 0x1c999001, 0xa0014efe, 0x18ee909f, 0x4ffe94bd, 0x90e9a001, 0xf9a014ff, 0xc4b2a132, 0xb926ff09, 0xb22b1bf4, 0xbdf2b2e3, 0x320ab204, 0x7e3cb21b, 0x33007d51, 0xbf311fa4, 0x9039bf2f, 0x9fbc0100, 0xb329a090, 0x3ee62404, 0xc4007eae, 0xfcb2ffba, 0x517e1b32, 0xa433007d, 0x49fe0e1f, 0x14999001, 0x49a099bf, 0x900149fe, 0x9fbf1c99, - 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xf40c45fb, 0xdcdfb830, 0xf9000005, 0xfeffbf82, + 0x0005ecd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xf40c45fb, 0xecdfb830, 0xf9000005, 0xfeffbf82, 0x99900149, 0xa0010568, 0x11c1b09f, 0xb049b130, 0xe1b010d1, 0x33c4bf0f, 0x30180aa0, 0x08f40aa6, 0x3302050f, 0x050c0ba0, 0x0ca03303, 0xbd543d06, 0x014ffe94, 0xff9064bd, 0xb504bd60, 0xf9a001f9, 0xff9274bd, 0xb2f92008, 0xb20ab2f1, 0x860e7e1b, 0x1fad3300, 0x193f0480, 0x1c009033, 0xb4bd010a, @@ -1062,10 +1062,10 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0xe9b5049b, 0x17f99801, 0xb5049cfd, 0xd99817f9, 0x049bfd01, 0x3e01d9b5, 0xf00083b1, 0x9cdbff54, 0xb2000029, 0x0394b659, 0x98909bbc, 0x9998209f, 0x1451b01f, 0xfd04f1fd, 0x90a60490, 0xa6081bf4, 0x100bf4f1, 0x44bd010e, 0xbd4ae130, 0x80db3e54, 0xb244bd00, 0xbd0cb21d, 0x3eb43d54, 0xc40080d0, - 0x0bf401c9, 0x14f0b425, 0x0006a4de, 0xffb9c400, 0xbc0394b6, 0x94b6909f, 0x909ebc03, 0x9f989ebf, + 0x0bf401c9, 0x14f0b425, 0x0006b4de, 0xffb9c400, 0xbc0394b6, 0x94b6909f, 0x909ebc03, 0x9f989ebf, 0x404ebc01, 0x10515fbc, 0xdd9501bb, 0x01cc9d01, 0xf495cdff, 0xf43dcc1b, 0xb44af130, 0x9cdb1490, 0xb6000029, 0x9bbc0394, 0x189f9890, 0xfd179998, 0x90fd04f1, 0xf490a604, 0xf1a6091b, 0x01200bf5, - 0xe43d94bd, 0xb01791b0, 0xe1301691, 0x81dc3e4b, 0x0169c400, 0x00b90bf5, 0x344b9034, 0x84df4bc0, + 0xe43d94bd, 0xb01791b0, 0xe1301691, 0x81dc3e4b, 0x0169c400, 0x00b90bf5, 0x344b9034, 0x94df4bc0, 0x0a000006, 0xff94f001, 0x9894b4bd, 0xffc4f006, 0x7e808fbc, 0xd20039cd, 0x000029f8, 0xb000b9b9, 0xa1b00db1, 0x00abb90e, 0xb00b91b0, 0x8db20cb1, 0xa034343d, 0x09d1b04b, 0x4cfe3b32, 0x58cc9001, 0x0089ca7e, 0x2c9829bf, 0x09d0b401, 0x351fa033, 0xdea0e4bd, 0xb401deb5, 0x2f980cb0, 0x092e9808, @@ -1075,7 +1075,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x34ff321b, 0xff0949f0, 0x0bf4f926, 0x1490b429, 0x00299cdb, 0x0394b600, 0x98909bbc, 0x9998189f, 0x04f1fd17, 0xa60490fd, 0xd71bf590, 0xf5f1a601, 0xb401d11b, 0xe5f013e0, 0x13e1b004, 0x900149fe, 0x96bf6099, 0xb4019798, 0x9cdf1490, 0x3d000029, 0xb624bde4, 0x34bd0394, 0x30909fbc, 0x9b9057e1, - 0x5c98907c, 0x3e0ab1b0, 0xc40082cf, 0x0bf40109, 0x14f0b472, 0xde579034, 0x00000684, 0x0006a4db, + 0x5c98907c, 0x3e0ab1b0, 0xc40082cf, 0x0bf40109, 0x14f0b472, 0xde579034, 0x00000694, 0x0006b4db, 0xf0010a00, 0x94b6ff94, 0x909fbc03, 0xb6039f94, 0xfbbc0394, 0x909ebcf0, 0x979896bf, 0x01f7b501, 0xc034f6a0, 0xbcb4bd57, 0x37bc2026, 0xffc4f031, 0x0039cd7e, 0xbf018f98, 0x00b9b98e, 0xb904f9fd, 0x8fb500a9, 0x04e9fd01, 0xf0b48ea0, 0x98f9bf0a, 0x9afd01ff, 0x05fbfd05, 0xa00ab0b4, 0x01bfb5b9, @@ -1086,7 +1086,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0xa60ffffe, 0x190df4c9, 0x950aaf95, 0xb9940abd, 0x059ffd16, 0x9eb2dfb2, 0xfdb2ecb2, 0xb0b4030f, 0x03f4f013, 0xb9fffc09, 0xe5f9ff94, 0x0d00d4b3, 0x0fffff89, 0x0df4c9a6, 0x08e9c50a, 0x0083a03e, 0xb694c9ff, 0x0fdf0494, 0xffff0000, 0xf9fdf4ef, 0xfff70905, 0xa03e94f9, 0x90b40083, 0x0895f013, - 0x0a10e0b4, 0xb4e2a01f, 0xf3a00ff0, 0xa011b0b4, 0x0149feb9, 0xbf689990, 0x05dcd99f, 0x99bf0000, + 0x0a10e0b4, 0xb4e2a01f, 0xf3a00ff0, 0xa011b0b4, 0x0149feb9, 0xbf689990, 0x05ecd99f, 0x99bf0000, 0x0bf4f9a6, 0x83e63e28, 0x49e03400, 0x73b262b2, 0xe926ff09, 0xfb8b1bf5, 0x71b260b2, 0x007f7d3e, 0xb13e090a, 0x317e0083, 0x85fb003a, 0xc0008f48, 0x00f9cf01, 0xb34c99c7, 0xb3220090, 0xf8f60190, 0x83f13e02, 0x00f9cf00, 0xb34c99c7, 0xb3330090, 0xf8f60190, 0x84053e02, 0xc1008900, 0x009af601, @@ -1099,16 +1099,16 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x05f9bbff, 0xbb94f0ff, 0x9ebb04fe, 0x00ffb904, 0xfd04fdfd, 0xcfa005f9, 0x01fb1f0a, 0xb1b212f9, 0xeb7ea0b2, 0xa033003c, 0xa43d0a00, 0x00853e3e, 0xdf0f1994, 0x01017000, 0xbc1404b6, 0x09bc000f, 0x000ab800, 0x277e0006, 0xa1b2001a, 0x03800ab8, 0x1a277e00, 0x05a1fd00, 0xf001a6f0, 0x11fb01a4, - 0xdff430f4, 0x000005dc, 0xffbf32f9, 0x900149fe, 0xb2b21899, 0x06039fa0, 0xf523a6b0, 0xfe00960c, + 0xdff430f4, 0x000005ec, 0xffbf32f9, 0x900149fe, 0xb2b21899, 0x06039fa0, 0xf523a6b0, 0xfe00960c, 0x40fe0141, 0x14119001, 0xb2100090, 0x7e0cb21b, 0x32008440, 0x1fa433a3, 0xbf1abf7c, 0x84fc7e0b, 0x00a03300, 0xbf19bf5a, 0x1494b60a, 0xbc0fa4b6, 0x00d9a0a9, 0xbc010100, 0x277ea0a9, 0xa4f0001a, 0x04a0b3ff, 0x04a6b04c, 0xb0130cf4, 0x0cf402a6, 0x01a6b039, 0x3e2d18f4, 0xb30085db, 0xb02c08a0, 0x0cf408a6, 0x05a4b30b, 0x85db3e10, 0x0aa0b300, 0x0ba0b31a, 0x3e060310, 0xbd0085f1, 0x85ef3e94, - 0x3e010900, 0x090085ef, 0x85ef3e02, 0xa0030900, 0x0149fe29, 0xbf189990, 0x05dcd99f, 0x99bf0000, - 0xf9a63a32, 0x7e070bf4, 0xfb003a31, 0x30f40c35, 0x05dcd9f8, 0x12f90000, 0x4ffe99bf, 0x0cff9001, + 0x3e010900, 0x090085ef, 0x85ef3e02, 0xa0030900, 0x0149fe29, 0xbf189990, 0x05ecd99f, 0x99bf0000, + 0xf9a63a32, 0x7e070bf4, 0xfb003a31, 0x30f40c35, 0x05ecd9f8, 0x12f90000, 0x4ffe99bf, 0x0cff9001, 0xf9a0b1b2, 0x40feff09, 0x08009001, 0x0bb209a0, 0x0085407e, 0x0e1fa433, 0x96b009bf, 0x0b9cf002, - 0x49fe1920, 0x0c999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x15fb003a, 0xe830f408, - 0x0005dcdf, 0xbf42f900, 0x0149feff, 0xb2289990, 0xb29fa0b0, 0x02a033c3, 0x02a63045, 0x330c0cf4, + 0x49fe1920, 0x0c999001, 0xecd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x15fb003a, 0xe830f408, + 0x0005ecdf, 0xbf42f900, 0x0149feff, 0xb2289990, 0xb29fa0b0, 0x02a033c3, 0x02a63045, 0x330c0cf4, 0x00a601ad, 0x0086963e, 0xb407a933, 0x08ad3300, 0x4a3e0098, 0xbab20087, 0x900140fe, 0x0bb22700, 0x00860e7e, 0xad33a232, 0x3f01141f, 0x00963009, 0xf00b9cf0, 0xb83e0196, 0x04020087, 0xf523b630, 0xc400fb0c, 0x44feffba, 0x0141fe01, 0x90204490, 0x4bb21c11, 0x407e1cb2, 0xa2320084, 0xde1fad33, @@ -1119,51 +1119,51 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0xb21bb214, 0x84407e4c, 0x33a23200, 0xc44f1fa4, 0x40feff0a, 0x20009001, 0x0e7e0bb2, 0xa2320086, 0x3a1fa433, 0x9433093f, 0x3f090a00, 0x0087b83e, 0x4b3f1a3f, 0xfe0141fe, 0x11900140, 0x1c009027, 0x0db21cb2, 0x007aac7e, 0x1f3f093f, 0xf00794f0, 0x94b607f4, 0x059ffd03, 0x49fe39a0, 0x28999001, - 0xdcd99fbf, 0xbf000005, 0xa62a3299, 0x070bf4f9, 0x003a317e, 0xf41845fb, 0xdcdff830, 0xf9000005, + 0xecd99fbf, 0xbf000005, 0xa62a3299, 0x070bf4f9, 0x003a317e, 0xf41845fb, 0xecdff830, 0xf9000005, 0xfeffbf62, 0xff010149, 0xfe209990, 0xa5320142, 0xc4b2b3b2, 0x04bd9fa0, 0xb21c2290, 0x882a3e16, 0xb25a3200, 0x7e2cb20b, 0x3300865d, 0xbf2a1fa4, 0xf416a629, 0x91b2091b, 0x0088273e, 0x0bf419a6, - 0x3e090a09, 0x90008835, 0x03a60100, 0xbfd508f4, 0xa01f0a22, 0x0149fe42, 0xbf209990, 0x05dcd99f, - 0x99bf0000, 0x0bf4f9a6, 0x3a317e07, 0x0865fb00, 0xdff830f4, 0x000005dc, 0xffbf82f9, 0x900149fe, + 0x3e090a09, 0x90008835, 0x03a60100, 0xbfd508f4, 0xa01f0a22, 0x0149fe42, 0xbf209990, 0x05ecd99f, + 0x99bf0000, 0x0bf4f9a6, 0x3a317e07, 0x0865fb00, 0xdff830f4, 0x000005ec, 0xffbf82f9, 0x900149fe, 0xc2b22899, 0xd5b2b0b2, 0x9fa0cbb2, 0xa4b2e7b2, 0x7ea000bc, 0xb20016fc, 0xbca3b25b, 0x0ab2c022, 0x7e6032bc, 0x01008458, 0x0c80b404, 0x7500a033, 0x43fe30b2, 0x24339001, 0x0088bb3e, 0x0bb24a32, 0x5d7e3cb2, 0xa1320086, 0x591fa433, 0x0bb23cbf, 0x00904ab2, 0x7e7db201, 0xa600846b, 0x4218f405, 0x08f406a6, 0x88f13eda, 0xb24a3200, 0x7e3cb20b, 0x3200865d, 0x1fa433a1, 0xb23cbf2c, 0x904ab20b, 0x8db20100, 0x00846b7e, 0x08f405a6, 0x89013e10, 0x0143fe00, 0x902062bc, 0x02a62433, 0x01cd08f4, - 0x0149fe1f, 0xbf289990, 0x05dcd99f, 0x99bf0000, 0xf9a61a32, 0x7e070bf4, 0xfb003a31, 0x30f40885, - 0x05dcdff4, 0x62f90000, 0x94bdffbf, 0xfe0141fe, 0x11900140, 0x1c009020, 0x09a019a0, 0x900149fe, + 0x0149fe1f, 0xbf289990, 0x05ecd99f, 0x99bf0000, 0xf9a61a32, 0x7e070bf4, 0xfb003a31, 0x30f40885, + 0x05ecdff4, 0x62f90000, 0x94bdffbf, 0xfe0141fe, 0x11900140, 0x1c009020, 0x09a019a0, 0x900149fe, 0xb2b22499, 0xd5b2c6b2, 0x1bb29fa0, 0x407e0cb2, 0xa3320084, 0x591fa433, 0x0bbf1abf, 0x0084fc7e, 0x0a00a433, 0xad3e0903, 0x19bf0089, 0x94b600bf, 0x0f04b614, 0x7e0009bc, 0xd900010e, 0x01015000, 0xbc0009bc, 0x60bc4002, 0x7e1ab210, 0xb2001a27, 0x7e4ab2a0, 0xb2001a27, 0x7e1ab2a2, 0xa6001a27, - 0xe81bf40a, 0x0001087e, 0xa00150b5, 0x0149fe52, 0xbf249990, 0x05dcd99f, 0x99bf0000, 0xf9a63a32, - 0x7e070bf4, 0xfb003a31, 0x30f40c65, 0x05dcdff4, 0x02f90000, 0x49feffbf, 0x0c999001, 0x9fa0c0b2, + 0xe81bf40a, 0x0001087e, 0xa00150b5, 0x0149fe52, 0xbf249990, 0x05ecd99f, 0x99bf0000, 0xf9a63a32, + 0x7e070bf4, 0xfb003a31, 0x30f40c65, 0x05ecdff4, 0x02f90000, 0x49feffbf, 0x0c999001, 0x9fa0c0b2, 0x040aaf32, 0xf423f630, 0x94bd780c, 0x90014dfe, 0xd9b504dd, 0x33d9a001, 0x302501b0, 0x08f401b6, 0x02b03311, 0x331f0a28, 0x3e3c03b4, 0xc4008a36, 0x4c4bfffa, 0x15504c15, 0x008a3f3e, 0x4bfffac4, 0x504c1d4c, 0x8a3f3e1d, 0xfffac400, 0x4c15f44b, 0x3f3e15f8, 0xfac4008a, 0x1df44bff, 0x7e1df84c, 0xfe00891e, 0x99900149, 0x989ebf04, 0xe5b60199, 0x069f9506, 0xb51a94b6, 0xe9fd010f, 0xfe0ea005, - 0x99900149, 0xd99fbf0c, 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, 0x9cd90c05, 0x18000029, + 0x99900149, 0xd99fbf0c, 0x000005ec, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, 0x9cd90c05, 0x18000029, 0x00f8159a, 0xa033080f, 0x1f0f1901, 0xf401a630, 0xa9121008, 0x30060f30, 0x0cf40496, 0x32070f05, - 0xf400f8fa, 0x22f9f830, 0x0005dcd2, 0xfe29bf00, 0x11900141, 0x0140fe10, 0x0e7e19a0, 0x00900001, + 0xf400f8fa, 0x22f9f830, 0x0005ecd2, 0xfe29bf00, 0x11900141, 0x0140fe10, 0x0e7e19a0, 0x00900001, 0x7e0ab20c, 0xdf00732c, 0x0000299c, 0xf9980ebf, 0x15feb515, 0x9cf09ea6, 0x58f9350b, 0x0001087e, 0x29bf1fbf, 0x0bf4f9a6, 0x3a317e07, 0x0825fb00, 0x00299cd9, 0x15991800, 0xbeb2adb2, 0x9033cfb2, - 0xb4d91a00, 0x98000029, 0x9bbf019c, 0x367efab2, 0x847e0021, 0x00f8008a, 0x000644d9, 0xb29abf00, + 0xb4d91a00, 0x98000029, 0x9bbf019c, 0x367efab2, 0x847e0021, 0x00f8008a, 0x000654d9, 0xb29abf00, 0xbcecb2cb, 0x7e7ea0ad, 0x1f0a000b, 0xbdb200f8, 0xa0b3ceb2, 0xb6b13800, 0x0cf423bf, 0x23c04930, 0xa6029bbb, 0x250cf4c9, 0x00299cd9, 0x15991800, 0x9033010f, 0xb4d91a00, 0x98000029, 0x9bbf019c, - 0x0020d07e, 0x6c3eaf32, 0x020f008b, 0x00f8fa32, 0xdfd830f4, 0x000005dc, 0xffbf72f9, 0x900149fe, + 0x0020d07e, 0x6c3eaf32, 0x020f008b, 0x00f8fa32, 0xdfd830f4, 0x000005ec, 0xffbf72f9, 0x900149fe, 0x46fe4499, 0xb29fa001, 0xb2b1b2a0, 0x246690c4, 0x23c0a6b1, 0xb17d0cf4, 0xf423c0b6, 0xbabc760c, 0xc096b190, 0x6c0cf423, 0x000e067e, 0xd50302c4, 0x000029b4, 0x07ff29c4, 0x3209bc20, 0x008c033e, 0x5c985bbf, 0xb26ab201, 0x7e200e3d, 0x330020d0, 0x000a00a0, 0x8c093e06, 0xff29c400, 0xa60279bc, 0x050df401, 0x2bc410b2, 0xff0cc4ff, 0x04f04ab2, 0xb06bbcff, 0xbb203390, 0x7e7e0210, 0x40bc000b, - 0xb3243d40, 0x00bd0014, 0x0ddd7e1f, 0x8c133e00, 0xfe060000, 0x99900149, 0xd99fbf44, 0x000005dc, + 0xb3243d40, 0x00bd0014, 0x0ddd7e1f, 0x8c133e00, 0xfe060000, 0x99900149, 0xd99fbf44, 0x000005ec, 0x0a3299bf, 0x0bf4f9a6, 0x3a317e07, 0x2875fb00, 0x00299cd9, 0x15991800, 0xbeb2adb2, 0x0a009033, - 0x008b707e, 0x44d900f8, 0xbf000006, 0xb2cab29b, 0xb0bdbcec, 0x000b7e7e, 0x00f81f0a, 0xdff430f4, - 0x000005dc, 0xffbf32f9, 0x900149fe, 0xa2b21899, 0xa9bf9fa0, 0xb39899c7, 0x00aa1d99, 0x00299cd9, + 0x008b707e, 0x54d900f8, 0xbf000006, 0xb2cab29b, 0xb0bdbcec, 0x000b7e7e, 0x00f81f0a, 0xdff430f4, + 0x000005ec, 0xffbf32f9, 0x900149fe, 0xa2b21899, 0xa9bf9fa0, 0xb39899c7, 0x00aa1d99, 0x00299cd9, 0x02999800, 0xb34299c7, 0x009a0099, 0x0a0140fe, 0x14009001, 0xef7e0bb2, 0xa4330094, 0x4bfe551f, 0x90020a01, 0xef7e10bb, 0xa4330094, 0x09bf451f, 0x04bd0103, 0xbc1493ff, 0x94f09530, 0x121bf401, 0x0f0204b3, 0x009a457e, 0x0700a033, 0x900415f0, 0x04b30100, 0x49fee50a, 0x14999001, 0x19a699bf, 0x0a150bf4, 0x7e1bb201, 0x3300950a, 0xf80a1fa0, 0x8d233e09, 0xfe2ebf00, 0x99900149, 0xdf99bf10, 0xbfffffff, 0xeffd1f0a, 0x0099b904, 0xf09419ff, 0x96f00b9c, 0x1e94b601, 0xa0059efd, 0x8d233e29, - 0xfe1f0a00, 0x99900149, 0xd99fbf18, 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, 0x30f40c35, - 0x05dcdfe4, 0x52f90000, 0x49feffbf, 0x30999001, 0x9fa0a3b2, 0xc5b2afbf, 0xfdc7b4b2, 0x00ddb31d, + 0xfe1f0a00, 0x99900149, 0xd99fbf18, 0x000005ec, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, 0x30f40c35, + 0x05ecdfe4, 0x52f90000, 0x49feffbf, 0x30999001, 0x9fa0a3b2, 0xc5b2afbf, 0xfdc7b4b2, 0x00ddb31d, 0xfa95075d, 0x10f99508, 0xa132f032, 0xf9339232, 0x3000d515, 0x0cf415f6, 0x05f93346, 0xf63005fc, 0x1c0cf405, 0x8701f933, 0x301f0a00, 0x08f501f6, 0xf630073a, 0x250cf503, 0x8e283e07, 0x10f93300, 0xf630041b, 0x0e0cf410, 0xf50df630, 0x3e070f08, 0x33009156, 0x070711fd, 0x0091603e, 0x431df933, @@ -1212,18 +1212,18 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x0093513e, 0xffc7ff49, 0x95f194f9, 0x1c3e0800, 0xff490093, 0x94f9ffc7, 0x100095f1, 0xfe3fff8f, 0xe5049ffd, 0x3ec0009f, 0x49009351, 0xf9ffc7ff, 0x0095f194, 0x93433e08, 0xc7ff4900, 0xf194f9ff, 0x8f100095, 0xfdfe3fff, 0x008f049f, 0x9fff0100, 0x299cd9f5, 0x99180000, 0x00903350, 0x0000890f, - 0x95f9ff02, 0x00936f3e, 0xfdffff89, 0xa094f9ff, 0x94313e49, 0x16a63000, 0x01480cf5, 0xd9ffafc4, + 0x95f9ff02, 0x00936f3e, 0xfdffff89, 0xa094f9ff, 0x94313e49, 0x17a63000, 0x01480cf5, 0xd9ffafc4, 0x000004d0, 0xd9e89fbc, 0x0000299c, 0xefc7080a, 0x989fbc3b, 0xbb96efc7, 0x94f0059f, 0x2b0bf501, 0xff29c401, 0x010defe7, 0x0a029b54, 0xf5bf6604, 0xf0011918, 0xb9e400f3, 0xf9bcffff, 0x04c6b0c2, 0x0c090df4, 0x93cb3e04, 0xe44da000, 0xc4ffffba, 0xebe703e9, 0x94330142, 0xbabc1200, 0x29bcd9b0, - 0x4ab20000, 0x0093f43e, 0x000644d9, 0xbc99bf00, 0x4ab2b0ba, 0x7eb09bbc, 0x3e000b7e, 0x32009431, + 0x4ab20000, 0x0093f43e, 0x000654d9, 0xbc99bf00, 0x4ab2b0ba, 0x7eb09bbc, 0x3e000b7e, 0x32009431, 0x9acb7e9b, 0x94c83e00, 0x00a03300, 0x33080a0f, 0x00b1011d, 0x0094c83e, 0x900140fe, 0x0ab22400, 0x0072fb7e, 0xa54f093f, 0x00943300, 0xa05a0f06, 0x3e1f0a4f, 0xd90094c8, 0x0000299c, 0x33159918, 0x00870099, 0x3802a033, 0xf402a630, 0xa0330f0c, 0xa4331800, 0x703e6e01, 0xa0330094, 0xa4332c03, 0x903e6204, 0x3ab20094, 0x009d827e, 0x0094c83e, 0xcbb2bab2, 0x009ffc7e, 0x0094c83e, 0x0b7e2a32, 0xc83e009d, 0x2a320094, 0x00a2127e, 0x0094c83e, 0xa67e2a32, 0xc83e00a1, 0x9cd90094, 0x18000029, 0x90331599, 0xfbc72400, 0xb22c326c, 0xf05eb24d, 0xac7e0fa4, 0xc83e009e, 0x020a0094, 0x0094c83e, - 0xc83e030a, 0x090a0094, 0x900149fe, 0x9fbf3099, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, + 0xc83e030a, 0x090a0094, 0x900149fe, 0x9fbf3099, 0x0005ecd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xf01c55fb, 0xa4b6ffa4, 0x0acaa002, 0x3200f81f, 0x30040aaf, 0x0cf402f6, 0xfff4f012, 0x002a5cd9, 0xf89fbc00, 0xbfa01f0a, 0xaf3200f8, 0xf630040a, 0x100cf402, 0xd9fff4f0, 0x00002a5c, 0x9bbc1f0a, 0xf900f8f9, 0x10af9512, 0xae95b1b2, 0x299cd008, 0xff090000, 0x1bf4e926, 0x4909183d, 0x1bf5f926, @@ -1241,20 +1241,20 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0xf49ba632, 0x9ea60808, 0xa62008f4, 0x080df4b9, 0x08f4bfa6, 0x2a68df16, 0x9fbc0000, 0xb0bfbca0, 0x000b7e7e, 0x00966e3e, 0xd03e040a, 0x030a0096, 0xc9b221fb, 0x0fffa6b1, 0xbc2b0cf4, 0x96b1909a, 0x0cf41000, 0x2a68de21, 0xaebc0000, 0x00d03390, 0x3e9ab20a, 0xb20096fb, 0x7e9bb2ba, 0x0a000b7e, - 0x0a00f81f, 0xf400f804, 0xdcdfe430, 0xf9000005, 0xfeffbf12, 0x99900149, 0xa0a0b220, 0xf0d1b29f, + 0x0a00f81f, 0xf400f804, 0xecdfe430, 0xf9000005, 0xfeffbf12, 0x99900149, 0xa0a0b220, 0xf0d1b29f, 0xedb2ffb4, 0xb40aa0b4, 0x09c40be0, 0xf49ba607, 0x0fc7751b, 0x0149fe2f, 0xa0089990, 0x029eb59d, 0xbc019ab5, 0x94bdb89f, 0x90014ffe, 0xf9a014ff, 0xb501fcb5, 0x09c702f1, 0xbcbabf23, 0x0fc7c8f9, 0x8a09c785, 0xf0e09f3c, 0x0dc71ff4, 0x05cfbb91, 0xb990d93c, 0xd4f000ee, 0x1fe4f01f, 0xbc0099b9, 0x94f0e0ef, 0xbcff0f1f, 0xf9bc909d, 0x05febb95, 0xfd049dbb, 0x99b904fc, 0x04fdbb00, 0xfd049afd, - 0xb9a0059f, 0x900149fe, 0x9fbf2099, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xf41c15fb, - 0xdcd9f430, 0xf9000005, 0xb299bf82, 0x014ffed1, 0xa02cff90, 0x92dd3ff9, 0x1f0003ff, 0xf0351709, - 0x02f03501, 0xb6b2f920, 0xa5b2e3b2, 0x1900d433, 0x000530db, 0x7e240c00, 0x09000b7e, 0x200a3209, + 0xb9a0059f, 0x900149fe, 0x9fbf2099, 0x0005ecd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xf41c15fb, + 0xecd9f430, 0xf9000005, 0xb299bf82, 0x014ffed1, 0xa02cff90, 0x92dd3ff9, 0x1f0003ff, 0xf0351709, + 0x02f03501, 0xb6b2f920, 0xa5b2e3b2, 0x1900d433, 0x000534db, 0x7e240c00, 0x09000b7e, 0x200a3209, 0x98823e19, 0x30030a00, 0x0cf409d6, 0x0147fe78, 0xb2ffc4c4, 0x90043df8, 0x793e2477, 0x09c40098, 0x947bb2ff, 0x040c0292, 0x3da026bc, 0x96d27ed4, 0x1fa43300, 0xc47fbf6b, 0x94a607f9, 0xc75e18f4, 0x991223f9, 0x01963001, 0xc7520cf4, 0xe9c42ffe, 0xc8893cff, 0xc78afdc7, 0xd93c85f9, 0xf49c2690, 0xe0333b0c, 0xf9c73803, 0x909d3c91, 0x0cf49c26, 0x9052bc2c, 0xa0010010, 0x26193f9f, 0xa108f409, - 0x49fe1f0a, 0x2c999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0xb23e230b, 0x0d0a0098, 0x0fc439bf, - 0x0000deff, 0x9efdff00, 0x05f9fd04, 0x823e3fa0, 0x317e0098, 0x85fb003a, 0xa830f40c, 0x0005dcd9, + 0x49fe1f0a, 0x2c999001, 0xecd99fbf, 0xbf000005, 0xf4f9a699, 0xb23e230b, 0x0d0a0098, 0x0fc439bf, + 0x0000deff, 0x9efdff00, 0x05f9fd04, 0x823e3fa0, 0x317e0098, 0x85fb003a, 0xa830f40c, 0x0005ecd9, 0xbf82f900, 0xf830f499, 0x4ffea7b2, 0x80ff9001, 0xaabff9a0, 0xb00eb1b0, 0xa6c70dc1, 0x01691268, 0xf5039630, 0xc7013b0c, 0x96306ca9, 0x310cf50a, 0x0141fe01, 0x900140fe, 0x00905711, 0x10a5b650, 0xb4bd1920, 0xe37e0cb2, 0xad330094, 0xbf011d1f, 0x0142fe09, 0x90ff6bc4, 0xb4b65822, 0xbc2ab204, @@ -1266,12 +1266,12 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x0433009a, 0x043d3f1f, 0x0099f53e, 0x98ff09c4, 0x1d98021c, 0x0de0b403, 0x90014ffe, 0xf9bc58ff, 0x0e90b4a8, 0x1001e1b0, 0x3b320100, 0xb20091b0, 0x97077e7e, 0x57903400, 0x08f40926, 0x9a083ed2, 0x3d19bf00, 0x1f929584, 0x90013310, 0x36261055, 0xff4208f5, 0x80331b0a, 0x243e1100, 0x030a009a, - 0x009a273e, 0xfe3fa034, 0x99900149, 0xd99fbf80, 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xf4003a31, - 0x85fb0830, 0xf430f458, 0x0005dcdf, 0xbf12f900, 0x0149feff, 0xfe109990, 0x9fa00141, 0x4a0c1190, + 0x009a273e, 0xfe3fa034, 0x99900149, 0xd99fbf80, 0x000005ec, 0xf9a699bf, 0x7e070bf4, 0xf4003a31, + 0x85fb0830, 0xf430f458, 0x0005ecdf, 0xbf12f900, 0x0149feff, 0xfe109990, 0x9fa00141, 0x4a0c1190, 0x040b00b8, 0x307e1cb2, 0xa433008c, 0x40fe2b1f, 0x00b44a01, 0x0b080090, 0x7e0cb204, 0x33008c30, 0xbf161fa4, 0xa60fbf19, 0x0b9cf09f, 0x320196f0, 0x9a973e9a, 0xfea43d00, 0x99900149, 0xd99fbf10, - 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, 0xa9980c15, 0x90afb204, 0x010b59ac, 0x4a2095f0, - 0xf9b50090, 0x8c307e04, 0xf400f800, 0xdcd99030, 0xf9000005, 0xfe99bf52, 0xff90014f, 0xa0030e84, + 0x000005ec, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, 0xa9980c15, 0x90afb204, 0x010b59ac, 0x4a2095f0, + 0xf9b50090, 0x8c307e04, 0xf400f800, 0xecd99030, 0xf9000005, 0xfe99bf52, 0xff90014f, 0xa0030e84, 0x00ad33f9, 0x9cd90105, 0x18000029, 0x99335999, 0x3200f600, 0x014cfeba, 0xcc90b4bd, 0x94e37e20, 0x33ae3200, 0x00e31fad, 0x4a0144fe, 0x449000b8, 0xb2040b1c, 0x8c307e4c, 0x33ae3200, 0x00cb1fad, 0x4a0140fe, 0x009000b4, 0xb2040b18, 0x8c307e0c, 0x33ae3200, 0x00b31fad, 0x4abf09bf, 0x0bf5a9a6, @@ -1280,20 +1280,20 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x90b0729b, 0xb3f0bcaa, 0x7e2cb200, 0xe4008c30, 0x32ffff0f, 0x1fa433ae, 0x7b39bf51, 0x2fbc0210, 0x90f9bc20, 0x0fff94f1, 0x147339a0, 0x49fec700, 0x20999001, 0x99909abf, 0xfe9c3f07, 0x010d014b, 0xf028bb90, 0xc4b6ffc4, 0x96d27e02, 0x33ae3200, 0xb2171fa4, 0x00b84a4c, 0xf07e040b, 0xae32008a, - 0x009be63e, 0x49fe090e, 0x84999001, 0xdcd99fbf, 0xbf000005, 0xa6ea3299, 0x070bf4f9, 0x003a317e, + 0x009be63e, 0x49fe090e, 0x84999001, 0xecd99fbf, 0xbf000005, 0xa6ea3299, 0x070bf4f9, 0x003a317e, 0x987055fb, 0x008f04a9, 0x9ffd3ff0, 0x04a9b505, 0xaeb200f8, 0x0a10bf12, 0x26ee0904, 0x2e0df4f9, 0x0a00c433, 0x2d3eea7f, 0xea58009c, 0x00a07301, 0x26ff0918, 0x140bf4b9, 0xffffa9e4, 0xf0059bbb, - 0x1bf40194, 0xf8090a07, 0xf81f0a00, 0xf830f400, 0x0005dcdf, 0xbf32f900, 0x0149feff, 0x900140fe, + 0x1bf40194, 0xf8090a07, 0xf81f0a00, 0xf830f400, 0x0005ecdf, 0xbf32f900, 0x0149feff, 0x900140fe, 0x43fe1499, 0xb29fa001, 0x90b1b2a2, 0x33901300, 0x10ec4a12, 0x0cb2010b, 0x008b707e, 0x741fa433, 0xa6300a3f, 0x690cf401, 0x210020b3, 0x94ffa4f0, 0x240b05a9, 0xb202a4b6, 0xa0a9bc2c, 0x10eeaab8, 0x8b707e00, 0x1fa43300, 0x0010b34b, 0x0b0a3f23, 0xf01cb204, 0xa994ffa4, 0x02a4b605, 0xb8a0a9bc, 0x0010eeaa, 0x008b707e, 0x281fa433, 0x0b10ec4a, 0x7e3cb201, 0x33008b70, 0x3f191fa4, 0x01f6303f, - 0x3f0e0cf4, 0xf49f2609, 0xf03e8a1b, 0x050a009c, 0x900149fe, 0x9fbf1499, 0x0005dcd9, 0xa699bf00, - 0x070bf4f9, 0x003a317e, 0xf40835fb, 0xdcdfd830, 0xf9000005, 0xfeffbf22, 0x99900149, 0xa0a13230, + 0x3f0e0cf4, 0xf49f2609, 0xf03e8a1b, 0x050a009c, 0x900149fe, 0x9fbf1499, 0x0005ecd9, 0xa699bf00, + 0x070bf4f9, 0x003a317e, 0xf40835fb, 0xecdfd830, 0xf9000005, 0xfeffbf22, 0x99900149, 0xa0a13230, 0x299cd99f, 0x99980000, 0x0ab2b204, 0x0094f108, 0x360bf440, 0xbd0140fe, 0x0c0090b4, 0x4d7e0ab2, 0xa433009c, 0x0ab2251f, 0x010c1b32, 0x009c127e, 0x171fa433, 0x90ff19c4, 0x99bc0299, 0x9009bc90, - 0x92f0997f, 0xfe29a00f, 0x99900149, 0xd99fbf30, 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, - 0x30f42825, 0x05dcdfd8, 0x62f90000, 0x49feffbf, 0x40999001, 0x9fa0b2b2, 0x00299cd9, 0x04999800, + 0x92f0997f, 0xfe29a00f, 0x99900149, 0xd99fbf30, 0x000005ec, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, + 0x30f42825, 0x05ecdfd8, 0x62f90000, 0x49feffbf, 0x40999001, 0x9fa0b2b2, 0x00299cd9, 0x04999800, 0xc3b2a6b2, 0x94f1080b, 0x0bf51000, 0xb4bd00e5, 0x900141fe, 0x1ab21c11, 0x009c4d7e, 0xad33ab32, 0x0b00d11f, 0x0c1ab2ff, 0x9c127e01, 0x33ab3200, 0x00c01fad, 0x1ab2ff0b, 0x127ec43d, 0xab32009c, 0xaf1fad33, 0x01145800, 0x29a094bd, 0x109039a0, 0x72157f04, 0x4da47d4c, 0xe4bd8000, 0x323e0101, @@ -1301,8 +1301,8 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x9e273e05, 0x90df7200, 0xc57601ee, 0x02009001, 0xc473fd72, 0x6ebfd000, 0xc400d3f0, 0xffdfffa9, 0xb6ff00ff, 0xeffd1094, 0x00008c04, 0x059efdff, 0xfd049cfd, 0x69a0059d, 0x4ee429bf, 0xafc7ffff, 0x10ed94e8, 0xff0094f1, 0xfd059dfd, 0x2fa005f9, 0xffff59e4, 0xff00eeb9, 0x0bf4a4e9, 0xfd39bf15, - 0x9afd049c, 0xbf39a005, 0x0095f129, 0xfe29a001, 0x99900149, 0xd99fbf40, 0x000005dc, 0xba3299bf, - 0x0bf4f9a6, 0x3a317e07, 0x2865fb00, 0xdff030f4, 0x000005dc, 0xffbf62f9, 0x900149fe, 0xa1322899, + 0x9afd049c, 0xbf39a005, 0x0095f129, 0xfe29a001, 0x99900149, 0xd99fbf40, 0x000005ec, 0xba3299bf, + 0x0bf4f9a6, 0x3a317e07, 0x2865fb00, 0xdff030f4, 0x000005ec, 0xffbf62f9, 0x900149fe, 0xa1322899, 0xb0329fa0, 0xd5b2c432, 0xb630e6b2, 0x120cf504, 0x299cd901, 0x9e980000, 0xffb9c404, 0xc4119990, 0x080a1f9f, 0xb905efbb, 0x94f00099, 0x909fbc1f, 0xf9bbff0f, 0x34feff05, 0xe9013db3, 0xfe94bd00, 0xff90014f, 0x0142fe20, 0x9001f9b5, 0xf9a01c22, 0x2bb2a4bd, 0x009c4d7e, 0xc91fad33, 0x322ab200, @@ -1312,27 +1312,27 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x009fa53e, 0xf1ff19c4, 0x0f012690, 0x5a9eb802, 0xa53e0011, 0x19c4009f, 0x2690f1ff, 0x01004f01, 0x115c9eb8, 0x03499400, 0x9cc4040a, 0xf4cfa6f8, 0xc9903218, 0xa6080b08, 0x060df49f, 0xbcb2fcbc, 0x40fea0ec, 0x20009001, 0x707e0cb2, 0xa433008b, 0x09bf131f, 0x009859a0, 0x3e60a001, 0x0a009fe1, - 0x0149fe03, 0xbf289990, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, 0x3a317e07, 0x1065fb00, 0xdfe830f4, - 0x000005dc, 0xffbf52f9, 0x900149fe, 0xa3b22c99, 0x9cd99fa0, 0x98000029, 0xb2b20499, 0x94f1080a, + 0x0149fe03, 0xbf289990, 0x05ecd99f, 0x99bf0000, 0x0bf4f9a6, 0x3a317e07, 0x1065fb00, 0xdfe830f4, + 0x000005ec, 0xffbf52f9, 0x900149fe, 0xa3b22c99, 0x9cd99fa0, 0x98000029, 0xb2b20499, 0x94f1080a, 0x0bf52000, 0x40fe00ca, 0x90a4bd01, 0x0bb21800, 0x009c4d7e, 0xb81fad33, 0x0b0ab200, 0x7ec43dff, 0x33009c12, 0x00a91fad, 0x7f0141fe, 0x1c119000, 0x0b10dc4a, 0x7e1cb210, 0x33008b70, 0x00911fad, 0x15b20b72, 0x04bdc4bd, 0xff04e001, 0x00a0e83e, 0xf401b9c4, 0xc6b0690b, 0x350cf407, 0x5c3c3dbf, 0x1f0ec4f8, 0xb9030990, 0xf4f00099, 0x1f94f0ff, 0xbc909ebc, 0x9fff9549, 0x049ebbf4, 0xb904febb, 0x9dfd0099, 0x059ffd04, 0xdc3e39a0, 0x2dbf00a0, 0xc4f85c3c, 0x09921f1e, 0x0099b91d, 0xf0fff4f0, 0x9ebc1f94, 0x9549bc90, 0xbbf49fff, 0xfebb049e, 0x0099b904, 0xfd049dfd, 0x29a0059f, 0x7601cc90, - 0x009001b5, 0x04119004, 0x8800b473, 0x900149fe, 0x9fbf2c99, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, - 0x003a317e, 0xf41855fb, 0xdcdfd430, 0xf9000005, 0xfeffbf22, 0x99900149, 0xfea23234, 0x9fa00141, + 0x009001b5, 0x04119004, 0x8800b473, 0x900149fe, 0x9fbf2c99, 0x0005ecd9, 0xa699bf00, 0x070bf4f9, + 0x003a317e, 0xf41855fb, 0xecdfd430, 0xf9000005, 0xfeffbf22, 0x99900149, 0xfea23234, 0x9fa00141, 0x4a0c1190, 0x280b2398, 0x707e1cb2, 0xa433008b, 0x10985d1f, 0xbc19bf01, 0x90a6f290, 0xb01008f4, 0x9cf001f6, 0x0196f00b, 0x00a1563e, 0xf9a6e109, 0xf00b9cf0, 0x0b0a0196, 0x33009033, 0x0029b4d9, 0x019c9800, 0x4ffe9bbf, 0x0cff9001, 0x4d90f0bc, 0x9235239c, 0x90240e08, 0x94f00109, 0x04fa901f, - 0x7e01f9b5, 0x7e002136, 0xfe008a84, 0x99900149, 0xd99fbf34, 0x000005dc, 0xf9a699bf, 0x7e070bf4, - 0xfb003a31, 0x30f42c25, 0x05dcdff8, 0x12f90000, 0x49feffbf, 0x0c999001, 0x9fa0a132, 0x00299cd9, + 0x7e01f9b5, 0x7e002136, 0xfe008a84, 0x99900149, 0xd99fbf34, 0x000005ec, 0xf9a699bf, 0x7e070bf4, + 0xfb003a31, 0x30f42c25, 0x05ecdff8, 0x12f90000, 0x49feffbf, 0x0c999001, 0x9fa0a132, 0x00299cd9, 0x049f9800, 0x0089080a, 0xf9fd0100, 0x2a0bf404, 0xbd0140fe, 0x080090a4, 0x4d7e0bb2, 0xa433009c, 0x0ab2191f, 0xc43d1b32, 0x009c127e, 0x0b1fa433, 0x7e1f1ac4, 0xfe00a107, 0x99900149, 0xd99fbf0c, - 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, 0x30f40815, 0x05dcdff8, 0x12f90000, 0x49feffbf, + 0x000005ec, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, 0x30f40815, 0x05ecdff8, 0x12f90000, 0x49feffbf, 0x0c999001, 0x9fa0a132, 0x00299cd9, 0x04999800, 0x94f1080a, 0x90738000, 0x40fe2e00, 0x90a4bd01, 0x0bb20800, 0x009c4d7e, 0x1c1fa433, 0x1b320ab2, 0x127ec43d, 0xa433009c, 0x1ac40e1f, 0x20a5f01f, - 0x00a1077e, 0x900149fe, 0x9fbf0c99, 0x0005dcd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xf90815fb, + 0x00a1077e, 0x900149fe, 0x9fbf0c99, 0x0005ecd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xf90815fb, 0x06b99552, 0x94b6c4b2, 0xbcd5b203, 0xb0c430a9, 0xa2e03e3f, 0x9831bf00, 0x54b30132, 0x010a1800, 0x0cb2b4bd, 0x0039cd7e, 0xfd052bfd, 0xc83e051a, 0x0cb200a2, 0xb4bd010a, 0x0039cd7e, 0xb900b9b9, 0x29fd00aa, 0x041afd04, 0xb3014492, 0x900b0040, 0x04b30100, 0x31a0c840, 0xbd0132b5, 0x08339004, @@ -1347,14 +1347,14 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x00409631, 0x31251df4, 0xf4005a96, 0xd0331e1c, 0xefc41b00, 0x04f9c4ff, 0xc4151bf4, 0x94b30af9, 0xa9180b02, 0x00903307, 0xf8060a08, 0xf8a4bd00, 0x0f12f900, 0xb2b1b202, 0x00a0b3a0, 0xf0a93f22, 0x1bf40894, 0xa3107e17, 0x0010b300, 0x181a2006, 0x060f0809, 0x1bf4a926, 0xb2f4bd05, 0xb211fbfa, - 0xb3020aa9, 0xbf1200c0, 0xb6cdb29a, 0x804c07b4, 0xb7627e00, 0xf400f800, 0xdcdff830, 0xf9000005, + 0xb3020aa9, 0xbf1200c0, 0xb6cdb29a, 0x804c07b4, 0xb7627e00, 0xf400f800, 0xecdff830, 0xf9000005, 0xfeffbf22, 0x99900149, 0xa0a0b210, 0xb3020a9f, 0xbf340000, 0x94943d0a, 0x41fe07b2, 0x902bb201, 0x010c0f11, 0x1db21920, 0x00b7797e, 0x1700a4b3, 0x0abf193f, 0x1db22bb2, 0x0cfd94f0, 0x7e192001, - 0xfe00b762, 0x99900149, 0xd99fbf10, 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, 0x30f40825, - 0x05dcdff8, 0x42f90000, 0x49feffbf, 0x18999001, 0x9fa0a1b2, 0xc0b2b4b2, 0xa0b3d3b2, 0xc0b35600, + 0xfe00b762, 0x99900149, 0xd99fbf10, 0x000005ec, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, 0x30f40825, + 0x05ecdff8, 0x42f90000, 0x49feffbf, 0x18999001, 0x9fa0a1b2, 0xc0b2b4b2, 0xa0b3d3b2, 0xc0b35600, 0xcf185200, 0xfe94bd07, 0x22900142, 0x01ff1014, 0xcf3529a0, 0x7ecab207, 0xb200a310, 0x080a352b, 0xb27e1ab2, 0xa4b300a7, 0x2bbf2c00, 0x1ab20cb2, 0x00a43f7e, 0x1e00a4b3, 0x4bb21ab2, 0x00a4577e, - 0x1200a4b3, 0x0e0030b3, 0x32a022bf, 0x00a5323e, 0x49fe020a, 0x18999001, 0xdcd99fbf, 0xbf000005, + 0x1200a4b3, 0x0e0030b3, 0x32a022bf, 0x00a5323e, 0x49fe020a, 0x18999001, 0xecd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x45fb003a, 0xb202f908, 0x00a0b3c0, 0x00c0b324, 0xb6aabf20, 0x804c07b4, 0x7e0db200, 0xb300b779, 0xb21000a4, 0xa3307e0a, 0xa5773e00, 0xfb020a00, 0x00a0b301, 0x00c0b317, 0xb2aabf13, 0x07b4b6cd, 0x797e100c, 0x00f800b7, 0x00f8020a, 0xb3b242f9, 0xa2b2c4b2, 0xa0b30200, @@ -1368,30 +1368,30 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x909dbc90, 0xb80394b6, 0x00014099, 0x269009bc, 0x0b1bf4ef, 0xa4bd29a0, 0x00a6a83e, 0x9001dd90, 0xd4b318cc, 0x040ab314, 0xabbf21fb, 0xf009acb2, 0x0bf4b9a6, 0x03aa980d, 0x7e01cbb5, 0xf800b65f, 0xb232f900, 0xbdb2b2a1, 0x3ef00304, 0xbf00a6f0, 0x01009019, 0x93a61ab2, 0x0a090df4, 0xa6f73e03, - 0xf493a600, 0x020a091b, 0x00a6f73e, 0x00a6aa7e, 0x08f402a6, 0xfba4bddd, 0xf830f431, 0x0005dcdf, + 0xf493a600, 0x020a091b, 0x00a6f73e, 0x00a6aa7e, 0x08f402a6, 0xfba4bddd, 0xf830f431, 0x0005ecdf, 0xbf82f900, 0x0149feff, 0xb2289990, 0xb29fa0a3, 0x00a9b3b8, 0xb0b30084, 0x47fe7f00, 0x05a49801, - 0x54bd24bd, 0x779014bd, 0xa7613e24, 0x0c3a9800, 0x02bc94bd, 0xb279a0b0, 0xb65f7e7c, 0x0f79bf00, + 0x14bd54bd, 0x779024bd, 0xa7613e24, 0x0c3a9800, 0x02bc94bd, 0xb279a0b0, 0xb65f7e7c, 0x0f79bf00, 0xf49fa6ff, 0x643d090b, 0x00a74f3e, 0x90015590, 0x04a60100, 0x33d908f4, 0x90070060, 0x24bc0111, 0x03399820, 0x18f429a6, 0xbd01060b, 0xa7523e04, 0xb24bb200, 0x16fc7e1a, 0xf45aa600, 0x1190060d, 0x06399801, 0x19a6f43d, 0x0f050cf4, 0xbd8f2001, 0xa7973ea4, 0xfe020a00, 0x99900149, 0xd99fbf28, - 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, 0x30f40885, 0x05dcdff0, 0x82f90000, 0x49feffbf, + 0x000005ec, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, 0x30f40885, 0x05ecdff0, 0x82f90000, 0x49feffbf, 0x30999001, 0xa00147fe, 0x08a9989f, 0xb1b0a6b2, 0xb0f10509, 0x843d0a91, 0x779090b2, 0x0369982c, 0x7fa0f4bd, 0x08f409a6, 0x0804bd07, 0x0a90b401, 0x1bf409a6, 0x00803335, 0xa85a3e32, 0x0c6a9800, 0xb24010bc, 0x7e4bb27c, 0xbf00b65f, 0xa6ff0f79, 0x0f1bf49f, 0x09012290, 0xf439a6f1, 0x43b2051b, 0x3e011190, 0xbd00a82d, 0xbdf10314, 0x05699824, 0x08f419a6, 0x0020b3cb, 0xf429a61e, 0x60b50f18, 0x09f0b408, 0x6b3ef3a0, 0xf10f00a8, 0x1bf45fa6, 0xbc05b205, 0xdd3e0009, 0x1a0a00a7, 0x59a6f109, - 0xb50d0bf4, 0x90b40865, 0xbd95a009, 0x0149fea4, 0xbf309990, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6, - 0x3a317e07, 0x1085fb00, 0xd9f830f4, 0x000005dc, 0x99bf82f9, 0x90014ffe, 0xa3b228ff, 0xb4b2f9a0, + 0xb50d0bf4, 0x90b40865, 0xbd95a009, 0x0149fea4, 0xbf309990, 0x05ecd99f, 0x99bf0000, 0x0bf4f9a6, + 0x3a317e07, 0x1085fb00, 0xd9f830f4, 0x000005ec, 0x99bf82f9, 0x90014ffe, 0xa3b228ff, 0xb4b2f9a0, 0xc033d0b2, 0xdab20e00, 0x140cb43d, 0x00b7907e, 0xbd0142fe, 0x24229014, 0xff07fe08, 0xfb05fc06, 0x00a93a3e, 0xbd0c3a98, 0xb014bc94, 0x2cb229a0, 0x00b65f7e, 0xf00f29bf, 0x0df49fa6, 0xa6fd0f56, 0x110cf49f, 0x18f496a6, 0xf495a630, 0x093e451b, 0x98a600a9, 0xa62f0bf4, 0x371bf497, 0x90010998, 0x09b50199, 0xa9373e01, 0x04099800, 0xb5019990, 0x373e0409, 0x099800a9, 0x01999002, 0x3e0209b5, 0x9800a937, 0x99900309, 0x0309b501, 0x00a9373e, 0x999009bf, 0x9009a001, 0x39980111, 0xf419a605, - 0x49fe8508, 0x28999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x85fb003a, 0xf830f408, - 0x0005dcdf, 0xb222f900, 0xb2ffbfa1, 0x03aa98b2, 0x49fe1bbf, 0x10999001, 0xa00140fe, 0x0c00909f, + 0x49fe8508, 0x28999001, 0xecd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x85fb003a, 0xf830f408, + 0x0005ecdf, 0xb222f900, 0xb2ffbfa1, 0x03aa98b2, 0x49fe1bbf, 0x10999001, 0xa00140fe, 0x0c00909f, 0x5f7e0cb2, 0x0cbf00b6, 0xb2031a98, 0xb6767e2b, 0x011b9800, 0xb9a6ff09, 0x98101bf4, 0x12b50419, 0x0292b502, 0x00a9b13e, 0xb2031a98, 0xb6767e2c, 0x031a9800, 0xfd0c1bbf, 0x00b6767e, 0x900149fe, - 0x12a01099, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x25fb003a, 0xc830f408, 0x0005dcdf, + 0x12a01099, 0xecd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x25fb003a, 0xc830f408, 0x0005ecdf, 0xbf82f900, 0xf830f4ff, 0x900149fe, 0x9fa06099, 0x18049992, 0xf4bd1cae, 0xa9989fa0, 0x0aa2b205, 0x0b91b005, 0x1a00e933, 0x0c2b9802, 0xfe092c98, 0xf100014a, 0xfe44aa90, 0xa6b20144, 0x8b7e2001, 0x05b200b6, 0x4490a3b2, 0xaa723e30, 0x08299800, 0x0bf439a6, 0xb22ab231, 0xb2010c3b, 0xa8887e4d, @@ -1410,8 +1410,8 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x0111b05c, 0x00a5e47e, 0xbf042c98, 0x048bb22a, 0xb74b7efb, 0x981ebf00, 0xa0b2042c, 0x2ab2b4bd, 0xe67e0db2, 0x04b300a5, 0xff040600, 0x013e04bd, 0x2a9800ac, 0xb003bc0c, 0x00904cb2, 0xb6767e01, 0x0b90b400, 0x08f409a6, 0x032f98ec, 0xb59039bc, 0x9fa60929, 0xbd0808f4, 0x0929b594, 0x49fea4bd, - 0x60999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x30f4003a, 0x3885fb08, 0xd9cc30f4, - 0x000005dc, 0x99bf82f9, 0xfef830f4, 0xff90014f, 0xb0f9a05c, 0xc8b20be1, 0xa3b2d6b2, 0x8400b9b3, + 0x60999001, 0xecd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x30f4003a, 0x3885fb08, 0xd9cc30f4, + 0x000005ec, 0x99bf82f9, 0xfef830f4, 0xff90014f, 0xb0f9a05c, 0xc8b20be1, 0xa3b2d6b2, 0x8400b9b3, 0x00e9b302, 0xaf18027f, 0x0141fe2c, 0x119094bd, 0x0019a054, 0x00f93303, 0xc43d026d, 0x407e1db2, 0xa0b200a6, 0x5e00adb3, 0xbc17bf02, 0x7998f068, 0xf59fa601, 0x98024d08, 0x94b30479, 0x05000a01, 0x00aee23e, 0x3e0069b3, 0x027f9802, 0xf9a6f009, 0x022a0bf5, 0xea7e3ab2, 0xa2b200a5, 0x1e00a9b3, @@ -1420,7 +1420,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x070b943a, 0xb200804c, 0xb7797e2d, 0x0ca1b000, 0xb600adb3, 0x05291801, 0x76042f18, 0xf4f00894, 0xe59fffff, 0xe966ff09, 0x01980bf5, 0xffffe9e4, 0x08f589a6, 0xf4bd018e, 0x18902fbc, 0x9d330999, 0x90018200, 0xf4b301ff, 0xfc3ef207, 0x8e3c00ae, 0xf59f26f2, 0xc4016d08, 0x94f0fffd, 0x529dbcff, - 0x0df456a6, 0x9065b205, 0xe4bd10d9, 0x3db029bc, 0x3ec43da4, 0xb100ada7, 0xf5006fd6, 0xb401450c, + 0x0df456a6, 0x9065b205, 0xa43d10d9, 0x3db029bc, 0x3ee4bdc4, 0xb100ada7, 0xf5006fd6, 0xb401450c, 0xbe3c0b10, 0xf81e3c98, 0x0bf4f926, 0xff94f017, 0xfd009939, 0x9033049f, 0x010a0600, 0x0ce9bf3c, 0x01ee9001, 0xa601dd90, 0xce08f4e5, 0xed00c933, 0xf0293f00, 0x0bf40894, 0x00a93308, 0x94bd00d0, 0x91b03ab2, 0x1391b014, 0x301291b0, 0x4bfe5b91, 0x5bbb9001, 0x00a6f97e, 0xadb3a0b2, 0x3400ef00, @@ -1432,8 +1432,8 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x49b5029f, 0xae993e01, 0xb20bb200, 0x7e2cb23a, 0xb200a43f, 0x00a4b3a0, 0x0265bb34, 0x90014afe, 0xaa7e34aa, 0x60b300a6, 0x90b42000, 0x8085bc0b, 0xb09095bc, 0xe53e0b91, 0x020000ac, 0x00aec93e, 0xc93e0300, 0x00b400ae, 0xb23ab20c, 0xa60c7e2b, 0xb594bd00, 0xe23e0579, 0x030000ae, 0x00aee23e, - 0x49fe0200, 0x5c999001, 0xdcd99fbf, 0xbf000005, 0xa60ab299, 0x170bf4f9, 0x00af083e, 0x33062918, - 0xfe4f009d, 0x00aec03e, 0x003a317e, 0xfb0830f4, 0x30f43485, 0x05dcdfdc, 0x82f90000, 0x30f4ffbf, + 0x49fe0200, 0x5c999001, 0xecd99fbf, 0xbf000005, 0xa60ab299, 0x170bf4f9, 0x00af083e, 0x33062918, + 0xfe4f009d, 0x00aec03e, 0x003a317e, 0xfb0830f4, 0x30f43485, 0x05ecdfdc, 0x82f90000, 0x30f4ffbf, 0x0149fef8, 0xa04c9990, 0x0bb1b09f, 0xd4b2c2b2, 0xa5b2e6b2, 0x1700b9b3, 0x00e9b301, 0x94bd0112, 0x3d0141fe, 0x481190c4, 0x1db219a0, 0x00a6407e, 0xadb3a0b2, 0xbf00fb00, 0xf042bc19, 0xa6019998, 0xea08f59f, 0x005ab200, 0xa5ea7e03, 0xb3a3b200, 0x00de00a9, 0x5c981bbf, 0x0140fe0c, 0xb2300090, @@ -1443,13 +1443,13 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x2cb20bb2, 0x797e3db2, 0x7ebf00b7, 0x3bb2a0b2, 0x2cb25ab2, 0xe67e0db2, 0x04b300a5, 0x3ab24500, 0x117eb4bd, 0xa0b200a4, 0x3700a4b3, 0x01bb7000, 0xf404a602, 0x40b2050d, 0xb2101b90, 0xb03bbc6a, 0x997e0cb2, 0x4afe00b7, 0x0240bb01, 0xbc30aa90, 0xaa7e6060, 0x14bd00a6, 0x6d004db3, 0xb280b2ff, - 0x7e3bb25a, 0x3e00a60c, 0x0000b04d, 0x0149fe02, 0xbf4c9990, 0x05dcd99f, 0x99bf0000, 0xf9a60ab2, - 0x7e070bf4, 0xf4003a31, 0x85fb0830, 0xf830f424, 0x0005dcd9, 0xbf32f900, 0x014ffe99, 0xb214ff90, + 0x7e3bb25a, 0x3e00a60c, 0x0000b04d, 0x0149fe02, 0xbf4c9990, 0x05ecd99f, 0x99bf0000, 0xf9a60ab2, + 0x7e070bf4, 0xf4003a31, 0x85fb0830, 0xf830f424, 0x0005ecd9, 0xbf32f900, 0x014ffe99, 0xb214ff90, 0xbdf9a0a1, 0xb2b2b294, 0x0140fec3, 0x9003204b, 0x09a01000, 0x9f7e0ab2, 0x09bf00b7, 0x4c0090b3, 0x4800a4b3, 0x09bf91a0, 0xbf0192b5, 0x1000490f, 0xbf04f9b5, 0xb520090f, 0x09bf05f9, 0xbf0693b5, 0x3501090f, 0x09bf1cf9, 0xbf2c9a35, 0xb5f0090f, 0x0fbf0af9, 0xb540f990, 0x0fbf0ef9, 0xb5c0f990, - 0x0abf0ff9, 0x00b0ea3e, 0x49fea4bd, 0x14999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, - 0x35fb003a, 0xd030f408, 0x0005dcdf, 0xbf82f900, 0x0149feff, 0xb2509990, 0x059fa0a3, 0x00a9b302, + 0x0abf0ff9, 0x00b0ea3e, 0x49fea4bd, 0x14999001, 0xecd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, + 0x35fb003a, 0xd030f408, 0x0005ecdf, 0xbf82f900, 0x0149feff, 0xb2509990, 0x059fa0a3, 0x00a9b302, 0xb63004fb, 0x0b9cf000, 0xbd2ca935, 0x0ca9b594, 0x00a5ea7e, 0x3abfa0b2, 0x804cb4bd, 0x7e0db200, 0xb200b779, 0x00adb3a5, 0x093f04b1, 0xa24a9d33, 0x01091804, 0x9a469d33, 0x02091804, 0x92469d33, 0x03091804, 0x8a539d33, 0x040e1804, 0x18050918, 0x0d18060f, 0xffe4f007, 0xf0ff94f0, 0x94b6fff4, @@ -1490,20 +1490,20 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0xf0f9bcff, 0x3e517fb5, 0x0a00b5d3, 0x3ea5b203, 0x9000b5de, 0x77900188, 0x148db318, 0x49fefd90, 0x3c999001, 0x497e9abf, 0xf43e00b7, 0x030500b5, 0x00b5f63e, 0x0bb204bd, 0x0c7e3ab2, 0x50b300a6, 0x3a981a00, 0x7e04bd0c, 0x9800b6c8, 0x30b50d3a, 0xb7497e0c, 0x0d30b500, 0x900149fe, 0x9fbf5099, - 0x0005dcd9, 0xb299bf00, 0xf4f9a65a, 0x383e110b, 0x010500b6, 0x00b5f43e, 0x003a317e, 0xf93085fb, + 0x0005ecd9, 0xb299bf00, 0xf4f9a65a, 0x383e110b, 0x010500b6, 0x00b5f43e, 0x003a317e, 0xf93085fb, 0x7ea0b202, 0x9800a5e8, 0xc87e0c0a, 0x0a9800b6, 0xb7497e0d, 0x7e0ab200, 0xbd00b749, 0xbf01fba4, 0x0aafb2a9, 0xf4b9a602, 0xb9900d18, 0x98f9bc01, 0xc9a0a4bd, 0xa9bf00f8, 0x020aafb2, 0x18f4b9a6, 0x01b9900b, 0xfcbca4bd, 0xbf00f899, 0xb2afb2b9, 0xf4c9a6ca, 0xf10a0708, 0xfbb500f8, 0xb5fca002, 0x00f801fc, 0xaf98a9bf, 0x90b9bc02, 0xfbbfa9a0, 0x08f49ba6, 0x029bbb08, 0xa998a9a0, 0xa6aabf01, - 0x051bf4a9, 0x00f8f10a, 0x0800a0b3, 0x00b7497e, 0x30f400f8, 0x05dcdff8, 0x32f90000, 0x49feffbf, + 0x051bf4a9, 0x00f8f10a, 0x0800a0b3, 0x00b7497e, 0x30f400f8, 0x05ecdff8, 0x32f90000, 0x49feffbf, 0x14999001, 0x9fa0a0b2, 0xa0b3b3b2, 0xfd024200, 0x0cf4a2a6, 0x01ab903a, 0xb60141fe, 0x119002b4, 0x7e1ab210, 0xb300b7b5, 0xbf2700a4, 0xb21db219, 0xa0e4bd2c, 0x90dfbf90, 0x9eb201e9, 0xa699fcbc, - 0xf408f490, 0x3da0ddbf, 0x00b72e3e, 0x49fe020a, 0x14999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, + 0xf408f490, 0x3da0ddbf, 0x00b72e3e, 0x49fe020a, 0x14999001, 0xecd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x35fb003a, 0xda00f808, 0x00002944, 0x0041c77e, 0xf000a630, 0xa6f00bac, 0x01aab901, 0x44da00f8, 0x7e000029, 0x30004142, 0xacf000a6, 0x01a6f00b, 0xf801aab9, 0x2944da00, 0xd77e0000, 0xa6300042, 0x0bacf000, 0xb901a6f0, 0x00f801aa, 0x7effb4f0, 0xf8000b94, 0x0b7e7e00, 0xf900f800, 0x3da0b202, 0x384c7ea4, 0x00a6b000, 0xa00b9cf0, 0xfb9ab20a, 0xb202f901, 0x7ea43da0, 0xb000382a, - 0x9cf000a6, 0xb20aa00b, 0xf401fb9a, 0xdcdfe430, 0xf9000005, 0xfeffbf82, 0x45fe0149, 0x3c999001, + 0x9cf000a6, 0xb20aa00b, 0xf401fb9a, 0xecdfe430, 0xf9000005, 0xfeffbf82, 0x45fe0149, 0x3c999001, 0xa00147fe, 0x2455909f, 0xd9347790, 0x0000141c, 0x4bfe9abf, 0x90080c01, 0xff0d2cbb, 0x0000c17e, 0xeb00a433, 0x3f0c30b4, 0x0c943339, 0x043118e2, 0x0f001033, 0xb0011933, 0x3e043d00, 0x9800b971, 0x2cd9023f, 0x98000014, 0x34580431, 0x3f5fa00a, 0x0339989f, 0xb5183690, 0xff090159, 0xf43379a0, @@ -1570,11 +1570,11 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x00000000, 0x00000001, 0x0000000e, 0x00000000, 0x08000000, 0x08400000, 0x08800000, 0x08c300a7, 0x09000000, 0x09400000, 0x09800000, 0x09c00000, 0x0a01c000, 0x0a404038, 0x0a804040, 0x0ac04048, 0x0b004050, 0x0b420058, 0x0b8201ab, 0x11800000, 0x11c00000, 0x12000000, 0x12400000, 0x12800000, - 0x12c00000, 0x00000000, 0x00000000, 0x00000001, 0x00001c08, 0x00101c09, 0x00201c0a, 0x0000bd08, - 0x00209d09, 0x00309d0a, 0x00011f08, 0x00113e09, 0x00311e0a, 0x00010309, 0x00000000, 0x0000ffff, - 0x00003b00, 0x46020f1f, 0x43010f1f, 0x44020f1f, 0x45020f1f, 0x601207ef, 0x601307ef, 0x601407ef, - 0x601507ef, 0x801607ef, 0x253207c2, 0x25330fc2, 0x25340fc2, 0x25350fc2, 0x1152079d, 0x1253079d, - 0x7014079d, 0x7015079d, 0x601203c8, 0x601307c8, 0x601407c8, 0xbb150720, 0x02172701, 0x00000000, + 0x12c00000, 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00001c08, 0x00101c09, 0x00201c0a, + 0x0000bd08, 0x00209d09, 0x00309d0a, 0x00011f08, 0x00113e09, 0x00311e0a, 0x00010309, 0x00000000, + 0x0000ffff, 0x00003b00, 0x46020f1f, 0x43010f1f, 0x44020f1f, 0x45020f1f, 0x601207ef, 0x601307ef, + 0x601407ef, 0x601507ef, 0x801607ef, 0x253207c2, 0x25330fc2, 0x25340fc2, 0x25350fc2, 0x1152079d, + 0x1253079d, 0x7014079d, 0x7015079d, 0x601203c8, 0x601307c8, 0x601407c8, 0xbb150720, 0x02172701, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -2269,8 +2269,8 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0xf0cc97fc, 0xc5e27e17, 0x63cc4ffc, 0xc48564fa, 0x176bd707, 0x7693db62, 0xcee1dbf7, 0x0ec5a1fa, - 0x956b7a40, 0x90bcaaf7, 0xdea25edb, 0x9aaef423, 0x930f31b1, 0x6ce8df20, 0xa1e5e4d9, 0xc55f48a9, + 0x69e9060c, 0xe6ca2d91, 0xac20edf2, 0xeafeafcc, 0xfb3a453a, 0x7158de23, 0xaef7305e, 0xd220040f, + 0x30867660, 0xbc4af25f, 0xbc09e1ed, 0xab87e0fc, 0x8db5cb00, 0x30cfe9a4, 0xc1a3eea2, 0x79a1340e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, diff --git a/src/common/nvswitch/kernel/inforom/ifrbbx_nvswitch.c b/src/common/nvswitch/kernel/inforom/ifrbbx_nvswitch.c index a92d9ee140..bdd3e39b94 100644 --- a/src/common/nvswitch/kernel/inforom/ifrbbx_nvswitch.c +++ b/src/common/nvswitch/kernel/inforom/ifrbbx_nvswitch.c @@ -130,3 +130,21 @@ nvswitch_inforom_bbx_get_sxid return status; } +NvlStatus +nvswitch_inforom_bbx_get_data +( + nvswitch_device *device, + NvU8 dataType, + void *params +) +{ + NvlStatus status; + + status = device->hal.nvswitch_bbx_get_data(device, dataType, params); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s: (type=%d) failed, status=%d\n", __FUNCTION__, dataType, status); + } + + return status; +} diff --git a/src/common/nvswitch/kernel/lr10/inforom_lr10.c b/src/common/nvswitch/kernel/lr10/inforom_lr10.c index c7d3c0e29b..3e52429bae 100644 --- a/src/common/nvswitch/kernel/lr10/inforom_lr10.c +++ b/src/common/nvswitch/kernel/lr10/inforom_lr10.c @@ -32,6 +32,7 @@ #include "nvVer.h" #include "regkey_nvswitch.h" #include "inforom/inforom_nvl_v3_nvswitch.h" +#include "soe/soeififr.h" // // TODO: Split individual object hals to their own respective files @@ -1280,3 +1281,14 @@ nvswitch_bbx_get_sxid_lr10 return -NVL_ERR_NOT_SUPPORTED; } +NvlStatus +nvswitch_bbx_get_data_lr10 +( + nvswitch_device *device, + NvU8 dataType, + void *params +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + diff --git a/src/common/nvswitch/kernel/lr10/link_lr10.c b/src/common/nvswitch/kernel/lr10/link_lr10.c index f0fa90ca77..552d88579f 100644 --- a/src/common/nvswitch/kernel/lr10/link_lr10.c +++ b/src/common/nvswitch/kernel/lr10/link_lr10.c @@ -566,6 +566,11 @@ nvswitch_init_lpwr_regs_lr10 NvU8 softwareDesired, hardwareDisable; NvBool bLpEnable; + if (IS_RTLSIM(device) || IS_EMULATION(device) || IS_FMODEL(device)) + { + return; + } + if (device->regkeys.enable_pm == NV_SWITCH_REGKEY_ENABLE_PM_NO) { return; @@ -681,15 +686,6 @@ nvswitch_init_lpwr_regs_lr10 tempRegVal); } -void -nvswitch_program_l1_scratch_reg_lr10 -( - nvswitch_device *device, - NvU32 linkNumber -) -{ - // Not Implemented for LR10 -} void nvswitch_init_buffer_ready_lr10 @@ -1020,6 +1016,7 @@ nvswitch_corelib_set_dl_link_mode_lr10 NVSWITCH_PRINT(device, ERROR, "%s: Failed to notify PORT_DOWN event\n", __FUNCTION__); } + nvswitch_record_port_event(device, &(device->log_PORT_EVENTS), link->linkNumber, NVSWITCH_PORT_EVENT_TYPE_DOWN); break; } @@ -2006,6 +2003,7 @@ nvswitch_corelib_training_complete_lr10 NVSWITCH_PRINT(device, ERROR, "%s: Failed to notify PORT_UP event\n", __FUNCTION__); } + nvswitch_record_port_event(device, &(device->log_PORT_EVENTS), link->linkNumber, NVSWITCH_PORT_EVENT_TYPE_UP); } diff --git a/src/common/nvswitch/kernel/lr10/lr10.c b/src/common/nvswitch/kernel/lr10/lr10.c index 1323ea28d2..f7bffaf1ac 100644 --- a/src/common/nvswitch/kernel/lr10/lr10.c +++ b/src/common/nvswitch/kernel/lr10/lr10.c @@ -837,23 +837,23 @@ nvswitch_read_vbios_link_entries_lr10 link_entries[i].nvLinkparam6 = (NvU8)vbios_link_entry.nvLinkparam6; tblPtr += (sizeof(NVLINK_VBIOS_CONFIG_DATA_LINKENTRY_20)/sizeof(NvU32)); - NVSWITCH_PRINT(device, SETUP, + NVSWITCH_PRINT(device, NOISY, "<<<---- NvLink ID 0x%x ---->>>\n", i); - NVSWITCH_PRINT(device, SETUP, + NVSWITCH_PRINT(device, NOISY, "NVLink Params 0 \t0x%x \tBinary:"BYTE_TO_BINARY_PATTERN"\n", vbios_link_entry.nvLinkparam0, BYTE_TO_BINARY(vbios_link_entry.nvLinkparam0)); - NVSWITCH_PRINT(device, SETUP, + NVSWITCH_PRINT(device, NOISY, "NVLink Params 1 \t0x%x \tBinary:"BYTE_TO_BINARY_PATTERN"\n", vbios_link_entry.nvLinkparam1, BYTE_TO_BINARY(vbios_link_entry.nvLinkparam1)); - NVSWITCH_PRINT(device, SETUP, + NVSWITCH_PRINT(device, NOISY, "NVLink Params 2 \t0x%x \tBinary:"BYTE_TO_BINARY_PATTERN"\n", vbios_link_entry.nvLinkparam2, BYTE_TO_BINARY(vbios_link_entry.nvLinkparam2)); - NVSWITCH_PRINT(device, SETUP, + NVSWITCH_PRINT(device, NOISY, "NVLink Params 3 \t0x%x \tBinary:"BYTE_TO_BINARY_PATTERN"\n", vbios_link_entry.nvLinkparam3, BYTE_TO_BINARY(vbios_link_entry.nvLinkparam3)); - NVSWITCH_PRINT(device, SETUP, + NVSWITCH_PRINT(device, NOISY, "NVLink Params 4 \t0x%x \tBinary:"BYTE_TO_BINARY_PATTERN"\n", vbios_link_entry.nvLinkparam4, BYTE_TO_BINARY(vbios_link_entry.nvLinkparam4)); - NVSWITCH_PRINT(device, SETUP, + NVSWITCH_PRINT(device, NOISY, "NVLink Params 5 \t0x%x \tBinary:"BYTE_TO_BINARY_PATTERN"\n", vbios_link_entry.nvLinkparam5, BYTE_TO_BINARY(vbios_link_entry.nvLinkparam5)); - NVSWITCH_PRINT(device, SETUP, + NVSWITCH_PRINT(device, NOISY, "NVLink Params 6 \t0x%x \tBinary:"BYTE_TO_BINARY_PATTERN"\n", vbios_link_entry.nvLinkparam6, BYTE_TO_BINARY(vbios_link_entry.nvLinkparam6)); - NVSWITCH_PRINT(device, SETUP, + NVSWITCH_PRINT(device, NOISY, "<<<---- NvLink ID 0x%x ---->>>\n\n", i); } *identified_link_entriesCount = i; @@ -914,23 +914,23 @@ _nvswitch_vbios_fetch_nvlink_entries goto vbios_fetch_nvlink_entries_done; } - NVSWITCH_PRINT(device, SETUP, + NVSWITCH_PRINT(device, NOISY, "<<<---- NvLink Header ---->>>\n\n"); - NVSWITCH_PRINT(device, SETUP, + NVSWITCH_PRINT(device, NOISY, "Version \t\t 0x%x\n", header.ver_20.Version); - NVSWITCH_PRINT(device, SETUP, + NVSWITCH_PRINT(device, NOISY, "Header Size \t0x%x\n", header.ver_20.HeaderSize); - NVSWITCH_PRINT(device, SETUP, + NVSWITCH_PRINT(device, NOISY, "Base Entry Size \t0x%x\n", header.ver_20.BaseEntrySize); - NVSWITCH_PRINT(device, SETUP, + NVSWITCH_PRINT(device, NOISY, "Base Entry count \t0x%x\n", header.ver_20.BaseEntryCount); - NVSWITCH_PRINT(device, SETUP, + NVSWITCH_PRINT(device, NOISY, "Link Entry Size \t0x%x\n", header.ver_20.LinkEntrySize); - NVSWITCH_PRINT(device, SETUP, + NVSWITCH_PRINT(device, NOISY, "Link Entry Count \t0x%x\n", header.ver_20.LinkEntryCount); - NVSWITCH_PRINT(device, SETUP, + NVSWITCH_PRINT(device, NOISY, "Reserved \t0x%x\n", header.ver_20.Reserved); - NVSWITCH_PRINT(device, SETUP, + NVSWITCH_PRINT(device, NOISY, "<<<---- NvLink Header ---->>>\n"); if (header.ver_20.Version == NVLINK_CONFIG_DATA_HEADER_VER_20) { @@ -6668,6 +6668,12 @@ nvswitch_is_soe_supported_lr10 nvswitch_device *device ) { + if (device->regkeys.soe_disable == NV_SWITCH_REGKEY_SOE_DISABLE_YES) + { + NVSWITCH_PRINT(device, INFO, "SOE is disabled via regkey.\n"); + return NV_FALSE; + } + return NV_TRUE; } diff --git a/src/common/nvswitch/kernel/ls10/discovery_ls10.c b/src/common/nvswitch/kernel/ls10/discovery_ls10.c index a84bb873be..650396e02e 100644 --- a/src/common/nvswitch/kernel/ls10/discovery_ls10.c +++ b/src/common/nvswitch/kernel/ls10/discovery_ls10.c @@ -32,7 +32,7 @@ #include -#define VERBOSE_MMIO_DISCOVERY 1 +#define VERBOSE_MMIO_DISCOVERY 0 #define MAKE_DISCOVERY_LS10(_engine) \ { \ diff --git a/src/common/nvswitch/kernel/ls10/inforom_ls10.c b/src/common/nvswitch/kernel/ls10/inforom_ls10.c index 588500af2b..363d174b5a 100644 --- a/src/common/nvswitch/kernel/ls10/inforom_ls10.c +++ b/src/common/nvswitch/kernel/ls10/inforom_ls10.c @@ -863,3 +863,174 @@ nvswitch_bbx_get_sxid_ls10 return status; } + +NvlStatus +nvswitch_bbx_get_data_ls10 +( + nvswitch_device *device, + NvU8 dataType, + void *params +) +{ + NvlStatus status; + void *pDmaBuf; + NvU64 dmaHandle; + FLCN *pFlcn; + RM_FLCN_CMD_SOE bbxCmd; + NvU32 cmdSeqDesc; + NVSWITCH_TIMEOUT timeout; + NvU32 transferSize; + + if (!nvswitch_is_inforom_supported_ls10(device)) + { + NVSWITCH_PRINT(device, ERROR, "%s: InfoROM is not supported\n", __FUNCTION__); + return -NVL_ERR_NOT_SUPPORTED; + } + + if (params == NULL) + { + NVSWITCH_PRINT(device, ERROR, "%s: params is NULL\n", __FUNCTION__); + return -NVL_BAD_ARGS; + } + + switch (dataType) + { + case RM_SOE_IFR_BBX_GET_SYS_INFO: + transferSize = sizeof(NVSWITCH_GET_SYS_INFO_PARAMS); + break; + + case RM_SOE_IFR_BBX_GET_TIME_INFO: + transferSize = sizeof(NVSWITCH_GET_TIME_INFO_PARAMS); + break; + + case RM_SOE_IFR_BBX_GET_TEMP_DATA: + transferSize = sizeof(NVSWITCH_GET_TEMP_DATA_PARAMS); + break; + + case RM_SOE_IFR_BBX_GET_TEMP_SAMPLES: + transferSize = sizeof(NVSWITCH_GET_TEMP_SAMPLES_PARAMS); + break; + default: + NVSWITCH_PRINT(device, ERROR, "Unknown dataType %d", dataType); + return -NVL_BAD_ARGS; + break; + } + + status = nvswitch_os_alloc_contig_memory(device->os_handle, &pDmaBuf, transferSize, + (device->dma_addr_width == 32)); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s: Failed to allocate contig memory. rc:%d\n", __FUNCTION__, status); + return status; + } + + status = nvswitch_os_map_dma_region(device->os_handle, pDmaBuf, &dmaHandle, + transferSize, NVSWITCH_DMA_DIR_TO_SYSMEM); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s: Failed to map DMA region. rc:%d\n", __FUNCTION__, status); + goto nvswitch_bbx_get_data_ls10_free_and_exit; + } + + nvswitch_os_memset(pDmaBuf, 0, transferSize); + + pFlcn = device->pSoe->pFlcn; + nvswitch_timeout_create(NVSWITCH_INTERVAL_5MSEC_IN_NS, &timeout); + + nvswitch_os_memset(&bbxCmd, 0, sizeof(bbxCmd)); + bbxCmd.hdr.unitId = RM_SOE_UNIT_IFR; + bbxCmd.hdr.size = sizeof(bbxCmd); + bbxCmd.cmd.ifr.cmdType = RM_SOE_IFR_BBX_DATA_GET; + bbxCmd.cmd.ifr.bbxDataGet.sizeInBytes = transferSize; + bbxCmd.cmd.ifr.bbxDataGet.dataType = dataType; + RM_FLCN_U64_PACK(&bbxCmd.cmd.ifr.bbxDataGet.dmaHandle, &dmaHandle); + + status = flcnQueueCmdPostBlocking(device, pFlcn, + (PRM_FLCN_CMD)&bbxCmd, + NULL, // pMsg + NULL, // pPayload + SOE_RM_CMDQ_LOG_ID, + &cmdSeqDesc, + &timeout); + if (status != NV_OK) + { + NVSWITCH_PRINT(device, ERROR, "%s: BX_GET_DATA type=%d failed. rc:%d\n", + __FUNCTION__, dataType, status); + goto nvswitch_bbx_get_data_ls10_unmap_and_exit; + } + + status = nvswitch_os_sync_dma_region_for_cpu(device->os_handle, dmaHandle, + transferSize, + NVSWITCH_DMA_DIR_TO_SYSMEM); + if (status != NV_OK) + { + NVSWITCH_PRINT(device, ERROR, "%s: Failed to sync DMA region. rc:%d\n", __FUNCTION__, status); + goto nvswitch_bbx_get_data_ls10_unmap_and_exit; + } + + if (dataType == RM_SOE_IFR_BBX_GET_SYS_INFO) + { + NVSWITCH_GET_SYS_INFO_PARAMS bbxSysInfoData = {0}; + + nvswitch_os_memcpy((NvU8 *)&bbxSysInfoData, (NvU8 *)pDmaBuf, sizeof(NVSWITCH_GET_SYS_INFO_PARAMS)); + nvswitch_os_memcpy((NvU8 *)params, (NvU8 *)&bbxSysInfoData, sizeof(NVSWITCH_GET_SYS_INFO_PARAMS)); + } + else if (dataType == RM_SOE_IFR_BBX_GET_TIME_INFO) + { + NVSWITCH_GET_TIME_INFO_PARAMS bbxTimeInfoData = {0}; + + nvswitch_os_memcpy((NvU8 *)&bbxTimeInfoData, (NvU8 *)pDmaBuf, sizeof(NVSWITCH_GET_TIME_INFO_PARAMS)); + nvswitch_os_memcpy((NvU8 *)params, (NvU8 *)&bbxTimeInfoData, sizeof(NVSWITCH_GET_TIME_INFO_PARAMS)); + } + else if (dataType == RM_SOE_IFR_BBX_GET_TEMP_DATA) + { + NVSWITCH_GET_TEMP_DATA_PARAMS *pBbxTempData = NULL; + + pBbxTempData = nvswitch_os_malloc(sizeof(NVSWITCH_GET_TEMP_DATA_PARAMS)); + if (pBbxTempData == NULL) + { + NVSWITCH_PRINT(device, ERROR, "Out of memory: dataType %d", dataType); + status = -NVL_NO_MEM; + goto nvswitch_bbx_get_data_ls10_unmap_and_exit; + } + + nvswitch_os_memset(pBbxTempData, 0, sizeof(NVSWITCH_GET_TEMP_DATA_PARAMS)); + + nvswitch_os_memcpy((NvU8 *)pBbxTempData, (NvU8 *)pDmaBuf, sizeof(NVSWITCH_GET_TEMP_DATA_PARAMS)); + nvswitch_os_memcpy((NvU8 *)params, (NvU8 *)pBbxTempData, sizeof(NVSWITCH_GET_TEMP_DATA_PARAMS)); + + nvswitch_os_free(pBbxTempData); + } + else if (dataType == RM_SOE_IFR_BBX_GET_TEMP_SAMPLES) + { + NVSWITCH_GET_TEMP_SAMPLES_PARAMS *pBbxTempSamples = NULL; + + pBbxTempSamples = nvswitch_os_malloc(sizeof(NVSWITCH_GET_TEMP_SAMPLES_PARAMS)); + if (pBbxTempSamples == NULL) + { + NVSWITCH_PRINT(device, ERROR, "Out of memory: dataType %d", dataType); + status = -NVL_NO_MEM; + goto nvswitch_bbx_get_data_ls10_unmap_and_exit; + } + + nvswitch_os_memset(pBbxTempSamples, 0, sizeof(NVSWITCH_GET_TEMP_SAMPLES_PARAMS)); + + nvswitch_os_memcpy((NvU8 *)pBbxTempSamples, (NvU8 *)pDmaBuf, sizeof(NVSWITCH_GET_TEMP_SAMPLES_PARAMS)); + nvswitch_os_memcpy((NvU8 *)params, (NvU8 *)pBbxTempSamples, sizeof(NVSWITCH_GET_TEMP_SAMPLES_PARAMS)); + + nvswitch_os_free(pBbxTempSamples); + } + else + { + NVSWITCH_PRINT(device, ERROR, "Unknown dataType %d", dataType); + goto nvswitch_bbx_get_data_ls10_unmap_and_exit; + } + +nvswitch_bbx_get_data_ls10_unmap_and_exit: + nvswitch_os_unmap_dma_region(device->os_handle, pDmaBuf, dmaHandle, + transferSize, NVSWITCH_DMA_DIR_FROM_SYSMEM); +nvswitch_bbx_get_data_ls10_free_and_exit: + nvswitch_os_free_contig_memory(device->os_handle, pDmaBuf, transferSize); + + return status; +} diff --git a/src/common/nvswitch/kernel/ls10/intr_ls10.c b/src/common/nvswitch/kernel/ls10/intr_ls10.c index bcdc3de0e7..a55a9fea58 100644 --- a/src/common/nvswitch/kernel/ls10/intr_ls10.c +++ b/src/common/nvswitch/kernel/ls10/intr_ls10.c @@ -5545,8 +5545,6 @@ _nvswitch_emit_link_errors_nvldl_fatal_link_ls10 if (nvswitch_test_flags(pending, bit)) { NVSWITCH_REPORT_FATAL(_HW_DLPL_LTSSM_FAULT_DOWN, "LTSSM Fault Down", NV_FALSE); - error_event.error = INFOROM_NVLINK_DL_LTSSM_FAULT_DOWN_FATAL; - nvswitch_inforom_nvlink_log_error_event(device, &error_event); } } @@ -5827,17 +5825,18 @@ _nvswitch_deferred_link_state_check_ls10 NvU64 lastLinkUpTime; NvU64 lastRetrainTime; NvU64 current_time = nvswitch_os_get_platform_time(); + NvBool bRedeferLinkStateCheck; chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); lastLinkUpTime = chip_device->deferredLinkErrors[link].state.lastLinkUpTime; lastRetrainTime = chip_device->deferredLinkErrors[link].state.lastRetrainTime; - // Sanity Check NVSWITCH_ASSERT(nvswitch_is_link_valid(device, link)); nvswitch_os_free(pErrorReportParams); pErrorReportParams = NULL; chip_device->deferredLinkErrors[link].state.bLinkStateCallBackEnabled = NV_FALSE; + bRedeferLinkStateCheck = NV_FALSE; // Link came up after last retrain if (lastLinkUpTime >= lastRetrainTime) @@ -5854,16 +5853,21 @@ _nvswitch_deferred_link_state_check_ls10 { if ((current_time - lastRetrainTime) < NVSWITCH_DEFERRED_LINK_STATE_CHECK_INTERVAL_NS) { - nvswitch_create_deferred_link_state_check_task_ls10(device, nvlipt_instance, link); - return; + bRedeferLinkStateCheck = NV_TRUE; } } + if (bRedeferLinkStateCheck) + { + nvswitch_create_deferred_link_state_check_task_ls10(device, nvlipt_instance, link); + return; + } + // // Otherwise, the link hasn't retrained within the timeout so emit the // deferred errors. // - _nvswitch_emit_deferred_link_errors_ls10(device, nvlipt_instance, link); + _nvswitch_emit_deferred_link_errors_ls10(device, nvlipt_instance, link); _nvswitch_clear_deferred_link_errors_ls10(device, link); } @@ -5948,9 +5952,9 @@ _nvswitch_deferred_link_errors_check_ls10 // It is assumed that this callback runs long before a link could have been // retrained and hit errors again. // - _nvswitch_emit_deferred_link_errors_ls10(device, nvlipt_instance, link); - _nvswitch_clear_deferred_link_errors_ls10(device, link); -} + _nvswitch_emit_deferred_link_errors_ls10(device, nvlipt_instance, link); + _nvswitch_clear_deferred_link_errors_ls10(device, link); + } static void _nvswitch_create_deferred_link_errors_task_ls10 @@ -6645,6 +6649,12 @@ _nvswitch_service_nvlipt_lnk_status_ls10 link = nvswitch_get_link(device, link_id); chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); + + if (link == NULL) + { + return -NVL_BAD_ARGS; + } + pending = NVSWITCH_LINK_RD32(device, link_id, NVLIPT_LNK, _NVLIPT_LNK, _INTR_STATUS); enabled = NVSWITCH_LINK_RD32(device, link_id, NVLIPT_LNK, _NVLIPT_LNK, _INTR_INT1_EN); pending &= enabled; @@ -6670,12 +6680,6 @@ _nvswitch_service_nvlipt_lnk_status_ls10 { NVSWITCH_PRINT(device, INFO, "%s: nvlipt_lnk_status: Link is up!. LinkId %d\n", __FUNCTION__, link_id); - if (nvswitch_lib_notify_client_events(device, - NVSWITCH_DEVICE_EVENT_PORT_UP) != NVL_SUCCESS) - { - NVSWITCH_PRINT(device, ERROR, "%s: Failed to notify PORT_UP event. LinkId %d\n", - __FUNCTION__, link_id); - } // // When a link comes up ensure that we finish off the post-training tasks: @@ -6684,7 +6688,7 @@ _nvswitch_service_nvlipt_lnk_status_ls10 // nvswitch_corelib_training_complete_ls10(link); nvswitch_init_buffer_ready(device, link, NV_TRUE); - link->bRxDetected = NV_TRUE; + link->bRxDetected = NV_TRUE; // // Clear out any cached interrupts for the link and update the last link up timestamp @@ -7754,38 +7758,51 @@ nvswitch_service_nvldl_fatal_link_ls10 // pending DL interrupts. In order to log all error before wiping that state, // service all other interrupts before this one // - bit = DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_FAULT_DOWN, 1); if (nvswitch_test_flags(pending, bit)) { + nvswitch_record_port_event(device, &(device->log_PORT_EVENTS), link, NVSWITCH_PORT_EVENT_TYPE_DOWN); + if (nvswitch_lib_notify_client_events(device, + NVSWITCH_DEVICE_EVENT_PORT_DOWN) != NVL_SUCCESS) { - dlDeferredIntrLinkMask |= bit; + NVSWITCH_PRINT(device, ERROR, "%s: Failed to notify PORT_DOWN event\n", + __FUNCTION__); + } + dlDeferredIntrLinkMask |= bit; - // - // Since reset and drain will reset the link, including clearing - // pending interrupts, skip the clear write below. There are cases - // where link clocks will not be on after reset and drain so there - // maybe PRI errors on writing to the register - // - bRequireResetAndDrain = NV_TRUE; - } + // + // Since reset and drain will reset the link, including clearing + // pending interrupts, skip the clear write below. There are cases + // where link clocks will not be on after reset and drain so there + // maybe PRI errors on writing to the register + // + { + bRequireResetAndDrain = NV_TRUE; + } nvswitch_clear_flags(&unhandled, bit); } bit = DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_FAULT_UP, 1); if (nvswitch_test_flags(pending, bit)) { + nvswitch_record_port_event(device, &(device->log_PORT_EVENTS), link, NVSWITCH_PORT_EVENT_TYPE_DOWN); + if (nvswitch_lib_notify_client_events(device, + NVSWITCH_DEVICE_EVENT_PORT_DOWN) != NVL_SUCCESS) { - dlDeferredIntrLinkMask |= bit; + NVSWITCH_PRINT(device, ERROR, "%s: Failed to notify PORT_DOWN event\n", + __FUNCTION__); + } + dlDeferredIntrLinkMask |= bit; - // - // Since reset and drain will reset the link, including clearing - // pending interrupts, skip the clear write below. There are cases - // where link clocks will not be on after reset and drain so there - // maybe PRI errors on writing to the register - // - bRequireResetAndDrain = NV_TRUE; - } + // + // Since reset and drain will reset the link, including clearing + // pending interrupts, skip the clear write below. There are cases + // where link clocks will not be on after reset and drain so there + // maybe PRI errors on writing to the register + // + { + bRequireResetAndDrain = NV_TRUE; + } nvswitch_clear_flags(&unhandled, bit); } diff --git a/src/common/nvswitch/kernel/ls10/link_ls10.c b/src/common/nvswitch/kernel/ls10/link_ls10.c index 0a3320d4e4..900ab70673 100644 --- a/src/common/nvswitch/kernel/ls10/link_ls10.c +++ b/src/common/nvswitch/kernel/ls10/link_ls10.c @@ -98,30 +98,6 @@ _nvswitch_configure_reserved_throughput_counters DRF_DEF(_NVLTLC_TX_LNK, _DEBUG_TP_CNTR_CTRL_0, _ENABLE, _ENABLE)); } -void -nvswitch_program_l1_scratch_reg_ls10 -( - nvswitch_device *device, - NvU32 linkNumber -) -{ - NvU32 scrRegVal; - NvU32 tempRegVal; - - // Read L1 register and store initial/VBIOS L1 Threshold Value in Scratch register - tempRegVal = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLIPT_LNK, _NVLIPT_LNK, _PWRM_L1_ENTER_THRESHOLD); - - scrRegVal = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLIPT_LNK, _NVLIPT_LNK, _SCRATCH_WARM); - - // Update the scratch register value only if it has not been written to before - if (scrRegVal == NV_NVLIPT_LNK_SCRATCH_WARM_DATA_INIT) - { - NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLIPT_LNK, _NVLIPT_LNK, _SCRATCH_WARM, tempRegVal); - } -} - -#define BUG_3797211_LS10_VBIOS_VERSION 0x9610410000 - void nvswitch_init_lpwr_regs_ls10 ( @@ -134,55 +110,33 @@ nvswitch_init_lpwr_regs_ls10 NvU32 tempRegVal, lpEntryThreshold; NvU8 softwareDesired; NvBool bLpEnable; - NvU64 biosVersion; - if (device->regkeys.enable_pm == NV_SWITCH_REGKEY_ENABLE_PM_NO) + if (IS_RTLSIM(device) || IS_EMULATION(device) || IS_FMODEL(device)) { return; } - if (nvswitch_lib_get_bios_version(device, &biosVersion) != NVL_SUCCESS) + if (device->regkeys.enable_pm == NV_SWITCH_REGKEY_ENABLE_PM_NO) { - NVSWITCH_PRINT(device, WARN, "%s Get VBIOS version failed.\n", - __FUNCTION__); - biosVersion = 0; + return; } // bios_config = nvswitch_get_bios_nvlink_config(device); - if (biosVersion >= BUG_3797211_LS10_VBIOS_VERSION) + + // IC Enter Threshold + if (device->regkeys.lp_threshold == NV_SWITCH_REGKEY_SET_LP_THRESHOLD_DEFAULT) { - // IC Enter Threshold - if (device->regkeys.lp_threshold == NV_SWITCH_REGKEY_SET_LP_THRESHOLD_DEFAULT) - { - // - // Do nothing since VBIOS (version 96.10.41.00.00 and above) - // sets the default L1 threshold. - // Refer Bug 3797211 for more info. - // - } - else - { - lpEntryThreshold = device->regkeys.lp_threshold; - tempRegVal = 0; - tempRegVal = FLD_SET_DRF_NUM(_NVLIPT, _LNK_PWRM_L1_ENTER_THRESHOLD, _THRESHOLD, lpEntryThreshold, tempRegVal); - NVSWITCH_LINK_WR32_LS10(device, linkNum, NVLIPT_LNK, _NVLIPT_LNK, _PWRM_L1_ENTER_THRESHOLD, tempRegVal); - } + // + // Do nothing since VBIOS sets the default L1 threshold. + // Refer Bug 3797211 for more info. + // } else { - // IC Enter Threshold - if (device->regkeys.lp_threshold == NV_SWITCH_REGKEY_SET_LP_THRESHOLD_DEFAULT) - { - lpEntryThreshold = 1; - } - else - { - lpEntryThreshold = device->regkeys.lp_threshold; - } - - tempRegVal = 0; - tempRegVal = FLD_SET_DRF_NUM(_NVLIPT, _LNK_PWRM_L1_ENTER_THRESHOLD, _THRESHOLD, lpEntryThreshold, tempRegVal); - NVSWITCH_LINK_WR32_LS10(device, linkNum, NVLIPT_LNK, _NVLIPT_LNK, _PWRM_L1_ENTER_THRESHOLD, tempRegVal); + lpEntryThreshold = device->regkeys.lp_threshold; + tempRegVal = 0; + tempRegVal = FLD_SET_DRF_NUM(_NVLIPT, _LNK_PWRM_L1_ENTER_THRESHOLD, _THRESHOLD, lpEntryThreshold, tempRegVal); + NVSWITCH_LINK_WR32_LS10(device, linkNum, NVLIPT_LNK, _NVLIPT_LNK, _PWRM_L1_ENTER_THRESHOLD, tempRegVal); } //LP Entry Enable @@ -211,6 +165,7 @@ nvswitch_corelib_training_complete_ls10 NVSWITCH_PRINT(device, ERROR, "%s: Failed to notify PORT_UP event\n", __FUNCTION__); } + nvswitch_record_port_event(device, &(device->log_PORT_EVENTS), link->linkNumber, NVSWITCH_PORT_EVENT_TYPE_UP); return; } @@ -1470,7 +1425,7 @@ nvswitch_load_link_disable_settings_ls10 nvswitch_device *device, nvlink_link *link ) -{ +{ NvU32 regVal; // Read state from NVLIPT HW @@ -1479,7 +1434,7 @@ nvswitch_load_link_disable_settings_ls10 if (FLD_TEST_DRF(_NVLIPT_LNK, _CTRL_LINK_STATE_STATUS, _CURRENTLINKSTATE, _DISABLE, regVal)) { - + // Set link to invalid and unregister from corelib device->link[link->linkNumber].valid = NV_FALSE; nvlink_lib_unregister_link(link); @@ -1619,7 +1574,7 @@ nvswitch_reset_and_train_link_ls10 link_intr_subcode = DRF_VAL(_NVLSTAT, _MN00, _LINK_INTR_SUBCODE, stat_data); if ((link_state == NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_MINION_REQUEST_FAIL) && - (link_intr_subcode == MINION_ALARM_BUSY)) + (link_intr_subcode == MINION_ALARM_BUSY)) { status = nvswitch_request_tl_link_state_ls10(link, diff --git a/src/common/nvswitch/kernel/ls10/ls10.c b/src/common/nvswitch/kernel/ls10/ls10.c index 3b2c797476..741312ee90 100644 --- a/src/common/nvswitch/kernel/ls10/ls10.c +++ b/src/common/nvswitch/kernel/ls10/ls10.c @@ -1353,7 +1353,7 @@ nvswitch_init_warm_reset_ls10 ) { NVSWITCH_PRINT(device, WARN, "%s: Function not implemented\n", __FUNCTION__); -} + } // // Helper funcction to query MINION to see if DL clocks are on @@ -1401,11 +1401,8 @@ _nvswitch_are_dl_clocks_on return NV_TRUE; } -// -// Implement reset and drain sequence for ls10 -// -NvlStatus -nvswitch_reset_and_drain_links_ls10 +static NvlStatus +_nvswitch_reset_and_drain_links_ls10 ( nvswitch_device *device, NvU64 link_mask @@ -1425,7 +1422,6 @@ nvswitch_reset_and_drain_links_ls10 NvBool bAreDlClocksOn; NVSWITCH_TIMEOUT timeout; - if (link_mask == 0) { NVSWITCH_PRINT(device, ERROR, "%s: Invalid link_mask 0\n", @@ -1538,6 +1534,14 @@ nvswitch_reset_and_drain_links_ls10 NVSWITCH_PRINT(device, ERROR, "%s: link %d failed to enter emergency shutdown\n", __FUNCTION__, link); + + // Re-register links. + status = nvlink_lib_register_link(device->nvlink_device, link_info); + if (status != NVL_SUCCESS) + { + nvswitch_destroy_link(link_info); + } + continue; } @@ -1632,10 +1636,10 @@ nvswitch_reset_and_drain_links_ls10 nvswitch_soe_restore_nport_state_ls10(device, link); // Step 7.0 : Re-program the routing table for DBEs - + // Step 8.0 : Reset NVLW and NPORT interrupt state _nvswitch_link_reset_interrupts_ls10(device, link); - + // Re-register links. status = nvlink_lib_register_link(device->nvlink_device, link_info); if (status != NVL_SUCCESS) @@ -1654,16 +1658,18 @@ nvswitch_reset_and_drain_links_ls10 // Request active, but don't block. FM will come back and check // active link status by blocking on this TLREQ's completion // - status = nvswitch_request_tl_link_state_ls10(link_info, - NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_ACTIVE, - NV_FALSE); - - if (status != NVL_SUCCESS) { - NVSWITCH_PRINT(device, ERROR, - "%s: TL link state request to active for ALI failed for link: 0x%x\n", - __FUNCTION__, link); - continue; + status = nvswitch_request_tl_link_state_ls10(link_info, + NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_ACTIVE, + NV_FALSE); + + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: TL link state request to active for ALI failed for link: 0x%x\n", + __FUNCTION__, link); + continue; + } } bAreDlClocksOn = NV_FALSE; @@ -1692,7 +1698,26 @@ nvswitch_reset_and_drain_links_ls10 } FOR_EACH_INDEX_IN_MASK_END; - // TODO: CCI Links Support: Reset the CCI links + return NVL_SUCCESS; +} + +// +// Implement reset and drain sequence for ls10 +// +NvlStatus +nvswitch_reset_and_drain_links_ls10 +( + nvswitch_device *device, + NvU64 link_mask +) +{ + NvlStatus status = NVL_SUCCESS; + + status = _nvswitch_reset_and_drain_links_ls10(device, link_mask); + if (status != NVL_SUCCESS) + { + return status; + } return NVL_SUCCESS; } @@ -2841,17 +2866,6 @@ nvswitch_set_fatal_error_ls10 NVSWITCH_ASSERT(link_id < nvswitch_get_num_links(device)); - // On first fatal error, notify PORT_DOWN - if (!device->link[link_id].fatal_error_occurred) - { - if (nvswitch_lib_notify_client_events(device, - NVSWITCH_DEVICE_EVENT_PORT_DOWN) != NVL_SUCCESS) - { - NVSWITCH_PRINT(device, ERROR, "%s: Failed to notify PORT_DOWN event\n", - __FUNCTION__); - } - } - device->link[link_id].fatal_error_occurred = NV_TRUE; if (device_fatal) @@ -2927,6 +2941,11 @@ nvswitch_is_soe_supported_ls10 return NV_FALSE; } + if (device->regkeys.soe_disable == NV_SWITCH_REGKEY_SOE_DISABLE_YES) + { + NVSWITCH_PRINT(device, WARN, "SOE can not be disabled via regkey.\n"); + } + return NV_TRUE; } @@ -5896,29 +5915,29 @@ nvswitch_read_vbios_link_entries_ls10 tblPtr += (sizeof(NVLINK_VBIOS_CONFIG_DATA_LINKENTRY_20)/sizeof(NvU32)); - NVSWITCH_PRINT(device, SETUP, + NVSWITCH_PRINT(device, NOISY, "<<<---- NvLink ID 0x%x ---->>>\n", i); - NVSWITCH_PRINT(device, SETUP, + NVSWITCH_PRINT(device, NOISY, "NVLink Params 0 \t0x%x \tBinary:"BYTE_TO_BINARY_PATTERN"\n", vbios_link_entry.nvLinkparam0, BYTE_TO_BINARY(vbios_link_entry.nvLinkparam0)); - NVSWITCH_PRINT(device, SETUP, + NVSWITCH_PRINT(device, NOISY, "NVLink Params 1 \t0x%x \tBinary:"BYTE_TO_BINARY_PATTERN"\n", vbios_link_entry.nvLinkparam1, BYTE_TO_BINARY(vbios_link_entry.nvLinkparam1)); - NVSWITCH_PRINT(device, SETUP, + NVSWITCH_PRINT(device, NOISY, "NVLink Params 2 \t0x%x \tBinary:"BYTE_TO_BINARY_PATTERN"\n", vbios_link_entry.nvLinkparam2, BYTE_TO_BINARY(vbios_link_entry.nvLinkparam2)); - NVSWITCH_PRINT(device, SETUP, + NVSWITCH_PRINT(device, NOISY, "NVLink Params 3 \t0x%x \tBinary:"BYTE_TO_BINARY_PATTERN"\n", vbios_link_entry.nvLinkparam3, BYTE_TO_BINARY(vbios_link_entry.nvLinkparam3)); - NVSWITCH_PRINT(device, SETUP, + NVSWITCH_PRINT(device, NOISY, "NVLink Params 4 \t0x%x \tBinary:"BYTE_TO_BINARY_PATTERN"\n", vbios_link_entry.nvLinkparam4, BYTE_TO_BINARY(vbios_link_entry.nvLinkparam4)); - NVSWITCH_PRINT(device, SETUP, + NVSWITCH_PRINT(device, NOISY, "NVLink Params 5 \t0x%x \tBinary:"BYTE_TO_BINARY_PATTERN"\n", vbios_link_entry.nvLinkparam5, BYTE_TO_BINARY(vbios_link_entry.nvLinkparam5)); - NVSWITCH_PRINT(device, SETUP, + NVSWITCH_PRINT(device, NOISY, "NVLink Params 6 \t0x%x \tBinary:"BYTE_TO_BINARY_PATTERN"\n", vbios_link_entry.nvLinkparam6, BYTE_TO_BINARY(vbios_link_entry.nvLinkparam6)); - NVSWITCH_PRINT(device, SETUP, + NVSWITCH_PRINT(device, NOISY, "NVLink Params 7 \t0x%x \tBinary:"BYTE_TO_BINARY_PATTERN"\n", vbios_link_entry.nvLinkparam7, BYTE_TO_BINARY(vbios_link_entry.nvLinkparam7)); - NVSWITCH_PRINT(device, SETUP, + NVSWITCH_PRINT(device, NOISY, "NVLink Params 8 \t0x%x \tBinary:"BYTE_TO_BINARY_PATTERN"\n", vbios_link_entry.nvLinkparam8, BYTE_TO_BINARY(vbios_link_entry.nvLinkparam8)); - NVSWITCH_PRINT(device, SETUP, + NVSWITCH_PRINT(device, NOISY, "NVLink Params 9 \t0x%x \tBinary:"BYTE_TO_BINARY_PATTERN"\n", vbios_link_entry.nvLinkparam9, BYTE_TO_BINARY(vbios_link_entry.nvLinkparam9)); - NVSWITCH_PRINT(device, SETUP, + NVSWITCH_PRINT(device, NOISY, "<<<---- NvLink ID 0x%x ---->>>\n\n", i); } *identified_link_entriesCount = i; diff --git a/src/common/nvswitch/kernel/ls10/soe_ls10.c b/src/common/nvswitch/kernel/ls10/soe_ls10.c index cb5095cb7f..65c4c861fa 100644 --- a/src/common/nvswitch/kernel/ls10/soe_ls10.c +++ b/src/common/nvswitch/kernel/ls10/soe_ls10.c @@ -515,7 +515,7 @@ nvswitch_soe_disable_nport_fatal_interrupts_ls10 NvlStatus stat; stat = device->hal.nvswitch_ctrl_get_bios_info(device, &p); - if ((stat != NVL_SUCCESS) || ((p.version & SOE_VBIOS_VERSION_MASK) < + if ((stat != NVL_SUCCESS) || ((p.version & SOE_VBIOS_VERSION_MASK) < SOE_VBIOS_REVLOCK_DISABLE_NPORT_FATAL_INTR)) { NVSWITCH_PRINT(device, ERROR, diff --git a/src/common/nvswitch/kernel/nvswitch.c b/src/common/nvswitch/kernel/nvswitch.c index bedc56600b..e1cb318e8d 100644 --- a/src/common/nvswitch/kernel/nvswitch.c +++ b/src/common/nvswitch/kernel/nvswitch.c @@ -30,6 +30,7 @@ #include "flcn/haldefs_flcnable_nvswitch.h" #include "flcn/flcn_nvswitch.h" #include "soe/soe_nvswitch.h" +#include "soe/soeififr.h" #include "nvVer.h" #include "nvlink_inband_msg.h" @@ -543,7 +544,19 @@ _nvswitch_init_device_regkeys NVSWITCH_INIT_REGKEY(_PRIVATE, reference_clock_mode, NV_SWITCH_REGKEY_REFERENCE_CLOCK_MODE, NV_SWITCH_REGKEY_REFERENCE_CLOCK_MODE_DEFAULT); + + NVSWITCH_INIT_REGKEY(_PRIVATE, debug_level, + NV_SWITCH_REGKEY_DBG_LEVEL, + NV_SWITCH_REGKEY_DBG_LEVEL_DEFAULT); } + +ct_assert(NVSWITCH_DBG_LEVEL_MMIO == NV_SWITCH_REGKEY_DBG_LEVEL_MMIO); +ct_assert(NVSWITCH_DBG_LEVEL_NOISY == NV_SWITCH_REGKEY_DBG_LEVEL_NOISY); +ct_assert(NVSWITCH_DBG_LEVEL_SETUP == NV_SWITCH_REGKEY_DBG_LEVEL_SETUP); +ct_assert(NVSWITCH_DBG_LEVEL_INFO == NV_SWITCH_REGKEY_DBG_LEVEL_INFO); +ct_assert(NVSWITCH_DBG_LEVEL_WARN == NV_SWITCH_REGKEY_DBG_LEVEL_WARN); +ct_assert(NVSWITCH_DBG_LEVEL_ERROR == NV_SWITCH_REGKEY_DBG_LEVEL_ERROR); + NvU64 nvswitch_lib_deferred_task_dispatcher ( @@ -727,12 +740,6 @@ nvswitch_is_soe_supported nvswitch_device *device ) { - if (device->regkeys.soe_disable == NV_SWITCH_REGKEY_SOE_DISABLE_YES) - { - NVSWITCH_PRINT(device, INFO, "SOE is disabled via regkey.\n"); - return NV_FALSE; - } - return device->hal.nvswitch_is_soe_supported(device); } @@ -743,12 +750,6 @@ nvswitch_init_soe nvswitch_device *device ) { - if (device->regkeys.soe_disable == NV_SWITCH_REGKEY_SOE_DISABLE_YES) - { - NVSWITCH_PRINT(device, INFO, "SOE is disabled via regkey.\n"); - return NV_FALSE; - } - return device->hal.nvswitch_init_soe(device); } @@ -1335,6 +1336,75 @@ _nvswitch_ctrl_therm_get_temperature_limit return device->hal.nvswitch_ctrl_therm_get_temperature_limit(device, pParams); } +// +// Construct an port event log +// +// If port_event_log_size > 0 a circular buffer is created to record port events +// +NvlStatus +_nvswitch_construct_port_event_log +( + NVSWITCH_PORT_EVENT_LOG_TYPE *port_events, + NvU32 port_event_log_size, + NvBool overwritable +) +{ + NvlStatus retval = NVL_SUCCESS; + + NVSWITCH_ASSERT(port_events != NULL); + + port_events->port_event_start = 0; + port_events->port_event_count = 0; + port_events->port_event_total = 0; + port_events->port_event_log_size = 0; + port_events->port_event_log = NULL; + port_events->overwritable = overwritable; + port_events->bOverflow = NV_FALSE; + + if (port_event_log_size > 0) + { + port_events->port_event_log = nvswitch_os_malloc(port_event_log_size * sizeof(NVSWITCH_PORT_EVENT_TYPE)); + } + + if (port_events->port_event_log != NULL) + { + port_events->port_event_log_size = port_event_log_size; + nvswitch_os_memset(port_events->port_event_log, 0, port_events->port_event_log_size * sizeof(NVSWITCH_PORT_EVENT_TYPE)); + } + + if (port_event_log_size != port_events->port_event_log_size) + { + retval = -NVL_NO_MEM; + } + + return retval; +} + +// +// Destroy an error log +// +void +_nvswitch_destroy_port_event_log +( + nvswitch_device *device, + NVSWITCH_PORT_EVENT_LOG_TYPE *port_events +) +{ + if (port_events == NULL) + return; + + port_events->port_event_start = 0; + port_events->port_event_count = 0; + port_events->port_event_log_size = 0; + port_events->bOverflow = NV_FALSE; + + if (port_events->port_event_log != NULL) + { + nvswitch_os_free(port_events->port_event_log); + port_events->port_event_log = NULL; + } +} + NvlStatus nvswitch_lib_initialize_device ( @@ -1507,17 +1577,10 @@ nvswitch_lib_initialize_device nvswitch_reset_persistent_link_hw_state(device, link_num); - // - // During Nvswitch initialization, the default L1 thresholds are programmed by the - // BIOS from the BIOS tables. Save these L1 Threshold Values in scratch registers - // for use when resetting the thresholds to default. - // - nvswitch_program_l1_scratch_reg(device, link_num); - // // WAR : Initializing the L1 threshold registers at this point as a WAR for - // Bug 3963639 where it was discussed that the L1 threshold register should have - // the default value for all available links and not just for active links. + // Bug 3963639 where is it was discussed that the L1 threshold register should have + // value the default value for all available links and not just for active links. // nvswitch_init_lpwr_regs(link); } @@ -1546,6 +1609,13 @@ nvswitch_lib_initialize_device goto nvswitch_construct_error_log_fail; } + retval = _nvswitch_construct_port_event_log(&device->log_PORT_EVENTS, NVSWITCH_PORT_EVENT_LOG_SIZE, NV_TRUE); + if (retval != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "Failed to construct log_PORT_EVENTS! rc: %d\n", retval); + goto nvswitch_construct_port_event_log_fail; + } + if (device->regkeys.latency_counter == NV_SWITCH_REGKEY_LATENCY_COUNTER_LOGGING_ENABLE) { nvswitch_task_create(device, &nvswitch_internal_latency_bin_log, @@ -1576,6 +1646,10 @@ nvswitch_lib_initialize_device nvswitch_destroy_error_log(device, &device->log_FATAL_ERRORS); nvswitch_destroy_error_log(device, &device->log_NONFATAL_ERRORS); +nvswitch_construct_port_event_log_fail: + //free allocated memory to avoid leaking + _nvswitch_destroy_port_event_log(device, &device->log_PORT_EVENTS); + nvswitch_link_fail: // Track down all links that successfully registered. for (link_num = 0; link_num < nvswitch_get_num_links(device); link_num++) @@ -1675,7 +1749,7 @@ nvswitch_lib_post_init_device } // - // There is an edge case where a hypervisor may not send same number + // There is an edge case where a hyperisor may not send same number // of reset to switch and GPUs, so try to re-train links in fault // if possible // @@ -1928,6 +2002,158 @@ nvswitch_lib_notify_client_events return NVL_SUCCESS; } +void +nvswitch_record_port_event +( + nvswitch_device *device, + NVSWITCH_PORT_EVENT_LOG_TYPE *port_events, + NvU32 link_id, + NvU8 port_event_type +) +{ + NvU32 idx; + + NVSWITCH_ASSERT(port_events != NULL); + + // If no port events log has been created, then don't log it. + if ((port_events->port_event_log_size != 0) && + (port_events->port_event_log != NULL)) + { + idx = (port_events->port_event_start + port_events->port_event_count) + % port_events->port_event_log_size; + + if (port_events->port_event_count == port_events->port_event_log_size) + { + // Error: ring buffer is already full/ + if (port_events->overwritable) + { + port_events->port_event_start = (port_events->port_event_start + 1) + % port_events->port_event_log_size; + port_events->bOverflow = NV_TRUE; + } + else + { + // No logging, ring buffer is full + return; + } + } + else + { + port_events->port_event_count++; + } + // Log port event info + port_events->port_event_log[idx].link_id = link_id; + port_events->port_event_log[idx].port_event_type = port_event_type; + + // Log tracking info + port_events->port_event_log[idx].time = nvswitch_os_get_platform_time(); + port_events->port_event_log[idx].local_port_event_num = port_events->port_event_total; + } + port_events->port_event_total++; +} + +/* + * @Brief : Retrives a port event entry by index. + * + * @Description : Retrieves the port_event at index port_event_idx. If index is out + * of range, returns an empty port event entry with port_event_type = 2 + * + * @param[in] device NVSwitch device to contain this link + * @param[in] port_events Log of all port events with metadata + * @param[in] port_event_idx Index of entry to retrieve (0 = oldest port event) + * @param[out] port_event_count Clear only non-persistent list + */ +void +nvswitch_get_port_event +( + nvswitch_device *device, + NVSWITCH_PORT_EVENT_LOG_TYPE *port_events, + NVSWITCH_PORT_EVENT_TYPE *port_event_entry, + NvU32 port_event_idx, + NvU32 *port_event_count +) +{ + NvU32 idx; + NVSWITCH_ASSERT(port_events != NULL); + + if (port_event_entry != NULL) + { + // Index is out of range + if (port_event_idx >= port_events->port_event_count) + { + nvswitch_os_memset(port_event_entry, 0, sizeof(*port_event_entry)); + port_event_entry->port_event_type = NVSWITCH_PORT_EVENT_TYPE_INVALID; + port_event_entry->time = nvswitch_os_get_platform_time(); + } + else + { + idx = (port_events->port_event_start + port_event_idx) % port_events->port_event_log_size; + *port_event_entry = port_events->port_event_log[idx]; + } + } + + if (port_event_count) + { + *port_event_count = port_events->port_event_count; + } +} + +NvlStatus +nvswitch_ctrl_get_port_events +( + nvswitch_device *device, + NVSWITCH_GET_PORT_EVENTS_PARAMS *p +) +{ + NvU32 index = 0; + NvU32 count = 0; + NVSWITCH_PORT_EVENT_LOG_TYPE *port_events = &device->log_PORT_EVENTS; + NVSWITCH_PORT_EVENT_TYPE port_event; + + nvswitch_os_memset(p->portEvent, 0, sizeof(NVSWITCH_PORT_EVENT) + *NVSWITCH_PORT_EVENT_COUNT_SIZE); + p->nextPortEventIndex = port_events->port_event_total; + p->portEventCount = 0; + p->bOverflow = port_events->bOverflow; + + // Return if there are no more port events to get + nvswitch_get_port_event(device, port_events, &port_event, index, &count); + if (count == 0) + { + return NVL_SUCCESS; + } + + // If port event's local_port_Event_num is smaller than the portEventIndex + // passed in by the client, fast-forward index by the difference. + // This will skip over port events that were previously read by the client. + if (port_event.local_port_event_num < p->portEventIndex) + { + index = (NvU32) (p->portEventIndex - port_event.local_port_event_num); + } + + // Return if there are no more events after fast-forwarding. + if (index >= count) + { + return NVL_SUCCESS; + } + + while ((p->portEventCount < NVSWITCH_PORT_EVENT_COUNT_SIZE) && (index < count)) + { + nvswitch_get_port_event(device, port_events, &port_event, index, NULL); + + p->portEvent[p->portEventCount].port_event_type = port_event.port_event_type; + p->portEvent[p->portEventCount].link_id = port_event.link_id; + p->portEvent[p->portEventCount].time = port_event.time; + + p->portEventCount++; + index++; + } + + p->portEventIndex = port_event.local_port_event_num + 1; + + return NVL_SUCCESS; +} + /*! @brief: Release ROM image from memory. */ @@ -1989,6 +2215,8 @@ nvswitch_lib_shutdown_device nvswitch_destroy_error_log(device, &device->log_FATAL_ERRORS); nvswitch_destroy_error_log(device, &device->log_NONFATAL_ERRORS); + _nvswitch_destroy_port_event_log(device, &device->log_PORT_EVENTS); + nvswitch_smbpbi_unload(device); _nvswitch_destroy_event_list(device); @@ -2012,17 +2240,18 @@ NvlStatus nvswitch_lib_get_log_count ( nvswitch_device *device, - NvU32 *fatal, NvU32 *nonfatal + NvU32 *fatal, NvU32 *nonfatal, NvU32 *portEvent ) { if (!NVSWITCH_IS_DEVICE_INITIALIZED(device) || - fatal == NULL || nonfatal == NULL) + fatal == NULL || nonfatal == NULL || portEvent == NULL) { return -NVL_BAD_ARGS; } *fatal = device->log_FATAL_ERRORS.error_count; *nonfatal = device->log_NONFATAL_ERRORS.error_count; + *portEvent = device->log_PORT_EVENTS.port_event_count; // No report of log_INFO currently return NVL_SUCCESS; @@ -3475,6 +3704,46 @@ _nvswitch_ctrl_get_inforom_bbx_sxid return nvswitch_inforom_bbx_get_sxid(device, params); } +static NvlStatus +_nvswitch_ctrl_get_inforom_bbx_sys_info +( + nvswitch_device *device, + NVSWITCH_GET_SYS_INFO_PARAMS *params +) +{ + return nvswitch_inforom_bbx_get_data(device, RM_SOE_IFR_BBX_GET_SYS_INFO, (void *)params); +} + +static NvlStatus +_nvswitch_ctrl_get_inforom_bbx_time_info +( + nvswitch_device *device, + NVSWITCH_GET_TIME_INFO_PARAMS *params +) +{ + return nvswitch_inforom_bbx_get_data(device, RM_SOE_IFR_BBX_GET_TIME_INFO, (void *)params); +} + +static NvlStatus +_nvswitch_ctrl_get_inforom_bbx_temp_data +( + nvswitch_device *device, + NVSWITCH_GET_TEMP_DATA_PARAMS *params +) +{ + return nvswitch_inforom_bbx_get_data(device, RM_SOE_IFR_BBX_GET_TEMP_DATA, (void *)params); +} + +static NvlStatus +_nvswitch_ctrl_get_inforom_bbx_temp_samples +( + nvswitch_device *device, + NVSWITCH_GET_TEMP_SAMPLES_PARAMS *params +) +{ + return nvswitch_inforom_bbx_get_data(device, RM_SOE_IFR_BBX_GET_TEMP_SAMPLES, (void *)params); +} + static NvlStatus _nvswitch_ctrl_get_nvlink_lp_counters ( @@ -4656,16 +4925,6 @@ nvswitch_init_lpwr_regs device->hal.nvswitch_init_lpwr_regs(link); } -void -nvswitch_program_l1_scratch_reg -( - nvswitch_device *device, - NvU32 linkNumber -) -{ - device->hal.nvswitch_program_l1_scratch_reg(device, linkNumber); -} - NvlStatus nvswitch_launch_ALI ( @@ -4870,6 +5129,9 @@ nvswitch_lib_ctrl NVSWITCH_DEV_CMD_DISPATCH(CTRL_NVSWITCH_GET_ERRORS, nvswitch_ctrl_get_errors, NVSWITCH_GET_ERRORS_PARAMS); + NVSWITCH_DEV_CMD_DISPATCH(CTRL_NVSWITCH_GET_PORT_EVENTS, + nvswitch_ctrl_get_port_events, + NVSWITCH_GET_PORT_EVENTS_PARAMS); NVSWITCH_DEV_CMD_DISPATCH(CTRL_NVSWITCH_GET_NVLINK_STATUS, _nvswitch_ctrl_get_nvlink_status, NVSWITCH_GET_NVLINK_STATUS_PARAMS); @@ -5181,6 +5443,26 @@ nvswitch_lib_ctrl NVSWITCH_DEV_CMD_DISPATCH(CTRL_NVSWITCH_GET_POWER, _nvswitch_ctrl_therm_read_power, NVSWITCH_GET_POWER_PARAMS); + NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED( + CTRL_NVSWITCH_GET_SYS_INFO, + _nvswitch_ctrl_get_inforom_bbx_sys_info, + NVSWITCH_GET_SYS_INFO_PARAMS, + osPrivate, flags); + NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED( + CTRL_NVSWITCH_GET_TIME_INFO, + _nvswitch_ctrl_get_inforom_bbx_time_info, + NVSWITCH_GET_TIME_INFO_PARAMS, + osPrivate, flags); + NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED( + CTRL_NVSWITCH_GET_TEMP_DATA, + _nvswitch_ctrl_get_inforom_bbx_temp_data, + NVSWITCH_GET_TEMP_DATA_PARAMS, + osPrivate, flags); + NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED( + CTRL_NVSWITCH_GET_TEMP_SAMPLES, + _nvswitch_ctrl_get_inforom_bbx_temp_samples, + NVSWITCH_GET_TEMP_SAMPLES_PARAMS, + osPrivate, flags); default: nvswitch_os_print(NVSWITCH_DBG_LEVEL_INFO, "unknown ioctl %x\n", cmd); diff --git a/src/common/sdk/nvidia/inc/class/cl00de.h b/src/common/sdk/nvidia/inc/class/cl00de.h index 8d90d9d8a0..20227baf1c 100644 --- a/src/common/sdk/nvidia/inc/class/cl00de.h +++ b/src/common/sdk/nvidia/inc/class/cl00de.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -28,21 +28,168 @@ extern "C" { #endif +#include "nvmisc.h" +#include "nvfixedtypes.h" + #define RM_USER_SHARED_DATA (0x000000de) +#define RUSD_TIMESTAMP_WRITE_IN_PROGRESS (NV_U64_MAX) +#define RUSD_TIMESTAMP_INVALID 0 + +enum { + RUSD_CLK_PUBLIC_DOMAIN_GRAPHICS = 0, + RUSD_CLK_PUBLIC_DOMAIN_MEMORY, + RUSD_CLK_PUBLIC_DOMAIN_VIDEO, + + // Put at the end. See bug 1000230 NVML doesn't report SM frequency on Kepler + RUSD_CLK_PUBLIC_DOMAIN_SM, + RUSD_CLK_PUBLIC_DOMAIN_MAX_TYPE, +}; + +enum { + RUSD_CLK_THROTTLE_REASON_GPU_IDLE = NVBIT(0), + RUSD_CLK_THROTTLE_REASON_APPLICATION_CLOCK_SETTING = NVBIT(1), + RUSD_CLK_THROTTLE_REASON_SW_POWER_CAP = NVBIT(2), + RUSD_CLK_THROTTLE_REASON_HW_SLOWDOWN = NVBIT(3), + RUSD_CLK_THROTTLE_REASON_SYNC_BOOST = NVBIT(4), + RUSD_CLK_THROTTLE_REASON_SW_THERMAL_SLOWDOWN = NVBIT(5), + RUSD_CLK_THROTTLE_REASON_HW_THERMAL_SLOWDOWN = NVBIT(6), + RUSD_CLK_THROTTLE_REASON_HW_POWER_BRAKES_SLOWDOWN = NVBIT(7), + RUSD_CLK_THROTTLE_REASON_DISPLAY_CLOCK_SETTING = NVBIT(8), +}; + +typedef struct RUSD_CLK_PUBLIC_DOMAIN_INFO { + NvU32 targetClkMHz; +} RUSD_CLK_PUBLIC_DOMAIN_INFO; + +typedef struct RUSD_CLK_PUBLIC_DOMAIN_INFOS { + volatile NvU64 lastModifiedTimestamp; + RUSD_CLK_PUBLIC_DOMAIN_INFO info[RUSD_CLK_PUBLIC_DOMAIN_MAX_TYPE]; +} RUSD_CLK_PUBLIC_DOMAIN_INFOS; + +typedef struct RUSD_PERF_DEVICE_UTILIZATION_INFO { + NvU8 gpuPercentBusy; + NvU8 memoryPercentBusy; +} RUSD_PERF_DEVICE_UTILIZATION_INFO; + +typedef struct RUSD_PERF_DEVICE_UTILIZATION { + volatile NvU64 lastModifiedTimestamp; + RUSD_PERF_DEVICE_UTILIZATION_INFO info; +} RUSD_PERF_DEVICE_UTILIZATION; + +typedef struct RUSD_PERF_CURRENT_PSTATE { + volatile NvU64 lastModifiedTimestamp; + NvU32 currentPstate; +} RUSD_PERF_CURRENT_PSTATE; + +typedef struct RUSD_CLK_THROTTLE_REASON { + volatile NvU64 lastModifiedTimestamp; + NvU32 reasonMask; +} RUSD_CLK_THROTTLE_REASON; + +typedef struct RUSD_MEM_ERROR_COUNTS { + NvU64 correctedVolatile; + NvU64 correctedAggregate; + NvU64 uncorrectedVolatile; + NvU64 uncorrectedAggregate; +} RUSD_MEM_ERROR_COUNTS; + +#define RUSD_MEMORY_ERROR_TYPE_TOTAL 0 +#define RUSD_MEMORY_ERROR_TYPE_DRAM 1 +#define RUSD_MEMORY_ERROR_TYPE_SRAM 2 +#define RUSD_MEMORY_ERROR_TYPE_COUNT 3 + +typedef struct RUSD_MEM_ECC { + volatile NvU64 lastModifiedTimestamp; + RUSD_MEM_ERROR_COUNTS count[RUSD_MEMORY_ERROR_TYPE_COUNT]; +} RUSD_MEM_ECC; + +typedef struct RUSD_POWER_LIMIT_INFO { + NvU32 requestedmW; + NvU32 enforcedmW; +} RUSD_POWER_LIMIT_INFO; + +typedef struct RUSD_ENFORCED_POWER_LIMITS { + volatile NvU64 lastModifiedTimestamp; + RUSD_POWER_LIMIT_INFO info; +} RUSD_POWER_LIMITS; + +typedef struct RUSD_TEMPERATURE_INFO{ + NvTemp gpuTemperature; + NvTemp hbmTemperature; +} RUSD_TEMPERATURE_INFO; + +typedef struct RUSD_TEMPERATURE { + volatile NvU64 lastModifiedTimestamp; + RUSD_TEMPERATURE_INFO info; +} RUSD_TEMPERATURE; + +typedef struct RUSD_MEM_ROW_REMAP_INFO { + NvU32 histogramMax; // No remapped row is used. + NvU32 histogramHigh; // One remapped row is used. + NvU32 histogramPartial; // More than one remapped rows are used. + NvU32 histogramLow; // One remapped row is available. + NvU32 histogramNone; // All remapped rows are used. + + NvU32 correctableRows; + NvU32 uncorrectableRows; + NvBool isPending; + NvBool hasFailureOccurred; +} RUSD_MEM_ROW_REMAP_INFO; + +typedef struct RUSD_MEM_ROW_REMAP { + volatile NvU64 lastModifiedTimestamp; + RUSD_MEM_ROW_REMAP_INFO info; +} RUSD_MEM_ROW_REMAP; + +typedef struct RUSD_AVG_POWER_INFO { + NvU32 averageGpuPower; // mW + NvU32 averageModulePower; // mW + NvU32 averageMemoryPower; // mW +} RUSD_AVG_POWER_INFO; + +typedef struct RUSD_AVG_POWER_USAGE { + volatile NvU64 lastModifiedTimestamp; + RUSD_AVG_POWER_INFO info; +} RUSD_AVG_POWER_USAGE; + +typedef struct RUSD_INST_POWER_INFO { + NvU32 instGpuPower; // mW + NvU32 instModulePower; // mW +} RUSD_INST_POWER_INFO; + +typedef struct RUSD_INST_POWER_USAGE { + volatile NvU64 lastModifiedTimestamp; + RUSD_INST_POWER_INFO info; +} RUSD_INST_POWER_USAGE; + typedef struct NV00DE_SHARED_DATA { volatile NvU32 seq; NvU32 bar1Size; NvU32 bar1AvailSize; - NvU32 gspAssertCount; - // New data members always add to bottom + // GSP polling data section + NV_DECLARE_ALIGNED(RUSD_CLK_PUBLIC_DOMAIN_INFOS clkPublicDomainInfos, 8); + NV_DECLARE_ALIGNED(RUSD_CLK_THROTTLE_REASON clkThrottleReason, 8); + NV_DECLARE_ALIGNED(RUSD_PERF_DEVICE_UTILIZATION perfDevUtil, 8); + NV_DECLARE_ALIGNED(RUSD_MEM_ECC memEcc, 8); + NV_DECLARE_ALIGNED(RUSD_PERF_CURRENT_PSTATE perfCurrentPstate, 8); + NV_DECLARE_ALIGNED(RUSD_POWER_LIMITS powerLimitGpu, 8); // Module Limit is not supported on Ampere/Hopper + NV_DECLARE_ALIGNED(RUSD_TEMPERATURE temperature, 8); + NV_DECLARE_ALIGNED(RUSD_MEM_ROW_REMAP memRowRemap, 8); + NV_DECLARE_ALIGNED(RUSD_AVG_POWER_USAGE avgPowerUsage, 8); + NV_DECLARE_ALIGNED(RUSD_INST_POWER_USAGE instPowerUsage, 8); } NV00DE_SHARED_DATA; +#define NV00DE_RUSD_POLL_CLOCK 0x1 +#define NV00DE_RUSD_POLL_PERF 0x2 +#define NV00DE_RUSD_POLL_MEMORY 0x4 +#define NV00DE_RUSD_POLL_POWER 0x8 +#define NV00DE_RUSD_POLL_THERMAL 0x10 + typedef struct NV00DE_ALLOC_PARAMETERS { - // initialize to 0 - NvU32 reserved; + NvU64 polledDataMask; // Bitmask of data to request polling at alloc time, 0 if not needed } NV00DE_ALLOC_PARAMETERS; #ifdef __cplusplus diff --git a/src/common/sdk/nvidia/inc/class/cl00e0.h b/src/common/sdk/nvidia/inc/class/cl00e0.h new file mode 100644 index 0000000000..f2dce87735 --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/cl00e0.h @@ -0,0 +1,65 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl00e0.finn +// + +#include "nvcfg_sdk.h" +#include "cl0080.h" + + + +#define NV_MEMORY_EXPORT (0xe0U) /* finn: Evaluated from "NV00E0_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NV_MEM_EXPORT_UUID_LEN 16 +#define NV_MEM_EXPORT_PACKET_LEN 32 +#define NV_MEM_EXPORT_METADATA_LEN 64 + +typedef struct NV_EXPORT_MEM_PACKET { + NvU8 uuid[NV_MEM_EXPORT_UUID_LEN]; + NvU8 opaque[16]; +} NV_EXPORT_MEM_PACKET; + +#define NV_MEM_EXPORT_FLAGS_DEFAULT 0x00000000 +#define NV_MEM_EXPORT_FLAGS_DUP_BY_UUID 0x00000001 + + + +#define NV00E0_ALLOCATION_PARAMETERS_MESSAGE_ID (0x00e0U) + +typedef struct NV00E0_ALLOCATION_PARAMETERS { + NvU32 imexChannel; + NV_EXPORT_MEM_PACKET packet; + NvU16 numMaxHandles; + NvU32 flags; + NvU8 metadata[NV_MEM_EXPORT_METADATA_LEN]; + NvU32 deviceInstanceMask; + NvU32 giIdMasks[NV_MAX_DEVICES]; + NvU16 numCurHandles; +} NV00E0_ALLOCATION_PARAMETERS; diff --git a/src/common/sdk/nvidia/inc/class/cl00fd.h b/src/common/sdk/nvidia/inc/class/cl00fd.h index 062b380bb0..271bcb3ad3 100644 --- a/src/common/sdk/nvidia/inc/class/cl00fd.h +++ b/src/common/sdk/nvidia/inc/class/cl00fd.h @@ -34,7 +34,10 @@ // Source file: class/cl00fd.finn // -#define NV_MEMORY_MULTICAST_FABRIC (0xfdU) /* finn: Evaluated from "NV00FD_ALLOCATION_PARAMETERS_MESSAGE_ID" */ +#include "cl00e0.h" + +#define NV_MEMORY_MULTICAST_FABRIC (0xfdU) /* finn: Evaluated from "NV00FD_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + /* * alignment [IN] @@ -48,8 +51,7 @@ * Requested page size. Can be any of the NV_MEMORY_MULTICAST_FABRIC_PAGE_SIZE_* * * allocFlags [IN] - * Reserved for future use - * Clients should pass 0 as of now. + * Should be one of NV_MEMORY_MULTICAST_FABRIC_ALLOC_FLAGS_* * * numGpus [IN] * Number of unique GPUs to be attached. @@ -58,16 +60,20 @@ * Optional OS event handle created with NvRmAllocOsEvent(). */ -#define NV_MEMORY_MULTICAST_FABRIC_PAGE_SIZE_512M 0x20000000 +#define NV_MEMORY_MULTICAST_FABRIC_PAGE_SIZE_512M 0x20000000 + + #define NV00FD_ALLOCATION_PARAMETERS_MESSAGE_ID (0x00fdU) typedef struct NV00FD_ALLOCATION_PARAMETERS { + NV_EXPORT_MEM_PACKET expPacket; + NvU16 index; NV_DECLARE_ALIGNED(NvU64 alignment, 8); NV_DECLARE_ALIGNED(NvU64 allocSize, 8); - NvU32 pageSize; - NvU32 allocFlags; - NvU32 numGpus; + NvU32 pageSize; + NvU32 allocFlags; + NvU32 numGpus; NV_DECLARE_ALIGNED(NvP64 pOsEvent, 8); } NV00FD_ALLOCATION_PARAMETERS; diff --git a/src/common/sdk/nvidia/inc/class/cl2080_notification.h b/src/common/sdk/nvidia/inc/class/cl2080_notification.h index 66d8862ca9..1097ec791b 100644 --- a/src/common/sdk/nvidia/inc/class/cl2080_notification.h +++ b/src/common/sdk/nvidia/inc/class/cl2080_notification.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -24,10 +24,14 @@ #ifndef _cl2080_notification_h_ #define _cl2080_notification_h_ +#include "nvcfg_sdk.h" + #ifdef __cplusplus extern "C" { #endif +#include "nvcfg_sdk.h" + /* event values */ #define NV2080_NOTIFIERS_SW (0) #define NV2080_NOTIFIERS_HOTPLUG (1) @@ -187,6 +191,7 @@ extern "C" { #define NV2080_NOTIFIERS_GR6 (151) #define NV2080_NOTIFIERS_GR7 (152) #define NV2080_NOTIFIERS_OFA (153) +#define NV2080_NOTIFIERS_OFA0 NV2080_NOTIFIERS_OFA #define NV2080_NOTIFIERS_DSTATE_HDA (154) #define NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL (155) #define NV2080_NOTIFIERS_POISON_ERROR_FATAL (156) @@ -199,18 +204,31 @@ extern "C" { #define NV2080_NOTIFIERS_SEC_FAULT_ERROR (163) #define NV2080_NOTIFIERS_POSSIBLE_ERROR (164) #define NV2080_NOTIFIERS_NVLINK_INFO_LINK_UP (165) +#define NV2080_NOTIFIERS_RESERVED166 (166) +#define NV2080_NOTIFIERS_RESERVED167 (167) +#define NV2080_NOTIFIERS_RESERVED168 (168) +#define NV2080_NOTIFIERS_RESERVED169 (169) +#define NV2080_NOTIFIERS_RESERVED170 (170) +#define NV2080_NOTIFIERS_RESERVED171 (171) +#define NV2080_NOTIFIERS_RESERVED172 (172) +#define NV2080_NOTIFIERS_RESERVED173 (173) +#define NV2080_NOTIFIERS_RESERVED174 (174) +#define NV2080_NOTIFIERS_RESERVED175 (175) #define NV2080_NOTIFIERS_NVLINK_INFO_LINK_DOWN (176) #define NV2080_NOTIFIERS_NVPCF_EVENTS (177) #define NV2080_NOTIFIERS_HDMI_FRL_RETRAINING_REQUEST (178) #define NV2080_NOTIFIERS_VRR_SET_TIMEOUT (179) -#define NV2080_NOTIFIERS_AUX_POWER_STATE_CHANGE (180) -#define NV2080_NOTIFIERS_MAXCOUNT (181) +#define NV2080_NOTIFIERS_RESERVED180 (180) +#define NV2080_NOTIFIERS_AUX_POWER_EVENT (181) +#define NV2080_NOTIFIERS_AUX_POWER_STATE_CHANGE (182) +#define NV2080_NOTIFIERS_MAXCOUNT (183) // Indexed GR notifier reference #define NV2080_NOTIFIERS_GR(x) ((x == 0) ? (NV2080_NOTIFIERS_GR0) : (NV2080_NOTIFIERS_GR1 + (x - 1))) #define NV2080_NOTIFIERS_GR_IDX(x) ((x) - NV2080_NOTIFIERS_GR0) #define NV2080_NOTIFIER_TYPE_IS_GR(x) (((x) == NV2080_NOTIFIERS_GR0) || (((x) >= NV2080_NOTIFIERS_GR1) && ((x) <= NV2080_NOTIFIERS_GR7))) +// Indexed CE notifier reference #define NV2080_NOTIFIERS_CE(x) (NV2080_NOTIFIERS_CE0 + (x)) #define NV2080_NOTIFIERS_CE_IDX(x) ((x) - NV2080_NOTIFIERS_CE0) #define NV2080_NOTIFIER_TYPE_IS_CE(x) (((x) >= NV2080_NOTIFIERS_CE0) && ((x) <= NV2080_NOTIFIERS_CE9)) @@ -228,6 +246,11 @@ extern "C" { #define NV2080_NOTIFIERS_NVJPEG_IDX(x) ((x) - NV2080_NOTIFIERS_NVJPEG0) #define NV2080_NOTIFIER_TYPE_IS_NVJPEG(x) (((x) >= NV2080_NOTIFIERS_NVJPEG0) && ((x) <= NV2080_NOTIFIERS_NVJPEG7)) +// Indexed OFA notifier reference +#define NV2080_NOTIFIERS_OFAn(x) ((x == 0) ? (NV2080_NOTIFIERS_OFA0) : (NV2080_NOTIFIERS_MAXCOUNT)) +#define NV2080_NOTIFIERS_OFA_IDX(x) ((x == NV2080_NOTIFIERS_OFA0) ? (0) : (-1)) +#define NV2080_NOTIFIER_TYPE_IS_OFA(x) (((x) == NV2080_NOTIFIERS_OFA0)) + #define NV2080_NOTIFIERS_GPIO_RISING_INTERRUPT(pin) (NV2080_NOTIFIERS_GPIO_0_RISING_INTERRUPT + (pin)) #define NV2080_NOTIFIERS_GPIO_FALLING_INTERRUPT(pin) (NV2080_NOTIFIERS_GPIO_0_FALLING_INTERRUPT + (pin)) @@ -295,14 +318,34 @@ extern "C" { #define NV2080_ENGINE_TYPE_NVJPEG6 (0x00000031) #define NV2080_ENGINE_TYPE_NVJPEG7 (0x00000032) #define NV2080_ENGINE_TYPE_OFA (0x00000033) -#define NV2080_ENGINE_TYPE_LAST (0x0000003e) +#define NV2080_ENGINE_TYPE_OFA0 NV2080_ENGINE_TYPE_OFA +#define NV2080_ENGINE_TYPE_RESERVED34 (0x00000034) +#define NV2080_ENGINE_TYPE_RESERVED35 (0x00000035) +#define NV2080_ENGINE_TYPE_RESERVED36 (0x00000036) +#define NV2080_ENGINE_TYPE_RESERVED37 (0x00000037) +#define NV2080_ENGINE_TYPE_RESERVED38 (0x00000038) +#define NV2080_ENGINE_TYPE_RESERVED39 (0x00000039) +#define NV2080_ENGINE_TYPE_RESERVED3a (0x0000003a) +#define NV2080_ENGINE_TYPE_RESERVED3b (0x0000003b) +#define NV2080_ENGINE_TYPE_RESERVED3c (0x0000003c) +#define NV2080_ENGINE_TYPE_RESERVED3d (0x0000003d) +#define NV2080_ENGINE_TYPE_RESERVED3e (0x0000003e) +#define NV2080_ENGINE_TYPE_LAST (0x0000003f) #define NV2080_ENGINE_TYPE_ALLENGINES (0xffffffff) -#define NV2080_ENGINE_TYPE_COPY_SIZE 10 +// +// NV2080_ENGINE_TYPE_COPY_SIZE is now defined as the maximum possible CE size. +// It does not reflect the max supported NV2080_ENGINE_TYPE_COPY counts. Bug 3713687 #90. +// It needs to use NV2080_ENGINE_TYPE_IS_COPY() to check if a CE is valid when +// the clients try to enumerate all NV2080_ENGINE_TYPE_COPYs. +// +#define NV2080_ENGINE_TYPE_COPY_SIZE 64 + #define NV2080_ENGINE_TYPE_NVENC_SIZE 3 #define NV2080_ENGINE_TYPE_NVJPEG_SIZE 8 #define NV2080_ENGINE_TYPE_NVDEC_SIZE 8 #define NV2080_ENGINE_TYPE_GR_SIZE 8 +#define NV2080_ENGINE_TYPE_OFA_SIZE 1 // Indexed engines #define NV2080_ENGINE_TYPE_COPY(i) (NV2080_ENGINE_TYPE_COPY0+(i)) @@ -325,6 +368,10 @@ extern "C" { #define NV2080_ENGINE_TYPE_IS_GR(i) (((i) >= NV2080_ENGINE_TYPE_GR0) && ((i) < NV2080_ENGINE_TYPE_GR(NV2080_ENGINE_TYPE_GR_SIZE))) #define NV2080_ENGINE_TYPE_GR_IDX(i) ((i) - NV2080_ENGINE_TYPE_GR0) +#define NV2080_ENGINE_TYPE_OFAn(i) ((i == 0) ? (NV2080_ENGINE_TYPE_OFA0) : (NV2080_ENGINE_TYPE_LAST)) +#define NV2080_ENGINE_TYPE_IS_OFA(i) (((i) == NV2080_ENGINE_TYPE_OFA0)) +#define NV2080_ENGINE_TYPE_OFA_IDX(i) ((i == NV2080_ENGINE_TYPE_OFA0) ? (0) : (-1)) + #define NV2080_ENGINE_TYPE_IS_VALID(i) (((i) > (NV2080_ENGINE_TYPE_NULL)) && ((i) < (NV2080_ENGINE_TYPE_LAST))) /* exported client defines */ diff --git a/src/common/sdk/nvidia/inc/class/cl503b.h b/src/common/sdk/nvidia/inc/class/cl503b.h index 79565a19e9..9f157566d4 100644 --- a/src/common/sdk/nvidia/inc/class/cl503b.h +++ b/src/common/sdk/nvidia/inc/class/cl503b.h @@ -37,13 +37,14 @@ #define NV503B_FLAGS_P2P_TYPE_GPA 0 #define NV503B_FLAGS_P2P_TYPE_SPA 1 -/* +/* * NV503B_BAR1_P2P_DMA_INFO * - * The DMA information for BAR1 P2P, it is only valid for BAR1 P2P. - * dma_address will be set to NV_U64_MAX and dma_size will be set to 0 - * when the DMA info is not available. - * + * The DMA information for BAR1 P2P. + * The default value for dma_address is NV_U64_MAX and dma_size is 0. + * This BAR1 P2P DMA information is only valid for the kernel-privileged clients. + * For unprivileged clients, all fields will be the default values. + * */ typedef struct NV503B_BAR1_P2P_DMA_INFO { NV_DECLARE_ALIGNED(NvU64 dma_address, 8); diff --git a/src/common/sdk/nvidia/inc/class/cl90cdvideo.h b/src/common/sdk/nvidia/inc/class/cl90cdvideo.h new file mode 100644 index 0000000000..145e662d4c --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/cl90cdvideo.h @@ -0,0 +1,121 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl90cdvideo_h_ +#define _cl90cdvideo_h_ + +/* This file defines parameters for FECS context switch events*/ + +#define NV_EVENT_BUFFER_VIDEO_VERSION 1 + +#define NV_EVENT_BUFFER_VIDEO_TAG_ENGINE_START 0x00 +#define NV_EVENT_BUFFER_VIDEO_TAG_ENGINE_END 0x01 +#define NV_EVENT_BUFFER_VIDEO_TAG_PSTATE_CHANGE 0x02 +#define NV_EVENT_BUFFER_VIDEO_TAG_LOG_DATA 0x03 +#define NV_EVENT_BUFFER_VIDEO_TAG_LAST NV_EVENT_BUFFER_VIDEO_TAG_LOG_DATA + +#define NV_EVENT_BUFFER_VIDEO_BITMASK_TAG_ENGINE_START NVBIT(NV_EVENT_BUFFER_VIDEO_TAG_ENGINE_START) +#define NV_EVENT_BUFFER_VIDEO_BITMASK_TAG_ENGINE_END NVBIT(NV_EVENT_BUFFER_VIDEO_TAG_ENGINE_END) +#define NV_EVENT_BUFFER_VIDEO_BITMASK_TAG_PSTATE_CHANGE NVBIT(NV_EVENT_BUFFER_VIDEO_TAG_PSTATE_CHANGE) +#define NV_EVENT_BUFFER_VIDEO_BITMASK_TAG_LOG_DATA NVBIT(NV_EVENT_BUFFER_VIDEO_TAG_LOG_DATA) + +/* context_id is set to this value if fecs info doesn't match a known channel/tsg handle*/ +#define NV_EVENT_BUFFER_VIDEO_INVALID_CONTEXT 0xFFFFFFFF + +/* + * PID/context_id are set to these values if the data is from another user's + * client and the current user is not an administrator + */ +#define NV_EVENT_BUFFER_VIDEO_HIDDEN_PID 0x0 +#define NV_EVENT_BUFFER_VIDEO_HIDDEN_CONTEXT 0x0 + +/* + * PID/context_id are set to these values if the data is from a kernel client + * and the data is being read by a user client + */ +#define NV_EVENT_BUFFER_VIDEO_KERNEL_PID 0xFFFFFFFF +#define NV_EVENT_BUFFER_VIDEO_KERNEL_CONTEXT 0xFFFFFFFF + +typedef enum +{ + NV_EVENT_BUFFER_VIDEO_ENGINE_TYPE__NVDEC = 0, + NV_EVENT_BUFFER_VIDEO_ENGINE_TYPE__NVENC, + NV_EVENT_BUFFER_VIDEO_ENGINE_TYPE__NVJPEG, + NV_EVENT_BUFFER_VIDEO_ENGINE_TYPE__OFA, + NV_EVENT_BUFFER_VIDEO_ENGINE_TYPE__LAST = NV_EVENT_BUFFER_VIDEO_ENGINE_TYPE__OFA, +} NV_EVENT_BUFFER_VIDEO_ENGINE_TYPE; + +typedef enum +{ + NV_EVENT_BUFFER_VIDEO_CODEC_ID__MPEG2 = 0, + NV_EVENT_BUFFER_VIDEO_CODEC_ID__VC1, + NV_EVENT_BUFFER_VIDEO_CODEC_ID__H264, + NV_EVENT_BUFFER_VIDEO_CODEC_ID__MPEG4, + NV_EVENT_BUFFER_VIDEO_CODEC_ID__VP8, + NV_EVENT_BUFFER_VIDEO_CODEC_ID__VP9, + NV_EVENT_BUFFER_VIDEO_CODEC_ID__HEVC, + NV_EVENT_BUFFER_VIDEO_CODEC_ID__AVD, + NV_EVENT_BUFFER_VIDEO_CODEC_ID__LAST = NV_EVENT_BUFFER_VIDEO_CODEC_ID__AVD, +} NV_EVENT_BUFFER_VIDEO_ENGINE_CODEC_ID; + +// V1 ------------------------------------------------------------------------ +typedef struct +{ + NvU8 event_id; ///< NV_EVENT_BUFFER_VIDEO_TAG_* + NvU8 vmid; + NvU16 seqno; + NvU32 context_id; ///< channel/tsg handle + NvU64 pid NV_ALIGN_BYTES(8); ///< process id + NvU64 timestamp NV_ALIGN_BYTES(8); + NvU64 api_id NV_ALIGN_BYTES(8); + union + { + NvU64 event_data; + + struct + { + NvU8 engine_type; + NvU8 engine_id; + NvU16 codec_id; + NvU32 status; + } session; + + struct + { + NvU16 from; + NvU16 to; + } stateChange; + + struct + { + NvU8 engine_type; + NvU8 engine_id; + NvU16 codec_id; + NvU32 size; + } logData; + }; +} NV_EVENT_BUFFER_VIDEO_RECORD_V1; + +typedef NV_EVENT_BUFFER_VIDEO_RECORD_V1 NV_EVENT_BUFFER_VIDEO_RECORD; +#endif /* _cl90cdvideo_h_ */ + diff --git a/src/nvidia/inc/kernel/os/os_fixed_mode_timings_props.h b/src/common/sdk/nvidia/inc/class/cl90e7.h similarity index 65% rename from src/nvidia/inc/kernel/os/os_fixed_mode_timings_props.h rename to src/common/sdk/nvidia/inc/class/cl90e7.h index 5b0e989058..3219f131d1 100644 --- a/src/nvidia/inc/kernel/os/os_fixed_mode_timings_props.h +++ b/src/common/sdk/nvidia/inc/class/cl90e7.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,32 +21,18 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef _OS_FIXED_MODE_TIMINGS_PROPS_H_ -#define _OS_FIXED_MODE_TIMINGS_PROPS_H_ +#ifndef _cl90e7_h_ +#define _cl90e7_h_ -#include "gpu/disp/kern_disp_max.h" -#include "nvtypes.h" - -typedef struct -{ - NvU16 hActive; - NvU16 hFrontPorch; - NvU16 hSyncWidth; - NvU16 hBackPorch; +#ifdef __cplusplus +extern "C" { +#endif - NvU16 vActive; - NvU16 vFrontPorch; - NvU16 vSyncWidth; - NvU16 vBackPorch; +#define GF100_SUBDEVICE_INFOROM (0x000090e7) - NvU32 pclkKHz; - NvU32 rrx1k; -} OS_MODE_TIMING; +#ifdef __cplusplus +}; /* extern "C" */ +#endif -typedef struct -{ - OS_MODE_TIMING timingsPerStream[OBJ_MAX_HEADS]; - NvU8 numTimings; -} OS_FIXED_MODE_TIMINGS; +#endif // _cl90e7_h -#endif diff --git a/src/common/sdk/nvidia/inc/class/cla084.h b/src/common/sdk/nvidia/inc/class/cla084.h index 3ba2152cf9..1840257405 100644 --- a/src/common/sdk/nvidia/inc/class/cla084.h +++ b/src/common/sdk/nvidia/inc/class/cla084.h @@ -54,6 +54,7 @@ * numGuestFbHandles -> number of guest memory handles, the client handle is hPluginClient * guestFbHandleList -> handle list to guest memory * hPluginHeapMemory -> plugin heap memory handle, the client handle is hPluginClient + * hMigRmHeapMemory -> MIG-RM heap memory handle * bDeviceProfilingEnabled -> If set to true, profiling is allowed */ #define NVA084_ALLOC_PARAMETERS_MESSAGE_ID (0xa084U) @@ -74,6 +75,7 @@ typedef struct NVA084_ALLOC_PARAMETERS { NvU32 numGuestFbHandles; NvHandle guestFbHandleList[NVA084_MAX_VMMU_SEGMENTS]; NvHandle hPluginHeapMemory; + NvHandle hMigRmHeapMemory; NV_DECLARE_ALIGNED(NvU64 ctrlBuffOffset, 8); NV_DECLARE_ALIGNED(NvU64 initTaskLogBuffOffset, 8); NV_DECLARE_ALIGNED(NvU64 initTaskLogBuffSize, 8); diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h index 6545c7ee8d..6e8cc5b113 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2006-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2006-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -179,5 +179,7 @@ typedef struct NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS { NvBool bDuplicates; /* [out] - Returns true if duplicates */ } NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS; + + /* _ctrl0000client_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h index 021996719a..ec89bb54ae 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h @@ -979,5 +979,53 @@ typedef struct NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS { NvU8 mode; } NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS; +/* + * NV0000_CTRL_GPU_ACTIVE_DEVICE + * + * This structure describes a single MIG or plain device in the system + * available for use. + * + * gpuId + * ID of an attached GPU. + * gpuInstanceId + * MIG gpu instance id of an instance existing on this GPU. + * NV0000_CTRL_GPU_INVALID_ID if the GPU is not in MIG mode. + * computeInstanceId + * MIG compute instance id of an instance existing on this GPU. + * NV0000_CTRL_GPU_INVALID_ID if the GPU is not in MIG mode. + * + */ +typedef struct NV0000_CTRL_GPU_ACTIVE_DEVICE { + NvU32 gpuId; + NvU32 gpuInstanceId; + NvU32 computeInstanceId; +} NV0000_CTRL_GPU_ACTIVE_DEVICE; + +/* + * NV0000_CTRL_CMD_GPU_GET_ACTIVE_DEVICE_IDS + * + * This command returns a list of valid GPUs treating uniformly MIG devices + * and GPUs not in MIG mode. + * + * [out] devices + * List of devices aviable for use. + * [out] numDevices + * Number of valid entries in gpus + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV0000_CTRL_CMD_GPU_GET_ACTIVE_DEVICE_IDS (0x288U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_MAX_ACTIVE_DEVICES 256U + +#define NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS_MESSAGE_ID (0x88U) + +typedef struct NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS { + NvU32 numDevices; + NV0000_CTRL_GPU_ACTIVE_DEVICE devices[NV0000_CTRL_GPU_MAX_ACTIVE_DEVICES]; +} NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS; + /* _ctrl0000gpu_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h index c1ad015ec3..1c9b6d0425 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2005-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -65,14 +65,21 @@ typedef struct NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS { /* Valid feature values */ #define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI 0:0 -#define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_FALSE (0x00000000U) -#define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_TRUE (0x00000001U) +#define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_TRUE (0x00000001U) + #define NV0000_CTRL_SYSTEM_GET_FEATURES_UEFI 1:1 -#define NV0000_CTRL_SYSTEM_GET_FEATURES_UEFI_FALSE (0x00000000U) -#define NV0000_CTRL_SYSTEM_GET_FEATURES_UEFI_TRUE (0x00000001U) +#define NV0000_CTRL_SYSTEM_GET_FEATURES_UEFI_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_FEATURES_UEFI_TRUE (0x00000001U) + #define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT 2:2 -#define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_FALSE (0x00000000U) -#define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_TRUE (0x00000001U) +#define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_TRUE (0x00000001U) + +#define NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING 3:3 +#define NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING_FALSE (0x00000000U) +#define NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING_TRUE (0x00000001U) + /* * NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION * @@ -103,7 +110,7 @@ typedef struct NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS { * NV_ERR_INVALID_PARAM_STRUCT */ -#define NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION (0x101U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION (0x101U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS_MESSAGE_ID" */ #define NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS_MESSAGE_ID (0x1U) @@ -260,6 +267,7 @@ typedef struct NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS { #define NV0000_CTRL_SYSTEM_CPU_TYPE_CELN_M16H (0x00000011U) #define NV0000_CTRL_SYSTEM_CPU_TYPE_CORE2_EXTRM (0x00000012U) #define NV0000_CTRL_SYSTEM_CPU_TYPE_ATOM (0x00000013U) +#define NV0000_CTRL_SYSTEM_CPU_TYPE_XEON_SPR (0x00000014U) /* AMD types */ #define NV0000_CTRL_SYSTEM_CPU_TYPE_K5 (0x00000030U) #define NV0000_CTRL_SYSTEM_CPU_TYPE_K6 (0x00000031U) @@ -432,6 +440,45 @@ typedef struct NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS { NvU32 memorySize; } NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS; +/* + * NV0000_CTRL_CMD_SYSTEM_GET_LOCK_TIMES + * + * This command is used to retrieve the measured times spent holding and waiting for + * the main RM locks (API and GPU). + * + * waitApiLock + * Total time spent by RM API's waiting to acquire the API lock + * + * holdRoApiLock + * Total time spent by RM API's holding the API lock in RO mode. + * + * holdRwApiLock + * Total time spent by RM API's holding the API lock in RW mode. + * + * waitGpuLock + * Total time spent by RM API's waiting to acquire one or more GPU locks. + * + * holdGpuLock + * Total time spent by RM API's holding one or more GPU locks. + * + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0000_CTRL_CMD_SYSTEM_GET_LOCK_TIMES (0x109U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS_MESSAGE_ID (0x9U) + +typedef struct NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS { + NV_DECLARE_ALIGNED(NvU64 waitApiLock, 8); + NV_DECLARE_ALIGNED(NvU64 holdRoApiLock, 8); + NV_DECLARE_ALIGNED(NvU64 holdRwApiLock, 8); + NV_DECLARE_ALIGNED(NvU64 waitGpuLock, 8); + NV_DECLARE_ALIGNED(NvU64 holdGpuLock, 8); +} NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS; + /* * NV0000_CTRL_CMD_SYSTEM_GET_CLASSLIST * @@ -2072,16 +2119,16 @@ typedef struct NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS { NvU32 subFunc; /* Configurable TGP offset, in mW */ - NvU32 ctgpOffsetmW; + NvS32 ctgpOffsetmW; /* TPP, as offset in mW */ - NvU32 targetTppOffsetmW; + NvS32 targetTppOffsetmW; /* Maximum allowed output, as offset in mW */ - NvU32 maxOutputOffsetmW; + NvS32 maxOutputOffsetmW; /* Minimum allowed output, as offset in mW */ - NvU32 minOutputOffsetmW; + NvS32 minOutputOffsetmW; /* The System Controller Table Version */ NvU8 version; diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000unix.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000unix.h index 17c4bdbcfb..9ddc1308b2 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000unix.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000unix.h @@ -225,6 +225,10 @@ typedef struct NV0000_CTRL_OS_GET_GPU_INFO_PARAMS { * NV_MAX_DEVICES is returned if the object is parented by a client instead * of a device. * + * gpuInstanceId + * For objects parented by device this parameter returns MIG GPU instance + * id the device is subscribed to or NV_U32_MAX if no subscription was made. + * * maxObjects * This parameter returns the maximum number of object handles that may be * contained in the file descriptor. @@ -246,9 +250,10 @@ typedef struct NV0000_CTRL_OS_GET_GPU_INFO_PARAMS { #define NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS_MESSAGE_ID (0x8U) typedef struct NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS { - NvS32 fd; /* IN */ + NvS32 fd; /* IN */ NvU32 deviceInstance; /* OUT */ - NvU16 maxObjects; /* OUT */ + NvU32 gpuInstanceId; /* OUT */ + NvU16 maxObjects; /* OUT */ NvU8 metadata[NV0000_OS_UNIX_EXPORT_OBJECT_FD_BUFFER_SIZE]; /* OUT */ } NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS; diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0041.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0041.h index 4ccdb8f636..29e8ef780c 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0041.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0041.h @@ -238,6 +238,12 @@ typedef NVXXXX_CTRL_XXX_INFO NV0041_CTRL_SURFACE_INFO; #define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY_WRITE_PROTECT NVOS32_ATTR_COHERENCY_WRITE_PROTECT #define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY_WRITE_BACK NVOS32_ATTR_COHERENCY_WRITE_BACK +/* Valid surface info format */ +#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_FORMAT NVOS32_ATTR_FORMAT +#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_FORMAT_PITCH NVOS32_ATTR_FORMAT_PITCH +#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_FORMAT_SWIZZLED NVOS32_ATTR_FORMAT_SWIZZLED +#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_FORMAT_BLOCK_LINEAR NVOS32_ATTR_FORMAT_BLOCK_LINEAR + /* * NV0041_CTRL_CMD_GET_SURFACE_INFO * diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h index 7195070e39..63f462763a 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2005-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -107,8 +107,8 @@ * This indicates whether this SOR uses DSI-A, DSI-B or both (ganged mode). * NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE * This indicates whether this DFP supports Dynamic MUX - * flags2 - * This parameter returns the extra information specific to this dfp. + * UHBRSupportedByDfp + * Bitmask to specify the UHBR link rates supported by this dfp. * * Possible status values returned are: * NV_OK @@ -123,7 +123,7 @@ typedef struct NV0073_CTRL_DFP_GET_INFO_PARAMS { NvU32 subDeviceInstance; NvU32 displayId; NvU32 flags; - NvU32 flags2; + NvU32 UHBRSupportedByDfp; } NV0073_CTRL_DFP_GET_INFO_PARAMS; /* valid display types */ @@ -942,6 +942,10 @@ typedef struct NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS_PARAMS { #define NV0073_CTRL_DFP_DISP_MUX_FLAGS_MUX_SWITCH_IGPU_POWER_TIMING 2:2 #define NV0073_CTRL_DFP_DISP_MUX_FLAGS_MUX_SWITCH_IGPU_POWER_TIMING_KNOWN 0x00000000 #define NV0073_CTRL_DFP_DISP_MUX_FLAGS_MUX_SWITCH_IGPU_POWER_TIMING_UNKNOWN 0x00000001 +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SKIP_BACKLIGHT_ENABLE 3:3 +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SKIP_BACKLIGHT_ENABLE_NO 0x00000000U +#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SKIP_BACKLIGHT_ENABLE_YES 0x00000001U + #define NV0073_CTRL_DISP_MUX_BACKLIGHT_BRIGHTNESS_MIN 0U #define NV0073_CTRL_DISP_MUX_BACKLIGHT_BRIGHTNESS_MAX 100U @@ -1231,13 +1235,23 @@ typedef struct NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS { * Pixel clock frequency in KHz * rrx1k (out) * Refresh rate in units of 0.001Hz +* x (out) +* x offset inside superframe at which this view starts + * y (out) +* y offset inside superframe at which this view starts + * width (out) +* Horizontal active width in pixels for this view +* height (out) +* Vertical active height in lines for this view * * Possible status values returned are: * NV_OK * NV_ERR_INVALID_ARGUMENT * NV_ERR_NOT_SUPPORTED */ -#define NV0073_CTRL_CMD_DFP_GET_FIXED_MODE_TIMING (0x731172) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8 | NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS_MESSAGE_ID)" */ +#define NV0073_CTRL_CMD_DFP_GET_FIXED_MODE_TIMING (0x731172) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8 | NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS_MESSAGE_ID)" */ + +#define NV0073_CTRL_DFP_FIXED_MODE_TIMING_MAX_SUPERFRAME_VIEWS 4U #define NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS_MESSAGE_ID (0x72U) @@ -1260,6 +1274,18 @@ typedef struct NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS { NvU32 pclkKHz; NvU32 rrx1k; + + struct { + NvU8 numViews; + struct { + NvU16 x; + NvU16 y; + NvU16 width; + NvU16 height; + } view[NV0073_CTRL_DFP_FIXED_MODE_TIMING_MAX_SUPERFRAME_VIEWS]; + } superframeInfo; } NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS; + + /* _ctrl0073dfp_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h index 441b2721f9..8f3f292173 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2005-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -1394,6 +1394,12 @@ typedef struct NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID_PARAMS { * linkBW * The BW of each lane that the DP transmitter hardware is set up to drive. * The values returned will be according to the DP specifications. + * dp2LinkBW + * Current BW of each lane that the DP transmitter hardware is set up to drive is UHBR. + * The values returned will be using 10M convention. + * + * Note: + * linkBW and dp2LinkBw are mutual exclusive. Only one of the value will be non-zero. * */ #define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG (0x731360U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_GET_LINK_CONFIG_PARAMS_MESSAGE_ID" */ @@ -1405,16 +1411,37 @@ typedef struct NV0073_CTRL_DP_GET_LINK_CONFIG_PARAMS { NvU32 displayId; NvU32 laneCount; NvU32 linkBW; + NvU32 dp2LinkBW; } NV0073_CTRL_DP_GET_LINK_CONFIG_PARAMS; #define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LANE_COUNT 3:0 -#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LANE_COUNT_0 (0x00000000U) -#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LANE_COUNT_1 (0x00000001U) -#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LANE_COUNT_2 (0x00000002U) -#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LANE_COUNT_4 (0x00000004U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LANE_COUNT_0 (0x00000000U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LANE_COUNT_1 (0x00000001U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LANE_COUNT_2 (0x00000002U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LANE_COUNT_4 (0x00000004U) #define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LINK_BW 3:0 -#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LINK_BW_1_62GBPS (0x00000006U) -#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LINK_BW_2_70GBPS (0x0000000aU) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LINK_BW_1_62GBPS (0x00000006U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LINK_BW_2_70GBPS (0x0000000aU) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LINK_BW_5_40GBPS (0x00000014U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LINK_BW_8_10GBPS (0x0000001EU) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LINK_BW_2_16GBPS (0x00000008U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LINK_BW_2_43GBPS (0x00000009U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LINK_BW_3_24GBPS (0x0000000CU) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LINK_BW_4_32GBPS (0x00000010U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LINK_BW_6_75GBPS (0x00000019U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW 15:0 +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_1_62GBPS (0x000000A2U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_2_70GBPS (0x0000010EU) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_5_40GBPS (0x0000021CU) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_8_10GBPS (0x0000032AU) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_2_16GBPS (0x000000D8U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_2_43GBPS (0x000000F3U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_3_24GBPS (0x00000114U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_4_32GBPS (0x000001B0U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_6_75GBPS (0x000002A3U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_10_0GBPS (0x000003E8U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_13_5GBPS (0x00000546U) +#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_20_0GBPS (0x000007D0U) /* * NV0073_CTRL_CMD_DP_GET_EDP_DATA @@ -1455,7 +1482,7 @@ typedef struct NV0073_CTRL_DP_GET_LINK_CONFIG_PARAMS { * NV0073_CTRL_DP_GET_EDP_DATA_DPCD_SET_POWER_D3 * This eDP panel is current standby. */ -#define NV0073_CTRL_CMD_DP_GET_EDP_DATA (0x731361U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_GET_EDP_DATA_PARAMS_MESSAGE_ID" */ +#define NV0073_CTRL_CMD_DP_GET_EDP_DATA (0x731361U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_GET_EDP_DATA_PARAMS_MESSAGE_ID" */ #define NV0073_CTRL_DP_GET_EDP_DATA_PARAMS_MESSAGE_ID (0x61U) @@ -1751,6 +1778,8 @@ typedef struct NV0073_CTRL_CMD_DP_SEND_ACT_PARAMS { * Specifies the SOR index. * dpVersionsSupported * Specified the DP versions supported by the GPU + * UHBRSupportedByGpu + * Bitmask to specify the UHBR link rates supported by the GPU. * bIsMultistreamSupported * Returns NV_TRUE if MST is supported by the GPU else NV_FALSE * bIsSCEnabled @@ -1787,7 +1816,7 @@ typedef struct NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS { NvU32 sorIndex; NvU32 maxLinkRate; NvU32 dpVersionsSupported; - NvU32 UHBRSupported; + NvU32 UHBRSupportedByGpu; NvBool bIsMultistreamSupported; NvBool bIsSCEnabled; NvBool bHasIncreasedWatermarkLimits; @@ -2212,7 +2241,7 @@ typedef struct NV0073_CTRL_CMD_DP_GET_AUXLOGGER_BUFFER_DATA_PARAMS { * linkRateTbl * Link rates in 200KHz as native granularity from eDP 1.4 * linkBwTbl - * Link rates in 270MHz and valid for client to apply to + * Link rates valid for client to apply to * linkBwCount * Total valid link rates * @@ -2235,7 +2264,7 @@ typedef struct NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES_PARAMS { NvU16 linkRateTbl[NV0073_CTRL_DP_MAX_INDEXED_LINK_RATES]; // Out - NvU8 linkBwTbl[NV0073_CTRL_DP_MAX_INDEXED_LINK_RATES]; + NvU16 linkBwTbl[NV0073_CTRL_DP_MAX_INDEXED_LINK_RATES]; NvU8 linkBwCount; } NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES_PARAMS; @@ -2786,4 +2815,245 @@ typedef struct NV0073_CTRL_DP_EXECUTE_OVERDRIVE_POLICY_PARAMS { NvU16 manfId; NvU16 prodId; } NV0073_CTRL_DP_EXECUTE_OVERDRIVE_POLICY_PARAMS; + +/* + * NV0073_CTRL_CMD_DP2X_LINK_TRAINING_CTRL + * + * This command is used to trigger link training on DP2.x device with 128b132b channel encoding. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior. + * + * displayId + * This parameter specifies the ID of the display for which the dfp + * caps should be returned. The display ID must a dfp display. + * If more than one displayId bit is set or the displayId is not a dfp, + * this call will return NV_ERR_INVALID_ARGUMENT. + * + * cmd + * This parameter is an input to this command. + * Here are the current defined fields: + * 1.Ask RM to enter specific stage + * NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SETTING + * NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SET_CHNL_EQ + * _CDS + * _SET_* only valid if _SETTING_TRUE + * + * 2.Ask RM to check the completion of specific stage + * NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLLING + * NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLL_CHNL_EQ_DONE + * _CHNL_EQ_INTERLANE_ALIGN + * _CDS + * _POLL_* only valid if _POLLING_TRUE + * + * _SETTING_TRUE and _POLLING_TRUE are mutual exclusive. + * RM will return NV_ERR_INVALID_ARGUMENT if both bit are set. + * + * 3.Downspread configuration + * NV0073_CTRL_DP2X_CMD_FORCED_DOWNSPREAD + * Specifies whether RM should be forced to enable or disable the DP + * Downspread setting. This can be used along with the Fake link + * training option so that we can configure the GPU to enable/disable + * spread when a real display is not connected. + * + * NV0073_CTRL_DP2X_CMD_FORCED_DOWNSPREAD_NO (default behavior) + * RM will enable Downspread when the display supports it. + * NV0073_CTRL_DP2X_CMD_FORCED_DOWNSPREAD_YES + * RM will enable/disable Downspread according to _SET_DOWNSPREAD field. + * + * NV0073_CTRL_DP2X_CMD_SET_DOWNSPREAD + * Specifies if RM should enable or disable downspread. + * Only valid when _FORCED_DOWNSPREAD is set to _YES + * + * NV0073_CTRL_DP2X_CMD_SET_DOWNSPREAD_ENABLE + * RM will enable Downspread even if the display does not support it. + * NV0073_CTRL_DP2X_CMD_SET_DOWNSPREAD_DISABLE + * RM will not enable Downspread even if the display does support it. + * + * 4.NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING + * This field specifies if fake link training is to be done. This will + * program enough of the hardware to avoid any hardware hangs and + * depending upon option chosen by the client, OR will be enabled for + * transmisssion. + * + * NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING_NO + * No Fake LT will be performed + * NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING_DONOT_TOGGLE_TRANSMISSION + * SOR will be not powered up during Fake LT + * NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING_TOGGLE_TRANSMISSION_ON + * SOR will be powered up during Fake LT + * + * 5.NV0073_CTRL_DP2X_CMD_FALLBACK_CONFIG + * + * 6.NV0073_CTRL_DP2X_CMD_SKIP_HW_PROGRAMMING + * Specifies whether RM should skip HW training of the link. + * If this is the case then RM only updates its SW state without actually + * touching any HW registers. Clients should use this ONLY if it has determined - + * a. link is trained and not lost + * b. desired link config is same as current trained link config + * c. link is not in D3 (should be in D0) + * + * NV0073_CTRL_DP2X_CMD_SKIP_HW_PROGRAMMING_NO + * RM doesn't skip HW LT as the current Link Config is not the same as the + * requested Link Config. + * NV0073_CTRL_DP2X_CMD_SKIP_HW_PROGRAMMING_YES + * RM skips HW LT and only updates its SW state as client has determined that + * the current state of the link and the requested Link Config is the same. + * data + * This parameter is an input and output to this command. + * Here are the current defined fields: + * NV0073_CTRL_DP2X_DATA_LANE_COUNT + * Valid values: 0, 1, 2, 4 + * NV0073_CTRL_DP2X_DATA_LINK_BW + * Valid values: all standard link rates defined in DP2.x and ILRs defined in eDP spec. + * + * pollingInfo + * This parameter is an output to this command. + * Here are the current defined fields: + * + * NV0073_CTRL_DP2X_POLLING_INFO_CHNL_EQ_INTERVAL + * For Channel equalization, the polling interval is defined in DPCD 0x2216. + * RM report to DPLib when _SET_STAGE is set to _CHNL_EQ. + * (For CDS stage, the polling interval is fixed at 3ms.) + * + * NV0073_CTRL_DP2X_POLLING_INFO_RESULT + * _DONE: if the specified stage is done. + * _PENDING: if the specified stage is still pending. + * + * err + * This parameter specifies provides info regarding the outcome + * of this calling control call. If zero, no errors were found. + * Otherwise, this parameter will specify the error detected. + * The valid parameter is broken down as follows: + * NV0073_CTRL_DP2X_ERR_CHANNEL_EQ_DONE + * If set to _ERR, link training failed at channel equalization phase. + * NV0073_CTRL_DP2X_ERR_CDS_DONE + * If set to _ERR, link training failed at CDS phase. + * NV0073_CTRL_DP2X_ERR_TIMEOUT + * If set to _ERR, link training failed because of timeout. + * NV0073_CTRL_DP2X_ERR_LT_FAILED + * If set to _ERR, link training failed. + * NV0073_CTRL_DP2X_ERR_INVALID_PARAMETER + * If set to _ERR, link configuration or displayID is invalid. + * NV0073_CTRL_DP2X_ERR_SET_LANE_COUNT + * If set to _ERR, link training failed when setting lane count. + * NV0073_CTRL_DP2X_ERR_SET_LINK_BW + * If set to _ERR, link training failed when setting link rate. + * NV0073_CTRL_DP2X_ERR_ENABLE_FEC + * If set to _ERR, link training failed when enabling FEC. + * NV0073_CTRL_DP2X_ERR_CONFIG_LTTPR + * If set to _ERR, link training failed when setting LTTPR. + * NV0073_CTRL_DP2X_ERR_PRE_LT + * If set to _ERR, link training failed before link training start. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NVOS_STATUS_ERROR + */ + +#define NV0073_CTRL_CMD_DP2X_LINK_TRAINING_CTRL (0x731383U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP2X_LINK_TRAINING_CTRL_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_DP2X_LINK_TRAINING_CTRL_PARAMS_MESSAGE_ID (0x83U) + +typedef struct NV0073_CTRL_CMD_DP2X_LINK_TRAINING_CTRL_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 cmd; + NvU32 data; + NvU32 pollingInfo; + NvU32 err; +} NV0073_CTRL_CMD_DP2X_LINK_TRAINING_CTRL_PARAMS; + +#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SETTING 0:0 +#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SETTING_FALSE (0x00000000U) +#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SETTING_TRUE (0x00000001U) +#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SET 1:1 +#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SET_CHNL_EQ (0x00000000U) +#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SET_CDS (0x00000001U) +#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLLING 8:8 +#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLLING_FALSE (0x00000000U) +#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLLING_TRUE (0x00000001U) +#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLL 10:9 +#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLL_CHNL_EQ_DONE (0x00000000U) +#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLL_CHNL_EQ_INTERLANE_ALIGN (0x00000001U) +#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLL_CDS (0x00000002U) + +// Flags for link training. +#define NV0073_CTRL_DP2X_CMD_FORCED_DOWNSPREAD 16:16 +#define NV0073_CTRL_DP2X_CMD_FORCED_DOWNSPREAD_NO (0x00000000U) +#define NV0073_CTRL_DP2X_CMD_FORCED_DOWNSPREAD_YES (0x00000001U) +#define NV0073_CTRL_DP2X_CMD_SET_DOWNSPREAD 17:17 +#define NV0073_CTRL_DP2X_CMD_SET_DOWNSPREAD_DISABLE (0x00000000U) +#define NV0073_CTRL_DP2X_CMD_SET_DOWNSPREAD_ENABLE (0x00000001U) +#define NV0073_CTRL_DP2X_CMD_SKIP_HW_PROGRAMMING 18:18 +#define NV0073_CTRL_DP2X_CMD_SKIP_HW_PROGRAMMING_NO (0x00000000U) +#define NV0073_CTRL_DP2X_CMD_SKIP_HW_PROGRAMMING_YES (0x00000001U) +#define NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING 20:19 +#define NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING_NO (0x00000000U) +#define NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING_DONOT_TOGGLE_TRANSMISSION (0x00000001U) +#define NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING_TOGGLE_TRANSMISSION_ON (0x00000002U) +#define NV0073_CTRL_DP2X_CMD_FALLBACK_CONFIG 21:21 +#define NV0073_CTRL_DP2X_CMD_FALLBACK_CONFIG_FALSE (0x00000000U) +#define NV0073_CTRL_DP2X_CMD_FALLBACK_CONFIG_TRUE (0x00000001U) + +// Basic Data for Link training: Lane count and bandwidth. +#define NV0073_CTRL_DP2X_DATA_LANE_COUNT 3:0 +#define NV0073_CTRL_DP2X_DATA_LANE_COUNT_0 (0x00000000U) +#define NV0073_CTRL_DP2X_DATA_LANE_COUNT_1 (0x00000001U) +#define NV0073_CTRL_DP2X_DATA_LANE_COUNT_2 (0x00000002U) +#define NV0073_CTRL_DP2X_DATA_LANE_COUNT_4 (0x00000004U) +#define NV0073_CTRL_DP2X_DATA_LINK_BW 7:4 +#define NV0073_CTRL_DP2X_DATA_LINK_BW_1_62GBPS (0x00000001U) +#define NV0073_CTRL_DP2X_DATA_LINK_BW_2_16GBPS (0x00000002U) +#define NV0073_CTRL_DP2X_DATA_LINK_BW_2_43GBPS (0x00000003U) +#define NV0073_CTRL_DP2X_DATA_LINK_BW_2_70GBPS (0x00000004U) +#define NV0073_CTRL_DP2X_DATA_LINK_BW_3_24GBPS (0x00000005U) +#define NV0073_CTRL_DP2X_DATA_LINK_BW_4_32GBPS (0x00000006U) +#define NV0073_CTRL_DP2X_DATA_LINK_BW_5_40GBPS (0x00000007U) +#define NV0073_CTRL_DP2X_DATA_LINK_BW_6_75GBPS (0x00000008U) +#define NV0073_CTRL_DP2X_DATA_LINK_BW_8_10GBPS (0x00000009U) +#define NV0073_CTRL_DP2X_DATA_LINK_BW_UHBR10_0 (0x0000000AU) +#define NV0073_CTRL_DP2X_DATA_LINK_BW_UHBR13_5 (0x0000000BU) +#define NV0073_CTRL_DP2X_DATA_LINK_BW_UHBR20_0 (0x0000000CU) + +#define NV0073_CTRL_DP2X_ERR_CHANNEL_EQ 0:0 +#define NV0073_CTRL_DP2X_ERR_CHANNEL_EQ_DONE (0x00000000U) +#define NV0073_CTRL_DP2X_ERR_CHANNEL_EQ_FAILED (0x00000001U) +#define NV0073_CTRL_DP2X_ERR_CDS 1:1 +#define NV0073_CTRL_DP2X_ERR_CDS_DONE (0x00000000U) +#define NV0073_CTRL_DP2X_ERR_CDS_FAILED (0x00000001U) +#define NV0073_CTRL_DP2X_ERR_TIMEOUT 2:2 +#define NV0073_CTRL_DP2X_ERR_TIMEOUT_NO (0x00000000U) +#define NV0073_CTRL_DP2X_ERR_TIMEOUT_YES (0x00000001U) +#define NV0073_CTRL_DP2X_ERR_LT_FAILED 3:3 +#define NV0073_CTRL_DP2X_ERR_LT_FAILED_NO (0x00000000U) +#define NV0073_CTRL_DP2X_ERR_LT_FAILED_YES (0x00000001U) +#define NV0073_CTRL_DP2X_ERR_INVALID_PARAMETER 4:4 +#define NV0073_CTRL_DP2X_ERR_INVALID_PARAMETER_NOERR (0x00000000U) +#define NV0073_CTRL_DP2X_ERR_INVALID_PARAMETER_ERR (0x00000001U) +#define NV0073_CTRL_DP2X_ERR_SET_LANE_COUNT 5:5 +#define NV0073_CTRL_DP2X_ERR_SET_LANE_COUNT_NOERR (0x00000000U) +#define NV0073_CTRL_DP2X_ERR_SET_LANE_COUNT_ERR (0x00000001U) +#define NV0073_CTRL_DP2X_ERR_SET_LINK_BW 6:6 +#define NV0073_CTRL_DP2X_ERR_SET_LINK_BW_NOERR (0x00000000U) +#define NV0073_CTRL_DP2X_ERR_SET_LINK_BW_ERR (0x00000001U) +#define NV0073_CTRL_DP2X_ERR_ENABLE_FEC 7:7 +#define NV0073_CTRL_DP2X_ERR_ENABLE_FEC_NOERR (0x00000000U) +#define NV0073_CTRL_DP2X_ERR_ENABLE_FEC_ERR (0x00000001U) +#define NV0073_CTRL_DP2X_ERR_CONFIG_LTTPR 8:8 +#define NV0073_CTRL_DP2X_ERR_CONFIG_LTTPR_NOERR (0x00000000U) +#define NV0073_CTRL_DP2X_ERR_CONFIG_LTTPR_ERR (0x00000001U) +#define NV0073_CTRL_DP2X_ERR_PRE_LT 9:9 +#define NV0073_CTRL_DP2X_ERR_PRE_LT_NOERR (0x00000000U) +#define NV0073_CTRL_DP2X_ERR_PRE_LT_ERR (0x00000001U) + +#define NV0073_CTRL_DP2X_POLLING_INFO_CHNL_EQ_INTERVAL 7:0 +#define NV0073_CTRL_DP2X_POLLING_INFO_RESULT 31:31 +#define NV0073_CTRL_DP2X_POLLING_INFO_RESULT_PENDING (0x00000001U) +#define NV0073_CTRL_DP2X_POLLING_INFO_RESULT_DONE (0x00000000U) /* _ctrl0073dp_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h index 00698b7da6..4bcf0bee89 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h @@ -1164,7 +1164,12 @@ typedef struct NV0073_CTRL_SPECIFIC_OR_GET_INFO_PARAMS { * The backlight brightness in the range [0,100], inclusive. This * is an input for SET_BACKLIGHT_BRIGHTNESS, and an output for * GET_BACKLIGHT_BRIGHTNESS. - * + * brightnessType + * This can take in one of the three parameters: + * NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_TYPE_PERCENT100(for percentage brightness with value calibrated to 100 scale), + * NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_TYPE_PERCENT1000(for percentage brightness with uncalibrated values), + * NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_TYPE_NITS(used when panel supports Nits based) + * based on the brightness control method to be used. * * Possible status values returned include: * NV_OK @@ -1180,7 +1185,11 @@ typedef struct NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS { NvU32 displayId; NvU32 brightness; NvBool bUncalibrated; + NvU8 brightnessType; } NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS; +#define NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_TYPE_PERCENT100 1 +#define NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_TYPE_PERCENT1000 2 +#define NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_TYPE_NITS 3 #define NV0073_CTRL_SPECIFIC_GET_BACKLIGHT_BRIGHTNESS_PARAMS_MESSAGE_ID (0x91U) diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h index bd3c3ac52c..91c9a50f78 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2005-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h index f68cd2912a..48fb1e0502 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h @@ -162,6 +162,7 @@ typedef struct NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS { NvU32 backingStoreCbcBase; NvU32 comptaglineAllocationPolicy; NV_DECLARE_ALIGNED(NvU64 privRegionStartOffset, 8); + NvU32 cbcCoveragePerSlice; } NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS; #define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_UNKNOWN 0 // ADDR_UNKNOWN diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h index 58f964e667..a115499697 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h @@ -465,7 +465,10 @@ typedef struct NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS { * bClientRmAllocatedCtxBuffer * Flag for whether engine ctx buffer is managed by client RM. * - * Possible status values returned are: + * bNonPowerOf2ChannelCountSupported + * Flag for whether non power of 2 VF channels are supported. + * +* Possible status values returned are: * NV_OK * NV_ERR_NOT_SUPPORTED */ @@ -490,6 +493,7 @@ typedef struct NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS { NvBool bSriovHeavyEnabled; NvBool bEmulateVFBar0TlbInvalidationRegister; NvBool bClientRmAllocatedCtxBuffer; + NvBool bNonPowerOf2ChannelCountSupported; } NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS; diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h index 4427b2c07c..c15b4aaccc 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h @@ -153,13 +153,16 @@ typedef NVXXXX_CTRL_XXX_INFO NV0080_CTRL_GR_INFO; #define NV0080_CTRL_GR_INFO_INDEX_DUMMY (0x00000033) #define NV0080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES (0x00000034) +#define NV0080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES (0x00000035) +#define NV0080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS (0x00000036) +#define NV0080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG (0x00000037) /* When adding a new INDEX, please update MAX_SIZE accordingly * NOTE: 0080 functionality is merged with 2080 functionality, so this max size * reflects that. */ -#define NV0080_CTRL_GR_INFO_INDEX_MAX (0x00000034) -#define NV0080_CTRL_GR_INFO_MAX_SIZE (0x35) /* finn: Evaluated from "(NV0080_CTRL_GR_INFO_INDEX_MAX + 1)" */ +#define NV0080_CTRL_GR_INFO_INDEX_MAX (0x00000037) +#define NV0080_CTRL_GR_INFO_MAX_SIZE (0x38) /* finn: Evaluated from "(NV0080_CTRL_GR_INFO_INDEX_MAX + 1)" */ /* * NV0080_CTRL_CMD_GR_GET_INFO diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl00de.h b/src/common/sdk/nvidia/inc/ctrl/ctrl00de.h new file mode 100644 index 0000000000..856941944c --- /dev/null +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl00de.h @@ -0,0 +1,57 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl00de.finn +// + +#include "ctrl/ctrlxxxx.h" + +#define NV00DE_CTRL_CMD(cat, idx) NVXXXX_CTRL_CMD(0x00de, NV00DE_CTRL_##cat, idx) + +/* RM_USER_SHARED_DATA control commands and parameters */ + +/* + * NV00DE_CTRL_CMD_REQUEST_DATA_POLL + * + * @brief Request some polled data elements to be updated + * + * @param[in] polledDataMask Bitmask of data to be updated + * + * @return NV_OK on success + * @return NV_ERR_ otherwise + */ +#define NV00DE_CTRL_CMD_REQUEST_DATA_POLL (0xde0001U) /* finn: Evaluated from "(FINN_RM_USER_SHARED_DATA_INTERFACE_ID << 8) | NV00DE_CTRL_REQUEST_DATA_POLL_PARAMS_MESSAGE_ID" */ + +#define NV00DE_CTRL_REQUEST_DATA_POLL_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV00DE_CTRL_REQUEST_DATA_POLL_PARAMS { + NV_DECLARE_ALIGNED(NvU64 polledDataMask, 8); +} NV00DE_CTRL_REQUEST_DATA_POLL_PARAMS; + +/* _ctrl00de.h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl00f8.h b/src/common/sdk/nvidia/inc/ctrl/ctrl00f8.h index ed4595b40d..240593aeca 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl00f8.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl00f8.h @@ -112,20 +112,54 @@ typedef struct NV00F8_CTRL_GET_INFO_PARAMS { * numPfns [OUT] * Number of valid entries in pfnArray. * - * Note: This ctrl call is only available for kerenl mode client in vGPU platforms. + * attrs [OUT] + * Attributes associated with memory allocation. + * + * physAttrs [OUT] + * Physical attributes associated with memory allocation. + * For flexible mappings, it is not possible to retrieve this information, + * behavior is undefined (returns all zeros). + * + * memFlags [OUT] + * Flags associated with memory allocation. + * + * Note: This control call is only available for privileged clients. */ #define NV00F8_CTRL_CMD_DESCRIBE (0xf80102) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00F8_CTRL_DESCRIBE_PARAMS_MESSAGE_ID" */ #define NV00F8_CTRL_DESCRIBE_PFN_ARRAY_SIZE 512 +/* + * kind + * Kind of memory allocation. + * + * pageSize + * Page size of memory allocation. + * + * size + * Size of memory allocation + * + * cliqueId + * Clique ID of the owner GPU + */ +typedef struct NV_FABRIC_MEMORY_ATTRS { + NvU32 kind; + NV_DECLARE_ALIGNED(NvU64 pageSize, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); + NvU32 cliqueId; +} NV_FABRIC_MEMORY_ATTRS; + #define NV00F8_CTRL_DESCRIBE_PARAMS_MESSAGE_ID (0x2U) typedef struct NV00F8_CTRL_DESCRIBE_PARAMS { NV_DECLARE_ALIGNED(NvU64 offset, 8); NV_DECLARE_ALIGNED(NvU64 totalPfns, 8); - NvU32 pfnArray[NV00F8_CTRL_DESCRIBE_PFN_ARRAY_SIZE]; - NvU32 numPfns; + NvU32 pfnArray[NV00F8_CTRL_DESCRIBE_PFN_ARRAY_SIZE]; + NvU32 numPfns; + NV_DECLARE_ALIGNED(NV_FABRIC_MEMORY_ATTRS attrs, 8); + NV_PHYSICAL_MEMORY_ATTRS physAttrs; + NvU32 memFlags; } NV00F8_CTRL_DESCRIBE_PARAMS; /* diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl00fd.h b/src/common/sdk/nvidia/inc/ctrl/ctrl00fd.h index d284fe041b..6a9f746c2d 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl00fd.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl00fd.h @@ -202,4 +202,6 @@ typedef struct NV00FD_CTRL_DETACH_MEM_PARAMS { NvU32 flags; } NV00FD_CTRL_DETACH_MEM_PARAMS; + + /* _ctrl00fd_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080.h index f7f8d6f934..1dfcf4db24 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080.h @@ -78,7 +78,8 @@ #include "ctrl2080/ctrl2080grmgr.h" -#include "ctrl2080/ctrl2080ucodefuzzer.h" + + #include "ctrl2080/ctrl2080vgpumgrinternal.h" #include "ctrl2080/ctrl2080hshub.h" /* include appropriate os-specific command header */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h index c7c7391bc5..f3ef290b3a 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h @@ -1467,44 +1467,6 @@ typedef struct NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS { NvBool bDisable; } NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS; -/* - * NV2080_CTRL_CMD_BUS_GET_C2C_ERR_INFO - * - * This command returns the C2C error info for a C2C links. - * - * errCnts[OUT] - * Array of structure that contains the error counts for - * number of times one of C2C fatal error interrupt has happened. - * The array size should be NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_NUM_C2C_INSTANCES - * * NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_C2C_LINKS_PER_INSTANCE. - * - * nrCrcErrIntr[OUT] - * Number of times CRC error interrupt triggered. - * nrReplayErrIntr[OUT] - * Number of times REPLAY error interrupt triggered. - * nrReplayB2bErrIntr[OUT] - * Number of times REPLAY_B2B error interrupt triggered. - * - * Possible status values returned are: - * NV_OK - * NV_ERR_INVALID_STATE - * NV_ERR_NOT_SUPPORTED - */ - -#define NV2080_CTRL_CMD_BUS_GET_C2C_ERR_INFO (0x2080182d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS_MESSAGE_ID" */ - -#define NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_NUM_C2C_INSTANCES 2 -#define NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_C2C_LINKS_PER_INSTANCE 5 - -#define NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS_MESSAGE_ID (0x2DU) - -typedef struct NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS { - struct { - NvU32 nrCrcErrIntr; - NvU32 nrReplayErrIntr; - NvU32 nrReplayB2bErrIntr; - } errCnts[NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_NUM_C2C_INSTANCES * NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_C2C_LINKS_PER_INSTANCE]; -} NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS; /* diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h index bf7d9fcbbb..f6890bb63e 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h @@ -186,7 +186,7 @@ typedef struct NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS { #define NV2080_CTRL_CMD_CE_SET_PCE_LCE_CONFIG (0x20802a04) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_MAX_PCES 32 -#define NV2080_CTRL_MAX_GRCES 2 +#define NV2080_CTRL_MAX_GRCES 4 #define NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS_MESSAGE_ID (0x4U) @@ -323,11 +323,13 @@ typedef struct NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS { #define NV2080_CTRL_CMD_CE_GET_ALL_CAPS (0x20802a0a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_MAX_CES 64 + #define NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_MESSAGE_ID (0xaU) typedef struct NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS { - NvU8 capsTbl[NV2080_CTRL_MAX_PCES][NV2080_CTRL_CE_CAPS_TBL_SIZE]; - NvU32 present; + NvU8 capsTbl[NV2080_CTRL_MAX_CES][NV2080_CTRL_CE_CAPS_TBL_SIZE]; + NV_DECLARE_ALIGNED(NvU64 present, 8); } NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS; #define NV2080_CTRL_CMD_CE_GET_ALL_PHYSICAL_CAPS (0x20802a0b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_ALL_PHYSICAL_CAPS_PARAMS_MESSAGE_ID" */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h index 2664849f46..c4558761a2 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2006-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2006-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -266,6 +266,8 @@ * NV2080_CTRL_FB_INFO_INDEX_ECC_STATUS_SIZE * Returns the ECC status size (corresponds to subpartitions or channels * depending on architecture/memory type). + * NV2080_CTRL_FB_INFO_INDEX_IS_ZERO_FB + * Returns true if FB is not present on this chip */ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_FB_INFO; @@ -328,9 +330,10 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_FB_INFO; #define NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_TOTAL_KB (0x00000033U) #define NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_FREE_KB (0x00000034U) #define NV2080_CTRL_FB_INFO_INDEX_ECC_STATUS_SIZE (0x00000035U) -#define NV2080_CTRL_FB_INFO_MAX_LIST_SIZE (0x00000036U) +#define NV2080_CTRL_FB_INFO_INDEX_IS_ZERO_FB (0x00000036U) +#define NV2080_CTRL_FB_INFO_MAX_LIST_SIZE (0x00000037U) -#define NV2080_CTRL_FB_INFO_INDEX_MAX (0x35U) /* finn: Evaluated from "(NV2080_CTRL_FB_INFO_MAX_LIST_SIZE - 1)" */ +#define NV2080_CTRL_FB_INFO_INDEX_MAX (0x36U) /* finn: Evaluated from "(NV2080_CTRL_FB_INFO_MAX_LIST_SIZE - 1)" */ /* valid fb RAM type values */ #define NV2080_CTRL_FB_INFO_RAM_TYPE_UNKNOWN (0x00000000U) @@ -2328,7 +2331,7 @@ typedef struct NV2080_CTRL_FB_FS_INFO_QUERY { } NV2080_CTRL_FB_FS_INFO_QUERY; // Max number of queries that can be batched in a single call to NV2080_CTRL_CMD_FB_GET_FS_INFO -#define NV2080_CTRL_FB_FS_INFO_MAX_QUERIES 96U +#define NV2080_CTRL_FB_FS_INFO_MAX_QUERIES 120U #define NV2080_CTRL_FB_GET_FS_INFO_PARAMS_MESSAGE_ID (0x46U) @@ -2651,4 +2654,58 @@ typedef struct NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS { NvU32 caps; } NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS; +typedef struct NV2080_CTRL_CMD_FB_STATS_ENTRY { + //! Total physical memory available (accounts row-remapping) + NV_DECLARE_ALIGNED(NvU64 totalSize, 8); + + //! Total reserved memory (includes both Region 1 and region 2) + NV_DECLARE_ALIGNED(NvU64 rsvdSize, 8); + + //! Total usable memory (Region 0) for OS/KMD + NV_DECLARE_ALIGNED(NvU64 osSize, 8); + + //! Region 1 (RM Internal) memory + NV_DECLARE_ALIGNED(NvU64 r1Size, 8); + + //! Region 2 (Reserved) memory + NV_DECLARE_ALIGNED(NvU64 r2Size, 8); + + //! Free memory (reserved but not allocated) + NV_DECLARE_ALIGNED(NvU64 freeSize, 8); +} NV2080_CTRL_CMD_FB_STATS_ENTRY; + +typedef struct NV2080_CTRL_CMD_FB_STATS_OWNER_INFO { + //! Total allocated size for this owner + NV_DECLARE_ALIGNED(NvU64 allocSize, 8); + + //! Total memory blocks belonging this owner + NvU32 numBlocks; + + //! Total reserved size for this owner + NV_DECLARE_ALIGNED(NvU64 rsvdSize, 8); +} NV2080_CTRL_CMD_FB_STATS_OWNER_INFO; + +#define NV2080_CTRL_CMD_FB_STATS_MAX_OWNER 200U + +/* + * NV2080_CTRL_CMD_FB_STATS_GET + * + * Get the FB allocations info. + */ +#define NV2080_CTRL_CMD_FB_STATS_GET (0x2080132a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_STATS_GET_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_FB_STATS_GET_PARAMS_MESSAGE_ID (0x2AU) + +typedef struct NV2080_CTRL_CMD_FB_STATS_GET_PARAMS { + + //! Version id for driver and tool matching + NV_DECLARE_ALIGNED(NvU64 version, 8); + + //! All sizes info + NV_DECLARE_ALIGNED(NV2080_CTRL_CMD_FB_STATS_ENTRY fbSizeInfo, 8); + + //! Level 2 owner info table + NV_DECLARE_ALIGNED(NV2080_CTRL_CMD_FB_STATS_OWNER_INFO fbBlockInfo[NV2080_CTRL_CMD_FB_STATS_MAX_OWNER], 8); +} NV2080_CTRL_CMD_FB_STATS_GET_PARAMS; + /* _ctrl2080fb_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h index a56b72c7bf..79838bfb5e 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h @@ -35,7 +35,7 @@ #include "nvcfg_sdk.h" #include "nvstatus.h" -#define NV_GRID_LICENSE_INFO_MAX_LENGTH (128) +#define NV_GRID_LICENSE_INFO_MAX_LENGTH (128) /* License info strings for vGPU products */ #define NV_GRID_LICENSE_FEATURE_VPC_EDITION "GRID-Virtual-PC,2.0;Quadro-Virtual-DWS,5.0;GRID-Virtual-WS,2.0;GRID-Virtual-WS-Ext,2.0" @@ -54,11 +54,6 @@ /* NV20_SUBDEVICE_XX gpu control commands and parameters */ -/* Valid feature values */ -#define NV2080_CTRL_GPU_GET_FEATURES_CLK_ARCH_DOMAINS 0:0 -#define NV2080_CTRL_GPU_GET_FEATURES_CLK_ARCH_DOMAINS_FALSE (0x00000000U) -#define NV2080_CTRL_GPU_GET_FEATURES_CLK_ARCH_DOMAINS_TRUE (0x00000001U) - typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO; @@ -112,7 +107,10 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO; #define NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED (0x0000003fU) -#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE (0x00000040U) + + + +#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE (0x00000041U) /* valid minor revision extended values */ #define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_NONE (0x00000000U) @@ -750,7 +748,7 @@ typedef struct NV2080_CTRL_GPU_GET_ENGINES_PARAMS { #define NV2080_CTRL_CMD_GPU_GET_ENGINES_V2 (0x20800170U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS_MESSAGE_ID" */ /* Must match NV2080_ENGINE_TYPE_LAST from cl2080.h */ -#define NV2080_GPU_MAX_ENGINES_LIST_SIZE 0x3EU +#define NV2080_GPU_MAX_ENGINES_LIST_SIZE 0x3FU #define NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS_MESSAGE_ID (0x70U) @@ -1123,7 +1121,7 @@ typedef struct NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS { #define NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS (0x2080012fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_MESSAGE_ID" */ -#define NV2080_CTRL_GPU_ECC_UNIT_COUNT (0x00000018U) +#define NV2080_CTRL_GPU_ECC_UNIT_COUNT (0x00000019U) @@ -2244,16 +2242,6 @@ typedef struct NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS { NvU8 oemInfo[NV2080_GPU_MAX_OEM_INFO_LENGTH]; } NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS; -/* NV2080_CTRL_CMD_GPU_PROCESS_POST_GC6_EXIT_TASKS - * - * Complete any pending tasks the need to be run after GC6 exit is complete at OS/KMD level - * - * Possible status return values are: - * NV_OK - * NV_ERR_NOT_READY - */ -#define NV2080_CTRL_CMD_GPU_PROCESS_POST_GC6_EXIT_TASKS (0x2080016aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x6A" */ - /* * NV2080_CTRL_CMD_GPU_GET_VPR_INFO * @@ -2286,7 +2274,7 @@ typedef struct NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS { * NV_OK * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_GPU_GET_VPR_INFO (0x2080016bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GPU_GET_VPR_INFO (0x2080016bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS_MESSAGE_ID" */ typedef enum NV2080_CTRL_VPR_INFO_QUERY_TYPE { @@ -2315,6 +2303,8 @@ typedef struct NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS { * H.264 encoding capacity on this GPU. * 2. NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_HEVC: Use this to query the * H.265/HEVC encoding capacity on this GPU. + * 3. NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_AV1: Use this to query the + * AV1 encoding capacity on this GPU. * * encoderCapacity [out] * Encoder capacity value from 0 to 100. Value of 0x00 indicates encoder performance @@ -2330,6 +2320,7 @@ typedef struct NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS { typedef enum NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE { NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_H264 = 0, NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_HEVC = 1, + NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_AV1 = 2, } NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE; #define NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS_MESSAGE_ID (0x6CU) @@ -2706,6 +2697,9 @@ typedef struct NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS { * validCTSIdMask[OUT] * - Mask of CTS IDs usable by this partition, not reflecting current allocations * + * validGfxCTSIdMask[OUT] + * - Mask of CTS IDs that contain Gfx capable Grs usable by this partition, not reflecting current allocations + * * Possible status values returned are: * NV_OK * NV_ERR_INVALID_ARGUMENT @@ -2735,6 +2729,7 @@ typedef struct NV2080_CTRL_GPU_GET_PARTITION_INFO { NvBool bValid; NvBool bPartitionError; NV_DECLARE_ALIGNED(NvU64 validCTSIdMask, 8); + NV_DECLARE_ALIGNED(NvU64 validGfxCTSIdMask, 8); } NV2080_CTRL_GPU_GET_PARTITION_INFO; /* @@ -4041,7 +4036,9 @@ typedef struct NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS { #define NV2080_GPU_FABRIC_CLUSTER_UUID_LEN 16U -#define NV2080_CTRL_GPU_FABRIC_PROBE_CAP_MC_SUPPORTED NVBIT64(0) +#define NV2080_CTRL_GPU_FABRIC_PROBE_CAP_MC_SUPPORTED NVBIT64(0) + + /*! * NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS @@ -4070,6 +4067,8 @@ typedef struct NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS { * - Summary of fabric capabilities received from probe resp * Possible values are * NV2080_CTRL_GPU_FABRIC_PROBE_CAP_* + * fabricCliqueId[OUT] + * - Unique ID of a set of GPUs within a fabric partition that can perform P2P */ #define NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xA3U) @@ -4079,6 +4078,7 @@ typedef struct NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS { NvU8 clusterUuid[NV2080_GPU_FABRIC_CLUSTER_UUID_LEN]; NvU16 fabricPartitionId; NV_DECLARE_ALIGNED(NvU64 fabricCaps, 8); + NvU32 fabricCliqueId; } NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS; #define NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO (0x208001a3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID" */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h index 86ec9b4792..dcb4336cbf 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h @@ -260,6 +260,9 @@ typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO; #define NV2080_CTRL_GR_INFO_INDEX_DUMMY NV0080_CTRL_GR_INFO_INDEX_DUMMY #define NV2080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES NV0080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES +#define NV2080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES NV0080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES +#define NV2080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS NV0080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS +#define NV2080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG NV0080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG /* When adding a new INDEX, please update INDEX_MAX and MAX_SIZE accordingly * NOTE: 0080 functionality is merged with 2080 functionality, so this max size @@ -1276,16 +1279,24 @@ typedef struct NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS { * NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS * struct to hand in the required info to RM * - * pControlStructure - * This input is the kernel CPU pointer to the control structure. + * maxSlots + * Max pool slots + * hMemory + * Handle to GFX Pool memory + * offset + * Offset of the control structure in GFX Pool memory + * size + * Size of the control structure */ #define NV2080_CTRL_CMD_GR_GFX_POOL_INITIALIZE (0x20801220U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS_MESSAGE_ID (0x20U) typedef struct NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS { - NV_DECLARE_ALIGNED(NvP64 pControlStructure, 8); - NvU32 maxSlots; + NvU32 maxSlots; + NvHandle hMemory; + NvU32 offset; + NvU32 size; } NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS; #define NV2080_CTRL_GR_GFX_POOL_MAX_SLOTS 64U @@ -1301,21 +1312,27 @@ typedef struct NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS { * * NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS * - * pControlStructure - * This input is the kernel CPU pointer to the control structure * numSlots * This input indicates how many slots are being added and are contained in the slots parameter * slots * This input contains an array of the slots to be added to the control structure + * hMemory + * Handle to GFX Pool memory + * offset + * Offset of the control structure in GFX Pool memory + * size + * Size of the control structure */ #define NV2080_CTRL_CMD_GR_GFX_POOL_ADD_SLOTS (0x20801221U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS_MESSAGE_ID (0x21U) typedef struct NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS { - NV_DECLARE_ALIGNED(NvP64 pControlStructure, 8); - NvU32 numSlots; - NvU32 slots[NV2080_CTRL_GR_GFX_POOL_MAX_SLOTS]; + NvU32 numSlots; + NvU32 slots[NV2080_CTRL_GR_GFX_POOL_MAX_SLOTS]; + NvHandle hMemory; + NvU32 offset; + NvU32 size; } NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS; /* @@ -1330,8 +1347,6 @@ typedef struct NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS { * * NV2080_CTRL_CMD_GR_GFX_POOL_REMOVE_SLOTS_PARAMS * - * pControlStructure - * This input is the kernel CPU pointer to the control structure * numSlots * This input indicates how many slots are being removed. if * bRemoveSpecificSlots is true, then it also indicates how many entries in @@ -1348,16 +1363,24 @@ typedef struct NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS { * the number of slots they want removed and RM will pick up to that * many. If there are not enough slots on the freelist to remove the * requested amount, RM will return the number it was able to remove. + * hMemory + * Handle to GFX Pool memory + * offset + * Offset of the control structure in GFX Pool memory + * size + * Size of the control structure */ #define NV2080_CTRL_CMD_GR_GFX_POOL_REMOVE_SLOTS (0x20801222U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS_MESSAGE_ID (0x22U) typedef struct NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS { - NV_DECLARE_ALIGNED(NvP64 pControlStructure, 8); - NvU32 numSlots; - NvU32 slots[NV2080_CTRL_GR_GFX_POOL_MAX_SLOTS]; - NvBool bRemoveSpecificSlots; + NvU32 numSlots; + NvU32 slots[NV2080_CTRL_GR_GFX_POOL_MAX_SLOTS]; + NvBool bRemoveSpecificSlots; + NvHandle hMemory; + NvU32 offset; + NvU32 size; } NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS; diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gsp.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gsp.h index 4bb6216580..a84119a02f 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gsp.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gsp.h @@ -75,9 +75,12 @@ typedef struct NV2080_CTRL_GSP_GET_FEATURES_PARAMS { } NV2080_CTRL_GSP_GET_FEATURES_PARAMS; /* Valid feature values */ -#define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED 0:0 -#define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_FALSE (0x00000000) -#define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_TRUE (0x00000001) +#define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED 0:0 +#define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_FALSE (0x00000000) +#define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_TRUE (0x00000001) +#define NV2080_CTRL_GSP_GET_FEATURES_VGPU_GSP_MIG_REFACTORING_ENABLED 1:1 +#define NV2080_CTRL_GSP_GET_FEATURES_VGPU_GSP_MIG_REFACTORING_ENABLED_FALSE (0x00000000) +#define NV2080_CTRL_GSP_GET_FEATURES_VGPU_GSP_MIG_REFACTORING_ENABLED_TRUE (0x00000001) /* * NV2080_CTRL_CMD_GSP_GET_RM_HEAP_STATS @@ -95,7 +98,7 @@ typedef struct NV2080_CTRL_GSP_GET_FEATURES_PARAMS { * An NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT record corresponding to * the "high water mark" of heap usage since GSP-RM was started. */ -#define NV2080_CTRL_CMD_GSP_GET_RM_HEAP_STATS (0x20803602) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GSP_INTERFACE_ID << 8) | NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_GSP_GET_RM_HEAP_STATS (0x20803602) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GSP_INTERFACE_ID << 8) | NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS_MESSAGE_ID" */ /* * NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080hshub.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080hshub.h index bc25c808d5..0160705ee8 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080hshub.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080hshub.h @@ -52,4 +52,22 @@ typedef struct NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS { #define NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK (0x20804101) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_HSHUB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS_MESSAGE_ID" */ +/* + * NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE + * + * This command sets EC throttle mode registers + * + * ecMode + * EC Mode 0-7 to write to mode register + * status + * return status + */ +#define NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS { + NvU32 ecMode; + NvU32 status; +} NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS; + +#define NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE (0x20804102) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_HSHUB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS_MESSAGE_ID" */ /* _ctrl2080hshub_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h index cb481c566f..451a070cb6 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h @@ -219,6 +219,23 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS { typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS; +/* + * NV2080_CTRL_CMD_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS + * + * Set flags for use by the video event buffer + * + * flags + * VIDEO_TRACE_FLAG__* + * + */ +#define NV2080_CTRL_CMD_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS (0x20800a21) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS_PARAMS_MESSAGE_ID (0x21U) + +typedef struct NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS_PARAMS { + NvU32 flags; +} NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS_PARAMS; + /*! * @ref NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER * @ref NV2080_CTRL_CMD_GR_GET_SM_TO_GPC_TPC_MAPPINGS @@ -793,37 +810,6 @@ typedef struct NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS { NV2080_CTRL_INTERNAL_CONSTRUCTED_FALCON_INFO constructedFalconsTable[NV2080_CTRL_CMD_INTERNAL_MAX_CONSTRUCTED_FALCONS]; } NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS; -typedef struct NV2080_CTRL_INTERNAL_NV_RANGE { - NV_DECLARE_ALIGNED(NvU64 lo, 8); - NV_DECLARE_ALIGNED(NvU64 hi, 8); -} NV2080_CTRL_INTERNAL_NV_RANGE; - -/*! - * NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS - * - * This structure specifies a target swizz-id and mem_range to update - * - * swizzId[IN] - * - Targeted swizz-id for which the memRange is being set - * - * memAddrRange[IN] - * - Memory Range for given GPU instance - */ -#define NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID (0x43U) - -typedef struct NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS { - NvU32 swizzId; - NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NV_RANGE memAddrRange, 8); -} NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS; - -#define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE (0x20800a44) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID" */ - -#define NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID (0x44U) - -typedef NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS; - -#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE (0x20800a43) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID" */ - /** * Get GR PDB properties synchronized between Kernel and Physical * @@ -1000,6 +986,9 @@ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS { * * validCTSIdMask [OUT] * # mask of CTS IDs which can be assigned under this profile + * + * validGfxCTSIdMask [OUT] + * # mask of CTS IDs that contain Gfx capable Grs which can be assigned under this profile */ #define NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES 20 @@ -1020,6 +1009,7 @@ typedef struct NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO { NvU32 nvJpgCount; NvU32 nvOfaCount; NV_DECLARE_ALIGNED(NvU64 validCTSIdMask, 8); + NV_DECLARE_ALIGNED(NvU64 validGfxCTSIdMask, 8); } NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO; /*! @@ -1543,6 +1533,11 @@ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS { #define NV2080_CTRL_INTERNAL_MAX_SWIZZ_ID 15 +typedef struct NV2080_CTRL_INTERNAL_NV_RANGE { + NV_DECLARE_ALIGNED(NvU64 lo, 8); + NV_DECLARE_ALIGNED(NvU64 hi, 8); +} NV2080_CTRL_INTERNAL_NV_RANGE; + #define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID (0x60U) typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS { @@ -1577,12 +1572,6 @@ typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS { typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS; -/*! - * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_VALID_SWIZZID_MASK - * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_VALID_SWIZZID_MASK - */ -#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_VALID_SWIZZID_MASK (0x20800a64) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x64" */ - /*! * NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES * NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES @@ -1981,7 +1970,7 @@ typedef struct NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X { #define NV2080_CTRL_CMD_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO (0x20800aa2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_SKYLINES 8 -#define NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_NON_SINGLETON_VGPCS 8 +#define NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_NON_SINGLETON_VGPCS 12 /*! * NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO * skylineVgpcSize[OUT] @@ -2181,6 +2170,8 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS { typedef struct NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS { NvBool bPcieGen4Capable; NvBool bIsC2CLinkUp; + NvBool bIsDeviceMultiFunction; + NvBool bGcxPmuCfgSpaceRestore; NV_DECLARE_ALIGNED(NvU64 dmaWindowStartAddress, 8); } NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS; @@ -3417,20 +3408,21 @@ typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS { } NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS; /* - * NV2080_CTRL_CMD_INTERNAL_GC6_ENTRY_PREREQUISITE + * NV2080_CTRL_CMD_INTERNAL_GCX_ENTRY_PREREQUISITE * * This command gets if GPU is in a proper state (P8 and engine idle) to be ready to enter RTD3 * * Possible status return values are: * NV_OK Success */ -#define NV2080_CTRL_CMD_INTERNAL_GC6_ENTRY_PREREQUISITE (0x2080a7d7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_POWER_LEGACY_NON_PRIVILEGED_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_INTERNAL_GCX_ENTRY_PREREQUISITE (0x2080a7d7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_POWER_LEGACY_NON_PRIVILEGED_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID" */ -#define NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID (0xD7U) +#define NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID (0xD7U) -typedef struct NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS { - NvBool bIsSatisfied; -} NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS; +typedef struct NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS { + NvBool bIsGC6Satisfied; + NvBool bIsGCOFFSatisfied; +} NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS; /* * This command unsets Dynamic Boost limit when nvidia-powerd is terminated unexpectedly. @@ -3910,4 +3902,39 @@ typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_P NvU32 limitBattMax; } NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS; +/* + * NV2080_CTRL_CMD_INTERNAL_INIT_USER_SHARED_DATA + * + * @brief Initialize RM User Shared Data memory mapping on physical RM + * + * @param[in] physAddr Physical address of memdesc to link physical to kernel + * 0 to de-initialize + * + * @return NV_OK on success + * @return NV_ERR_ otherwise + */ +#define NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS_MESSAGE_ID (0xFEU) + +typedef struct NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS { + NV_DECLARE_ALIGNED(NvU64 physAddr, 8); +} NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_INIT_USER_SHARED_DATA (0x20800afe) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL + * + * @brief Set mask of data to be polled on physical for RUSD + * + * @param[in] polledDataMask Bitmask of data requested, defined in cl00de + * + * @return NV_OK on success + * @return NV_ERR_ otherwise + */ +#define NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS_MESSAGE_ID (0xFFU) + +typedef struct NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS { + NV_DECLARE_ALIGNED(NvU64 polledDataMask, 8); +} NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL (0x20800aff) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS_MESSAGE_ID" */ + /* ctrl2080internal_h */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvd.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvd.h index 767c33d056..f5b7202c56 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvd.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvd.h @@ -281,6 +281,7 @@ typedef struct NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS { #define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_TDR_REASON 1 #define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_INSERT_RECORD 2 #define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_SET_TAG 3 +#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_RCLOG 4 #define NV2080_CTRL_NOCAT_TDR_TYPE_NONE 0 #define NV2080_CTRL_NOCAT_TDR_TYPE_LEGACY 1 @@ -324,6 +325,16 @@ typedef struct NV2080CtrlNocatJournalSetTag { NvU8 tag[NV2080_NOCAT_JOURNAL_MAX_STR_LEN]; } NV2080CtrlNocatJournalSetTag; +typedef struct NV2080CtrlNocatJournalRclog { + NvU32 flags; + NvU32 rclogSize; // rclog size + NvU32 rmGpuId; // RMGpuId associated with the adapter + NvU32 APIType; // API Type (dx9, dx1x, ogl, etc.) + NvU32 contextType; // Context type (OGL, DX, etc.) + NvU32 exceptType; // ROBUST_CHANNEL_* error identifier + NvU8 processImageName[NV2080_NOCAT_JOURNAL_MAX_STR_LEN]; // process image name (without path) +} NV2080CtrlNocatJournalRclog; + #define NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_MESSAGE_ID (0xBU) typedef struct NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS { @@ -333,6 +344,7 @@ typedef struct NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS { NV_DECLARE_ALIGNED(NV2080CtrlNocatJournalDataTdrReason tdrReason, 8); NV_DECLARE_ALIGNED(NV2080CtrlNocatJournalInsertRecord insertData, 8); NV2080CtrlNocatJournalSetTag tagData; + NV2080CtrlNocatJournalRclog rclog; } nocatJournalData; } NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS; /* _ctr2080nvd_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h index 5dce870366..411a6194dd 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h @@ -2971,8 +2971,91 @@ typedef struct NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS { NvU32 linkId; } NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS; -#define NV2080_CTRL_CMD_NVLINK_POST_FAULT_UP (0x20803043U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_NVLINK_POST_FAULT_UP (0x20803043U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NVLINK_PORT_EVENT_COUNT_SIZE 64U + +/* +* Structure to store port event information +* +* portEventType +* Type of port even that occurred: NVLINK_PORT_EVENT_TYPE* +* +* gpuId +* Gpu that port event occurred on +* +* linkId +* Link id that port event occurred on +* +* time +* Platform time (nsec) when event occurred +*/ +typedef struct NV2080_CTRL_NVLINK_PORT_EVENT { + NvU32 portEventType; + NvU32 gpuId; + NvU32 linkId; + NV_DECLARE_ALIGNED(NvU64 time, 8); +} NV2080_CTRL_NVLINK_PORT_EVENT; + +/* +* NV2080_CTRL_CMD_NVLINK_GET_PORT_EVENTS +* +* This command returns the port up and port down events that have occurred +* +* Parameters: +* +* portEventIndex [IN/OUT] +* On input: The index of the first port event at which to start reading out of the driver. +* +* On output: The index of the first port event that wasn't reported through the 'port event' array +* in this call to NV2080_CTRL_CMD_NVLINK_GET_PORT_EVENTS. +* +* nextPortEventIndex[OUT] +* The index that will be assigned to the next port event that occurs. +* Users of the GET_PORT_EVENTS control call may set 'portEventIndex' to this field on initialization +* to bypass port events that have already occurred without making multiple control calls. +* +* portEventCount [OUT] +* Number of port events returned by the call. Currently, portEventCount is limited +* by NV2080_CTRL_NVLINK_PORT_EVENT_COUNT_SIZE. In order to query all the port events, a +* client needs to keep calling the control till portEventCount is zero. +* +* bOverflow [OUT] +* True when the port event log is overflowed and no longer contains all the port +* events that have occurred, false otherwise. +* +* portEvent [OUT] +* The port event entires. +*/ +#define NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS_MESSAGE_ID (0x44U) + +typedef struct NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS { + NV_DECLARE_ALIGNED(NvU64 portEventIndex, 8); + NV_DECLARE_ALIGNED(NvU64 nextPortEventIndex, 8); + NvU32 portEventCount; + NvBool bOverflow; + NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_PORT_EVENT portEvent[NV2080_CTRL_NVLINK_PORT_EVENT_COUNT_SIZE], 8); +} NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_GET_PORT_EVENTS (0x20803044U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS_MESSAGE_ID" */ + +/* +* NV2080_CTRL_CMD_NVLINK_CYCLE_LINK +* +* This command cycles a link by faulting it and then retraining the link +* +* Parameters: +* +* linkId [IN] +* The link id of the link to be cycled +*/ +#define NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS_MESSAGE_ID (0x45U) + +typedef struct NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS { + NvU32 linkId; +} NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS; +#define NV2080_CTRL_CMD_NVLINK_CYCLE_LINK (0x20803045U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS_MESSAGE_ID" */ /* * NV2080_CTRL_CMD_NVLINK_IS_REDUCED_CONFIG @@ -2982,13 +3065,13 @@ typedef struct NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS { * [out] bReducedNvlinkConfig * Link number which the sequence should be triggered */ -#define NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS_MESSAGE_ID (0x44U) +#define NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS_MESSAGE_ID (0x46U) typedef struct NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS { NvBool bReducedNvlinkConfig; } NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS; -#define NV2080_CTRL_CMD_NVLINK_IS_REDUCED_CONFIG (0x20803044U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_NVLINK_IS_REDUCED_CONFIG (0x20803046U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS_MESSAGE_ID" */ /* _ctrl2080nvlink_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080spdm.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080spdm.h index 28e999a1b8..35a309b04a 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080spdm.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080spdm.h @@ -60,6 +60,9 @@ typedef struct RM_GSP_SPDM_CC_INIT_CTX { NvU64_ALIGN32 dmaAddr; // The address RM allocate in SYS memory or FB memory. + + NvU32 rmBufferSizeInByte; // The memort size allocated by RM(exclude NV_SPDM_DESC_HEADER) + } RM_GSP_SPDM_CC_INIT_CTX; typedef struct RM_GSP_SPDM_CC_INIT_CTX *PRM_GSP_SPDM_CC_INIT_CTX; diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ucodefuzzer.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ucodefuzzer.h index aedb3cef74..7a3cd3a564 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ucodefuzzer.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ucodefuzzer.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h index c090e795a6..61a40b67c9 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h @@ -52,6 +52,8 @@ * guestFbLengthList - list of guest FB memory length in bytes * pluginHeapMemoryPhysAddr - plugin heap memory offset * pluginHeapMemoryLength - plugin heap memory length in bytes + * migRmHeapMemoryPhysAddr - Mig rm heap memory region's physical offset. + * migRmHeapMemoryLength - Mig rm heap memory length in bytes * bDeviceProfilingEnabled - If set to true, profiling is allowed */ #define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK (0x20804001) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID" */ @@ -59,7 +61,7 @@ #define NV2080_CTRL_MAX_VMMU_SEGMENTS 384 /* Must match NV2080_ENGINE_TYPE_LAST from cl2080.h */ -#define NV2080_GPU_MAX_ENGINES 0x3e +#define NV2080_GPU_MAX_ENGINES 0x3f #define NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID (0x1U) @@ -83,6 +85,8 @@ typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAM NV_DECLARE_ALIGNED(NvU64 initTaskLogBuffSize, 8); NV_DECLARE_ALIGNED(NvU64 vgpuTaskLogBuffOffset, 8); NV_DECLARE_ALIGNED(NvU64 vgpuTaskLogBuffSize, 8); + NV_DECLARE_ALIGNED(NvU64 migRmHeapMemoryPhysAddr, 8); + NV_DECLARE_ALIGNED(NvU64 migRmHeapMemoryLength, 8); NvBool bDeviceProfilingEnabled; } NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS; diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fbif.h b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fbif.h index b6cf87c11d..2ec0925327 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fbif.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fbif.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2009-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fmmu.h b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fmmu.h index 2e4964f400..8271ff70da 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fmmu.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fmmu.h @@ -68,6 +68,7 @@ typedef struct NV208F_CTRL_MMU_ECC_INJECT_ERROR_PARAMS { NvU32 sublocation; NvU8 unit; NvU8 errorType; + } NV208F_CTRL_MMU_ECC_INJECT_ERROR_PARAMS; diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl90e7.h b/src/common/sdk/nvidia/inc/ctrl/ctrl90e7.h new file mode 100644 index 0000000000..f3ea79e77a --- /dev/null +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl90e7.h @@ -0,0 +1,72 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl90e7.finn +// + +#include "nvfixedtypes.h" +#include "ctrl/ctrlxxxx.h" +/* GF100_SUBDEVICE_INFOROM control commands and parameters */ + +#define NV90E7_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x90E7, NV90E7_CTRL_##cat, idx) + +/* Command categories (6 bits) */ +#define NV90E7_CTRL_RESERVED (0x00) +#define NV90E7_CTRL_BBX (0x01) + + + +/* + * NV90E7_CTRL_CMD_BBX_GET_LAST_FLUSH_TIME + * + * This command is used to query the last BBX flush timestamp and duration. If BBX has not yet + * been flushed, the status returned is NV_ERR_NOT_READY. + * + * timestamp + * This parameter specifies the start timestamp of the last BBX flush. + * + * durationUs + * This parameter specifies the duration (us) of the last BBX flush. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_READY + * NV_ERR_NOT_SUPPORTED + */ +#define NV90E7_CTRL_CMD_BBX_GET_LAST_FLUSH_TIME (0x90e70113) /* finn: Evaluated from "(FINN_GF100_SUBDEVICE_INFOROM_BBX_INTERFACE_ID << 8) | NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS_MESSAGE_ID" */ + +#define NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS_MESSAGE_ID (0x13U) + +typedef struct NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS { + NV_DECLARE_ALIGNED(NvU64 timestamp, 8); + NvU32 durationUs; +} NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS; + + + diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl90f1.h b/src/common/sdk/nvidia/inc/ctrl/ctrl90f1.h index c98c8cb3de..73555b5abd 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl90f1.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl90f1.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -32,6 +32,7 @@ #include "ctrl/ctrlxxxx.h" #include "mmu_fmt_types.h" +#include "nvcfg_sdk.h" #define GMMU_FMT_MAX_LEVELS 6U @@ -85,30 +86,35 @@ typedef struct NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS { typedef struct NV_CTRL_VASPACE_PAGE_LEVEL { /*! - * Format of this level. - */ + * Format of this level. + */ NV_DECLARE_ALIGNED(struct MMU_FMT_LEVEL *pFmt, 8); /*! - * Level/Sublevel Formats flattened - */ + * Level/Sublevel Formats flattened + */ NV_DECLARE_ALIGNED(MMU_FMT_LEVEL levelFmt, 8); NV_DECLARE_ALIGNED(MMU_FMT_LEVEL sublevelFmt[MMU_FMT_MAX_SUB_LEVELS], 8); /*! - * Physical address of this page level instance. - */ + * Physical address of this page level instance. + */ NV_DECLARE_ALIGNED(NvU64 physAddress, 8); /*! - * Aperture in which this page level instance resides. - */ + * Aperture in which this page level instance resides. + */ NvU32 aperture; /*! - * Size in bytes allocated for this level instance. - */ + * Size in bytes allocated for this level instance. + */ NV_DECLARE_ALIGNED(NvU64 size, 8); + + /*! + * Entry Index for this offset. + */ + NvU32 entryIndex; } NV_CTRL_VASPACE_PAGE_LEVEL; #define NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS_MESSAGE_ID (0x2U) @@ -135,6 +141,12 @@ typedef struct NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS { */ NV_DECLARE_ALIGNED(NvU64 pageSize, 8); + /*! + * [in] Flags + * Contains flags to control various aspects of page level info. + */ + NV_DECLARE_ALIGNED(NvU64 flags, 8); + /*! * [out] Number of levels populated. */ @@ -146,6 +158,11 @@ typedef struct NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS { NV_DECLARE_ALIGNED(NV_CTRL_VASPACE_PAGE_LEVEL levels[GMMU_FMT_MAX_LEVELS], 8); } NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS; +/* valid flags parameter values */ +#define NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_FLAG_NONE 0x0ULL +#define NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_FLAG_BAR1 NVBIT64(0) + + /*! * Reserve (allocate and bind) page directory/table entries up to * a given level of the MMU format. Also referred to as "lock-down". @@ -155,7 +172,7 @@ typedef struct NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS { * A particular VA range and level (page size) combination may only be * locked down once at a given time, but each level is independent. */ -#define NV90F1_CTRL_CMD_VASPACE_RESERVE_ENTRIES (0x90f10103U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS_MESSAGE_ID" */ +#define NV90F1_CTRL_CMD_VASPACE_RESERVE_ENTRIES (0x90f10103U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS_MESSAGE_ID" */ #define NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS_MESSAGE_ID (0x3U) @@ -314,4 +331,77 @@ typedef struct NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS { } levels[GMMU_FMT_MAX_LEVELS]; } NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS; +/*! + * Retrieve extra VA range that RM needs to reserve from the OS + */ +#define NV90F1_CTRL_CMD_VASPACE_GET_HOST_RM_MANAGED_SIZE (0x90f10107U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS_MESSAGE_ID" */ +#define NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS { + /*! + * [in] GPU sub-device handle - this API only supports unicast. + * Pass 0 to use subDeviceId instead. + */ + NvHandle hSubDevice; + + /*! + * [in] GPU sub-device ID. Ignored if hSubDevice is non-zero. + */ + NvU32 subDeviceId; + + /*! + * [out] The required VA range, in Megabytes + */ + NV_DECLARE_ALIGNED(NvU64 requiredVaRange, 8); +} NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS; + +/*! + * Retrieve info on a VAS heap - used only for the MODS test RandomVATest + */ +#define NV90F1_CTRL_CMD_VASPACE_GET_VAS_HEAP_INFO (0x90f10108U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS_MESSAGE_ID" */ +#define NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS { + /*! + * [in] GPU sub-device handle - this API only supports unicast. + * Pass 0 to use subDeviceId instead. + */ + NvHandle hSubDevice; + + /*! + * [in] GPU sub-device ID. Ignored if hSubDevice is non-zero. + */ + NvU32 subDeviceId; + + /*! + * [out] Number of free bytes in the heap + */ + NV_DECLARE_ALIGNED(NvU64 bytesFree, 8); + + /*! + * [out] Number of bytes in the heap + */ + NV_DECLARE_ALIGNED(NvU64 bytesTotal, 8); + + /*! + * [out] Offset of largest free block + */ + NV_DECLARE_ALIGNED(NvU64 largestFreeOffset, 8); + + /*! + * [out] Size of the largest free block + */ + NV_DECLARE_ALIGNED(NvU64 largestFreeSize, 8); + + /*! + * [out] Number of usable free bytes + */ + NV_DECLARE_ALIGNED(NvU64 usableBytesFree, 8); + + /*! + * [out] Number of free blocks + */ + NvU32 numFreeBlocks; +} NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS; + /* _ctrl90f1_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h b/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h index 74bab8e6d8..fad97c53fa 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -556,4 +556,39 @@ typedef struct NVB0CC_CTRL_RELEASE_HES_PARAMS { NVB0CC_CTRL_HES_TYPE type; } NVB0CC_CTRL_RELEASE_HES_PARAMS; + /* End of extension construct */ + + +/*! + * NVB0CC_CTRL_CMD_DISABLE_DYNAMIC_MMA_BOOST + * + * Disable the Dynamic MMA clock boost during profiler lifetime. + * + */ +#define NVB0CC_CTRL_CMD_DISABLE_DYNAMIC_MMA_BOOST (0xb0cc0117) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS_MESSAGE_ID" */ +#define NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS_MESSAGE_ID (0x17U) + +typedef struct NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS { + /*! + * [in]: En/Disable Dynamic MMA Boost. True = disable Boost; False = re-enable Boost. + */ + NvBool disable; +} NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS; + +/*! + * NVB0CC_CTRL_CMD_GET_DYNAMIC_MMA_BOOST_STATUS + * + * Request the Dynamic MMA clock boost feature enablement status. + * + */ +#define NVB0CC_CTRL_CMD_GET_DYNAMIC_MMA_BOOST_STATUS (0xb0cc0118) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS_MESSAGE_ID" */ +#define NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS_MESSAGE_ID (0x18U) + +typedef struct NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS { + /*! + * [out]: Dynamic MMA Boost status: true = boost enabled/available; False = Boost disabled/unavailable. + */ + NvBool enabled; +} NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS; + /* _ctrlb0ccprofiler_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc372/ctrlc372chnc.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc372/ctrlc372chnc.h index 3e2f6e8d10..58b0291b98 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlc372/ctrlc372chnc.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc372/ctrlc372chnc.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2021,2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -35,6 +35,7 @@ #define NVC372_CTRL_MAX_POSSIBLE_HEADS 8 #define NVC372_CTRL_MAX_POSSIBLE_WINDOWS 32 +#define NVC372_CTRL_MAX_POSSIBLE_TILES 8 #define NVC372_CTRL_CMD_IS_MODE_POSSIBLE (0xc3720101) /* finn: Evaluated from "(FINN_NVC372_DISPLAY_SW_CHNCTL_INTERFACE_ID << 8) | NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS_MESSAGE_ID" */ @@ -117,6 +118,10 @@ * bOverfetchEnabled indicates whether or not the vertical overfetch is * enabled in postcomp scaler. * + * head.bLtmAllowed + * bLtmAllowed indicates whether or not the Local Tone Mapping (LTM) is + * enabled in postcomp. + * * head.minFrameIdle.leadingRasterLines * leadingRasterLines defines the number of lines between the start of the * frame (vsync) and the start of the active region. This includes Vsync, @@ -132,6 +137,17 @@ * This parameter specifies whether or not the output LUT is enabled, and * the size of the LUT. The parameter should be an * NVC372_CTRL_IMP_LUT_USAGE_xxx value. + * On Volta, the value should be one of these: + * NVC372_CTRL_IMP_LUT_USAGE_1025, NVC372_CTRL_IMP_LUT_USAGE_257 or + * NVC372_CTRL_IMP_LUT_USAGE_NONE + * + * After Volta, the value should be one of these: + * NVC372_CTRL_IMP_LUT_USAGE_HW_MAX (this indicates that LUT is allowed) or + * NVC372_CTRL_IMP_LUT_USAGE_NONE + * (On older post-Volta products, clients may set other + * NVC372_CTRL_IMP_LUT_USAGE_xxx values, but they map to + * NVC372_CTRL_IMP_LUT_USAGE_HW_MAX in RM-SW.) + * * head.cursorSize32p * This parameter specifies the width of the cursor, in units of 32 pixels. @@ -141,6 +157,21 @@ * head.bEnableDsc * bEnableDsc indicates whether or not DSC is enabled * + * head.possibleDscSliceCountMask + * This is a bit mask indicating how many DSC slices are allowed in a + * scanline. If a bit n is set in the bit mask, it means that one possible + * configuration has n+1 DSC slices per scanline. + * + * This field is required only on systems that support tiling, and only if + * head.bEnableDsc is true. + * + * head.maxDscSliceWidth + * The maximum allowed DSC slice width is determined by spec restrictions + * and monitor capabilities. + * + * This field is required only on systems that support tiling, and only if + * head.bEnableDsc is true. + * * head.bYUV420Format * This parameter indicates output format is YUV420. * Refer to NVD_YUV420_Output_Functional_Description.docx for more details. @@ -224,11 +255,31 @@ * This parameter specifies whether or not the input LUT is enabled, and * the size of the LUT. The parameter should be an * NVC372_CTRL_IMP_LUT_USAGE_xxx value. + * On Volta, the value should be one of these: + * NVC372_CTRL_IMP_LUT_USAGE_1025, NVC372_CTRL_IMP_LUT_USAGE_257 or + * NVC372_CTRL_IMP_LUT_USAGE_NONE + * + * After Volta, the value should be one of these: + * NVC372_CTRL_IMP_LUT_USAGE_HW_MAX (this indicates that LUT is allowed) or + * NVC372_CTRL_IMP_LUT_USAGE_NONE + * (On older post-Volta products, clients may set other + * NVC372_CTRL_IMP_LUT_USAGE_xxx values, but they map to + * NVC372_CTRL_IMP_LUT_USAGE_HW_MAX in RM-SW.) * * window.tmoLut * This parameter specifies whether or not the tmo LUT is enabled, and * the size of the LUT. This lut is used for HDR. The parameter should be * an NVC372_CTRL_IMP_LUT_USAGE_xxx value. + * On Volta, the value should be one of these: + * NVC372_CTRL_IMP_LUT_USAGE_1025, NVC372_CTRL_IMP_LUT_USAGE_257 or + * NVC372_CTRL_IMP_LUT_USAGE_NONE + * + * After Volta, the value should be one of these: + * NVC372_CTRL_IMP_LUT_USAGE_HW_MAX (this indicates that LUT is allowed) or + * NVC372_CTRL_IMP_LUT_USAGE_NONE + * (On older post-Volta products, clients may set other + * NVC372_CTRL_IMP_LUT_USAGE_xxx values, but they map to + * NVC372_CTRL_IMP_LUT_USAGE_HW_MAX in RM-SW.) * * numHeads * This is the number of heads in the "head" array of the @@ -382,6 +433,101 @@ * Returns a short text string naming the domain for the margin returned in * "worstCaseMargin". See "worstCaseMargin" for more information. * + * numTilingAssignments + * This is the number of entries in the tilingAssignments array, each of + * which represents a possible distinct tiling configuration. The client + * will do the actual assignment of tiles during the modeset, but the + * information provided here will help the client to know how many tiles + * to assign to each head. + * + * The first tiling assignment (tilingAssignments[0]) is required; it will + * specify that one or more tiles must be assigned to each active head in + * order for the mode to be possible. Subsequent tiling assignments are + * optional; each higher assignment will reduce the required dispclk to a + * lower frequency, so the client may choose to use some or all of these + * assignments because they might reduce power consumption. + * + * The tiling assignments are incremental; the client may choose how many + * assignments to use (after the first one, which is required), but they + * must be used in sequence. For example, if there are five possible + * assignments (numTilingAssignments = 5), and the client wishes to apply + * the third assignment, the tiles from the first two assignments must also + * be allocated. + * + * If the client decides to use a particular tiling assignment, it should + * assign all tiles specified in that assignment. (Otherwise, there will + * be no benefit from that assignment for reducing dispclk.) + * + * A 3-head example of a set of tiling assignments is: + * numTilingAssignments = 3 + * tilingAssignments[0].numTiles = 4 + * tilingAssignments[1].numTiles = 2 + * tilingAssignments[2].numTiles = 1 + * tileList[0].head = 0 (first tile for tilingAssignments[0]) + * tileList[0].headDscSlices = 2 + * tileList[1].head = 0 (second tile for tilingAssignments[0]) + * tileList[1].headDscSlices = xxx (not used, because it is specified in + * tileList[0].headDscSlices) + * tileList[2].head = 1 (third tile for tilingAssignments[0]) + * tileList[2].headDscSlices = 1 + * tileList[3].head = 2 (fourth tile for tilingAssignments[0]) + * tileList[3].headDscSlices = 1 + * tileList[4].head = 1 (first tile for tilingAssignments[1]) + * tileList[4].headDscSlices = 2 + * tileList[5].head = 2 (second tile for tilingAssignments[1]) + * tileList[5].headDscSlices = 2 + * tileList[6].head = 0 (tile for tilingAssignments[2] + * tileList[6].headDscSlices = 3 + * + * tilingAssignments[0] always specifies the minimum tiling assignment + * necessary to make the mode possible. In this example, two tiles are + * required on head 0, but heads 1 and 2 can work with a single tile each. + * + * After the four required tiles are assigned for tilingAssignments[0], the + * client may choose to apply tilingAssignment[1] as well, to reduce + * dispclk further. Two additional tiles would be required for this, one + * on head 1 and one on head 2. Note that there would be no benefit to + * assigning a tile to only one of these two heads; all heads specified in + * the tilingAssignment must be assigned (if the tilingAssignment is to be + * used). After this assignment, head 1 and head 2 would each have two + * tiles assigned (one from tilingAssignment[0] and one from + * tilingAssignent[1]). Head 0 would still have 2 tiles assigned. + * + * If tilingAssignments[2] is also used, an additional tile would be + * assigned to head 0, bringing the tile total to three for that head. The + * number of DSC slices required for that head would be increased to three. + * + * tilingAssignments.numTiles + * This is the number of additional tiles required for the indexed tiling + * assignment. The tilingAssignment does not provide any benefit unless + * all of its specified tiles are assigned. + * + * tileList.head + * This specifies the head to which a tile must be assigned, to receive a + * benefit (dispclk reduction) for a given tiling assignment. + * tileList entries (head indexes) are assigned consecutively, based on the + * tilingAssignments.numTiles entries. For example, if + * tilingAssignments[0].numTiles = 3 and tilingAssignments[1].numTiles = 2, + * then the first three tileList entries (indexes 0, 1, and 2) would be for tiling + * assignment 0 and the next 2 entries (indexes 3 and 4) would be for + * tiling assignment 1. + * + * A single assignment may have multiple tileList.head entries for the same + * head (if a single head requires that more than one additional tile be + * assigned). + * + * tileList.headDscSlices + * headDscSlices gives the recommended number of DSC slices for each + * scanline for the head specified in tileList.head. If a specific tiling + * assignment has multiple tiles assigned to the same head, the + * headDscSlices value for the first tileList entry should be used; + * subsequent entries may be ignored. If multiple tilingAssignments are + * applied, the headDscSlices entry for the highest indexed + * tilingAssignment takes precedence over any entries from lower indexed + * assignments, for the same head. + * + * This field is relevant only if head.bEnableDsc is true. + * * Possible status values returned are: * NVOS_STATUS_SUCCESS * NVOS_STATUS_ERROR_GENERIC @@ -389,6 +535,7 @@ #define NVC372_CTRL_IMP_LUT_USAGE_NONE 0 #define NVC372_CTRL_IMP_LUT_USAGE_257 1 #define NVC372_CTRL_IMP_LUT_USAGE_1025 2 +#define NVC372_CTRL_IMP_LUT_USAGE_HW_MAX 3 typedef struct NVC372_CTRL_IMP_HEAD { NvU8 headIndex; @@ -427,6 +574,7 @@ typedef struct NVC372_CTRL_IMP_HEAD { NvU8 outputScalerVerticalTaps; NvBool bUpscalingAllowedV; NvBool bOverfetchEnabled; + NvBool bLtmAllowed; struct { NvU16 leadingRasterLines; @@ -438,6 +586,10 @@ typedef struct NVC372_CTRL_IMP_HEAD { NvBool bEnableDsc; + NvU32 possibleDscSliceCountMask; + + NvU32 maxDscSliceWidth; + NvBool bYUV420Format; NvBool bIs2Head1Or; @@ -464,6 +616,15 @@ typedef struct NVC372_CTRL_IMP_WINDOW { } NVC372_CTRL_IMP_WINDOW; typedef struct NVC372_CTRL_IMP_WINDOW *PNVC372_CTRL_IMP_WINDOW; +typedef struct NVC372_TILING_ASSIGNMENT { + NvU8 numTiles; +} NVC372_TILING_ASSIGNMENT; + +typedef struct NVC372_TILE_ENTRY { + NvU8 head; + NvU8 headDscSlices; +} NVC372_TILE_ENTRY; + #define NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_GET_MARGIN (0x00000001) #define NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE (0x00000002) @@ -506,6 +667,12 @@ typedef struct NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS { NvU32 dispClkKHz; + NvU32 numTilingAssignments; + + NVC372_TILING_ASSIGNMENT tilingAssignments[NVC372_CTRL_MAX_POSSIBLE_TILES]; + + NVC372_TILE_ENTRY tileList[NVC372_CTRL_MAX_POSSIBLE_TILES]; + char worstCaseDomain[8]; NvBool bUseCachedPerfState; diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlxxxx.h b/src/common/sdk/nvidia/inc/ctrl/ctrlxxxx.h index 3daf2358f2..6f03990d2e 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlxxxx.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlxxxx.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2005-2008,2013,2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2005-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/common/sdk/nvidia/inc/g_finn_rm_api.h b/src/common/sdk/nvidia/inc/g_finn_rm_api.h index 7f26fd544f..b1b14c667a 100644 --- a/src/common/sdk/nvidia/inc/g_finn_rm_api.h +++ b/src/common/sdk/nvidia/inc/g_finn_rm_api.h @@ -294,6 +294,12 @@ typedef FINN_RM_API FINN_NV01_DEVICE_0_OS_UNIX; typedef FINN_RM_API FINN_NV0090_KERNEL_GRAPHICS_CONTEXT; #define FINN_NV_SEMAPHORE_SURFACE_INTERFACE_ID (0x00da00U) typedef FINN_RM_API FINN_NV_SEMAPHORE_SURFACE; +#define FINN_RM_USER_SHARED_DATA_INTERFACE_ID (0xde00U) +typedef FINN_RM_API FINN_RM_USER_SHARED_DATA; +#define FINN_NV_MEMORY_EXPORT_RESERVED_INTERFACE_ID (0xE000U) +typedef FINN_RM_API FINN_NV_MEMORY_EXPORT_RESERVED; +#define FINN_NV_MEMORY_EXPORT_INTERFACE_ID (0xE001U) +typedef FINN_RM_API FINN_NV_MEMORY_EXPORT; #define FINN_IMEX_SESSION_INTERFACE_ID (0xf100U) typedef FINN_RM_API FINN_IMEX_SESSION; #define FINN_NV01_MEMORY_FABRIC_EXPORT_RESERVED_INTERFACE_ID (0xf400U) @@ -558,8 +564,6 @@ typedef FINN_RM_API FINN_GF100_SUBDEVICE_MASTER_MASTER; typedef FINN_RM_API FINN_GF100_SUBDEVICE_INFOROM_RESERVED; #define FINN_GF100_SUBDEVICE_INFOROM_BBX_INTERFACE_ID (0x90e701U) typedef FINN_RM_API FINN_GF100_SUBDEVICE_INFOROM_BBX; -#define FINN_GF100_SUBDEVICE_INFOROM_RPR_INTERFACE_ID (0x90e702U) -typedef FINN_RM_API FINN_GF100_SUBDEVICE_INFOROM_RPR; #define FINN_GF100_HDACODEC_RESERVED_INTERFACE_ID (0x90ec00U) typedef FINN_RM_API FINN_GF100_HDACODEC_RESERVED; diff --git a/src/common/sdk/nvidia/inc/nvdisptypes.h b/src/common/sdk/nvidia/inc/nvdisptypes.h index 7ebe391c43..adcfb98ab7 100644 --- a/src/common/sdk/nvidia/inc/nvdisptypes.h +++ b/src/common/sdk/nvidia/inc/nvdisptypes.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2016 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2016,2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/common/sdk/nvidia/inc/nverror.h b/src/common/sdk/nvidia/inc/nverror.h index dc24149639..9ef5493037 100644 --- a/src/common/sdk/nvidia/inc/nverror.h +++ b/src/common/sdk/nvidia/inc/nverror.h @@ -35,7 +35,6 @@ #include "nvcfg_sdk.h" #define ROBUST_CHANNEL_GR_EXCEPTION (13) -#define ROBUST_CHANNEL_GR_ERROR_SW_NOTIFY (13) #define ROBUST_CHANNEL_FAKE_ERROR (14) #define ROBUST_CHANNEL_VBLANK_CALLBACK_TIMEOUT (16) #define ROBUST_CHANNEL_DISP_MISSED_NOTIFIER (19) @@ -46,7 +45,7 @@ #define ROBUST_CHANNEL_VP_ERROR (27) #define ROBUST_CHANNEL_VP2_ERROR (28) #define ROBUST_CHANNEL_BSP_ERROR (29) -#define ROBUST_CHANNEL_BAD_ADDR_ACCESS (30) +#define ROBUST_CHANNEL_UNUSED_ERROR_30 (30) #define ROBUST_CHANNEL_FIFO_ERROR_MMU_ERR_FLT (31) #define ROBUST_CHANNEL_PBDMA_ERROR (32) #define ROBUST_CHANNEL_SEC_ERROR (33) @@ -120,7 +119,6 @@ #define ALI_TRAINING_FAIL (136) #define NVLINK_FLA_PRIV_ERR (137) #define ROBUST_CHANNEL_DLA_ERROR (138) -#define ROBUST_CHANNEL_FAST_PATH_ERROR (139) #define UNRECOVERABLE_ECC_ERROR_ESCAPE (140) #define ROBUST_CHANNEL_LAST_ERROR (UNRECOVERABLE_ECC_ERROR_ESCAPE) @@ -219,6 +217,15 @@ (x - ROBUST_CHANNEL_NVJPG0_ERROR) : \ (x - ROBUST_CHANNEL_NVJPG1_ERROR + 1)) +#define ROBUST_CHANNEL_OFA_ERROR(x) \ + (ROBUST_CHANNEL_OFA0_ERROR) + +#define ROBUST_CHANNEL_IS_OFA_ERROR(x) \ + (x == ROBUST_CHANNEL_OFA0_ERROR) + +#define ROBUST_CHANNEL_OFA_ERROR_IDX(x) \ + (x - ROBUST_CHANNEL_OFA0_ERROR) + // Error Levels #define ROBUST_CHANNEL_ERROR_RECOVERY_LEVEL_INFO (0) #define ROBUST_CHANNEL_ERROR_RECOVERY_LEVEL_NON_FATAL (1) diff --git a/src/common/sdk/nvidia/inc/nvos.h b/src/common/sdk/nvidia/inc/nvos.h index beafa59c81..15d1465960 100644 --- a/src/common/sdk/nvidia/inc/nvos.h +++ b/src/common/sdk/nvidia/inc/nvos.h @@ -995,13 +995,6 @@ typedef struct #define NVOS32_ATTR_AA_SAMPLES_8_VIRTUAL_16 0x00000009 #define NVOS32_ATTR_AA_SAMPLES_8_VIRTUAL_32 0x0000000A -// Tiled region -#define NVOS32_ATTR_TILED 9:8 -#define NVOS32_ATTR_TILED_NONE 0x00000000 -#define NVOS32_ATTR_TILED_REQUIRED 0x00000001 -#define NVOS32_ATTR_TILED_ANY 0x00000002 -#define NVOS32_ATTR_TILED_DEFERRED 0x00000003 - // Zcull region (NV40 and up) // If ATTR_ZCULL is REQUIRED or ANY and ATTR_DEPTH is UNKNOWN, the // allocation will fail. @@ -1026,6 +1019,14 @@ typedef struct #define NVOS32_ATTR_COMPR_PLC_ANY NVOS32_ATTR_COMPR_ANY #define NVOS32_ATTR_COMPR_DISABLE_PLC_ANY 0x00000003 +// +// Force the allocation to go to the reserved heap. +// This flag is used for KMD allocations when MIG is enabled. +// +#define NVOS32_ATTR_ALLOCATE_FROM_RESERVED_HEAP 14:14 +#define NVOS32_ATTR_ALLOCATE_FROM_RESERVED_HEAP_NO 0x00000000 +#define NVOS32_ATTR_ALLOCATE_FROM_RESERVED_HEAP_YES 0x00000001 + // Format // _BLOCK_LINEAR is only available for nv50+. #define NVOS32_ATTR_FORMAT 17:16 @@ -1169,12 +1170,15 @@ typedef struct #define NVOS32_ATTR2_32BIT_POINTER_ENABLE 0x00000001 // -// Indicates address conversion to be used, which affects what -// pitch alignment needs to be used +// Whether or not a NUMA Node ID has been specified. +// If yes, the NUMA node ID specified in numaNode will be used. +// If no, memory can be allocated from any socket (numaNode will be ignored). +// Specified numaNode must be of a CPU's memory // -#define NVOS32_ATTR2_TILED_TYPE 7:7 -#define NVOS32_ATTR2_TILED_TYPE_LINEAR 0x00000000 -#define NVOS32_ATTR2_TILED_TYPE_XY 0x00000001 + +#define NVOS32_ATTR2_FIXED_NUMA_NODE_ID 7:7 +#define NVOS32_ATTR2_FIXED_NUMA_NODE_ID_NO 0x00000000 +#define NVOS32_ATTR2_FIXED_NUMA_NODE_ID_YES 0x00000001 // // Force SMMU mapping on GPU physical allocation in Tegra @@ -1316,6 +1320,14 @@ typedef struct #define NVOS32_ATTR2_ALLOCATE_FROM_SUBHEAP_NO 0x00000000 #define NVOS32_ATTR2_ALLOCATE_FROM_SUBHEAP_YES 0x00000001 +// +// When allocating memory, register the memory descriptor to GSP-RM +// so that GSP-RM is aware of and can access it +// +#define NVOS32_ATTR2_REGISTER_MEMDESC_TO_PHYS_RM 31:31 +#define NVOS32_ATTR2_REGISTER_MEMDESC_TO_PHYS_RM_FALSE 0x00000000 +#define NVOS32_ATTR2_REGISTER_MEMDESC_TO_PHYS_RM_TRUE 0x00000001 + /** * NVOS32 ALLOC_FLAGS * @@ -1631,6 +1643,8 @@ typedef struct NvU32 internalflags; // [IN] - internal flags to change allocation behaviors from internal paths NvU32 tag; // [IN] - memory tag used for debugging + + NvS32 numaNode; // [IN] - CPU NUMA node from which memory should be allocated } NV_MEMORY_ALLOCATION_PARAMS; /* @@ -1776,7 +1790,7 @@ typedef struct // - Used for controlling CPU addresses in CUDA's unified CPU+GPU virtual // address space // - Only valid on NvRmMapMemory -// - Only implemented on Linux +// - Implemented on Unix but not VMware #define NVOS33_FLAGS_MAP_FIXED 18:18 #define NVOS33_FLAGS_MAP_FIXED_DISABLE (0x00000000) #define NVOS33_FLAGS_MAP_FIXED_ENABLE (0x00000001) @@ -1794,9 +1808,10 @@ typedef struct // - When combined with MAP_FIXED, this allows the client to exert // significant control over the CPU heap // - Used in CUDA's unified CPU+GPU virtual address space -// - Only valid on NvRmMapMemory (specifies RM's behavior whenever the +// - Valid in nvRmUnmapMemory +// - Valid on NvRmMapMemory (specifies RM's behavior whenever the // mapping is destroyed, regardless of mechanism) -// - Only implemented on Linux +// - Implemented on Unix but not VMware #define NVOS33_FLAGS_RESERVE_ON_UNMAP 19:19 #define NVOS33_FLAGS_RESERVE_ON_UNMAP_DISABLE (0x00000000) #define NVOS33_FLAGS_RESERVE_ON_UNMAP_ENABLE (0x00000001) @@ -2551,6 +2566,7 @@ typedef struct { NvU32 size; NvU32 prohibitMultipleInstances; // Prohibit multiple allocations of OFA? + NvU32 engineInstance; } NV_OFA_ALLOCATION_PARAMETERS; #define NV04_ADD_VBLANK_CALLBACK (0x0000003D) diff --git a/src/common/shared/inc/g_vgpu_resman_specific.h b/src/common/shared/inc/g_vgpu_resman_specific.h index 02f0e520d8..22273b7c6c 100644 --- a/src/common/shared/inc/g_vgpu_resman_specific.h +++ b/src/common/shared/inc/g_vgpu_resman_specific.h @@ -14,10 +14,7 @@ static inline void _get_chip_id_for_alias_pgpu(NvU32 *dev_id, NvU32 *subdev_id) } vgpu_aliases[] = { { 0x20B5, 0x1642, 0x20B5, 0x1533 }, { 0x20B8, 0x1581, 0x20B5, 0x1533 }, - { 0x20B7, 0x1804, 0x20B7, 0x1532 }, - { 0x20B7, 0x1852, 0x20B7, 0x1532 }, { 0x20B9, 0x157F, 0x20B7, 0x1532 }, - { 0x20FD, 0x17F8, 0x20F5, 0x0 }, { 0x2330, 0x16C0, 0x2330, 0x16C1 }, }; diff --git a/src/common/shared/inc/nvdevid.h b/src/common/shared/inc/nvdevid.h index 08a32c3f5c..5dc62cbda3 100644 --- a/src/common/shared/inc/nvdevid.h +++ b/src/common/shared/inc/nvdevid.h @@ -86,6 +86,7 @@ #define NV_PCI_SUBID_VENDOR_SONY 0x104D #define NV_PCI_SUBID_VENDOR_BITLAND 0x1642 #define NV_PCI_SUBID_VENDOR_PC_PARTNER 0x174B +#define NV_PCI_SUBID_VENDOR_CAVIUM 0x177D #define NV_PCI_SUBID_VENDOR_NZXT 0x1D96 // XXX CKEANUP TO REMOVE IN FAVOR OF NV_PCI_SUBID_VENDOR_* @@ -288,10 +289,6 @@ // Intel Ivy Bridge E definitions #define DEVICE_ID_INTEL_0E00_HOST_BRIDGE 0x0E00 -// Intel Haswell definitions -#define DEVICE_ID_INTEL_0C00_HASWELL_HOST_BRIDGE 0x0C00 -#define DEVICE_ID_INTEL_0C04_HASWELL_HOST_BRIDGE 0x0C04 - // Intel PCH definitions #define DEVICE_ID_INTEL_9D10_PCH_BRIDGE 0x9d10 #define DEVICE_ID_INTEL_9D18_PCH_BRIDGE 0x9d18 @@ -446,6 +443,9 @@ #define FOXCONN_EINSTEIN_64_DEVID 0xA1C1 #define FOXCONN_EINSTEIN_64_SSDEVID 0x7270 +// Cavium, Inc. CN99xx [ThunderX2] [177d:af00] +#define CAVIUM_X2_DEVID 0xAF00 + // Lenovo Tomcat Workstation #define LENOVO_TOMCAT_DEVID 0x1B81 #define LENOVO_TOMCAT_SSDEVID 0x104e diff --git a/src/common/shared/nvstatus/nvstatus.c b/src/common/shared/nvstatus/nvstatus.c index e377dd9f9b..92c5d7af8f 100644 --- a/src/common/shared/nvstatus/nvstatus.c +++ b/src/common/shared/nvstatus/nvstatus.c @@ -24,11 +24,11 @@ #include "nvstatus.h" #if !defined(NV_PRINTF_STRING_SECTION) -#if defined(NVRM) && NVCPU_IS_RISCV64 +#if defined(NVRM) && NVOS_IS_LIBOS #define NV_PRINTF_STRING_SECTION __attribute__ ((section (".logging"))) -#else // defined(NVRM) && NVCPU_IS_RISCV64 +#else // defined(NVRM) && NVOS_IS_LIBOS #define NV_PRINTF_STRING_SECTION -#endif // defined(NVRM) && NVCPU_IS_RISCV64 +#endif // defined(NVRM) && NVOS_IS_LIBOS #endif // !defined(NV_PRINTF_STRING_SECTION) /* diff --git a/src/common/unix/common/inc/nv_common_utils.h b/src/common/unix/common/inc/nv_common_utils.h index a7701d1ac7..6b10e76982 100644 --- a/src/common/unix/common/inc/nv_common_utils.h +++ b/src/common/unix/common/inc/nv_common_utils.h @@ -25,6 +25,7 @@ #define __NV_COMMON_UTILS_H__ #include "nvtypes.h" +#include "nvmisc.h" #if !defined(TRUE) #define TRUE NV_TRUE @@ -95,4 +96,25 @@ static inline unsigned short PALETTE_DEPTH_SHIFT(unsigned short val, int depth) return NV_UNDER_REPLICATE(val, depth, 8); } +/* + * Use __builtin_ffs where it is supported, or provide an equivalent + * implementation for platforms like riscv where it is not. + */ +#if defined(__GNUC__) && !NVCPU_IS_RISCV64 +static inline int nv_ffs(int x) +{ + return __builtin_ffs(x); +} +#else +static inline int nv_ffs(int x) +{ + if (x == 0) + return 0; + + LOWESTBITIDX_32(x); + + return 1 + x; +} +#endif + #endif /* __NV_COMMON_UTILS_H__ */ diff --git a/src/common/unix/common/inc/nv_dpy_id.h b/src/common/unix/common/inc/nv_dpy_id.h index 7c50e97679..fe742a5114 100644 --- a/src/common/unix/common/inc/nv_dpy_id.h +++ b/src/common/unix/common/inc/nv_dpy_id.h @@ -32,6 +32,7 @@ #include "nvtypes.h" #include "nvmisc.h" +#include "nv_common_utils.h" #include /* NV_MAX_SUBDEVICES */ typedef struct { @@ -299,7 +300,7 @@ static inline int nvDpyIdListToNvControlVal(NVDpyIdList dpyIdList) static inline NVDpyId nvNvControlValToDpyId(int val) { NVDpyId dpyId; - dpyId.opaqueDpyId = (val == 0) ? 0 : 1 << (__builtin_ffs(val)-1); + dpyId.opaqueDpyId = (val == 0) ? 0 : 1 << (nv_ffs(val)-1); return dpyId; } @@ -316,7 +317,7 @@ static inline NVDpyIdList nvNvControlValToDpyIdList(int val) static inline NVDpyId nvNvU32ToDpyId(NvU32 val) { NVDpyId dpyId; - dpyId.opaqueDpyId = (val == 0) ? 0 : 1 << (__builtin_ffs(val)-1); + dpyId.opaqueDpyId = (val == 0) ? 0 : 1 << (nv_ffs(val)-1); return dpyId; } @@ -340,7 +341,7 @@ static inline NvU32 nvDpyIdListToNvU32(NVDpyIdList dpyIdList) /* Return the bit position of dpyId: a number in the range [0..31]. */ static inline NvU32 nvDpyIdToIndex(NVDpyId dpyId) { - return __builtin_ffs(dpyId.opaqueDpyId) - 1; + return nv_ffs(dpyId.opaqueDpyId) - 1; } /* Return a display ID that is not in the list passed in. */ @@ -352,7 +353,7 @@ static inline NVDpyId nvNewDpyId(NVDpyIdList excludeList) return nvInvalidDpyId(); } dpyId.opaqueDpyId = - 1U << (__builtin_ffs(~excludeList.opaqueDpyIdList) - 1); + 1U << (nv_ffs(~excludeList.opaqueDpyIdList) - 1); return dpyId; } diff --git a/src/common/unix/nvidia-push/interface/nvidia-push-utils.h b/src/common/unix/nvidia-push/interface/nvidia-push-utils.h index 7dfa8e2080..9eeb617b59 100644 --- a/src/common/unix/nvidia-push/interface/nvidia-push-utils.h +++ b/src/common/unix/nvidia-push/interface/nvidia-push-utils.h @@ -67,7 +67,7 @@ void nvPushAcquireTimelineSemaphore( NvU64 val); NvBool nvPushDecodeMethod(NvU32 header, NvU32 *count); -void nvPushSetObject(NvPushChannelPtr p, NvU32 subch, NvU32 object[NV_MAX_SUBDEVICES]); +void nvPushSetObject(NvPushChannelPtr p, NvU32 subch, NvU32 *object); void nvPushSetSubdeviceMask(NvPushChannelPtr p, NvU32 mask); void __nvPushMakeRoom(NvPushChannelPtr, NvU32 count); diff --git a/src/common/unix/nvidia-push/src/nvidia-push-init.c b/src/common/unix/nvidia-push/src/nvidia-push-init.c index db0b4c9afb..ad006591d5 100644 --- a/src/common/unix/nvidia-push/src/nvidia-push-init.c +++ b/src/common/unix/nvidia-push/src/nvidia-push-init.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/common/unix/nvidia-push/src/nvidia-push.c b/src/common/unix/nvidia-push/src/nvidia-push.c index e039fc46f7..c73e69f8d1 100644 --- a/src/common/unix/nvidia-push/src/nvidia-push.c +++ b/src/common/unix/nvidia-push/src/nvidia-push.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -971,7 +971,7 @@ static NvU32 GetSetObjectHandle(NvPushChannelPtr pChannel, NvU32 handle, } // Issue a SET_OBJECT method on the specified subchannel. -void nvPushSetObject(NvPushChannelPtr p, NvU32 subch, NvU32 object[NV_MAX_SUBDEVICES]) +void nvPushSetObject(NvPushChannelPtr p, NvU32 subch, NvU32 *object) { const NvPushDeviceRec *pDevice = p->pDevice; const NvU32 oldSubDevMask = p->currentSubDevMask; diff --git a/src/common/uproc/os/common/include/liblogdecode.h b/src/common/uproc/os/common/include/liblogdecode.h index eefb3e94af..c0c6862e78 100644 --- a/src/common/uproc/os/common/include/liblogdecode.h +++ b/src/common/uproc/os/common/include/liblogdecode.h @@ -141,11 +141,10 @@ typedef struct char lineBuffer[LIBOS_LOG_LINE_BUFFER_SIZE]; NvBool bSynchronousBuffer; NvBool bPtrSymbolResolve; + NvU8 lineLogLevel; - // Attempt to decode %s format arguments - // This requires all %s libos log arguments to be present in the logging elf, otherwise - // garbage output may be produced. - NvBool bDecodeStrFmt; + // Fall back to SHDR when a PDHR with %s argument is not found. + NvBool bDecodeStrShdr; #endif // LIBOS_LOG_DECODE_ENABLE #if defined(NVSYM_STANDALONE) && !defined(PROTODMP_BUILD) diff --git a/src/common/uproc/os/common/include/libos_log.h b/src/common/uproc/os/common/include/libos_log.h index 7aad0ea409..6cb781b43f 100644 --- a/src/common/uproc/os/common/include/libos_log.h +++ b/src/common/uproc/os/common/include/libos_log.h @@ -28,6 +28,11 @@ #include #include "libos_printf_arg.h" +#if defined(NVRM) +#include "nvctassert.h" +#include "utils/nvprintf_level.h" +#endif + /** * @brief The log metadata structures and format strings are stripped * These structures are emitted into the .logging section @@ -188,19 +193,49 @@ static inline LibosPrintfArgument LibosPrintfArgumentS64(NvS64 i) { LIBOS_LOG_BUILD_APPLY( \ LIBOS_MACRO_PASTE_EVAL(LIBOS_LOG_BUILD_, LIBOS_MACRO_GET_COUNT(__VA_ARGS__)), __VA_ARGS__) -#define LOG_LEVEL_INFO 0 -#define LOG_LEVEL_WARNING 1 -#define LOG_LEVEL_ERROR 2 +// Defines for clients that cannot include nvprintf.h +#define LOG_LEVEL_INFO 1 +#define LOG_LEVEL_WARNING 3 +#define LOG_LEVEL_ERROR 4 + +#if defined(NVRM) && !defined(NVOC) +// Verify log levels are in sync with RM +ct_assert(LOG_LEVEL_INFO == LEVEL_INFO); +ct_assert(LOG_LEVEL_WARNING == LEVEL_WARNING); +ct_assert(LOG_LEVEL_ERROR == LEVEL_ERROR); +#endif + +// +// Store string literal in LIBOS_SECTION_LOGGING so that it can be passed as %s format argument. +// This uses GNU statement expression extension. +// +#if defined(__GNUC__) +#define MAKE_LIBOS_LOGGING_STR(str) \ +({ \ + static LIBOS_SECTION_LOGGING const char libos_pvt_str[] = str; \ + libos_pvt_str; \ +}) +#else +#define MAKE_LIBOS_LOGGING_STR(str) str +#endif #define LIBOS_SECTION_LOGGING __attribute__((section(".logging"))) // The compiler used for Windows doesn't have access to the format attribute +#if defined(__GNUC__) __attribute__((format(printf, 1, 2))) +#endif static inline void gccFakePrintf(const char *pFmt, ...) { (void)pFmt; } +#if defined(DEBUG) +#define LIBOS_CHECK_PRINTF_FMT(...) gccFakePrintf(__VA_ARGS__) +#else +#define LIBOS_CHECK_PRINTF_FMT(...) +#endif // defined(DEBUG) + void LibosLogTokens(const libosLogMetadata * metadata, const LibosPrintfArgument * tokens, NvU64 count); /*! @@ -210,7 +245,8 @@ void LibosLogTokens(const libosLogMetadata * metadata, const LibosPrintfArgument #define LibosLog(level, ...) \ do \ { \ - gccFakePrintf(__VA_ARGS__); \ + if (0) \ + LIBOS_CHECK_PRINTF_FMT(__VA_ARGS__); \ static const LIBOS_SECTION_LOGGING char libos_pvt_format[] = {LIBOS_MACRO_FIRST(__VA_ARGS__)}; \ static const LIBOS_SECTION_LOGGING char libos_pvt_file[] = {__FILE__}; \ static const LIBOS_SECTION_LOGGING libosLogMetadata libos_pvt_meta = { \ @@ -260,6 +296,8 @@ void LibosLogTokens(const libosLogMetadata * metadata, const LibosPrintfArgument { \ static const LIBOS_SECTION_LOGGING_CONST char libos_pvt_format[] = {LIBOS_MACRO_FIRST(__VA_ARGS__)}; \ static const LIBOS_SECTION_LOGGING_CONST char libos_pvt_file[] = {__FILE__}; \ + if (0) \ + LIBOS_CHECK_PRINTF_FMT(__VA_ARGS__); \ LIBOS_LOGGING_AUX_METADATA_DUMP; \ static const LIBOS_SECTION_LOGGING_METADATA libosLogMetadata libos_pvt_meta = { \ .filename = &libos_pvt_file[0], \ diff --git a/src/common/uproc/os/libos-v3.1.0/lib/libdwarf.c b/src/common/uproc/os/libos-v3.1.0/lib/libdwarf.c index b9b5b545b0..bd33eefbae 100644 --- a/src/common/uproc/os/libos-v3.1.0/lib/libdwarf.c +++ b/src/common/uproc/os/libos-v3.1.0/lib/libdwarf.c @@ -112,7 +112,7 @@ enum */ LibosStatus LibosDebugResolverConstruct(LibosDebugResolver *pThis, LibosElfImage * image) { - + LibosElf64SectionHeader * debugLine = LibosElfFindSectionByName(image, ".debug_line"); if (!debugLine || LibosOk != LibosElfMapSection(image, debugLine, &pThis->debugLineStart, &pThis->debugLineEnd)) pThis->debugLineStart = pThis->debugLineEnd = 0; @@ -855,7 +855,7 @@ static void dwarfBuildARangeTable(LibosDebugResolver *pThis) // Table has been allocated -- fill it in. DwarfARangeTuple *pEntry = &pThis->arangeTable[nARangeEntries]; pEntry->address = combAddress; - pEntry->length = combLength; + pEntry->length = (NvU32)combLength; pEntry->arangeUnit = nUnit; } nARangeEntries++; @@ -919,6 +919,6 @@ static void dwarfSetARangeTableLineUnit(LibosDebugResolver *pThis, DwarfStream u for (; foundUnit == pThis->arangeTable[i].arangeUnit; i++) { pThis->arangeTable[i].lineUnitBuffer = unit.buffer; - pThis->arangeTable[i].lineUnitSize = unit.size; + pThis->arangeTable[i].lineUnitSize = (NvU32)unit.size; } } diff --git a/src/common/uproc/os/libos-v3.1.0/lib/liblogdecode.c b/src/common/uproc/os/libos-v3.1.0/lib/liblogdecode.c index 5f6e18c67e..104cc9654c 100644 --- a/src/common/uproc/os/libos-v3.1.0/lib/liblogdecode.c +++ b/src/common/uproc/os/libos-v3.1.0/lib/liblogdecode.c @@ -29,7 +29,8 @@ # include # include // size_t -# define printf(fmt, ...) portDbgExPrintfLevel(LEVEL_ERROR, fmt, ##__VA_ARGS__) +#define LIBOS_LOG_DECODE_PRINTF(level, fmt, ...) portDbgExPrintfLevel(level, fmt, ##__VA_ARGS__) + # define snprintf nvDbgSnprintf #else // NVRM @@ -56,24 +57,29 @@ # if defined(PROTODMP_BUILD) int logPrintf(const char *, ...); // Forward declaration. TODO: allow libos code to #include protodmp headers? -# define printf(fmt, ...) logPrintf(fmt, ##__VA_ARGS__) +# define LIBOS_LOG_DECODE_PRINTF(level, fmt, ...) logPrintf(fmt, ##__VA_ARGS__) # elif defined(NVSYM_STANDALONE) -# define printf(fmt, ...) fprintf(logDecode->fout, fmt, ##__VA_ARGS__) +# define LIBOS_LOG_DECODE_PRINTF(level, fmt, ...) fprintf(logDecode->fout, fmt, ##__VA_ARGS__) # elif defined(NVWATCH) # pragma warning(push) # pragma warning(disable : 4200) # pragma warning(disable : 4244) # pragma warning(disable : 4267) # define snprintf _snprintf -# define printf(fmt, ...) do { logDecode->dest += sprintf(logDecode->dest, fmt, ##__VA_ARGS__); } while (NV_FALSE) +# define LIBOS_LOG_DECODE_PRINTF(level, fmt, ...) do { logDecode->dest += sprintf(logDecode->dest, fmt, ##__VA_ARGS__); } while (NV_FALSE) # endif #endif // NVRM +#ifndef LIBOS_LOG_DECODE_PRINTF +#define LIBOS_LOG_DECODE_PRINTF(level, fmt, ...) printf(fmt, ...) +#endif + #include #include "nvtypes.h" #include "liblogdecode.h" +#include "utils/nvprintf_level.h" #if LIBOS_LOG_DECODE_ENABLE @@ -305,9 +311,18 @@ static void flush_line_buffer(LIBOS_LOG_DECODE *logDecode) { if (logDecode->curLineBufPtr != logDecode->lineBuffer) { + NvU8 logLevel = logDecode->lineLogLevel; + /* Make sure line is NULL terminated */ *logDecode->curLineBufPtr = 0; - printf("%s", logDecode->lineBuffer); + +#if defined(NVRM) + // Sanitize log level for live decoding from RM. + if (logLevel > NV_LEVEL_MAX) + logLevel = NV_LEVEL_MAX; +#endif + + LIBOS_LOG_DECODE_PRINTF(logLevel, "%s", logDecode->lineBuffer); logDecode->curLineBufPtr = logDecode->lineBuffer; } } @@ -440,6 +455,32 @@ static int getint(char **s) i = 10 * i + (**s - '0'); return i; } + +#if !defined(NVRM) +static const char* printfLevelToString(NvU32 level) +{ + switch (level) + { + case LEVEL_SILENT: + return " SILENT "; + case LEVEL_INFO: + return " INFO "; + case LEVEL_NOTICE: + return " NOTICE "; + case LEVEL_WARNING: + return " WARNING "; + case LEVEL_ERROR: + return " ERROR "; + case LEVEL_HW_ERROR: + return " HW_ERROR "; + case LEVEL_FATAL: + return " FATAL "; + default: + return " "; + } +} +#endif + static int libos_printf_a( LIBOS_LOG_DECODE *logDecode, LIBOS_LOG_DECODE_RECORD *pRec, const char *fmt, const char *filename) { @@ -522,8 +563,9 @@ static int libos_printf_a( snprintf( logDecode->curLineBufPtr, LIBOS_LOG_LINE_BUFFER_SIZE - 1, - "GPU%u %s-%s: %s(%u): ", - pRec->log->gpuInstance, logDecode->sourceName, pRec->log->taskPrefix, + "GPU%u%s%s-%s: %s(%u): ", + pRec->log->gpuInstance, printfLevelToString(pRec->meta->printLevel), + logDecode->sourceName, pRec->log->taskPrefix, filename, pRec->meta->lineNumber); logDecode->curLineBufPtr += portStringLength(logDecode->curLineBufPtr); } @@ -763,7 +805,7 @@ static int libos_printf_a( } goto print_string; case 's': - a = (char *)LibosElfMapVirtualString(&pRec->log->elfImage, (NvUPtr)arg.p, logDecode->bDecodeStrFmt); + a = (char *)LibosElfMapVirtualString(&pRec->log->elfImage, (NvUPtr)arg.p, logDecode->bDecodeStrShdr); if (!a) a = (char *)"(bad-pointer)"; print_string: @@ -863,12 +905,14 @@ static void libosPrintLogRecords(LIBOS_LOG_DECODE *logDecode, NvU64 *scratchBuff if (pRec->meta == NULL) { - printf( + LIBOS_LOG_DECODE_PRINTF(LEVEL_WARNING, "**** Bad metadata. Lost %lld entries from %s ****\n", valid_elements - index, logDecode->sourceName); return; } + logDecode->lineLogLevel = pRec->meta->printLevel; + // Locate format string format = LibosElfMapVirtualString(&pRec->log->elfImage, (NvU64)(NvUPtr)pRec->meta->format, NV_TRUE); if (!format) @@ -1004,7 +1048,7 @@ static void libosExtractLog_ReadRecord(LIBOS_LOG_DECODE *logDecode, LIBOS_LOG_DE // Sanity check meta data. if (pLog->record.meta == NULL || pLog->record.meta->argumentCount > LIBOS_LOG_MAX_ARGS) { - printf( + LIBOS_LOG_DECODE_PRINTF(LEVEL_WARNING, "**** Bad metadata. Lost %lld entries from %s-%s ****\n", pLog->putIter - previousPut, logDecode->sourceName, pLog->taskPrefix); goto error_ret; @@ -1040,7 +1084,7 @@ static void libosExtractLog_ReadRecord(LIBOS_LOG_DECODE *logDecode, LIBOS_LOG_DE buffer_wrapped: // Put pointer wrapped and caught up to us. This means we lost entries. - printf( + LIBOS_LOG_DECODE_PRINTF(LEVEL_WARNING, "**** Buffer wrapped. Lost %lld entries from %s-%s ****\n", pLog->putIter - pLog->previousPut, logDecode->sourceName, pLog->taskPrefix); @@ -1075,7 +1119,7 @@ static void libosExtractLogs_decode(LIBOS_LOG_DECODE *logDecode) if (!pLog->physicLogBuffer) { - printf("logDecode->physicLogBuffer is NULL\n"); + LIBOS_LOG_DECODE_PRINTF(LEVEL_ERROR, "logDecode->physicLogBuffer is NULL\n"); return; } @@ -1118,7 +1162,7 @@ static void libosExtractLogs_decode(LIBOS_LOG_DECODE *logDecode) // Record is not identical to previous record. if (dst < recSize) { - printf("**** scratch buffer overflow. lost entries ****\n"); + LIBOS_LOG_DECODE_PRINTF(LEVEL_WARNING, "**** scratch buffer overflow. lost entries ****\n"); break; } @@ -1346,11 +1390,11 @@ void libosLogAddLogEx(LIBOS_LOG_DECODE *logDecode, void *buffer, NvU64 bufferSiz if (logDecode->numLogBuffers >= LIBOS_LOG_MAX_LOGS) { - printf("LIBOS_LOG_DECODE::log array is too small. Increase LIBOS_LOG_MAX_LOGS.\n"); + LIBOS_LOG_DECODE_PRINTF(LEVEL_ERROR, "LIBOS_LOG_DECODE::log array is too small. Increase LIBOS_LOG_MAX_LOGS.\n"); return; } - i = logDecode->numLogBuffers++; + i = (NvU32)(logDecode->numLogBuffers++); pLog = &logDecode->log[i]; pLog->physicLogBuffer = (volatile NvU64 *)buffer; pLog->logBufferSize = bufferSize; @@ -1420,7 +1464,7 @@ void libosLogAddLogEx(LIBOS_LOG_DECODE *logDecode, void *buffer, NvU64 bufferSiz } else { - printf("nvlogAllocBuffer nowrap failed\n"); + LIBOS_LOG_DECODE_PRINTF(LEVEL_ERROR, "nvlogAllocBuffer nowrap failed\n"); } } else @@ -1458,7 +1502,7 @@ void libosLogAddLogEx(LIBOS_LOG_DECODE *logDecode, void *buffer, NvU64 bufferSiz } else { - printf("nvlogAllocBuffer wrap failed\n"); + LIBOS_LOG_DECODE_PRINTF(LEVEL_ERROR, "nvlogAllocBuffer wrap failed\n"); } #endif // LIBOS_LOG_TO_NVLOG } @@ -1573,12 +1617,12 @@ void libosLogInit(LIBOS_LOG_DECODE *logDecode, LibosElf64Header *elf, NvU64 elfS void libosLogInitEx( LIBOS_LOG_DECODE *logDecode, LibosElf64Header *elf, NvBool bSynchronousBuffer, - NvBool bPtrSymbolResolve, NvBool bDecodeStrFmt, NvU64 elfSize) + NvBool bPtrSymbolResolve, NvBool bDecodeStrShdr, NvU64 elfSize) { // Set extended config logDecode->bSynchronousBuffer = bSynchronousBuffer; logDecode->bPtrSymbolResolve = bPtrSymbolResolve; - logDecode->bDecodeStrFmt = bDecodeStrFmt; + logDecode->bDecodeStrShdr = bDecodeStrShdr; // Complete init libosLogInit(logDecode, elf, elfSize); @@ -1590,7 +1634,7 @@ void libosLogInit(LIBOS_LOG_DECODE *logDecode, void *elf, NvU64 elfSize) {} void libosLogInitEx( LIBOS_LOG_DECODE *logDecode, void *elf, - NvBool bSynchronousBuffer, NvBool bPtrSymbolResolve, NvBool bDecodeStrFmt, NvU64 elfSize) + NvBool bSynchronousBuffer, NvBool bPtrSymbolResolve, NvBool bDecodeStrShdr, NvU64 elfSize) { // No extended config to set when decode is disabled } diff --git a/src/nvidia-modeset/include/dp/nvdp-connector.h b/src/nvidia-modeset/include/dp/nvdp-connector.h index d44cf86a32..6f99db260a 100644 --- a/src/nvidia-modeset/include/dp/nvdp-connector.h +++ b/src/nvidia-modeset/include/dp/nvdp-connector.h @@ -53,21 +53,9 @@ NVDPLibModesetStatePtr nvDPLibCreateModesetState( void nvDPLibFreeModesetState(NVDPLibModesetStatePtr pDpLibModesetState); -void nvDPBeginValidation(NVDispEvoPtr pDispEvo); - -NvBool nvDPLibValidateTimings( - const NVDispEvoRec *pDispEvo, - const NvU32 head, - const NvU32 displayId, - const NVDpyIdList dpyIdList, - const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, - const enum NvKmsDpyAttributeColorBpcValue colorBpc, - const struct NvKmsModeValidationParams *pModeValidationParams, - const NVHwModeTimingsEvo *pTimings, - const NvBool b2Heads1Or, - NVDscInfoEvoRec *pDscInfo); - -NvBool nvDPEndValidation(NVDispEvoPtr pDispEvo); +NvBool nvDPLibIsModePossible(const NVDPLibConnectorRec *pDpLibConnector, + const NVDpLibIsModePossibleParamsRec *pParams, + NvU32 *pFailedHeadMask); NvBool nvDPValidateModeForDpyEvo( const NVDpyEvoRec *pDpyEvo, diff --git a/src/nvidia-modeset/include/dp/nvdp-device.h b/src/nvidia-modeset/include/dp/nvdp-device.h index 979aaa20c9..ef120ec2f7 100644 --- a/src/nvidia-modeset/include/dp/nvdp-device.h +++ b/src/nvidia-modeset/include/dp/nvdp-device.h @@ -36,6 +36,9 @@ NvBool nvDPGetEDID(const NVDpyEvoRec *pDpyEvo, void *buffer, unsigned int size); void nvDPGetDpyGUID(NVDpyEvoPtr pDpyEvo); void nvDPDpyFree(NVDpyEvoPtr pDpyEvo); NvBool nvDPDpyIsDscPossible(const NVDpyEvoRec *pDpyEvo); +NvBool nvDPDpyGetDpcdRevision(const NVDpyEvoRec *pDpyEvo, + unsigned int *major, + unsigned int *minor); #ifdef __cplusplus }; diff --git a/src/nvidia-modeset/include/g_nvkms-evo-states.h b/src/nvidia-modeset/include/g_nvkms-evo-states.h index 4250227717..828539a448 100644 --- a/src/nvidia-modeset/include/g_nvkms-evo-states.h +++ b/src/nvidia-modeset/include/g_nvkms-evo-states.h @@ -32,6 +32,11 @@ extern "C" { #endif void nvEvoStateStartNoLock(NVEvoSubDevPtr); +#if defined(DEBUG) +void nvEvoStateAssertNoLock(const NVEvoSubDevRec *); +#else +static inline void nvEvoStateAssertNoLock(const NVEvoSubDevRec *unused) { }; +#endif #ifdef __cplusplus }; diff --git a/src/nvidia-modeset/include/nvkms-ctxdma.h b/src/nvidia-modeset/include/nvkms-ctxdma.h new file mode 100644 index 0000000000..1ebb188096 --- /dev/null +++ b/src/nvidia-modeset/include/nvkms-ctxdma.h @@ -0,0 +1,42 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVKMS_CTXDMA_H__ +#define __NVKMS_CTXDMA_H__ + +#include "nvkms-types.h" +#include "nvkms-flip-workarea.h" + +NvBool nvCtxDmaRegisterPreSyncpt(NVDevEvoRec *pDevEvo, + struct NvKmsFlipWorkArea *pWorkArea); + +void nvCtxDmaFreeSyncptHandle(NVDevEvoRec *pDevEvo, NVEvoSyncpt *pSyncpt); + +NvU32 nvCtxDmaBind(NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChannel, NvU32 hCtxDma); + +void nvCtxDmaFree(NVDevEvoPtr pDevEvo, NvU32 deviceHandle, NvU32 *hDispCtxDma); + +NvU32 nvCtxDmaAlloc(NVDevEvoPtr pDevEvo, NvU32 *pCtxDmaHandle, + NvU32 memoryHandle, NvU32 localCtxDmaFlags, NvU64 limit); + +#endif /* __NVKMS_CTXDMA_H__ */ diff --git a/src/nvidia-modeset/include/nvkms-dma.h b/src/nvidia-modeset/include/nvkms-dma.h index 6e6f6c39d9..26f5e067af 100644 --- a/src/nvidia-modeset/include/nvkms-dma.h +++ b/src/nvidia-modeset/include/nvkms-dma.h @@ -60,7 +60,8 @@ void nvEvoResetCRC32Notifier(volatile NvU32 *pCRC32Notifier, NvU32 offset, NvU32 reset_base_bit, NvU32 reset_value); -NvBool nvEvoWaitForCRC32Notifier(volatile NvU32 *pCRC32Notifier, +NvBool nvEvoWaitForCRC32Notifier(const NVDevEvoPtr pDevEvo, + volatile NvU32 *pCRC32Notifier, NvU32 offset, NvU32 done_base_bit, NvU32 done_extent_bit, @@ -228,11 +229,7 @@ void nvDisableCoreInterlockUpdateState(NVDevEvoPtr pDevEvo, #define NV_UDISP_DMA_OPCODE 31:29 /* RWXUF */ #define NV_UDISP_DMA_OPCODE_METHOD 0x00000000 /* RW--V */ #define NV_UDISP_DMA_METHOD_COUNT 27:18 /* RWXUF */ -// Technically, the METHOD_OFFSET field is 13:2 for nvdisplay (classes c3*), -// and only 11:2 for older display classes. But, the higher bits were -// unused in the older classes, and we should never push any methods of that -// size on them anyway, so we always use the wider definition here. -#define NV_UDISP_DMA_METHOD_OFFSET 13:2 /* RWXUF */ +#define NV_UDISP_DMA_METHOD_OFFSET 15:2 /* RWXUF */ // Start an EVO method. static inline void nvDmaSetStartEvoMethod( diff --git a/src/nvidia-modeset/include/nvkms-dpy.h b/src/nvidia-modeset/include/nvkms-dpy.h index 4885fb2c1b..635a2dffb8 100644 --- a/src/nvidia-modeset/include/nvkms-dpy.h +++ b/src/nvidia-modeset/include/nvkms-dpy.h @@ -42,6 +42,8 @@ NVDpyEvoPtr nvAllocDpyEvo(NVDispEvoPtr pDispEvo, void nvFreeDpyEvo(NVDispEvoPtr pDispEvo, NVDpyEvoPtr pDpyEvo); NVConnectorEvoPtr nvGetConnectorFromDisp(NVDispEvoPtr pDispEvo, NVDpyId dpyId); +void nvDpyAssignSDRInfoFramePayload(NVT_HDR_INFOFRAME_PAYLOAD *pPayload); +void nvCancelSDRTransitionTimer(NVDpyEvoRec *pDpyEvo); void nvUpdateInfoFrames(NVDpyEvoRec *pDpyEvo); NvBool nvDpyRequiresDualLinkEvo(const NVDpyEvoRec *pDpyEvo, @@ -85,6 +87,8 @@ NVColorFormatInfoRec nvGetColorFormatInfo(const NVDpyEvoRec *pDpyEvo); NvU32 nvDpyGetPossibleApiHeadsMask(const NVDpyEvoRec *pDpyEvo); +NvBool nvDpyIsHDRCapable(const NVDpyEvoRec *pDpyEvo); + #ifdef __cplusplus }; #endif diff --git a/src/nvidia-modeset/include/nvkms-evo-states.h b/src/nvidia-modeset/include/nvkms-evo-states.h index 8d06c88180..ab34f2a675 100644 --- a/src/nvidia-modeset/include/nvkms-evo-states.h +++ b/src/nvidia-modeset/include/nvkms-evo-states.h @@ -40,6 +40,8 @@ typedef enum NVEvoLockSignal { } NVEvoLockSignal; typedef enum NVEvoLockAction { + NV_EVO_PROHIBIT_LOCK, + NV_EVO_PROHIBIT_LOCK_DISABLE, NV_EVO_LOCK_HEADS, NV_EVO_UNLOCK_HEADS, NV_EVO_ADD_FRAME_LOCK_SERVER, @@ -48,10 +50,6 @@ typedef enum NVEvoLockAction { NV_EVO_REM_FRAME_LOCK_HOUSE_SYNC, NV_EVO_ADD_FRAME_LOCK_CLIENT, NV_EVO_REM_FRAME_LOCK_CLIENT, - NV_EVO_ENABLE_VRR, - NV_EVO_DISABLE_VRR, - NV_EVO_ENABLE_MERGE_MODE, - NV_EVO_DISABLE_MERGE_MODE, NV_EVO_ADD_FRAME_LOCK_REF, NV_EVO_REM_FRAME_LOCK_REF, NV_EVO_ADD_SLI_SECONDARY, @@ -74,8 +72,6 @@ NvBool nvEvoUnRefFrameLockSli(NVDispEvoPtr pDispEvo, /* nvkms-hw-states.c */ -NvBool nvEvoLockHWStateNoChange(NVDispEvoPtr, NVEvoSubDevPtr, const NvU32 *pHeads); -NvBool nvEvoLockHWStateMergeMode(NVDispEvoPtr, NVEvoSubDevPtr, const NvU32 *pHeads); NvBool nvEvoLockHWStateNoLock(NVDispEvoPtr, NVEvoSubDevPtr, const NvU32 *pHeads); NvBool nvEvoLockHWStateLockHeads(NVDispEvoPtr, NVEvoSubDevPtr, const NvU32 *pHeads); NvBool nvEvoLockHWStateFrameLockClient(NVDispEvoPtr, NVEvoSubDevPtr, const NvU32 *pHeads); diff --git a/src/nvidia-modeset/include/nvkms-evo.h b/src/nvidia-modeset/include/nvkms-evo.h index 218de01e8d..e3f8a405ab 100644 --- a/src/nvidia-modeset/include/nvkms-evo.h +++ b/src/nvidia-modeset/include/nvkms-evo.h @@ -46,6 +46,8 @@ void nvEvoUpdateAndKickOff(const NVDispEvoRec *pDispEvo, NvBool sync, NVEvoUpdateState *updateState, NvBool releaseElv); void nvDoIMPUpdateEvo(NVDispEvoPtr pDispEvo, NVEvoUpdateState *updateState); +void nvEvoFlipUpdate(NVDispEvoPtr pDispEvo, + NVEvoUpdateState *updateState); void nvEvoArmLightweightSupervisor(NVDispEvoPtr pDispEvo, const NvU32 head, NvBool isVrr, @@ -96,9 +98,13 @@ NvU64 nvEvoGetFormatsWithEqualOrLowerUsageBound( void nvCancelLowerDispBandwidthTimer(NVDevEvoPtr pDevEvo); void nvScheduleLowerDispBandwidthTimer(NVDevEvoPtr pDevEvo); void nvAssertAllDpysAreInactive(NVDevEvoPtr pDevEvo); -void nvEvoLockStatePreModeset(NVDevEvoPtr pDevEvo, NvU32 *dispNeedsEarlyUpdate, - NVEvoUpdateState *updateState); +void nvEvoLockStatePreModeset(NVDevEvoPtr pDevEvo); void nvEvoLockStatePostModeset(NVDevEvoPtr pDevEvo, const NvBool doRasterLock); +NvBool nvSetFlipLockGroup(NVDevEvoRec *pDevEvo[NV_MAX_SUBDEVICES], + const struct NvKmsSetFlipLockGroupRequest *pRequest); +void nvEvoRemoveOverlappingFlipLockRequestGroupsForModeset( + NVDevEvoPtr pDevEvo, + const struct NvKmsSetModeRequest *pRequest); NvBool nvSetUsageBoundsEvo( NVDevEvoPtr pDevEvo, NvU32 sd, @@ -129,7 +135,7 @@ void nvSetDitheringEvo( NvBool nvEnableFrameLockEvo(NVDispEvoPtr pDispEvo); NvBool nvDisableFrameLockEvo(NVDispEvoPtr pDispEvo); NvBool nvQueryRasterLockEvo(const NVDpyEvoRec *pDpyEvo, NvS64 *val); -void nvInvalidateTopologiesEvo(void); +void nvInvalidateRasterLockGroupsEvo(void); NvBool nvSetFlipLockEvo(NVDpyEvoPtr pDpyEvo, NvS64 value); NvBool nvGetFlipLockEvo(const NVDpyEvoRec *pDpyEvo, NvS64 *pValue); NvBool nvAllowFlipLockEvo(NVDispEvoPtr pDispEvo, NvS64 value); @@ -227,6 +233,13 @@ NvBool nvValidateImpOneDispDowngrade( NvBool nvFrameLockServerPossibleEvo(const NVDpyEvoRec *pDpyEvo); NvBool nvFrameLockClientPossibleEvo(const NVDpyEvoRec *pDpyEvo); +NvBool nvEvoLUTNotifiersNeedCommit(NVDispEvoPtr pDispEvo); +int nvEvoCommitLUTNotifiers(NVDispEvoPtr pDispEvo); +void nvEvoClearStagedLUTNotifiers(NVDispEvoPtr pDispEvo); +void nvEvoStageLUTNotifier(NVDispEvoPtr pDispEvo, NvU32 apiHead); +NvBool nvEvoIsLUTNotifierComplete(NVDispEvoPtr pDispEvo, NvU32 apiHead); +void nvEvoWaitForLUTNotifier(const NVDispEvoPtr pDispEvo, NvU32 apiHead); + void nvEvoSetLut(NVDispEvoPtr pDispEvo, NvU32 apiHead, NvBool kickoff, const struct NvKmsSetLutCommonParams *pParams); NvBool nvValidateSetLutCommonParams( @@ -234,7 +247,7 @@ NvBool nvValidateSetLutCommonParams( const struct NvKmsSetLutCommonParams *pParams); NvBool nvChooseColorRangeEvo( - enum NvKmsOutputTf tf, + enum NvKmsOutputColorimetry colorimetry, const enum NvKmsDpyAttributeColorRangeValue requestedColorRange, const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, const enum NvKmsDpyAttributeColorBpcValue colorBpc, @@ -242,8 +255,9 @@ NvBool nvChooseColorRangeEvo( NvBool nvChooseCurrentColorSpaceAndRangeEvo( const NVDpyEvoRec *pDpyEvo, - enum NvYuv420Mode yuv420Mode, - enum NvKmsOutputTf tf, + const NVHwModeTimingsEvo *pHwTimings, + NvU8 hdmiFrlBpc, + enum NvKmsOutputColorimetry colorimetry, const enum NvKmsDpyAttributeRequestedColorSpaceValue requestedColorSpace, const enum NvKmsDpyAttributeColorRangeValue requestedColorRange, enum NvKmsDpyAttributeCurrentColorSpaceValue *pCurrentColorSpace, @@ -253,6 +267,7 @@ NvBool nvChooseCurrentColorSpaceAndRangeEvo( void nvUpdateCurrentHardwareColorSpaceAndRangeEvo( NVDispEvoPtr pDispEvo, const NvU32 head, + const enum NvKmsOutputColorimetry colorimetry, const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, const enum NvKmsDpyAttributeColorRangeValue colorRange, NVEvoUpdateState *pUpdateState); @@ -274,7 +289,6 @@ NVDevEvoPtr nvAllocDevEvo(const struct NvKmsAllocDeviceRequest *pRequest, NvU32 nvGetActiveSorMask(const NVDispEvoRec *pDispEvo); NvBool nvUpdateFlipLockEvoOneHead(NVDispEvoPtr pDispEvo, const NvU32 head, NvU32 *val, NvBool set, - NvBool *needsEarlyUpdate, NVEvoUpdateState *updateState); void nvEvoSetLUTContextDma(NVDispEvoPtr pDispEvo, @@ -317,9 +331,6 @@ void nvDPSerializerPostSetMode(NVDispEvoPtr pDispEvo, NvBool nvFramelockSetControlUnsyncEvo(NVDispEvoPtr pDispEvo, const NvU32 headMask, NvBool server); -NvBool nvIsHDRCapableHead(const NVDispEvoRec *pDispEvo, - NvU32 apiHead); - NvU32 nvGetHDRSrcMaxLum(const NVFlipChannelEvoHwState *pHwState); NvBool nvNeedsTmoLut(NVDevEvoPtr pDevEvo, @@ -389,6 +400,8 @@ NvBool nvEvoUse2Heads1OR(const NVDpyEvoRec *pDpyEvo, const NVHwModeTimingsEvo *pTimings, const struct NvKmsModeValidationParams *pParams); +NvU32 nvGetRefreshRate10kHz(const NVHwModeTimingsEvo *pTimings); + #ifdef __cplusplus }; #endif diff --git a/src/nvidia-modeset/include/nvkms-evo3.h b/src/nvidia-modeset/include/nvkms-evo3.h new file mode 100644 index 0000000000..974cfd8983 --- /dev/null +++ b/src/nvidia-modeset/include/nvkms-evo3.h @@ -0,0 +1,285 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVKMS_EVO_3_H__ +#define __NVKMS_EVO_3_H__ + +#include "nvkms-types.h" +#include "nv-float.h" +#include "nvkms-softfloat.h" +#include // NVC57D_CORE_CHANNEL_DMA + +#define NV_EVO3_X_EMULATED_SURFACE_MEMORY_FORMATS_C6 \ + (NVBIT64(NvKmsSurfaceMemoryFormatRF16GF16BF16XF16) | \ + NVBIT64(NvKmsSurfaceMemoryFormatX2B10G10R10)) + +#define NV_EVO3_SUPPORTED_DITHERING_MODES \ + ((1 << NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING_MODE_AUTO) | \ + (1 << NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING_MODE_DYNAMIC_2X2) | \ + (1 << NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING_MODE_STATIC_2X2) | \ + (1 << NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING_MODE_TEMPORAL)) + +#define NV_EVO3_SUPPORTED_CURSOR_COMP_BLEND_MODES \ + ((1 << NVKMS_COMPOSITION_BLENDING_MODE_OPAQUE) | \ + (1 << NVKMS_COMPOSITION_BLENDING_MODE_NON_PREMULT_ALPHA) | \ + (1 << NVKMS_COMPOSITION_BLENDING_MODE_PREMULT_ALPHA) | \ + (1 << NVKMS_COMPOSITION_BLENDING_MODE_NON_PREMULT_SURFACE_ALPHA) | \ + (1 << NVKMS_COMPOSITION_BLENDING_MODE_PREMULT_SURFACE_ALPHA)) + +#define NV_EVO3_DEFAULT_WINDOW_USAGE_BOUNDS_C5 \ + (DRF_DEF(C57D, _WINDOW_SET_WINDOW_USAGE_BOUNDS, _ILUT_ALLOWED, _TRUE) | \ + DRF_DEF(C57D, _WINDOW_SET_WINDOW_USAGE_BOUNDS, _TMO_LUT_ALLOWED, _TRUE)) + +// HW supports ratio = 1, 2 (downscaling), 4 (downscaling) +#define NUM_SCALER_RATIOS 3 + +// There are 16 phases stored in matrix, but HW can derive the values of phase +// +16 and -16 from phase 0. Therefore, SW loads phase +16/-16 in phase 0 coeff +// values. +// coeff values in phase 0. +#define NUM_TAPS5_COEFF_PHASES 16 + +// There are 5 coefficient values per phase (or matrix row), but SW doesn't need +// to upload c2. So, the value here is set to 4. +#define NUM_TAPS5_COEFF_VALUES 4 + +extern const NvU32 scalerTaps5Coeff[NUM_SCALER_RATIOS][NUM_TAPS5_COEFF_PHASES][NUM_TAPS5_COEFF_VALUES]; + +struct EvoClampRangeC5 { + NvU32 green, red_blue; +}; + +/* + * Converts FP32 to fixed point S5.14 coefficient format + */ +static inline NvU32 nvCscCoefConvertS514(float32_t x) +{ + /* more concisely, (NvS32)floor(x * 65536.0 + 2.0) */ + const NvS32 y = f32_to_i32(f32_mulAdd(x, + NvU32viewAsF32(NV_FLOAT_65536), + NvU32viewAsF32(NV_FLOAT_TWO)), + softfloat_round_min, FALSE); + return (NvU32)(0x001ffffc & clamp_S32(y, -0x100000, 0xfffff)); +} + +NvBool nvComputeMinFrameIdle( + const NVHwModeTimingsEvo *pTimings, + NvU16 *pLeadingRasterLines, + NvU16 *pTrailingRasterLines); + +void nvEvoSetControlC3(NVDevEvoPtr pDevEvo, int sd); + +void nvEvoORSetControlC3(NVDevEvoPtr pDevEvo, + const NVConnectorEvoRec *pConnectorEvo, + const enum nvKmsTimingsProtocol protocol, + const NvU32 orIndex, + const NvU32 headMask, + NVEvoUpdateState *updateState); + +NvU32 nvEvoGetPixelDepthC3(const enum nvKmsPixelDepth pixelDepth); + +NvBool nvEvoSetUsageBoundsC5(NVDevEvoPtr pDevEvo, NvU32 sd, NvU32 head, + const struct NvKmsUsageBounds *pUsage, + NVEvoUpdateState *updateState); + +void nvEvoUpdateC3(NVDevEvoPtr pDevEvo, + const NVEvoUpdateState *updateState, + NvBool releaseElv); + +void +nvEvoIsModePossibleC3(NVDispEvoPtr pDispEvo, + const NVEvoIsModePossibleDispInput *pInput, + NVEvoIsModePossibleDispOutput *pOutput); + +void nvEvoPrePostIMPC3(NVDispEvoPtr pDispEvo, NvBool isPre); + +void nvEvoSetNotifierC3(NVDevEvoRec *pDevEvo, + const NvBool notify, + const NvBool awaken, + const NvU32 notifier, + NVEvoUpdateState *updateState); + +NvBool nvEvoGetCapabilitiesC6(NVDevEvoPtr pDevEvo); + +void +nvEvoFlipC6(NVDevEvoPtr pDevEvo, + NVEvoChannelPtr pChannel, + const NVFlipChannelEvoHwState *pHwState, + NVEvoUpdateState *updateState, + NvBool bypassComposition); + +void nvEvoFlipTransitionWARC6(NVDevEvoPtr pDevEvo, NvU32 sd, NvU32 head, + const NVEvoSubDevHeadStateRec *pSdHeadState, + const NVFlipEvoHwState *pFlipState, + NVEvoUpdateState *updateState); + +void +nvEvoFillLUTSurfaceC5(NVEvoLutEntryRec *pLUTBuffer, + const NvU16 *red, + const NvU16 *green, + const NvU16 *blue, + int nColorMapEntries, int depth); + +void nvSetupOutputLUT5(NVDevEvoPtr pDevEvo, + const NVDispHeadStateEvoRec *pHeadState, + const int head, + NVLutSurfaceEvoPtr pLutSurfEvo, + NvBool enableBaseLut, + NvBool enableOutputLut, + NVEvoUpdateState *updateState, + NvBool bypassComposition, + NVSurfaceDescriptor **pSurfaceDesc, + NvU32 *lutSize, + NvBool *disableOcsc0, + NvU32 *fpNormScale, + NvBool *isLutModeVss); + +NvBool nvEvoGetHeadSetControlCursorValueC3(const NVDevEvoRec *pDevEvo, + const NVSurfaceEvoRec *pSurfaceEvo, + NvU32 *pValue); + +NvBool nvEvoValidateCursorSurfaceC3(const NVDevEvoRec *pDevEvo, + const NVSurfaceEvoRec *pSurfaceEvo); + +NvBool nvEvoValidateWindowFormatC6( + const enum NvKmsSurfaceMemoryFormat format, + const struct NvKmsRect *sourceFetchRect, + NvU32 *hwFormatOut); + +void nvEvoInitCompNotifierC3(const NVDispEvoRec *pDispEvo, int idx); + +NvBool nvEvoIsCompNotifierCompleteC3(NVDispEvoPtr pDispEvo, int idx); + +void nvEvoWaitForCompNotifierC3(const NVDispEvoRec *pDispEvo, int idx); + +void nvEvoInitChannel3(NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChannel); + +void nvInitScalerCoefficientsPrecomp5(NVEvoChannelPtr pChannel, + NvU32 coeff, NvU32 index); + +void nvEvoInitDefaultLutC5(NVDevEvoPtr pDevEvo); + +void nvEvoInitWindowMappingC5(const NVDispEvoRec *pDispEvo, + NVEvoModesetUpdateState *pModesetUpdateState); + +NvBool nvEvoIsChannelIdleC3(NVDevEvoPtr pDevEvo, + NVEvoChannelPtr pChan, + NvU32 sd, + NvBool *result); + +NvBool nvEvoIsChannelMethodPendingC3(NVDevEvoPtr pDevEvo, + NVEvoChannelPtr pChan, + NvU32 sd, + NvBool *result); + +NvBool nvEvoForceIdleSatelliteChannelC3( + NVDevEvoPtr pDevEvo, + const NVEvoIdleChannelState *idleChannelState); + +NvBool nvEvoForceIdleSatelliteChannelIgnoreLockC3( + NVDevEvoPtr pDevEvo, + const NVEvoIdleChannelState *idleChannelState); + +void nvEvoAccelerateChannelC3(NVDevEvoPtr pDevEvo, + NVEvoChannelPtr pChannel, + const NvU32 sd, + const NvBool trashPendingMethods, + const NvBool unblockMethodsInExecutation, + NvU32 *pOldAccelerators); + +void nvEvoResetChannelAcceleratorsC3(NVDevEvoPtr pDevEvo, + NVEvoChannelPtr pChannel, + const NvU32 sd, + const NvBool trashPendingMethods, + const NvBool unblockMethodsInExecutation, + NvU32 oldAccelerators); + +NvBool nvEvoAllocRmCtrlObjectC3(NVDevEvoPtr pDevEvo); + +void nvEvoFreeRmCtrlObjectC3(NVDevEvoPtr pDevEvo); + +void nvEvoSetImmPointOutC3(NVDevEvoPtr pDevEvo, + NVEvoChannelPtr pChannel, + NvU32 sd, + NVEvoUpdateState *updateState, + NvU16 x, NvU16 y); + +NvBool nvEvoQueryHeadCRC32_C3(NVDevEvoPtr pDevEvo, + NVEvoDmaPtr pDma, + NvU32 sd, + NvU32 entry_count, + CRC32NotifierCrcOut *crc32, + NvU32 *numCRC32); + +void nvEvoGetScanLineC3(const NVDispEvoRec *pDispEvo, + const NvU32 head, + NvU16 *pScanLine, + NvBool *pInBlankingPeriod); + +NvU32 nvEvoGetActiveViewportOffsetC3(NVDispEvoRec *pDispEvo, NvU32 head); + +NvBool nvEvoComputeWindowScalingTapsC5(const NVDevEvoRec *pDevEvo, + const NVEvoChannel *pChannel, + NVFlipChannelEvoHwState *pHwState); + +const struct NvKmsCscMatrix* nvEvoGetOCsc1MatrixC5(const NVDispHeadStateEvoRec *pHeadState); + +struct EvoClampRangeC5 nvEvoGetOCsc1ClampRange(const NVDispHeadStateEvoRec *pHeadState); + +void nvEvo3PickOCsc0(NVDispEvoPtr pDispEvo, const NvU32 head, struct NvKms3x4MatrixF32 *ocsc0Matrix); + +static inline const NVEvoScalerCaps* +nvEvoGetWindowScalingCapsC3(const NVDevEvoRec *pDevEvo) +{ + /* + * Use window 0 by default. This should be fine for now since precomp + * scaling will only be enabled on Orin, and all windows have the same + * capabilities on Orin. + * + * The mapping in this function can be updated if/when precomp scaling + * support is extended to other display architectures. + */ + return &pDevEvo->gpus[0].capabilities.window[0].scalerCaps; +} + +static inline NvU32 nvGetMaxPixelsFetchedPerLine(NvU16 inWidth, + NvU16 maxHDownscaleFactor) +{ + /* + * Volta should be: + * (((SetViewportSizeIn.Width + 6) * SetMaxInputScaleFactor.Horizontal + 1023 ) >> 10 ) + 6 + * + * Turing should be: + * (((SetViewportSizeIn.Width + 6) * SetMaxInputScaleFactor.Horizontal + 1023 ) >> 10 ) + 8 + * + * Ampere, which adds "overfetch" to have tiled displays / 2-head-1-OR use cases without + * visual artefacts at head boundaries: + * (((SetViewportSizeIn.Width + 14) * SetMaxInputScaleFactor.Horizontal + 1023) >> 10) + 8 + * + * We don't have to be super-precise when programming maxPixelsFetchedPerLine, + * so return realistic worst-case value. + */ + return (((inWidth + 14) * maxHDownscaleFactor + 1023) >> 10) + 8; +} + +#endif /* __NVKMS_EVO_3_H__ */ diff --git a/src/nvidia-modeset/include/nvkms-flip-workarea.h b/src/nvidia-modeset/include/nvkms-flip-workarea.h index 55794d34c0..2899192b76 100644 --- a/src/nvidia-modeset/include/nvkms-flip-workarea.h +++ b/src/nvidia-modeset/include/nvkms-flip-workarea.h @@ -29,12 +29,16 @@ typedef struct { struct { enum NvKmsOutputTf tf; + enum NvKmsOutputColorimetry colorimetry; + NvBool infoFrameOverride; + NvU32 staticMetadataLayerMask; enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace; enum NvKmsDpyAttributeColorBpcValue colorBpc; enum NvKmsDpyAttributeColorRangeValue colorRange; } hdr; struct NvKmsPoint viewPortPointIn; + struct NvKmsSetLutCommonParams lut; struct { NvU32 viewPortPointIn : 1; diff --git a/src/nvidia-modeset/include/nvkms-flip.h b/src/nvidia-modeset/include/nvkms-flip.h index 85cb0d2280..aac0d3181b 100644 --- a/src/nvidia-modeset/include/nvkms-flip.h +++ b/src/nvidia-modeset/include/nvkms-flip.h @@ -69,8 +69,6 @@ void nvApiHeadUpdateFlipLock(NVDevEvoRec *pDevEvo, const NvU32 apiHeadMaskPerSd[NVKMS_MAX_SUBDEVICES], const NvBool enable); -void nvCancelSDRTransitionTimer(NVDispApiHeadStateEvoRec *pApiHeadState); - NvBool nvIdleMainLayerChannelCheckIdleOneApiHead(NVDispEvoPtr pDispEvo, NvU32 apiHead); diff --git a/src/nvidia-modeset/include/nvkms-hdmi.h b/src/nvidia-modeset/include/nvkms-hdmi.h index eaebf5dc3b..674d0cbafe 100644 --- a/src/nvidia-modeset/include/nvkms-hdmi.h +++ b/src/nvidia-modeset/include/nvkms-hdmi.h @@ -43,6 +43,7 @@ void nvUpdateHdmiCaps(NVDpyEvoPtr pDpyEvo); void nvLogEdidCea861InfoEvo(NVDpyEvoPtr pDpyEvo, NVEvoInfoStringPtr pInfoString); NvBool nvDpyIsHdmiEvo(const NVDpyEvoRec *pDpyEvo); +NvBool nvDpyIsHdmiDepth30Evo(const NVDpyEvoRec *pDpyEvo); NvBool nvHdmi204k60HzRGB444Allowed(const NVDpyEvoRec *pDpyEvo, const struct NvKmsModeValidationParams *pParams, @@ -66,6 +67,7 @@ NvBool nvHdmiFrlQueryConfig(const NVDpyEvoRec *pDpyEvo, const NvBool b2Heads1Or, const struct NvKmsModeValidationParams *pValidationParams, HDMI_FRL_CONFIG *pConfig, + NvU8 *pHdmiFrlBpc, NVDscInfoEvoRec *pDscInfo); void nvHdmiFrlClearConfig(NVDispEvoRec *pDispEvo, NvU32 activeRmId); void nvHdmiFrlSetConfig(NVDispEvoRec *pDispEvo, NvU32 head); @@ -75,7 +77,8 @@ void nvHdmiDpConstructHeadAudioState(const NvU32 displayId, NVDispHeadAudioStateEvoRec *pAudioState); NvBool nvHdmiTimingsNeedFrl(const NVDpyEvoRec *pDpyEvo, - const NVHwModeTimingsEvo *pHwTimings); + const NVHwModeTimingsEvo *pHwTimings, + NvU8 bpc); static inline NvBool nvHdmiDpySupportsDsc(const NVDpyEvoRec *pDpyEvo) { diff --git a/src/nvidia-modeset/include/nvkms-headsurface-priv.h b/src/nvidia-modeset/include/nvkms-headsurface-priv.h index 854c1d5aa0..d799466ccf 100644 --- a/src/nvidia-modeset/include/nvkms-headsurface-priv.h +++ b/src/nvidia-modeset/include/nvkms-headsurface-priv.h @@ -481,6 +481,7 @@ static inline void HsIncrementNextIndex( } static inline void HsChangeSurfaceFlipRefCount( + NVDevEvoPtr pDevEvo, NVSurfaceEvoPtr pSurfaceEvo, NvBool increase) { @@ -488,7 +489,7 @@ static inline void HsChangeSurfaceFlipRefCount( if (increase) { nvEvoIncrementSurfaceRefCnts(pSurfaceEvo); } else { - nvEvoDecrementSurfaceRefCnts(pSurfaceEvo); + nvEvoDecrementSurfaceRefCnts(pDevEvo, pSurfaceEvo); } } } diff --git a/src/nvidia-modeset/include/nvkms-headsurface.h b/src/nvidia-modeset/include/nvkms-headsurface.h index 7e9eeb762c..a32b14b430 100644 --- a/src/nvidia-modeset/include/nvkms-headsurface.h +++ b/src/nvidia-modeset/include/nvkms-headsurface.h @@ -47,7 +47,7 @@ void nvHsUnmapSurfaceFromDevice( NVHsSurfacePtr nvHsAllocSurface( NVDevEvoRec *pDevEvo, - const NvBool requireCtxDma, + const NvBool requireDisplayHardwareAccess, const enum NvKmsSurfaceMemoryFormat format, const NvU32 widthInPixels, const NvU32 heightInPixels); @@ -121,7 +121,7 @@ void nvHsProcessPendingViewportFlips(NVDevEvoPtr pDevEvo); NVSurfaceEvoRec *nvHsGetNvKmsSurface(const NVDevEvoRec *pDevEvo, NvKmsSurfaceHandle surfaceHandle, - const NvBool requireCtxDma); + const NvBool requireDisplayHardwareAccess); #if NVKMS_PROCFS_ENABLE void nvHsProcFs( diff --git a/src/nvidia-modeset/include/nvkms-modeset-types.h b/src/nvidia-modeset/include/nvkms-modeset-types.h index 197f372b32..782c1c74f3 100644 --- a/src/nvidia-modeset/include/nvkms-modeset-types.h +++ b/src/nvidia-modeset/include/nvkms-modeset-types.h @@ -40,8 +40,10 @@ typedef struct { NVDispStereoParamsEvoRec stereo; NVDscInfoEvoRec dscInfo; NVDispHeadInfoFrameStateEvoRec infoFrame; - NvU8 allowFlipLockGroup; enum NvKmsOutputTf tf; + enum NvKmsOutputColorimetry colorimetry; + NvBool hdrInfoFrameOverride; + NvU32 hdrStaticMetadataLayerMask; NvBool colorSpaceSpecified : 1; NvBool colorRangeSpecified : 1; NvBool hs10bpcHint : 1; @@ -53,6 +55,7 @@ typedef struct { NVHwModeTimingsEvo timings; NVConnectorEvoRec *pConnectorEvo; HDMI_FRL_CONFIG hdmiFrlConfig; + NvU8 hdmiFrlBpc; NVDPLibModesetStatePtr pDpLibModesetState; NVDispHeadAudioStateEvoRec audio; } NVProposedModeSetHwStateOneHead; diff --git a/src/nvidia-modeset/include/nvkms-modeset-workarea.h b/src/nvidia-modeset/include/nvkms-modeset-workarea.h index 832e186718..a4db8b73ee 100644 --- a/src/nvidia-modeset/include/nvkms-modeset-workarea.h +++ b/src/nvidia-modeset/include/nvkms-modeset-workarea.h @@ -42,7 +42,6 @@ typedef struct { NvU32 assignedSorMask; } sd[NVKMS_MAX_SUBDEVICES]; NVHsConfig hsConfig; - NVEvoUpdateState earlyUpdateState; NVEvoModesetUpdateState modesetUpdateState; /* diff --git a/src/nvidia-modeset/include/nvkms-modeset.h b/src/nvidia-modeset/include/nvkms-modeset.h index b2095c732c..2fd91f4997 100644 --- a/src/nvidia-modeset/include/nvkms-modeset.h +++ b/src/nvidia-modeset/include/nvkms-modeset.h @@ -50,10 +50,14 @@ NvBool nvSetDispModeEvo(NVDevEvoPtr pDevEvo, typedef NvBool (*NVShutDownApiHeadsTestFunc)( const NVDispEvoRec *pDispEvo, - const NvU32 apiHead); + const NvU32 apiHead, + void *pData); void nvShutDownApiHeads(NVDevEvoPtr pDevEvo, - NVShutDownApiHeadsTestFunc pTestFunc); + struct NvKmsPerOpenDev *pOpenDev, + NVShutDownApiHeadsTestFunc pTestFunc, + void *pData, + NvBool doRasterLock); NVVBlankCallbackPtr nvApiHeadRegisterVBlankCallback(NVDispEvoPtr pDispEvo, diff --git a/src/nvidia-modeset/include/nvkms-prealloc-types.h b/src/nvidia-modeset/include/nvkms-prealloc-types.h index 61a99d4f2c..ddb4693d7e 100644 --- a/src/nvidia-modeset/include/nvkms-prealloc-types.h +++ b/src/nvidia-modeset/include/nvkms-prealloc-types.h @@ -42,6 +42,7 @@ enum NVPreallocType { PREALLOC_TYPE_MODE_SET_REPLY_TMP_USAGE_BOUNDS, PREALLOC_TYPE_VALIDATE_MODE_IMP_OUT_HW_MODE_TIMINGS, PREALLOC_TYPE_VALIDATE_MODE_TMP_USAGE_BOUNDS, + PREALLOC_TYPE_DPLIB_IS_MODE_POSSIBLE_PARAMS, PREALLOC_TYPE_MAX }; diff --git a/src/nvidia-modeset/include/nvkms-prealloc.h b/src/nvidia-modeset/include/nvkms-prealloc.h index 2616dce004..25266f3c94 100644 --- a/src/nvidia-modeset/include/nvkms-prealloc.h +++ b/src/nvidia-modeset/include/nvkms-prealloc.h @@ -24,6 +24,10 @@ #ifndef __NVKMS_PREALLOC_H__ #define __NVKMS_PREALLOC_H__ +#ifdef __cplusplus +extern "C" { +#endif + #include "nvkms-types.h" #include "nvkms-prealloc-types.h" @@ -33,4 +37,8 @@ void nvPreallocRelease(NVDevEvoPtr pDevEvo, enum NVPreallocType type); NvBool nvPreallocAlloc(NVDevEvoPtr pDevEvo); void nvPreallocFree(NVDevEvoPtr pDevEvo); +#ifdef __cplusplus +}; +#endif + #endif /* __NVKMS_PREALLOC_H__ */ diff --git a/src/nvidia-modeset/include/nvkms-private.h b/src/nvidia-modeset/include/nvkms-private.h index c337819e0a..0728fbb926 100644 --- a/src/nvidia-modeset/include/nvkms-private.h +++ b/src/nvidia-modeset/include/nvkms-private.h @@ -68,8 +68,6 @@ NVEvoApiHandlesRec *nvGetSurfaceHandlesFromOpenDev( struct NvKmsPerOpenDev *pOpenDev); const NVEvoApiHandlesRec *nvGetSurfaceHandlesFromOpenDevConst( const struct NvKmsPerOpenDev *pOpenDev); -NVDevEvoPtr nvGetDevEvoFromOpenDev( - const struct NvKmsPerOpenDev *pOpenDev); void nvKmsServiceNonStallInterrupt(void *dataPtr, NvU32 dataU32); diff --git a/src/nvidia-modeset/include/nvkms-rm.h b/src/nvidia-modeset/include/nvkms-rm.h index 336c6a140a..0178fc5d28 100644 --- a/src/nvidia-modeset/include/nvkms-rm.h +++ b/src/nvidia-modeset/include/nvkms-rm.h @@ -77,25 +77,16 @@ NvBool nvRMSyncEvoChannel( NvBool nvRMIdleBaseChannel(NVDevEvoPtr pDevEvo, NvU32 head, NvU32 sd, NvBool *stoppedBase); NvBool nvRmEvoClassListCheck(const NVDevEvoRec *pDevEvo, NvU32 classID); -NvU32 nvRmEvoBindDispContextDMA( - NVDevEvoPtr pDevEvo, - NVEvoChannelPtr pChannel, - NvU32 hCtxDma); -NvU32 nvRmEvoAllocateAndBindDispContextDMA( - NVDevEvoPtr pDevEvo, - NvU32 hMemory, - const enum NvKmsSurfaceMemoryLayout layout, - NvU64 limit); NvBool nvRmEvoAllocAndBindSyncpt( NVDevEvoRec *pDevEvo, NVEvoChannel *pChannel, NvU32 id, - NvU32 *pSyncptHandle, - NvU32 *pSyncptCtxDmaHandle); + NVSurfaceDescriptor *pSurfaceDesc, + NVEvoSyncpt *pEvoSyncpt); void nvRmEvoFreePreSyncpt(NVDevEvoRec *pDevEvo, NVEvoChannel *pChannel); -NvBool nvRmGarbageCollectSyncpts( - NVDevEvoRec *pDevEvo); +void nvRmFreeSyncptHandle(NVDevEvoRec *pDevEvo, + NVEvoSyncpt *pSyncpt); void nvRmEvoFreeSyncpt(NVDevEvoRec *pDevEvo, NVEvoSyncpt *pEvoSyncpt); void nvRmEvoFreeDispContextDMA(NVDevEvoPtr pDevEvo, @@ -153,6 +144,13 @@ void nvRmUnregisterBacklight(NVDispEvoRec *pDispEvo); void nvRmAllocCoreRGSyncpts(NVDevEvoPtr pDevEvo); void nvRmFreeCoreRGSyncpts(NVDevEvoPtr pDevEvo); +NvU32 nvRmAllocAndBindSurfaceDescriptor( + NVDevEvoPtr pDevEvo, + NvU32 hMemory, + const enum NvKmsSurfaceMemoryLayout layout, + NvU64 limit, + NVSurfaceDescriptor *pSurfaceDesc); + #ifdef __cplusplus }; #endif diff --git a/src/nvidia-modeset/include/nvkms-rmapi.h b/src/nvidia-modeset/include/nvkms-rmapi.h index a4f5cf6771..faadd8a61a 100644 --- a/src/nvidia-modeset/include/nvkms-rmapi.h +++ b/src/nvidia-modeset/include/nvkms-rmapi.h @@ -54,6 +54,14 @@ NvU32 nvRmApiControl( void *pParams, NvU32 paramsSize); +NvU32 nvRmApiDupObject2( + NvU32 hClient, + NvU32 hParent, + NvU32 *hObjectDest, + NvU32 hClientSrc, + NvU32 hObjectSrc, + NvU32 flags); + NvU32 nvRmApiDupObject( NvU32 hClient, NvU32 hParent, diff --git a/src/nvidia-modeset/include/nvkms-surface.h b/src/nvidia-modeset/include/nvkms-surface.h index 0a05242cd2..a6160dc9d2 100644 --- a/src/nvidia-modeset/include/nvkms-surface.h +++ b/src/nvidia-modeset/include/nvkms-surface.h @@ -47,7 +47,8 @@ void nvEvoIncrementSurfaceStructRefCnt(NVSurfaceEvoPtr pSurfaceEvo); void nvEvoDecrementSurfaceStructRefCnt(NVSurfaceEvoPtr pSurfaceEvo); void nvEvoIncrementSurfaceRefCnts(NVSurfaceEvoPtr pSurfaceEvo); -void nvEvoDecrementSurfaceRefCnts(NVSurfaceEvoPtr pSurfaceEvo); +void nvEvoDecrementSurfaceRefCnts(NVDevEvoPtr pDevEvo, + NVSurfaceEvoPtr pSurfaceEvo); NvBool nvEvoSurfaceRefCntsTooLarge(const NVSurfaceEvoRec *pSurfaceEvo); @@ -58,7 +59,7 @@ NVSurfaceEvoPtr nvEvoGetSurfaceFromHandle( const NvBool isUsedByCursorChannel, const NvBool isUsedByLayerChannel); -NVSurfaceEvoPtr nvEvoGetSurfaceFromHandleNoCtxDmaOk( +NVSurfaceEvoPtr nvEvoGetSurfaceFromHandleNoDispHWAccessOk( const NVDevEvoRec *pDevEvo, const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, NvKmsSurfaceHandle surfaceHandle); diff --git a/src/nvidia-modeset/include/nvkms-types.h b/src/nvidia-modeset/include/nvkms-types.h index c5c1433ff0..6291b2813e 100644 --- a/src/nvidia-modeset/include/nvkms-types.h +++ b/src/nvidia-modeset/include/nvkms-types.h @@ -150,7 +150,7 @@ typedef struct _NVSurfaceEvoRec NVSurfaceEvoRec, *NVSurfaceEvoPtr; typedef struct _NVDeferredRequestFifoRec *NVDeferredRequestFifoPtr; typedef struct _NVSwapGroupRec *NVSwapGroupPtr; typedef struct _NVEvoModesetUpdateState NVEvoModesetUpdateState; -typedef struct _NVEvoRasterLockTopology *RasterLockTopologyPtr; +typedef struct _NVLockGroup NVLockGroup; /* * _NVHs*EvoRec are defined in nvkms-headsurface-priv.h; they are intentionally @@ -174,10 +174,16 @@ typedef struct _NVEvoApiHandlesRec { NvU32 defaultSize; } NVEvoApiHandlesRec; +typedef struct _NVSurfaceDescriptor +{ + NvU32 ctxDmaHandle; + NvU64 iovaAddress; +} NVSurfaceDescriptor; + typedef struct _NVEvoDma { NvU32 memoryHandle; - NvU32 ctxHandle; + NVSurfaceDescriptor surfaceDesc; NvU64 limit; @@ -279,10 +285,6 @@ typedef struct { } NVEvoSorCaps; #define NV_EVO_NUM_SOR_CAPS 8 -typedef struct { -} NVEvoPiorCaps; -#define NV_EVO_NUM_PIOR_CAPS 4 - typedef struct { NvBool usable; NvBool csc0MatricesPresent; @@ -430,12 +432,14 @@ typedef struct { /*! basic syncpt structure used for pre and post syncpt usage */ typedef struct _NVEvoSyncpt { + /* syncpt is allocated */ + NvBool allocated; /*! syncpt id (only useful for post-syncpt) */ NvU32 id; /*! bitmask of channels using this syncpt */ NVEvoChannelMask channelMask; - /*! handle of context dma allocated to this syncpt */ - NvU32 hCtxDma; + /*! Surface descriptor for the syncpt */ + NVSurfaceDescriptor surfaceDesc; /*! handle of syncpt object */ NvU32 hSyncpt; /*! stores syncpt max value */ @@ -566,7 +570,6 @@ typedef struct _NVEvoCapabilities { NVEvoMiscCaps misc; NVEvoHeadCaps head[NV_EVO_NUM_HEAD_CAPS]; NVEvoSorCaps sor[NV_EVO_NUM_SOR_CAPS]; - NVEvoPiorCaps pior[NV_EVO_NUM_PIOR_CAPS]; NVEvoWindowCaps window[NV_EVO_NUM_WINDOW_CAPS]; } NVEvoCapabilities; @@ -595,7 +598,8 @@ typedef struct { NvU32 preSyncpt; NvU32 preValue; - NvU32 postCtxDma; + NvBool isPostSyncptSpecified; + NVSurfaceDescriptor surfaceDesc; NvU32 postValue; } syncpts; } u; @@ -649,7 +653,9 @@ typedef struct { NvBool enabled; } hdrStaticMetadata; - enum NvKmsInputColorSpace colorspace; + enum NvKmsInputColorSpace colorSpace; + + enum NvKmsInputColorRange colorRange; struct { NvBool specified; @@ -692,6 +698,14 @@ typedef struct { NvBool disableMidFrameAndDWCFWatermark; enum NvKmsOutputTf tf; + struct { + NvBool enabled; + enum NvKmsInfoFrameEOTF eotf; + struct NvKmsHDRStaticMetadata staticMetadata; + } hdrInfoFrame; + + enum NvKmsOutputColorimetry colorimetry; + NvBool skipLayerPendingFlips[NVKMS_MAX_LAYERS_PER_HEAD]; struct { @@ -700,6 +714,7 @@ typedef struct { NvBool cursorPosition : 1; NvBool tf : 1; NvBool hdrStaticMetadata : 1; + NvBool colorimetry : 1; NvBool layerPosition[NVKMS_MAX_LAYERS_PER_HEAD]; NvBool layerSyncObjects[NVKMS_MAX_LAYERS_PER_HEAD]; @@ -707,17 +722,17 @@ typedef struct { } dirty; } NVFlipEvoHwState; -enum NvKmsHDROutputState { - NVKMS_HDR_OUTPUT_STATE_SDR = 0, - NVKMS_HDR_OUTPUT_STATE_HDR = 1, - NVKMS_HDR_OUTPUT_STATE_TRANSITIONING_TO_SDR = 2, +/* + * XXX Default to NVKMS_HDR_INFOFRAME_STATE_TRANSITIONING to send SDR + * infoframe for 2 seconds to WAR issue where some displays may remain in HDR + * mode after head has been previously shut down. + */ +enum NvKmsHDRInfoFrameState { + NVKMS_HDR_INFOFRAME_STATE_TRANSITIONING = 0, + NVKMS_HDR_INFOFRAME_STATE_DISABLED = 1, + NVKMS_HDR_INFOFRAME_STATE_ENABLED = 2, }; -/*! - * State requested through the NVKMS API. This may differ from - * the current hardware state (e.g., if the head has been - * momentarily blanked during DP link training). - */ typedef struct _NVEvoSubDevHeadStateRec { struct NvKmsPoint viewPortPointIn; NVFlipCursorEvoHwState cursor; @@ -840,7 +855,6 @@ typedef struct _NVEvoSubDevRec { NVEvoLockPin sliServerLockPin; NVEvoLockPin sliClientLockPin; - NvBool forceZeroClientLockoutWindow; } NVEvoSubDevRec; typedef struct _NVEvoColorRec { @@ -982,6 +996,13 @@ typedef struct _NVEvoDevRec { */ NvBool modesetOwnerChanged; + /*! + * modesetSubOwner points to the pOpenDev of the client that called + * NVKMS_IOCTL_ACQUIRE_PERMISSIONS with a file descriptor that grants + * NV_KMS_PERMISSIONS_TYPE_SUB_OWNER. + */ + const struct NvKmsPerOpenDev *modesetSubOwner; + /*! * NVEvoDevRec::numSubDevices is the number of GPUs in the SLI * device. This is the number of NVEvoSubDevPtrs in @@ -1201,6 +1222,30 @@ typedef struct _NVEvoDevRec { NVLutSurfaceEvoPtr defaultLut; enum NvKmsLUTState defaultBaseLUTState[NVKMS_MAX_SUBDEVICES]; enum NvKmsLUTState defaultOutputLUTState[NVKMS_MAX_SUBDEVICES]; + + /* + * Track outstanding LUT notifiers. Each notifier can have any number + * of apiHeads waiting on it. + * + * waitingApiHeadMask tracks all apiHeads waiting on a LUT notifier. + * stagedApiHeadMask tracks a set of apiHeads that will be tracked by + * the next LUT notifier kickoff. + * + * notifiers is an array of trackers for specific core + * notifiers. If notifiers[i].waiting is true, then the apiHeads listed + * in notifiers[i].apiHeadMask are waiting on notifiers[i].notifier. + */ + struct { + struct { + NvU32 waitingApiHeadMask; + NvU32 stagedApiHeadMask; + struct { + int notifier; + NvU32 apiHeadMask; + NvBool waiting; + } notifiers[NVKMS_MAX_HEADS_PER_DISP]; + } sd[NVKMS_MAX_SUBDEVICES]; + } notifierState; } lut; /*! stores pre-syncpts */ @@ -1614,6 +1659,19 @@ NvBool nvIsConnectorActiveEvo(const NVConnectorEvoRec *pConnectorEvo) (pConnectorEvo->or.ownerHeadMask[pConnectorEvo->or.primary] != 0x0); } +typedef struct _NVDpLibIsModePossibleParamsRec { + struct { + NvU32 displayId; + NVDpyIdList dpyIdList; + enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace; + enum NvKmsDpyAttributeColorBpcValue colorBpc; + const struct NvKmsModeValidationParams *pModeValidationParams; + const NVHwModeTimingsEvo *pTimings; + NvBool b2Heads1Or; + NVDscInfoEvoRec *pDscInfo; + } head[NV_MAX_HEADS]; +} NVDpLibIsModePossibleParamsRec; + typedef struct _NVDpyAttributeCurrentDitheringConfigRec { NvBool enabled; enum NvKmsDpyAttributeCurrentDitheringDepthValue depth; @@ -1732,14 +1790,6 @@ typedef struct _NVDispHeadStateEvoRec { /*! Cached, to preserve across modesets. */ struct NvKmsModeValidationParams modeValidationParams; - /* - * Heads on the same NVDevEvoRec with the same non-zero - * NVDispHeadStateEvoRec::allowFlipLockGroup value are eligible to - * be flipLocked, from an NVKMS client point of view, if the - * hardware requirements for flipLock are met. - */ - NvU8 allowFlipLockGroup; - /* * For Turing and newer, enable display composition bypass mode. * @@ -1768,6 +1818,7 @@ typedef struct _NVDispHeadStateEvoRec { NVConnectorEvoRec *pConnectorEvo; /* NULL if the head is not active */ HDMI_FRL_CONFIG hdmiFrlConfig; + NvU8 hdmiFrlBpc; NVDscInfoEvoRec dscInfo; @@ -1777,10 +1828,19 @@ typedef struct _NVDispHeadStateEvoRec { enum NvKmsOutputTf tf; + enum NvKmsOutputColorimetry colorimetry; + + struct { + NvBool enabled; + enum NvKmsInfoFrameEOTF eotf; + struct NvKmsHDRStaticMetadata staticMetadata; + } hdrInfoFrameOverride; + struct { - enum NvKmsHDROutputState outputState; + enum NvKmsHDRInfoFrameState state; + enum NvKmsInfoFrameEOTF eotf; struct NvKmsHDRStaticMetadata staticMetadata; - } hdr; + } hdrInfoFrame; struct { NVLutSurfaceEvoPtr pCurrSurface; @@ -1825,7 +1885,11 @@ typedef struct _NVDispApiHeadStateEvoRec { NVAttributesSetEvoRec attributes; enum NvKmsOutputTf tf; - nvkms_timer_handle_t *hdrToSdrTransitionTimer; + + enum NvKmsOutputColorimetry colorimetry; + + NvBool hdrInfoFrameOverride; + NvU32 hdrStaticMetadataLayerMask; /* * Hardware timings which are split across hardware heads. @@ -1941,6 +2005,17 @@ typedef struct _NVDispEvoRec { /* NVDevEvoRec::pSwapGroup[] is indexed by the api heads */ NVSwapGroupPtr pSwapGroup[NVKMS_MAX_HEADS_PER_DISP]; + /* If cross-GPU rasterlock is possible with the currently-active + * configuration */ + NvBool rasterLockPossible; + + /* + * This points to an *active* lock group (i.e., a set of 1 or more pDisps + * across which rasterlock -- and possibly fliplock -- is currently + * enabled), or NULL if no lock group is active on this pDisp. + */ + NVLockGroup *pLockGroup; + /*! * ref_ptr to the structure. * @@ -2079,6 +2154,8 @@ typedef struct _NVDpyEvoRec { NVAttributesSetEvoRec currentAttributes; + nvkms_timer_handle_t *hdrToSdrTransitionTimer; + struct { char *addressString; NVDPLibDevicePtr pDpLibDevice; // DP Lib's notion of the device. @@ -2306,7 +2383,7 @@ static inline NvBool nvApiHeadIsActive(const NVDispEvoRec *pDispEvo, /*! * Return the mask of active heads on this pDispEvo. */ -static inline NvU32 nvGetActiveHeadMask(NVDispEvoPtr pDispEvo) +static inline NvU32 nvGetActiveHeadMask(const NVDispEvoRec *pDispEvo) { NvU32 head; NvU32 headMask = 0; @@ -2389,7 +2466,7 @@ typedef struct _NVLutSurfaceEvo { NvU32 handle; NvU32 size; - NvU32 dispCtxDma; + NVSurfaceDescriptor surfaceDesc; NvU32 allocRefCnt; /* Only used for dynamically allocated LUTs */ @@ -2541,23 +2618,24 @@ enum NvHsMapPermissions { struct _NVSurfaceEvoRec { /* - * By default, all NVSurfaceEvoRecs will have requireCtxDma == TRUE, and - * have a ctxDma allocated and placed in the display engine hash table for - * each plane. + * By default, all NVSurfaceEvoRecs will have requireDisplayHardwareAccess + * as TRUE and on chips where ctxDma is supported, a ctxDma is allocated + * and placed in the display engine hash table for each plane. * * But, if the client specified the noDisplayHardwareAccess flag, - * requireCtxDma will be FALSE, and ctxDma will be 0 for all planes. + * requireDisplayHardwareAccess will be FALSE, and ctxDma will be 0 for + * all planes. * - * requireCtxDma is used to remember what the client requested, so that - * we correctly honor noDisplayHardwareAccess across + * requireDisplayHardwareAccess is used to remember what the client + * requested, so that we correctly honor noDisplayHardwareAccess across * FreeSurfaceCtxDmasForAllOpens() / * AllocSurfaceCtxDmasForAllOpens() cycles. */ - NvBool requireCtxDma; + NvBool requireDisplayHardwareAccess; struct { NvU32 rmHandle; - NvU32 ctxDma; + NVSurfaceDescriptor surfaceDesc; NvU32 pitch; NvU64 offset; NvU64 rmObjectSizeInBytes; @@ -2699,10 +2777,6 @@ typedef struct { #endif struct NvKmsPerOpen *nvKmsPerOpen; - - RasterLockTopologyPtr globalTopologies; - NvU32 numGlobalTopos; - } NVEvoGlobal; extern NVEvoGlobal nvEvoGlobal; @@ -2956,7 +3030,7 @@ typedef const struct _nv_evo_hal { NvU16 rasterLine, NvU32 head, NvU32 semaphoreIndex, - NvU32 hCtxDma, + const NVSurfaceDescriptor *pSurfaceDesc, NVEvoUpdateState* pUpdateState); void (*SetDscParams) (const NVDispEvoRec *pDispEvo, @@ -2986,13 +3060,60 @@ typedef const struct _nv_evo_hal { const NVEvoMergeMode mode, NVEvoUpdateState* pUpdateState); + NvU32 (*AllocSurfaceDescriptor) (NVDevEvoPtr pDevEvo, + NVSurfaceDescriptor *pSurfaceDesc, + NvU32 memoryHandle, + NvU32 localCtxDmaFlags, + NvU64 limit); + + void (*FreeSurfaceDescriptor) (NVDevEvoPtr pDevEvo, + NvU32 deviceHandle, + NVSurfaceDescriptor *pSurfaceDesc); + + NvU32 (*BindSurfaceDescriptor) (NVDevEvoPtr pDevEvo, + NVEvoChannelPtr pChannel, + NVSurfaceDescriptor *pSurfaceDesc); + + void (*SetTmoLutSurfaceAddress) (NVEvoChannelPtr pChannel, + const NVSurfaceDescriptor *pSurfaceDesc, + NvU32 offset); + + void (*SetILUTSurfaceAddress) (NVEvoChannelPtr pChannel, + const NVSurfaceDescriptor *pSurfaceDesc, + NvU32 offset); + + void (*SetISOSurfaceAddress) (NVEvoChannelPtr pChannel, + const NVSurfaceDescriptor *pSurfaceDesc, + NvU32 offset, + NvU32 ctxDmaIdx, + NvBool isBlocklinear); + + void (*SetCoreNotifierSurfaceAddressAndControl) (NVEvoChannelPtr pChannel, + const NVSurfaceDescriptor *pSurfaceDesc, + NvU32 notifierOffset, + NvU32 ctrlVal); + + void (*SetWinNotifierSurfaceAddressAndControl) (NVEvoChannelPtr pChannel, + const NVSurfaceDescriptor *pSurfaceDesc, + NvU32 notifierOffset, + NvU32 ctrlVal); + + void (*SetSemaphoreSurfaceAddressAndControl) (NVEvoChannelPtr pChannel, + const NVSurfaceDescriptor *pSurfaceDesc, + NvU32 semaphoreOffset, + NvU32 ctrlVal); + + void (*SetAcqSemaphoreSurfaceAddressAndControl) (NVEvoChannelPtr pChannel, + const NVSurfaceDescriptor *pSurfaceDesc, + NvU32 semaphoreOffset, + NvU32 ctrlVal); + struct { NvU32 supportsNonInterlockedUsageBoundsUpdate :1; NvU32 supportsDisplayRate :1; NvU32 supportsFlipLockRGStatus :1; NvU32 needDefaultLutSurface :1; NvU32 hasUnorm16OLUT :1; - NvU32 supportsDigitalVibrance :1; NvU32 supportsImageSharpening :1; NvU32 supportsHDMIVRR :1; NvU32 supportsCoreChannelSurface :1; @@ -3004,6 +3125,7 @@ typedef const struct _nv_evo_hal { NvU32 supportsVblankSyncObjects :1; NvU32 requiresScalingTapsInBothDimensions :1; NvU32 supportsMergeMode :1; + NvU32 supportsHDMI10BPC :1; NvU32 supportedDitheringModes; size_t impStructSize; diff --git a/src/nvidia-modeset/include/nvkms-utils.h b/src/nvidia-modeset/include/nvkms-utils.h index e44394bb07..b75f88f0ce 100644 --- a/src/nvidia-modeset/include/nvkms-utils.h +++ b/src/nvidia-modeset/include/nvkms-utils.h @@ -91,7 +91,7 @@ static inline NvBool nvHasBitAboveMax(NvU32 bitmask, NvU8 max) * break; * } * - * if (nvExceedsTimeoutUSec(&startTime, TIMEOUT-IN-USEC)) { + * if (nvExceedsTimeoutUSec(pDevEvo, &startTime, TIMEOUT-IN-USEC)) { * break; * } * @@ -107,11 +107,16 @@ static inline NvBool nvHasBitAboveMax(NvU32 bitmask, NvU8 max) * needed). */ static inline NvBool nvExceedsTimeoutUSec( + const NVDevEvoRec *pDevEvo, NvU64 *pStartTime, NvU64 timeoutPeriod) { const NvU64 currentTime = nvkms_get_usec(); + if (nvIsEmulationEvo(pDevEvo)) { + return FALSE; + } + if (*pStartTime == 0) { *pStartTime = currentTime; return FALSE; diff --git a/src/nvidia-modeset/interface/nvkms-api-types.h b/src/nvidia-modeset/interface/nvkms-api-types.h index 7131b32b8a..f56195c193 100644 --- a/src/nvidia-modeset/interface/nvkms-api-types.h +++ b/src/nvidia-modeset/interface/nvkms-api-types.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -45,6 +45,11 @@ #define NVKMS_DEVICE_ID_TEGRA 0x0000ffff +#define NVKMS_MAX_SUPERFRAME_VIEWS 4 + +#define NVKMS_LOG2_LUT_ARRAY_SIZE 10 +#define NVKMS_LUT_ARRAY_SIZE (1 << NVKMS_LOG2_LUT_ARRAY_SIZE) + typedef NvU32 NvKmsDeviceHandle; typedef NvU32 NvKmsDispHandle; typedef NvU32 NvKmsConnectorHandle; @@ -179,6 +184,14 @@ enum NvKmsEventType { NVKMS_EVENT_TYPE_FLIP_OCCURRED, }; +enum NvKmsFlipResult { + NV_KMS_FLIP_RESULT_SUCCESS = 0, /* Success */ + NV_KMS_FLIP_RESULT_INVALID_PARAMS, /* Parameter validation failed */ + NV_KMS_FLIP_RESULT_IN_PROGRESS, /* Flip would fail because an outstanding + flip containing changes that cannot be + queued is in progress */ +}; + typedef enum { NV_EVO_SCALER_1TAP = 0, NV_EVO_SCALER_2TAPS = 1, @@ -221,6 +234,16 @@ struct NvKmsUsageBounds { } layer[NVKMS_MAX_LAYERS_PER_HEAD]; }; +/*! + * Per-component arrays of NvU16s describing the LUT; used for both the input + * LUT and output LUT. + */ +struct NvKmsLutRamps { + NvU16 red[NVKMS_LUT_ARRAY_SIZE]; /*! in */ + NvU16 green[NVKMS_LUT_ARRAY_SIZE]; /*! in */ + NvU16 blue[NVKMS_LUT_ARRAY_SIZE]; /*! in */ +}; + /* * A 3x4 row-major colorspace conversion matrix. * @@ -531,6 +554,18 @@ typedef struct { NvBool noncoherent; } NvKmsDispIOCoherencyModes; +enum NvKmsInputColorRange { + /* + * If DEFAULT is provided, driver will assume full range for RGB formats + * and limited range for YUV formats. + */ + NVKMS_INPUT_COLORRANGE_DEFAULT = 0, + + NVKMS_INPUT_COLORRANGE_LIMITED = 1, + + NVKMS_INPUT_COLORRANGE_FULL = 2, +}; + enum NvKmsInputColorSpace { /* Unknown colorspace; no de-gamma will be applied */ NVKMS_INPUT_COLORSPACE_NONE = 0, @@ -542,6 +577,12 @@ enum NvKmsInputColorSpace { NVKMS_INPUT_COLORSPACE_BT2100_PQ = 2, }; +enum NvKmsOutputColorimetry { + NVKMS_OUTPUT_COLORIMETRY_DEFAULT = 0, + + NVKMS_OUTPUT_COLORIMETRY_BT2100 = 1, +}; + enum NvKmsOutputTf { /* * NVKMS itself won't apply any OETF (clients are still @@ -552,6 +593,17 @@ enum NvKmsOutputTf { NVKMS_OUTPUT_TF_PQ = 2, }; +/*! + * EOTF Data Byte 1 as per CTA-861-G spec. + * This is expected to match exactly with the spec. + */ +enum NvKmsInfoFrameEOTF { + NVKMS_INFOFRAME_EOTF_SDR_GAMMA = 0, + NVKMS_INFOFRAME_EOTF_HDR_GAMMA = 1, + NVKMS_INFOFRAME_EOTF_ST2084 = 2, + NVKMS_INFOFRAME_EOTF_HLG = 3, +}; + /*! * HDR Static Metadata Type1 Descriptor as per CEA-861.3 spec. * This is expected to match exactly with the spec. @@ -605,4 +657,29 @@ struct NvKmsHDRStaticMetadata { NvU16 maxFALL; }; +/*! + * A superframe is made of two or more video streams that are combined in + * a specific way. A DP serializer (an external device connected to a Tegra + * ARM SOC over DP or HDMI) can receive a video stream comprising multiple + * videos combined into a single frame and then split it into multiple + * video streams. The following structure describes the number of views + * and dimensions of each view inside a superframe. + */ +struct NvKmsSuperframeInfo { + NvU8 numViews; + struct { + /* x offset inside superframe at which this view starts */ + NvU16 x; + + /* y offset inside superframe at which this view starts */ + NvU16 y; + + /* Horizontal active width in pixels for this view */ + NvU16 width; + + /* Vertical active height in lines for this view */ + NvU16 height; + } view[NVKMS_MAX_SUPERFRAME_VIEWS]; +}; + #endif /* NVKMS_API_TYPES_H */ diff --git a/src/nvidia-modeset/interface/nvkms-api.h b/src/nvidia-modeset/interface/nvkms-api.h index e1fa905d8f..99da27e79b 100644 --- a/src/nvidia-modeset/interface/nvkms-api.h +++ b/src/nvidia-modeset/interface/nvkms-api.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -267,6 +267,7 @@ enum NvKmsIoctlCommand { NVKMS_IOCTL_ENABLE_VBLANK_SYNC_OBJECT, NVKMS_IOCTL_DISABLE_VBLANK_SYNC_OBJECT, NVKMS_IOCTL_NOTIFY_VBLANK, + NVKMS_IOCTL_SET_FLIPLOCK_GROUP, }; @@ -291,8 +292,6 @@ enum NvKmsIoctlCommand { #define NVKMS_3DVISION_DONGLE_PARAM_BYTES 20 #define NVKMS_GPU_STRING_SIZE 80 -#define NVKMS_LOG2_LUT_ARRAY_SIZE 10 -#define NVKMS_LUT_ARRAY_SIZE (1 << NVKMS_LOG2_LUT_ARRAY_SIZE) #define NVKMS_VRR_SEMAPHORE_SURFACE_SIZE 1024 /* @@ -524,16 +523,6 @@ struct NvKmsMoveCursorCommonParams { NvS16 y; /*! in */ }; -/*! - * Per-component arrays of NvU16s describing the LUT; used for both the input - * LUT and output LUT. - */ -struct NvKmsLutRamps { - NvU16 red[NVKMS_LUT_ARRAY_SIZE]; /*! in */ - NvU16 green[NVKMS_LUT_ARRAY_SIZE]; /*! in */ - NvU16 blue[NVKMS_LUT_ARRAY_SIZE]; /*! in */ -}; - /*! * Description of the main layer LUT on a single head; this is used by any NVKMS * request that needs to specify the LUT. @@ -730,13 +719,12 @@ struct NvKmsFlipCommonParams { /* * Set the output transfer function. * - * If output transfer function is HDR and staticMetadata is disabled - * for all the layers, flip request will be rejected. + * If output transfer function is HDR and no staticMetadata is specified + * for the head or layers, flip request will be rejected. * - * If output transfer function is HDR and staticMetadata is enabled - * for any of the layers, HDR output will be enabled. In this case, - * output lut values specified during modeset will be ignored and - * output lut will be set with the specified HDR transfer function. + * If output transfer is set, output lut values specified during modeset + * will be ignored and output lut will be set with the specified HDR + * transfer function. * * If output transfer function is SDR and staticMetadata is enabled, * HDR content for that layer will be tonemapped to the SDR output @@ -747,6 +735,32 @@ struct NvKmsFlipCommonParams { NvBool specified; } tf; + /*! + * Describe the LUT to be used with the modeset or flip. + */ + struct NvKmsSetLutCommonParams lut; + + struct { + NvBool specified; + /*! + * If TRUE, override HDR static metadata for the head, instead of + * calculating it from HDR layer(s). If FALSE, do not override. + * + * Note that “specified” serves to mark the field as being changed in + * this flip request, rather than as specified for this frame. So to + * disable HDR static metadata, set hdrStaticMetadata.specified = TRUE + * and hdrStaticMetadata.enabled = FALSE. + */ + NvBool enabled; + enum NvKmsInfoFrameEOTF eotf; + struct NvKmsHDRStaticMetadata staticMetadata; + } hdrInfoFrame; + + struct { + NvBool specified; + enum NvKmsOutputColorimetry val; + } colorimetry; + struct { struct { NvKmsSurfaceHandle handle[NVKMS_MAX_EYES]; @@ -910,11 +924,17 @@ struct NvKmsFlipCommonParams { struct NvKmsHDRStaticMetadata staticMetadata; } hdr; + /* Specifies whether the input color range is FULL or LIMITED. */ + struct { + enum NvKmsInputColorRange val; + NvBool specified; + } colorRange; + /* This field has no effect right now. */ struct { enum NvKmsInputColorSpace val; NvBool specified; - } colorspace; + } colorSpace; } layer[NVKMS_MAX_LAYERS_PER_HEAD]; }; @@ -1450,6 +1470,8 @@ struct NvKmsQueryDpyDynamicDataReply { */ char infoString[NVKMS_EDID_INFO_STRING_LENGTH]; } edid; + + struct NvKmsSuperframeInfo superframeInfo; }; struct NvKmsQueryDpyDynamicDataParams { @@ -1782,11 +1804,6 @@ struct NvKmsSetModeOneHeadRequest { */ struct NvKmsSize viewPortSizeIn; - /*! - * Describe the LUT to be used with the modeset. - */ - struct NvKmsSetLutCommonParams lut; - /*! * Describe the surfaces to present on this head. */ @@ -1799,14 +1816,6 @@ struct NvKmsSetModeOneHeadRequest { NvBool viewPortOutSpecified; /*! Whether to use viewPortOut. */ - /*! - * Allow this head to be flipLocked to any other heads, set as - * part of this NVKMS_IOCTL_SET_MODE, who also have allowFlipLock - * set. FlipLock will only be enabled if additional criteria, - * such as identical modetimings, are also met. - */ - NvBool allowFlipLock; - /*! * Allow G-SYNC to be enabled on this head if it is supported by the GPU * and monitor. @@ -2180,6 +2189,11 @@ struct NvKmsFlipReply { */ enum NvKmsVrrFlipType vrrFlipType; + /*! + * Indicates either success or the reason the flip request failed. + */ + enum NvKmsFlipResult flipResult; + /*! * Entries correspond to the heads specified in * NvKmsFlipRequest::pFlipHead, in the same order. @@ -3181,6 +3195,11 @@ struct NvKmsSetLayerPositionParams { * * Releasing modeset ownership enables console hotplug handling. See the * explanation in the comment for enableConsoleHotplugHandling above. + * + * If modeset ownership is held by nvidia-drm, then NVKMS_IOCTL_GRAB_OWNERSHIP + * will fail. Clients should open the corresponding DRM device node, acquire + * 'master' on it, and then use DRM_NVIDIA_GRANT_PERMISSIONS with permission + * type NV_DRM_PERMISSIONS_TYPE_SUB_OWNER to acquire sub-owner permission. */ struct NvKmsGrabOwnershipRequest { @@ -3219,8 +3238,9 @@ struct NvKmsReleaseOwnershipParams { * successfully called NVKMS_IOCTL_GRAB_OWNERSHIP) is allowed to flip * or set modes. * - * However, the modeset owner can grant various permissions to other - * clients through the following steps: + * However, the modeset owner or another NVKMS client with + * NV_KMS_PERMISSIONS_TYPE_SUB_OWNER permission can grant various + * permissions to other clients through the following steps: * * - The modeset owner should open /dev/nvidia-modeset, and call * NVKMS_IOCTL_GRANT_PERMISSIONS to define a set of permissions @@ -3248,6 +3268,8 @@ struct NvKmsReleaseOwnershipParams { * - The modeset owner can optionally revoke any previously granted * permissions with NVKMS_IOCTL_REVOKE_PERMISSIONS. This can be * device-scope for all of a type, or just a set of permissions. + * Note that _REVOKE_PERMISSIONS to revoke a set of modeset permissions + * will cause the revoked heads to be shut down. * * Notes: * @@ -3269,6 +3291,7 @@ struct NvKmsReleaseOwnershipParams { enum NvKmsPermissionsType { NV_KMS_PERMISSIONS_TYPE_FLIPPING = 1, NV_KMS_PERMISSIONS_TYPE_MODESET = 2, + NV_KMS_PERMISSIONS_TYPE_SUB_OWNER = 3, }; struct NvKmsFlipPermissions { @@ -4016,4 +4039,44 @@ struct NvKmsNotifyVblankParams { struct NvKmsNotifyVblankReply reply; /*! out */ }; +/*! + * NVKMS_IOCTL_SET_FLIPLOCK_GROUP: + * + * This ioctl specifies a set of active heads on which fliplock is allowed. + * The heads can span devices. + * The requested state for this group will be maintained until: + * a) A subsequent SetFlipLockGroup ioctl that specifies any of the heads + * b) A subsequent ModeSet ioctl that specifies any of the heads + * If either of those occurs, the requested state will be destroyed for *all* + * of the heads. + * + * Note that a successful call with 'enable = TRUE' only indicates that the + * request to enable fliplock is registered, not that fliplock was actually + * enabled. Fliplock may not be enabled due to incompatible modetimings, for + * example. + */ + +struct NvKmsSetFlipLockGroupOneDev { + NvKmsDeviceHandle deviceHandle; + + NvU32 requestedDispsBitMask; + struct { + NvU32 requestedHeadsBitMask; + } disp[NVKMS_MAX_SUBDEVICES]; +}; + +struct NvKmsSetFlipLockGroupRequest { + NvBool enable; + struct NvKmsSetFlipLockGroupOneDev dev[NV_MAX_SUBDEVICES]; +}; + +struct NvKmsSetFlipLockGroupReply { + NvU32 padding; +}; + +struct NvKmsSetFlipLockGroupParams { + struct NvKmsSetFlipLockGroupRequest request; /*! in */ + struct NvKmsSetFlipLockGroupReply reply; /*! out */ +}; + #endif /* NVKMS_API_H */ diff --git a/src/nvidia-modeset/kapi/include/nvkms-kapi-internal.h b/src/nvidia-modeset/kapi/include/nvkms-kapi-internal.h index a0ba458992..91b9e9fc2a 100644 --- a/src/nvidia-modeset/kapi/include/nvkms-kapi-internal.h +++ b/src/nvidia-modeset/kapi/include/nvkms-kapi-internal.h @@ -174,4 +174,41 @@ void nvKmsKapiFreeChannelEvent(struct NvKmsKapiDevice *device, struct NvKmsKapiChannelEvent *cb); +struct NvKmsKapiSemaphoreSurface* +nvKmsKapiImportSemaphoreSurface(struct NvKmsKapiDevice *device, + NvU64 nvKmsParamsUser, + NvU64 nvKmsParamsSize, + void **pSemaphoreMap, + void **pMaxSubmittedMap); + +void +nvKmsKapiFreeSemaphoreSurface(struct NvKmsKapiDevice *device, + struct NvKmsKapiSemaphoreSurface *ss); + +NvKmsKapiRegisterWaiterResult +nvKmsKapiRegisterSemaphoreSurfaceCallback( + struct NvKmsKapiDevice *device, + struct NvKmsKapiSemaphoreSurface *semaphoreSurface, + NvKmsSemaphoreSurfaceCallbackProc *pCallback, + void *pData, + NvU64 index, + NvU64 wait_value, + NvU64 new_value, + struct NvKmsKapiSemaphoreSurfaceCallback **pCallbackHandle); + +NvBool +nvKmsKapiUnregisterSemaphoreSurfaceCallback( + struct NvKmsKapiDevice *device, + struct NvKmsKapiSemaphoreSurface *semaphoreSurface, + NvU64 index, + NvU64 wait_value, + struct NvKmsKapiSemaphoreSurfaceCallback *callbackHandle); + +NvBool +nvKmsKapiSetSemaphoreSurfaceValue( + struct NvKmsKapiDevice *device, + struct NvKmsKapiSemaphoreSurface *semaphoreSurface, + NvU64 index, + NvU64 new_value); + #endif /* __NVKMS_KAPI_INTERNAL_H__ */ diff --git a/src/nvidia-modeset/kapi/interface/nvkms-kapi-private.h b/src/nvidia-modeset/kapi/interface/nvkms-kapi-private.h index 8b1dab9014..cc0c4e3242 100644 --- a/src/nvidia-modeset/kapi/interface/nvkms-kapi-private.h +++ b/src/nvidia-modeset/kapi/interface/nvkms-kapi-private.h @@ -58,4 +58,10 @@ struct NvKmsKapiPrivExportMemoryParams { int memFd; }; +struct NvKmsKapiPrivImportSemaphoreSurfaceParams { + NvHandle hClient; + NvHandle hSemaphoreSurface; + NvU64 semaphoreSurfaceSize; +}; + #endif /* !defined(__NVKMS_KAPI_PRIVATE_H__) */ diff --git a/src/nvidia-modeset/kapi/interface/nvkms-kapi.h b/src/nvidia-modeset/kapi/interface/nvkms-kapi.h index cf0c2a5902..c487b4b786 100644 --- a/src/nvidia-modeset/kapi/interface/nvkms-kapi.h +++ b/src/nvidia-modeset/kapi/interface/nvkms-kapi.h @@ -49,6 +49,8 @@ struct NvKmsKapiDevice; struct NvKmsKapiMemory; struct NvKmsKapiSurface; struct NvKmsKapiChannelEvent; +struct NvKmsKapiSemaphoreSurface; +struct NvKmsKapiSemaphoreSurfaceCallback; typedef NvU32 NvKmsKapiConnector; typedef NvU32 NvKmsKapiDisplay; @@ -67,6 +69,14 @@ typedef NvU32 NvKmsKapiDisplay; */ typedef void NvKmsChannelEventProc(void *dataPtr, NvU32 dataU32); +/* + * Note: Same as above, this function must not call back into NVKMS-KAPI, nor + * directly into RM. Doing so could cause deadlocks given the notification + * function will most likely be called from within RM's interrupt handler + * callchain. + */ +typedef void NvKmsSemaphoreSurfaceCallbackProc(void *pData); + /** @} */ /** @@ -126,6 +136,11 @@ struct NvKmsKapiDeviceResourcesInfo { NvU32 validCursorCompositionModes; NvU64 supportedCursorSurfaceMemoryFormats; + struct { + NvU64 maxSubmittedOffset; + NvU64 stride; + } semsurf; + struct { NvU16 validRRTransforms; NvU32 validCompositionModes; @@ -218,8 +233,10 @@ struct NvKmsKapiLayerConfig { struct NvKmsRRParams rrParams; struct NvKmsKapiSyncpt syncptParams; - struct NvKmsHDRStaticMetadata hdrMetadata; - NvBool hdrMetadataSpecified; + struct { + struct NvKmsHDRStaticMetadata val; + NvBool enabled; + } hdrMetadata; enum NvKmsOutputTf tf; @@ -233,16 +250,21 @@ struct NvKmsKapiLayerConfig { NvU16 dstWidth, dstHeight; enum NvKmsInputColorSpace inputColorSpace; + struct NvKmsCscMatrix csc; + NvBool cscUseMain; }; struct NvKmsKapiLayerRequestedConfig { struct NvKmsKapiLayerConfig config; struct { - NvBool surfaceChanged : 1; - NvBool srcXYChanged : 1; - NvBool srcWHChanged : 1; - NvBool dstXYChanged : 1; - NvBool dstWHChanged : 1; + NvBool surfaceChanged : 1; + NvBool srcXYChanged : 1; + NvBool srcWHChanged : 1; + NvBool dstXYChanged : 1; + NvBool dstWHChanged : 1; + NvBool cscChanged : 1; + NvBool tfChanged : 1; + NvBool hdrMetadataChanged : 1; } flags; }; @@ -286,14 +308,41 @@ struct NvKmsKapiHeadModeSetConfig { struct NvKmsKapiDisplayMode mode; NvBool vrrEnabled; + + struct { + NvBool enabled; + enum NvKmsInfoFrameEOTF eotf; + struct NvKmsHDRStaticMetadata staticMetadata; + } hdrInfoFrame; + + enum NvKmsOutputColorimetry colorimetry; + + struct { + struct { + NvBool specified; + NvU32 depth; + NvU32 start; + NvU32 end; + struct NvKmsLutRamps *pRamps; + } input; + + struct { + NvBool specified; + NvBool enabled; + struct NvKmsLutRamps *pRamps; + } output; + } lut; }; struct NvKmsKapiHeadRequestedConfig { struct NvKmsKapiHeadModeSetConfig modeSetConfig; struct { - NvBool activeChanged : 1; - NvBool displaysChanged : 1; - NvBool modeChanged : 1; + NvBool activeChanged : 1; + NvBool displaysChanged : 1; + NvBool modeChanged : 1; + NvBool hdrInfoFrameChanged : 1; + NvBool colorimetryChanged : 1; + NvBool lutChanged : 1; } flags; struct NvKmsKapiCursorRequestedConfig cursorRequestedConfig; @@ -318,6 +367,7 @@ struct NvKmsKapiHeadReplyConfig { }; struct NvKmsKapiModeSetReplyConfig { + enum NvKmsFlipResult flipResult; struct NvKmsKapiHeadReplyConfig headReplyConfig[NVKMS_KAPI_MAX_HEADS]; }; @@ -434,6 +484,12 @@ enum NvKmsKapiAllocationType { NVKMS_KAPI_ALLOCATION_TYPE_OFFSCREEN = 2, }; +typedef enum NvKmsKapiRegisterWaiterResultRec { + NVKMS_KAPI_REG_WAITER_FAILED, + NVKMS_KAPI_REG_WAITER_SUCCESS, + NVKMS_KAPI_REG_WAITER_ALREADY_SIGNALLED, +} NvKmsKapiRegisterWaiterResult; + struct NvKmsKapiFunctionsTable { /*! @@ -519,8 +575,8 @@ struct NvKmsKapiFunctionsTable { ); /*! - * Revoke permissions previously granted. Only one (dispIndex, head, - * display) is currently supported. + * Revoke modeset permissions previously granted. Only one (dispIndex, + * head, display) is currently supported. * * \param [in] device A device returned by allocateDevice(). * @@ -537,6 +593,34 @@ struct NvKmsKapiFunctionsTable { NvKmsKapiDisplay display ); + /*! + * Grant modeset sub-owner permissions to fd. This is used by clients to + * convert drm 'master' permissions into nvkms sub-owner permission. + * + * \param [in] fd fd from opening /dev/nvidia-modeset. + * + * \param [in] device A device returned by allocateDevice(). + * + * \return NV_TRUE on success, NV_FALSE on failure. + */ + NvBool (*grantSubOwnership) + ( + NvS32 fd, + struct NvKmsKapiDevice *device + ); + + /*! + * Revoke sub-owner permissions previously granted. + * + * \param [in] device A device returned by allocateDevice(). + * + * \return NV_TRUE on success, NV_FALSE on failure. + */ + NvBool (*revokeSubOwnership) + ( + struct NvKmsKapiDevice *device + ); + /*! * Registers for notification, via * NvKmsKapiAllocateDeviceParams::eventCallback, of the events specified @@ -1122,6 +1206,199 @@ struct NvKmsKapiFunctionsTable { NvP64 dmaBuf, NvU32 limit); + /*! + * Import a semaphore surface allocated elsewhere to NVKMS and return a + * handle to the new object. + * + * \param [in] device A device allocated using allocateDevice(). + * + * \param [in] nvKmsParamsUser Userspace pointer to driver-specific + * parameters describing the semaphore + * surface being imported. + * + * \param [in] nvKmsParamsSize Size of the driver-specific parameter + * struct. + * + * \param [out] pSemaphoreMap Returns a CPU mapping of the semaphore + * surface's semaphore memory to the client. + * + * \param [out] pMaxSubmittedMap Returns a CPU mapping of the semaphore + * surface's semaphore memory to the client. + * + * \return struct NvKmsKapiSemaphoreSurface* on success, NULL on failure. + */ + struct NvKmsKapiSemaphoreSurface* (*importSemaphoreSurface) + ( + struct NvKmsKapiDevice *device, + NvU64 nvKmsParamsUser, + NvU64 nvKmsParamsSize, + void **pSemaphoreMap, + void **pMaxSubmittedMap + ); + + /*! + * Free an imported semaphore surface. + * + * \param [in] device The device passed to + * importSemaphoreSurface() when creating + * semaphoreSurface. + * + * \param [in] semaphoreSurface A semaphore surface returned by + * importSemaphoreSurface(). + */ + void (*freeSemaphoreSurface) + ( + struct NvKmsKapiDevice *device, + struct NvKmsKapiSemaphoreSurface *semaphoreSurface + ); + + /*! + * Register a callback to be called when a semaphore reaches a value. + * + * The callback will be called when the semaphore at index in + * semaphoreSurface reaches the value wait_value. The callback will + * be called at most once and is automatically unregistered when called. + * It may also be unregistered (i.e., cancelled) explicitly using the + * unregisterSemaphoreSurfaceCallback() function. To avoid leaking the + * memory used to track the registered callback, callers must ensure one + * of these methods of unregistration is used for every successful + * callback registration that returns a non-NULL pCallbackHandle. + * + * \param [in] device The device passed to + * importSemaphoreSurface() when creating + * semaphoreSurface. + * + * \param [in] semaphoreSurface A semaphore surface returned by + * importSemaphoreSurface(). + * + * \param [in] pCallback A pointer to the function to call when + * the specified value is reached. NULL + * means no callback. + * + * \param [in] pData Arbitrary data to be passed back to the + * callback as its sole parameter. + * + * \param [in] index The index of the semaphore within + * semaphoreSurface. + * + * \param [in] wait_value The value the semaphore must reach or + * exceed before the callback is called. + * + * \param [in] new_value The value the semaphore will be set to + * when it reaches or exceeds . + * 0 means do not update the value. + * + * \param [out] pCallbackHandle On success, the value pointed to will + * contain an opaque handle to the + * registered callback that may be used to + * cancel it if needed. Unused if pCallback + * is NULL. + * + * \return NVKMS_KAPI_REG_WAITER_SUCCESS if the waiter was registered or if + * no callback was requested and the semaphore at has + * already reached or exceeded + * + * NVKMS_KAPI_REG_WAITER_ALREADY_SIGNALLED if a callback was + * requested and the semaphore at has already reached or + * exceeded + * + * NVKMS_KAPI_REG_WAITER_FAILED if waiter registration failed. + */ + NvKmsKapiRegisterWaiterResult + (*registerSemaphoreSurfaceCallback) + ( + struct NvKmsKapiDevice *device, + struct NvKmsKapiSemaphoreSurface *semaphoreSurface, + NvKmsSemaphoreSurfaceCallbackProc *pCallback, + void *pData, + NvU64 index, + NvU64 wait_value, + NvU64 new_value, + struct NvKmsKapiSemaphoreSurfaceCallback **pCallbackHandle + ); + + /*! + * Unregister a callback registered via registerSemaphoreSurfaceCallback() + * + * If the callback has not yet been called, this function will cancel the + * callback and free its associated resources. + * + * Note this function treats the callback handle as a pointer. While this + * function does not dereference that pointer itself, the underlying call + * to RM does within a properly guarded critical section that first ensures + * it is not in the process of being used within a callback. This means + * the callstack must take into consideration that pointers are not in + * general unique handles if they may have been freed, since a subsequent + * malloc could return the same pointer value at that point. This callchain + * avoids that by leveraging the behavior of the underlying RM APIs: + * + * 1) A callback handle is referenced relative to its corresponding + * (semaphore surface, index, wait_value) tuple here and within RM. It + * is not a valid handle outside of that scope. + * + * 2) A callback can not be registered against an already-reached value + * for a given semaphore surface index. + * + * 3) A given callback handle can not be registered twice against the same + * (semaphore surface, index, wait_value) tuple, so unregistration will + * never race with registration at the RM level, and would only race at + * a higher level if used incorrectly. Since this is kernel code, we + * can safely assume there won't be malicious clients purposely misuing + * the API, but the burden is placed on the caller to ensure its usage + * does not lead to races at higher levels. + * + * These factors considered together ensure any valid registered handle is + * either still in the relevant waiter list and refers to the same event/ + * callback as when it was registered, or has been removed from the list + * as part of a critical section that also destroys the list itself and + * makes future lookups in that list impossible, and hence eliminates the + * chance of comparing a stale handle with a new handle of the same value + * as part of a lookup. + * + * \param [in] device The device passed to + * importSemaphoreSurface() when creating + * semaphoreSurface. + * + * \param [in] semaphoreSurface The semaphore surface passed to + * registerSemaphoreSurfaceCallback() when + * registering the callback. + * + * \param [in] index The index passed to + * registerSemaphoreSurfaceCallback() when + * registering the callback. + * + * \param [in] wait_value The wait_value passed to + * registerSemaphoreSurfaceCallback() when + * registering the callback. + * + * \param [in] callbackHandle The callback handle returned by + * registerSemaphoreSurfaceCallback(). + */ + NvBool + (*unregisterSemaphoreSurfaceCallback) + ( + struct NvKmsKapiDevice *device, + struct NvKmsKapiSemaphoreSurface *semaphoreSurface, + NvU64 index, + NvU64 wait_value, + struct NvKmsKapiSemaphoreSurfaceCallback *callbackHandle + ); + + /*! + * Update the value of a semaphore surface from the CPU. + * + * Update the semaphore value at the specified index from the CPU, then + * wake up any pending CPU waiters associated with that index that are + * waiting on it reaching a value <= the new value. + */ + NvBool + (*setSemaphoreSurfaceValue) + ( + struct NvKmsKapiDevice *device, + struct NvKmsKapiSemaphoreSurface *semaphoreSurface, + NvU64 index, + NvU64 new_value + ); }; /** @} */ diff --git a/src/nvidia-modeset/kapi/src/nvkms-kapi-sync.c b/src/nvidia-modeset/kapi/src/nvkms-kapi-sync.c index f7c54ca5da..1b243d64e6 100644 --- a/src/nvidia-modeset/kapi/src/nvkms-kapi-sync.c +++ b/src/nvidia-modeset/kapi/src/nvkms-kapi-sync.c @@ -29,7 +29,9 @@ #include "nvkms-kapi-private.h" #include "nvkms-kapi-internal.h" +#include "class/cl0000.h" #include "class/cl0005.h" +#include "ctrl/ctrl00da.h" struct NvKmsKapiChannelEvent { struct NvKmsKapiDevice *device; @@ -168,3 +170,402 @@ struct NvKmsKapiChannelEvent* nvKmsKapiAllocateChannelEvent nvKmsKapiFreeChannelEvent(device, cb); return NULL; } + +struct NvKmsKapiSemaphoreSurface { + NvHandle hSemaphoreSurface; + + NvHandle hSemaphoreMem; + NvHandle hMaxSubmittedMem; +}; + +struct NvKmsKapiSemaphoreSurface* +nvKmsKapiImportSemaphoreSurface +( + struct NvKmsKapiDevice *device, + NvU64 nvKmsParamsUser, + NvU64 nvKmsParamsSize, + void **pSemaphoreMap, + void **pMaxSubmittedMap +) +{ + struct NvKmsKapiSemaphoreSurface *ss = NULL; + struct NvKmsKapiPrivImportSemaphoreSurfaceParams p, *pHeap; + NV_SEMAPHORE_SURFACE_CTRL_REF_MEMORY_PARAMS refParams = {}; + NvU32 ret; + int status; + + /* Verify the driver-private params size and copy it in from userspace */ + + if (nvKmsParamsSize != sizeof(p)) { + nvKmsKapiLogDebug( + "NVKMS semaphore surface import parameter size mismatch - expected: 0x%llx, caller specified: 0x%llx", + (NvU64)sizeof(p), nvKmsParamsSize); + goto fail; + } + + /* + * Use a heap allocation as the destination pointer passed to + * nvkms_copyin; stack allocations created within core NVKMS may not + * be recognizable to the Linux kernel's CONFIG_HARDENED_USERCOPY + * checker, triggering false errors. But then save the result to a + * variable on the stack, so that we can free the heap memory + * immediately and not worry about its lifetime. + */ + + pHeap = nvKmsKapiCalloc(1, sizeof(*pHeap)); + if (pHeap == NULL) { + nvKmsKapiLogDebug( + "NVKMS failed to allocate semaphore surface parameter struct of size: %ld", + (long)sizeof(*pHeap)); + goto fail; + } + + status = nvkms_copyin(pHeap, nvKmsParamsUser, sizeof(*pHeap)); + + p = *pHeap; + nvKmsKapiFree(pHeap); + + if (status != 0) { + nvKmsKapiLogDebug( + "NVKMS semaphore surface import parameters could not be read from userspace"); + goto fail; + } + + ss = nvKmsKapiCalloc(1, sizeof(*ss)); + if (ss == NULL) { + nvKmsKapiLogDeviceDebug( + device, + "Failed to allocate memory for NVKMS semaphore surface while importing (0x%08x, 0x%08x)", + p.hClient, p.hSemaphoreSurface); + goto fail; + } + + ret = nvRmApiDupObject2(device->hRmClient, + device->hRmSubDevice, + &ss->hSemaphoreSurface, + p.hClient, + p.hSemaphoreSurface, + 0); + + if (ret != NVOS_STATUS_SUCCESS) { + nvKmsKapiLogDeviceDebug( + device, + "Failed to dup RM semaphore surface object (0x%08x, 0x%08x)", + p.hClient, p.hSemaphoreSurface); + goto fail; + } + + ret = nvRmApiControl(device->hRmClient, + ss->hSemaphoreSurface, + NV_SEMAPHORE_SURFACE_CTRL_CMD_REF_MEMORY, + &refParams, + sizeof(refParams)); + + if (ret != NVOS_STATUS_SUCCESS) { + nvKmsKapiLogDeviceDebug( + device, + "Failed to ref RM semaphore surface memory objects (0x%08x, 0x%08x)", + p.hClient, p.hSemaphoreSurface); + goto fail; + } + + ss->hSemaphoreMem = refParams.hSemaphoreMem; + ss->hMaxSubmittedMem = refParams.hMaxSubmittedMem; + + ret = nvRmApiMapMemory(device->hRmClient, + device->hRmDevice, + ss->hSemaphoreMem, + 0, + p.semaphoreSurfaceSize, + pSemaphoreMap, + 0); + + if (ret != NVOS_STATUS_SUCCESS) { + nvKmsKapiLogDeviceDebug( + device, + "Failed to map RM semaphore surface semaphore memory (0x%08x, 0x%08x)", + p.hClient, p.hSemaphoreSurface); + goto fail; + } + + if (ss->hMaxSubmittedMem != NV01_NULL_OBJECT) { + if (ss->hMaxSubmittedMem != ss->hSemaphoreMem) { + ret = nvRmApiMapMemory(device->hRmClient, + device->hRmDevice, + ss->hMaxSubmittedMem, + 0, + p.semaphoreSurfaceSize, + pMaxSubmittedMap, + 0); + if (ret != NVOS_STATUS_SUCCESS) { + nvKmsKapiLogDeviceDebug( + device, + "Failed to map RM semaphore surface max submitted memory (0x%08x, 0x%08x)", + p.hClient, p.hSemaphoreSurface); + goto fail; + } + } else { + *pMaxSubmittedMap = *pSemaphoreMap; + } + } else { + *pMaxSubmittedMap = NULL; + } + + return ss; + +fail: + if (ss && ss->hSemaphoreSurface) { + if ((ss->hMaxSubmittedMem != NV01_NULL_OBJECT) && + (ss->hMaxSubmittedMem != ss->hSemaphoreMem)) { + nvRmApiFree(device->hRmClient, + device->hRmDevice, + ss->hMaxSubmittedMem); + } + + if (ss->hSemaphoreMem != NV01_NULL_OBJECT) { + nvRmApiFree(device->hRmClient, + device->hRmDevice, + ss->hSemaphoreMem); + } + + nvRmApiFree(device->hRmClient, + device->hRmDevice, + ss->hSemaphoreSurface); + } + nvKmsKapiFree(ss); + return NULL; +} + +void nvKmsKapiFreeSemaphoreSurface +( + struct NvKmsKapiDevice *device, + struct NvKmsKapiSemaphoreSurface *ss +) +{ + if (device == NULL || ss == NULL) { + return; + } + + if ((ss->hMaxSubmittedMem != NV01_NULL_OBJECT) && + (ss->hMaxSubmittedMem != ss->hSemaphoreMem)) { + nvRmApiFree(device->hRmClient, + device->hRmDevice, + ss->hMaxSubmittedMem); + } + + nvRmApiFree(device->hRmClient, + device->hRmDevice, + ss->hSemaphoreMem); + + nvRmApiFree(device->hRmClient, + device->hRmSubDevice, + ss->hSemaphoreSurface); + + nvKmsKapiFree(ss); +} + +struct NvKmsKapiSemaphoreSurfaceCallback { + NvKmsSemaphoreSurfaceCallbackProc *pCallback; + void *pData; + + NVOS10_EVENT_KERNEL_CALLBACK_EX rmCallback; +}; + +static void SemaphoreSurfaceKapiCallback(void *arg1, void *arg2, NvHandle hEvent, + NvU32 data, NvU32 status) +{ + struct NvKmsKapiSemaphoreSurfaceCallback *cb = arg1; + cb->pCallback(cb->pData); + nvKmsKapiFree(cb); +} + +NvKmsKapiRegisterWaiterResult +nvKmsKapiRegisterSemaphoreSurfaceCallback( + struct NvKmsKapiDevice *device, + struct NvKmsKapiSemaphoreSurface *semaphoreSurface, + NvKmsSemaphoreSurfaceCallbackProc *pCallback, + void *pData, + NvU64 index, + NvU64 wait_value, + NvU64 new_value, + struct NvKmsKapiSemaphoreSurfaceCallback **pCallbackHandle) +{ + NvU32 ret; + + struct NvKmsKapiSemaphoreSurfaceCallback *cb = NULL; + NV_SEMAPHORE_SURFACE_CTRL_REGISTER_WAITER_PARAMS waiterParams = { }; + + if (device == NULL) { + nvKmsKapiLogDebug( + "Invalid device while registering semaphore surface callback"); + goto fail; + } + + if ((semaphoreSurface == NULL) || + ((pCallback == NULL) && (new_value == 0))) { + nvKmsKapiLogDeviceDebug( + device, + "Invalid parameter while registering semaphore surface callback"); + goto fail; + } + + waiterParams.index = index; + waiterParams.waitValue = wait_value; + waiterParams.newValue = new_value; + + if (pCallback) { + cb = nvKmsKapiCalloc(1, sizeof(*cb)); + if (cb == NULL) { + nvKmsKapiLogDeviceDebug( + device, + "Failed to allocate memory for semaphore surface (0x%08x, 0x%08x) callback on index %" NvU64_fmtu " for value %" NvU64_fmtx, + device->hRmClient, semaphoreSurface->hSemaphoreSurface, + index, wait_value); + goto fail; + } + + cb->pCallback = pCallback; + cb->pData = pData; + cb->rmCallback.func = SemaphoreSurfaceKapiCallback; + cb->rmCallback.arg = cb; + + waiterParams.notificationHandle = (NvUPtr)&cb->rmCallback; + } + + ret = nvRmApiControl(device->hRmClient, + semaphoreSurface->hSemaphoreSurface, + NV_SEMAPHORE_SURFACE_CTRL_CMD_REGISTER_WAITER, + &waiterParams, + sizeof(waiterParams)); + + switch (ret) { + case NVOS_STATUS_SUCCESS: + if (pCallback) { + *pCallbackHandle = cb; + } + return NVKMS_KAPI_REG_WAITER_SUCCESS; + case NVOS_STATUS_ERROR_ALREADY_SIGNALLED: + return NVKMS_KAPI_REG_WAITER_ALREADY_SIGNALLED; + default: + break; + } + +fail: + nvKmsKapiFree(cb); + return NVKMS_KAPI_REG_WAITER_FAILED; +} + +NvBool +nvKmsKapiUnregisterSemaphoreSurfaceCallback( + struct NvKmsKapiDevice *device, + struct NvKmsKapiSemaphoreSurface *semaphoreSurface, + NvU64 index, + NvU64 wait_value, + struct NvKmsKapiSemaphoreSurfaceCallback *callbackHandle) +{ + NV_SEMAPHORE_SURFACE_CTRL_UNREGISTER_WAITER_PARAMS waiterParams = { }; + NvU32 ret; + + + if (device == NULL) { + nvKmsKapiLogDebug( + "Invalid device while unregistering semaphore surface callback"); + return NV_FALSE; + } + + if ((semaphoreSurface == NULL) || (callbackHandle == NULL) || + (wait_value == 0)) { + nvKmsKapiLogDeviceDebug( + device, + "Invalid parameter while unregistering semaphore surface callback"); + return NV_FALSE; + } + + /* + * Note this function does not actually dereference callbackHandle before + * making the RM control call. This is important, as there may exist a race + * such that the client is calling this function while another thread is + * running the callback and freeing its handle. + * + * The existance of this race seems to imply there is an additional hazard + * where a new callback may be registered against the same wait value during + * the first race, which this call would then mistakenly delete. That is + * impossible because the RM semaphore surface code would detect that such a + * waiter is already signaled and return without adding it to the waiter + * list. + */ + waiterParams.index = index; + waiterParams.waitValue = wait_value; + + /* + * Manually perform the equivalent of &callbackHandle->rmCallback, but with + * semantics that make it clearer there is no access of the memory pointed + * to by callbackHandle. + */ + waiterParams.notificationHandle = (NvUPtr)callbackHandle + + offsetof(struct NvKmsKapiSemaphoreSurfaceCallback, rmCallback); + + ret = nvRmApiControl(device->hRmClient, + semaphoreSurface->hSemaphoreSurface, + NV_SEMAPHORE_SURFACE_CTRL_CMD_UNREGISTER_WAITER, + &waiterParams, + sizeof(waiterParams)); + + switch (ret) { + case NVOS_STATUS_SUCCESS: + /* + * The callback was successfully unregistered, and will never run. Free + * its associated data. + */ + nvKmsKapiFree(callbackHandle); + return NV_TRUE; + + default: + /* + * This code must assume failure to unregister for any reason indicates + * the callback is being run right now, or is on a list of pending + * callbacks which will be run in finite time. Do not free its data. + */ + return NV_FALSE; + } +} + +NvBool +nvKmsKapiSetSemaphoreSurfaceValue( + struct NvKmsKapiDevice *device, + struct NvKmsKapiSemaphoreSurface *semaphoreSurface, + NvU64 index, + NvU64 new_value) +{ + NvU32 ret; + + NV_SEMAPHORE_SURFACE_CTRL_SET_VALUE_PARAMS setParams = { }; + + if (device == NULL) { + nvKmsKapiLogDebug( + "Invalid device used to set semaphore surface value"); + return NV_FALSE; + } + + if (semaphoreSurface == NULL) { + nvKmsKapiLogDeviceDebug( + device, + "Attempt to set value on Invalid semaphore surface"); + return NV_FALSE; + } + + setParams.index = index; + setParams.newValue = new_value; + + ret = nvRmApiControl(device->hRmClient, + semaphoreSurface->hSemaphoreSurface, + NV_SEMAPHORE_SURFACE_CTRL_CMD_SET_VALUE, + &setParams, + sizeof(setParams)); + + if (ret != NVOS_STATUS_SUCCESS) { + return NV_FALSE; + } + + return NV_TRUE; +} diff --git a/src/nvidia-modeset/kapi/src/nvkms-kapi.c b/src/nvidia-modeset/kapi/src/nvkms-kapi.c index 52ce05359b..cc2d7fe851 100644 --- a/src/nvidia-modeset/kapi/src/nvkms-kapi.c +++ b/src/nvidia-modeset/kapi/src/nvkms-kapi.c @@ -46,6 +46,7 @@ #include /* NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_VIDMEM */ #include /* NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES */ #include /* NV0080_CTRL_CMD_FB_GET_CAPS_V2 */ +#include /* NV2080_CTRL_CMD_FB_GET_SEMAPHORE_SURFACE_LAYOUT */ #include /* NV2080_CTRL_CMD_OS_UNIX_GC6_BLOCKER_REFCNT */ #include "ctrl/ctrl003e.h" /* NV003E_CTRL_CMD_GET_SURFACE_PHYS_PAGES */ @@ -914,6 +915,51 @@ static NvBool RevokePermissions sizeof(paramsRevoke)); } +static NvBool GrantSubOwnership +( + NvS32 fd, + struct NvKmsKapiDevice *device +) +{ + struct NvKmsGrantPermissionsParams paramsGrant = { }; + struct NvKmsPermissions *perm = ¶msGrant.request.permissions; + + if (device->hKmsDevice == 0x0) { + return NV_TRUE; + } + + perm->type = NV_KMS_PERMISSIONS_TYPE_SUB_OWNER; + + paramsGrant.request.fd = fd; + paramsGrant.request.deviceHandle = device->hKmsDevice; + + return nvkms_ioctl_from_kapi(device->pKmsOpen, + NVKMS_IOCTL_GRANT_PERMISSIONS, ¶msGrant, + sizeof(paramsGrant)); +} + +static NvBool RevokeSubOwnership +( + struct NvKmsKapiDevice *device +) +{ + struct NvKmsRevokePermissionsParams paramsRevoke = { }; + + if (device->hKmsDevice == 0x0) { + return NV_TRUE; + } + + paramsRevoke.request.permissionsTypeBitmask = + NVBIT(NV_KMS_PERMISSIONS_TYPE_FLIPPING) | + NVBIT(NV_KMS_PERMISSIONS_TYPE_MODESET) | + NVBIT(NV_KMS_PERMISSIONS_TYPE_SUB_OWNER); + paramsRevoke.request.deviceHandle = device->hKmsDevice; + + return nvkms_ioctl_from_kapi(device->pKmsOpen, + NVKMS_IOCTL_REVOKE_PERMISSIONS, ¶msRevoke, + sizeof(paramsRevoke)); +} + static NvBool DeclareEventInterest ( const struct NvKmsKapiDevice *device, @@ -941,12 +987,30 @@ static NvBool GetDeviceResourcesInfo ) { struct NvKmsQueryDispParams paramsDisp = { }; + NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS semsurfLayoutParams = { }; NvBool status = NV_FALSE; + NvU32 ret; NvU32 i; nvkms_memset(info, 0, sizeof(*info)); + ret = nvRmApiControl(device->hRmClient, + device->hRmSubDevice, + NV2080_CTRL_CMD_FB_GET_SEMAPHORE_SURFACE_LAYOUT, + &semsurfLayoutParams, + sizeof(semsurfLayoutParams)); + + if (ret == NVOS_STATUS_SUCCESS) { + info->caps.semsurf.stride = semsurfLayoutParams.size; + info->caps.semsurf.maxSubmittedOffset = + semsurfLayoutParams.maxSubmittedSemaphoreValueOffset; + } else { + /* Non-fatal. No semaphore surface support. */ + info->caps.semsurf.stride = 0; + info->caps.semsurf.maxSubmittedOffset = 0; + } + info->caps.hasVideoMemory = !device->isSOC; info->caps.genericPageKind = device->caps.genericPageKind; @@ -2436,16 +2500,18 @@ static NvBool AssignSyncObjectConfig( static void AssignHDRMetadataConfig( const struct NvKmsKapiLayerConfig *layerConfig, + const struct NvKmsKapiLayerRequestedConfig *layerRequestedConfig, const NvU32 layer, - struct NvKmsFlipCommonParams *params) + struct NvKmsFlipCommonParams *params, + NvBool bFromKmsSetMode) { - if (layerConfig->hdrMetadataSpecified) { - params->layer[layer].hdr.enabled = TRUE; - params->layer[layer].hdr.specified = TRUE; - params->layer[layer].hdr.staticMetadata = layerConfig->hdrMetadata; - } else { - params->layer[layer].hdr.enabled = FALSE; - params->layer[layer].hdr.specified = TRUE; + params->layer[layer].hdr.specified = + bFromKmsSetMode || layerRequestedConfig->flags.hdrMetadataChanged; + params->layer[layer].hdr.enabled = + layerConfig->hdrMetadata.enabled; + if (layerConfig->hdrMetadata.enabled) { + params->layer[layer].hdr.staticMetadata = + layerConfig->hdrMetadata.val; } } @@ -2513,15 +2579,30 @@ static NvBool NvKmsKapiOverlayLayerConfigToKms( params->layer[layer].compositionParams.specified = TRUE; params->layer[layer].minPresentInterval = layerConfig->minPresentInterval; + + params->layer[layer].colorSpace.val = layerConfig->inputColorSpace; + params->layer[layer].colorSpace.specified = TRUE; } - params->layer[layer].sizeIn.val.width = layerConfig->srcWidth; - params->layer[layer].sizeIn.val.height = layerConfig->srcHeight; - params->layer[layer].sizeIn.specified = TRUE; + if (layerRequestedConfig->flags.cscChanged) { + params->layer[layer].csc.specified = NV_TRUE; + params->layer[layer].csc.useMain = layerConfig->cscUseMain; + if (!layerConfig->cscUseMain) { + params->layer[layer].csc.matrix = layerConfig->csc; + } + } - params->layer[layer].sizeOut.val.width = layerConfig->dstWidth; - params->layer[layer].sizeOut.val.height = layerConfig->dstHeight; - params->layer[layer].sizeOut.specified = TRUE; + if (layerRequestedConfig->flags.srcWHChanged || bFromKmsSetMode) { + params->layer[layer].sizeIn.val.width = layerConfig->srcWidth; + params->layer[layer].sizeIn.val.height = layerConfig->srcHeight; + params->layer[layer].sizeIn.specified = TRUE; + } + + if (layerRequestedConfig->flags.dstWHChanged || bFromKmsSetMode) { + params->layer[layer].sizeOut.val.width = layerConfig->dstWidth; + params->layer[layer].sizeOut.val.height = layerConfig->dstHeight; + params->layer[layer].sizeOut.specified = TRUE; + } if (layerRequestedConfig->flags.dstXYChanged || bFromKmsSetMode) { params->layer[layer].outputPosition.val.x = layerConfig->dstX; @@ -2530,10 +2611,8 @@ static NvBool NvKmsKapiOverlayLayerConfigToKms( params->layer[layer].outputPosition.specified = NV_TRUE; } - params->layer[layer].colorspace.val = layerConfig->inputColorSpace; - params->layer[layer].colorspace.specified = TRUE; - - AssignHDRMetadataConfig(layerConfig, layer, params); + AssignHDRMetadataConfig(layerConfig, layerRequestedConfig, layer, + params, bFromKmsSetMode); if (commit) { NvU32 nextIndex = NVKMS_KAPI_INC_NOTIFIER_INDEX( @@ -2619,6 +2698,9 @@ static NvBool NvKmsKapiPrimaryLayerConfigToKms( } } + params->layer[NVKMS_MAIN_LAYER].colorSpace.val = layerConfig->inputColorSpace; + params->layer[NVKMS_MAIN_LAYER].colorSpace.specified = TRUE; + changed = TRUE; } @@ -2630,10 +2712,18 @@ static NvBool NvKmsKapiPrimaryLayerConfigToKms( changed = TRUE; } - params->layer[NVKMS_MAIN_LAYER].colorspace.val = layerConfig->inputColorSpace; - params->layer[NVKMS_MAIN_LAYER].colorspace.specified = TRUE; + if (layerRequestedConfig->flags.cscChanged) { + nvAssert(!layerConfig->cscUseMain); + + params->layer[NVKMS_MAIN_LAYER].csc.specified = NV_TRUE; + params->layer[NVKMS_MAIN_LAYER].csc.useMain = FALSE; + params->layer[NVKMS_MAIN_LAYER].csc.matrix = layerConfig->csc; + + changed = TRUE; + } - AssignHDRMetadataConfig(layerConfig, NVKMS_MAIN_LAYER, params); + AssignHDRMetadataConfig(layerConfig, layerRequestedConfig, NVKMS_MAIN_LAYER, + params, bFromKmsSetMode); if (commit && changed) { NvU32 nextIndex = NVKMS_KAPI_INC_NOTIFIER_INDEX( @@ -2707,6 +2797,47 @@ static NvBool NvKmsKapiLayerConfigToKms( bFromKmsSetMode); } +static void NvKmsKapiHeadLutConfigToKms( + const struct NvKmsKapiHeadModeSetConfig *modeSetConfig, + struct NvKmsSetLutCommonParams *lutParams) +{ + struct NvKmsSetInputLutParams *input = &lutParams->input; + struct NvKmsSetOutputLutParams *output = &lutParams->output; + + /* input LUT */ + input->specified = modeSetConfig->lut.input.specified; + input->depth = modeSetConfig->lut.input.depth; + input->start = modeSetConfig->lut.input.start; + input->end = modeSetConfig->lut.input.end; + + input->pRamps = nvKmsPointerToNvU64(modeSetConfig->lut.input.pRamps); + + /* output LUT */ + output->specified = modeSetConfig->lut.output.specified; + output->enabled = modeSetConfig->lut.output.enabled; + + output->pRamps = nvKmsPointerToNvU64(modeSetConfig->lut.output.pRamps); +} + +static NvBool AnyLayerTransferFunctionChanged( + const struct NvKmsKapiHeadRequestedConfig *headRequestedConfig) +{ + NvU32 layer; + + for (layer = 0; + layer < ARRAY_LEN(headRequestedConfig->layerRequestedConfig); + layer++) { + const struct NvKmsKapiLayerRequestedConfig *layerRequestedConfig = + &headRequestedConfig->layerRequestedConfig[layer]; + + if (layerRequestedConfig->flags.tfChanged) { + return NV_TRUE; + } + } + + return NV_FALSE; +} + static NvBool GetOutputTransferFunction( const struct NvKmsKapiHeadRequestedConfig *headRequestedConfig, enum NvKmsOutputTf *tf) @@ -2724,7 +2855,7 @@ static NvBool GetOutputTransferFunction( const struct NvKmsKapiLayerConfig *layerConfig = &layerRequestedConfig->config; - if (layerConfig->hdrMetadataSpecified) { + if (layerConfig->hdrMetadata.enabled) { if (!found) { *tf = layerConfig->tf; found = NV_TRUE; @@ -2797,6 +2928,10 @@ static NvBool NvKmsKapiRequestedModeSetConfigToKms( NvKmsKapiDisplayModeToKapi(&headModeSetConfig->mode, ¶msHead->mode); + if (headRequestedConfig->flags.lutChanged) { + NvKmsKapiHeadLutConfigToKms(headModeSetConfig, ¶msHead->flip.lut); + } + NvKmsKapiCursorConfigToKms(&headRequestedConfig->cursorRequestedConfig, ¶msHead->flip, NV_TRUE /* bFromKmsSetMode */); @@ -2825,6 +2960,19 @@ static NvBool NvKmsKapiRequestedModeSetConfigToKms( paramsHead->flip.tf.val = tf; paramsHead->flip.tf.specified = NV_TRUE; + paramsHead->flip.hdrInfoFrame.specified = NV_TRUE; + paramsHead->flip.hdrInfoFrame.enabled = + headModeSetConfig->hdrInfoFrame.enabled; + if (headModeSetConfig->hdrInfoFrame.enabled) { + paramsHead->flip.hdrInfoFrame.eotf = + headModeSetConfig->hdrInfoFrame.eotf; + paramsHead->flip.hdrInfoFrame.staticMetadata = + headModeSetConfig->hdrInfoFrame.staticMetadata; + } + + paramsHead->flip.colorimetry.specified = NV_TRUE; + paramsHead->flip.colorimetry.val = headModeSetConfig->colorimetry; + paramsHead->viewPortSizeIn.width = headModeSetConfig->mode.timings.hVisible; paramsHead->viewPortSizeIn.height = @@ -2846,6 +2994,7 @@ static NvBool NvKmsKapiRequestedModeSetConfigToKms( static NvBool KmsSetMode( struct NvKmsKapiDevice *device, const struct NvKmsKapiRequestedModeSetConfig *requestedConfig, + struct NvKmsKapiModeSetReplyConfig *replyConfig, const NvBool commit) { struct NvKmsSetModeParams *params = NULL; @@ -2868,6 +3017,11 @@ static NvBool KmsSetMode( NVKMS_IOCTL_SET_MODE, params, sizeof(*params)); + replyConfig->flipResult = + (params->reply.status == NVKMS_SET_MODE_STATUS_SUCCESS) ? + NV_KMS_FLIP_RESULT_SUCCESS : + NV_KMS_FLIP_RESULT_INVALID_PARAMS; + if (!status) { nvKmsKapiLogDeviceDebug( device, @@ -2966,7 +3120,6 @@ static NvBool KmsFlip( &requestedConfig->headRequestedConfig[head]; const struct NvKmsKapiHeadModeSetConfig *headModeSetConfig = &headRequestedConfig->modeSetConfig; - enum NvKmsOutputTf tf; struct NvKmsFlipCommonParams *flipParams = NULL; @@ -3006,17 +3159,42 @@ static NvBool KmsFlip( } } - status = GetOutputTransferFunction(headRequestedConfig, &tf); - if (status != NV_TRUE) { - goto done; + flipParams->tf.specified = + AnyLayerTransferFunctionChanged(headRequestedConfig); + if (flipParams->tf.specified) { + enum NvKmsOutputTf tf; + status = GetOutputTransferFunction(headRequestedConfig, &tf); + if (status != NV_TRUE) { + goto done; + } + flipParams->tf.val = tf; + } + + flipParams->hdrInfoFrame.specified = + headRequestedConfig->flags.hdrInfoFrameChanged; + if (flipParams->hdrInfoFrame.specified) { + flipParams->hdrInfoFrame.enabled = + headModeSetConfig->hdrInfoFrame.enabled; + if (headModeSetConfig->hdrInfoFrame.enabled) { + flipParams->hdrInfoFrame.eotf = + headModeSetConfig->hdrInfoFrame.eotf; + flipParams->hdrInfoFrame.staticMetadata = + headModeSetConfig->hdrInfoFrame.staticMetadata; + } } - flipParams->tf.val = tf; - flipParams->tf.specified = NV_TRUE; + flipParams->colorimetry.specified = + headRequestedConfig->flags.colorimetryChanged; + if (flipParams->colorimetry.specified) { + flipParams->colorimetry.val = headModeSetConfig->colorimetry; + } if (headModeSetConfig->vrrEnabled) { params->request.allowVrr = NV_TRUE; } + if (headRequestedConfig->flags.lutChanged) { + NvKmsKapiHeadLutConfigToKms(headModeSetConfig, &flipParams->lut); + } } if (params->request.numFlipHeads == 0) { @@ -3027,6 +3205,8 @@ static NvBool KmsFlip( NVKMS_IOCTL_FLIP, params, sizeof(*params)); + replyConfig->flipResult = params->reply.flipResult; + if (!status) { nvKmsKapiLogDeviceDebug( device, @@ -3129,12 +3309,16 @@ static NvBool ApplyModeSetConfig( } if (bRequiredModeset) { - return KmsSetMode(device, requestedConfig, commit); + return KmsSetMode(device, requestedConfig, replyConfig, commit); } return KmsFlip(device, requestedConfig, replyConfig, commit); } +/* + * This executes without the nvkms_lock held. The lock will be grabbed + * during the kapi dispatching contained in this function. + */ void nvKmsKapiHandleEventQueueChange ( struct NvKmsKapiDevice *device @@ -3279,6 +3463,8 @@ NvBool nvKmsKapiGetFunctionsTableInternal funcsTable->grantPermissions = GrantPermissions; funcsTable->revokePermissions = RevokePermissions; + funcsTable->grantSubOwnership = GrantSubOwnership; + funcsTable->revokeSubOwnership = RevokeSubOwnership; funcsTable->declareEventInterest = DeclareEventInterest; @@ -3320,5 +3506,14 @@ NvBool nvKmsKapiGetFunctionsTableInternal funcsTable->isMemoryValidForDisplay = IsMemoryValidForDisplay; + funcsTable->importSemaphoreSurface = nvKmsKapiImportSemaphoreSurface; + funcsTable->freeSemaphoreSurface = nvKmsKapiFreeSemaphoreSurface; + funcsTable->registerSemaphoreSurfaceCallback = + nvKmsKapiRegisterSemaphoreSurfaceCallback; + funcsTable->unregisterSemaphoreSurfaceCallback = + nvKmsKapiUnregisterSemaphoreSurfaceCallback; + funcsTable->setSemaphoreSurfaceValue = + nvKmsKapiSetSemaphoreSurfaceValue; + return NV_TRUE; } diff --git a/src/nvidia-modeset/os-interface/include/nvidia-modeset-os-interface.h b/src/nvidia-modeset/os-interface/include/nvidia-modeset-os-interface.h index 16b89c1ca2..9f1a2f5428 100644 --- a/src/nvidia-modeset/os-interface/include/nvidia-modeset-os-interface.h +++ b/src/nvidia-modeset/os-interface/include/nvidia-modeset-os-interface.h @@ -97,8 +97,9 @@ typedef struct { } NvKmsSyncPtOpParams; NvBool nvkms_output_rounding_fix(void); - +NvBool nvkms_disable_hdmi_frl(void); NvBool nvkms_disable_vrr_memclk_switch(void); +NvBool nvkms_hdmi_deepcolor(void); void nvkms_call_rm (void *ops); void* nvkms_alloc (size_t size, diff --git a/src/nvidia-modeset/os-interface/include/nvkms.h b/src/nvidia-modeset/os-interface/include/nvkms.h index e770341b89..b64fbb098e 100644 --- a/src/nvidia-modeset/os-interface/include/nvkms.h +++ b/src/nvidia-modeset/os-interface/include/nvkms.h @@ -66,6 +66,8 @@ enum NvKmsClientType { NVKMS_CLIENT_KERNEL_SPACE, }; +struct NvKmsPerOpenDev; + NvBool nvKmsIoctl( void *pOpenVoid, NvU32 cmd, @@ -104,4 +106,6 @@ NvBool nvKmsKapiGetFunctionsTableInternal NvBool nvKmsGetBacklight(NvU32 display_id, void *drv_priv, NvU32 *brightness); NvBool nvKmsSetBacklight(NvU32 display_id, void *drv_priv, NvU32 brightness); +NvBool nvKmsOpenDevHasSubOwnerPermissionOrBetter(const struct NvKmsPerOpenDev *pOpenDev); + #endif /* __NV_KMS_H__ */ diff --git a/src/nvidia-modeset/src/dp/nvdp-connector.cpp b/src/nvidia-modeset/src/dp/nvdp-connector.cpp index 91224df2c7..a812a14f98 100644 --- a/src/nvidia-modeset/src/dp/nvdp-connector.cpp +++ b/src/nvidia-modeset/src/dp/nvdp-connector.cpp @@ -32,6 +32,7 @@ #include "nvkms-modeset.h" #include "nvkms-utils.h" #include "nvkms-rmapi.h" +#include "nvkms-prealloc.h" #include @@ -159,20 +160,6 @@ NvBool nvDPIsLinkAwaitingTransition(NVConnectorEvoPtr pConnectorEvo) return FALSE; } -/* - * Start DisplayPort mode validation on all connectors on a disp. - */ -void nvDPBeginValidation(NVDispEvoPtr pDispEvo) -{ - NVConnectorEvoPtr pConnectorEvo; - - FOR_ALL_EVO_CONNECTORS(pConnectorEvo, pDispEvo) { - if (nvConnectorUsesDPLib(pConnectorEvo)) { - pConnectorEvo->pDpLibConnector->connector->beginCompoundQuery(); - } - } -} - /*! * Create a new DisplayPort group and populate it with the devices specified by * dpyIdList. For MST groups, this allocates a dynamic RM display ID. @@ -401,19 +388,26 @@ void nvDPLibFreeModesetState(NVDPLibModesetStatePtr pDpLibModesetState) nvFree(pDpLibModesetState); } -/* - * Validate the mode for a given NVHwModeTimingsEvo + dpyIdList. This - * function should be called for each head, and must be called between - * nvDPBeginValidation and nvDPEndValidation. - * - * If validation fails, this function returns FALSE. You must still call - * nvDPEndValidation even if an individual head fails. - * - * If validation succeeds, the DSC fields within pTimings are updated with what - * is returned by compoundQueryAttach(). - */ -NvBool nvDPLibValidateTimings( - const NVDispEvoRec *pDispEvo, +static void DestructDpLibIsModesetPossibleParamsOneHead( + const NvU32 head, + DisplayPort::DpLinkIsModePossibleParams *pParams) +{ + nvFree(pParams->head[head].pModesetParams); + + if (pParams->head[head].pDscParams != NULL) { + nvFree(pParams->head[head].pDscParams->pDscOutParams); + } + nvFree(pParams->head[head].pDscParams); + + if (pParams->head[head].pTarget != NULL) { + pParams->head[head].pTarget->destroy(); + } + + nvkms_memset(&pParams->head[head], 0, sizeof(pParams->head[head])); +} + +static NvBool ConstructDpLibIsModesetPossibleParamsOneHead( + const NVDPLibConnectorRec *pDpLibConnector, const NvU32 head, const NvU32 displayId, const NVDpyIdList dpyIdList, @@ -422,51 +416,42 @@ NvBool nvDPLibValidateTimings( const struct NvKmsModeValidationParams *pModeValidationParams, const NVHwModeTimingsEvo *pTimings, const NvBool b2Heads1Or, - NVDscInfoEvoRec *pDscInfo) + DisplayPort::DP_IMP_ERROR *pErrorCode, + DisplayPort::DpLinkIsModePossibleParams *pParams) { + const NVConnectorEvoRec *pConnectorEvo = pDpLibConnector->pConnectorEvo; + const NVDispEvoRec *pDispEvo = pConnectorEvo->pDispEvo; const NVDpyEvoRec *pDpyEvo; - const NVDPLibConnectorRec *pDpLibConnector = NULL; - bool found = false; - - DisplayPort::Group *pGroup = NULL; - DisplayPort::DscOutParams *pDscOutParams = NULL; - DisplayPort::DpModesetParams *pModesetParams = NULL; - DisplayPort::DscParams dpDscParams; - NvBool ret = FALSE; FOR_ALL_EVO_DPYS(pDpyEvo, dpyIdList, pDispEvo) { - if (!found) { - pDpLibConnector = pDpyEvo->pConnectorEvo->pDpLibConnector; - found = true; - } else if (pDpLibConnector != pDpyEvo->pConnectorEvo->pDpLibConnector) { - /* All Dpys must belongs to same DP connector */ - return FALSE; + if (pDpyEvo->pConnectorEvo->pDpLibConnector != pDpLibConnector) { + goto failed; } } - /* Do nothing if any of the display is not DP */ - if (pDpLibConnector == NULL) { - return TRUE; - } - - pGroup = CreateGroup(pDpLibConnector, dpyIdList); - if (pGroup == NULL) { + pParams->head[head].pTarget = CreateGroup(pDpLibConnector, dpyIdList); + if (pParams->head[head].pTarget == NULL) { nvEvoLogDisp(pDispEvo, EVO_LOG_ERROR, "Failed to create a DisplayPort group"); - goto done; + goto failed; } - pDscOutParams = - (DisplayPort::DscOutParams*) nvCalloc(1, sizeof(*pDscOutParams)); - if (pDscOutParams == NULL) { - goto done; + pParams->head[head].pDscParams = (DisplayPort::DscParams*) + nvCalloc(1, sizeof(*pParams->head[head].pDscParams)); + if (pParams->head[head].pDscParams == NULL) { + goto failed; } + pParams->head[head].pDscParams->pDscOutParams = (DisplayPort::DscOutParams*) + nvCalloc(1, sizeof(*pParams->head[head].pDscParams->pDscOutParams)); + if (pParams->head[head].pDscParams->pDscOutParams == NULL) { + goto failed; + } - pModesetParams = - (DisplayPort::DpModesetParams*) nvCalloc(1, sizeof(*pModesetParams)); - if (pModesetParams == NULL) { - goto done; + pParams->head[head].pModesetParams = (DisplayPort::DpModesetParams*) + nvCalloc(1, sizeof(*pParams->head[head].pModesetParams)); + if (pParams->head[head].pModesetParams == NULL) { + goto failed; } InitDpModesetParams(pDispEvo, @@ -475,14 +460,14 @@ NvBool nvDPLibValidateTimings( pTimings, colorSpace, colorBpc, - pModesetParams); + pParams->head[head].pModesetParams); if (b2Heads1Or) { - pModesetParams->modesetInfo.mode = DSC_DUAL; + pParams->head[head].pModesetParams->modesetInfo.mode = DSC_DUAL; } - dpDscParams.bCheckWithDsc = true; - dpDscParams.forceDsc = pModeValidationParams->forceDsc ? + pParams->head[head].pDscParams->bCheckWithDsc = true; + pParams->head[head].pDscParams->forceDsc = pModeValidationParams->forceDsc ? DisplayPort::DSC_FORCE_ENABLE : DisplayPort::DSC_DEFAULT; /* @@ -490,70 +475,118 @@ NvBool nvDPLibValidateTimings( * but YUV420 is not, force DSC. */ if (b2Heads1Or && (pTimings->yuv420Mode != NV_YUV420_MODE_HW)) { - dpDscParams.forceDsc = DisplayPort::DSC_FORCE_ENABLE; + pParams->head[head].pDscParams->forceDsc = DisplayPort::DSC_FORCE_ENABLE; } - dpDscParams.bitsPerPixelX16 = + + pParams->head[head].pDscParams->bitsPerPixelX16 = pModeValidationParams->dscOverrideBitsPerPixelX16; - dpDscParams.pDscOutParams = pDscOutParams; - ret = pDpLibConnector->connector->compoundQueryAttach( - pGroup, *pModesetParams, - &dpDscParams); + pParams->head[head].pErrorStatus = pErrorCode; - if (ret && b2Heads1Or) { - /* - * 2Heads1OR requires either YUV420 or DSC; - * dpDscParams.bEnableDsc is assigned by compoundQueryAttach(). - */ - nvAssert(dpDscParams.bEnableDsc || - (pTimings->yuv420Mode == NV_YUV420_MODE_HW)); - } + return TRUE; - if (ret && (pDscInfo != NULL)) { - nvkms_memset(pDscInfo, 0, sizeof(*pDscInfo)); +failed: + DestructDpLibIsModesetPossibleParamsOneHead(head, pParams); + return FALSE; +} - if (dpDscParams.bEnableDsc) { - pDscInfo->type = NV_DSC_INFO_EVO_TYPE_DP; +/* + * Validate the DP link for all specified NVHwModeTimingsEvos + dpyIdLists + heads. + * + * If validation fails, this function returns FALSE and the mask of heads for + * which validation is failed. + * + * If validation succeeds, the DSC fields within the per head mode parameters + * are updated with what is returned by dpLinkIsModePossible(). + */ +NvBool nvDPLibIsModePossible(const NVDPLibConnectorRec *pDpLibConnector, + const NVDpLibIsModePossibleParamsRec *pParams, + NvU32 *pFailedHeadMask) +{ + DisplayPort::DpLinkIsModePossibleParams dpImpParams = { }; + DisplayPort::DP_IMP_ERROR dpErrorCode[NV_MAX_HEADS] = { }; + const NVConnectorEvoRec *pConnectorEvo = pDpLibConnector->pConnectorEvo; + const NVDispEvoRec *pDispEvo = pConnectorEvo->pDispEvo; + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + NvBool ret = FALSE; + NvU32 head; - pDscInfo->dp.dscMode = b2Heads1Or ? - NV_DSC_EVO_MODE_DUAL : NV_DSC_EVO_MODE_SINGLE; - pDscInfo->dp.bitsPerPixelX16 = dpDscParams.bitsPerPixelX16; - ct_assert(sizeof(pDscInfo->dp.pps) == sizeof(pDscOutParams->PPS)); - nvkms_memcpy(pDscInfo->dp.pps, pDscOutParams->PPS, - sizeof(pDscInfo->dp.pps)); - } else { - pDscInfo->type = NV_DSC_INFO_EVO_TYPE_DISABLED; + for (head = 0; head < pDevEvo->numHeads; head++) { + if (nvDpyIdListIsEmpty(pParams->head[head].dpyIdList)) { + continue; } - } -done: - nvFree(pDscOutParams); - nvFree(pModesetParams); - if (pGroup != NULL) { - pGroup->destroy(); + if (!ConstructDpLibIsModesetPossibleParamsOneHead( + pDpLibConnector, + head, + pParams->head[head].displayId, + pParams->head[head].dpyIdList, + pParams->head[head].colorSpace, + pParams->head[head].colorBpc, + pParams->head[head].pModeValidationParams, + pParams->head[head].pTimings, + pParams->head[head].b2Heads1Or, + &dpErrorCode[head], + &dpImpParams)) { + goto done; + } } - return ret; -} -/* - * Finishes DisplayPort mode validation. Returns TRUE if the complete - * configuration is possible, and FALSE if it can't be achieved. - */ -NvBool nvDPEndValidation(NVDispEvoPtr pDispEvo) -{ - NvBool ret = TRUE; - NVConnectorEvoPtr pConnectorEvo; + ret = pDpLibConnector->connector->dpLinkIsModePossible(dpImpParams); + + for (head = 0; head < pDevEvo->numHeads; head++) { + DisplayPort::DscParams *pDpDscParams = + dpImpParams.head[head].pDscParams; + NVDscInfoEvoRec *pDscInfo = pParams->head[head].pDscInfo; + const NvBool b2Heads1Or = pParams->head[head].b2Heads1Or; +#if defined(DEBUG) + const NVHwModeTimingsEvo *pTimings = pParams->head[head].pTimings; +#endif + + if (nvDpyIdListIsEmpty(pParams->head[head].dpyIdList)) { + continue; + } - FOR_ALL_EVO_CONNECTORS(pConnectorEvo, pDispEvo) { - if (nvConnectorUsesDPLib(pConnectorEvo)) { - DisplayPort::Connector *connector = - pConnectorEvo->pDpLibConnector->connector; + if (ret) { + if (b2Heads1Or) { + /* + * 2Heads1OR requires either YUV420 or DSC; + * dpDscParams.bEnableDsc is assigned by compoundQueryAttach(). + */ + nvAssert(pDpDscParams->bEnableDsc || + (pTimings->yuv420Mode == NV_YUV420_MODE_HW)); + } - /* endCompoundQuery() must be called for all dp connectors */ - ret = connector->endCompoundQuery() && ret; + if (pDscInfo != NULL) { + nvkms_memset(pDscInfo, 0, sizeof(*pDscInfo)); + + if (pDpDscParams->bEnableDsc) { + pDscInfo->type = NV_DSC_INFO_EVO_TYPE_DP; + + pDscInfo->dp.dscMode = b2Heads1Or ? + NV_DSC_EVO_MODE_DUAL : NV_DSC_EVO_MODE_SINGLE; + pDscInfo->dp.bitsPerPixelX16 = pDpDscParams->bitsPerPixelX16; + ct_assert(sizeof(pDscInfo->dp.pps) == + sizeof(pDpDscParams->pDscOutParams->PPS)); + nvkms_memcpy(pDscInfo->dp.pps, + pDpDscParams->pDscOutParams->PPS, + sizeof(pDscInfo->dp.pps)); + } else { + pDscInfo->type = NV_DSC_INFO_EVO_TYPE_DISABLED; + } + } + } else if (dpErrorCode[head] != DisplayPort::DP_IMP_ERROR_NONE) { + *pFailedHeadMask |= NVBIT(head); } } + nvAssert(ret || (*pFailedHeadMask != 0x0)); + +done: + for (head = 0; head < pDevEvo->numHeads; head++) { + DestructDpLibIsModesetPossibleParamsOneHead(head, &dpImpParams); + } + return ret; } @@ -567,37 +600,43 @@ NvBool nvDPValidateModeForDpyEvo( NVDscInfoEvoRec *pDscInfo) { const NVConnectorEvoRec *pConnectorEvo = pDpyEvo->pConnectorEvo; + const NVDispEvoRec *pDispEvo = pConnectorEvo->pDispEvo; + NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + NvU32 failedHeadMask = 0x0; + const NvU32 head = 0; + NvBool ret; + + NVDpLibIsModePossibleParamsRec *pParams = (NVDpLibIsModePossibleParamsRec*) + nvPreallocGet(pDevEvo, PREALLOC_TYPE_DPLIB_IS_MODE_POSSIBLE_PARAMS, + sizeof(*pParams)); + nvAssert(pParams != NULL); + + nvkms_memset(pParams, 0, sizeof(*pParams)); nvAssert(nvConnectorUsesDPLib(pConnectorEvo)); - DisplayPort::Connector *connector = - pConnectorEvo->pDpLibConnector->connector; + pParams->head[head].displayId = 0; + pParams->head[head].dpyIdList = nvAddDpyIdToEmptyDpyIdList(pDpyEvo->id); + pParams->head[head].colorSpace = colorSpace; + pParams->head[head].colorBpc = colorBpc; + pParams->head[head].pModeValidationParams = pModeValidationParams; + pParams->head[head].pTimings = pTimings; + pParams->head[head].b2Heads1Or = b2Heads1Or; + pParams->head[head].pDscInfo = pDscInfo; + + ret = nvDPLibIsModePossible(pConnectorEvo->pDpLibConnector, pParams, + &failedHeadMask); - connector->beginCompoundQuery(); - NvBool ret = nvDPLibValidateTimings(pDpyEvo->pDispEvo, - 0 /* head */, - 0 /* displayId */, - nvAddDpyIdToEmptyDpyIdList(pDpyEvo->id), - colorSpace, - colorBpc, - pModeValidationParams, - pTimings, - b2Heads1Or, - pDscInfo); - connector->endCompoundQuery(); + nvPreallocRelease(pDevEvo, PREALLOC_TYPE_DPLIB_IS_MODE_POSSIBLE_PARAMS); return ret; } -/* - * Notify the DisplayPort library that a given mode is about to be set on a - * given head. The configuration for this head must have previously been - * validated by a call to nvDPLibValidateTimings. - */ static -void NotifyAttachBegin(NVDPLibConnectorPtr pDpLibConnector, - const NvU32 head, - const NVDPLibModesetStateRec *pDpLibModesetState) +void DPAttachBeginOneHead(NVDPLibConnectorPtr pDpLibConnector, + const NvU32 head, + const NVDPLibModesetStateRec *pDpLibModesetState, + DisplayPort::DpPreModesetParams *pPreModesetParams) { const NVConnectorEvoRec *pConnectorEvo = pDpLibConnector->pConnectorEvo; const NVDispEvoRec *pDispEvo = pConnectorEvo->pDispEvo; @@ -614,45 +653,29 @@ void NotifyAttachBegin(NVDPLibConnectorPtr pDpLibConnector, } } - pDpLibConnector->connector->notifyAttachBegin( - pDpLibConnector->pGroup[head], - *pParams); + pPreModesetParams->head[head].pTarget = pDpLibConnector->pGroup[head]; + pPreModesetParams->head[head].pModesetParams = pParams; + + pPreModesetParams->headMask |= NVBIT(head); } -/* - * Notify the DisplayPort library that a modeset on a head begun by - * nvDPNotifyAttachBegin is finished. - */ -static void NotifyAttachEnd(NVDPLibConnectorPtr pDpLibConnector, NvU32 head) +static void DPAttachEndOneHead(NVDPLibConnectorPtr pDpLibConnector, NvU32 head) { - pDpLibConnector->connector->notifyAttachEnd(false); pDpLibConnector->headMask |= NVBIT(head); } -/* - * Notify the DisplayPort library that the given head driving displays on this - * connector is about to be shut down. - */ -static void NotifyDetachBegin(NVDPLibConnectorPtr pDpLibConnector, const NvU32 head) +static void DPDetachBeginOneHead(NVDPLibConnectorPtr pDpLibConnector, + const NvU32 head, + DisplayPort::DpPreModesetParams *pPreModesetParams) { - /* - * The firmware group is the VBIOS monitor group the DP Library manages - * internally. In notifyDetachBegin(NULL), the NULL defaults to firmware - * group. - */ - pDpLibConnector->connector->notifyDetachBegin( - pDpLibConnector->headInFirmware ? - NULL : pDpLibConnector->pGroup[head]); + nvAssert((NVBIT(head) & pDpLibConnector->headMask) != 0x0); + + pPreModesetParams->head[head].pTarget = NULL; + pPreModesetParams->headMask |= NVBIT(head); } -/* - * Notify the DisplayPort library that the driver has finished shutting down a - * head that was previously driving this connector. - */ -static void NotifyDetachEnd(NVDPLibConnectorPtr pDpLibConnector, const NvU32 head) +static void DPDetachEndOneHead(NVDPLibConnectorPtr pDpLibConnector, const NvU32 head) { - pDpLibConnector->connector->notifyDetachEnd(); - if (!pDpLibConnector->headInFirmware) { const NVConnectorEvoRec *pConnectorEvo = pDpLibConnector->pConnectorEvo; @@ -686,10 +709,12 @@ void nvDPPreSetMode(NVDPLibConnectorPtr pDpLibConnector, { const NVConnectorEvoRec *pConnectorEvo = pDpLibConnector->pConnectorEvo; + DisplayPort::Connector *connector = pDpLibConnector->connector; NVDispEvoRec *pDispEvo = pConnectorEvo->pDispEvo; const NvU32 oldHeadMask = pDpLibConnector->headMask; const NvU32 newHeadMask = nvConnectorGetAttachedHeadMaskEvo(pConnectorEvo); + DisplayPort::DpPreModesetParams preModesetParams = { }; for (NvU32 head = 0; head < pDispEvo->pDevEvo->numHeads; head++) { @@ -697,17 +722,20 @@ void nvDPPreSetMode(NVDPLibConnectorPtr pDpLibConnector, (oldHeadMask & NVBIT(head)) == 0x0) { if (pModesetUpdateState->pDpLibModesetState[head] != NULL) { - NotifyAttachBegin(pDpLibConnector, - head, - pModesetUpdateState->pDpLibModesetState[head]); + DPAttachBeginOneHead(pDpLibConnector, + head, + pModesetUpdateState->pDpLibModesetState[head], + &preModesetParams); } } else if ((newHeadMask & NVBIT(head)) == 0x0 && (oldHeadMask & NVBIT(head)) != 0x0) { - NotifyDetachBegin(pDpLibConnector, head); + DPDetachBeginOneHead(pDpLibConnector, head, &preModesetParams); } } + + connector->dpPreModeset(preModesetParams); } /* @@ -720,23 +748,26 @@ void nvDPPostSetMode(NVDPLibConnectorPtr pDpLibConnector, { const NVConnectorEvoRec *pConnectorEvo = pDpLibConnector->pConnectorEvo; + DisplayPort::Connector *connector = pDpLibConnector->connector; const NVDispEvoRec *pDispEvo = pConnectorEvo->pDispEvo; const NvU32 oldHeadMask = pDpLibConnector->headMask; const NvU32 newHeadMask = nvConnectorGetAttachedHeadMaskEvo(pConnectorEvo); + connector->dpPostModeset(); + for (NvU32 head = 0; head < pDispEvo->pDevEvo->numHeads; head++) { if ((newHeadMask & NVBIT(head)) != 0x0 && (oldHeadMask & NVBIT(head)) == 0x0) { if (pModesetUpdateState->pDpLibModesetState[head] != NULL) { - NotifyAttachEnd(pDpLibConnector, head); + DPAttachEndOneHead(pDpLibConnector, head); } } else if ((newHeadMask & NVBIT(head)) == 0x0 && (oldHeadMask & NVBIT(head)) != 0x0) { - NotifyDetachEnd(pDpLibConnector, head); + DPDetachEndOneHead(pDpLibConnector, head); } } @@ -954,7 +985,8 @@ void nvDPSetAllowMultiStreamingOneConnector( } static NvBool IsDpSinkMstCapableForceSst(const NVDispEvoRec *pDispEvo, - const NvU32 apiHead) + const NvU32 apiHead, + void *pData) { const NVDispApiHeadStateEvoRec *pApiHeadState = &pDispEvo->apiHeadState[apiHead]; @@ -976,7 +1008,8 @@ static NvBool IsDpSinkMstCapableForceSst(const NVDispEvoRec *pDispEvo, static NvBool IsDpLinkTransitionWaitingForHeadShutDown( const NVDispEvoRec *pDispEvo, - const NvU32 apiHead) + const NvU32 apiHead, + void *pData) { const NVDispApiHeadStateEvoRec *pApiHeadState = &pDispEvo->apiHeadState[apiHead]; @@ -1011,7 +1044,9 @@ void nvDPSetAllowMultiStreaming(NVDevEvoPtr pDevEvo, NvBool allowMST) return; } - nvShutDownApiHeads(pDevEvo, IsDpSinkMstCapableForceSst); + nvShutDownApiHeads(pDevEvo, pDevEvo->pNvKmsOpenDev, + IsDpSinkMstCapableForceSst, NULL /* pData */, + TRUE /* doRasterLock */); /* * Heads driving MST capable sinks in force SST mode, are shut down. Now you @@ -1036,8 +1071,10 @@ void nvDPSetAllowMultiStreaming(NVDevEvoPtr pDevEvo, NvBool allowMST) } /* Shut down all DisplayPort heads that need to transition to/from SST. */ - nvShutDownApiHeads(pDevEvo, - IsDpLinkTransitionWaitingForHeadShutDown); + nvShutDownApiHeads(pDevEvo, pDevEvo->pNvKmsOpenDev, + IsDpLinkTransitionWaitingForHeadShutDown, + NULL /* pData */, + TRUE /* doRasterLock */); /* * Handle any pending timers the DP library scheduled to notify us diff --git a/src/nvidia-modeset/src/dp/nvdp-device.cpp b/src/nvidia-modeset/src/dp/nvdp-device.cpp index 7bb79cd0c3..f9015042d3 100644 --- a/src/nvidia-modeset/src/dp/nvdp-device.cpp +++ b/src/nvidia-modeset/src/dp/nvdp-device.cpp @@ -155,3 +155,15 @@ NvBool nvDPDpyIsDscPossible(const NVDpyEvoRec *pDpyEvo) } return pDpyEvo->dp.pDpLibDevice->device->isDSCPossible(); } + +NvBool nvDPDpyGetDpcdRevision(const NVDpyEvoRec *pDpyEvo, + unsigned int *major, + unsigned int *minor) +{ + if (!nvDpyUsesDPLib(pDpyEvo) || + (pDpyEvo->dp.pDpLibDevice == NULL)) { + return FALSE; + } + + return pDpyEvo->dp.pDpLibDevice->device->getDpcdRevision(major, minor); +} diff --git a/src/nvidia-modeset/src/g_nvkms-evo-states.c b/src/nvidia-modeset/src/g_nvkms-evo-states.c index 9c6c633a3f..373241e786 100644 --- a/src/nvidia-modeset/src/g_nvkms-evo-states.c +++ b/src/nvidia-modeset/src/g_nvkms-evo-states.c @@ -50,9 +50,8 @@ static NvBool EvoLockStateLockHeadsFrameLockServerManyHeads(NVDispEvoPtr, NVEvoS static NvBool EvoLockStateLockHeadsFrameLockServerManyHeadsPlusRef(NVDispEvoPtr, NVEvoSubDevPtr, NVEvoLockAction, const NvU32 *pHeads); static NvBool EvoLockStateLockHeadsFrameLockServerPlusRef(NVDispEvoPtr, NVEvoSubDevPtr, NVEvoLockAction, const NvU32 *pHeads); static NvBool EvoLockStateLockHeadsPlusRef(NVDispEvoPtr, NVEvoSubDevPtr, NVEvoLockAction, const NvU32 *pHeads); -static NvBool EvoLockStateMergeMode(NVDispEvoPtr, NVEvoSubDevPtr, NVEvoLockAction, const NvU32 *pHeads); -static NvBool EvoLockStateMergeModeVrr(NVDispEvoPtr, NVEvoSubDevPtr, NVEvoLockAction, const NvU32 *pHeads); static NvBool EvoLockStateNoLock(NVDispEvoPtr, NVEvoSubDevPtr, NVEvoLockAction, const NvU32 *pHeads); +static NvBool EvoLockStateProhibitLock(NVDispEvoPtr, NVEvoSubDevPtr, NVEvoLockAction, const NvU32 *pHeads); static NvBool EvoLockStateSliLastSecondary(NVDispEvoPtr, NVEvoSubDevPtr, NVEvoLockAction, const NvU32 *pHeads); static NvBool EvoLockStateSliLastSecondaryFrameLockClient(NVDispEvoPtr, NVEvoSubDevPtr, NVEvoLockAction, const NvU32 *pHeads); static NvBool EvoLockStateSliLastSecondaryLockHeads(NVDispEvoPtr, NVEvoSubDevPtr, NVEvoLockAction, const NvU32 *pHeads); @@ -85,7 +84,6 @@ static NvBool EvoLockStateSliSecondaryFrameLockClient(NVDispEvoPtr, NVEvoSubDevP static NvBool EvoLockStateSliSecondaryLockHeads(NVDispEvoPtr, NVEvoSubDevPtr, NVEvoLockAction, const NvU32 *pHeads); static NvBool EvoLockStateSliSecondaryLockHeadsFrameLockClient(NVDispEvoPtr, NVEvoSubDevPtr, NVEvoLockAction, const NvU32 *pHeads); static NvBool EvoLockStateSliSecondaryLockHeadsFrameLockClientManyHeads(NVDispEvoPtr, NVEvoSubDevPtr, NVEvoLockAction, const NvU32 *pHeads); -static NvBool EvoLockStateVrr(NVDispEvoPtr, NVEvoSubDevPtr, NVEvoLockAction, const NvU32 *pHeads); static NvBool EvoLockStateFrameLockClient( NVDispEvoPtr pDispEvo, @@ -1409,7 +1407,7 @@ static NvBool EvoLockStateLockHeadsPlusRef( } } -static NvBool EvoLockStateMergeMode( +static NvBool EvoLockStateNoLock( NVDispEvoPtr pDispEvo, NVEvoSubDevPtr pEvoSubDev, NVEvoLockAction action, @@ -1420,59 +1418,13 @@ static NvBool EvoLockStateMergeMode( switch (action) { - case NV_EVO_DISABLE_MERGE_MODE: + case NV_EVO_PROHIBIT_LOCK: if (!queryOnly) { nvEvoLockHWStateNoLock(pDispEvo, pEvoSubDev, pHeads); - pEvoSubDev->scanLockState = EvoLockStateNoLock; - } - return TRUE; - - case NV_EVO_ENABLE_VRR: - if (!queryOnly) { - nvEvoLockHWStateNoChange(pDispEvo, pEvoSubDev, pHeads); - pEvoSubDev->scanLockState = EvoLockStateMergeModeVrr; - } - return TRUE; - - default: - return FALSE; - } -} - -static NvBool EvoLockStateMergeModeVrr( - NVDispEvoPtr pDispEvo, - NVEvoSubDevPtr pEvoSubDev, - NVEvoLockAction action, - const NvU32 *pHeads -) -{ - NvBool queryOnly = pHeads == NULL; - - switch (action) { - - case NV_EVO_DISABLE_VRR: - if (!queryOnly) { - nvEvoLockHWStateMergeMode(pDispEvo, pEvoSubDev, pHeads); - pEvoSubDev->scanLockState = EvoLockStateMergeMode; + pEvoSubDev->scanLockState = EvoLockStateProhibitLock; } return TRUE; - default: - return FALSE; - } -} - -static NvBool EvoLockStateNoLock( - NVDispEvoPtr pDispEvo, - NVEvoSubDevPtr pEvoSubDev, - NVEvoLockAction action, - const NvU32 *pHeads -) -{ - NvBool queryOnly = pHeads == NULL; - - switch (action) { - case NV_EVO_ADD_FRAME_LOCK_CLIENT: if (!queryOnly) { nvEvoLockHWStateFrameLockClient(pDispEvo, pEvoSubDev, pHeads); @@ -1508,13 +1460,6 @@ static NvBool EvoLockStateNoLock( } return TRUE; - case NV_EVO_ENABLE_VRR: - if (!queryOnly) { - nvEvoLockHWStateNoLock(pDispEvo, pEvoSubDev, pHeads); - pEvoSubDev->scanLockState = EvoLockStateVrr; - } - return TRUE; - case NV_EVO_ADD_SLI_SECONDARY: if (!queryOnly) { nvEvoLockHWStateSliSecondary(pDispEvo, pEvoSubDev, pHeads); @@ -1522,10 +1467,26 @@ static NvBool EvoLockStateNoLock( } return TRUE; - case NV_EVO_ENABLE_MERGE_MODE: + default: + return FALSE; + } +} + +static NvBool EvoLockStateProhibitLock( + NVDispEvoPtr pDispEvo, + NVEvoSubDevPtr pEvoSubDev, + NVEvoLockAction action, + const NvU32 *pHeads +) +{ + NvBool queryOnly = pHeads == NULL; + + switch (action) { + + case NV_EVO_PROHIBIT_LOCK_DISABLE: if (!queryOnly) { - nvEvoLockHWStateMergeMode(pDispEvo, pEvoSubDev, pHeads); - pEvoSubDev->scanLockState = EvoLockStateMergeMode; + nvEvoLockHWStateNoLock(pDispEvo, pEvoSubDev, pHeads); + pEvoSubDev->scanLockState = EvoLockStateNoLock; } return TRUE; @@ -2848,29 +2809,6 @@ static NvBool EvoLockStateSliSecondaryLockHeadsFrameLockClientManyHeads( } } -static NvBool EvoLockStateVrr( - NVDispEvoPtr pDispEvo, - NVEvoSubDevPtr pEvoSubDev, - NVEvoLockAction action, - const NvU32 *pHeads -) -{ - NvBool queryOnly = pHeads == NULL; - - switch (action) { - - case NV_EVO_DISABLE_VRR: - if (!queryOnly) { - nvEvoLockHWStateNoLock(pDispEvo, pEvoSubDev, pHeads); - pEvoSubDev->scanLockState = EvoLockStateNoLock; - } - return TRUE; - - default: - return FALSE; - } -} - void nvEvoStateStartNoLock( NVEvoSubDevPtr pEvoSubDev ) @@ -2878,3 +2816,11 @@ void nvEvoStateStartNoLock( pEvoSubDev->scanLockState = EvoLockStateNoLock; } +#if defined(DEBUG) +void nvEvoStateAssertNoLock( + const NVEvoSubDevRec *pEvoSubDev +) +{ + nvAssert(pEvoSubDev->scanLockState == EvoLockStateNoLock); +} +#endif diff --git a/src/nvidia-modeset/src/nvkms-attributes.c b/src/nvidia-modeset/src/nvkms-attributes.c index 9505c1344b..cad8d2b856 100644 --- a/src/nvidia-modeset/src/nvkms-attributes.c +++ b/src/nvidia-modeset/src/nvkms-attributes.c @@ -430,18 +430,7 @@ static NvBool GetCurrentDitheringDepth(const NVDpyEvoRec *pDpyEvo, static NvBool DigitalVibranceAvailable(const NVDpyEvoRec *pDpyEvo) { - const NVDispEvoRec *pDispEvo = pDpyEvo->pDispEvo; - NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; - - if (!nvDpyEvoIsActive(pDpyEvo)) { - return FALSE; - } - - if (!pDevEvo->hal->caps.supportsDigitalVibrance) { - return FALSE; - } - - return TRUE; + return nvDpyEvoIsActive(pDpyEvo); } /*! @@ -619,9 +608,11 @@ static void DpyPostColorSpaceOrRangeSetEvo(NVDpyEvoPtr pDpyEvo) NVEvoUpdateState updateState = { }; NVDispEvoRec *pDispEvo = pDpyEvo->pDispEvo; NVDispApiHeadStateEvoRec *pApiHeadState; - enum NvYuv420Mode yuv420Mode; - enum NvKmsOutputTf tf; + NvU8 hdmiFrlBpc; NvU32 head; +#if defined(DEBUG) + NvU32 hwHead; +#endif if (pDpyEvo->apiHead == NV_INVALID_HEAD) { return; @@ -632,12 +623,11 @@ static void DpyPostColorSpaceOrRangeSetEvo(NVDpyEvoPtr pDpyEvo) (nvDpyIdIsInDpyIdList(pDpyEvo->id, pApiHeadState->activeDpys))); head = nvGetPrimaryHwHead(pDispEvo, pDpyEvo->apiHead); - yuv420Mode = pDispEvo->headState[head].timings.yuv420Mode; - tf = pDispEvo->headState[head].tf; + hdmiFrlBpc = pDispEvo->headState[head].hdmiFrlBpc; #if defined(DEBUG) - FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { - nvAssert(yuv420Mode == pDispEvo->headState[head].timings.yuv420Mode); - nvAssert(tf == pDispEvo->headState[head].tf); + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, hwHead) { + nvAssert(pDispEvo->headState[head].timings.yuv420Mode == + pDispEvo->headState[hwHead].timings.yuv420Mode); } #endif @@ -646,8 +636,9 @@ static void DpyPostColorSpaceOrRangeSetEvo(NVDpyEvoPtr pDpyEvo) * timings and the requested color space and range. */ if (!nvChooseCurrentColorSpaceAndRangeEvo(pDpyEvo, - yuv420Mode, - tf, + &pDispEvo->headState[head].timings, + hdmiFrlBpc, + pApiHeadState->colorimetry, pDpyEvo->requestedColorSpace, pDpyEvo->requestedColorRange, &colorSpace, @@ -676,6 +667,7 @@ static void DpyPostColorSpaceOrRangeSetEvo(NVDpyEvoPtr pDpyEvo) nvUpdateCurrentHardwareColorSpaceAndRangeEvo(pDispEvo, head, + pApiHeadState->colorimetry, pApiHeadState->attributes.colorSpace, pApiHeadState->attributes.colorRange, &updateState); diff --git a/src/nvidia-modeset/src/nvkms-console-restore.c b/src/nvidia-modeset/src/nvkms-console-restore.c index bb9d96695f..810c5c6b42 100644 --- a/src/nvidia-modeset/src/nvkms-console-restore.c +++ b/src/nvidia-modeset/src/nvkms-console-restore.c @@ -165,6 +165,16 @@ static void FlipBaseToNull(NVDevEvoPtr pDevEvo) i++; nvAssert(i <= numFlipApiHeads); + // Disable HDR on head + pRequestApiHead->tf.specified = TRUE; + pRequestApiHead->tf.val = NVKMS_OUTPUT_TF_NONE; + + pRequestApiHead->hdrInfoFrame.specified = TRUE; + pRequestApiHead->hdrInfoFrame.enabled = FALSE; + + pRequestApiHead->colorimetry.specified = TRUE; + pRequestApiHead->colorimetry.val = NVKMS_OUTPUT_COLORIMETRY_DEFAULT; + for (layer = 0; layer < pDevEvo->apiHead[apiHead].numLayers; layer++) { pRequestApiHead->layer[layer].surface.specified = TRUE; // No need to specify sizeIn/sizeOut as we are flipping NULL surface. @@ -172,14 +182,13 @@ static void FlipBaseToNull(NVDevEvoPtr pDevEvo) pRequestApiHead->layer[layer].completionNotifier.specified = TRUE; pRequestApiHead->layer[layer].syncObjects.specified = TRUE; - // Disable HDR - pRequestApiHead->tf.val = NVKMS_OUTPUT_TF_NONE; - pRequestApiHead->tf.specified = TRUE; + // Disable HDR on layers pRequestApiHead->layer[layer].hdr.enabled = FALSE; pRequestApiHead->layer[layer].hdr.specified = TRUE; - pRequestApiHead->layer[layer].colorspace.val = + + pRequestApiHead->layer[layer].colorSpace.val = NVKMS_INPUT_COLORSPACE_NONE; - pRequestApiHead->layer[layer].colorspace.specified = TRUE; + pRequestApiHead->layer[layer].colorSpace.specified = TRUE; } } } @@ -321,9 +330,9 @@ static NvBool InitModeOneHeadRequest( // Disable other features. pFlip->cursor.imageSpecified = TRUE; - pRequestHead->lut.input.specified = TRUE; - pRequestHead->lut.output.specified = TRUE; - pRequestHead->lut.synchronous = TRUE; + pFlip->lut.input.specified = TRUE; + pFlip->lut.output.specified = TRUE; + pFlip->lut.synchronous = TRUE; pRequestHead->allowGsync = FALSE; pRequestHead->allowAdaptiveSync = NVKMS_ALLOW_ADAPTIVE_SYNC_DISABLED; @@ -950,7 +959,10 @@ NvBool nvEvoRestoreConsole(NVDevEvoPtr pDevEvo, const NvBool allowMST) /* If console restore failed then simply shut down all heads */ if (!ret) { - nvShutDownApiHeads(pDevEvo, NULL /* pTestFunc, shut down all heads */); + nvShutDownApiHeads(pDevEvo, pDevEvo->pNvKmsOpenDev, + NULL /* pTestFunc, shut down all heads */, + NULL /* pData */, + FALSE /* doRasterLock */); } // If restoring the console from here succeeded, then skip triggering RM's diff --git a/src/nvidia-modeset/src/nvkms-ctxdma.c b/src/nvidia-modeset/src/nvkms-ctxdma.c new file mode 100644 index 0000000000..f485c1a4f4 --- /dev/null +++ b/src/nvidia-modeset/src/nvkms-ctxdma.c @@ -0,0 +1,221 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvkms-private.h" +#include "nvkms-ctxdma.h" +#include "nvkms-utils.h" +#include "nvkms-rm.h" +#include "nvkms-rmapi.h" + +#include "class/cl0002.h" /* NV01_CONTEXT_DMA */ + +#include /* NV0002_CTRL_CMD_BIND_CONTEXTDMA */ + +static NvBool GarbageCollectSyncptHelperOneChannel( + NVDevEvoRec *pDevEvo, + NvU32 sd, + NVEvoChannel *pChannel, + NVEvoSyncpt *pSyncpt, + NVEvoChannelMask *pIdledChannelMask) +{ + NvBool isChannelIdle = FALSE; + + if ((pChannel->channelMask & pSyncpt->channelMask) == 0) { + return TRUE; + } + + if ((*pIdledChannelMask) & pChannel->channelMask) { + goto done; + } + + /*! Check whether channel is idle. */ + pDevEvo->hal->IsChannelIdle(pDevEvo, pChannel, sd, &isChannelIdle); + + if (!isChannelIdle) { + return FALSE; + } + + /*! record idle channel mask to use in next check */ + *pIdledChannelMask |= pChannel->channelMask; + +done: + pSyncpt->channelMask &= ~pChannel->channelMask; + return TRUE; +} + +static NvBool GarbageCollectSyncptHelperOneSyncpt( + NVDevEvoRec *pDevEvo, + NVEvoSyncpt *pSyncpt, + NVEvoChannelMask *pIdledChannelMask) +{ + NvBool ret = TRUE; + NvU32 head, sd; + + for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { + + for (head = 0; head < pDevEvo->numHeads; head++) { + NvU32 layer; + + /*! + * If a given channel isn't idle, continue to check if this syncpt + * is used on other channels which may be idle. + */ + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + if (!GarbageCollectSyncptHelperOneChannel( + pDevEvo, + sd, + pDevEvo->head[head].layer[layer], + pSyncpt, + &pIdledChannelMask[sd])) { + ret = FALSE; + } + } + } + } + + return ret; +} + +/*! + * This API try to find free syncpt and then unregisters it. + * It searches global table, and when finds that all channels using this + * syncpt are idle then frees it. It makes sure that syncpt is not part + * of current flip. + */ +static NvBool GarbageCollectSyncpts( + NVDevEvoRec *pDevEvo) +{ + NvU32 i; + NvBool freedSyncpt = FALSE; + NVEvoChannelMask idledChannelMask[NVKMS_MAX_SUBDEVICES] = { 0 }; + + if (!pDevEvo->supportsSyncpts) { + return FALSE; + } + + for (i = 0; i < NV_SYNCPT_GLOBAL_TABLE_LENGTH; i++) { + + NvBool allLayersIdle = NV_TRUE; + + if (pDevEvo->pAllSyncptUsedInCurrentFlip != NULL) { + if (pDevEvo->pAllSyncptUsedInCurrentFlip[i]) { + /*! syncpt is part of current flip, so skip it */ + continue; + } + } + + if (pDevEvo->preSyncptTable[i].surfaceDesc.ctxDmaHandle == 0) { + /*! syncpt isn't registered, so skip it */ + continue; + } + + allLayersIdle = GarbageCollectSyncptHelperOneSyncpt( + pDevEvo, + &pDevEvo->preSyncptTable[i], + idledChannelMask); + + if (allLayersIdle) { + /*! Free handles */ + nvRmFreeSyncptHandle(pDevEvo, &pDevEvo->preSyncptTable[i]); + freedSyncpt = TRUE; + } + } + + return freedSyncpt; +} + +NvU32 nvCtxDmaBind( + NVDevEvoPtr pDevEvo, + NVEvoChannelPtr pChannel, + NvU32 hCtxDma) +{ + NV0002_CTRL_BIND_CONTEXTDMA_PARAMS params = { }; + NvU32 ret; + NvBool retryOnlyOnce = TRUE; + + params.hChannel = pChannel->pb.channel_handle; + +retryOnce: + ret = nvRmApiControl(nvEvoGlobal.clientHandle, + hCtxDma, + NV0002_CTRL_CMD_BIND_CONTEXTDMA, + ¶ms, sizeof(params)); + if (ret != NVOS_STATUS_SUCCESS) { + /*! + * syncpts (lazily freed) occupy space in the disp ctxDma hash + * table, and therefore may cause bind ctxDma to fail. + * Free any unused syncpts and try again. + */ + if (retryOnlyOnce) { + /*! try to free syncpt only once */ + if (GarbageCollectSyncpts(pDevEvo)) { + retryOnlyOnce = FALSE; + goto retryOnce; + } + } + } + return ret; +} + +void nvCtxDmaFree(NVDevEvoPtr pDevEvo, + NvU32 deviceHandle, + NvU32 *hDispCtxDma) +{ + if (*hDispCtxDma) { + nvRmApiFree(nvEvoGlobal.clientHandle, + deviceHandle, *hDispCtxDma); + nvFreeUnixRmHandle(&pDevEvo->handleAllocator, *hDispCtxDma); + *hDispCtxDma = 0; + } +} + +NvU32 nvCtxDmaAlloc(NVDevEvoPtr pDevEvo, NvU32 *pCtxDmaHandle, + NvU32 memoryHandle, NvU32 localCtxDmaFlags, NvU64 limit) +{ + NV_CONTEXT_DMA_ALLOCATION_PARAMS ctxdmaParams = { }; + NvU32 ret, ctxDmaHandle; + + ctxDmaHandle = nvGenerateUnixRmHandle(&pDevEvo->handleAllocator); + if (ctxDmaHandle == 0) { + return NVOS_STATUS_ERROR_GENERIC; + } + + ctxdmaParams.hMemory = memoryHandle; + ctxdmaParams.flags = localCtxDmaFlags; + ctxdmaParams.offset = 0; + ctxdmaParams.limit = limit; + + ret = nvRmApiAlloc(nvEvoGlobal.clientHandle, + pDevEvo->deviceHandle, + ctxDmaHandle, + NV01_CONTEXT_DMA, + &ctxdmaParams); + + if (ret != NVOS_STATUS_SUCCESS) { + nvFreeUnixRmHandle(&pDevEvo->handleAllocator, ctxDmaHandle); + } else { + *pCtxDmaHandle = ctxDmaHandle; + } + + return ret; +} diff --git a/src/nvidia-modeset/src/nvkms-cursor.c b/src/nvidia-modeset/src/nvkms-cursor.c index a766c46679..316d7d22d9 100644 --- a/src/nvidia-modeset/src/nvkms-cursor.c +++ b/src/nvidia-modeset/src/nvkms-cursor.c @@ -118,7 +118,7 @@ SetCursorImageOneHead(NVDispEvoPtr pDispEvo, } if (pSurfaceEvoOld) { - nvEvoDecrementSurfaceRefCnts(pSurfaceEvoOld); + nvEvoDecrementSurfaceRefCnts(pDevEvo, pSurfaceEvoOld); } pDevEvo->gpus[sd].headState[head].cursor.pSurfaceEvo = pSurfaceEvoNew; diff --git a/src/nvidia-modeset/src/nvkms-cursor3.c b/src/nvidia-modeset/src/nvkms-cursor3.c index 354f13864c..6df29a4136 100644 --- a/src/nvidia-modeset/src/nvkms-cursor3.c +++ b/src/nvidia-modeset/src/nvkms-cursor3.c @@ -45,7 +45,7 @@ static void WaitForFreeSpace(NVDevEvoPtr pDevEvo, return; } - if (nvExceedsTimeoutUSec(&startTime, timeout)) { + if (nvExceedsTimeoutUSec(pDevEvo, &startTime, timeout)) { break; } @@ -112,3 +112,4 @@ NVEvoCursorHAL nvEvoCursorC6 = { 256, /* maxSize */ }, }; + diff --git a/src/nvidia-modeset/src/nvkms-dma.c b/src/nvidia-modeset/src/nvkms-dma.c index efa9e24aeb..4438fd093f 100644 --- a/src/nvidia-modeset/src/nvkms-dma.c +++ b/src/nvidia-modeset/src/nvkms-dma.c @@ -167,7 +167,7 @@ NvBool nvEvoPollForEmptyChannel(NVEvoChannelPtr pChannel, NvU32 sd, break; } - if (nvExceedsTimeoutUSec(pStartTime, timeout)) { + if (nvExceedsTimeoutUSec(push_buffer->pDevEvo, pStartTime, timeout)) { return FALSE; } @@ -235,7 +235,7 @@ void nvEvoMakeRoom(NVEvoChannelPtr pChannel, NvU32 count) * isn't much we can do as currently structured, so just reset * startTime. */ - if (nvExceedsTimeoutUSec(&startTime, timeout)) { + if (nvExceedsTimeoutUSec(push_buffer->pDevEvo, &startTime, timeout)) { nvEvoLogDev(push_buffer->pDevEvo, EVO_LOG_ERROR, "Error while waiting for GPU progress: " "0x%08x:%d %d:%d:%d:%d", @@ -306,8 +306,8 @@ static NvBool EvoCheckNotifier(const NVDispEvoRec *pDispEvo, return FALSE; } - if (!nvIsEmulationEvo(pDevEvo) && - nvExceedsTimeoutUSec( + if (nvExceedsTimeoutUSec( + pDevEvo, &startTime, NV_EVO_NOTIFIER_SHORT_TIMEOUT_USEC) && (p->put_offset == EvoCoreReadGet(p, sd))) @@ -470,7 +470,8 @@ void nvEvoResetCRC32Notifier(volatile NvU32 *pCRC32Notifier, EvoWriteNotifier(pCRC32Notifier, reset_val); } -NvBool nvEvoWaitForCRC32Notifier(volatile NvU32 *pCRC32Notifier, +NvBool nvEvoWaitForCRC32Notifier(const NVDevEvoPtr pDevEvo, + volatile NvU32 *pCRC32Notifier, NvU32 offset, NvU32 done_base_bit, NvU32 done_extent_bit, @@ -491,6 +492,7 @@ NvBool nvEvoWaitForCRC32Notifier(volatile NvU32 *pCRC32Notifier, } if (nvExceedsTimeoutUSec( + pDevEvo, &startTime, NV_EVO_NOTIFIER_SHORT_TIMEOUT_USEC)) { return FALSE; diff --git a/src/nvidia-modeset/src/nvkms-dpy.c b/src/nvidia-modeset/src/nvkms-dpy.c index 34e1ded898..aa3fe3b868 100644 --- a/src/nvidia-modeset/src/nvkms-dpy.c +++ b/src/nvidia-modeset/src/nvkms-dpy.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2005-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -81,7 +81,7 @@ static void PatchAndParseEdid (const NVDpyEvoRec *pDpyEvo, NVEvoInfoStringPtr pInfoString); static void ReadAndApplyEdidEvo (NVDpyEvoPtr pDpyEvo, struct NvKmsQueryDpyDynamicDataParams *pParams); -static NvBool GetFixedModeTimings (NVDpyEvoPtr pDpyEvo); +static NvBool GetFixedModeTimings (NVDpyEvoPtr pDpyEvo, struct NvKmsSuperframeInfo *pSuperframeInfo); static NvBool ReadDSITimingsFromResman (const NVDpyEvoRec *pDpyEvo, NVT_TIMING *pTimings, NvU8 *pBpc); @@ -114,7 +114,9 @@ static NvBool DpyConnectEvo( if ((pDpyEvo->pConnectorEvo->signalFormat == NVKMS_CONNECTOR_SIGNAL_FORMAT_DSI) || nvConnectorIsDPSerializer(pDpyEvo->pConnectorEvo)) { - return GetFixedModeTimings(pDpyEvo); + if (!GetFixedModeTimings(pDpyEvo, &pParams->reply.superframeInfo)) { + return FALSE; + } } else { ReadAndApplyEdidEvo(pDpyEvo, pParams); } @@ -460,10 +462,84 @@ static NvBool ReadDSITimingsFromResman( return TRUE; } +static NvBool ParseSuperframeInfo( + NVDpyEvoRec *pDpyEvo, + const NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS *pParams, + struct NvKmsSuperframeInfo *pSuperframeInfo) +{ + NvU8 i; + + if (pParams->superframeInfo.numViews == 0) { + return TRUE; + } + + // Currently, we support only dual view superframe. + if (pParams->superframeInfo.numViews != 2) { + nvEvoLog(EVO_LOG_ERROR, "Invalid number of superframe views"); + return FALSE; + } + + // Currently, we support only packed symmetrical side-by-side superframe. + if ((pParams->superframeInfo.view[0].width * pParams->superframeInfo.numViews) != + pParams->hActive) { + nvEvoLog(EVO_LOG_ERROR, "The width of Superframe view[0] is invalid"); + return FALSE; + } + + if (pParams->superframeInfo.view[0].height != pParams->vActive) { + nvEvoLog(EVO_LOG_ERROR, "The height of Superframe view[0] is invalid"); + return FALSE; + } + + pSuperframeInfo->numViews = 0; + + for (i = 0; i < pParams->superframeInfo.numViews; i++) { + // All superframe views must not have horizontal spacing in between them. + if ((pParams->superframeInfo.view[0].width * i) != + pParams->superframeInfo.view[i].x) { + nvEvoLog(EVO_LOG_ERROR, "The x offset of Superframe view[%u] is invalid", i); + goto fail; + } + + // All superframe views must have y offset as 0. + if (pParams->superframeInfo.view[i].y != 0) { + nvEvoLog(EVO_LOG_ERROR, "The y offset of Superframe view[%u] is invalid", i); + goto fail; + } + + // All superframe views must have the same width. + if (pParams->superframeInfo.view[0].width != + pParams->superframeInfo.view[i].width) { + nvEvoLog(EVO_LOG_ERROR, "The width of Superframe view[%u] is invalid", i); + goto fail; + } + + // All superframe views must have the same height. + if (pParams->superframeInfo.view[0].height != + pParams->superframeInfo.view[i].height) { + nvEvoLog(EVO_LOG_ERROR, "The height of Superframe view[%u] is invalid", i); + goto fail; + } + + pSuperframeInfo->view[i].x = pParams->superframeInfo.view[i].x; + pSuperframeInfo->view[i].width = pParams->superframeInfo.view[i].width; + pSuperframeInfo->view[i].y = pParams->superframeInfo.view[i].y; + pSuperframeInfo->view[i].height = pParams->superframeInfo.view[i].height; + pSuperframeInfo->numViews++; + } + + return TRUE; + +fail: + nvkms_memset(pSuperframeInfo, 0, sizeof(*pSuperframeInfo)); + return FALSE; +} + static NvBool ReadDPSerializerTimings( - const NVDpyEvoRec *pDpyEvo, + NVDpyEvoRec *pDpyEvo, NVT_TIMING *pTimings, - NvU8 *pBpc) + NvU8 *pBpc, + struct NvKmsSuperframeInfo *pSuperframeInfo) { NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS timingParams = { }; NVDispEvoPtr pDispEvo = pDpyEvo->pDispEvo; @@ -492,6 +568,10 @@ static NvBool ReadDPSerializerTimings( return FALSE; } + if (!ParseSuperframeInfo(pDpyEvo, &timingParams, pSuperframeInfo)) { + return FALSE; + } + nvkms_memset(pTimings, 0, sizeof(NVT_TIMING)); pTimings->HVisible = timingParams.hActive; @@ -515,7 +595,8 @@ static NvBool ReadDPSerializerTimings( } static NvBool GetFixedModeTimings( - NVDpyEvoPtr pDpyEvo) + NVDpyEvoPtr pDpyEvo, + struct NvKmsSuperframeInfo *pSuperframeInfo) { NVT_TIMING timings = { }; NvBool ret = FALSE; @@ -524,7 +605,8 @@ static NvBool GetFixedModeTimings( if (pDpyEvo->pConnectorEvo->signalFormat == NVKMS_CONNECTOR_SIGNAL_FORMAT_DSI) { ret = ReadDSITimingsFromResman(pDpyEvo, &timings, &bpc); } else if (nvConnectorIsDPSerializer(pDpyEvo->pConnectorEvo)) { - ret = ReadDPSerializerTimings(pDpyEvo, &timings, &bpc); + ret = ReadDPSerializerTimings(pDpyEvo, &timings, &bpc, + pSuperframeInfo); } if (!ret) { @@ -1184,7 +1266,6 @@ static NvBool ValidateEdid(const NVDpyEvoRec *pDpyEvo, NVEdidPtr pEdid, const NvBool ignoreEdidChecksum) { NvU32 status, tmpStatus; - int errorCount = 0; status = NvTiming_EDIDValidationMask(pEdid->buffer, pEdid->length, TRUE); tmpStatus = status; @@ -1207,7 +1288,6 @@ static NvBool ValidateEdid(const NVDpyEvoRec *pDpyEvo, NVEdidPtr pEdid, nvEvoLogInfoString(pInfoString, "- The EDID has an unrecognized version."); tmpStatus &= ~NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_VERSION); - errorCount++; } if (status & @@ -1215,7 +1295,6 @@ static NvBool ValidateEdid(const NVDpyEvoRec *pDpyEvo, NVEdidPtr pEdid, nvEvoLogInfoString(pInfoString, "- The EDID is too short."); tmpStatus &= ~NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_SIZE); - errorCount++; } if (status & @@ -1237,7 +1316,6 @@ static NvBool ValidateEdid(const NVDpyEvoRec *pDpyEvo, NVEdidPtr pEdid, "timings beyond the capabilities of your display, and " "could damage your hardware. Please use with care."); tmpStatus &= ~NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_CHECKSUM); - errorCount++; } if (status & @@ -1245,7 +1323,6 @@ static NvBool ValidateEdid(const NVDpyEvoRec *pDpyEvo, NVEdidPtr pEdid, nvEvoLogInfoString(pInfoString, "- The EDID has a bad range limit."); tmpStatus &= ~NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_RANGE_LIMIT); - errorCount++; } if (status & @@ -1253,7 +1330,6 @@ static NvBool ValidateEdid(const NVDpyEvoRec *pDpyEvo, NVEdidPtr pEdid, nvEvoLogInfoString(pInfoString, "- The EDID has a bad detailed timing descriptor."); tmpStatus &= ~NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_DTD); - errorCount++; } if (status & @@ -1262,7 +1338,6 @@ static NvBool ValidateEdid(const NVDpyEvoRec *pDpyEvo, NVEdidPtr pEdid, "- The EDID has an extension block with a bad detailed " "timing descriptor."); tmpStatus &= ~NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_DTD); - errorCount++; } if (status & @@ -1270,13 +1345,11 @@ static NvBool ValidateEdid(const NVDpyEvoRec *pDpyEvo, NVEdidPtr pEdid, nvEvoLogInfoString(pInfoString, "- The EDID extension block is invalid."); tmpStatus &= ~NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT); - errorCount++; } if (tmpStatus) { nvEvoLogInfoString(pInfoString, "- The EDID has an unrecognized error."); - errorCount++; } /* @@ -2283,6 +2356,8 @@ NVDpyEvoPtr nvAllocDpyEvo(NVDispEvoPtr pDispEvo, void nvFreeDpyEvo(NVDispEvoPtr pDispEvo, NVDpyEvoPtr pDpyEvo) { + nvCancelSDRTransitionTimer(pDpyEvo); + DpyDisconnectEvo(pDpyEvo); // Let the DP library host implementation handle deleting a pDpy as if the @@ -2333,12 +2408,12 @@ NVConnectorEvoPtr nvGetConnectorFromDisp(NVDispEvoPtr pDispEvo, NVDpyId dpyId) return NULL; } -static const NVT_HDR_INFOFRAME_PAYLOAD NV_SDR_PAYLOAD = +void nvDpyAssignSDRInfoFramePayload(NVT_HDR_INFOFRAME_PAYLOAD *pPayload) { - .eotf = NVT_CEA861_HDR_INFOFRAME_EOTF_SDR_GAMMA, - .static_metadata_desc_id = NVT_CEA861_STATIC_METADATA_SM0 - // type1 is empty - no metadata -}; + nvkms_memset(pPayload, 0, sizeof(*pPayload)); + pPayload->eotf = NVT_CEA861_HDR_INFOFRAME_EOTF_SDR_GAMMA; + pPayload->static_metadata_desc_id = NVT_CEA861_STATIC_METADATA_SM0; +} static void UpdateDpHDRInfoFrame(const NVDispEvoRec *pDispEvo, const NvU32 head) { @@ -2372,13 +2447,11 @@ static void UpdateDpHDRInfoFrame(const NVDispEvoRec *pDispEvo, const NvU32 head) nvAssert((sizeof(sdp->db) - 2) >= sizeof(NVT_HDR_INFOFRAME_PAYLOAD)); - if (pHeadState->hdr.outputState == NVKMS_HDR_OUTPUT_STATE_HDR) { + if (pHeadState->hdrInfoFrame.state == NVKMS_HDR_INFOFRAME_STATE_ENABLED) { NVT_HDR_INFOFRAME_PAYLOAD *payload = (NVT_HDR_INFOFRAME_PAYLOAD *) &sdp->db.db2; - // XXX HDR TODO: Support EOTFs other than PQ. - nvAssert(pHeadState->tf == NVKMS_OUTPUT_TF_PQ); - payload->eotf = NVT_CEA861_HDR_INFOFRAME_EOTF_ST2084; + payload->eotf = pHeadState->hdrInfoFrame.eotf; payload->static_metadata_desc_id = NVT_CEA861_STATIC_METADATA_SM0; @@ -2386,21 +2459,21 @@ static void UpdateDpHDRInfoFrame(const NVDispEvoRec *pDispEvo, const NvU32 head) nvAssert(sizeof(NVT_HDR_INFOFRAME_MASTERING_DATA) == (sizeof(struct NvKmsHDRStaticMetadata))); nvkms_memcpy(&payload->type1, - &pHeadState->hdr.staticMetadata, + &pHeadState->hdrInfoFrame.staticMetadata, sizeof(NVT_HDR_INFOFRAME_MASTERING_DATA)); params.transmitControl = DRF_DEF(0073_CTRL_SPECIFIC, _SET_OD_PACKET_TRANSMIT_CONTROL, _SINGLE_FRAME, _DISABLE); - } else if (pHeadState->hdr.outputState == - NVKMS_HDR_OUTPUT_STATE_TRANSITIONING_TO_SDR) { - nvkms_memcpy(&sdp->db.db2, &NV_SDR_PAYLOAD, sizeof(NVT_HDR_INFOFRAME_PAYLOAD)); + } else if (pHeadState->hdrInfoFrame.state == + NVKMS_HDR_INFOFRAME_STATE_TRANSITIONING) { + nvDpyAssignSDRInfoFramePayload((NVT_HDR_INFOFRAME_PAYLOAD *) &sdp->db.db2); params.transmitControl = DRF_DEF(0073_CTRL_SPECIFIC, _SET_OD_PACKET_TRANSMIT_CONTROL, _SINGLE_FRAME, _DISABLE); } else { - nvAssert(pHeadState->hdr.outputState == NVKMS_HDR_OUTPUT_STATE_SDR); + nvAssert(pHeadState->hdrInfoFrame.state == NVKMS_HDR_INFOFRAME_STATE_DISABLED); - nvkms_memcpy(&sdp->db.db2, &NV_SDR_PAYLOAD, sizeof(NVT_HDR_INFOFRAME_PAYLOAD)); + nvDpyAssignSDRInfoFramePayload((NVT_HDR_INFOFRAME_PAYLOAD *) &sdp->db.db2); params.transmitControl = DRF_DEF(0073_CTRL_SPECIFIC, _SET_OD_PACKET_TRANSMIT_CONTROL, _SINGLE_FRAME, _ENABLE); @@ -2523,10 +2596,54 @@ static void UpdateDpInfoFrames(const NVDispEvoRec *pDispEvo, UpdateDpYUV420InfoFrame(pDispEvo, head, pAttributesSet); } +void nvCancelSDRTransitionTimer(NVDpyEvoRec *pDpyEvo) +{ + nvkms_free_timer(pDpyEvo->hdrToSdrTransitionTimer); + pDpyEvo->hdrToSdrTransitionTimer = NULL; +} + +static void SDRTransition(void *dataPtr, NvU32 dataU32) +{ + NvU32 head; + NVDpyEvoRec *pDpyEvo = dataPtr; + NVDispEvoRec *pDispEvo = pDpyEvo->pDispEvo; + NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[pDpyEvo->apiHead]; + + nvCancelSDRTransitionTimer(pDpyEvo); + + nvAssert(pApiHeadState->hwHeadsMask != 0); + + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { + NVDispHeadStateEvoRec *pHeadState = + &pDispEvo->headState[head]; + nvAssert(pHeadState->hdrInfoFrame.state == + NVKMS_HDR_INFOFRAME_STATE_TRANSITIONING); + pHeadState->hdrInfoFrame.state = NVKMS_HDR_INFOFRAME_STATE_DISABLED; + } + + nvUpdateInfoFrames(pDpyEvo); +} + +static +void ScheduleSDRTransitionTimer(NVDpyEvoRec *pDpyEvo) +{ + if (pDpyEvo->hdrToSdrTransitionTimer) { + return; + } + + pDpyEvo->hdrToSdrTransitionTimer = + nvkms_alloc_timer(SDRTransition, + pDpyEvo, + 0, + 2000000 /* 2 seconds */); +} + void nvUpdateInfoFrames(NVDpyEvoRec *pDpyEvo) { - const NVDispEvoRec *pDispEvo = pDpyEvo->pDispEvo; + NVDispEvoRec *pDispEvo = pDpyEvo->pDispEvo; const NVDispApiHeadStateEvoRec *pApiHeadState; + const NVDispHeadStateEvoRec *pHeadState; NvU32 head; if (pDpyEvo->apiHead == NV_INVALID_HEAD) { @@ -2541,6 +2658,8 @@ void nvUpdateInfoFrames(NVDpyEvoRec *pDpyEvo) nvAssert(head != NV_INVALID_HEAD); + pHeadState = &pDispEvo->headState[head]; + if (nvConnectorUsesDPLib(pDpyEvo->pConnectorEvo)) { UpdateDpInfoFrames(pDispEvo, head, &pApiHeadState->attributes); } else { @@ -2550,6 +2669,13 @@ void nvUpdateInfoFrames(NVDpyEvoRec *pDpyEvo) &pApiHeadState->infoFrame, pDpyEvo); } + + if (pHeadState->hdrInfoFrame.state == NVKMS_HDR_INFOFRAME_STATE_ENABLED) { + nvCancelSDRTransitionTimer(pDpyEvo); + } else if (pHeadState->hdrInfoFrame.state == + NVKMS_HDR_INFOFRAME_STATE_TRANSITIONING) { + ScheduleSDRTransitionTimer(pDpyEvo); + } } /*! @@ -3106,10 +3232,13 @@ NVColorFormatInfoRec nvGetColorFormatInfo(const NVDpyEvoRec *pDpyEvo) NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8; } } else { - colorFormatsInfo.rgb444.maxBpc = - NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8; + nvDpyIsHdmiDepth30Evo(pDpyEvo) ? + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_10 : + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8; + if (nvDpyIsHdmiEvo(pDpyEvo)) { + // TODO: Handle depth 30 YUV colorFormatsInfo.yuv444.maxBpc = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8; colorFormatsInfo.yuv422.maxBpc = @@ -3151,3 +3280,60 @@ NvU32 nvDpyGetPossibleApiHeadsMask(const NVDpyEvoRec *pDpyEvo) return possibleApiHeadMask; } + +NvBool nvDpyIsHDRCapable(const NVDpyEvoRec *pDpyEvo) +{ + const NVDispEvoRec *pDispEvo = pDpyEvo->pDispEvo; + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + + const NVT_EDID_INFO *pInfo = &pDpyEvo->parsedEdid.info; + const NVT_HDR_STATIC_METADATA *pHdrInfo = + &pInfo->hdr_static_metadata_info; + + // Only supported on DP 1.3+ or HDMI + if (nvDpyUsesDPLib(pDpyEvo)) { + unsigned int major; + unsigned int minor; + + if(!pDevEvo->caps.supportsDP13) { + return FALSE; + } + + if (!nvDPDpyGetDpcdRevision(pDpyEvo, &major, &minor)) { + return FALSE; + } + + if ((major < 1) || (minor < 3)) { + return FALSE; + } + } else if (!nvDpyIsHdmiEvo(pDpyEvo)) { + return FALSE; + } + + if (!pDpyEvo->parsedEdid.valid) { + return FALSE; + } + + /* + * XXX HDR is not supported with HDMI 3D due to both using VSI + * infoframes. + */ + if (pInfo->HDMI3DSupported) { + return FALSE; + } + + // Sink should support ST2084 EOTF. + if (!pHdrInfo->supported_eotf.smpte_st_2084_eotf) { + return FALSE; + } + + /* + * Sink should support static metadata type1. Nvtiming sets + * static_metadata_type to 1 if the sink supports static metadata type1. + */ + if (pHdrInfo->static_metadata_type != 1) { + return FALSE; + } + + return TRUE; +} diff --git a/src/nvidia-modeset/src/nvkms-evo.c b/src/nvidia-modeset/src/nvkms-evo.c index 536e958c38..c65b08c72e 100644 --- a/src/nvidia-modeset/src/nvkms-evo.c +++ b/src/nvidia-modeset/src/nvkms-evo.c @@ -80,31 +80,36 @@ /* * This struct is used to describe a single set of GPUs to lock together by - * GetRasterLockTopologies(). + * GetRasterLockGroups(). */ -typedef struct _NVEvoRasterLockTopology { +typedef struct _NVEvoRasterLockGroup { NvU32 numDisps; NVDispEvoPtr pDispEvoOrder[NVKMS_MAX_SUBDEVICES]; -} RasterLockTopology; +} RasterLockGroup; /* * These are used hold additional state for each DispEvo during building of - * topologies. + * RasterLockGroups. */ typedef struct { NVDispEvoPtr pDispEvo; NvU32 gpuId; - RasterLockTopology *topo; + RasterLockGroup *pRasterLockGroup; } DispEntry; typedef struct { - /* Array of DispEvos and their assigned topologies. */ + /* Array of DispEvos and their assigned RasterLockGroups. */ NvU32 numDisps; DispEntry disps[NVKMS_MAX_SUBDEVICES]; } DispEvoList; +struct _NVLockGroup { + RasterLockGroup rasterLockGroup; + NvBool flipLockEnabled; +}; + static void EvoSetViewportPointIn(NVDispEvoPtr pDispEvo, NvU32 head, NvU16 x, NvU16 y, NVEvoUpdateState *updateState); @@ -120,11 +125,12 @@ static void EvoUpdateHeadParams(const NVDispEvoRec *pDispEvo, NvU32 head, static void SetRefClk(NVDevEvoPtr pDevEvo, NvU32 sd, NvU32 head, NvBool external, NVEvoUpdateState *updateState); -static void UnlockRasterLockGroup(NVDevEvoPtr pDevEvo); static NvBool ApplyLockActionIfPossible(NVDispEvoPtr pDispEvo, NVEvoSubDevPtr pEvoSubDev, NVEvoLockAction action); -static void FinishModesetOneTopology(RasterLockTopology *topo); +static void FinishModesetOneDev(NVDevEvoRec *pDevEvo); +static void FinishModesetOneGroup(RasterLockGroup *pRasterLockGroup); +static void EnableFlipLockIfRequested(NVLockGroup *pLockGroup); static void SyncEvoLockState(void); static void UpdateEvoLockState(void); @@ -133,6 +139,11 @@ static void ScheduleLutUpdate(NVDispEvoRec *pDispEvo, const NvU32 apiHead, const NvU32 data, const NvU64 usec); +static NvBool DowngradeColorBpc( + const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, + enum NvKmsDpyAttributeColorBpcValue *pColorBpc, + enum NvKmsDpyAttributeColorRangeValue *pColorRange); + NVEvoGlobal nvEvoGlobal = { .clientHandle = 0, .frameLockList = NV_LIST_INIT(&nvEvoGlobal.frameLockList), @@ -141,10 +152,29 @@ NVEvoGlobal nvEvoGlobal = { .debugMemoryAllocationList = NV_LIST_INIT(&nvEvoGlobal.debugMemoryAllocationList), #endif /* DEBUG */ - .globalTopologies = NULL, - .numGlobalTopos = 0 }; +static RasterLockGroup *globalRasterLockGroups = NULL; +static NvU32 numGlobalRasterLockGroups = 0; + +/* + * Keep track of groups of HW heads which the modeset owner has requested to be + * fliplocked together. All of the heads specified here are guaranteed to be + * active. A given head can only be in one group at a time. Fliplock is not + * guaranteed to be enabled in the hardware for these groups. + */ +typedef struct _FlipLockRequestedGroup { + struct { + NVDispEvoPtr pDispEvo; + NvU32 flipLockHeads; + } disp[NV_MAX_SUBDEVICES]; + + NVListRec listEntry; +} FlipLockRequestedGroup; + +static NVListRec requestedFlipLockGroups = + NV_LIST_INIT(&requestedFlipLockGroups); + /* * The dummy infoString should be used in paths that take an * NVEvoInfoStringPtr where we don't need to log to a @@ -496,6 +526,28 @@ void nvDoIMPUpdateEvo(NVDispEvoPtr pDispEvo, pDevEvo->hal->PrePostIMP(pDispEvo, FALSE /* isPre */); } +void nvEvoFlipUpdate(NVDispEvoPtr pDispEvo, + NVEvoUpdateState *updateState) +{ + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + int notifier = -1; + + if (nvEvoLUTNotifiersNeedCommit(pDispEvo)) { + notifier = nvEvoCommitLUTNotifiers(pDispEvo); + } + + if (notifier >= 0) { + EvoUpdateAndKickOffWithNotifier(pDispEvo, + TRUE /* notify */, + FALSE /* sync */, + notifier, + updateState, + TRUE /* releaseElv */); + } else { + pDevEvo->hal->Update(pDevEvo, updateState, TRUE /* releaseElv */); + } +} + /*! * Tell RM not to expect anything other than a stall lock change during the next * update. @@ -778,17 +830,63 @@ static void TweakTimingsForGsync(const NVDpyEvoRec *pDpyEvo, nvEvoLogModeValidationModeTimings(pInfoString, &modeTimings); } +static NvBool HeadStateIsHdmiTmdsDeepColor(const NVDispHeadStateEvoRec *pHeadState) +{ + nvAssert(pHeadState->pConnectorEvo != NULL); + + // Check for HDMI TMDS. + if (pHeadState->pConnectorEvo->isHdmiEnabled && + (pHeadState->timings.protocol != NVKMS_PROTOCOL_SOR_HDMI_FRL)) { + // Check for pixelDepth >= 30. + switch (pHeadState->pixelDepth) { + case NVKMS_PIXEL_DEPTH_18_444: + case NVKMS_PIXEL_DEPTH_24_444: + case NVKMS_PIXEL_DEPTH_20_422: + case NVKMS_PIXEL_DEPTH_16_422: + return FALSE; + case NVKMS_PIXEL_DEPTH_30_444: + return TRUE; + } + } + return FALSE; +} /*! - * Check whether rasterlock is possible between the two sets of rastertimings. + * Check whether rasterlock is possible between the two head states. * Note that we don't compare viewports, but I don't believe the viewport size * affects whether it is possible to rasterlock. */ -static NvBool RasterLockPossible(const NVHwModeTimingsEvo *pTimings1, - const NVHwModeTimingsEvo *pTimings2) +static NvBool RasterLockPossible(const NVDispHeadStateEvoRec *pHeadState1, + const NVDispHeadStateEvoRec *pHeadState2) { + const NVHwModeTimingsEvo *pTimings1 = &pHeadState1->timings; + const NVHwModeTimingsEvo *pTimings2 = &pHeadState2->timings; + + /* + * XXX Bug 4235728: With HDMI TMDS signaling >= 10 BPC, display requires a + * higher VPLL clock multiplier varying by pixel depth, which can cause + * rasterlock to fail between heads with differing multipliers. So, if a + * head is using HDMI TMDS >= 10 BPC, it can only rasterlock with heads that + * that are using HDMI TMDS with the same pixel depth. + */ + + // If either head is HDMI TMDS DeepColor (10+ BPC)... + if (HeadStateIsHdmiTmdsDeepColor(pHeadState1) || + HeadStateIsHdmiTmdsDeepColor(pHeadState2)) { + // The other head must also be HDMI TMDS DeepColor. + if (!HeadStateIsHdmiTmdsDeepColor(pHeadState1) || + !HeadStateIsHdmiTmdsDeepColor(pHeadState2)) { + return FALSE; + } + + // Both heads must have identical pixel depth. + if (pHeadState1->pixelDepth != pHeadState2->pixelDepth) { + return FALSE; + } + } + return ((pTimings1->rasterSize.x == pTimings2->rasterSize.x) && (pTimings1->rasterSize.y == pTimings2->rasterSize.y) && (pTimings1->rasterSyncEnd.x == pTimings2->rasterSyncEnd.x) && @@ -898,84 +996,89 @@ void nvEvoSetTimings(NVDispEvoPtr pDispEvo, } /* - * growTopologies() - Increase the size of the provided raster lock topology by - * 1. + * Increase the size of the provided raster lock group by 1. * - * This involves incrementing *numTopologies, reallocating the topos array, and - * initializing the new entry. + * This involves incrementing *pNumRasterLockGroups, reallocating the + * pRasterLockGroups array, and initializing the new entry. */ -static RasterLockTopology *GrowTopologies(RasterLockTopology *topos, - unsigned int *numTopologies) +static RasterLockGroup *GrowRasterLockGroup(RasterLockGroup *pRasterLockGroups, + unsigned int *pNumRasterLockGroups) { - RasterLockTopology *newTopos, *topo; - unsigned int numTopos; + RasterLockGroup *pNewRasterLockGroups, *pRasterLockGroup; + unsigned int numRasterLockGroups; - numTopos = *numTopologies; + numRasterLockGroups = *pNumRasterLockGroups; - numTopos++; - newTopos = nvRealloc(topos, numTopos * sizeof(RasterLockTopology)); - if (!newTopos) { - nvFree(topos); - *numTopologies = 0; + numRasterLockGroups++; + pNewRasterLockGroups = + nvRealloc(pRasterLockGroups, + numRasterLockGroups * sizeof(RasterLockGroup)); + if (!pNewRasterLockGroups) { + nvFree(pRasterLockGroups); + *pNumRasterLockGroups = 0; return NULL; } - topo = &newTopos[numTopos - 1]; - topo->numDisps = 0; + pRasterLockGroup = &pNewRasterLockGroups[numRasterLockGroups - 1]; + pRasterLockGroup->numDisps = 0; - *numTopologies = numTopos; + *pNumRasterLockGroups = numRasterLockGroups; - return newTopos; - -} /* GrowTopologies() */ + return pNewRasterLockGroups; +} -static RasterLockTopology *CopyAndAppendTopology(RasterLockTopology *topos, - unsigned int *numTopos, - const RasterLockTopology *source) +static RasterLockGroup *CopyAndAppendRasterLockGroup( + RasterLockGroup *pRasterLockGroups, + unsigned int *pNumRasterLockGroups, + const RasterLockGroup *source) { - RasterLockTopology *dest; + RasterLockGroup *dest; - topos = GrowTopologies(topos, numTopos); - if (topos) { - dest = &topos[*numTopos - 1]; - nvkms_memcpy(dest, source, sizeof(RasterLockTopology)); + pRasterLockGroups = GrowRasterLockGroup(pRasterLockGroups, + pNumRasterLockGroups); + if (pRasterLockGroups) { + dest = &pRasterLockGroups[*pNumRasterLockGroups - 1]; + nvkms_memcpy(dest, source, sizeof(RasterLockGroup)); } - return topos; + return pRasterLockGroups; } -static void AddDispEvoIntoTopology(RasterLockTopology *topo, NVDispEvoPtr pDispEvo) +static void AddDispEvoIntoRasterLockGroup(RasterLockGroup *pRasterLockGroup, + NVDispEvoPtr pDispEvo) { NvU32 i; /* - * The extent of a topology is the largest number of GPUs that can be - * linked together. + * The extent of a RasterLockGroup is the largest number of GPUs that can + * be linked together. */ - nvAssert(topo->numDisps < NVKMS_MAX_SUBDEVICES); + nvAssert(pRasterLockGroup->numDisps < NVKMS_MAX_SUBDEVICES); /* Caller should keep track of not adding duplicate entries. */ - for (i = 0; i < topo->numDisps; i++) { - nvAssert(topo->pDispEvoOrder[i] != pDispEvo); + for (i = 0; i < pRasterLockGroup->numDisps; i++) { + nvAssert(pRasterLockGroup->pDispEvoOrder[i] != pDispEvo); } /* Add to the end of the array. */ - topo->pDispEvoOrder[topo->numDisps] = pDispEvo; - topo->numDisps++; + pRasterLockGroup->pDispEvoOrder[pRasterLockGroup->numDisps] = pDispEvo; + pRasterLockGroup->numDisps++; } -static const RasterLockTopology *FindTopologyForDispEvo( - const RasterLockTopology *topos, - unsigned int numTopologies, +static const RasterLockGroup *FindRasterLockGroupForDispEvo( + const RasterLockGroup *pRasterLockGroups, + unsigned int numRasterLockGroups, const NVDispEvoPtr pDispEvo) { - const RasterLockTopology *topo; + const RasterLockGroup *pRasterLockGroup; NvU32 i; - for (topo = topos; topo < topos + numTopologies; topo++) { - for (i = 0; i < topo->numDisps; i++) { - if (topo->pDispEvoOrder[i] == pDispEvo) { - return topo; + for (pRasterLockGroup = pRasterLockGroups; + pRasterLockGroup < pRasterLockGroups + numRasterLockGroups; + pRasterLockGroup++) { + for (i = 0; i < pRasterLockGroup->numDisps; i++) { + if (pRasterLockGroup->pDispEvoOrder[i] == pDispEvo) { + return pRasterLockGroup; } } } @@ -1009,7 +1112,7 @@ static void DispEvoListAppend(DispEvoList *list, NVDispEvoPtr pDispEvo) nvAssert(list->numDisps < ARRAY_LEN(list->disps)); list->disps[list->numDisps].pDispEvo = pDispEvo; list->disps[list->numDisps].gpuId = nvGpuIdOfDispEvo(pDispEvo); - list->disps[list->numDisps].topo = NULL; + list->disps[list->numDisps].pRasterLockGroup = NULL; list->numDisps++; } @@ -1036,10 +1139,11 @@ static NV0000_CTRL_GPU_VIDEO_LINKS *FindLinksForGpuId( return NULL; } -static void BuildTopologyFromVideoLinks(DispEvoList *list, - RasterLockTopology *topo, - NvU32 gpuId, - NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS *vidLinksParams) +static void BuildRasterLockGroupFromVideoLinks( + DispEvoList *list, + RasterLockGroup *pRasterLockGroup, + NvU32 gpuId, + NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS *vidLinksParams) { DispEntry *dispEntry; NV0000_CTRL_GPU_VIDEO_LINKS *links; @@ -1054,13 +1158,13 @@ static void BuildTopologyFromVideoLinks(DispEvoList *list, } /* - * Unless we've seen this gpuId already add into current topology and - * try to discover bridged GPUs. + * Unless we've seen this gpuId already add into current RasterLockGroup + * and try to discover bridged GPUs. */ - if (!dispEntry->topo) { - /* Assign in the current topology. */ - AddDispEvoIntoTopology(topo, dispEntry->pDispEvo); - dispEntry->topo = topo; + if (!dispEntry->pRasterLockGroup) { + /* Assign in the current RasterLockGroup. */ + AddDispEvoIntoRasterLockGroup(pRasterLockGroup, dispEntry->pDispEvo); + dispEntry->pRasterLockGroup = pRasterLockGroup; /* First, get the links for this gpuId. */ links = FindLinksForGpuId(vidLinksParams, gpuId); @@ -1072,10 +1176,10 @@ static void BuildTopologyFromVideoLinks(DispEvoList *list, break; } - BuildTopologyFromVideoLinks(list, - topo, - links->connectedGpuIds[i], - vidLinksParams); + BuildRasterLockGroupFromVideoLinks(list, + pRasterLockGroup, + links->connectedGpuIds[i], + vidLinksParams); } } } @@ -1083,34 +1187,35 @@ static void BuildTopologyFromVideoLinks(DispEvoList *list, /* * Stateless (RM SLI/client SLI agnostic) discovery of bridged GPUs: build - * topologies for all non-RM SLI devices based on the found GPU links. + * RasterLockGroups for all non-RM SLI devices based on the found GPU links. * - * This function and BuildTopologyFromVideoLinks() implement a simple - * algorithm that puts clusters of bridged GPUs into distinct topologies. - * Here's an outline of how we basically generate the final topologies: + * This function and BuildRasterLockGroupFromVideoLinks() implement a simple + * algorithm that puts clusters of bridged GPUs into distinct RasterLockGroups. + * Here's an outline of how we basically generate the final RasterLockGroups: * - * 1. Create a DispEvoList array to hold topology state for all the DispEvo - * objects in the system. + * 1. Create a DispEvoList array to hold RasterLockGroup state for all the + * DispEvo objects in the system. * * 2. Query RM for an array of video links for each GPU. * * 3. As long as the DispEvoList contains DispEvos of the given pDevEvo - * without a topology, find the first occurrence of such, create a new - * topology, and populate it by recursively adding the DispEvo and all - * its connected DispEvos into the new topology. + * without a group, find the first occurrence of such, create a new + * group, and populate it by recursively adding the DispEvo and all + * its connected DispEvos into the new group. * * 4. Once all known DispEvos are assigned the result will be a list of - * global RasterLockTopologies, each of which hosts DispEvos that are + * global RasterLockGroups, each of which hosts DispEvos that are * connected together. * * The result of this function should be cached once and later used to - * cheaply look up the appropriate, immutable topology for a DispEvo. + * cheaply look up the appropriate, immutable RasterLockGroup for a DispEvo. * */ -static RasterLockTopology *GetGpuTopologyStateless(unsigned int *numTopologies) +static RasterLockGroup *GetRasterLockGroupsStateless( + unsigned int *pNumRasterLockGroups) { - RasterLockTopology *topos = NULL; - RasterLockTopology *topo; + RasterLockGroup *pRasterLockGroups = NULL; + RasterLockGroup *pRasterLockGroup; DispEvoList evoList; NVDevEvoPtr pCurDev; NVDispEvoPtr pCurDisp; @@ -1152,50 +1257,51 @@ static RasterLockTopology *GetGpuTopologyStateless(unsigned int *numTopologies) for (i = 0; i < evoList.numDisps; i++) { /* - * Create a new topology starting from the first DispEvo not yet - * assigned into a topology, and all GPUs possibly reachable + * Create a new group starting from the first DispEvo not yet + * assigned into a RasterLockGroup, and all GPUs possibly reachable * from it through bridges. * - * TODO: Consider if we should only ever start a new topology - * with a GPU that has only one connection and not two. Then the - * topology's pDispEvoOrder would always start from a "leaf" GPU - * of a linkage graph. But will the GPU links always be linear - * and non-branching? NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS + * TODO: Consider if we should only ever start a new + * RasterLockGroup with a GPU that has only one connection and not + * two. Then the group's pDispEvoOrder would always start from a + * "leaf" GPU of a linkage graph. But will the GPU links always be + * linear and non-branching? NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS * makes it possible to represent GPUs with any number of links. - * Either FinishModesetOneTopology() must be able to handle that + * Either FinishModesetOneGroup() must be able to handle that * (in which case this is not a concern) or we must be able to * trust that only 0-2 links will be reported per GPU. */ - if (evoList.disps[i].topo) { + if (evoList.disps[i].pRasterLockGroup) { continue; } - topos = GrowTopologies(topos, numTopologies); - if (!topos) { + pRasterLockGroups = GrowRasterLockGroup(pRasterLockGroups, + pNumRasterLockGroups); + if (!pRasterLockGroups) { nvFree(vidLinksParams); return NULL; } - topo = &topos[*numTopologies - 1]; + pRasterLockGroup = &pRasterLockGroups[*pNumRasterLockGroups - 1]; - BuildTopologyFromVideoLinks(&evoList, - topo, - evoList.disps[i].gpuId, - vidLinksParams); + BuildRasterLockGroupFromVideoLinks(&evoList, + pRasterLockGroup, + evoList.disps[i].gpuId, + vidLinksParams); } nvFree(vidLinksParams); - nvAssert(*numTopologies > 0); - return topos; + nvAssert(*pNumRasterLockGroups > 0); + return pRasterLockGroups; } nvFree(vidLinksParams); - nvFree(topos); + nvFree(pRasterLockGroups); return NULL; } /* - * GetRasterLockTopologies() - Determine which GPUs to consider for locking (or + * GetRasterLockGroups() - Determine which GPUs to consider for locking (or * unlocking) displays. This is one of the following: * 1. SLI video bridge order, if SLI is enabled; * 2. GPUs linked through rasterlock pins, no SLI (like in clientSLI); @@ -1205,13 +1311,14 @@ static RasterLockTopology *GetGpuTopologyStateless(unsigned int *numTopologies) * Note that we still go through the same codepaths for the last degenerate * case, in order to potentially lock heads on the same GPU together. */ -static RasterLockTopology *GetRasterLockTopologies(NVDevEvoPtr pDevEvo, - unsigned int *numTopologies) +static RasterLockGroup *GetRasterLockGroups( + NVDevEvoPtr pDevEvo, + unsigned int *pNumRasterLockGroups) { unsigned int i; - RasterLockTopology *topos = NULL; + RasterLockGroup *pRasterLockGroups = NULL; - *numTopologies = 0; + *pNumRasterLockGroups = 0; if (pDevEvo->numSubDevices > 1 && pDevEvo->sli.bridge.present) { NV0080_CTRL_GPU_GET_VIDLINK_ORDER_PARAMS params = { 0 }; @@ -1231,14 +1338,15 @@ static RasterLockTopology *GetRasterLockTopologies(NVDevEvoPtr pDevEvo, } if (params.ConnectionCount > 0) { - RasterLockTopology *topo; - topos = GrowTopologies(topos, numTopologies); + RasterLockGroup *pRasterLockGroup; + pRasterLockGroups = GrowRasterLockGroup(pRasterLockGroups, + pNumRasterLockGroups); - if (!topos) { + if (!pRasterLockGroups) { return NULL; } - topo = &topos[*numTopologies - 1]; + pRasterLockGroup = &pRasterLockGroups[*pNumRasterLockGroups - 1]; /* * For some reason this interface returns a mask instead of an @@ -1258,47 +1366,51 @@ static RasterLockTopology *GetRasterLockTopologies(NVDevEvoPtr pDevEvo, nvAssert(pDevEvo->pDispEvo[sd] != NULL); /* SLI Mosaic. */ - AddDispEvoIntoTopology(topo, pDevEvo->pDispEvo[sd]); + AddDispEvoIntoRasterLockGroup(pRasterLockGroup, + pDevEvo->pDispEvo[sd]); } } - if (*numTopologies > 0) { - return topos; + if (*pNumRasterLockGroups > 0) { + return pRasterLockGroups; } } /* - * Client SLI: Create a RasterLockTopology from pDevEvo's only DispEvo + * Client SLI: Create a RasterLockGroup from pDevEvo's only DispEvo * and other DispEvos potentially bridged to that. */ if (pDevEvo->numSubDevices == 1) { - /* Get-or-create cached rasterlock topology for this device. */ - if (!nvEvoGlobal.globalTopologies) { - nvEvoGlobal.globalTopologies = - GetGpuTopologyStateless(&nvEvoGlobal.numGlobalTopos); - } - - /* Look for a cached topo containing this device's DispEvo. */ - if (nvEvoGlobal.globalTopologies && nvEvoGlobal.numGlobalTopos > 0) { - const RasterLockTopology *foundTopo = - FindTopologyForDispEvo(nvEvoGlobal.globalTopologies, - nvEvoGlobal.numGlobalTopos, - pDevEvo->pDispEvo[0]); - - /* Make a copy of it and add to 'topos'. */ - if (foundTopo) { - topos = CopyAndAppendTopology(topos, numTopologies, foundTopo); + /* Get-or-create cached RasterLockGroup for this device. */ + if (!globalRasterLockGroups) { + globalRasterLockGroups = + GetRasterLockGroupsStateless(&numGlobalRasterLockGroups); + } + + /* Look for a cached group containing this device's DispEvo. */ + if (globalRasterLockGroups && numGlobalRasterLockGroups > 0) { + const RasterLockGroup *pRasterLockGroup = + FindRasterLockGroupForDispEvo(globalRasterLockGroups, + numGlobalRasterLockGroups, + pDevEvo->pDispEvo[0]); + + /* Make a copy of it and add to 'pRasterLockGroups'. */ + if (pRasterLockGroup) { + pRasterLockGroups = + CopyAndAppendRasterLockGroup(pRasterLockGroups, + pNumRasterLockGroups, + pRasterLockGroup); } } - if (*numTopologies > 0) { - return topos; + if (*pNumRasterLockGroups > 0) { + return pRasterLockGroups; } } /* - * Single GPU or bridgeless SLI. We create a topology for each + * Single GPU or bridgeless SLI. We create a group for each * individual DispEvo. */ @@ -1306,21 +1418,21 @@ static RasterLockTopology *GetRasterLockTopologies(NVDevEvoPtr pDevEvo, unsigned int sd; FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - RasterLockTopology *topo; - topos = GrowTopologies(topos, numTopologies); + RasterLockGroup *pRasterLockGroup; + pRasterLockGroups = GrowRasterLockGroup(pRasterLockGroups, + pNumRasterLockGroups); - if (!topos) { + if (!pRasterLockGroups) { return NULL; } - topo = &topos[*numTopologies - 1]; + pRasterLockGroup = &pRasterLockGroups[*pNumRasterLockGroups - 1]; - AddDispEvoIntoTopology(topo, pDispEvo); + AddDispEvoIntoRasterLockGroup(pRasterLockGroup, pDispEvo); } - return topos; - -} // GetRasterLockTopologies() + return pRasterLockGroups; +} /* * ApplyLockActionIfPossible() - Check if the given action is a valid @@ -1331,134 +1443,231 @@ static NvBool ApplyLockActionIfPossible(NVDispEvoPtr pDispEvo, NVEvoSubDevPtr pEvoSubDev, NVEvoLockAction action) { - NvBool changed = FALSE; - NvU32 head; - if (!pEvoSubDev) { return FALSE; } - for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { - if (!nvHeadIsActive(pDispEvo, head)) { - continue; + if (pEvoSubDev->scanLockState(pDispEvo, pEvoSubDev, + action, NULL)) { + unsigned int i = 0; + NvU32 pHeads[NVKMS_MAX_HEADS_PER_DISP + 1] = { NV_INVALID_HEAD, }; + NvU32 head; + + for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { + if (nvHeadIsActive(pDispEvo, head)) { + pHeads[i++] = head; + } } + nvAssert(i <= NVKMS_MAX_HEADS_PER_DISP); + pHeads[i] = NV_INVALID_HEAD; - if (pEvoSubDev->scanLockState(pDispEvo, pEvoSubDev, - action, NULL)) { - NvU32 otherHead; - unsigned int i = 0; - NvU32 pHeads[NVKMS_MAX_HEADS_PER_DISP + 1]; + pEvoSubDev->scanLockState(pDispEvo, pEvoSubDev, action, pHeads); - pHeads[i++] = head; - for (otherHead = 0; otherHead < NVKMS_MAX_HEADS_PER_DISP; - otherHead++) { - if (!nvHeadIsActive(pDispEvo, otherHead)) { - continue; - } - if (otherHead == head) { - continue; - } + return TRUE; + } - pHeads[i++] = otherHead; - } - nvAssert(i <= NVKMS_MAX_HEADS_PER_DISP); - pHeads[i] = NV_INVALID_HEAD; + return FALSE; + +} // ApplyLockActionIfPossible() + +/* + * Disable any intra-GPU lock state set up in FinishModesetOneDisp(). + * This assumes that any cross-GPU locking which may have been set up on this + * GPU was already torn down. + */ +static void UnlockRasterLockOneDisp(NVDispEvoPtr pDispEvo) +{ + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + NvU32 sd = pDispEvo->displayOwner; + NVEvoSubDevPtr pEvoSubDev = &pDevEvo->gpus[sd]; + NvBool changed = FALSE; + + /* Initialize the assembly state */ + SyncEvoLockState(); + + /* We want to evaluate all of these, so don't use || */ + changed |= ApplyLockActionIfPossible(pDispEvo, pEvoSubDev, + NV_EVO_PROHIBIT_LOCK_DISABLE); + changed |= ApplyLockActionIfPossible(pDispEvo, pEvoSubDev, + NV_EVO_UNLOCK_HEADS); + + /* Update the hardware if anything has changed */ + if (changed) { + UpdateEvoLockState(); + } + + pDispEvo->rasterLockPossible = FALSE; +} + +/* + * Call UnlockRasterLockOneDisp() for each disp on this device to tear down + * intra-GPU locking on each. + */ +static void UnlockRasterLockOneDev(NVDevEvoPtr pDevEvo) +{ + NVDispEvoPtr pDispEvo; + NvU32 sd; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + UnlockRasterLockOneDisp(pDispEvo); + } +} + +static void DisableLockGroupFlipLock(NVLockGroup *pLockGroup) +{ + + const RasterLockGroup *pRasterLockGroup = &pLockGroup->rasterLockGroup; + NvU32 i; + + if (!pLockGroup->flipLockEnabled) { + return; + } + + for (i = 0; i < pRasterLockGroup->numDisps; i++) { + NVEvoUpdateState updateState = { }; + NVDispEvoPtr pDispEvo = pRasterLockGroup->pDispEvoOrder[i]; + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + NvU32 sd = pDispEvo->displayOwner; + NVEvoSubDevPtr pEvoSubDev = &pDevEvo->gpus[sd]; + NvU32 head; + NvBool changed = FALSE; - pEvoSubDev->scanLockState(pDispEvo, pEvoSubDev, action, pHeads); + for (head = 0; head < pDevEvo->numHeads; head++) { + NvBool headChanged = FALSE; + if (!nvHeadIsActive(pDispEvo, head)) { + continue; + } /* * scanLockState transitions (such as nvEvoLockHWStateLockHeads) * will update headControlAssy values for all heads, so we should * update flipLock and flipLockPin for all heads as well. */ - for (i = 0; pHeads[i] != NV_INVALID_HEAD; i++) { - NVEvoHeadControlPtr pHC = &pEvoSubDev->headControlAssy[pHeads[i]]; - /* - * Reset the fliplock pin, if it's not in use for framelock, - * and unregister our use of the fliplock pin - */ - if (!HEAD_MASK_QUERY(pEvoSubDev->flipLockPinSetForFrameLockHeadMask, - pHeads[i])) { + NVEvoHeadControlPtr pHC = &pEvoSubDev->headControlAssy[head]; + /* + * Reset the fliplock pin, if it's not in use for framelock, + * and unregister our use of the fliplock pin + */ + if (!HEAD_MASK_QUERY(pEvoSubDev->flipLockPinSetForFrameLockHeadMask, + head)) { + if (pHC->flipLockPin != NV_EVO_LOCK_PIN_INTERNAL(0)) { pHC->flipLockPin = NV_EVO_LOCK_PIN_INTERNAL(0); + headChanged = TRUE; } - pEvoSubDev->flipLockPinSetForSliHeadMask = - HEAD_MASK_UNSET(pEvoSubDev->flipLockPinSetForSliHeadMask, - pHeads[i]); + } + pEvoSubDev->flipLockPinSetForSliHeadMask = + HEAD_MASK_UNSET(pEvoSubDev->flipLockPinSetForSliHeadMask, + head); - /* - * Disable fliplock, if it's not in use for framelock, and - * unregister our need for fliplock to be enabled - */ - if (!HEAD_MASK_QUERY(pEvoSubDev->flipLockEnabledForFrameLockHeadMask, - pHeads[i])) { + /* + * Disable fliplock, if it's not in use for framelock, and + * unregister our need for fliplock to be enabled + */ + if (!HEAD_MASK_QUERY(pEvoSubDev->flipLockEnabledForFrameLockHeadMask, + head)) { + if (pHC->flipLock) { pHC->flipLock = FALSE; + headChanged = TRUE; } - pEvoSubDev->flipLockEnabledForSliHeadMask = - HEAD_MASK_UNSET(pEvoSubDev->flipLockEnabledForSliHeadMask, - pHeads[i]); } - - changed = TRUE; + pEvoSubDev->flipLockEnabledForSliHeadMask = + HEAD_MASK_UNSET(pEvoSubDev->flipLockEnabledForSliHeadMask, + head); + if (headChanged) { + EvoUpdateHeadParams(pDispEvo, head, &updateState); + } + } + if (changed) { + nvEvoUpdateAndKickOff(pDispEvo, TRUE, &updateState, + TRUE /* releaseElv */); } } - return changed; - -} // ApplyLockActionIfPossible() - + pLockGroup->flipLockEnabled = FALSE; +} /* - * UnlockRasterLockGroup() - Unlock all GPUs in the rasterlock group associated - * with the given device. + * Unlock cross-GPU locking in the given lock group. */ +static void UnlockLockGroup(NVLockGroup *pLockGroup) +{ + RasterLockGroup *pRasterLockGroup; + int i; -static void UnlockRasterLockGroup(NVDevEvoPtr pDevEvo) { - RasterLockTopology *topos, *topo; - unsigned int numTopos; - NvBool changed = FALSE; - - topos = GetRasterLockTopologies(pDevEvo, &numTopos); - if (!topos) { + if (pLockGroup == NULL) { return; } - for (topo = topos; topo < topos + numTopos; topo++) { - int i; - - for (i = (int)topo->numDisps - 1; i >= 0; i--) { - NVDispEvoPtr pDispEvo = topo->pDispEvoOrder[i]; - NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; - NvU32 sd = pDispEvo->displayOwner; - NVEvoSubDevPtr pEvoSubDev = &pDevEvo->gpus[sd]; + pRasterLockGroup = &pLockGroup->rasterLockGroup; - /* Initialize the assembly state */ - SyncEvoLockState(); + DisableLockGroupFlipLock(pLockGroup); - /* We want to evaluate all of these, so don't use || */ - changed |= ApplyLockActionIfPossible(pDispEvo, pEvoSubDev, - NV_EVO_DISABLE_VRR); - changed |= ApplyLockActionIfPossible(pDispEvo, pEvoSubDev, - NV_EVO_REM_SLI); - changed |= ApplyLockActionIfPossible(pDispEvo, pEvoSubDev, - NV_EVO_UNLOCK_HEADS); + for (i = (int)pRasterLockGroup->numDisps - 1; i >= 0; i--) { + NVDispEvoPtr pDispEvo = pRasterLockGroup->pDispEvoOrder[i]; + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + NvU32 sd = pDispEvo->displayOwner; + NVEvoSubDevPtr pEvoSubDev = &pDevEvo->gpus[sd]; - /* Finally, update the hardware if anything has changed */ - if (changed) { - UpdateEvoLockState(); - changed = FALSE; - } + /* Initialize the assembly state */ + SyncEvoLockState(); - pEvoSubDev->flipLockProhibitedHeadMask = 0x0; + if (ApplyLockActionIfPossible(pDispEvo, pEvoSubDev, + NV_EVO_REM_SLI)) { + /* Update the hardware if anything has changed */ + UpdateEvoLockState(); } + + pEvoSubDev->flipLockProhibitedHeadMask = 0x0; + + nvAssert(pDispEvo->pLockGroup == pLockGroup); + pDispEvo->pLockGroup = NULL; + } + + /* + * Disable any SLI video bridge features we may have enabled for locking. + * This is a separate loop from the above in order to handle both cases: + * + * a) Multiple pDispEvos on the same pDevEvo (linked RM-SLI): all disps in + * the lock group will share the same pDevEvo. In that case we should + * not call RM to disable the video bridge power across the entire + * device until we've disabled locking on all GPUs). This loop will + * call nvEvoUpdateSliVideoBridge() redundantly for the same pDevEvo, + * but those calls will be filtered out. (If we did this in the loop + * above, RM would broadcast the video bridge disable call to all pDisps + * on the first call, even before we've disabled locking on them.) + * + * b) Each pDispEvo on a separate pDevEvo (client-side SLI or no SLI, when + * a video bridge is present): in that case each pDispEvo has a separate + * pDevEvo, and we need to call nvEvoUpdateSliVideoBridge() on each. + * (It would be okay in this case to call nvEvoUpdateSliVideoBridge() in + * the loop above since it will only disable the video bridge power for + * one GPU at a time.) + */ + for (i = (int)pRasterLockGroup->numDisps - 1; i >= 0; i--) { + NVDispEvoPtr pDispEvo = pRasterLockGroup->pDispEvoOrder[i]; + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + + pDevEvo->sli.bridge.powerNeededForRasterLock = FALSE; + nvEvoUpdateSliVideoBridge(pDevEvo); } - /* Disable any SLI video bridge features we may have enabled for locking. */ - pDevEvo->sli.bridge.powerNeededForRasterLock = FALSE; - nvEvoUpdateSliVideoBridge(pDevEvo); + nvFree(pLockGroup); +} - nvFree(topos); +/* + * Unlock all any cross-GPU locking in the rasterlock group(s) associated with + * the given device. + */ +static void UnlockLockGroupsForDevice(NVDevEvoPtr pDevEvo) +{ + NVDispEvoPtr pDispEvo; + NvU32 sd; -} // UnlockRasterLockGroup() + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + UnlockLockGroup(pDispEvo->pLockGroup); + nvAssert(pDispEvo->pLockGroup == NULL); + } +} void nvAssertAllDpysAreInactive(NVDevEvoPtr pDevEvo) { @@ -1476,55 +1685,37 @@ void nvAssertAllDpysAreInactive(NVDevEvoPtr pDevEvo) /*! * Disable locking-related state. */ -static void DisableLockState(NVDevEvoPtr pDevEvo, - NvU32 *dispNeedsUpdate, - NVEvoUpdateState *updateState) +static void DisableLockState(NVDevEvoPtr pDevEvo) { NvU32 dispIndex; NVDispEvoPtr pDispEvo; - *dispNeedsUpdate = 0; - - /* Disable flip lock. */ + /* Disable flip lock as requested by swap groups/framelock. */ FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { - NvU32 head; - for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { - if (!nvHeadIsActive(pDispEvo, head)) { - continue; - } - NvU32 flipLockEnable = 0; - NvBool needsUpdate; - - if (!nvUpdateFlipLockEvoOneHead(pDispEvo, head, - &flipLockEnable, TRUE /* set */, - &needsUpdate, - updateState)) { - nvEvoLogDisp(pDispEvo, EVO_LOG_ERROR, - "Unable to update fliplock"); - } - - if (needsUpdate) { - *dispNeedsUpdate |= (1 << dispIndex); - } - } + nvToggleFlipLockPerDisp(pDispEvo, + nvGetActiveHeadMask(pDispEvo), + FALSE /* enable */); } - /* Disable raster lock. */ + /* Disable any locking across GPUs. */ + + UnlockLockGroupsForDevice(pDevEvo); - UnlockRasterLockGroup(pDevEvo); + /* Disable intra-GPU rasterlock on this pDevEvo. */ + UnlockRasterLockOneDev(pDevEvo); /* Reset the EVO locking state machine. */ FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + nvEvoStateAssertNoLock(&pDevEvo->gpus[pDispEvo->displayOwner]); nvEvoStateStartNoLock(&pDevEvo->gpus[pDispEvo->displayOwner]); } } -void nvEvoLockStatePreModeset(NVDevEvoPtr pDevEvo, NvU32 *dispNeedsEarlyUpdate, - NVEvoUpdateState *updateState) +void nvEvoLockStatePreModeset(NVDevEvoPtr pDevEvo) { - DisableLockState(pDevEvo, dispNeedsEarlyUpdate, updateState); + DisableLockState(pDevEvo); } /*! @@ -1532,52 +1723,27 @@ void nvEvoLockStatePreModeset(NVDevEvoPtr pDevEvo, NvU32 *dispNeedsEarlyUpdate, */ void nvEvoLockStatePostModeset(NVDevEvoPtr pDevEvo, const NvBool doRasterLock) { - RasterLockTopology *topos, *topo; - unsigned int numTopos; - - /* - * Always unlock everything on this rasterlock group to begin with a clean - * slate. We'll relock below, if possible. - */ - - UnlockRasterLockGroup(pDevEvo); + RasterLockGroup *pRasterLockGroups, *pRasterLockGroup; + unsigned int numRasterLockGroups; if (!doRasterLock) { return; } - topos = GetRasterLockTopologies(pDevEvo, &numTopos); - if (!topos) { - return; - } + FinishModesetOneDev(pDevEvo); - for (topo = topos; topo < topos + numTopos; topo++) { - FinishModesetOneTopology(topo); + pRasterLockGroups = GetRasterLockGroups(pDevEvo, &numRasterLockGroups); + if (!pRasterLockGroups) { + return; } - nvFree(topos); - -} - -static NvBool EnableVrr(NVDispEvoPtr pDispEvo, - NVEvoSubDevPtr pEvoSubDev, - const NvU32 *pHeads) -{ - NvBool ret; - - SyncEvoLockState(); - - ret = pEvoSubDev->scanLockState(pDispEvo, pEvoSubDev, NV_EVO_ENABLE_VRR, - pHeads); - if (!ret) { - nvEvoLogDispDebug(pDispEvo, EVO_LOG_ERROR, - "Failed to enable VRR frame lock"); - return FALSE; + for (pRasterLockGroup = pRasterLockGroups; + pRasterLockGroup < pRasterLockGroups + numRasterLockGroups; + pRasterLockGroup++) { + FinishModesetOneGroup(pRasterLockGroup); } - UpdateEvoLockState(); - - return TRUE; + nvFree(pRasterLockGroups); } /*! @@ -1614,134 +1780,283 @@ void nvEvoUpdateSliVideoBridge(NVDevEvoPtr pDevEvo) pDevEvo->sli.bridge.powered = enable; } -void nvEvoLockStateSetMergeMode(NVDispEvoPtr pDispEvo) +/* + * Check if VRR or MergeMode are enabled; if so, go into the special "prohibit + * lock" mode which prevents other scanlock states from being reached. + * + * Return TRUE iff VRR or MergeMode is in use on this GPU. + */ +static NvBool ProhibitLockIfNecessary(NVDispEvoRec *pDispEvo) { NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; NVEvoSubDevPtr pEvoSubDev = &pDevEvo->gpus[pDispEvo->displayOwner]; - NvU32 activeHeads[NVKMS_MAX_HEADS_PER_DISP + 1]; - NvU32 mergeModeHeads[NVKMS_MAX_HEADS_PER_DISP + 1]; - NvU32 numMergeModeHeads = 0; + NvU32 activeHeads[NVKMS_MAX_HEADS_PER_DISP + 1] = { NV_INVALID_HEAD, }; + NvBool prohibitLock = FALSE; NvU32 numActiveHeads = 0; - NvBool needUpdate = FALSE; + NvU32 head; - for (NvU32 head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { + for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { if (nvHeadIsActive(pDispEvo, head)) { + activeHeads[numActiveHeads++] = head; + if ((pDispEvo->headState[head].timings.vrr.type != + NVKMS_DPY_VRR_TYPE_NONE)) { + prohibitLock = TRUE; + } + if (pDispEvo->headState[head].mergeMode != NV_EVO_MERGE_MODE_DISABLED) { - mergeModeHeads[numMergeModeHeads++] = head; + prohibitLock = TRUE; } - activeHeads[numActiveHeads++] = head; } } - mergeModeHeads[numMergeModeHeads] = NV_INVALID_HEAD; - activeHeads[numActiveHeads] = NV_INVALID_HEAD; - SyncEvoLockState(); - if (pEvoSubDev->scanLockState(pDispEvo, pEvoSubDev, - NV_EVO_DISABLE_MERGE_MODE, NULL)) { - pEvoSubDev->scanLockState(pDispEvo, pEvoSubDev, - NV_EVO_DISABLE_MERGE_MODE, activeHeads); - needUpdate = TRUE; - } - - if (numMergeModeHeads > 0) { - nvAssert(pDevEvo->hal->caps.supportsMergeMode); - if (pEvoSubDev->scanLockState(pDispEvo, - pEvoSubDev, - NV_EVO_ENABLE_MERGE_MODE, - mergeModeHeads)) { - needUpdate = TRUE; - } else { + if (prohibitLock) { + activeHeads[numActiveHeads] = NV_INVALID_HEAD; + + SyncEvoLockState(); + + if (!pEvoSubDev->scanLockState(pDispEvo, pEvoSubDev, + NV_EVO_PROHIBIT_LOCK, + activeHeads)) { nvEvoLogDispDebug(pDispEvo, EVO_LOG_ERROR, - "Failed to enable lock state merge mode"); + "Failed to prohibit lock"); + return FALSE; } - } - if (needUpdate) { UpdateEvoLockState(); + + return TRUE; } + return FALSE; } + /* - * FinishModesetOneTopology() - Set up raster lock between GPUs, if applicable, - * for one RasterLockTopology. Called in a loop from nvFinishModesetEvo(). + * Set up rasterlock between heads on a single GPU, if certain conditions are met: + * - Locking is not prohibited due to the active configuration + * - All active heads have identical mode timings + * + * Set pDispEvo->pRasterLockPossible to indicate whether rasterlock is possible + * on this GPU, which will be used to determine if rasterlock is possible + * between this GPU and other GPUs. + * Note that this isn't the same as whether heads were locked: if fewer than + * two heads were active, heads will not be locked but rasterlock with other + * GPUs may still be possible. */ - -static void FinishModesetOneTopology(RasterLockTopology *topo) +static void FinishModesetOneDisp( + NVDispEvoRec *pDispEvo) { - NVDispEvoPtr *pDispEvoOrder = topo->pDispEvoOrder; - NvU32 numUsedGpus = 0; - const NVHwModeTimingsEvo *pPrevTimings = NULL; - NvBool headInUse[NVKMS_MAX_SUBDEVICES][NVKMS_MAX_HEADS_PER_DISP]; - NvBool lockPossible = TRUE, foundUnused = FALSE; - NvBool vrrInUse = FALSE; - NvBool flipLockPossible = TRUE; - unsigned int i, j; - NvU8 allowFlipLockGroup = 0; - NVDevEvoPtr pDevEvoFlipLockGroup = NULL; - NvBool mergeModeInUse = FALSE; + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + NVEvoSubDevPtr pEvoSubDev; + const NVDispHeadStateEvoRec *pPrevHeadState = NULL; + NvU32 head, usedHeads = 0; + NvU32 headsToLock[NVKMS_MAX_HEADS_PER_DISP + 1] = { NV_INVALID_HEAD, }; - /* - * First, look for devices with VRR enabled. If we find any, go into the - * special VRR framelock mode. - * - * If we find devices with VRR or merge mode enabled, don't try to - * rasterlock any other heads. - */ - for (i = 0; i < topo->numDisps; i++) { - NVDispEvoPtr pDispEvo = pDispEvoOrder[i]; - NvU32 sd = pDispEvo->displayOwner; - NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; - NvU32 vrrHeads[NVKMS_MAX_HEADS_PER_DISP + 1]; - unsigned int numVrrHeads = 0; - NvU32 head; + if (pDevEvo->gpus == NULL) { + return; + } - if (!pDevEvo->gpus) { - continue; - } + pEvoSubDev = &pDevEvo->gpus[pDispEvo->displayOwner]; - for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { - if (nvHeadIsActive(pDispEvo, head)) { - if (pDispEvo->headState[head].mergeMode != - NV_EVO_MERGE_MODE_DISABLED) { - mergeModeInUse = TRUE; - } - } - } + pDispEvo->rasterLockPossible = FALSE; + + if (ProhibitLockIfNecessary(pDispEvo)) { + /* If locking is prohibited, do not attempt to lock heads. */ + return; + } - if (!pDevEvo->vrr.enabled) { + /* + * Determine if rasterlock is possible: check each active display for + * rasterlock compatibility with the previous one we looked at. If any of + * them aren't compatible, rasterlock is not possible. + */ + pDispEvo->rasterLockPossible = TRUE; + for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { + const NVDispHeadStateEvoRec *pHeadState = + &pDispEvo->headState[head]; + + if (!nvHeadIsActive(pDispEvo, head)) { continue; } - for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { - if (nvHeadIsActive(pDispEvo, head) && - (pDispEvo->headState[head].timings.vrr.type != - NVKMS_DPY_VRR_TYPE_NONE)) { - vrrHeads[numVrrHeads++] = head; + if (pPrevHeadState && + !RasterLockPossible(pHeadState, pPrevHeadState)) { + pDispEvo->rasterLockPossible = FALSE; + break; + } + + pPrevHeadState = pHeadState; + + headsToLock[usedHeads] = head; + usedHeads++; + } + + if (!pDispEvo->rasterLockPossible) { + return; + } + + if (usedHeads > 1) { + /* Terminate array */ + headsToLock[usedHeads] = NV_INVALID_HEAD; + + /* Initialize the assembly state */ + SyncEvoLockState(); + + /* Set up rasterlock between heads on this disp. */ + nvAssert(headsToLock[0] != NV_INVALID_HEAD); + if (!pEvoSubDev->scanLockState(pDispEvo, pEvoSubDev, + NV_EVO_LOCK_HEADS, + headsToLock)) { + nvEvoLogDispDebug(pDispEvo, EVO_LOG_ERROR, + "Unable to lock heads"); + pDispEvo->rasterLockPossible = FALSE; + } + + /* Update the hardware with the new state */ + UpdateEvoLockState(); + } +} + +/* Call FinishModesetOneDisp() for each disp on this device to set up intra-GPU + * locking on each. */ +static void FinishModesetOneDev( + NVDevEvoRec *pDevEvo) +{ + NVDispEvoPtr pDispEvo; + NvU32 sd; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + FinishModesetOneDisp(pDispEvo); + } +} + +/* + * Enable fliplock for the specified pLockGroup. + * This assumes that rasterlock was already enabled. + */ +static void EnableLockGroupFlipLock(NVLockGroup *pLockGroup) +{ + const RasterLockGroup *pRasterLockGroup = &pLockGroup->rasterLockGroup; + NvU32 i; + + if (pRasterLockGroup->numDisps < 2) { + /* TODO: enable fliplock for single GPUs */ + return; + } + + pLockGroup->flipLockEnabled = TRUE; + + for (i = 0; i < pRasterLockGroup->numDisps; i++) { + NVEvoUpdateState updateState = { }; + NVDispEvoPtr pDispEvo = pRasterLockGroup->pDispEvoOrder[i]; + NvU32 sd = pDispEvo->displayOwner; + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + NvU32 head; + + for (head = 0; head < pDevEvo->numHeads; head++) { + NvU64 startTime = 0; + + if (!nvHeadIsActive(pDispEvo, head)) { + continue; } + + NVEvoLockPin pin = + nvEvoGetPinForSignal(pDispEvo, &pDevEvo->gpus[sd], + NV_EVO_LOCK_SIGNAL_FLIP_LOCK); + + /* Wait for the raster lock to sync in.. */ + if (pin == NV_EVO_LOCK_PIN_ERROR || + !EvoWaitForLock(pDevEvo, sd, head, EVO_RASTER_LOCK, + &startTime)) { + nvEvoLogDisp(pDispEvo, EVO_LOG_ERROR, + "Timed out waiting for rasterlock; not enabling fliplock."); + goto fail; + } + + /* + * Enable fliplock, and register that we've enabled + * fliplock for SLI to ensure it doesn't get disabled + * later. + */ + pDevEvo->gpus[sd].headControl[head].flipLockPin = pin; + pDevEvo->gpus[sd].flipLockPinSetForSliHeadMask = + HEAD_MASK_SET(pDevEvo->gpus[sd].flipLockPinSetForSliHeadMask, head); + + pDevEvo->gpus[sd].headControl[head].flipLock = TRUE; + pDevEvo->gpus[sd].flipLockEnabledForSliHeadMask = + HEAD_MASK_SET(pDevEvo->gpus[sd].flipLockEnabledForSliHeadMask, head); + + EvoUpdateHeadParams(pDispEvo, head, &updateState); } - if (numVrrHeads > 0) { - vrrHeads[numVrrHeads] = NV_INVALID_HEAD; - if (EnableVrr(pDispEvo, &pDevEvo->gpus[sd], vrrHeads)) { - vrrInUse = TRUE; + /* + * This must be synchronous as EVO reports lock success if + * locking isn't enabled, so we could race through the + * WaitForLock check below otherwise. + */ + nvEvoUpdateAndKickOff(pDispEvo, TRUE, &updateState, + TRUE /* releaseElv */); + + /* + * Wait for flip lock sync. I'm not sure this is really + * necessary, but the docs say to do this before attempting any + * flips in the base channel. + */ + for (head = 0; head < pDevEvo->numHeads; head++) { + NvU64 startTime = 0; + + if (!nvHeadIsActive(pDispEvo, head)) { + continue; + } + + if (!EvoWaitForLock(pDevEvo, sd, head, EVO_FLIP_LOCK, + &startTime)) { + nvEvoLogDisp(pDispEvo, EVO_LOG_ERROR, + "Timed out waiting for fliplock."); + goto fail; } } } - if (vrrInUse || mergeModeInUse) { - return; + return; +fail: + DisableLockGroupFlipLock(pLockGroup); +} + +/* + * FinishModesetOneGroup() - Set up raster lock between GPUs, if applicable, + * for one RasterLockGroup. Called in a loop from nvFinishModesetEvo(). + */ + +static void FinishModesetOneGroup(RasterLockGroup *pRasterLockGroup) +{ + NVDispEvoPtr *pDispEvoOrder = pRasterLockGroup->pDispEvoOrder; + NvU32 numUsedGpus = 0; + const NVDispHeadStateEvoRec *pPrevHeadState = NULL; + NvBool headInUse[NVKMS_MAX_SUBDEVICES][NVKMS_MAX_HEADS_PER_DISP]; + NvBool rasterLockPossible = TRUE, foundUnused = FALSE; + unsigned int i, j; + NVLockGroup *pLockGroup = NULL; + + /* Don't attempt locking across GPUs if, on any individual GPU, rasterlock + * isn't possible. */ + for (i = 0; i < pRasterLockGroup->numDisps; i++) { + NVDispEvoPtr pDispEvo = pDispEvoOrder[i]; + + if (!pDispEvo->rasterLockPossible) { + return; + } } nvkms_memset(headInUse, 0, sizeof(headInUse)); /* - * Next, figure out if we can perform locking and which GPUs/heads we can - * use. For now, only attempt locking if all heads on the device have - * compatible timings and consecutive in the video bridge order. + * Next, figure out if we can perform cross-GPU locking and which + * GPUs/heads we can use. Only attempt locking if all heads across GPUs + * have compatible timings and are consecutive in the video bridge order. */ - for (i = 0; i < topo->numDisps; i++) { + for (i = 0; i < pRasterLockGroup->numDisps; i++) { NVDispEvoPtr pDispEvo = pDispEvoOrder[i]; NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; NvU32 head; @@ -1758,7 +2073,7 @@ static void FinishModesetOneTopology(RasterLockTopology *topo) continue; } else { if (foundUnused) { - lockPossible = FALSE; + rasterLockPossible = FALSE; break; } @@ -1772,69 +2087,66 @@ static void FinishModesetOneTopology(RasterLockTopology *topo) for (head = 0; head < NVKMS_MAX_HEADS_PER_DISP; head++) { const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; - const NVHwModeTimingsEvo *pTimings = &pHeadState->timings; if (!nvHeadIsActive(pDispEvo, head)) { continue; } - /* - * Only flip lock if all of the heads are in the same - * allowFlipLockGroup. - * - * Also, for now, only allow fliplocking if all heads are on - * GPUs with the same pDevEvo (i.e., single GPU or RM-linked - * SLI). - */ - if (allowFlipLockGroup == 0) { - allowFlipLockGroup = pHeadState->allowFlipLockGroup; - pDevEvoFlipLockGroup = pDevEvo; - } else if (allowFlipLockGroup != pHeadState->allowFlipLockGroup || - pDevEvoFlipLockGroup != pDevEvo) { - flipLockPossible = FALSE; - } - - if (pPrevTimings && - !RasterLockPossible(pTimings, pPrevTimings)) { - lockPossible = FALSE; + if (pPrevHeadState && + !RasterLockPossible(pHeadState, pPrevHeadState)) { + rasterLockPossible = FALSE; goto exitHeadLoop; } headInUse[i][head] = TRUE; - pPrevTimings = pTimings; + pPrevHeadState = pHeadState; } exitHeadLoop: - if (!lockPossible) { + if (!rasterLockPossible) { break; } } - if (!lockPossible) { + if (!rasterLockPossible || numUsedGpus == 0) { + return; + } + + /* Create a new lock group to store the current configuration */ + pLockGroup = nvCalloc(1, sizeof(*pLockGroup)); + + if (pLockGroup == NULL) { return; } + pLockGroup->rasterLockGroup = *pRasterLockGroup; + /* * Finally, actually set up locking: go through the video bridge order * setting it up. */ - for (i = 0; i < topo->numDisps; i++) { + for (i = 0; i < pRasterLockGroup->numDisps; i++) { NVDispEvoPtr pDispEvo = pDispEvoOrder[i]; NvU32 sd = pDispEvo->displayOwner; NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; - NvU32 head[NVKMS_MAX_HEADS_PER_DISP + 1]; + NvU32 head[NVKMS_MAX_HEADS_PER_DISP + 1] = { NV_INVALID_HEAD, }; unsigned int usedHeads = 0; - NvBool headsLocked = FALSE, gpusLocked = FALSE; + NvBool gpusLocked = FALSE; - /* Initialize the assembly state */ - SyncEvoLockState(); + /* Remember that we've enabled this lock group on this GPU. */ + nvAssert(pDispEvo->pLockGroup == NULL); + pDispEvo->pLockGroup = pLockGroup; - /* If we're past the end of the chain, we're done. */ - if (i == numUsedGpus) { - break; + /* If we're past the end of the chain, stop applying locking below, but + * continue this loop to assign pDispEvo->pLockGroup above. */ + if (i >= numUsedGpus) { + continue; } + /* Initialize the assembly state */ + SyncEvoLockState(); + for (j = 0; j < NVKMS_MAX_HEADS_PER_DISP; j++) { if (headInUse[i][j]) { @@ -1845,22 +2157,6 @@ static void FinishModesetOneTopology(RasterLockTopology *topo) } head[usedHeads] = NV_INVALID_HEAD; - nvAssert(head[0] != NV_INVALID_HEAD); - - /* First lock the heads together, if we have enough heads */ - if (usedHeads > 1) { - NVEvoSubDevPtr pEvoSubDev = &pDevEvo->gpus[sd]; - - if (!pEvoSubDev->scanLockState(pDispEvo, pEvoSubDev, - NV_EVO_LOCK_HEADS, - head)) { - nvEvoLogDispDebug(pDispEvo, EVO_LOG_ERROR, - "Unable to lock heads"); - } else { - headsLocked = TRUE; - } - } - /* Then set up cross-GPU locking, if we have enough active GPUs */ if (numUsedGpus > 1) { NVEvoLockAction action; @@ -1917,21 +2213,6 @@ static void FinishModesetOneTopology(RasterLockTopology *topo) NULL, pClientPin); } - /* - * Normally, the scanlock state machine can determine the client - * lockout window most appropriate for the given configuration. - * However, if we are driving pixels over the DR bus (rather than - * driving a monitor directly via an OR), then the RM programs the - * VPLL with a multiplier that is double the rate of the DR primary. - * This can be inexact, so we may need to crash lock more often than - * when the VPLL settings are identical; not doing so may cause - * rasterlock to fail. Frequent crash locking when driving pixels - * over the DR bus is okay, since they are cleaned up before being - * sent to a non-DR OR. - */ - pDevEvo->gpus[sd].forceZeroClientLockoutWindow = - (sd != pDispEvo->displayOwner); - if (!pDevEvo->gpus[sd].scanLockState(pDispEvo, &pDevEvo->gpus[sd], action, head)) { nvEvoLogDispDebug(pDispEvo, EVO_LOG_ERROR, @@ -1954,89 +2235,443 @@ static void FinishModesetOneTopology(RasterLockTopology *topo) } /* If anything changed, update the hardware */ - if (headsLocked || gpusLocked) { - + if (gpusLocked) { UpdateEvoLockState(); + } + } + + /* Enable fliplock, if we can */ + EnableFlipLockIfRequested(pLockGroup); +} + +/* + * Check if the given LockGroup matches the given FlipLockRequestedGroup. + * This is true if the flip lock heads match the currently-active + * heads on all pDispEvos. + */ +static NvBool CheckLockGroupMatchFlipLockRequestedGroup( + const NVLockGroup *pLockGroup, + const FlipLockRequestedGroup *pFLRG) +{ + const RasterLockGroup *pRasterLockGroup = &pLockGroup->rasterLockGroup; + NvU32 disp, requestedDisp; + + /* Verify the number of disps is the same. */ + NvU32 numRequestedDisps = 0; + for (requestedDisp = 0; + requestedDisp < ARRAY_LEN(pFLRG->disp); + requestedDisp++) { + const NVDispEvoRec *pRequestedDispEvo = + pFLRG->disp[requestedDisp].pDispEvo; + if (pRequestedDispEvo == NULL) { + break; + } + numRequestedDisps++; + } + if (numRequestedDisps != pRasterLockGroup->numDisps) { + return FALSE; + } + + /* + * For each disp in the rasterlock group: + * - If there is no matching disp in the pFLRG, no match + * - If the disp's active head mask doesn't match the pFLRG's requested + * head mask for that disp, no match + * If none of the conditions above failed, then we have a match. + */ + for (disp = 0; disp < pRasterLockGroup->numDisps; disp++) { + const NVDispEvoRec *pDispEvo = pRasterLockGroup->pDispEvoOrder[disp]; + NvBool found = FALSE; + for (requestedDisp = 0; + requestedDisp < ARRAY_LEN(pFLRG->disp); + requestedDisp++) { + const NVDispEvoRec *pRequestedDispEvo = + pFLRG->disp[requestedDisp].pDispEvo; + if (pRequestedDispEvo == NULL) { + break; + } + if (pRequestedDispEvo == pDispEvo) { + if (pFLRG->disp[requestedDisp].flipLockHeads != + nvGetActiveHeadMask(pDispEvo)) { + return FALSE; + } + found = TRUE; + break; + } + } + if (!found) { + return FALSE; + } + } + + return TRUE; +} + +/* + * Check if any requested fliplock groups match this lockgroup; if so, enable + * fliplock on the lockgroup. + */ +static void EnableFlipLockIfRequested(NVLockGroup *pLockGroup) +{ + FlipLockRequestedGroup *pFLRG; + nvListForEachEntry(pFLRG, &requestedFlipLockGroups, listEntry) { + if (CheckLockGroupMatchFlipLockRequestedGroup(pLockGroup, pFLRG)) { + EnableLockGroupFlipLock(pLockGroup); + break; + } + } +} + +/* + * Check if there is an active NVLockGroup that matches the given + * FlipLockRequestedGroup. + * "Matches" means that the NVLockGroup extends to the exact same GPUs as the + * FlipLockRequestedGroup, and that the *active* heads on those GPUs exactly + * match the heads requested in the FlipLockRequestedGroup. + */ +static NVLockGroup *FindMatchingLockGroup(const FlipLockRequestedGroup *pFLRG) +{ + /* If there is an active lock group that matches this pFLRG, it must also + * be active on the first disp, so we don't need to bother looping over + * all disps. */ + NVLockGroup *pLockGroup = pFLRG->disp[0].pDispEvo->pLockGroup; + + if (pLockGroup != NULL && + CheckLockGroupMatchFlipLockRequestedGroup(pLockGroup, pFLRG)) { + return pLockGroup; + } + return NULL; +} + +/* Disable any currently-active lock groups that match the given pFLRG */ +static void +DisableRequestedFlipLockGroup(const FlipLockRequestedGroup *pFLRG) +{ + NVLockGroup *pLockGroup = FindMatchingLockGroup(pFLRG); + if (pLockGroup != NULL) { + DisableLockGroupFlipLock(pLockGroup); + + nvAssert(!pLockGroup->flipLockEnabled); + } +} + +/* + * Check if there is a currently-active rasterlock group that matches the + * disps/heads of this FlipLockRequestedGroup. If so, enable flip lock between + * those heads. + */ +static void +EnableRequestedFlipLockGroup(const FlipLockRequestedGroup *pFLRG) +{ + NVLockGroup *pLockGroup = FindMatchingLockGroup(pFLRG); + if (pLockGroup != NULL) { + EnableLockGroupFlipLock(pLockGroup); + } +} + +/* + * Convert the given API head mask to a HW head mask, using the + * currently-active API head->HW head mapping. + */ +static NvU32 ApiHeadMaskToHwHeadMask( + const NVDispEvoRec *pDispEvo, + const NvU32 apiHeadMask) +{ + const NvU32 numHeads = pDispEvo->pDevEvo->numHeads; + NvU32 apiHead; + NvU32 hwHeadMask = 0; + + for (apiHead = 0; apiHead < numHeads; apiHead++) { + if ((apiHeadMask & (1 << apiHead)) != 0) { + const NVDispApiHeadStateEvoRec *pApiHeadState = + &pDispEvo->apiHeadState[apiHead]; + if (nvApiHeadIsActive(pDispEvo, apiHead)) { + hwHeadMask |= pApiHeadState->hwHeadsMask; + } + } + } + + return hwHeadMask; +} + +/* + * Return true if all main channels are idle on the heads specified in the + * FlipLockRequestedGroup. + */ +static NvBool CheckFlipLockGroupIdle( + const FlipLockRequestedGroup *pFLRG) +{ + NvU32 i; + + for (i = 0; i < ARRAY_LEN(pFLRG->disp); i++) { + NVDispEvoPtr pDispEvo = pFLRG->disp[i].pDispEvo; + if (pDispEvo != NULL) { + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + const NvU32 sd = pDispEvo->displayOwner; + const NvU32 numHeads = pDevEvo->numHeads; + NvU32 head; + + for (head = 0; head < numHeads; head++) { + NvBool isMethodPending; + if (!nvHeadIsActive(pDispEvo, head)) { + continue; + } + if (!pDevEvo->hal->IsChannelMethodPending( + pDevEvo, + pDevEvo->head[head].layer[NVKMS_MAIN_LAYER], + sd, + &isMethodPending) || isMethodPending) { + return FALSE; + } + } + } + } + + return TRUE; +} + +/* + * Return true if all main channels are idle on each head in overlapping flip + * lock groups. + */ +static NvBool CheckOverlappingFlipLockRequestGroupsIdle( + NVDevEvoRec *pDevEvo[NV_MAX_SUBDEVICES], + const struct NvKmsSetFlipLockGroupRequest *pRequest) +{ + NvU32 dev; + + /* Loop over the GPUs specified in this FlipLockGroupRequest */ + for (dev = 0; dev < NV_MAX_SUBDEVICES && pDevEvo[dev] != NULL; dev++) { + NVDispEvoPtr pDispEvo; + NvU32 sd; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo[dev]) { + FlipLockRequestedGroup *pFLRG; + + if ((pRequest->dev[dev].requestedDispsBitMask & (1 << sd)) == 0) { + continue; + } /* - * Enable fliplock, if we can + * For each specified GPU, search through existing requested + * fliplock groups and find any that overlap with heads in this + * request. * - * XXX this should arguably be done in the state machine proper. - * However, in order to guarantee that we get rasterlock before - * attempting fliplock (and to be symmetric with framelock, which - * turns on and off fliplock from GLS), do it here for now. + * Return FALSE if any overlapping fliplock groups are not idle. */ - if (gpusLocked && flipLockPossible) { - NVEvoUpdateState updateState = { }; + nvListForEachEntry(pFLRG, &requestedFlipLockGroups, listEntry) { + NvU32 i; + for (i = 0; i < ARRAY_LEN(pFLRG->disp); i++) { + if (pFLRG->disp[i].pDispEvo == NULL) { + break; + } + if (pFLRG->disp[i].pDispEvo == pDispEvo) { + /* API heads requested for this disp by the client */ + const NvU32 requestedApiHeadMask = + pRequest->dev[dev].disp[sd].requestedHeadsBitMask; + const NvU32 requestedHwHeadMask = + ApiHeadMaskToHwHeadMask(pDispEvo, requestedApiHeadMask); + + if ((requestedHwHeadMask & + pFLRG->disp[i].flipLockHeads) != 0) { + /* Match */ + if (!CheckFlipLockGroupIdle(pFLRG)) { + return FALSE; + } + } + break; + } + } + } + } + } - /* - * Before turning on flip lock, we're supposed to wait for - * raster lock sync. The update performed in - * UpdateEvoLockState() to kick off and apply the rasterlock - * params must be synchronous as EVO reports lock success if - * locking isn't enabled, so we could race through the - * WaitForLock check below otherwise. - */ + return TRUE; +} - for (j = 0; j < usedHeads; j++) { - NvU32 tmpHead = head[j]; - NvU64 startTime = 0; +/* + * Disable and remove any FlipLockRequestGroups that contain any of the heads + * in 'hwHeadsMask' on the given pDispEvo. + */ +static void +RemoveOverlappingFlipLockRequestGroupsOneDisp( + NVDispEvoRec *pDispEvo, + NvU32 hwHeadMask) +{ + FlipLockRequestedGroup *pFLRG, *tmp; - NVEvoLockPin pin = - nvEvoGetPinForSignal(pDispEvo, &pDevEvo->gpus[sd], - NV_EVO_LOCK_SIGNAL_FLIP_LOCK); + /* + * For each specified GPU, search through existing requested + * fliplock groups and find any that overlap with heads in this + * request. + * + * For any that are found, disable fliplock and remove the + * requested flip lock group. + */ + nvListForEachEntry_safe(pFLRG, tmp, &requestedFlipLockGroups, listEntry) { + NvU32 i; - /* Wait for the raster lock to sync in.. */ - if (pin == NV_EVO_LOCK_PIN_ERROR || - !EvoWaitForLock(pDevEvo, sd, tmpHead, EVO_RASTER_LOCK, - &startTime)) { - flipLockPossible = FALSE; - break; - } + for (i = 0; i < ARRAY_LEN(pFLRG->disp); i++) { + if (pFLRG->disp[i].pDispEvo == NULL) { + break; + } + if (pFLRG->disp[i].pDispEvo == pDispEvo) { + + if ((hwHeadMask & + pFLRG->disp[i].flipLockHeads) != 0) { + /* Match */ + DisableRequestedFlipLockGroup(pFLRG); + + /* Remove from global list */ + nvListDel(&pFLRG->listEntry); + nvFree(pFLRG); + } + break; + } + } + } +} + +/* + * Disable and remove any FlipLockRequestGroups that contain any of the heads + * specified in 'pRequest'. + */ +static void +RemoveOverlappingFlipLockRequestGroups( + NVDevEvoRec *pDevEvo[NV_MAX_SUBDEVICES], + const struct NvKmsSetFlipLockGroupRequest *pRequest) +{ + NvU32 dev; + + /* Loop over the GPUs specified in this FlipLockGroupRequest */ + for (dev = 0; dev < NV_MAX_SUBDEVICES && pDevEvo[dev] != NULL; dev++) { + NVDispEvoPtr pDispEvo; + NvU32 sd; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo[dev]) { + NvU32 requestedApiHeadMask, requestedHwHeadMask; + + if ((pRequest->dev[dev].requestedDispsBitMask & (1 << sd)) == 0) { + continue; + } + + /* API heads requested for this disp by the client */ + requestedApiHeadMask = + pRequest->dev[dev].disp[sd].requestedHeadsBitMask; + requestedHwHeadMask = + ApiHeadMaskToHwHeadMask(pDispEvo, requestedApiHeadMask); + + RemoveOverlappingFlipLockRequestGroupsOneDisp(pDispEvo, + requestedHwHeadMask); + } + } +} + +/* + * Disable and remove any FlipLockRequestGroups that contain any of the heads + * specified in 'pRequest'. + */ +void nvEvoRemoveOverlappingFlipLockRequestGroupsForModeset( + NVDevEvoPtr pDevEvo, + const struct NvKmsSetModeRequest *pRequest) +{ + NVDispEvoPtr pDispEvo; + NvU32 sd; + + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + NvU32 requestedApiHeadMask, requestedHwHeadMask; + + if ((pRequest->requestedDispsBitMask & (1 << sd)) == 0) { + continue; + } + + /* API heads requested for this disp by the client */ + requestedApiHeadMask = + pRequest->disp[sd].requestedHeadsBitMask; + requestedHwHeadMask = + ApiHeadMaskToHwHeadMask(pDispEvo, requestedApiHeadMask); + + RemoveOverlappingFlipLockRequestGroupsOneDisp(pDispEvo, + requestedHwHeadMask); + } +} + +/*! + * Handle a NVKMS_IOCTL_SET_FLIPLOCK_GROUP request. This assumes that the + * request was already validated by nvkms.c:SetFlipLockGroup(). + * + * param[in] pDevEvo Array of NVDevEvoPtr pointers, in the same order as + * the deviceHandle were specified in the request. + * param[in] pRequest The ioctl request. + */ +NvBool +nvSetFlipLockGroup(NVDevEvoRec *pDevEvo[NV_MAX_SUBDEVICES], + const struct NvKmsSetFlipLockGroupRequest *pRequest) +{ + FlipLockRequestedGroup *pFLRG = NULL; + + /* Construct the new RequestedFlipLockGroup first, so if it fails we can + * return before removing overlapping groups. */ + if (pRequest->enable) { + NvU32 dev, disp; - /* - * Enable fliplock, and register that we've enabled - * fliplock for SLI to ensure it doesn't get disabled - * later. - */ - pDevEvo->gpus[sd].headControl[tmpHead].flipLockPin = pin; - pDevEvo->gpus[sd].flipLockPinSetForSliHeadMask = - HEAD_MASK_SET(pDevEvo->gpus[sd].flipLockPinSetForSliHeadMask, tmpHead); + pFLRG = nvCalloc(1, sizeof(*pFLRG)); + if (pFLRG == NULL) { + goto fail; + } - pDevEvo->gpus[sd].headControl[tmpHead].flipLock = TRUE; - pDevEvo->gpus[sd].flipLockEnabledForSliHeadMask = - HEAD_MASK_SET(pDevEvo->gpus[sd].flipLockEnabledForSliHeadMask, tmpHead); + disp = 0; + for (dev = 0; dev < NV_MAX_SUBDEVICES && pDevEvo[dev] != NULL; dev++) { + NVDispEvoPtr pDispEvo; + NvU32 sd; - EvoUpdateHeadParams(pDispEvo, tmpHead, &updateState); - } + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo[dev]) { + const NvU32 requestedApiHeads = + pRequest->dev[dev].disp[sd].requestedHeadsBitMask; - /* - * This must be synchronous as EVO reports lock success if - * locking isn't enabled, so we could race through the - * WaitForLock check below otherwise. - */ - nvEvoUpdateAndKickOff(pDispEvo, TRUE, &updateState, - TRUE /* releaseElv */); + if ((pRequest->dev[dev].requestedDispsBitMask & (1 << sd)) == 0) { + continue; + } - /* - * Wait for flip lock sync. I'm not sure this is really - * necessary, but the docs say to do this before attempting any - * flips in the base channel. - */ - for (j = 0; j < usedHeads; j++) { - NvU64 startTime = 0; - if (flipLockPossible && - !EvoWaitForLock(pDevEvo, sd, head[j], EVO_FLIP_LOCK, - &startTime)) { - flipLockPossible = FALSE; - break; - } + if (disp >= ARRAY_LEN(pFLRG->disp)) { + nvAssert(!"FlipLockRequestedGroup::disp too short?"); + goto fail; } + + pFLRG->disp[disp].pDispEvo = pDispEvo; + pFLRG->disp[disp].flipLockHeads = + ApiHeadMaskToHwHeadMask(pDispEvo, requestedApiHeads); + disp++; } } + + if (!CheckFlipLockGroupIdle(pFLRG)) { + nvEvoLogDebug(EVO_LOG_ERROR, + "Failed to request flip lock: group not idle"); + goto fail; + } } -} /* FinishModesetOneTopology() */ + if (!CheckOverlappingFlipLockRequestGroupsIdle(pDevEvo, pRequest)) { + nvEvoLogDebug(EVO_LOG_ERROR, + "Failed to request flip lock: overlapping group(s) not idle"); + goto fail; + } + + RemoveOverlappingFlipLockRequestGroups(pDevEvo, pRequest); + + if (pFLRG) { + nvListAdd(&pFLRG->listEntry, &requestedFlipLockGroups); + + EnableRequestedFlipLockGroup(pFLRG); + } + + return TRUE; + +fail: + nvFree(pFLRG); + return FALSE; +} NvBool nvSetUsageBoundsEvo( NVDevEvoPtr pDevEvo, @@ -2112,7 +2747,7 @@ NvBool nvGetDefaultColorSpace( } NvBool nvChooseColorRangeEvo( - enum NvKmsOutputTf tf, + enum NvKmsOutputColorimetry colorimetry, const enum NvKmsDpyAttributeColorRangeValue requestedColorRange, const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, const enum NvKmsDpyAttributeColorBpcValue colorBpc, @@ -2125,16 +2760,16 @@ NvBool nvChooseColorRangeEvo( if ((colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB) && (colorBpc == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_6)) { /* At depth 18 only RGB and full range are allowed */ - if (tf == NVKMS_OUTPUT_TF_PQ) { - /* NVKMS_OUTPUT_TF_PQ requires limited color range */ + if (colorimetry == NVKMS_OUTPUT_COLORIMETRY_BT2100) { + /* BT2100 requires limited color range */ return FALSE; } *pColorRange = NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_FULL; } else if ((colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr444) || (colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422) || (colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr420) || - (tf == NVKMS_OUTPUT_TF_PQ)) { - /* Both YUV and NVKMS_OUTPUT_TF_PQ requires limited color range. */ + (colorimetry == NVKMS_OUTPUT_COLORIMETRY_BT2100)) { + /* Both YUV and BT2100 colorimetry require limited color range. */ *pColorRange = NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_LIMITED; } else { *pColorRange = requestedColorRange; @@ -2157,8 +2792,9 @@ NvBool nvChooseColorRangeEvo( */ NvBool nvChooseCurrentColorSpaceAndRangeEvo( const NVDpyEvoRec *pDpyEvo, - enum NvYuv420Mode yuv420Mode, - enum NvKmsOutputTf tf, + const NVHwModeTimingsEvo *pHwTimings, + NvU8 hdmiFrlBpc, + enum NvKmsOutputColorimetry colorimetry, const enum NvKmsDpyAttributeRequestedColorSpaceValue requestedColorSpace, const enum NvKmsDpyAttributeColorRangeValue requestedColorRange, enum NvKmsDpyAttributeCurrentColorSpaceValue *pCurrentColorSpace, @@ -2174,30 +2810,21 @@ NvBool nvChooseCurrentColorSpaceAndRangeEvo( const NVColorFormatInfoRec colorFormatsInfo = nvGetColorFormatInfo(pDpyEvo); - // XXX HDR TODO: Handle other transfer functions + // XXX HDR TODO: Handle other colorimetries // XXX HDR TODO: Handle YUV - if (tf == NVKMS_OUTPUT_TF_PQ) { + if (colorimetry == NVKMS_OUTPUT_COLORIMETRY_BT2100) { /* - * If the head is currently in PQ output mode, we override the + * If the head currently has BT2100 colorimetry, we override the * requested color space with RGB. We cannot support yuv420Mode in * that configuration, so fail in that case. */ - if (yuv420Mode != NV_YUV420_MODE_NONE) { + if (pHwTimings->yuv420Mode != NV_YUV420_MODE_NONE) { return FALSE; } - /* - * At depth 18 only RGB and full range are allowed. Also, - * NVKMS_OUTPUT_TF_PQ requires limited range, which we can't do at - * depth 18; fail in that case. - */ - if (colorFormatsInfo.rgb444.maxBpc == - NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_6) { - return FALSE; - } newColorSpace = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB; newColorBpc = colorFormatsInfo.rgb444.maxBpc; - } else if (yuv420Mode != NV_YUV420_MODE_NONE) { + } else if (pHwTimings->yuv420Mode != NV_YUV420_MODE_NONE) { /* * If the current mode timing requires YUV420 compression, we override the * requested color space with YUV420. @@ -2238,11 +2865,31 @@ NvBool nvChooseCurrentColorSpaceAndRangeEvo( } } - if (!nvChooseColorRangeEvo(tf, requestedColorRange, newColorSpace, - newColorBpc, &newColorRange)) { + /* + * Downgrade BPC if HDMI configuration does not support current selection + * with TMDS or FRL. + */ + if (nvDpyIsHdmiEvo(pDpyEvo) && + nvHdmiTimingsNeedFrl(pDpyEvo, pHwTimings, newColorBpc) && + (newColorBpc > hdmiFrlBpc)) { + + newColorBpc = + hdmiFrlBpc ? hdmiFrlBpc : NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8; + nvAssert(newColorBpc >= NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8); + } + + // 10 BPC required for HDR + // XXX HDR TODO: Handle other colorimetries + // XXX HDR TODO: Handle YUV + if ((colorimetry == NVKMS_OUTPUT_COLORIMETRY_BT2100) && + (newColorBpc < NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_10)) { return FALSE; } + if (!nvChooseColorRangeEvo(colorimetry, requestedColorRange, newColorSpace, + newColorBpc, &newColorRange)) { + } + *pCurrentColorSpace = newColorSpace; *pCurrentColorRange = newColorRange; *pCurrentColorBpc = newColorBpc; @@ -2253,6 +2900,7 @@ NvBool nvChooseCurrentColorSpaceAndRangeEvo( void nvUpdateCurrentHardwareColorSpaceAndRangeEvo( NVDispEvoPtr pDispEvo, const NvU32 head, + enum NvKmsOutputColorimetry colorimetry, const enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace, const enum NvKmsDpyAttributeColorRangeValue colorRange, NVEvoUpdateState *pUpdateState) @@ -2263,7 +2911,8 @@ void nvUpdateCurrentHardwareColorSpaceAndRangeEvo( nvAssert(pConnectorEvo != NULL); - if (pHeadState->tf == NVKMS_OUTPUT_TF_PQ) { + // XXX HDR TODO: Support more output colorimetries + if (colorimetry == NVKMS_OUTPUT_COLORIMETRY_BT2100) { nvAssert(pHeadState->timings.yuv420Mode == NV_YUV420_MODE_NONE); nvAssert(colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB); nvAssert(colorRange == NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_LIMITED); @@ -2752,11 +3401,33 @@ static NvU32 GpuIndex(const NVDevEvoRec *pDevEvo, NvU32 sd) return 0; } +NvU32 nvGetRefreshRate10kHz(const NVHwModeTimingsEvo *pTimings) +{ + const NvU32 totalPixels = pTimings->rasterSize.x * pTimings->rasterSize.y; + + /* + * pTimings->pixelClock is in 1000/s + * we want 0.0001/s + * factor = 1000/0.0001 = 10000000. + */ + NvU32 factor = 10000000; + + if (pTimings->doubleScan) factor /= 2; + if (pTimings->interlaced) factor *= 2; + + if (totalPixels == 0) { + return 0; + } + + return axb_div_c(pTimings->pixelClock, factor, totalPixels); +} + /*! * Get the current refresh rate for the heads in headMask, in 0.0001 Hz units. * All heads in headMask are expected to have the same refresh rate. */ -static NvU32 GetRefreshRate10kHz(const NVDispEvoRec *pDispEvo, NvU32 headMask) +static NvU32 GetRefreshRateHeadMask10kHz(const NVDispEvoRec *pDispEvo, + NvU32 headMask) { const NVHwModeTimingsEvo *pTimings = NULL; NvU32 head; @@ -2787,18 +3458,7 @@ static NvU32 GetRefreshRate10kHz(const NVDispEvoRec *pDispEvo, NvU32 headMask) return 0; } - /* - * pTimings->pixelClock is in 1000/s - * we want 0.0001/s - * factor = 1000/0.0001 = 10000000. - */ - NvU32 factor = 10000000; - NvU32 totalPixels = pTimings->rasterSize.x * pTimings->rasterSize.y; - - if (pTimings->doubleScan) factor /= 2; - if (pTimings->interlaced) factor *= 2; - - return axb_div_c(pTimings->pixelClock, factor, totalPixels); + return nvGetRefreshRate10kHz(pTimings); } /*! @@ -2840,7 +3500,8 @@ static NvBool FramelockSetControlSync(NVDispEvoPtr pDispEvo, const NvU32 headMas return FALSE; } - gsyncSetControlSyncParams.refresh = GetRefreshRate10kHz(pDispEvo, headMask); + gsyncSetControlSyncParams.refresh = + GetRefreshRateHeadMask10kHz(pDispEvo, headMask); ret = nvRmApiControl(nvEvoGlobal.clientHandle, pFrameLockEvo->device, @@ -3317,7 +3978,7 @@ static NvU32 applyActionForHeads(NVDispEvoPtr pDispEvo, NvU32 head; FOR_ALL_HEADS(head, headMask) { - NvU32 pHeads[NVKMS_MAX_HEADS_PER_DISP + 1]; + NvU32 pHeads[NVKMS_MAX_HEADS_PER_DISP + 1] = { NV_INVALID_HEAD, }; unsigned int i = 0; NvU32 tmpHead, usedHeadMask = 0; @@ -3552,13 +4213,13 @@ NvBool nvQueryRasterLockEvo(const NVDpyEvoRec *pDpyEvo, NvS64 *val) return TRUE; } -void nvInvalidateTopologiesEvo(void) +void nvInvalidateRasterLockGroupsEvo(void) { - if (nvEvoGlobal.globalTopologies) { - nvFree(nvEvoGlobal.globalTopologies); + if (globalRasterLockGroups) { + nvFree(globalRasterLockGroups); - nvEvoGlobal.globalTopologies = NULL; - nvEvoGlobal.numGlobalTopos = 0; + globalRasterLockGroups = NULL; + numGlobalRasterLockGroups = 0; } } @@ -3626,31 +4287,19 @@ NvU64 nvEvoGetFormatsWithEqualOrLowerUsageBound( NvBool nvUpdateFlipLockEvoOneHead(NVDispEvoPtr pDispEvo, const NvU32 head, NvU32 *val, NvBool set, - NvBool *needsEarlyUpdate, NVEvoUpdateState *updateState) { NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; NVEvoSubDevPtr pEvoSubDev = &pDevEvo->gpus[pDispEvo->displayOwner]; NVEvoHeadControlPtr pHC = &pEvoSubDev->headControl[head]; - /* - * XXX: [2Heads1OR] If head is locked in the merge mode then its flip-lock - * state can not be changed. - */ - if (pHC->mergeMode) { - return FALSE; - } - - if (needsEarlyUpdate) { - *needsEarlyUpdate = FALSE; - } - if (set) { // make sure we're dealing with a bool NvBool setVal = !!*val; if (setVal ^ pHC->flipLock) { NvBool isMethodPending; + NvBool changed = FALSE; if (!pDevEvo->hal-> IsChannelMethodPending(pDevEvo, @@ -3663,35 +4312,37 @@ NvBool nvUpdateFlipLockEvoOneHead(NVDispEvoPtr pDispEvo, const NvU32 head, } if (setVal) { - // make sure flip lock is not prohibited and raster lock is enabled + /* make sure flip lock is not prohibited and raster lock is enabled + * + * XXX: [2Heads1OR] If head is locked in the merge mode then + * its flip-lock state can not be changed. + */ if ((pHC->serverLock == NV_EVO_NO_LOCK && pHC->clientLock == NV_EVO_NO_LOCK) || HEAD_MASK_QUERY(pEvoSubDev->flipLockProhibitedHeadMask, - head)) { + head) || + pHC->mergeMode) { return FALSE; } pHC->flipLock = TRUE; + changed = TRUE; } else { - /* Only actually disable fliplock if it's not needed for SLI */ - if (!HEAD_MASK_QUERY(pEvoSubDev->flipLockEnabledForSliHeadMask, + /* Only actually disable fliplock if it's not needed for SLI. + * + * XXX: [2Heads1OR] If head is locked in the merge mode then + * its flip-lock state can not be changed. + */ + if (!pHC->mergeMode && + !HEAD_MASK_QUERY(pEvoSubDev->flipLockEnabledForSliHeadMask, head)) { pHC->flipLock = FALSE; - - /* - * When disabling fliplock during a modeset, the core - * channel needs to be updated before issuing further - * base flips. Notify the caller that fliplock has - * been disabled in the core channel's assembly state, - * and needs to be committed before issuing non-fliplocked - * base flips. - */ - if (needsEarlyUpdate) { - *needsEarlyUpdate = TRUE; - } + changed = TRUE; } } - EvoUpdateHeadParams(pDispEvo, head, updateState); + if (changed) { + EvoUpdateHeadParams(pDispEvo, head, updateState); + } } /* Remember if we currently need fliplock enabled for framelock */ @@ -3721,23 +4372,11 @@ static NvBool UpdateFlipLock50(const NVDpyEvoRec *pDpyEvo, NVEvoUpdateState updateState = { }; NvBool ret; - /* - * XXX[2Heads1OR] The EVO lock state machine is not currently supported with - * 2Heads1OR, the api head is expected to be mapped onto a single - * hardware head (which is the primary hardware head) if 2Heads1OR is not - * active and the EVO lock state machine is in use. - */ - if ((apiHead == NV_INVALID_HEAD) || - (nvPopCount32(pDispEvo->apiHeadState[apiHead].hwHeadsMask) != 1)) { - return FALSE; - } - if (head == NV_INVALID_HEAD) { return FALSE; } ret = nvUpdateFlipLockEvoOneHead(pDispEvo, head, val, set, - NULL /* needsEarlyUpdate */, &updateState); if (set && ret) { @@ -3980,12 +4619,6 @@ static void EvoSetViewportPointIn(NVDispEvoPtr pDispEvo, const NvU32 head, nvPopEvoSubDevMask(pDevEvo); } -static inline NvU32 LUTNotifierForApiHead(const NvU32 apiHead) -{ - nvAssert(apiHead != NV_INVALID_HEAD); - return 1 + apiHead; -} - void nvEvoSetLUTContextDma(NVDispEvoPtr pDispEvo, const NvU32 head, NVEvoUpdateState *pUpdateState) { @@ -4020,17 +4653,39 @@ static void EvoUpdateCurrentPalette(NVDispEvoPtr pDispEvo, const NvU32 apiHead) * state to kickoff. */ if (!nvIsUpdateStateEmpty(pDevEvo, &updateState)) { + int notifier; + NvBool notify; + + nvEvoStageLUTNotifier(pDispEvo, apiHead); + notifier = nvEvoCommitLUTNotifiers(pDispEvo); + + nvAssert(notifier >= 0); + + /* + * XXX: The notifier index returned by nvEvoCommitLUTNotifiers here + * shouldn't be < 0 because this function shouldn't have been called + * while a previous LUT update is outstanding. If + * nvEvoCommitLUTNotifiers ever returns -1 for one reason or another, + * using notify and setting notifier to 0 in this manner to avoid + * setting an invalid notifier in the following Update call prevents + * potential kernel panics and Xids. + */ + notify = notifier >= 0; + if (!notify) { + notifier = 0; + } + // Clear the completion notifier and kick off an update. Wait for it // here if NV_CTRL_SYNCHRONOUS_PALETTE_UPDATES is enabled. Otherwise, // don't wait for the notifier -- it'll be checked the next time a LUT // change request comes in. EvoUpdateAndKickOffWithNotifier(pDispEvo, - TRUE, /* notify */ + notify, /* notify */ FALSE, /* sync */ - LUTNotifierForApiHead(apiHead), + notifier, &updateState, TRUE /* releaseElv */); - pDevEvo->lut.apiHead[apiHead].disp[dispIndex].waitForPreviousUpdate = TRUE; + pDevEvo->lut.apiHead[apiHead].disp[dispIndex].waitForPreviousUpdate |= notify; } } @@ -4855,7 +5510,10 @@ NvBool nvResumeDevEvo(NVDevEvoRec *pDevEvo) * restore the assignment, might be in use by the boot display setup * by vbios/gop driver. */ - nvShutDownApiHeads(pDevEvo, NULL /* pTestFunc, shut down all heads */); + nvShutDownApiHeads(pDevEvo, pDevEvo->pNvKmsOpenDev, + NULL /* pTestFunc, shut down all heads */, + NULL /* pData */, + TRUE /* doRasterLock */); FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { RestoreSorAssignList(pDispEvo, disp[dispIndex].sorAssignList); @@ -5120,6 +5778,7 @@ static void LayerSetPositionOneApiHead(NVDispEvoRec *pDispEvo, const NvU32 sd = pDispEvo->displayOwner; NvU32 head; + nvPushEvoSubDevMaskDisp(pDispEvo); FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { NVEvoSubDevHeadStateRec *pSdHeadState = &pDevEvo->gpus[sd].headState[head]; @@ -5136,6 +5795,7 @@ static void LayerSetPositionOneApiHead(NVDispEvoRec *pDispEvo, x, y); } } + nvPopEvoSubDevMask(pDevEvo); } NvBool nvLayerSetPositionEvo( @@ -5824,9 +6484,14 @@ void nvAssignDefaultUsageBounds(const NVDispEvoRec *pDispEvo, for (i = 0; i < ARRAY_LEN(pPossible->layer); i++) { struct NvKmsScalingUsageBounds *pScaling = &pPossible->layer[i].scaling; - pPossible->layer[i].usable = TRUE; pPossible->layer[i].supportedSurfaceMemoryFormats = pDevEvo->caps.layerCaps[i].supportedSurfaceMemoryFormats; + pPossible->layer[i].usable = + (pPossible->layer[i].supportedSurfaceMemoryFormats != 0); + if (!pPossible->layer[i].usable) { + continue; + } + nvInitScalingUsageBounds(pDevEvo, pScaling); if (pDevEvo->hal->GetWindowScalingCaps) { @@ -5978,10 +6643,12 @@ ConstructHwModeTimingsViewPort(const NVDispEvoRec *pDispEvo, */ static NvBool GetDfpProtocol(const NVDpyEvoRec *pDpyEvo, + const struct NvKmsModeValidationParams *pParams, NVHwModeTimingsEvoPtr pTimings) { NVConnectorEvoPtr pConnectorEvo = pDpyEvo->pConnectorEvo; const NvU32 rmProtocol = pConnectorEvo->or.protocol; + const NvU32 overrides = pParams->overrides; enum nvKmsTimingsProtocol timingsProtocol; nvAssert(pConnectorEvo->legacyType == @@ -5990,10 +6657,20 @@ static NvBool GetDfpProtocol(const NVDpyEvoRec *pDpyEvo, if (pConnectorEvo->or.type == NV0073_CTRL_SPECIFIC_OR_TYPE_SOR) { /* Override protocol if this mode requires HDMI FRL. */ if (nvDpyIsHdmiEvo(pDpyEvo) && - nvHdmiTimingsNeedFrl(pDpyEvo, pTimings)) { + /* If we don't require boot clocks... */ + ((overrides & NVKMS_MODE_VALIDATION_REQUIRE_BOOT_CLOCKS) == 0) && + /* If FRL is supported, use it for 10 BPC if needed. */ + ((nvHdmiDpySupportsFrl(pDpyEvo) && + nvDpyIsHdmiDepth30Evo(pDpyEvo) && + nvHdmiTimingsNeedFrl(pDpyEvo, pTimings, HDMI_BPC10)) || + /* Fall back to 8 BPC, use FRL if needed. */ + nvHdmiTimingsNeedFrl(pDpyEvo, pTimings, HDMI_BPC8))) { + + /* If FRL is needed for 8 BPC, but not supported, fail. */ if (!nvHdmiDpySupportsFrl(pDpyEvo)) { return FALSE; } + nvAssert(nvDpyIsHdmiEvo(pDpyEvo)); nvAssert(rmProtocol == NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_A || rmProtocol == NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_B); @@ -6113,7 +6790,7 @@ static NvBool ConstructHwModeTimingsEvoDfp(const NVDpyEvoRec *pDpyEvo, ConstructHwModeTimingsFromNvModeTimings(pModeTimings, pTimings); - ret = GetDfpProtocol(pDpyEvo, pTimings); + ret = GetDfpProtocol(pDpyEvo, pParams, pTimings); if (!ret) { return ret; @@ -7098,26 +7775,26 @@ static NvBool FrameLockSli(NVDevEvoPtr pDevEvo, NvU32 action, NvBool queryOnly) { - RasterLockTopology *topos; + RasterLockGroup *pRasterLockGroups; NVEvoSubDevPtr pEvoSubDev; NVDispEvoPtr pDispEvo; - unsigned int numTopos; + unsigned int numRasterLockGroups; - topos = GetRasterLockTopologies(pDevEvo, &numTopos); - if (!topos) { + pRasterLockGroups = GetRasterLockGroups(pDevEvo, &numRasterLockGroups); + if (!pRasterLockGroups) { return FALSE; } - nvAssert(numTopos == 1); - if (numTopos != 1) { - nvFree(topos); + nvAssert(numRasterLockGroups == 1); + if (numRasterLockGroups != 1) { + nvFree(pRasterLockGroups); return FALSE; } /* Want to be framelock server */ - pDispEvo = topos[0].pDispEvoOrder[0]; + pDispEvo = pRasterLockGroups[0].pDispEvoOrder[0]; - nvFree(topos); + nvFree(pRasterLockGroups); if (!pDispEvo) { return FALSE; @@ -7130,7 +7807,7 @@ static NvBool FrameLockSli(NVDevEvoPtr pDevEvo, if (queryOnly) { return pEvoSubDev->scanLockState(pDispEvo, pEvoSubDev, action, NULL); } else { - NvU32 pHeads[NVKMS_MAX_HEADS_PER_DISP + 1]; + NvU32 pHeads[NVKMS_MAX_HEADS_PER_DISP + 1] = { NV_INVALID_HEAD, }; NvU32 i = 0; NvU32 head; @@ -7241,6 +7918,193 @@ static void GetRasterLockPin(NVDispEvoPtr pDispEvo0, NvU32 head0, } } /* GetRasterLockPin */ +static void UpdateLUTNotifierTracking( + NVDispEvoPtr pDispEvo) +{ + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + const int dispIndex = pDispEvo->displayOwner; + NvU32 i; + + for (i = 0; i < ARRAY_LEN(pDevEvo->lut.notifierState.sd[dispIndex].notifiers); i++) { + int notifier = pDevEvo->lut.notifierState.sd[dispIndex].notifiers[i].notifier; + + if (!pDevEvo->lut.notifierState.sd[dispIndex].notifiers[i].waiting) { + continue; + } + + if (!pDevEvo->hal->IsCompNotifierComplete(pDevEvo->pDispEvo[dispIndex], + notifier)) { + continue; + } + + pDevEvo->lut.notifierState.sd[dispIndex].waitingApiHeadMask &= + ~pDevEvo->lut.notifierState.sd[dispIndex].notifiers[i].apiHeadMask; + pDevEvo->lut.notifierState.sd[dispIndex].notifiers[i].waiting = FALSE; + } +} + +/* + * Check whether there are any staged API head LUT notifiers that need to be + * committed. + */ +NvBool nvEvoLUTNotifiersNeedCommit( + NVDispEvoPtr pDispEvo) +{ + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + const int dispIndex = pDispEvo->displayOwner; + NvU32 apiHeadMask = pDevEvo->lut.notifierState.sd[dispIndex].stagedApiHeadMask; + + return apiHeadMask != 0; +} + +/* + * Set up tracking for a LUT Notifier for the apiHeads in stagedApiHeadMask. + * + * The notifier returned by this function must be passed to a subsequent call to + * EvoUpdateAndKickOffWithNotifier. + * + * Returns -1 if an error occurs or no apiHeads need a new LUT notifier. Passing + * the -1 to EvoUpdateAndKickOffWithNotifier with its notify parameter set may + * result in kernel panics. + */ +int nvEvoCommitLUTNotifiers( + NVDispEvoPtr pDispEvo) +{ + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + const int dispIndex = pDispEvo->displayOwner; + NvU32 apiHeadMask = pDevEvo->lut.notifierState.sd[dispIndex].stagedApiHeadMask; + int i; + + pDevEvo->lut.notifierState.sd[dispIndex].stagedApiHeadMask = 0; + + UpdateLUTNotifierTracking(pDispEvo); + + if (apiHeadMask == 0) { + return -1; + } + + if (pDevEvo->lut.notifierState.sd[dispIndex].waitingApiHeadMask & + apiHeadMask) { + /* + * an apiHead in the requested list is already waiting on a + * notifier + */ + nvEvoLogDisp(pDispEvo, EVO_LOG_WARN, "A requested API head is already waiting on a notifier"); + return -1; + } + + for (i = 0; i < ARRAY_LEN(pDevEvo->lut.notifierState.sd[dispIndex].notifiers); i++) { + int notifier = (dispIndex * NVKMS_MAX_HEADS_PER_DISP) + i + 1; + + if (pDevEvo->lut.notifierState.sd[dispIndex].notifiers[i].waiting) { + continue; + } + + /* use this notifier */ + pDevEvo->lut.notifierState.sd[dispIndex].notifiers[i].notifier = notifier; + pDevEvo->lut.notifierState.sd[dispIndex].notifiers[i].waiting = TRUE; + pDevEvo->lut.notifierState.sd[dispIndex].notifiers[i].apiHeadMask = apiHeadMask; + + pDevEvo->lut.notifierState.sd[dispIndex].waitingApiHeadMask |= + apiHeadMask; + + return notifier; + } + + /* slot not found */ + nvEvoLogDisp(pDispEvo, EVO_LOG_WARN, "No remaining LUT notifier slots"); + return -1; +} + +/* + * Unstage any staged API Heads' notifiers. + */ +void nvEvoClearStagedLUTNotifiers( + NVDispEvoPtr pDispEvo) +{ + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + const int dispIndex = pDispEvo->displayOwner; + + pDevEvo->lut.notifierState.sd[dispIndex].stagedApiHeadMask = 0; +} + +/* + * Stage the API Head's notifier for tracking. In order to kickoff the staged + * notifier, nvEvoCommitLUTNotifiers must be called and its return value + * passed to EvoUpdateAndKickoffWithNotifier. + * + * This function and its siblings nvEvoIsLUTNotifierComplete and + * nvEvoWaitForLUTNotifier can be used by callers of nvEvoSetLut to ensure the + * triple-buffer for the color LUT is not overflowed even when nvEvoSetLut is + * called with kickoff = FALSE. + */ +void nvEvoStageLUTNotifier( + NVDispEvoPtr pDispEvo, + NvU32 apiHead) +{ + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + const int dispIndex = pDispEvo->displayOwner; + + nvAssert((pDevEvo->lut.notifierState.sd[dispIndex].stagedApiHeadMask & + NVBIT(apiHead)) == 0); + + pDevEvo->lut.notifierState.sd[dispIndex].stagedApiHeadMask |= + NVBIT(apiHead); +} + +/* + * Check if the api head's LUT Notifier is complete. + */ + +NvBool nvEvoIsLUTNotifierComplete( + NVDispEvoPtr pDispEvo, + NvU32 apiHead) +{ + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + const int dispIndex = pDispEvo->displayOwner; + + UpdateLUTNotifierTracking(pDispEvo); + + return (pDevEvo->lut.notifierState.sd[dispIndex].waitingApiHeadMask & + NVBIT(apiHead)) == 0; +} + +/* + * Wait for the api head's LUT Notifier to complete. + * + * This function blocks while waiting for the notifier. + */ + +void nvEvoWaitForLUTNotifier( + const NVDispEvoPtr pDispEvo, + NvU32 apiHead) +{ + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + const int dispIndex = pDispEvo->displayOwner; + int i; + + if (nvEvoIsLUTNotifierComplete(pDispEvo, apiHead)) { + return; + } + + for (i = 0; i < ARRAY_LEN(pDevEvo->lut.notifierState.sd[dispIndex].notifiers); i++) { + int notifier = pDevEvo->lut.notifierState.sd[dispIndex].notifiers[i].notifier; + + if (!pDevEvo->lut.notifierState.sd[dispIndex].notifiers[i].waiting) { + continue; + } + + if ((pDevEvo->lut.notifierState.sd[dispIndex].notifiers[i].apiHeadMask & + NVBIT(apiHead)) == 0) { + + continue; + } + + pDevEvo->hal->WaitForCompNotifier(pDispEvo, notifier); + return; + } +} + static void EvoIncrementCurrentLutIndex(NVDispEvoRec *pDispEvo, const NvU32 apiHead, const NvBool baseLutEnabled, @@ -7278,10 +8142,7 @@ static NvU32 UpdateLUTTimer(NVDispEvoPtr pDispEvo, const NvBool baseLutEnabled, const NvBool outputLutEnabled) { - NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; - - if (!pDevEvo->hal->IsCompNotifierComplete(pDispEvo, - LUTNotifierForApiHead(apiHead))) { + if (!nvEvoIsLUTNotifierComplete(pDispEvo, apiHead)) { // If the notifier is still pending, then the previous update is still // pending and further LUT changes should continue to go into the third // buffer. Reschedule the timer for another 10 ms. @@ -7499,10 +8360,14 @@ void nvEvoSetLut(NVDispEvoPtr pDispEvo, NvU32 apiHead, NvBool kickoff, // update is complete, or if we need to guarantee that this update // is synchronous. NvBool previousUpdateComplete = - pDevEvo->hal->IsCompNotifierComplete(pDispEvo, - LUTNotifierForApiHead(apiHead)); + nvEvoIsLUTNotifierComplete(pDispEvo, apiHead); if (!waitForPreviousUpdate || previousUpdateComplete || pParams->synchronous) { + + if (!previousUpdateComplete) { + nvEvoWaitForLUTNotifier(pDispEvo, apiHead); + } + // Kick off an update now. EvoIncrementCurrentLutIndex(pDispEvo, apiHead, baseLutEnabled, outputLutEnabled); @@ -7512,8 +8377,7 @@ void nvEvoSetLut(NVDispEvoPtr pDispEvo, NvU32 apiHead, NvBool kickoff, if (pParams->synchronous && pDevEvo->lut.apiHead[apiHead].disp[dispIndex].waitForPreviousUpdate) { - pDevEvo->hal->WaitForCompNotifier(pDispEvo, - LUTNotifierForApiHead(apiHead)); + nvEvoWaitForLUTNotifier(pDispEvo, apiHead); pDevEvo->lut.apiHead[apiHead].disp[dispIndex].waitForPreviousUpdate = FALSE; } @@ -7979,7 +8843,7 @@ static NvBool EvoWaitForLock(const NVDevEvoRec *pDevEvo, const NvU32 sd, break; } - if (nvExceedsTimeoutUSec(pStartTime, LOCK_TIMEOUT)) { + if (nvExceedsTimeoutUSec(pDevEvo, pStartTime, LOCK_TIMEOUT)) { nvEvoLogDev(pDevEvo, EVO_LOG_ERROR, "SLI lock timeout exceeded (type %d)", type); return FALSE; @@ -8059,12 +8923,12 @@ NvBool nvReadCRC32Evo(NVDispEvoPtr pDispEvo, NvU32 head, return FALSE; } - // Bind the CRC32 notifier ctxDma - ret = nvRmEvoBindDispContextDMA(pDevEvo, pDevEvo->core, dma->ctxHandle); + // Bind the CRC32 notifier surface descriptor + ret = pDevEvo->hal->BindSurfaceDescriptor(pDevEvo, pDevEvo->core, &dma->surfaceDesc); if (ret != NVOS_STATUS_SUCCESS) { nvEvoLogDevDebug(pDevEvo, EVO_LOG_ERROR, - "Failed to bind display engine CRC32 notify context " - "DMA: 0x%x (%s)", ret, nvstatusToString(ret)); + "Failed to bind display engine CRC32 notify surface descriptor " + ": 0x%x (%s)", ret, nvstatusToString(ret)); res = FALSE; goto done; } @@ -8189,7 +9053,7 @@ NvBool nvEvoPollForNoMethodPending(NVDevEvoPtr pDevEvo, break; } - if (nvExceedsTimeoutUSec(pStartTime, timeout)) { + if (nvExceedsTimeoutUSec(pDevEvo, pStartTime, timeout)) { return FALSE; } @@ -8379,60 +9243,6 @@ void nvDPSerializerPostSetMode(NVDispEvoPtr pDispEvo, } } -NvBool nvIsHDRCapableHead(const NVDispEvoRec *pDispEvo, - NvU32 apiHead) -{ - const NVDpyEvoRec *pDpyEvo; - NvU32 primaryHwHead = nvGetPrimaryHwHead(pDispEvo, apiHead); - NvU32 activeDpyCount = 0; - - if (primaryHwHead != NV_INVALID_HEAD) { - const NVDispHeadStateEvoRec *pHeadState = - &pDispEvo->headState[primaryHwHead]; - const NVConnectorEvoRec *pConnectorEvo = pHeadState->pConnectorEvo; - - if (pConnectorEvo == NULL) { - return FALSE; - } - - // XXX HDR TODO: Currently only DP is supported, not HDMI. - if (!nvConnectorUsesDPLib(pConnectorEvo)) { - return FALSE; - } - } else { - return FALSE; - } - - FOR_ALL_EVO_DPYS(pDpyEvo, - pDispEvo->apiHeadState[apiHead].activeDpys, - pDispEvo) { - const NVT_EDID_INFO *pInfo = &pDpyEvo->parsedEdid.info; - const NVT_HDR_STATIC_METADATA *pHdrInfo = - &pInfo->hdr_static_metadata_info; - - if (!pDpyEvo->parsedEdid.valid) { - return FALSE; - } - - // Sink should support ST2084 EOTF. - if (!pHdrInfo->supported_eotf.smpte_st_2084_eotf) { - return FALSE; - } - - /* - * Sink should support static metadata type1. Nvtiming sets - * static_metadata_type to 1 if the sink supports static metadata type1. - */ - if (pHdrInfo->static_metadata_type != 1) { - return FALSE; - } - - activeDpyCount++; - } - - return (activeDpyCount > 0); -} - NvU32 nvGetHDRSrcMaxLum(const NVFlipChannelEvoHwState *pHwState) { if (!pHwState->hdrStaticMetadata.enabled) { @@ -8455,13 +9265,11 @@ NvBool nvNeedsTmoLut(NVDevEvoPtr pDevEvo, const NvU32 win = NV_EVO_CHANNEL_MASK_WINDOW_NUMBER(pChannel->channelMask); const NvU32 head = pDevEvo->headForWindow[win]; const NvU32 sdMask = nvPeekEvoSubDevMask(pDevEvo); - const NvU32 sd = (sdMask == 0) ? 0 : __builtin_ffs(sdMask) - 1; + const NvU32 sd = (sdMask == 0) ? 0 : nv_ffs(sdMask) - 1; const NVDispHeadStateEvoRec *pHeadState = &pDevEvo->pDispEvo[sd]->headState[head]; -#if defined(DEBUG) const NVEvoWindowCaps *pWinCaps = &pDevEvo->gpus[sd].capabilities.window[pChannel->instance]; -#endif // Don't tone map if flipped to NULL. if (!pHwState->pSurfaceEvo[NVKMS_LEFT]) { @@ -8474,14 +9282,16 @@ NvBool nvNeedsTmoLut(NVDevEvoPtr pDevEvo, return FALSE; } - // Don't tone map if output isn't HDR. + // Don't tone map if HDR infoframe isn't enabled // XXX HDR TODO: Support tone mapping HDR surfaces to SDR - if (pHeadState->hdr.outputState != NVKMS_HDR_OUTPUT_STATE_HDR) { + if (pHeadState->hdrInfoFrame.state != NVKMS_HDR_INFOFRAME_STATE_ENABLED) { return FALSE; } - // Don't tone map if TMO not present, implied by NVKMS_HDR_OUTPUT_STATE_HDR. - nvAssert(pWinCaps->tmoPresent); + // Don't tone map if TMO not present + if (!pWinCaps->tmoPresent) { + return FALSE; + } // Don't tone map if source or target max luminance is unspecified. if ((srcMaxLum == 0) || (targetMaxCLL == 0)) { @@ -8586,6 +9396,7 @@ void nvEvoEnableMergeModePreModeset(NVDispEvoRec *pDispEvo, nvAssert((pHC->serverLock == NV_EVO_NO_LOCK) && (pHC->clientLock == NV_EVO_NO_LOCK)); + pHC->mergeMode = TRUE; if (head == primaryHead) { pHC->serverLock = NV_EVO_RASTER_LOCK; pHC->serverLockPin = NV_EVO_LOCK_PIN_INTERNAL(primaryHead); @@ -8672,6 +9483,7 @@ void nvEvoDisableMergeMode(NVDispEvoRec *pDispEvo, pDevEvo->hal->SetMergeMode(pDispEvo, head, pHeadState->mergeMode, pUpdateState); + pHC->mergeMode = FALSE; pHC->serverLock = NV_EVO_NO_LOCK; pHC->serverLockPin = NV_EVO_LOCK_PIN_INTERNAL(0); pHC->clientLock = NV_EVO_NO_LOCK; diff --git a/src/nvidia-modeset/src/nvkms-evo2.c b/src/nvidia-modeset/src/nvkms-evo2.c index 3642c5384a..7a9de9abdd 100644 --- a/src/nvidia-modeset/src/nvkms-evo2.c +++ b/src/nvidia-modeset/src/nvkms-evo2.c @@ -33,6 +33,7 @@ #include "nvkms-evo.h" #include "nvkms-evo1.h" +#include "nvkms-ctxdma.h" #include @@ -918,7 +919,7 @@ static void EvoSetNotifierMethods90(NVDevEvoRec *pDevEvo, DRF_NUM(917D, _SET_CONTEXT_DMA_NOTIFIER, _HANDLE, - pDevEvo->core->notifiersDma[sd].ctxHandle)); + pDevEvo->core->notifiersDma[sd].surfaceDesc.ctxDmaHandle)); nvPopEvoSubDevMask(pDevEvo); } } @@ -1327,7 +1328,7 @@ static void EvoSetSurface(NVDevEvoPtr pDevEvo, return; } - nvAssert(pSurfaceEvo->planes[0].ctxDma); + nvAssert(pSurfaceEvo->planes[0].surfaceDesc.ctxDmaHandle); // XXX[AGP]: These methods are sequential, but sending them with a single // count=7 method header sometimes causes EVO to throw an IsoViolation @@ -1354,7 +1355,7 @@ static void EvoSetSurface(NVDevEvoPtr pDevEvo, DRF_DEF(917D, _HEAD_SET_PARAMS, _GAMMA, _LINEAR)); nvDmaSetStartEvoMethod(pChannel, NV917D_HEAD_SET_CONTEXT_DMAS_ISO(head), 1); - nvDmaSetEvoMethodData(pChannel, pSurfaceEvo->planes[0].ctxDma); + nvDmaSetEvoMethodData(pChannel, pSurfaceEvo->planes[0].surfaceDesc.ctxDmaHandle); /* NULL => don't change the CSC. */ if (pCscMatrix) { @@ -1382,7 +1383,7 @@ EvoPushSetCoreSurfaceMethodsForOneSd(NVDevEvoRec *pDevEvo, NVLutSurfaceEvoPtr pCurLutSurfEvo = pHeadState->lut.pCurrSurface; NvU32 lutCtxdma = pCurLutSurfEvo != NULL ? - pCurLutSurfEvo->dispCtxDma : 0x0; + pCurLutSurfEvo->surfaceDesc.ctxDmaHandle : 0x0; if (pSurfaceEvo == NULL || pCurLutSurfEvo == NULL) { enableOutputLut = FALSE; @@ -1451,7 +1452,7 @@ FlipBase90(NVDevEvoPtr pDevEvo, NV917C_SET_NOTIFIER_CONTROL_MODE_WRITE, value); nvDmaSetStartEvoMethod(pChannel, NV917C_SET_CONTEXT_DMA_NOTIFIER, 1); - nvDmaSetEvoMethodData(pChannel, pNIso->pSurfaceEvo->planes[0].ctxDma); + nvDmaSetEvoMethodData(pChannel, pNIso->pSurfaceEvo->planes[0].surfaceDesc.ctxDmaHandle); nvDmaSetStartEvoMethod(pChannel, NV917C_SET_NOTIFIER_CONTROL, 1); nvDmaSetEvoMethodData(pChannel, value); @@ -1490,7 +1491,7 @@ FlipBase90(NVDevEvoPtr pDevEvo, pNIso->offsetInWords, value); nvDmaSetStartEvoMethod(pChannel, NV917C_SET_CONTEXT_DMA_SEMAPHORE, 1); - nvDmaSetEvoMethodData(pChannel, pNIso->pSurfaceEvo->planes[0].ctxDma); + nvDmaSetEvoMethodData(pChannel, pNIso->pSurfaceEvo->planes[0].surfaceDesc.ctxDmaHandle); nvDmaSetStartEvoMethod(pChannel, NV917C_SET_SEMAPHORE_ACQUIRE, 1); nvDmaSetEvoMethodData(pChannel, @@ -1589,7 +1590,7 @@ FlipBase90(NVDevEvoPtr pDevEvo, NvU64 offset = 0; if (pHwState->pSurfaceEvo[eye]) { - ctxdma = pHwState->pSurfaceEvo[eye]->planes[0].ctxDma; + ctxdma = pHwState->pSurfaceEvo[eye]->planes[0].surfaceDesc.ctxDmaHandle; offset = pHwState->pSurfaceEvo[eye]->planes[0].offset; } @@ -1677,7 +1678,7 @@ FlipOverlay90(NVDevEvoPtr pDevEvo, if (pSurfaceEvo != NULL) { pDevEvo->pSubDevices[sd]->overlayContextDmaIso[head] = - pSurfaceEvo->planes[0].ctxDma; + pSurfaceEvo->planes[0].surfaceDesc.ctxDmaHandle; pDevEvo->pSubDevices[sd]->overlaySurfFormat[head] = pSurfaceEvo->format; } else { @@ -1716,7 +1717,7 @@ FlipOverlay90(NVDevEvoPtr pDevEvo, NV917E_SET_NOTIFIER_CONTROL_MODE_WRITE, value); nvDmaSetStartEvoMethod(pChannel, NV917E_SET_CONTEXT_DMA_NOTIFIER, 1); - nvDmaSetEvoMethodData(pChannel, pNIso->pSurfaceEvo->planes[0].ctxDma); + nvDmaSetEvoMethodData(pChannel, pNIso->pSurfaceEvo->planes[0].surfaceDesc.ctxDmaHandle); nvDmaSetStartEvoMethod(pChannel, NV917E_SET_NOTIFIER_CONTROL, 1); nvDmaSetEvoMethodData(pChannel, value); @@ -1750,7 +1751,7 @@ FlipOverlay90(NVDevEvoPtr pDevEvo, pNIso->offsetInWords, value); nvDmaSetStartEvoMethod(pChannel, NV917E_SET_CONTEXT_DMA_SEMAPHORE, 1); - nvDmaSetEvoMethodData(pChannel, pNIso->pSurfaceEvo->planes[0].ctxDma); + nvDmaSetEvoMethodData(pChannel, pNIso->pSurfaceEvo->planes[0].surfaceDesc.ctxDmaHandle); nvDmaSetStartEvoMethod(pChannel, NV917E_SET_SEMAPHORE_ACQUIRE, 1); nvDmaSetEvoMethodData(pChannel, @@ -1794,7 +1795,7 @@ FlipOverlay90(NVDevEvoPtr pDevEvo, return; } - nvAssert(pSurfaceEvo->planes[0].ctxDma); + nvAssert(pSurfaceEvo->planes[0].surfaceDesc.ctxDmaHandle); nvDmaSetStartEvoMethod(pChannel, NV917E_SET_SIZE_IN, 1); nvDmaSetEvoMethodData(pChannel, @@ -1828,7 +1829,7 @@ FlipOverlay90(NVDevEvoPtr pDevEvo, SetCscMatrix(pChannel, NV917E_SET_CSC_RED2RED, &pHwState->cscMatrix, 0); nvDmaSetStartEvoMethod(pChannel, NV917E_SET_CONTEXT_DMAS_ISO(NVKMS_LEFT), 1); - nvDmaSetEvoMethodData(pChannel, pSurfaceEvo->planes[0].ctxDma); + nvDmaSetEvoMethodData(pChannel, pSurfaceEvo->planes[0].surfaceDesc.ctxDmaHandle); nvAssert(pHwState->inputLut.pLutSurfaceEvo == NULL); } @@ -2484,7 +2485,7 @@ static void EvoSetLUTContextDma90(const NVDispEvoRec *pDispEvo, const NvBool coreChannelCtxDmaNonNull = pDevEvo->pSubDevices[sd]->pCoreChannelSurface[head] != NULL; - const NvU32 ctxdma = (pLutSurfEvo != NULL) ? pLutSurfEvo->dispCtxDma : 0; + const NvU32 ctxdma = (pLutSurfEvo != NULL) ? pLutSurfEvo->surfaceDesc.ctxDmaHandle : 0; /* * If the core channel doesn't have a scanout surface set, then setting the @@ -2973,7 +2974,7 @@ static void EvoSetCursorImage(NVDevEvoPtr pDevEvo, const int head, const struct NvKmsCompositionParams *pCursorCompParams) { NVEvoChannelPtr pChannel = pDevEvo->core; - const NvU32 ctxdma = pSurfaceEvo ? pSurfaceEvo->planes[0].ctxDma : 0; + const NvU32 ctxdma = pSurfaceEvo ? pSurfaceEvo->planes[0].surfaceDesc.ctxDmaHandle : 0; const NvU64 offset = pSurfaceEvo ? pSurfaceEvo->planes[0].offset : 0; NvU32 headSetControlCursorValue = 0; NvBool ret; @@ -3223,7 +3224,7 @@ static NvBool ForceIdleBaseChannel( stopParams.base.subdeviceIndex = sd; stopParams.channelInstance = pChannel->instance; stopParams.notifyMode = NV5070_CTRL_CMD_STOP_BASE_NOTIFY_MODE_WRITE; - stopParams.hNotifierCtxDma = pChannel->notifiersDma[sd].ctxHandle; + stopParams.hNotifierCtxDma = pChannel->notifiersDma[sd].surfaceDesc.ctxDmaHandle; stopParams.offset = 0; stopParams.hEvent = 0; @@ -3241,7 +3242,7 @@ static NvBool ForceIdleBaseChannel( break; } - if (nvExceedsTimeoutUSec(&startTime, timeout)) { + if (nvExceedsTimeoutUSec(pDevEvo, &startTime, timeout)) { nvAssert(!"STOP_BASE timed out"); return FALSE; } @@ -3271,7 +3272,7 @@ static NvBool ForceIdleOverlayChannel( stopParams.base.subdeviceIndex = sd; stopParams.channelInstance = pChannel->instance; stopParams.notifyMode = NV5070_CTRL_CMD_STOP_OVERLAY_NOTIFY_MODE_WRITE; - stopParams.hNotifierCtxDma = pChannel->notifiersDma[sd].ctxHandle; + stopParams.hNotifierCtxDma = pChannel->notifiersDma[sd].surfaceDesc.ctxDmaHandle; stopParams.offset = 0; stopParams.hEvent = 0; @@ -3289,7 +3290,7 @@ static NvBool ForceIdleOverlayChannel( break; } - if (nvExceedsTimeoutUSec(&startTime, timeout)) { + if (nvExceedsTimeoutUSec(pDevEvo, &startTime, timeout)) { nvAssert(!"STOP_OVERLAY timed out"); return FALSE; } @@ -3397,7 +3398,7 @@ static void EvoStartHeadCRC32Capture90(NVDevEvoPtr pDevEvo, NVEvoUpdateState *updateState) { NVEvoChannelPtr pChannel = pDevEvo->core; - NvU32 dmaCtx = pDma->ctxHandle; + NvU32 dmaCtx = pDma->surfaceDesc.ctxDmaHandle; NvU32 orOutput = 0; /* These method should only apply to a single pDpy */ @@ -3545,7 +3546,8 @@ static NvBool EvoQueryHeadCRC32_90(NVDevEvoPtr pDevEvo, } }; - if (!nvEvoWaitForCRC32Notifier(pCRC32Notifier, + if (!nvEvoWaitForCRC32Notifier(pDevEvo, + pCRC32Notifier, NV917D_NOTIFIER_CRC_1_STATUS_0, DRF_BASE(NV917D_NOTIFIER_CRC_1_STATUS_0_DONE), DRF_EXTENT(NV917D_NOTIFIER_CRC_1_STATUS_0_DONE), @@ -3806,6 +3808,30 @@ static void EvoResetChannelAccelerators91(NVDevEvoPtr pDevEvo, } } +static NvU32 EvoAllocSurfaceDescriptor90( + NVDevEvoPtr pDevEvo, NVSurfaceDescriptor *pSurfaceDesc, + NvU32 memoryHandle, NvU32 localCtxDmaFlags, + NvU64 limit) +{ + return nvCtxDmaAlloc(pDevEvo, &pSurfaceDesc->ctxDmaHandle, + memoryHandle, + localCtxDmaFlags, limit); +} + +static void EvoFreeSurfaceDescriptor90( + NVDevEvoPtr pDevEvo, + NvU32 deviceHandle, + NVSurfaceDescriptor *pSurfaceDesc) +{ + nvCtxDmaFree(pDevEvo, deviceHandle, &pSurfaceDesc->ctxDmaHandle); +} + +static NvU32 EvoBindSurfaceDescriptor90( + NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChannel, NVSurfaceDescriptor *pSurfaceDesc) +{ + return nvCtxDmaBind(pDevEvo, pChannel, pSurfaceDesc->ctxDmaHandle); +} + NVEvoHAL nvEvo94 = { EvoSetRasterParams91, /* SetRasterParams */ EvoSetProcAmp90, /* SetProcAmp */ @@ -3860,13 +3886,22 @@ NVEvoHAL nvEvo94 = { EvoComputeWindowScalingTaps91, /* ComputeWindowScalingTaps */ NULL, /* GetWindowScalingCaps */ NULL, /* SetMergeMode */ + EvoAllocSurfaceDescriptor90, /* AllocSurfaceDescriptor */ + EvoFreeSurfaceDescriptor90, /* FreeSurfaceDescriptor */ + EvoBindSurfaceDescriptor90, /* BindSurfaceDescriptor */ + NULL, /* SetTmoLutSurfaceAddress */ + NULL, /* SetILUTSurfaceAddress */ + NULL, /* SetISOSurfaceAddress */ + NULL, /* SetCoreNotifierSurfaceAddressAndControl */ + NULL, /* SetWinNotifierSurfaceAddressAndControl */ + NULL, /* SetSemaphoreSurfaceAddressAndControl */ + NULL, /* SetAcqSemaphoreSurfaceAddressAndControl */ { /* caps */ FALSE, /* supportsNonInterlockedUsageBoundsUpdate */ FALSE, /* supportsDisplayRate */ TRUE, /* supportsFlipLockRGStatus */ FALSE, /* needDefaultLutSurface */ FALSE, /* hasUnorm10OLUT */ - TRUE, /* supportsDigitalVibrance */ TRUE, /* supportsImageSharpening */ FALSE, /* supportsHDMIVRR */ TRUE, /* supportsCoreChannelSurface */ @@ -3878,6 +3913,7 @@ NVEvoHAL nvEvo94 = { FALSE, /* supportsVblankSyncObjects */ TRUE, /* requiresScalingTapsInBothDimensions */ FALSE, /* supportsMergeMode */ + FALSE, /* supportsHDMI10BPC */ NV_EVO2_SUPPORTED_DITHERING_MODES, /* supportedDitheringModes */ sizeof(NV5070_CTRL_CMD_IS_MODE_POSSIBLE_PARAMS), /* impStructSize */ NV_EVO_SCALER_1TAP, /* minScalerTaps */ diff --git a/src/nvidia-modeset/src/nvkms-evo3.c b/src/nvidia-modeset/src/nvkms-evo3.c index e4bc5d634b..73b3383c35 100644 --- a/src/nvidia-modeset/src/nvkms-evo3.c +++ b/src/nvidia-modeset/src/nvkms-evo3.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2010-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -33,10 +33,12 @@ #include "nvkms-softfloat.h" #include "nvkms-evo.h" #include "nvkms-evo1.h" +#include "nvkms-evo3.h" #include "nvkms-prealloc.h" #include "nv-float.h" #include "nvkms-dpy.h" #include "nvkms-vrr.h" +#include "nvkms-ctxdma.h" #include @@ -65,20 +67,46 @@ #define NV_EVO3_X_EMULATED_SURFACE_MEMORY_FORMATS_C5 \ (NVBIT64(NvKmsSurfaceMemoryFormatRF16GF16BF16XF16)) -#define NV_EVO3_X_EMULATED_SURFACE_MEMORY_FORMATS_C6 \ - (NVBIT64(NvKmsSurfaceMemoryFormatRF16GF16BF16XF16) | \ - NVBIT64(NvKmsSurfaceMemoryFormatX2B10G10R10)) - /** Number of CRCs supported by hardware on NVC37D hardware (SF/SOR, Comp, RG) */ #define NV_EVO3_NUM_CRC_FIELDS 3 /** Number of CRCs supported by hardware on NVC37D hardware SF/SOR, Comp, RG Ovf and Count */ #define NV_EVO3_NUM_CRC_FLAGS 4 -static NvBool EvoIsChannelIdleC3(NVDevEvoPtr pDevEvo, - NVEvoChannelPtr pChan, - NvU32 sd, - NvBool *result); +enum FMTCoeffType +{ + FMT_COEFF_TYPE_IDENTITY = 0, + + FMT_COEFF_TYPE_REC709_YUV_8BPC_LTD_TO_RGB_16BPC_FULL, + FMT_COEFF_TYPE_REC709_YUV_8BPC_FULL_TO_RGB_16BPC_FULL, + FMT_COEFF_TYPE_REC709_YUV_10BPC_LTD_TO_RGB_16BPC_FULL, + FMT_COEFF_TYPE_REC709_YUV_10BPC_FULL_TO_RGB_16BPC_FULL, + FMT_COEFF_TYPE_REC709_YUV_12BPC_LTD_TO_RGB_16BPC_FULL, + FMT_COEFF_TYPE_REC709_YUV_12BPC_FULL_TO_RGB_16BPC_FULL, + + // FMT is always identity for RGB to avoid possible calculation error. + + // must be the last entry + FMT_COEFF_TYPE_MAX +}; + +static const NvU32 FMTMatrix[FMT_COEFF_TYPE_MAX][12] = +{ + // FMT_COEFF_TYPE_IDENTITY + { 0x10000, 0, 0, 0, 0, 0x10000, 0, 0, 0, 0, 0x10000, 0 }, + // FMT_COEFF_TYPE_REC709_YUV_8BPC_LTD_TO_RGB_16BPC_FULL + { 0x1CCB7, 0x12B3C, 0, 0x1F06F1, 0x1F770C, 0x12B3C, 0x1FC933, 0x4D2D, 0, 0x12B3C, 0x21EDD, 0x1EDDDE }, + // FMT_COEFF_TYPE_REC709_YUV_8BPC_FULL_TO_RGB_16BPC_FULL + { 0x194B4, 0x100FD, 0, 0x1F373A, 0x1F87B3, 0x100FD, 0x1FCFDC, 0x5390, 0, 0x100FD, 0x1DCDE, 0x1F136E }, + // FMT_COEFF_TYPE_REC709_YUV_10BPC_LTD_TO_RGB_16BPC_FULL + { 0x1CCB7, 0x12B3C, 0, 0x1F06F1, 0x1F770C, 0x12B3C, 0x1FC933, 0x4D2D, 0, 0x12B3C, 0x21EDD, 0x1EDDDE }, + // FMT_COEFF_TYPE_REC709_YUV_10BPC_FULL_TO_RGB_16BPC_FULL + { 0x19385, 0x1003C, 0, 0x1F36A3, 0x1F880D, 0x1003C, 0x1FD000, 0x53CF, 0, 0x1003C, 0x1DB78, 0x1F12BB }, + // FMT_COEFF_TYPE_REC709_YUV_12BPC_LTD_TO_RGB_16BPC_FULL + { 0x1CCB7, 0x12B3C, 0, 0x1F06F1, 0x1F770C, 0x12B3C, 0x1FC933, 0x4D2D, 0, 0x12B3C, 0x21EDD, 0x1EDDDE }, + // FMT_COEFF_TYPE_REC709_YUV_12BPC_FULL_TO_RGB_16BPC_FULL + { 0x19339, 0x1000C, 0, 0x1F367D, 0x1F8823, 0x1000C, 0x1FD009, 0x53DF, 0, 0x1000C, 0x1DB1F, 0x1F128E }, +}; static void SetCsc00MatrixC5(NVEvoChannelPtr pChannel, const struct NvKmsCscMatrix *matrix); @@ -116,19 +144,6 @@ ct_assert(NV_EVO_LOCK_PIN_0 > /* nvdisplay has a maximum of 2 eyes and 3 planes per surface */ ct_assert((NVKMS_MAX_EYES * NVKMS_MAX_PLANES_PER_SURFACE) == 6); -#define NV_EVO3_SUPPORTED_DITHERING_MODES \ - ((1 << NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING_MODE_AUTO) | \ - (1 << NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING_MODE_DYNAMIC_2X2) | \ - (1 << NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING_MODE_STATIC_2X2) | \ - (1 << NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING_MODE_TEMPORAL)) - -#define NV_EVO3_SUPPORTED_CURSOR_COMP_BLEND_MODES \ - ((1 << NVKMS_COMPOSITION_BLENDING_MODE_OPAQUE) | \ - (1 << NVKMS_COMPOSITION_BLENDING_MODE_NON_PREMULT_ALPHA) | \ - (1 << NVKMS_COMPOSITION_BLENDING_MODE_PREMULT_ALPHA) | \ - (1 << NVKMS_COMPOSITION_BLENDING_MODE_NON_PREMULT_SURFACE_ALPHA) | \ - (1 << NVKMS_COMPOSITION_BLENDING_MODE_PREMULT_SURFACE_ALPHA)) - /* Windows support all composition modes. */ #define NV_EVO3_SUPPORTED_WINDOW_COMP_BLEND_MODES \ ((1 << NVKMS_COMPOSITION_BLENDING_MODE_OPAQUE) | \ @@ -143,10 +158,6 @@ ct_assert((NVKMS_MAX_EYES * NVKMS_MAX_PLANES_PER_SURFACE) == 6); DRF_DEF(C37D, _WINDOW_SET_WINDOW_USAGE_BOUNDS, _INPUT_SCALER_TAPS, _TAPS_2) | \ DRF_DEF(C37D, _WINDOW_SET_WINDOW_USAGE_BOUNDS, _UPSCALING_ALLOWED, _FALSE)) -#define NV_EVO3_DEFAULT_WINDOW_USAGE_BOUNDS_C5 \ - (DRF_DEF(C57D, _WINDOW_SET_WINDOW_USAGE_BOUNDS, _ILUT_ALLOWED, _TRUE) | \ - DRF_DEF(C57D, _WINDOW_SET_WINDOW_USAGE_BOUNDS, _TMO_LUT_ALLOWED, _TRUE)) - static inline NvU8 EyeAndPlaneToCtxDmaIdx(const NvU8 eye, const NvU8 plane) { /* @@ -180,19 +191,6 @@ static void InitChannelCapsC3(NVDevEvoPtr pDevEvo, } } -// HW supports ratio = 1, 2 (downscaling), 4 (downscaling) -#define NUM_SCALER_RATIOS 3 - -// There are 16 phases stored in matrix, but HW can derive the values of phase -// +16 and -16 from phase 0. Therefore, SW loads phase +16/-16 in phase 0 coeff -// values. -// coeff values in phase 0. -#define NUM_TAPS5_COEFF_PHASES 16 - -// There are 5 coefficient values per phase (or matrix row), but SW doesn't need -// to upload c2. So, the value here is set to 4. -#define NUM_TAPS5_COEFF_VALUES 4 - // The coefficient values are obtained from bug 1953108 comment 10 // Per MFS: However since all 5 coefficients have to add up to 1.0, only 4 need to be specified, and // HW can derive the missing one. The center coefficient is the one that is left out, so @@ -208,7 +206,7 @@ static void InitChannelCapsC3(NVDevEvoPtr pDevEvo, // Therefore, based on MFS above, the matrix below contains the values loaded to HW. // Real Phase 0 is commented for easy reference. // Also, phase 16 values (last row) are commented, but its C0,C1 values are loaded in row 0/phase 0. -static const NvU32 scalerTaps5Coeff[NUM_SCALER_RATIOS][NUM_TAPS5_COEFF_PHASES][NUM_TAPS5_COEFF_VALUES] = +const NvU32 scalerTaps5Coeff[NUM_SCALER_RATIOS][NUM_TAPS5_COEFF_PHASES][NUM_TAPS5_COEFF_VALUES] = { // ratio = 1 {{ 0 , 0 , -16 , 144}, // real phase 0:{ 0, 0, /*256,*/ 0, 0 }, @@ -269,7 +267,7 @@ static const NvU32 scalerTaps5Coeff[NUM_SCALER_RATIOS][NUM_TAPS5_COEFF_PHASES][N } }; -static void InitScalerCoefficientsPrecomp5(NVEvoChannelPtr pChannel, +void nvInitScalerCoefficientsPrecomp5(NVEvoChannelPtr pChannel, NvU32 coeff, NvU32 index) { nvDmaSetStartEvoMethod(pChannel, NVC57E_SET_INPUT_SCALER_COEFF_VALUE, 1); @@ -318,7 +316,7 @@ static void InitTaps5ScalerCoefficientsC5(NVDevEvoPtr pDevEvo, NvU32 index = ratio << 6 | phase << 2 | coeffIdx; if (isPrecomp) { - InitScalerCoefficientsPrecomp5(pChannel, coeff, index); + nvInitScalerCoefficientsPrecomp5(pChannel, coeff, index); } else { InitScalerCoefficientsPostcomp5(pDevEvo, pChannel, coeff, index); @@ -641,45 +639,34 @@ static float64_t P(float64_t B, float64_t KS, float64_t maxLum) * curve. Messing with nonlinearity and remapping in the SDR portion of the * curve results in bad looking PC desktop and game content. * + * Lmax = InvPQEotf(targetMaxLum/10000.0) + * Lw = InvPQEotf(srcMaxLum/10000.0) + * maxLumRatio = Lmax/Lw + * KS = 1.5*maxLumRatio - 0.5 + * KSEqualsOne = (KS == 1.0) + * * XXX HDR TODO: Remap blacks and implement toe section for video content? */ -static NvU16 TmoLutEntry(NvU32 i, NvU32 targetMaxLum, NvU32 srcMaxLum) +static NvU16 TmoLutEntry(NvU32 i, + const float64_t Lmax, + const float64_t Lw, + const float64_t maxLumRatio, + const float64_t KS, + const NvBool KSEqualsOne) { const float64_t zero = {0x0000000000000000}; // 0.0 - const float64_t half = {0x3FE0000000000000}; // 0.5 - const float64_t one = {0x3FF0000000000000}; // 1.0 - const float64_t oneHalf = {0x3FF8000000000000}; // 1.5 - const float64_t tenThousand = {0x40C3880000000000}; // 10000.0 const float64_t maxIntensity = {0x40CFFF8000000000}; // 16383.0 float64_t outputF; float64_t inputF = f64_div(ui32_to_f64(i), ui32_to_f64(TMO_LUT_NUM_ENTRIES - 1)); - float64_t targetMaxLumF = ui32_to_f64(targetMaxLum); - float64_t srcMaxLumF = ui32_to_f64(srcMaxLum); - - // Normalize luminance to 10,000 nits - float64_t Lw = f64_div(srcMaxLumF, tenThousand); - float64_t Lmax = f64_div(targetMaxLumF, tenThousand); - - float64_t maxLumRatio; - float64_t KS; float64_t E1; float64_t E2; - nvAssert(srcMaxLum >= targetMaxLum); - - Lw = PQEotf(Lw, TRUE); - Lmax = PQEotf(Lmax, TRUE); - - maxLumRatio = f64_div(Lmax, Lw); - - KS = f64_sub(f64_mul(oneHalf, maxLumRatio), half); - E1 = f64_div(inputF, Lw); - if (f64_lt(E1, KS) || f64_eq(KS, one)) { + if (KSEqualsOne || f64_lt(E1, KS)) { E2 = E1; } else { E2 = P(E1, KS, maxLumRatio); @@ -700,6 +687,29 @@ static void InitializeTmoLut(const NVEvoChannelPtr pChannel, NvU64 vssHead = 0; NvU32 lutEntryCounter = 0, i; + // Precalculate constants for TmoLutEntry(). + const float64_t tenThousand = {0x40C3880000000000}; // 10000.0 + const float64_t one = {0x3FF0000000000000}; // 1.0 + const float64_t half = {0x3FE0000000000000}; // 0.5 + const float64_t oneHalf = {0x3FF8000000000000}; // 1.5 + // Lmax = InvPQEotf(targetMaxLum/10,000) + const float64_t Lmax = + PQEotf(f64_div(ui32_to_f64(pChannel->tmoParams.targetMaxLums[sd]), + tenThousand), TRUE); + // Lw = InvPQEotf(srcMaxLum/10,000) + const float64_t Lw = + PQEotf(f64_div(ui32_to_f64(pChannel->tmoParams.srcMaxLum), + tenThousand), TRUE); + // maxLumRatio = Lmax/Lw + const float64_t maxLumRatio = f64_div(Lmax, Lw); + // KS = 1.5*maxLumRatio - 0.5 + const float64_t KS = f64_sub(f64_mul(oneHalf, maxLumRatio), half); + // KSEqualsOne = (KS == 1.0) + const NvBool KSEqualsOne = f64_eq(KS, one); + + nvAssert(pChannel->tmoParams.srcMaxLum >= + pChannel->tmoParams.targetMaxLums[sd]); + // VSS Header for (lutEntryCounter = 0; lutEntryCounter < NV_LUT_VSS_HEADER_SIZE; lutEntryCounter++) { vssHead = 0; @@ -714,9 +724,7 @@ static void InitializeTmoLut(const NVEvoChannelPtr pChannel, pData->base[i + NV_LUT_VSS_HEADER_SIZE].Red = pData->base[i + NV_LUT_VSS_HEADER_SIZE].Green = pData->base[i + NV_LUT_VSS_HEADER_SIZE].Blue = - TmoLutEntry(i, - pChannel->tmoParams.targetMaxLums[sd], - pChannel->tmoParams.srcMaxLum); + TmoLutEntry(i, Lmax, Lw, maxLumRatio, KS, KSEqualsOne); } // Copy the last entry for interpolation @@ -756,6 +764,22 @@ static NvBool UpdateTmoParams(NVEvoChannelPtr pChannel, return dirty; } +static void EvoSetTmoLutSurfaceAddressC5( + NVEvoChannelPtr pChannel, + const NVSurfaceDescriptor *pSurfaceDesc, + NvU32 offset) +{ + NvU32 ctxDmaHandle = pSurfaceDesc ? pSurfaceDesc->ctxDmaHandle : 0; + + nvDmaSetStartEvoMethod(pChannel, NVC57E_SET_CONTEXT_DMA_TMO_LUT, 1); + nvDmaSetEvoMethodData(pChannel, + DRF_NUM(C57E, _SET_CONTEXT_DMA_TMO_LUT, _HANDLE, ctxDmaHandle)); + + nvDmaSetStartEvoMethod(pChannel, NVC57E_SET_OFFSET_TMO_LUT, 1); + nvDmaSetEvoMethodData(pChannel, + DRF_NUM(C57E, _SET_OFFSET_TMO_LUT, _ORIGIN, offset >> 8)); +} + static void ConfigureTmoLut(NVDevEvoPtr pDevEvo, const NVFlipChannelEvoHwState *pHwState, NVEvoChannelPtr pChannel) @@ -763,7 +787,6 @@ static void ConfigureTmoLut(NVDevEvoPtr pDevEvo, NvU16 sd; const NvU32 win = NV_EVO_CHANNEL_MASK_WINDOW_NUMBER(pChannel->channelMask); const NvU32 head = pDevEvo->headForWindow[win]; - NvU32 ctxDma; const NvU32 offset = offsetof(NVEvoLutDataRec, base); const struct TmoLutSettings *tmoLutSettings; const NvU32 srcMaxLum = nvGetHDRSrcMaxLum(pHwState); @@ -774,7 +797,7 @@ static void ConfigureTmoLut(NVDevEvoPtr pDevEvo, const NVDispHeadStateEvoRec *pHeadState = &pDevEvo->pDispEvo[sd]->headState[head]; - targetMaxLums[sd] = pHeadState->hdr.staticMetadata.maxCLL; + targetMaxLums[sd] = pHeadState->hdrInfoFrame.staticMetadata.maxCLL; // If any head needs tone mapping, enable TMO for channel if (nvNeedsTmoLut(pDevEvo, pChannel, pHwState, @@ -789,10 +812,8 @@ static void ConfigureTmoLut(NVDevEvoPtr pDevEvo, } if (!pChannel->tmoParams.enabled) { - nvDmaSetStartEvoMethod(pChannel, NVC57E_SET_CONTEXT_DMA_TMO_LUT, 1); - nvDmaSetEvoMethodData(pChannel, - DRF_NUM(C57E, _SET_CONTEXT_DMA_TMO_LUT, _HANDLE, 0)); - + pDevEvo->hal->SetTmoLutSurfaceAddress(pChannel, + NULL /* pSurfaceDesc */, 0 /* offset */); return; } @@ -807,8 +828,6 @@ static void ConfigureTmoLut(NVDevEvoPtr pDevEvo, // XXX HDR TODO: Support other transfer functions tmoLutSettings = &TMO_LUT_SETTINGS_REC2020; - ctxDma = pHwState->tmoLut.pLutSurfaceEvo->dispCtxDma; - nvDmaSetStartEvoMethod(pChannel, NVC57E_SET_TMO_CONTROL, 1); nvDmaSetEvoMethodData(pChannel, DRF_NUM(C57E, _SET_TMO_CONTROL, _SIZE, @@ -816,14 +835,8 @@ static void ConfigureTmoLut(NVDevEvoPtr pDevEvo, DRF_DEF(C57E, _SET_TMO_CONTROL, _INTERPOLATE, _ENABLE) | DRF_NUM(C57E, _SET_TMO_CONTROL, _SAT_MODE, tmoLutSettings->satMode)); - nvDmaSetStartEvoMethod(pChannel, NVC57E_SET_OFFSET_TMO_LUT, 1); - nvDmaSetEvoMethodData(pChannel, - DRF_NUM(C57E, _SET_OFFSET_TMO_LUT, _ORIGIN, offset >> 8)); - - nvDmaSetStartEvoMethod(pChannel, NVC57E_SET_CONTEXT_DMA_TMO_LUT, 1); - nvDmaSetEvoMethodData(pChannel, - DRF_NUM(C57E, _SET_CONTEXT_DMA_TMO_LUT, _HANDLE, ctxDma)); - + pDevEvo->hal->SetTmoLutSurfaceAddress(pChannel, + &pHwState->tmoLut.pLutSurfaceEvo->surfaceDesc, offset); // Low Intensity @@ -894,7 +907,7 @@ static void ConfigureCsc1C5(NVDevEvoPtr pDevEvo, if (enable) { const NvU32 sdMask = nvPeekEvoSubDevMask(pDevEvo); - const NvU32 sd = (sdMask == 0) ? 0 : __builtin_ffs(sdMask) - 1; + const NvU32 sd = (sdMask == 0) ? 0 : nv_ffs(sdMask) - 1; const NVDispHeadStateEvoRec *pHeadState; /* @@ -905,9 +918,8 @@ static void ConfigureCsc1C5(NVDevEvoPtr pDevEvo, pHeadState = &pDevEvo->pDispEvo[sd]->headState[head]; - if (pHeadState->hdr.outputState == NVKMS_HDR_OUTPUT_STATE_HDR) { - // XXX HDR TODO: Support other transfer functions - nvAssert(pHeadState->tf == NVKMS_OUTPUT_TF_PQ); + // If postcomp is PQ, composite in Rec2020 + if (pHeadState->tf == NVKMS_OUTPUT_TF_PQ) { matrix = LMSToRec2020RGB; } else { matrix = LMSToRec709RGB; @@ -976,7 +988,7 @@ static void InitDesktopColorC5(NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChannel) } } -static void EvoInitChannel3(NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChannel) +void nvEvoInitChannel3(NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChannel) { InitChannelCapsC3(pDevEvo, pChannel); } @@ -987,7 +999,7 @@ static void EvoInitChannelC3(NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChannel) FLD_TEST_DRF64(_EVO, _CHANNEL_MASK, _CORE, _ENABLE, pChannel->channelMask); - EvoInitChannel3(pDevEvo, pChannel); + nvEvoInitChannel3(pDevEvo, pChannel); if (isCore) { InitDesktopColorC3(pDevEvo, pChannel); @@ -1002,7 +1014,7 @@ static void EvoInitChannelC5(NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChannel) const NvBool isWindow = ((pChannel->channelMask & NV_EVO_CHANNEL_MASK_WINDOW_ALL) != 0); - EvoInitChannel3(pDevEvo, pChannel); + nvEvoInitChannel3(pDevEvo, pChannel); if (isCore) { InitTaps5ScalerCoefficientsC5(pDevEvo, pChannel, FALSE); @@ -1028,40 +1040,52 @@ static void EvoInitChannelC5(NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChannel) } } -static const NvU32 IdentityFMTMatrix[12] = { - 0x00010000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00010000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00010000, 0x00000000 -}; - -/* - * TODO: The full set of FMT matrices needs to be generated for each RGB and YUV - * encoding. For now, I'm using the matrix below to convert all YUV input - * formats to pipe native. - */ -static const NvU32 YCbCrRec709_8bpcFMTMatrix[12] = { - 0x0001ccb7, 0x00012b3c, 0x00000000, 0x001f06f1, - 0x001f770c, 0x00012b3c, 0x001fc933, 0x00004d2d, - 0x00000000, 0x00012b3c, 0x00021edd, 0x001eddde -}; - static const NvU32* EvoGetFMTMatrixC5( - const enum NvKmsSurfaceMemoryFormat format) + const enum NvKmsSurfaceMemoryFormat format, + const NVFlipChannelEvoHwState *pHwState) { + const NvU32* retValue = NULL; const NvKmsSurfaceMemoryFormatInfo *pFormatInfo = nvKmsGetSurfaceMemoryFormatInfo(format); + // Choose FMT matrix based on input colorspace, bpc, and colorrange. if (pFormatInfo->isYUV) { - return YCbCrRec709_8bpcFMTMatrix; + NvBool specifiedFull = (pHwState->colorRange == NVKMS_INPUT_COLORRANGE_FULL); + if (pFormatInfo->yuv.depthPerComponent == 8) { + if (specifiedFull) { + retValue = FMTMatrix[FMT_COEFF_TYPE_REC709_YUV_8BPC_FULL_TO_RGB_16BPC_FULL]; + } else { + retValue = FMTMatrix[FMT_COEFF_TYPE_REC709_YUV_8BPC_LTD_TO_RGB_16BPC_FULL]; + } + } else if (pFormatInfo->yuv.depthPerComponent == 10) { + if (specifiedFull) { + retValue = FMTMatrix[FMT_COEFF_TYPE_REC709_YUV_10BPC_FULL_TO_RGB_16BPC_FULL]; + } else { + retValue = FMTMatrix[FMT_COEFF_TYPE_REC709_YUV_10BPC_LTD_TO_RGB_16BPC_FULL]; + } + } else if (pFormatInfo->yuv.depthPerComponent == 12) { + if (specifiedFull) { + retValue = FMTMatrix[FMT_COEFF_TYPE_REC709_YUV_12BPC_FULL_TO_RGB_16BPC_FULL]; + } else { + retValue = FMTMatrix[FMT_COEFF_TYPE_REC709_YUV_12BPC_LTD_TO_RGB_16BPC_FULL]; + } + } else { + // Unsupported bit depth, fail silently by defaulting to identity. + retValue = FMTMatrix[FMT_COEFF_TYPE_IDENTITY]; + } } else { - return IdentityFMTMatrix; + // All inputs with RGB colorspace receive an identity FMT. + retValue = FMTMatrix[FMT_COEFF_TYPE_IDENTITY]; } + + return retValue; } static void EvoSetFMTMatrixC5( - NVEvoChannelPtr pChannel, const enum NvKmsSurfaceMemoryFormat format) + NVEvoChannelPtr pChannel, const enum NvKmsSurfaceMemoryFormat format, + const NVFlipChannelEvoHwState *pHwState) { - const NvU32 *matrix = EvoGetFMTMatrixC5(format); + const NvU32 *matrix = EvoGetFMTMatrixC5(format, pHwState); NvU32 method = NVC57E_SET_FMT_COEFFICIENT_C00; int i; @@ -1073,7 +1097,7 @@ static void EvoSetFMTMatrixC5( } } -static void EvoInitDefaultLutC5(NVDevEvoPtr pDevEvo) +void nvEvoInitDefaultLutC5(NVDevEvoPtr pDevEvo) { NVLutSurfaceEvoPtr pLut = pDevEvo->lut.defaultLut; NvU16 sd; @@ -1139,13 +1163,13 @@ static void EvoInitWindowMapping3(NVDevEvoPtr pDevEvo, /* This core channel must be idle before reading state cache */ do { NvBool isIdle = NV_FALSE; - if (!EvoIsChannelIdleC3(pDevEvo, pChannel, sd, &isIdle)) { - nvEvoLogDevDebug(pDevEvo, EVO_LOG_ERROR, "EvoIsChannelIdleC3() failed!"); + if (!nvEvoIsChannelIdleC3(pDevEvo, pChannel, sd, &isIdle)) { + nvEvoLogDevDebug(pDevEvo, EVO_LOG_ERROR, "nvEvoIsChannelIdleC3() failed!"); } if (isIdle) { break; } - if (nvExceedsTimeoutUSec(&startTime, timeout)) { + if (nvExceedsTimeoutUSec(pDevEvo, &startTime, timeout)) { nvEvoLogDev(pDevEvo, EVO_LOG_ERROR, "Timed out waiting for core channel idle."); break; @@ -1195,7 +1219,7 @@ static void EvoInitWindowMappingC3(const NVDispEvoRec *pDispEvo, nvPopEvoSubDevMask(pDevEvo); } -static void EvoInitWindowMappingC5(const NVDispEvoRec *pDispEvo, +void nvEvoInitWindowMappingC5(const NVDispEvoRec *pDispEvo, NVEvoModesetUpdateState *pModesetUpdateState) { NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; @@ -1224,7 +1248,7 @@ static void EvoInitWindowMappingC5(const NVDispEvoRec *pDispEvo, nvPopEvoSubDevMask(pDevEvo); } -static NvBool ComputeMinFrameIdle( +NvBool nvComputeMinFrameIdle( const NVHwModeTimingsEvo *pTimings, NvU16 *pLeadingRasterLines, NvU16 *pTrailingRasterLines) @@ -1316,7 +1340,7 @@ static void EvoSetRasterParams3(NVDevEvoPtr pDevEvo, int head, DRF_NUM(C37D, _HEAD_SET_RASTER_BLANK_START, _X, pTimings->rasterBlankStart.x) | DRF_NUM(C37D, _HEAD_SET_RASTER_BLANK_START, _Y, pTimings->rasterBlankStart.y)); - ret = ComputeMinFrameIdle(pTimings, + ret = nvComputeMinFrameIdle(pTimings, &minFrameIdleLeadingRasterLines, &minFrameIdleTrailingRasterLines); if (!ret) { @@ -1562,11 +1586,12 @@ static const struct NvKmsCscMatrix RGBToLimitedRangeRGB = {{ { 0, 0, 0xdb04, 0x1000 }, }}; + /*! * Return the appropriate OCSC1 matrix for the requested color range and * colorimetry, or NULL if the OCSC1 should be disabled. */ -static const struct NvKmsCscMatrix* EvoGetOCsc1MatrixC5(const NVDispHeadStateEvoRec *pHeadState) +const struct NvKmsCscMatrix* nvEvoGetOCsc1MatrixC5(const NVDispHeadStateEvoRec *pHeadState) { if (pHeadState->procAmp.colorRange == NVT_COLOR_RANGE_FULL) { switch (pHeadState->procAmp.colorimetry) { @@ -1602,16 +1627,12 @@ static const struct NvKmsCscMatrix* EvoGetOCsc1MatrixC5(const NVDispHeadStateEvo } } -struct EvoClampRangeC5 { - NvU32 green, red_blue; -}; - /*! * Return the output clamping ranges for the requested color range and * colorimetry. */ -static struct EvoClampRangeC5 -EvoGetOCsc1ClampRange(const NVDispHeadStateEvoRec *pHeadState) +struct EvoClampRangeC5 +nvEvoGetOCsc1ClampRange(const NVDispHeadStateEvoRec *pHeadState) { if (pHeadState->procAmp.colorRange == NVT_COLOR_RANGE_FULL) { return (struct EvoClampRangeC5) { @@ -1647,43 +1668,6 @@ EvoGetOCsc1ClampRange(const NVDispHeadStateEvoRec *pHeadState) } } - -static void EvoSetOCsc1C5(NVDispEvoPtr pDispEvo, const NvU32 head) -{ - NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; - NVEvoChannelPtr pChannel = pDevEvo->core; - const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; - const struct NvKmsCscMatrix *matrix = EvoGetOCsc1MatrixC5(pHeadState); - struct EvoClampRangeC5 clamp = EvoGetOCsc1ClampRange(pHeadState); - - nvDmaSetStartEvoMethod(pChannel, NVC57D_HEAD_SET_CLAMP_RANGE_GREEN(head), 1); - nvDmaSetEvoMethodData(pChannel, clamp.green); - nvDmaSetStartEvoMethod(pChannel, NVC57D_HEAD_SET_CLAMP_RANGE_RED_BLUE(head), 1); - nvDmaSetEvoMethodData(pChannel, clamp.red_blue); - - if (matrix) { - int x, y; - NvU32 method = NVC57D_HEAD_SET_OCSC1COEFFICIENT_C00(head); - - nvDmaSetStartEvoMethod(pChannel, NVC57D_HEAD_SET_OCSC1CONTROL(head), 1); - nvDmaSetEvoMethodData(pChannel, - DRF_DEF(C57D, _HEAD_SET_OCSC1CONTROL, _ENABLE, _ENABLE)); - - for (y = 0; y < 3; y++) { - for (x = 0; x < 4; x++) { - nvDmaSetStartEvoMethod(pChannel, method, 1); - nvDmaSetEvoMethodData(pChannel, matrix->m[y][x]); - - method += 4; - } - } - } else { - nvDmaSetStartEvoMethod(pChannel, NVC57D_HEAD_SET_OCSC1CONTROL(head), 1); - nvDmaSetEvoMethodData(pChannel, - DRF_DEF(C57D, _HEAD_SET_OCSC1CONTROL, _ENABLE, _DISABLE)); - } -} - /* * 1.402 1.0 0.0 * -0.714136 1.0 -0.344136 @@ -1728,17 +1712,40 @@ static const struct NvKmsMatrix RGBtoCrYCb709Matrix = { { { 0xbdeaa3ad, 0xbec55715, 0x3f000000 } } }; -/* - * Converts FP32 to fixed point S5.14 coefficient format - */ -static inline NvU32 cscCoefConvertS514(float32_t x) +static void EvoSetOCsc1C5(NVDispEvoPtr pDispEvo, const NvU32 head) { - /* more concisely, (NvS32)floor(x * 65536.0 + 2.0) */ - const NvS32 y = f32_to_i32(f32_mulAdd(x, - NvU32viewAsF32(NV_FLOAT_65536), - NvU32viewAsF32(NV_FLOAT_TWO)), - softfloat_round_min, FALSE); - return (NvU32)(0x001ffffc & clamp_S32(y, -0x100000, 0xfffff)); + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + NVEvoChannelPtr pChannel = pDevEvo->core; + const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + const struct NvKmsCscMatrix *matrix = nvEvoGetOCsc1MatrixC5(pHeadState); + struct EvoClampRangeC5 clamp = nvEvoGetOCsc1ClampRange(pHeadState); + + nvDmaSetStartEvoMethod(pChannel, NVC57D_HEAD_SET_CLAMP_RANGE_GREEN(head), 1); + nvDmaSetEvoMethodData(pChannel, clamp.green); + nvDmaSetStartEvoMethod(pChannel, NVC57D_HEAD_SET_CLAMP_RANGE_RED_BLUE(head), 1); + nvDmaSetEvoMethodData(pChannel, clamp.red_blue); + + if (matrix) { + int x, y; + NvU32 method = NVC57D_HEAD_SET_OCSC1COEFFICIENT_C00(head); + + nvDmaSetStartEvoMethod(pChannel, NVC57D_HEAD_SET_OCSC1CONTROL(head), 1); + nvDmaSetEvoMethodData(pChannel, + DRF_DEF(C57D, _HEAD_SET_OCSC1CONTROL, _ENABLE, _ENABLE)); + + for (y = 0; y < 3; y++) { + for (x = 0; x < 4; x++) { + nvDmaSetStartEvoMethod(pChannel, method, 1); + nvDmaSetEvoMethodData(pChannel, matrix->m[y][x]); + + method += 4; + } + } + } else { + nvDmaSetStartEvoMethod(pChannel, NVC57D_HEAD_SET_OCSC1CONTROL(head), 1); + nvDmaSetEvoMethodData(pChannel, + DRF_DEF(C57D, _HEAD_SET_OCSC1CONTROL, _ENABLE, _DISABLE)); + } } /* @@ -1752,15 +1759,9 @@ static inline NvU32 cscCoefConvertS514(float32_t x) * the final output. Then we multiply by its inverse to convert back * to RGB. Finally, we convert the coefficients to S5.14 fixed point * format. - * - * The OCSC0 matrix will be enabled later in EvoSetLUTContextDmaC5 if - * and only if we also enable the OLUT as required by the - * specification. */ -static void EvoSetOCsc0C5(NVDispEvoPtr pDispEvo, const NvU32 head) +void nvEvo3PickOCsc0(NVDispEvoPtr pDispEvo, const NvU32 head, struct NvKms3x4MatrixF32 *ocsc0MatrixOutput) { - NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; - NVEvoChannelPtr pChannel = pDevEvo->core; const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; const float32_t zeroF32 = NvU32viewAsF32(NV_FLOAT_ZERO); @@ -1783,6 +1784,8 @@ static void EvoSetOCsc0C5(NVDispEvoPtr pDispEvo, const NvU32 head) struct NvKmsMatrixF32 CrYCbtoRGBMatrix; struct NvKmsMatrixF32 RGBtoCrYCbMatrix; + + switch (pHeadState->procAmp.colorimetry) { default: nvAssert(!"Unexpected colorimetry"); @@ -1817,21 +1820,40 @@ static void EvoSetOCsc0C5(NVDispEvoPtr pDispEvo, const NvU32 head) } } + *ocsc0MatrixOutput = ocsc0Matrix; +} + +/* + * Programs the OCSC0 matrix coefficients, used to perform saturation + * adjustment. + * + * The OCSC0 matrix will be enabled later in EvoSetLUTContextDmaC5 if + * and only if we also enable the OLUT as required by the + * specification. + */ +static void EvoSetOCsc0C5(NVDispEvoPtr pDispEvo, const NvU32 head) +{ + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + NVEvoChannelPtr pChannel = pDevEvo->core; + struct NvKms3x4MatrixF32 ocsc0Matrix; + + nvEvo3PickOCsc0(pDispEvo, head, &ocsc0Matrix); + nvDmaSetStartEvoMethod(pChannel, NVC57D_HEAD_SET_OCSC0COEFFICIENT_C00(head), 12); - nvDmaSetEvoMethodData(pChannel, DRF_NUM(C57D, _HEAD_SET_OCSC0COEFFICIENT_C00, _VALUE, cscCoefConvertS514(ocsc0Matrix.m[0][0]))); - nvDmaSetEvoMethodData(pChannel, DRF_NUM(C57D, _HEAD_SET_OCSC0COEFFICIENT_C01, _VALUE, cscCoefConvertS514(ocsc0Matrix.m[0][1]))); - nvDmaSetEvoMethodData(pChannel, DRF_NUM(C57D, _HEAD_SET_OCSC0COEFFICIENT_C02, _VALUE, cscCoefConvertS514(ocsc0Matrix.m[0][2]))); - nvDmaSetEvoMethodData(pChannel, DRF_NUM(C57D, _HEAD_SET_OCSC0COEFFICIENT_C03, _VALUE, cscCoefConvertS514(ocsc0Matrix.m[0][3]))); + nvDmaSetEvoMethodData(pChannel, DRF_NUM(C57D, _HEAD_SET_OCSC0COEFFICIENT_C00, _VALUE, nvCscCoefConvertS514(ocsc0Matrix.m[0][0]))); + nvDmaSetEvoMethodData(pChannel, DRF_NUM(C57D, _HEAD_SET_OCSC0COEFFICIENT_C01, _VALUE, nvCscCoefConvertS514(ocsc0Matrix.m[0][1]))); + nvDmaSetEvoMethodData(pChannel, DRF_NUM(C57D, _HEAD_SET_OCSC0COEFFICIENT_C02, _VALUE, nvCscCoefConvertS514(ocsc0Matrix.m[0][2]))); + nvDmaSetEvoMethodData(pChannel, DRF_NUM(C57D, _HEAD_SET_OCSC0COEFFICIENT_C03, _VALUE, nvCscCoefConvertS514(ocsc0Matrix.m[0][3]))); - nvDmaSetEvoMethodData(pChannel, DRF_NUM(C57D, _HEAD_SET_OCSC0COEFFICIENT_C10, _VALUE, cscCoefConvertS514(ocsc0Matrix.m[1][0]))); - nvDmaSetEvoMethodData(pChannel, DRF_NUM(C57D, _HEAD_SET_OCSC0COEFFICIENT_C11, _VALUE, cscCoefConvertS514(ocsc0Matrix.m[1][1]))); - nvDmaSetEvoMethodData(pChannel, DRF_NUM(C57D, _HEAD_SET_OCSC0COEFFICIENT_C12, _VALUE, cscCoefConvertS514(ocsc0Matrix.m[1][2]))); - nvDmaSetEvoMethodData(pChannel, DRF_NUM(C57D, _HEAD_SET_OCSC0COEFFICIENT_C13, _VALUE, cscCoefConvertS514(ocsc0Matrix.m[1][3]))); + nvDmaSetEvoMethodData(pChannel, DRF_NUM(C57D, _HEAD_SET_OCSC0COEFFICIENT_C10, _VALUE, nvCscCoefConvertS514(ocsc0Matrix.m[1][0]))); + nvDmaSetEvoMethodData(pChannel, DRF_NUM(C57D, _HEAD_SET_OCSC0COEFFICIENT_C11, _VALUE, nvCscCoefConvertS514(ocsc0Matrix.m[1][1]))); + nvDmaSetEvoMethodData(pChannel, DRF_NUM(C57D, _HEAD_SET_OCSC0COEFFICIENT_C12, _VALUE, nvCscCoefConvertS514(ocsc0Matrix.m[1][2]))); + nvDmaSetEvoMethodData(pChannel, DRF_NUM(C57D, _HEAD_SET_OCSC0COEFFICIENT_C13, _VALUE, nvCscCoefConvertS514(ocsc0Matrix.m[1][3]))); - nvDmaSetEvoMethodData(pChannel, DRF_NUM(C57D, _HEAD_SET_OCSC0COEFFICIENT_C20, _VALUE, cscCoefConvertS514(ocsc0Matrix.m[2][0]))); - nvDmaSetEvoMethodData(pChannel, DRF_NUM(C57D, _HEAD_SET_OCSC0COEFFICIENT_C21, _VALUE, cscCoefConvertS514(ocsc0Matrix.m[2][1]))); - nvDmaSetEvoMethodData(pChannel, DRF_NUM(C57D, _HEAD_SET_OCSC0COEFFICIENT_C22, _VALUE, cscCoefConvertS514(ocsc0Matrix.m[2][2]))); - nvDmaSetEvoMethodData(pChannel, DRF_NUM(C57D, _HEAD_SET_OCSC0COEFFICIENT_C23, _VALUE, cscCoefConvertS514(ocsc0Matrix.m[2][3]))); + nvDmaSetEvoMethodData(pChannel, DRF_NUM(C57D, _HEAD_SET_OCSC0COEFFICIENT_C20, _VALUE, nvCscCoefConvertS514(ocsc0Matrix.m[2][0]))); + nvDmaSetEvoMethodData(pChannel, DRF_NUM(C57D, _HEAD_SET_OCSC0COEFFICIENT_C21, _VALUE, nvCscCoefConvertS514(ocsc0Matrix.m[2][1]))); + nvDmaSetEvoMethodData(pChannel, DRF_NUM(C57D, _HEAD_SET_OCSC0COEFFICIENT_C22, _VALUE, nvCscCoefConvertS514(ocsc0Matrix.m[2][2]))); + nvDmaSetEvoMethodData(pChannel, DRF_NUM(C57D, _HEAD_SET_OCSC0COEFFICIENT_C23, _VALUE, nvCscCoefConvertS514(ocsc0Matrix.m[2][3]))); } static void EvoSetProcAmpC5(NVDispEvoPtr pDispEvo, const NvU32 head, @@ -1907,7 +1929,7 @@ static void EvoSetProcAmpC5(NVDispEvoPtr pDispEvo, const NvU32 head, * determine which pins should be enabled in the SetControl method. It should * be called any time the HeadControl data structures are updated. */ -static void SetControl(NVDevEvoPtr pDevEvo, int sd) +void nvEvoSetControlC3(NVDevEvoPtr pDevEvo, int sd) { NVEvoSubDevPtr pEvoSubDev = &pDevEvo->gpus[sd]; NVEvoChannelPtr pChannel = pDevEvo->core; @@ -2087,7 +2109,7 @@ static void EvoSetHeadControlC3(NVDevEvoPtr pDevEvo, int sd, int head, nvDmaSetStartEvoMethod(pChannel, NVC37D_HEAD_SET_CONTROL(head), 1); nvDmaSetEvoMethodData(pChannel, data); - SetControl(pDevEvo, sd); + nvEvoSetControlC3(pDevEvo, sd); nvDmaSetStartEvoMethod(pChannel, NVC37D_HEAD_SET_LOCK_CHAIN(head), 1); nvDmaSetEvoMethodData(pChannel, DRF_NUM(C37D, _HEAD_SET_LOCK_CHAIN, _POSITION, @@ -2193,7 +2215,7 @@ static void EvoSORSetControlC3(const NVConnectorEvoRec *pConnectorEvo, DRF_DEF(C37D, _SOR_SET_CONTROL, _PIXEL_REPLICATE_MODE, _OFF)); } -static NvU32 EvoGetPixelDepthC3(const enum nvKmsPixelDepth pixelDepth) +NvU32 nvEvoGetPixelDepthC3(const enum nvKmsPixelDepth pixelDepth) { switch (pixelDepth) { case NVKMS_PIXEL_DEPTH_18_444: @@ -2278,7 +2300,7 @@ static void EvoORSetControlC3Helper(const NVConnectorEvoRec *pConnectorEvo, } } -static void EvoORSetControlC3(NVDevEvoPtr pDevEvo, +void nvEvoORSetControlC3(NVDevEvoPtr pDevEvo, const NVConnectorEvoRec *pConnectorEvo, const enum nvKmsTimingsProtocol protocol, const NvU32 orIndex, @@ -2323,7 +2345,7 @@ static void EvoHeadSetControlORC3(NVDevEvoPtr pDevEvo, NVEvoUpdateState *updateState) { NVEvoChannelPtr pChannel = pDevEvo->core; - const NvU32 hwPixelDepth = EvoGetPixelDepthC3(pixelDepth); + const NvU32 hwPixelDepth = nvEvoGetPixelDepthC3(pixelDepth); const NvU16 colorSpaceFlag = nvEvo1GetColorSpaceFlag(pDevEvo, colorSpaceOverride); @@ -2351,7 +2373,7 @@ static void EvoHeadSetControlORC5(NVDevEvoPtr pDevEvo, NVEvoUpdateState *updateState) { NVEvoChannelPtr pChannel = pDevEvo->core; - const NvU32 hwPixelDepth = EvoGetPixelDepthC3(pixelDepth); + const NvU32 hwPixelDepth = nvEvoGetPixelDepthC3(pixelDepth); const NvU16 colorSpaceFlag = nvEvo1GetColorSpaceFlag(pDevEvo, colorSpaceOverride); @@ -2457,26 +2479,6 @@ static void SetFormatUsageBoundsOneWindow3(NVDevEvoPtr pDevEvo, NvU32 window, nvDmaSetEvoMethodData(pChannel, value); } -static inline NvU32 GetMaxPixelsFetchedPerLine(NvU16 inWidth, - NvU16 maxHDownscaleFactor) -{ - /* - * Volta should be: - * (((SetViewportSizeIn.Width + 6) * SetMaxInputScaleFactor.Horizontal + 1023 ) >> 10 ) + 6 - * - * Turing should be: - * (((SetViewportSizeIn.Width + 6) * SetMaxInputScaleFactor.Horizontal + 1023 ) >> 10 ) + 8 - * - * Ampere, which adds "overfetch" to have tiled displays / 2-head-1-OR use cases without - * visual artefacts at head boundaries: - * (((SetViewportSizeIn.Width + 14) * SetMaxInputScaleFactor.Horizontal + 1023) >> 10) + 8 - * - * We don't have to be super-precise when programming maxPixelsFetchedPerLine, - * so return realistic worst-case value. - */ - return (((inWidth + 14) * maxHDownscaleFactor + 1023) >> 10) + 8; -} - static void SetScalingUsageBoundsOneWindow5( NVDevEvoPtr pDevEvo, NvU32 window, const struct NvKmsScalingUsageBounds *pScaling, @@ -2499,7 +2501,7 @@ static void SetScalingUsageBoundsOneWindow5( pScaling->maxVDownscaleFactor)); if (layerUsable) { - maxPixelsFetchedPerLine = GetMaxPixelsFetchedPerLine(pViewPort->in.width, + maxPixelsFetchedPerLine = nvGetMaxPixelsFetchedPerLine(pViewPort->in.width, pScaling->maxHDownscaleFactor); } else { maxPixelsFetchedPerLine = 0; @@ -2566,7 +2568,7 @@ static NvBool EvoSetUsageBoundsC3(NVDevEvoPtr pDevEvo, NvU32 sd, NvU32 head, return EvoSetUsageBounds3(pDevEvo, sd, head, pUsage, updateState); } -static NvBool EvoSetUsageBoundsC5(NVDevEvoPtr pDevEvo, NvU32 sd, NvU32 head, +NvBool nvEvoSetUsageBoundsC5(NVDevEvoPtr pDevEvo, NvU32 sd, NvU32 head, const struct NvKmsUsageBounds *pUsage, NVEvoUpdateState *updateState) { @@ -2599,16 +2601,50 @@ static NvBool EvoSetUsageBoundsC5(NVDevEvoPtr pDevEvo, NvU32 sd, NvU32 head, return needCoreUpdate; } -static void EvoSetNotifierC3(NVDevEvoRec *pDevEvo, +static void EvoSetCoreNotifierSurfaceAddressAndControlC3( + NVEvoChannelPtr pChannel, + const NVSurfaceDescriptor *pSurfaceDesc, + NvU32 notifierOffset, + NvU32 ctrlVal) +{ + NvU32 ctxDmaHandle = pSurfaceDesc ? pSurfaceDesc->ctxDmaHandle : 0; + + nvDmaSetStartEvoMethod(pChannel, NVC37D_SET_CONTEXT_DMA_NOTIFIER, 1); + nvDmaSetEvoMethodData(pChannel, + DRF_NUM(C37D, _SET_CONTEXT_DMA_NOTIFIER, _HANDLE, ctxDmaHandle)); + + nvDmaSetStartEvoMethod(pChannel, NVC37D_SET_NOTIFIER_CONTROL, 1); + nvDmaSetEvoMethodData(pChannel, + DRF_NUM(C37D, _SET_NOTIFIER_CONTROL, _OFFSET, notifierOffset) | ctrlVal); +} + +void nvEvoSetNotifierC3(NVDevEvoRec *pDevEvo, const NvBool notify, const NvBool awaken, const NvU32 notifier, NVEvoUpdateState *updateState) { NVEvoChannelPtr pChannel = pDevEvo->core; + NvU32 ctrlVal = 0; nvUpdateUpdateState(pDevEvo, updateState, pChannel); + /* + * XXXnvdisplay: Note that nvdClass_01.mfs says: + * "The units of the offset are 16 bytes.", while dispClass_02.mfs says: + * "The units of the offset are 32 bit words." + * The "legacy" 32-bit notifier format is no longer supported. This will + * have to be exposed to upper layers. + */ + ASSERT_DRF_NUM(C37D, _SET_NOTIFIER_CONTROL, _OFFSET, notifier); + + ctrlVal = (awaken ? + DRF_DEF(C37D, _SET_NOTIFIER_CONTROL, _MODE, _WRITE_AWAKEN) : + DRF_DEF(C37D, _SET_NOTIFIER_CONTROL, _MODE, _WRITE)); + ctrlVal |= (notify ? + DRF_DEF(C37D, _SET_NOTIFIER_CONTROL, _NOTIFY, _ENABLE) : + DRF_DEF(C37D, _SET_NOTIFIER_CONTROL, _NOTIFY, _DISABLE)); + // To work around HW BUG 1945716, set the core channel completion notifier // context DMA to 0 when notification is not requested. if (notify) { @@ -2616,41 +2652,16 @@ static void EvoSetNotifierC3(NVDevEvoRec *pDevEvo, for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { if (nvPeekEvoSubDevMask(pDevEvo) & (1 << sd)) { nvPushEvoSubDevMask(pDevEvo, NVBIT(sd)); - nvDmaSetStartEvoMethod(pChannel, - NVC37D_SET_CONTEXT_DMA_NOTIFIER, 1); - nvDmaSetEvoMethodData(pChannel, - DRF_NUM(C37D, - _SET_CONTEXT_DMA_NOTIFIER, - _HANDLE, - pDevEvo->core->notifiersDma[sd].ctxHandle)); + pDevEvo->hal->SetCoreNotifierSurfaceAddressAndControl(pChannel, + &pDevEvo->core->notifiersDma[sd].surfaceDesc, + notifier, ctrlVal); nvPopEvoSubDevMask(pDevEvo); } } } else { - nvDmaSetStartEvoMethod(pChannel, - NVC37D_SET_CONTEXT_DMA_NOTIFIER, 1); - nvDmaSetEvoMethodData(pChannel, - DRF_NUM(C37D, _SET_CONTEXT_DMA_NOTIFIER, _HANDLE, 0)); + pDevEvo->hal->SetCoreNotifierSurfaceAddressAndControl(pChannel, + NULL /* pSurfaceDesc */, 0 /* offset */ , 0 /* ctrlVal */); } - - /* - * XXXnvdisplay: Note that nvdClass_01.mfs says: - * "The units of the offset are 16 bytes.", while dispClass_02.mfs says: - * "The units of the offset are 32 bit words." - * The "legacy" 32-bit notifier format is no longer supported. This will - * have to be exposed to upper layers. - */ - ASSERT_DRF_NUM(C37D, _SET_NOTIFIER_CONTROL, _OFFSET, notifier); - - nvDmaSetStartEvoMethod(pChannel, NVC37D_SET_NOTIFIER_CONTROL, 1); - nvDmaSetEvoMethodData(pChannel, - DRF_NUM(C37D, _SET_NOTIFIER_CONTROL, _OFFSET, notifier) | - (awaken ? - DRF_DEF(C37D, _SET_NOTIFIER_CONTROL, _MODE, _WRITE_AWAKEN) : - DRF_DEF(C37D, _SET_NOTIFIER_CONTROL, _MODE, _WRITE)) | - (notify ? - DRF_DEF(C37D, _SET_NOTIFIER_CONTROL, _NOTIFY, _ENABLE) : - DRF_DEF(C37D, _SET_NOTIFIER_CONTROL, _NOTIFY, _DISABLE))); } static void UpdateCoreC3(NVEvoChannelPtr pChannel, @@ -2951,7 +2962,7 @@ static NVEvoChannelMask ProcessFlipLockUpdates( return handledMask; } -static void EvoUpdateC3(NVDevEvoPtr pDevEvo, +void nvEvoUpdateC3(NVDevEvoPtr pDevEvo, const NVEvoUpdateState *updateState, NvBool releaseElv) { @@ -3079,7 +3090,7 @@ static NvBool AssignPerHeadImpParams(NVC372_CTRL_IMP_HEAD *pImpHead, pImpHead->outputScalerVerticalTaps = NVEvoScalerTapsToNum(scalingUsageBounds.vTaps); - if (!ComputeMinFrameIdle(pTimings, + if (!nvComputeMinFrameIdle(pTimings, &pImpHead->minFrameIdle.leadingRasterLines, &pImpHead->minFrameIdle.trailingRasterLines)) { return FALSE; @@ -3176,7 +3187,7 @@ static void AssignPerWindowImpParams(NVC372_CTRL_IMP_WINDOW *pImpWindow, } pImpWindow->maxPixelsFetchedPerLine = - GetMaxPixelsFetchedPerLine(pViewPort->in.width, + nvGetMaxPixelsFetchedPerLine(pViewPort->in.width, pScaling->maxHDownscaleFactor); pImpWindow->maxDownscaleFactorH = pScaling->maxHDownscaleFactor; @@ -3191,8 +3202,8 @@ static void AssignPerWindowImpParams(NVC372_CTRL_IMP_WINDOW *pImpWindow, pImpWindow->tmoLut = NVC372_CTRL_IMP_LUT_USAGE_1025; } -static void -EvoIsModePossibleC3(NVDispEvoPtr pDispEvo, +void +nvEvoIsModePossibleC3(NVDispEvoPtr pDispEvo, const NVEvoIsModePossibleDispInput *pInput, NVEvoIsModePossibleDispOutput *pOutput) { @@ -3294,7 +3305,7 @@ EvoIsModePossibleC3(NVDispEvoPtr pDispEvo, nvPreallocRelease(pDevEvo, PREALLOC_TYPE_IMP_PARAMS); } -static void EvoPrePostIMPC3(NVDispEvoPtr pDispEvo, NvBool isPre) +void nvEvoPrePostIMPC3(NVDispEvoPtr pDispEvo, NvBool isPre) { /* Nothing to do on nvdisplay -- pre/post IMP calls are not required. */ } @@ -3502,7 +3513,7 @@ EvoProgramSemaphore3(NVDevEvoPtr pDevEvo, nvAssert((pNIso->offsetInWords % 4) == 0); nvDmaSetStartEvoMethod(pChannel, NVC37E_SET_CONTEXT_DMA_SEMAPHORE, 1); - nvDmaSetEvoMethodData(pChannel, pNIso->pSurfaceEvo->planes[0].ctxDma); + nvDmaSetEvoMethodData(pChannel, pNIso->pSurfaceEvo->planes[0].surfaceDesc.ctxDmaHandle); nvDmaSetStartEvoMethod(pChannel, NVC37E_SET_SEMAPHORE_ACQUIRE, 1); nvDmaSetEvoMethodData(pChannel, @@ -3518,6 +3529,42 @@ EvoProgramSemaphore3(NVDevEvoPtr pDevEvo, } } +static void EvoSetSemaphoreSurfaceAddressAndControlC6( + NVEvoChannelPtr pChannel, + const NVSurfaceDescriptor *pSurfaceDesc, + NvU32 semaphoreOffset, + NvU32 ctrlVal) +{ + NvU32 ctxDmaHandle = pSurfaceDesc ? pSurfaceDesc->ctxDmaHandle : 0; + + /*! set ctx dma handle */ + nvDmaSetStartEvoMethod(pChannel, NVC67E_SET_CONTEXT_DMA_SEMAPHORE, 1); + nvDmaSetEvoMethodData(pChannel, + DRF_NUM(C67E, _SET_CONTEXT_DMA_SEMAPHORE, _HANDLE, ctxDmaHandle)); + + /*! set semaphore control and acq-rel mode */ + nvDmaSetStartEvoMethod(pChannel, NVC67E_SET_SEMAPHORE_CONTROL, 1); + nvDmaSetEvoMethodData(pChannel, semaphoreOffset | ctrlVal); +} + +static void EvoSetAcqSemaphoreSurfaceAddressAndControlC6( + NVEvoChannelPtr pChannel, + const NVSurfaceDescriptor *pSurfaceDesc, + NvU32 semaphoreOffset, + NvU32 ctrlVal) +{ + NvU32 ctxDmaHandle = pSurfaceDesc ? pSurfaceDesc->ctxDmaHandle : 0; + + /*! set ctx dma handle */ + nvDmaSetStartEvoMethod(pChannel, NVC67E_SET_CONTEXT_DMA_ACQ_SEMAPHORE, 1); + nvDmaSetEvoMethodData(pChannel, + DRF_NUM(C67E, _SET_CONTEXT_DMA_ACQ, _SEMAPHORE_HANDLE, ctxDmaHandle)); + + /*! set semaphore control and acq mode */ + nvDmaSetStartEvoMethod(pChannel, NVC67E_SET_ACQ_SEMAPHORE_CONTROL, 1); + nvDmaSetEvoMethodData(pChannel, semaphoreOffset | ctrlVal); +} + /*! * On Tegra, syncpts are used for synchronization between SW and HW, * and also across HW engines. Since NvDisplay 4.0 only natively @@ -3533,17 +3580,18 @@ EvoProgramSemaphore6(NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChannel, const NVFlipChannelEvoHwState *pHwState) { - NvU32 hCtxDma, offset, acqMode, relMode, value; + NvU32 offset, acqMode, relMode, value; + const NVSurfaceDescriptor *pSurfaceDesc = NULL; const NVFlipNIsoSurfaceEvoHwState *pNIso; /*! Program Acq-only semaphore */ - hCtxDma = offset = acqMode = relMode = value = 0; + offset = acqMode = relMode = value = 0; if (pHwState->syncObject.usingSyncpt) { if (pHwState->syncObject.u.syncpts.isPreSyncptSpecified) { NvU32 id = pHwState->syncObject.u.syncpts.preSyncpt; - hCtxDma = pDevEvo->preSyncptTable[id].hCtxDma; + pSurfaceDesc = &pDevEvo->preSyncptTable[id].surfaceDesc; } else { - hCtxDma = 0; + pSurfaceDesc = NULL; } offset = 0; acqMode = DRF_DEF(C67E, _SET_ACQ_SEMAPHORE_CONTROL, _ACQ_MODE, _CGEQ); @@ -3551,41 +3599,38 @@ EvoProgramSemaphore6(NVDevEvoPtr pDevEvo, } else { if (pHwState->syncObject.u.semaphores.acquireSurface.pSurfaceEvo != NULL) { pNIso = &pHwState->syncObject.u.semaphores.acquireSurface; - hCtxDma = pNIso->pSurfaceEvo->planes[0].ctxDma; + pSurfaceDesc = &pNIso->pSurfaceEvo->planes[0].surfaceDesc; offset = pNIso->offsetInWords / 4; acqMode = DRF_DEF(C67E, _SET_ACQ_SEMAPHORE_CONTROL, _ACQ_MODE, _EQ); value = pHwState->syncObject.u.semaphores.acquireValue; } } - /*! set ctx dma handle */ - nvDmaSetStartEvoMethod(pChannel, NVC67E_SET_CONTEXT_DMA_ACQ_SEMAPHORE, 1); - nvDmaSetEvoMethodData(pChannel, - DRF_NUM(C67E, _SET_CONTEXT_DMA_ACQ, _SEMAPHORE_HANDLE, hCtxDma)); - /*! set semaphore control and acq mode */ - nvDmaSetStartEvoMethod(pChannel, NVC67E_SET_ACQ_SEMAPHORE_CONTROL, 1); - nvDmaSetEvoMethodData(pChannel, offset | acqMode); + pDevEvo->hal->SetAcqSemaphoreSurfaceAddressAndControl(pChannel, + pSurfaceDesc, offset, acqMode); + /*! set semaphore value */ nvDmaSetStartEvoMethod(pChannel, NVC67E_SET_ACQ_SEMAPHORE_VALUE, 1); nvDmaSetEvoMethodData(pChannel, DRF_NUM(C67E, _SET_ACQ_SEMAPHORE_VALUE, _VALUE, value)); /*! Program Rel-only semaphore */ - hCtxDma = offset = acqMode = relMode = value = 0; + pSurfaceDesc = NULL; + offset = acqMode = relMode = value = 0; if (pHwState->syncObject.usingSyncpt) { - hCtxDma = pHwState->syncObject.u.syncpts.postCtxDma; + pSurfaceDesc = &pHwState->syncObject.u.syncpts.surfaceDesc; offset = 0; acqMode = DRF_DEF(C67E, _SET_SEMAPHORE_CONTROL, _SKIP_ACQ, _TRUE); relMode = DRF_DEF(C67E, _SET_SEMAPHORE_CONTROL, _REL_MODE, _WRITE); value = pHwState->syncObject.u.syncpts.postValue; /*! increase local max val as well */ - if (hCtxDma != 0) { + if (pHwState->syncObject.u.syncpts.isPostSyncptSpecified) { pChannel->postSyncpt.syncptMaxVal++; } } else { if (pHwState->syncObject.u.semaphores.releaseSurface.pSurfaceEvo != NULL) { pNIso = &pHwState->syncObject.u.semaphores.releaseSurface; - hCtxDma = pNIso->pSurfaceEvo->planes[0].ctxDma; + pSurfaceDesc = &pNIso->pSurfaceEvo->planes[0].surfaceDesc; offset = pNIso->offsetInWords / 4; acqMode = DRF_DEF(C67E, _SET_SEMAPHORE_CONTROL, _SKIP_ACQ, _TRUE); relMode = DRF_DEF(C67E, _SET_SEMAPHORE_CONTROL, _REL_MODE, _WRITE); @@ -3593,19 +3638,48 @@ EvoProgramSemaphore6(NVDevEvoPtr pDevEvo, } } - /*! set ctx dma handle */ - nvDmaSetStartEvoMethod(pChannel, NVC67E_SET_CONTEXT_DMA_SEMAPHORE, 1); - nvDmaSetEvoMethodData(pChannel, - DRF_NUM(C67E, _SET_CONTEXT_DMA_SEMAPHORE, _HANDLE, hCtxDma)); - /*! set semaphore control and acq-rel mode */ - nvDmaSetStartEvoMethod(pChannel, NVC67E_SET_SEMAPHORE_CONTROL, 1); - nvDmaSetEvoMethodData(pChannel, offset | acqMode | relMode); + pDevEvo->hal->SetSemaphoreSurfaceAddressAndControl(pChannel, + pSurfaceDesc, offset, (acqMode | relMode)); + /*! set semaphore value */ nvDmaSetStartEvoMethod(pChannel, NVC67E_SET_SEMAPHORE_RELEASE, 1); nvDmaSetEvoMethodData(pChannel, DRF_NUM(C67E, _SET_SEMAPHORE_RELEASE, _VALUE, value)); } +static void EvoSetWinNotifierSurfaceAddressAndControlC3( + NVEvoChannelPtr pChannel, + const NVSurfaceDescriptor *pSurfaceDesc, + NvU32 notifierOffset, + NvU32 ctrlVal) +{ + NvU32 ctxDmaHandle = pSurfaceDesc ? pSurfaceDesc->ctxDmaHandle : 0; + + nvDmaSetStartEvoMethod(pChannel, NVC37E_SET_CONTEXT_DMA_NOTIFIER, 1); + nvDmaSetEvoMethodData(pChannel, + DRF_NUM(C37E, _SET_CONTEXT_DMA_NOTIFIER, _HANDLE, ctxDmaHandle)); + + nvDmaSetStartEvoMethod(pChannel, NVC37E_SET_NOTIFIER_CONTROL, 1); + nvDmaSetEvoMethodData(pChannel, + DRF_NUM(C37E, _SET_NOTIFIER_CONTROL, _OFFSET, notifierOffset) | ctrlVal); +} + +static void EvoSetISOSurfaceAddressC3( + NVEvoChannelPtr pChannel, + const NVSurfaceDescriptor *pSurfaceDesc, + NvU32 offset, + NvU32 ctxDmaIdx, + NvBool isBlocklinear) +{ + NvU32 ctxDmaHandle = pSurfaceDesc ? pSurfaceDesc->ctxDmaHandle : 0; + + nvDmaSetStartEvoMethod(pChannel, NVC37E_SET_CONTEXT_DMA_ISO(ctxDmaIdx), 1); + nvDmaSetEvoMethodData(pChannel, ctxDmaHandle); + + nvDmaSetStartEvoMethod(pChannel, NVC37E_SET_OFFSET(ctxDmaIdx), 1); + nvDmaSetEvoMethodData(pChannel, nvCtxDmaOffsetFromBytes(offset)); +} + static NvBool EvoFlipC3Common(NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChannel, @@ -3617,6 +3691,8 @@ EvoFlipC3Common(NVDevEvoPtr pDevEvo, NvU32 presentControl, eye; NvU32 storage; NvU8 planeIndex; + NVSurfaceDescriptor *pSurfaceDesc = NULL; + NvU32 offset, ctrlVal; nvUpdateUpdateState(pDevEvo, updateState, pChannel); @@ -3628,56 +3704,43 @@ EvoFlipC3Common(NVDevEvoPtr pDevEvo, * for frame pacing are enabled then we need to provide our own * surface and keep getting flip completion updates. */ - NvU32 offset; const NvU32 sdMask = nvPeekEvoSubDevMask(pDevEvo); - const NvU32 sd = (sdMask == 0) ? 0 : __builtin_ffs(sdMask) - 1; + const NvU32 sd = (sdMask == 0) ? 0 : nv_ffs(sdMask) - 1; NVDispHeadStateEvoRec *pHeadState = &pDevEvo->pDispEvo[sd]->headState[head]; struct NvKmsVrrFramePacingInfo *pVrrFramePacingInfo = &pHeadState->vrrFramePacingInfo; if (pVrrFramePacingInfo->framePacingActive) { - nvDmaSetStartEvoMethod(pChannel, NVC37E_SET_CONTEXT_DMA_NOTIFIER, 1); - nvDmaSetEvoMethodData(pChannel, - DRF_NUM(C37E, - _SET_CONTEXT_DMA_NOTIFIER, - _HANDLE, - pChannel->notifiersDma[sd].ctxHandle)); - + pSurfaceDesc = &pChannel->notifiersDma[sd].surfaceDesc; offset = nvPrepareNextVrrNotifier(pChannel, sd, head); - nvDmaSetStartEvoMethod(pChannel, NVC37E_SET_NOTIFIER_CONTROL, 1); - nvDmaSetEvoMethodData(pChannel, - DRF_NUM(C37E, _SET_NOTIFIER_CONTROL, _OFFSET, offset) | - (DRF_DEF(C37E, _SET_NOTIFIER_CONTROL, _MODE, _WRITE_AWAKEN))); + ctrlVal = DRF_DEF(C37E, _SET_NOTIFIER_CONTROL, _MODE, _WRITE_AWAKEN); + pDevEvo->hal->SetWinNotifierSurfaceAddressAndControl(pChannel, + pSurfaceDesc, offset, ctrlVal); } else { - nvDmaSetStartEvoMethod(pChannel, NVC37E_SET_CONTEXT_DMA_NOTIFIER, 1); - nvDmaSetEvoMethodData(pChannel, 0); - nvDmaSetStartEvoMethod(pChannel, NVC37E_SET_NOTIFIER_CONTROL, 1); - nvDmaSetEvoMethodData(pChannel, 0); + offset = ctrlVal = 0; + pDevEvo->hal->SetWinNotifierSurfaceAddressAndControl(pChannel, + NULL, offset, ctrlVal); } } else { const NVFlipNIsoSurfaceEvoHwState *pNIso = &pHwState->completionNotifier.surface; - NvU32 value = 0; - - nvDmaSetStartEvoMethod(pChannel, NVC37E_SET_CONTEXT_DMA_NOTIFIER, 1); - nvDmaSetEvoMethodData(pChannel, pNIso->pSurfaceEvo->planes[0].ctxDma); nvAssert(pNIso->format == NVKMS_NISO_FORMAT_FOUR_WORD_NVDISPLAY); /* XXX nvdisplay: enforce this at a higher level */ nvAssert((pNIso->offsetInWords % 4) == 0); - value = FLD_SET_DRF_NUM(C37E, _SET_NOTIFIER_CONTROL, _OFFSET, - pNIso->offsetInWords / 4, value); - + pSurfaceDesc = &pNIso->pSurfaceEvo->planes[0].surfaceDesc; + offset = pNIso->offsetInWords / 4; + ctrlVal = 0; if (pHwState->completionNotifier.awaken) { - value = FLD_SET_DRF(C37E, _SET_NOTIFIER_CONTROL, _MODE, - _WRITE_AWAKEN, value); + ctrlVal = FLD_SET_DRF(C37E, _SET_NOTIFIER_CONTROL, _MODE, + _WRITE_AWAKEN, ctrlVal); } else { - value = FLD_SET_DRF(C37E, _SET_NOTIFIER_CONTROL, _MODE, - _WRITE, value); + ctrlVal = FLD_SET_DRF(C37E, _SET_NOTIFIER_CONTROL, _MODE, + _WRITE, ctrlVal); } - nvDmaSetStartEvoMethod(pChannel, NVC37E_SET_NOTIFIER_CONTROL, 1); - nvDmaSetEvoMethodData(pChannel, value); + pDevEvo->hal->SetWinNotifierSurfaceAddressAndControl(pChannel, + pSurfaceDesc, offset, ctrlVal); } if (!pHwState->pSurfaceEvo[NVKMS_LEFT]) { @@ -3687,10 +3750,9 @@ EvoFlipC3Common(NVDevEvoPtr pDevEvo, planeIndex < NVKMS_MAX_PLANES_PER_SURFACE; planeIndex++) { const NvU8 ctxDmaIdx = EyeAndPlaneToCtxDmaIdx(eye, planeIndex); - nvDmaSetStartEvoMethod(pChannel, - NVC37E_SET_CONTEXT_DMA_ISO(ctxDmaIdx), - 1); - nvDmaSetEvoMethodData(pChannel, 0); + pDevEvo->hal->SetISOSurfaceAddress(pChannel, + NULL /* pSurfaceDec */, 0 /* offset */, ctxDmaIdx, + NV_FALSE /* isBlocklinear */); } } @@ -3744,30 +3806,30 @@ EvoFlipC3Common(NVDevEvoPtr pDevEvo, FOR_ALL_EYES(eye) { const NVSurfaceEvoRec *pSurfaceEvoPerEye = pHwState->pSurfaceEvo[eye]; NvU8 numSurfacePlanes = 0; + NvBool isBlockLinear = NV_FALSE; if (pSurfaceEvoPerEye != NULL) { pFormatInfo = nvKmsGetSurfaceMemoryFormatInfo(pSurfaceEvoPerEye->format); numSurfacePlanes = pFormatInfo->numPlanes; + isBlockLinear = + (pSurfaceEvoPerEye->layout == NvKmsSurfaceMemoryLayoutBlockLinear); } for (planeIndex = 0; planeIndex < NVKMS_MAX_PLANES_PER_SURFACE; planeIndex++) { - NvU32 ctxdma = 0; + const NVSurfaceDescriptor *pSurfaceDesc = NULL; NvU64 offset = 0; const NvU8 ctxDmaIdx = EyeAndPlaneToCtxDmaIdx(eye, planeIndex); if (planeIndex < numSurfacePlanes) { - ctxdma = pSurfaceEvoPerEye->planes[planeIndex].ctxDma; + pSurfaceDesc = &pSurfaceEvoPerEye->planes[planeIndex].surfaceDesc; offset = pSurfaceEvoPerEye->planes[planeIndex].offset; } - nvDmaSetStartEvoMethod(pChannel, - NVC37E_SET_CONTEXT_DMA_ISO(ctxDmaIdx), 1); - nvDmaSetEvoMethodData(pChannel, ctxdma); - nvDmaSetStartEvoMethod(pChannel, NVC37E_SET_OFFSET(ctxDmaIdx), 1); - nvDmaSetEvoMethodData(pChannel, nvCtxDmaOffsetFromBytes(offset)); + pDevEvo->hal->SetISOSurfaceAddress(pChannel, + pSurfaceDesc, offset, ctxDmaIdx, isBlockLinear); } } @@ -4201,7 +4263,7 @@ EvoFlipC3(NVDevEvoPtr pDevEvo, DRF_DEF(C37E, _SET_PARAMS, _UNDERREPLICATE, _DISABLE)); if (pLutSurfaceEvo) { - const NvU32 ctxDma = pLutSurfaceEvo->dispCtxDma; + const NvU32 ctxDma = pLutSurfaceEvo->surfaceDesc.ctxDmaHandle; const NvU32 origin = offsetof(NVEvoLutDataRec, base); nvDmaSetStartEvoMethod(pChannel, NVC37E_SET_CONTROL_INPUT_LUT, 1); @@ -4309,6 +4371,20 @@ EvoSetupIdentityBaseLutC5(NVEvoLutDataRec *pData, *isLutModeVss = FALSE; } +static void EvoSetILUTSurfaceAddressC5( + NVEvoChannelPtr pChannel, + const NVSurfaceDescriptor *pSurfaceDesc, + NvU32 offset) +{ + NvU32 ctxDmaHandle = pSurfaceDesc ? pSurfaceDesc->ctxDmaHandle : 0; + + nvDmaSetStartEvoMethod(pChannel, NVC57E_SET_CONTEXT_DMA_ILUT, 1); + nvDmaSetEvoMethodData(pChannel, DRF_NUM(C57E, _SET_CONTEXT_DMA_ILUT, _HANDLE, ctxDmaHandle)); + + nvDmaSetStartEvoMethod(pChannel, NVC57E_SET_OFFSET_ILUT, 1); + nvDmaSetEvoMethodData(pChannel, DRF_NUM(C57E, _SET_OFFSET_ILUT, _ORIGIN, offset)); +} + static void EvoFlipC5Common(NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChannel, @@ -4328,12 +4404,12 @@ EvoFlipC5Common(NVDevEvoPtr pDevEvo, NvU32 head = pDevEvo->headForWindow[win]; const NvU32 sdMask = nvPeekEvoSubDevMask(pDevEvo); - const NvU32 sd = (sdMask == 0) ? 0 : __builtin_ffs(sdMask) - 1; + const NvU32 sd = (sdMask == 0) ? 0 : nv_ffs(sdMask) - 1; const NVDispHeadStateEvoRec *pHeadState = &pDevEvo->pDispEvo[sd]->headState[head]; // XXX HDR TODO: Handle other colorspaces // XXX HDR TODO: Enable custom input LUTs with HDR - if (pHwState->colorspace != NVKMS_INPUT_COLORSPACE_BT2100_PQ) { + if (pHwState->colorSpace != NVKMS_INPUT_COLORSPACE_BT2100_PQ) { pLutSurfaceEvo = EvoGetLutSurface3(pDevEvo, pChannel, pHwState); } @@ -4360,7 +4436,7 @@ EvoFlipC5Common(NVDevEvoPtr pDevEvo, * explicitly configure to convert the input surface format to the internal * RGB pipe native format. */ - EvoSetFMTMatrixC5(pChannel, format); + EvoSetFMTMatrixC5(pChannel, format, pHwState); vTaps = (pHwState->vTaps >= NV_EVO_SCALER_5TAPS) ? NVC57E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS_TAPS_5 : @@ -4387,11 +4463,11 @@ EvoFlipC5Common(NVDevEvoPtr pDevEvo, if (scaling || nvNeedsTmoLut(pDevEvo, pChannel, pHwState, nvGetHDRSrcMaxLum(pHwState), - pHeadState->hdr.staticMetadata.maxCLL)) { - ConfigureCsc0C5(pDevEvo, pChannel, pHwState->colorspace, TRUE); + pHeadState->hdrInfoFrame.staticMetadata.maxCLL)) { + ConfigureCsc0C5(pDevEvo, pChannel, pHwState->colorSpace, TRUE); ConfigureCsc1C5(pDevEvo, pChannel, TRUE); } else { - ConfigureCsc0C5(pDevEvo, pChannel, pHwState->colorspace, FALSE); + ConfigureCsc0C5(pDevEvo, pChannel, pHwState->colorSpace, FALSE); ConfigureCsc1C5(pDevEvo, pChannel, FALSE); SetCsc11MatrixC5(pChannel, &pHwState->cscMatrix); @@ -4401,8 +4477,8 @@ EvoFlipC5Common(NVDevEvoPtr pDevEvo, // unless the surface being displayed is already FP16 to begin with. if ((format == NvKmsSurfaceMemoryFormatRF16GF16BF16AF16) || (format == NvKmsSurfaceMemoryFormatRF16GF16BF16XF16) || bypassComposition) { - nvAssert((pHwState->colorspace == NVKMS_INPUT_COLORSPACE_SCRGB_LINEAR) || - (pHwState->colorspace == NVKMS_INPUT_COLORSPACE_NONE)); + nvAssert((pHwState->colorSpace == NVKMS_INPUT_COLORSPACE_SCRGB_LINEAR) || + (pHwState->colorSpace == NVKMS_INPUT_COLORSPACE_NONE)); pLutSurfaceEvo = NULL; } else if (!pLutSurfaceEvo) { NVEvoLutDataRec *pData = NULL; @@ -4412,7 +4488,7 @@ EvoFlipC5Common(NVDevEvoPtr pDevEvo, nvAssert(pData); - switch (pHwState->colorspace) { + switch (pHwState->colorSpace) { case NVKMS_INPUT_COLORSPACE_BT2100_PQ: EvoSetupPQEotfBaseLutC5(pData, &pDevEvo->lut.defaultBaseLUTState[sd], @@ -4433,7 +4509,6 @@ EvoFlipC5Common(NVDevEvoPtr pDevEvo, } if (pLutSurfaceEvo) { - const NvU32 ctxDma = pLutSurfaceEvo->dispCtxDma; const NvU32 origin = offsetof(NVEvoLutDataRec, base); nvDmaSetStartEvoMethod(pChannel, NVC57E_SET_ILUT_CONTROL, 1); @@ -4445,16 +4520,11 @@ EvoFlipC5Common(NVDevEvoPtr pDevEvo, DRF_DEF(C57E, _SET_ILUT_CONTROL, _MODE, _DIRECT10)) | DRF_NUM(C57E, _SET_ILUT_CONTROL, _SIZE, lutSize)); - nvDmaSetStartEvoMethod(pChannel, NVC57E_SET_OFFSET_ILUT, 1); - nvDmaSetEvoMethodData(pChannel, - DRF_NUM(C57E, _SET_OFFSET_ILUT, _ORIGIN, origin)); - - nvDmaSetStartEvoMethod(pChannel, NVC57E_SET_CONTEXT_DMA_ILUT, 1); - nvDmaSetEvoMethodData(pChannel, - DRF_NUM(C57E, _SET_CONTEXT_DMA_ILUT, _HANDLE, ctxDma)); + pDevEvo->hal->SetILUTSurfaceAddress(pChannel, + &pLutSurfaceEvo->surfaceDesc, origin); } else { - nvDmaSetStartEvoMethod(pChannel, NVC57E_SET_CONTEXT_DMA_ILUT, 1); - nvDmaSetEvoMethodData(pChannel, 0); + pDevEvo->hal->SetILUTSurfaceAddress(pChannel, + NULL /* pSurfaceDesc */, 0 /* offset */); } ConfigureTmoLut(pDevEvo, pHwState, pChannel); @@ -4497,8 +4567,8 @@ EvoFlipC5(NVDevEvoPtr pDevEvo, EvoProgramSemaphore3(pDevEvo, pChannel, pHwState); } -static void -EvoFlipC6(NVDevEvoPtr pDevEvo, +void +nvEvoFlipC6(NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChannel, const NVFlipChannelEvoHwState *pHwState, NVEvoUpdateState *updateState, @@ -4633,7 +4703,7 @@ static void EvoFlipTransitionWARC5(NVDevEvoPtr pDevEvo, NvU32 sd, NvU32 head, } } -static void EvoFlipTransitionWARC6(NVDevEvoPtr pDevEvo, NvU32 sd, NvU32 head, +void nvEvoFlipTransitionWARC6(NVDevEvoPtr pDevEvo, NvU32 sd, NvU32 head, const NVEvoSubDevHeadStateRec *pSdHeadState, const NVFlipEvoHwState *pFlipState, NVEvoUpdateState *updateState) @@ -4904,8 +4974,8 @@ static inline float16_t ColorToFp16(NvU16 val, float32_t maxf) return nvUnormToFp16(val, maxf); } -static void -EvoFillLUTSurfaceC5(NVEvoLutEntryRec *pLUTBuffer, +void +nvEvoFillLUTSurfaceC5(NVEvoLutEntryRec *pLUTBuffer, const NvU16 *red, const NvU16 *green, const NvU16 *blue, @@ -4979,7 +5049,7 @@ static void EvoSetLUTContextDma3(NVDevEvoPtr pDevEvo, * without releasing semaphore. * * Note that higher-level code will use core channel notifiers to - * synchronize these LUT updates, but that's okay because EvoUpdateC3() + * synchronize these LUT updates, but that's okay because nvEvoUpdateC3() * will interlock the core and window channel(s) updates together. */ for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { @@ -5018,7 +5088,7 @@ static void EvoSetLUTContextDmaC3(const NVDispEvoRec *pDispEvo, NVEvoUpdateState *updateState, NvBool bypassComposition) { - NvU32 ctxdma = (pLutSurfEvo != NULL) ? pLutSurfEvo->dispCtxDma : 0; + NvU32 ctxdma = (pLutSurfEvo != NULL) ? pLutSurfEvo->surfaceDesc.ctxDmaHandle : 0; NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; NVEvoChannelPtr pChannel = pDevEvo->core; NvU64 offset; @@ -5155,32 +5225,21 @@ static void SetupHDROutputLUT(NVDevEvoPtr pDevEvo, EvoSetupPQOetfOutputLutC5(pData, lutState, lutSize, isLutModeVss); } -static void EvoSetLUTContextDmaC5(const NVDispEvoRec *pDispEvo, - const int head, - NVLutSurfaceEvoPtr pLutSurfEvo, - NvBool enableBaseLut, - NvBool enableOutputLut, - NVEvoUpdateState *updateState, - NvBool bypassComposition) +void nvSetupOutputLUT5(NVDevEvoPtr pDevEvo, + const NVDispHeadStateEvoRec *pHeadState, + const int head, + NVLutSurfaceEvoPtr pLutSurfEvo, + NvBool enableBaseLut, + NvBool enableOutputLut, + NVEvoUpdateState *updateState, + NvBool bypassComposition, + NVSurfaceDescriptor **pSurfaceDesc, + NvU32 *lutSize, + NvBool *disableOcsc0, + NvU32 *fpNormScale, + NvBool *isLutModeVss) { - NvU32 ctxdma = (pLutSurfEvo != NULL) ? pLutSurfEvo->dispCtxDma : 0; - NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; - NVEvoChannelPtr pChannel = pDevEvo->core; - NvU64 offset; - NvU32 sd, lutSize = NV_NUM_EVO_LUT_ENTRIES; - NvBool isLutModeVss = FALSE; - const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; - NvBool disableOcsc0 = FALSE; - NvU32 fpNormScale = 0xFFFFFFFF; - - // XXX HDR TODO: Enable custom output LUTs with HDR - if (pHeadState->hdr.outputState == NVKMS_HDR_OUTPUT_STATE_HDR) { - enableOutputLut = FALSE; - } - - nvAssert(ctxdma || (!enableBaseLut && !enableOutputLut)); - - nvPushEvoSubDevMaskDisp(pDispEvo); + NvU32 sd; EvoSetLUTContextDma3(pDevEvo, head, @@ -5192,28 +5251,29 @@ static void EvoSetLUTContextDmaC5(const NVDispEvoRec *pDispEvo, /* Set the ctxdma for the output LUT */ if (bypassComposition) { - ctxdma = 0; + *pSurfaceDesc = NULL; /* if we're not enabling the OLUT, OCSC0 also needs to be disabled */ - disableOcsc0 = TRUE; + *disableOcsc0 = TRUE; } else if (!enableOutputLut) { /* Use the default OLUT if the client didn't provide one */ - ctxdma = pDevEvo->lut.defaultLut->dispCtxDma; + *pSurfaceDesc = &pDevEvo->lut.defaultLut->surfaceDesc; // Setup default OLUT for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { - if (pHeadState->hdr.outputState == NVKMS_HDR_OUTPUT_STATE_HDR) { + // XXX HDR TODO: Support other transfer functions + if (pHeadState->tf == NVKMS_OUTPUT_TF_PQ) { SetupHDROutputLUT(pDevEvo, pHeadState, sd, &pDevEvo->lut.defaultOutputLUTState[sd], - &lutSize, &isLutModeVss); + lutSize, isLutModeVss); - disableOcsc0 = TRUE; + *disableOcsc0 = TRUE; /* * Scale from [0.0, 125.0] to [0.0, 1.0] * XXX HDR TODO: Assumes input is in this range, SDR is not. */ - fpNormScale = 0xFFFFFFFF / 125; + *fpNormScale = 0xFFFFFFFF / 125; } else { NVLutSurfaceEvoPtr pLut = pDevEvo->lut.defaultLut; NVEvoLutDataRec *pData = pLut->subDeviceAddress[sd]; @@ -5221,10 +5281,71 @@ static void EvoSetLUTContextDmaC5(const NVDispEvoRec *pDispEvo, EvoSetupIdentityOutputLutC5( pData, &pDevEvo->lut.defaultOutputLUTState[sd], - &lutSize, &isLutModeVss); + lutSize, isLutModeVss); } } } +} + +static void SetOLUTSurfaceAddress( + NVEvoChannelPtr pChannel, + const NVSurfaceDescriptor *pSurfaceDesc, + NvU32 offset, + NvU32 head) +{ + NvU32 ctxDmaHandle = pSurfaceDesc ? pSurfaceDesc->ctxDmaHandle : 0; + + nvDmaSetStartEvoMethod(pChannel, NVC57D_HEAD_SET_CONTEXT_DMA_OLUT(head), 1); + nvDmaSetEvoMethodData(pChannel, + DRF_NUM(C57D, _HEAD_SET_CONTEXT_DMA_OLUT, _HANDLE, ctxDmaHandle)); + + nvDmaSetStartEvoMethod(pChannel, NVC57D_HEAD_SET_OFFSET_OLUT(head), 1); + nvDmaSetEvoMethodData(pChannel, + DRF_NUM(C57D, _HEAD_SET_OFFSET_OLUT, _ORIGIN, offset >> 8)); +} + +static void EvoSetLUTContextDmaC5(const NVDispEvoRec *pDispEvo, + const int head, + NVLutSurfaceEvoPtr pLutSurfEvo, + NvBool enableBaseLut, + NvBool enableOutputLut, + NVEvoUpdateState *updateState, + NvBool bypassComposition) +{ + NVSurfaceDescriptor *pSurfaceDesc = + (pLutSurfEvo != NULL) ? &pLutSurfEvo->surfaceDesc : NULL; + NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo; + NVEvoChannelPtr pChannel = pDevEvo->core; + NvU64 offset; + NvU32 lutSize = NV_NUM_EVO_LUT_ENTRIES; + NvBool isLutModeVss = FALSE; + const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head]; + NvBool disableOcsc0 = FALSE; + NvU32 fpNormScale = 0xFFFFFFFF; + + // XXX HDR TODO: Enable custom output LUTs with HDR + // XXX HDR TODO: Support other transfer functions + if (pHeadState->tf == NVKMS_OUTPUT_TF_PQ) { + enableOutputLut = FALSE; + } + + nvAssert(pSurfaceDesc || (!enableBaseLut && !enableOutputLut)); + + nvPushEvoSubDevMaskDisp(pDispEvo); + + nvSetupOutputLUT5(pDevEvo, + pHeadState, + head, + pLutSurfEvo, + enableBaseLut, + enableOutputLut, + updateState, + bypassComposition, + &pSurfaceDesc, + &lutSize, + &disableOcsc0, + &fpNormScale, + &isLutModeVss); if (disableOcsc0) { nvDmaSetStartEvoMethod(pChannel, NVC57D_HEAD_SET_OCSC0CONTROL(head), 1); @@ -5247,17 +5368,11 @@ static void EvoSetLUTContextDmaC5(const NVDispEvoRec *pDispEvo, DRF_NUM(C57D, _HEAD_SET_OLUT_CONTROL, _SIZE, NV_LUT_VSS_HEADER_SIZE + lutSize)); - nvDmaSetStartEvoMethod(pChannel, NVC57D_HEAD_SET_OFFSET_OLUT(head), 1); - nvDmaSetEvoMethodData(pChannel, - DRF_NUM(C57D, _HEAD_SET_OFFSET_OLUT, _ORIGIN, offset >> 8)); + SetOLUTSurfaceAddress(pChannel, pSurfaceDesc, offset, head); nvDmaSetStartEvoMethod(pChannel, NVC57D_HEAD_SET_OLUT_FP_NORM_SCALE(head), 1); nvDmaSetEvoMethodData(pChannel, fpNormScale); - nvDmaSetStartEvoMethod(pChannel, NVC57D_HEAD_SET_CONTEXT_DMA_OLUT(head), 1); - nvDmaSetEvoMethodData(pChannel, - DRF_NUM(C57D, _HEAD_SET_CONTEXT_DMA_OLUT, _HANDLE, ctxdma)); - if (!disableOcsc0) { /* only enable OCSC0 after enabling the OLUT */ nvDmaSetStartEvoMethod(pChannel, NVC57D_HEAD_SET_OCSC0CONTROL(head), 1); @@ -5796,6 +5911,10 @@ static void SetHDRLayerCaps(NVDevEvoPtr pDevEvo) NVEvoWindowCaps *pWinCaps = &pEvoCaps->window[win]; const NvU32 head = pDevEvo->headForWindow[win]; + if (head == NV_INVALID_HEAD) { + continue; + } + /* * XXX HDR: layerCaps assumes that every head has layers with the * same capabilities. @@ -6009,7 +6128,7 @@ static NvBool EvoGetCapabilitiesC5(NVDevEvoPtr pDevEvo) sizeof(_NvC573DispCapabilities)); } -static NvBool EvoGetCapabilitiesC6(NVDevEvoPtr pDevEvo) +NvBool nvEvoGetCapabilitiesC6(NVDevEvoPtr pDevEvo) { return EvoGetCapabilities3(pDevEvo, EvoParseCapabilityNotifierC6, nvHwFormatFromKmsFormatC6, @@ -6135,7 +6254,7 @@ static NvBool EvoSetViewportInOut3(NVDevEvoPtr pDevEvo, const int head, */ setWindowUsageBounds |= DRF_NUM(C37D, _WINDOW_SET_WINDOW_USAGE_BOUNDS, _MAX_PIXELS_FETCHED_PER_LINE, - GetMaxPixelsFetchedPerLine(pViewPort->in.width, + nvGetMaxPixelsFetchedPerLine(pViewPort->in.width, NV_EVO_SCALE_FACTOR_1X)); for (win = 0; win < pDevEvo->numWindows; win++) { @@ -6216,7 +6335,7 @@ static void EvoSetViewportInOutC5(NVDevEvoPtr pDevEvo, const int head, * pValue contains the method value. If FALSE, the surface * cannot be used as a cursor image. */ -static NvBool EvoGetHeadSetControlCursorValueC3(const NVDevEvoRec *pDevEvo, +NvBool nvEvoGetHeadSetControlCursorValueC3(const NVDevEvoRec *pDevEvo, const NVSurfaceEvoRec *pSurfaceEvo, NvU32 *pValue) { @@ -6283,13 +6402,40 @@ static NvBool EvoGetHeadSetControlCursorValueC3(const NVDevEvoRec *pDevEvo, return TRUE; } +static void SetCursorSurfaceAddress( + NVEvoChannelPtr pChannel, + const NVSurfaceDescriptor *pSurfaceDesc, + NvU32 offset, + NvU32 head) +{ + NvU32 ctxDmaHandle = pSurfaceDesc ? pSurfaceDesc->ctxDmaHandle : 0; + + nvAssert(!pSurfaceDesc || ctxDmaHandle); + + nvDmaSetStartEvoMethod(pChannel, NVC37D_HEAD_SET_CONTEXT_DMA_CURSOR(head, 0), 4); + nvDmaSetEvoMethodData(pChannel, + DRF_NUM(C37D, _HEAD_SET_CONTEXT_DMA_CURSOR, _HANDLE, ctxDmaHandle)); + + // Always set the right cursor context DMA. + // HW will just ignore this if it is not in stereo cursor mode. + nvDmaSetEvoMethodData(pChannel, + DRF_NUM(C37D, _HEAD_SET_CONTEXT_DMA_CURSOR, _HANDLE, ctxDmaHandle)); + nvDmaSetEvoMethodData(pChannel, + DRF_NUM(C37D, _HEAD_SET_OFFSET_CURSOR, _ORIGIN, + nvCtxDmaOffsetFromBytes(offset))); + nvDmaSetEvoMethodData(pChannel, + DRF_NUM(C37D, _HEAD_SET_OFFSET_CURSOR, _ORIGIN, + nvCtxDmaOffsetFromBytes(offset))); +} + static void EvoSetCursorImageC3(NVDevEvoPtr pDevEvo, const int head, const NVSurfaceEvoRec *pSurfaceEvo, NVEvoUpdateState *updateState, const struct NvKmsCompositionParams *pCursorCompParams) { NVEvoChannelPtr pChannel = pDevEvo->core; - const NvU32 ctxdma = pSurfaceEvo ? pSurfaceEvo->planes[0].ctxDma : 0; + const NVSurfaceDescriptor *pSurfaceDesc = + pSurfaceEvo ? &pSurfaceEvo->planes[0].surfaceDesc : NULL; const NvU64 offset = pSurfaceEvo ? pSurfaceEvo->planes[0].offset : 0; NvU32 headSetControlCursorValue = 0; NvBool ret; @@ -6302,9 +6448,7 @@ static void EvoSetCursorImageC3(NVDevEvoPtr pDevEvo, const int head, /* These methods should only apply to a single pDpy */ nvAssert(pDevEvo->subDevMaskStackDepth > 0); - nvAssert(!pSurfaceEvo || ctxdma); - - ret = EvoGetHeadSetControlCursorValueC3(pDevEvo, pSurfaceEvo, + ret = nvEvoGetHeadSetControlCursorValueC3(pDevEvo, pSurfaceEvo, &headSetControlCursorValue); /* * The caller should have already validated the surface, so there @@ -6318,19 +6462,7 @@ static void EvoSetCursorImageC3(NVDevEvoPtr pDevEvo, const int head, nvDmaSetEvoMethodData(pChannel, DRF_DEF(C37D, _HEAD_SET_PRESENT_CONTROL_CURSOR, _MODE, _MONO)); - nvDmaSetStartEvoMethod(pChannel, NVC37D_HEAD_SET_CONTEXT_DMA_CURSOR(head, 0), 4); - nvDmaSetEvoMethodData(pChannel, - DRF_NUM(C37D, _HEAD_SET_CONTEXT_DMA_CURSOR, _HANDLE, ctxdma)); - // Always set the right cursor context DMA. - // HW will just ignore this if it is not in stereo cursor mode. - nvDmaSetEvoMethodData(pChannel, - DRF_NUM(C37D, _HEAD_SET_CONTEXT_DMA_CURSOR, _HANDLE, ctxdma)); - nvDmaSetEvoMethodData(pChannel, - DRF_NUM(C37D, _HEAD_SET_OFFSET_CURSOR, _ORIGIN, - nvCtxDmaOffsetFromBytes(offset))); - nvDmaSetEvoMethodData(pChannel, - DRF_NUM(C37D, _HEAD_SET_OFFSET_CURSOR, _ORIGIN, - nvCtxDmaOffsetFromBytes(offset))); + SetCursorSurfaceAddress(pChannel, pSurfaceDesc, offset, head); nvDmaSetStartEvoMethod(pChannel, NVC37D_HEAD_SET_CONTROL_CURSOR(head), 1); nvDmaSetEvoMethodData(pChannel, headSetControlCursorValue); @@ -6393,10 +6525,10 @@ static void EvoSetCursorImageC3(NVDevEvoPtr pDevEvo, const int head, } } -static NvBool EvoValidateCursorSurfaceC3(const NVDevEvoRec *pDevEvo, +NvBool nvEvoValidateCursorSurfaceC3(const NVDevEvoRec *pDevEvo, const NVSurfaceEvoRec *pSurfaceEvo) { - return EvoGetHeadSetControlCursorValueC3(pDevEvo, pSurfaceEvo, NULL); + return nvEvoGetHeadSetControlCursorValueC3(pDevEvo, pSurfaceEvo, NULL); } static NvBool ValidateWindowFormatSourceRectC3( @@ -6493,7 +6625,7 @@ static NvBool EvoValidateWindowFormatC5( hwFormatOut); } -static NvBool EvoValidateWindowFormatC6( +NvBool nvEvoValidateWindowFormatC6( const enum NvKmsSurfaceMemoryFormat format, const struct NvKmsRect *sourceFetchRect, NvU32 *hwFormatOut) @@ -6514,20 +6646,20 @@ static NvU32 OffsetForNotifier(int idx) return base + NV_DISP_NOTIFIER__0; } -static void EvoInitCompNotifierC3(const NVDispEvoRec *pDispEvo, int idx) +void nvEvoInitCompNotifierC3(const NVDispEvoRec *pDispEvo, int idx) { nvWriteEvoCoreNotifier(pDispEvo, OffsetForNotifier(idx), DRF_DEF(_DISP, _NOTIFIER__0, _STATUS, _NOT_BEGUN)); } -static NvBool EvoIsCompNotifierCompleteC3(NVDispEvoPtr pDispEvo, int idx) { +NvBool nvEvoIsCompNotifierCompleteC3(NVDispEvoPtr pDispEvo, int idx) { return nvEvoIsCoreNotifierComplete(pDispEvo, OffsetForNotifier(idx), DRF_BASE(NV_DISP_NOTIFIER__0_STATUS), DRF_EXTENT(NV_DISP_NOTIFIER__0_STATUS), NV_DISP_NOTIFIER__0_STATUS_FINISHED); } -static void EvoWaitForCompNotifierC3(const NVDispEvoRec *pDispEvo, int idx) +void nvEvoWaitForCompNotifierC3(const NVDispEvoRec *pDispEvo, int idx) { nvEvoWaitForCoreNotifier(pDispEvo, OffsetForNotifier(idx), DRF_BASE(NV_DISP_NOTIFIER__0_STATUS), @@ -6701,7 +6833,7 @@ static NvBool GetChannelState(NVDevEvoPtr pDevEvo, return TRUE; } -static NvBool EvoIsChannelIdleC3(NVDevEvoPtr pDevEvo, +NvBool nvEvoIsChannelIdleC3(NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChan, NvU32 sd, NvBool *result) @@ -6717,7 +6849,7 @@ static NvBool EvoIsChannelIdleC3(NVDevEvoPtr pDevEvo, return TRUE; } -static NvBool EvoIsChannelMethodPendingC3(NVDevEvoPtr pDevEvo, +NvBool nvEvoIsChannelMethodPendingC3(NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChan, NvU32 sd, NvBool *result) @@ -6728,7 +6860,7 @@ static NvBool EvoIsChannelMethodPendingC3(NVDevEvoPtr pDevEvo, ct_assert(NVC370_CTRL_GET_CHANNEL_INFO_STATE_IDLE == NVC370_CTRL_GET_CHANNEL_INFO_STATE_NO_METHOD_PENDING); - if (!EvoIsChannelIdleC3(pDevEvo, pChan, sd, &tmpResult)) { + if (!nvEvoIsChannelIdleC3(pDevEvo, pChan, sd, &tmpResult)) { return FALSE; } @@ -6737,7 +6869,7 @@ static NvBool EvoIsChannelMethodPendingC3(NVDevEvoPtr pDevEvo, return TRUE; } -static NvBool EvoAllocRmCtrlObjectC3(NVDevEvoPtr pDevEvo) +NvBool nvEvoAllocRmCtrlObjectC3(NVDevEvoPtr pDevEvo) { const NvU32 handle = nvGenerateUnixRmHandle(&pDevEvo->handleAllocator); @@ -6819,7 +6951,7 @@ static NvBool SetAccelerators( return TRUE; } -static void EvoAccelerateChannelC3(NVDevEvoPtr pDevEvo, +void nvEvoAccelerateChannelC3(NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChannel, const NvU32 sd, const NvBool trashPendingMethods, @@ -6852,7 +6984,7 @@ static void EvoAccelerateChannelC3(NVDevEvoPtr pDevEvo, } } -static void EvoResetChannelAcceleratorsC3(NVDevEvoPtr pDevEvo, +void nvEvoResetChannelAcceleratorsC3(NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChannel, const NvU32 sd, const NvBool trashPendingMethods, @@ -6910,7 +7042,7 @@ static NvBool PollForChannelIdle( NvBool isMethodPending = TRUE; do { - if (!EvoIsChannelMethodPendingC3(pDevEvo, pChannel, sd, + if (!nvEvoIsChannelMethodPendingC3(pDevEvo, pChannel, sd, &isMethodPending)) { break; } @@ -6919,7 +7051,7 @@ static NvBool PollForChannelIdle( break; } - if (nvExceedsTimeoutUSec(&startTime, timeout)) { + if (nvExceedsTimeoutUSec(pDevEvo, &startTime, timeout)) { return FALSE; } @@ -7014,7 +7146,7 @@ static NvBool EvoForceIdleSatelliteChannelsWithAccel( } /* Push one update for all of the flips programmed above. */ - EvoUpdateC3(pDevEvo, &updateState, TRUE /* releaseElv */); + nvEvoUpdateC3(pDevEvo, &updateState, TRUE /* releaseElv */); for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { for (window = 0; window < pDevEvo->numWindows; window++) { @@ -7062,7 +7194,7 @@ static NvBool EvoForceIdleSatelliteChannelsWithAccel( return ret; } -static NvBool EvoForceIdleSatelliteChannelC3( +NvBool nvEvoForceIdleSatelliteChannelC3( NVDevEvoPtr pDevEvo, const NVEvoIdleChannelState *idleChannelState) { @@ -7077,7 +7209,7 @@ static NvBool EvoForceIdleSatelliteChannelC3( accelMask); } -static NvBool EvoForceIdleSatelliteChannelIgnoreLockC3( +NvBool nvEvoForceIdleSatelliteChannelIgnoreLockC3( NVDevEvoPtr pDevEvo, const NVEvoIdleChannelState *idleChannelState) { @@ -7092,7 +7224,7 @@ static NvBool EvoForceIdleSatelliteChannelIgnoreLockC3( accelMask); } -static void EvoFreeRmCtrlObjectC3(NVDevEvoPtr pDevEvo) +void nvEvoFreeRmCtrlObjectC3(NVDevEvoPtr pDevEvo) { if (pDevEvo->rmCtrlHandle) { NvU32 status; @@ -7110,7 +7242,7 @@ static void EvoFreeRmCtrlObjectC3(NVDevEvoPtr pDevEvo) } } -static void EvoSetImmPointOutC3(NVDevEvoPtr pDevEvo, +void nvEvoSetImmPointOutC3(NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChannel, NvU32 sd, NVEvoUpdateState *updateState, @@ -7121,6 +7253,10 @@ static void EvoSetImmPointOutC3(NVDevEvoPtr pDevEvo, nvAssert((pChannel->channelMask & NV_EVO_CHANNEL_MASK_WINDOW_ALL) != 0); nvAssert(pChannel->imm.type == NV_EVO_IMM_CHANNEL_DMA); + /* This should only be called for one GPU at a time, since the + * pre-nvdisplay version uses PIO and cannot broadcast. */ + nvAssert(ONEBITSET(nvPeekEvoSubDevMask(pDevEvo))); + nvDmaSetStartEvoMethod(pImmChannel, NVC37B_SET_POINT_OUT(0 /* Left eye */), 1); @@ -7131,6 +7267,18 @@ static void EvoSetImmPointOutC3(NVDevEvoPtr pDevEvo, nvWinImmChannelUpdateState(pDevEvo, updateState, pChannel); } +static void SetCrcSurfaceAddress( + NVEvoChannelPtr pChannel, + const NVSurfaceDescriptor *pSurfaceDesc, + NvU32 head) +{ + NvU32 ctxDmaHandle = pSurfaceDesc ? pSurfaceDesc->ctxDmaHandle : 0; + + nvDmaSetStartEvoMethod(pChannel, NVC37D_HEAD_SET_CONTEXT_DMA_CRC(head), 1); + nvDmaSetEvoMethodData(pChannel, + DRF_NUM(C37D, _HEAD_SET_CONTEXT_DMA_CRC, _HANDLE, ctxDmaHandle)); +} + static void EvoStartHeadCRC32CaptureC3(NVDevEvoPtr pDevEvo, NVEvoDmaPtr pDma, NVConnectorEvoPtr pConnectorEvo, @@ -7142,7 +7290,6 @@ static void EvoStartHeadCRC32CaptureC3(NVDevEvoPtr pDevEvo, { const NvU32 winChannel = head << 1; NVEvoChannelPtr pChannel = pDevEvo->core; - NvU32 dmaCtx = pDma->ctxHandle; NvU32 orOutput = 0; /* These method should only apply to a single pDpy */ @@ -7175,9 +7322,7 @@ static void EvoStartHeadCRC32CaptureC3(NVDevEvoPtr pDevEvo, break; } - nvDmaSetStartEvoMethod(pChannel, NVC37D_HEAD_SET_CONTEXT_DMA_CRC(head), 1); - nvDmaSetEvoMethodData(pChannel, - DRF_NUM(C37D, _HEAD_SET_CONTEXT_DMA_CRC, _HANDLE, dmaCtx)); + SetCrcSurfaceAddress(pChannel, &pDma->surfaceDesc, head); nvDmaSetStartEvoMethod(pChannel, NVC37D_HEAD_SET_CRC_CONTROL(head), 1); nvDmaSetEvoMethodData(pChannel, @@ -7205,8 +7350,7 @@ static void EvoStopHeadCRC32CaptureC3(NVDevEvoPtr pDevEvo, nvUpdateUpdateState(pDevEvo, updateState, pChannel); - nvDmaSetStartEvoMethod(pChannel, NVC37D_HEAD_SET_CONTEXT_DMA_CRC(head), 1); - nvDmaSetEvoMethodData(pChannel, 0); + SetCrcSurfaceAddress(pChannel, NULL /* pSurfaceDesc */, head); nvDmaSetStartEvoMethod(pChannel, NVC37D_HEAD_SET_CRC_CONTROL(head), 1); nvDmaSetEvoMethodData(pChannel, @@ -7235,7 +7379,7 @@ static void EvoStopHeadCRC32CaptureC3(NVDevEvoPtr pDevEvo, * \return Returns TRUE if was able to successfully read CRCs from DMA, * otherwise FALSE */ -static NvBool EvoQueryHeadCRC32_C3(NVDevEvoPtr pDevEvo, +NvBool nvEvoQueryHeadCRC32_C3(NVDevEvoPtr pDevEvo, NVEvoDmaPtr pDma, NvU32 sd, NvU32 entry_count, @@ -7304,7 +7448,8 @@ static NvBool EvoQueryHeadCRC32_C3(NVDevEvoPtr pDevEvo, } }; - if (!nvEvoWaitForCRC32Notifier(pCRC32Notifier, + if (!nvEvoWaitForCRC32Notifier(pDevEvo, + pCRC32Notifier, NVC37D_NOTIFIER_CRC_STATUS_0, DRF_BASE(NVC37D_NOTIFIER_CRC_STATUS_0_DONE), DRF_EXTENT(NVC37D_NOTIFIER_CRC_STATUS_0_DONE), @@ -7329,7 +7474,7 @@ static NvBool EvoQueryHeadCRC32_C3(NVDevEvoPtr pDevEvo, return TRUE; } -static void EvoGetScanLineC3(const NVDispEvoRec *pDispEvo, +void nvEvoGetScanLineC3(const NVDispEvoRec *pDispEvo, const NvU32 head, NvU16 *pScanLine, NvBool *pInBlankingPeriod) @@ -7357,7 +7502,7 @@ EvoConfigureVblankSyncObjectC6(const NVDevEvoPtr pDevEvo, const NvU16 rasterLine, const NvU32 head, const NvU32 semaphoreIndex, - const NvU32 hCtxDma, + const NVSurfaceDescriptor *pSurfaceDesc, NVEvoUpdateState* pUpdateState) { NVEvoChannelPtr pChannel = pDevEvo->core; @@ -7370,15 +7515,16 @@ EvoConfigureVblankSyncObjectC6(const NVDevEvoPtr pDevEvo, /* * Tell HW what ctxdma entry to use to look up actual RG semaphore surface. - * If hCtxDma is 0, HW will disable the semaphore. + * If ctxdma handle is 0, HW will disable the semaphore. */ nvDmaSetStartEvoMethod(pChannel, NVC67D_HEAD_SET_CONTEXT_DMA_RG_REL_SEMAPHORE(head, semaphoreIndex), 1); nvDmaSetEvoMethodData(pChannel, - DRF_NUM(C67D, _HEAD_SET_CONTEXT_DMA_RG_REL_SEMAPHORE, _HANDLE, hCtxDma)); + DRF_NUM(C67D, _HEAD_SET_CONTEXT_DMA_RG_REL_SEMAPHORE, _HANDLE, + (pSurfaceDesc == NULL) ? 0 : pSurfaceDesc->ctxDmaHandle)); - if (hCtxDma == 0) { + if ((pSurfaceDesc == NULL) || (pSurfaceDesc->ctxDmaHandle == 0)) { /* Disabling semaphore so no configuration necessary. */ return; } @@ -7598,7 +7744,7 @@ EvoEnableMidFrameAndDWCFWatermarkC5(NVDevEvoPtr pDevEvo, nvPopEvoSubDevMask(pDevEvo); } -static NvU32 EvoGetActiveViewportOffsetC3(NVDispEvoRec *pDispEvo, NvU32 head) +NvU32 nvEvoGetActiveViewportOffsetC3(NVDispEvoRec *pDispEvo, NvU32 head) { NVC372_CTRL_CMD_GET_ACTIVE_VIEWPORT_POINT_IN_PARAMS params = { }; NvU32 ret; @@ -7640,7 +7786,7 @@ static NvBool EvoComputeWindowScalingTapsC3(const NVDevEvoRec *pDevEvo, return TRUE; } -static NvBool EvoComputeWindowScalingTapsC5(const NVDevEvoRec *pDevEvo, +NvBool nvEvoComputeWindowScalingTapsC5(const NVDevEvoRec *pDevEvo, const NVEvoChannel *pChannel, NVFlipChannelEvoHwState *pHwState) { @@ -7663,20 +7809,6 @@ static NvBool EvoComputeWindowScalingTapsC5(const NVDevEvoRec *pDevEvo, return TRUE; } -static inline const NVEvoScalerCaps* -EvoGetWindowScalingCapsC3(const NVDevEvoRec *pDevEvo) -{ - /* - * Use window 0 by default. This should be fine for now since precomp - * scaling will only be enabled on Orin, and all windows have the same - * capabilities on Orin. - * - * The mapping in this function can be updated if/when precomp scaling - * support is extended to other display architectures. - */ - return &pDevEvo->gpus[0].capabilities.window[0].scalerCaps; -} - static void EvoSetMergeModeC5(const NVDispEvoRec *pDispEvo, const NvU32 head, const NVEvoMergeMode mode, @@ -7711,19 +7843,45 @@ static void EvoSetMergeModeC5(const NVDispEvoRec *pDispEvo, nvPopEvoSubDevMask(pDevEvo); } +static NvU32 EvoAllocSurfaceDescriptorC3( + NVDevEvoPtr pDevEvo, NVSurfaceDescriptor *pSurfaceDesc, + NvU32 memoryHandle, NvU32 localCtxDmaFlags, + NvU64 limit) +{ + return nvCtxDmaAlloc(pDevEvo, &pSurfaceDesc->ctxDmaHandle, + memoryHandle, + localCtxDmaFlags, limit); +} + +static void EvoFreeSurfaceDescriptorC3( + NVDevEvoPtr pDevEvo, + NvU32 deviceHandle, + NVSurfaceDescriptor *pSurfaceDesc) +{ + nvCtxDmaFree(pDevEvo, deviceHandle, &pSurfaceDesc->ctxDmaHandle); +} + +static NvU32 EvoBindSurfaceDescriptorC3( + NVDevEvoPtr pDevEvo, + NVEvoChannelPtr pChannel, + NVSurfaceDescriptor *pSurfaceDesc) +{ + return nvCtxDmaBind(pDevEvo, pChannel, pSurfaceDesc->ctxDmaHandle); +} + NVEvoHAL nvEvoC3 = { EvoSetRasterParamsC3, /* SetRasterParams */ EvoSetProcAmpC3, /* SetProcAmp */ EvoSetHeadControlC3, /* SetHeadControl */ EvoSetHeadRefClkC3, /* SetHeadRefClk */ EvoHeadSetControlORC3, /* HeadSetControlOR */ - EvoORSetControlC3, /* ORSetControl */ + nvEvoORSetControlC3, /* ORSetControl */ EvoHeadSetDisplayIdC3, /* HeadSetDisplayId */ EvoSetUsageBoundsC3, /* SetUsageBounds */ - EvoUpdateC3, /* Update */ - EvoIsModePossibleC3, /* IsModePossible */ - EvoPrePostIMPC3, /* PrePostIMP */ - EvoSetNotifierC3, /* SetNotifier */ + nvEvoUpdateC3, /* Update */ + nvEvoIsModePossibleC3, /* IsModePossible */ + nvEvoPrePostIMPC3, /* PrePostIMP */ + nvEvoSetNotifierC3, /* SetNotifier */ EvoGetCapabilitiesC3, /* GetCapabilities */ EvoFlipC3, /* Flip */ EvoFlipTransitionWARC3, /* FlipTransitionWAR */ @@ -7733,45 +7891,54 @@ NVEvoHAL nvEvoC3 = { EvoSetViewportPointInC3, /* SetViewportPointIn */ EvoSetViewportInOutC3, /* SetViewportInOut */ EvoSetCursorImageC3, /* SetCursorImage */ - EvoValidateCursorSurfaceC3, /* ValidateCursorSurface */ + nvEvoValidateCursorSurfaceC3, /* ValidateCursorSurface */ EvoValidateWindowFormatC3, /* ValidateWindowFormat */ - EvoInitCompNotifierC3, /* InitCompNotifier */ - EvoIsCompNotifierCompleteC3, /* IsCompNotifierComplete */ - EvoWaitForCompNotifierC3, /* WaitForCompNotifier */ + nvEvoInitCompNotifierC3, /* InitCompNotifier */ + nvEvoIsCompNotifierCompleteC3, /* IsCompNotifierComplete */ + nvEvoWaitForCompNotifierC3, /* WaitForCompNotifier */ EvoSetDitherC3, /* SetDither */ EvoSetStallLockC3, /* SetStallLock */ EvoSetDisplayRateC3, /* SetDisplayRate */ EvoInitChannelC3, /* InitChannel */ NULL, /* InitDefaultLut */ EvoInitWindowMappingC3, /* InitWindowMapping */ - EvoIsChannelIdleC3, /* IsChannelIdle */ - EvoIsChannelMethodPendingC3, /* IsChannelMethodPending */ - EvoForceIdleSatelliteChannelC3, /* ForceIdleSatelliteChannel */ - EvoForceIdleSatelliteChannelIgnoreLockC3, /* ForceIdleSatelliteChannelIgnoreLock */ - EvoAccelerateChannelC3, /* AccelerateChannel */ - EvoResetChannelAcceleratorsC3, /* ResetChannelAccelerators */ - EvoAllocRmCtrlObjectC3, /* AllocRmCtrlObject */ - EvoFreeRmCtrlObjectC3, /* FreeRmCtrlObject */ - EvoSetImmPointOutC3, /* SetImmPointOut */ + nvEvoIsChannelIdleC3, /* IsChannelIdle */ + nvEvoIsChannelMethodPendingC3, /* IsChannelMethodPending */ + nvEvoForceIdleSatelliteChannelC3, /* ForceIdleSatelliteChannel */ + nvEvoForceIdleSatelliteChannelIgnoreLockC3, /* ForceIdleSatelliteChannelIgnoreLock */ + nvEvoAccelerateChannelC3, /* AccelerateChannel */ + nvEvoResetChannelAcceleratorsC3, /* ResetChannelAccelerators */ + nvEvoAllocRmCtrlObjectC3, /* AllocRmCtrlObject */ + nvEvoFreeRmCtrlObjectC3, /* FreeRmCtrlObject */ + nvEvoSetImmPointOutC3, /* SetImmPointOut */ EvoStartHeadCRC32CaptureC3, /* StartCRC32Capture */ EvoStopHeadCRC32CaptureC3, /* StopCRC32Capture */ - EvoQueryHeadCRC32_C3, /* QueryCRC32 */ - EvoGetScanLineC3, /* GetScanLine */ + nvEvoQueryHeadCRC32_C3, /* QueryCRC32 */ + nvEvoGetScanLineC3, /* GetScanLine */ NULL, /* ConfigureVblankSyncObject */ nvEvo1SetDscParams, /* SetDscParams */ NULL, /* EnableMidFrameAndDWCFWatermark */ - EvoGetActiveViewportOffsetC3, /* GetActiveViewportOffset */ + nvEvoGetActiveViewportOffsetC3, /* GetActiveViewportOffset */ NULL, /* ClearSurfaceUsage */ EvoComputeWindowScalingTapsC3, /* ComputeWindowScalingTaps */ - EvoGetWindowScalingCapsC3, /* GetWindowScalingCaps */ + nvEvoGetWindowScalingCapsC3, /* GetWindowScalingCaps */ NULL, /* SetMergeMode */ + EvoAllocSurfaceDescriptorC3, /* AllocSurfaceDescriptor */ + EvoFreeSurfaceDescriptorC3, /* FreeSurfaceDescriptor */ + EvoBindSurfaceDescriptorC3, /* BindSurfaceDescriptor */ + NULL, /* SetTmoLutSurfaceAddress */ + NULL, /* SetILUTSurfaceAddress */ + EvoSetISOSurfaceAddressC3, /* SetISOSurfaceAddress */ + EvoSetCoreNotifierSurfaceAddressAndControlC3, /* SetCoreNotifierSurfaceAddressAndControl */ + EvoSetWinNotifierSurfaceAddressAndControlC3, /* SetWinNotifierSurfaceAddressAndControl */ + NULL, /* SetSemaphoreSurfaceAddressAndControl */ + NULL, /* SetAcqSemaphoreSurfaceAddressAndControl */ { /* caps */ TRUE, /* supportsNonInterlockedUsageBoundsUpdate */ TRUE, /* supportsDisplayRate */ FALSE, /* supportsFlipLockRGStatus */ FALSE, /* needDefaultLutSurface */ FALSE, /* hasUnorm10OLUT */ - TRUE, /* supportsDigitalVibrance */ FALSE, /* supportsImageSharpening */ FALSE, /* supportsHDMIVRR */ FALSE, /* supportsCoreChannelSurface */ @@ -7783,6 +7950,7 @@ NVEvoHAL nvEvoC3 = { FALSE, /* supportsVblankSyncObjects */ FALSE, /* requiresScalingTapsInBothDimensions */ FALSE, /* supportsMergeMode */ + FALSE, /* supportsHDMI10BPC */ NV_EVO3_SUPPORTED_DITHERING_MODES, /* supportedDitheringModes */ sizeof(NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS), /* impStructSize */ NV_EVO_SCALER_2TAPS, /* minScalerTaps */ @@ -7796,61 +7964,70 @@ NVEvoHAL nvEvoC5 = { EvoSetHeadControlC3, /* SetHeadControl */ EvoSetHeadRefClkC3, /* SetHeadRefClk */ EvoHeadSetControlORC5, /* HeadSetControlOR */ - EvoORSetControlC3, /* ORSetControl */ + nvEvoORSetControlC3, /* ORSetControl */ EvoHeadSetDisplayIdC3, /* HeadSetDisplayId */ - EvoSetUsageBoundsC5, /* SetUsageBounds */ - EvoUpdateC3, /* Update */ - EvoIsModePossibleC3, /* IsModePossible */ - EvoPrePostIMPC3, /* PrePostIMP */ - EvoSetNotifierC3, /* SetNotifier */ + nvEvoSetUsageBoundsC5, /* SetUsageBounds */ + nvEvoUpdateC3, /* Update */ + nvEvoIsModePossibleC3, /* IsModePossible */ + nvEvoPrePostIMPC3, /* PrePostIMP */ + nvEvoSetNotifierC3, /* SetNotifier */ EvoGetCapabilitiesC5, /* GetCapabilities */ EvoFlipC5, /* Flip */ EvoFlipTransitionWARC5, /* FlipTransitionWAR */ - EvoFillLUTSurfaceC5, /* FillLUTSurface */ + nvEvoFillLUTSurfaceC5, /* FillLUTSurface */ EvoSetLUTContextDmaC5, /* SetLUTContextDma */ EvoSetOutputScalerC3, /* SetOutputScaler */ EvoSetViewportPointInC3, /* SetViewportPointIn */ EvoSetViewportInOutC5, /* SetViewportInOut */ EvoSetCursorImageC3, /* SetCursorImage */ - EvoValidateCursorSurfaceC3, /* ValidateCursorSurface */ + nvEvoValidateCursorSurfaceC3, /* ValidateCursorSurface */ EvoValidateWindowFormatC5, /* ValidateWindowFormat */ - EvoInitCompNotifierC3, /* InitCompNotifier */ - EvoIsCompNotifierCompleteC3, /* IsCompNotifierComplete */ - EvoWaitForCompNotifierC3, /* WaitForCompNotifier */ + nvEvoInitCompNotifierC3, /* InitCompNotifier */ + nvEvoIsCompNotifierCompleteC3, /* IsCompNotifierComplete */ + nvEvoWaitForCompNotifierC3, /* WaitForCompNotifier */ EvoSetDitherC3, /* SetDither */ EvoSetStallLockC3, /* SetStallLock */ EvoSetDisplayRateC3, /* SetDisplayRate */ EvoInitChannelC5, /* InitChannel */ - EvoInitDefaultLutC5, /* InitDefaultLut */ - EvoInitWindowMappingC5, /* InitWindowMapping */ - EvoIsChannelIdleC3, /* IsChannelIdle */ - EvoIsChannelMethodPendingC3, /* IsChannelMethodPending */ - EvoForceIdleSatelliteChannelC3, /* ForceIdleSatelliteChannel */ - EvoForceIdleSatelliteChannelIgnoreLockC3, /* ForceIdleSatelliteChannelIgnoreLock */ - EvoAccelerateChannelC3, /* AccelerateChannel */ - EvoResetChannelAcceleratorsC3, /* ResetChannelAccelerators */ - EvoAllocRmCtrlObjectC3, /* AllocRmCtrlObject */ - EvoFreeRmCtrlObjectC3, /* FreeRmCtrlObject */ - EvoSetImmPointOutC3, /* SetImmPointOut */ + nvEvoInitDefaultLutC5, /* InitDefaultLut */ + nvEvoInitWindowMappingC5, /* InitWindowMapping */ + nvEvoIsChannelIdleC3, /* IsChannelIdle */ + nvEvoIsChannelMethodPendingC3, /* IsChannelMethodPending */ + nvEvoForceIdleSatelliteChannelC3, /* ForceIdleSatelliteChannel */ + nvEvoForceIdleSatelliteChannelIgnoreLockC3, /* ForceIdleSatelliteChannelIgnoreLock */ + nvEvoAccelerateChannelC3, /* AccelerateChannel */ + nvEvoResetChannelAcceleratorsC3, /* ResetChannelAccelerators */ + nvEvoAllocRmCtrlObjectC3, /* AllocRmCtrlObject */ + nvEvoFreeRmCtrlObjectC3, /* FreeRmCtrlObject */ + nvEvoSetImmPointOutC3, /* SetImmPointOut */ EvoStartHeadCRC32CaptureC3, /* StartCRC32Capture */ EvoStopHeadCRC32CaptureC3, /* StopCRC32Capture */ - EvoQueryHeadCRC32_C3, /* QueryCRC32 */ - EvoGetScanLineC3, /* GetScanLine */ + nvEvoQueryHeadCRC32_C3, /* QueryCRC32 */ + nvEvoGetScanLineC3, /* GetScanLine */ NULL, /* ConfigureVblankSyncObject */ EvoSetDscParamsC5, /* SetDscParams */ EvoEnableMidFrameAndDWCFWatermarkC5, /* EnableMidFrameAndDWCFWatermark */ - EvoGetActiveViewportOffsetC3, /* GetActiveViewportOffset */ + nvEvoGetActiveViewportOffsetC3, /* GetActiveViewportOffset */ NULL, /* ClearSurfaceUsage */ - EvoComputeWindowScalingTapsC5, /* ComputeWindowScalingTaps */ - EvoGetWindowScalingCapsC3, /* GetWindowScalingCaps */ + nvEvoComputeWindowScalingTapsC5, /* ComputeWindowScalingTaps */ + nvEvoGetWindowScalingCapsC3, /* GetWindowScalingCaps */ EvoSetMergeModeC5, /* SetMergeMode */ + EvoAllocSurfaceDescriptorC3, /* AllocSurfaceDescriptor */ + EvoFreeSurfaceDescriptorC3, /* FreeSurfaceDescriptor */ + EvoBindSurfaceDescriptorC3, /* BindSurfaceDescriptor */ + EvoSetTmoLutSurfaceAddressC5, /* SetTmoLutSurfaceAddress */ + EvoSetILUTSurfaceAddressC5, /* SetILUTSurfaceAddress */ + EvoSetISOSurfaceAddressC3, /* SetISOSurfaceAddress */ + EvoSetCoreNotifierSurfaceAddressAndControlC3, /* SetCoreNotifierSurfaceAddressAndControl */ + EvoSetWinNotifierSurfaceAddressAndControlC3, /* SetWinNotifierSurfaceAddressAndControl */ + NULL, /* SetSemaphoreSurfaceAddressAndControl */ + NULL, /* SetAcqSemaphoreSurfaceAddressAndControl */ { /* caps */ TRUE, /* supportsNonInterlockedUsageBoundsUpdate */ TRUE, /* supportsDisplayRate */ FALSE, /* supportsFlipLockRGStatus */ TRUE, /* needDefaultLutSurface */ TRUE, /* hasUnorm10OLUT */ - TRUE, /* supportsDigitalVibrance */ FALSE, /* supportsImageSharpening */ TRUE, /* supportsHDMIVRR */ FALSE, /* supportsCoreChannelSurface */ @@ -7862,6 +8039,7 @@ NVEvoHAL nvEvoC5 = { FALSE, /* supportsVblankSyncObjects */ FALSE, /* requiresScalingTapsInBothDimensions */ TRUE, /* supportsMergeMode */ + FALSE, /* supportsHDMI10BPC */ NV_EVO3_SUPPORTED_DITHERING_MODES, /* supportedDitheringModes */ sizeof(NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS), /* impStructSize */ NV_EVO_SCALER_2TAPS, /* minScalerTaps */ @@ -7877,59 +8055,68 @@ NVEvoHAL nvEvoC6 = { EvoHeadSetControlORC5, /* HeadSetControlOR */ EvoORSetControlC6, /* ORSetControl */ EvoHeadSetDisplayIdC3, /* HeadSetDisplayId */ - EvoSetUsageBoundsC5, /* SetUsageBounds */ - EvoUpdateC3, /* Update */ - EvoIsModePossibleC3, /* IsModePossible */ - EvoPrePostIMPC3, /* PrePostIMP */ - EvoSetNotifierC3, /* SetNotifier */ - EvoGetCapabilitiesC6, /* GetCapabilities */ - EvoFlipC6, /* Flip */ - EvoFlipTransitionWARC6, /* FlipTransitionWAR */ - EvoFillLUTSurfaceC5, /* FillLUTSurface */ + nvEvoSetUsageBoundsC5, /* SetUsageBounds */ + nvEvoUpdateC3, /* Update */ + nvEvoIsModePossibleC3, /* IsModePossible */ + nvEvoPrePostIMPC3, /* PrePostIMP */ + nvEvoSetNotifierC3, /* SetNotifier */ + nvEvoGetCapabilitiesC6, /* GetCapabilities */ + nvEvoFlipC6, /* Flip */ + nvEvoFlipTransitionWARC6, /* FlipTransitionWAR */ + nvEvoFillLUTSurfaceC5, /* FillLUTSurface */ EvoSetLUTContextDmaC5, /* SetLUTContextDma */ EvoSetOutputScalerC3, /* SetOutputScaler */ EvoSetViewportPointInC3, /* SetViewportPointIn */ EvoSetViewportInOutC5, /* SetViewportInOut */ EvoSetCursorImageC3, /* SetCursorImage */ - EvoValidateCursorSurfaceC3, /* ValidateCursorSurface */ - EvoValidateWindowFormatC6, /* ValidateWindowFormat */ - EvoInitCompNotifierC3, /* InitCompNotifier */ - EvoIsCompNotifierCompleteC3, /* IsCompNotifierComplete */ - EvoWaitForCompNotifierC3, /* WaitForCompNotifier */ + nvEvoValidateCursorSurfaceC3, /* ValidateCursorSurface */ + nvEvoValidateWindowFormatC6, /* ValidateWindowFormat */ + nvEvoInitCompNotifierC3, /* InitCompNotifier */ + nvEvoIsCompNotifierCompleteC3, /* IsCompNotifierComplete */ + nvEvoWaitForCompNotifierC3, /* WaitForCompNotifier */ EvoSetDitherC3, /* SetDither */ EvoSetStallLockC3, /* SetStallLock */ EvoSetDisplayRateC3, /* SetDisplayRate */ EvoInitChannelC5, /* InitChannel */ - EvoInitDefaultLutC5, /* InitDefaultLut */ - EvoInitWindowMappingC5, /* InitWindowMapping */ - EvoIsChannelIdleC3, /* IsChannelIdle */ - EvoIsChannelMethodPendingC3, /* IsChannelMethodPending */ - EvoForceIdleSatelliteChannelC3, /* ForceIdleSatelliteChannel */ - EvoForceIdleSatelliteChannelIgnoreLockC3, /* ForceIdleSatelliteChannelIgnoreLock */ - EvoAccelerateChannelC3, /* AccelerateChannel */ - EvoResetChannelAcceleratorsC3, /* ResetChannelAccelerators */ - EvoAllocRmCtrlObjectC3, /* AllocRmCtrlObject */ - EvoFreeRmCtrlObjectC3, /* FreeRmCtrlObject */ - EvoSetImmPointOutC3, /* SetImmPointOut */ + nvEvoInitDefaultLutC5, /* InitDefaultLut */ + nvEvoInitWindowMappingC5, /* InitWindowMapping */ + nvEvoIsChannelIdleC3, /* IsChannelIdle */ + nvEvoIsChannelMethodPendingC3, /* IsChannelMethodPending */ + nvEvoForceIdleSatelliteChannelC3, /* ForceIdleSatelliteChannel */ + nvEvoForceIdleSatelliteChannelIgnoreLockC3, /* ForceIdleSatelliteChannelIgnoreLock */ + nvEvoAccelerateChannelC3, /* AccelerateChannel */ + nvEvoResetChannelAcceleratorsC3, /* ResetChannelAccelerators */ + nvEvoAllocRmCtrlObjectC3, /* AllocRmCtrlObject */ + nvEvoFreeRmCtrlObjectC3, /* FreeRmCtrlObject */ + nvEvoSetImmPointOutC3, /* SetImmPointOut */ EvoStartHeadCRC32CaptureC3, /* StartCRC32Capture */ EvoStopHeadCRC32CaptureC3, /* StopCRC32Capture */ - EvoQueryHeadCRC32_C3, /* QueryCRC32 */ - EvoGetScanLineC3, /* GetScanLine */ + nvEvoQueryHeadCRC32_C3, /* QueryCRC32 */ + nvEvoGetScanLineC3, /* GetScanLine */ EvoConfigureVblankSyncObjectC6, /* ConfigureVblankSyncObject */ EvoSetDscParamsC5, /* SetDscParams */ NULL, /* EnableMidFrameAndDWCFWatermark */ - EvoGetActiveViewportOffsetC3, /* GetActiveViewportOffset */ + nvEvoGetActiveViewportOffsetC3, /* GetActiveViewportOffset */ NULL, /* ClearSurfaceUsage */ - EvoComputeWindowScalingTapsC5, /* ComputeWindowScalingTaps */ - EvoGetWindowScalingCapsC3, /* GetWindowScalingCaps */ + nvEvoComputeWindowScalingTapsC5, /* ComputeWindowScalingTaps */ + nvEvoGetWindowScalingCapsC3, /* GetWindowScalingCaps */ EvoSetMergeModeC5, /* SetMergeMode */ + EvoAllocSurfaceDescriptorC3, /* AllocSurfaceDescriptor */ + EvoFreeSurfaceDescriptorC3, /* FreeSurfaceDescriptor */ + EvoBindSurfaceDescriptorC3, /* BindSurfaceDescriptor */ + EvoSetTmoLutSurfaceAddressC5, /* SetTmoLutSurfaceAddress */ + EvoSetILUTSurfaceAddressC5, /* SetILUTSurfaceAddress */ + EvoSetISOSurfaceAddressC3, /* SetISOSurfaceAddress */ + EvoSetCoreNotifierSurfaceAddressAndControlC3, /* SetCoreNotifierSurfaceAddressAndControl */ + EvoSetWinNotifierSurfaceAddressAndControlC3, /* SetWinNotifierSurfaceAddressAndControl */ + EvoSetSemaphoreSurfaceAddressAndControlC6, /* SetSemaphoreSurfaceAddressAndControl */ + EvoSetAcqSemaphoreSurfaceAddressAndControlC6, /* SetAcqSemaphoreSurfaceAddressAndControl */ { /* caps */ TRUE, /* supportsNonInterlockedUsageBoundsUpdate */ TRUE, /* supportsDisplayRate */ FALSE, /* supportsFlipLockRGStatus */ TRUE, /* needDefaultLutSurface */ TRUE, /* hasUnorm10OLUT */ - TRUE, /* supportsDigitalVibrance */ FALSE, /* supportsImageSharpening */ TRUE, /* supportsHDMIVRR */ FALSE, /* supportsCoreChannelSurface */ @@ -7941,6 +8128,7 @@ NVEvoHAL nvEvoC6 = { TRUE, /* supportsVblankSyncObjects */ FALSE, /* requiresScalingTapsInBothDimensions */ TRUE, /* supportsMergeMode */ + TRUE, /* supportsHDMI10BPC */ NV_EVO3_SUPPORTED_DITHERING_MODES, /* supportedDitheringModes */ sizeof(NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS), /* impStructSize */ NV_EVO_SCALER_2TAPS, /* minScalerTaps */ diff --git a/src/nvidia-modeset/src/nvkms-flip.c b/src/nvidia-modeset/src/nvkms-flip.c index cf0178e1b3..96d018b1d1 100644 --- a/src/nvidia-modeset/src/nvkms-flip.c +++ b/src/nvidia-modeset/src/nvkms-flip.c @@ -28,6 +28,7 @@ #include "nvkms-utils-flip.h" #include "nvkms-prealloc.h" #include "nvkms-private.h" +#include "nvkms-utils.h" #include "nvkms-vrr.h" #include "nvkms-dpy.h" #include "nvkms-rm.h" @@ -67,9 +68,11 @@ NvBool nvCheckFlipPermissions( layerMask = allLayersMask; } - /* Changing viewPortIn requires permission to alter all layers. */ + /* Changing viewPortIn or LUT requires permission to alter all layers. */ - if (pParams->viewPortIn.specified && (layerMask != allLayersMask)) { + if ((layerMask != allLayersMask) && ((pParams->viewPortIn.specified) || + (pParams->lut.input.specified) || + (pParams->lut.output.specified))) { return FALSE; } @@ -123,27 +126,48 @@ static NvBool UpdateProposedFlipStateOneApiHead( const struct NvKmsFlipCommonParams *pParams, NVProposedFlipStateOneApiHead *pProposedApiHead) { + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; const NVDispApiHeadStateEvoRec *pApiHeadState = &pDispEvo->apiHeadState[apiHead]; + const NVDpyEvoRec *pDpyEvo = + nvGetOneArbitraryDpyEvo(pApiHeadState->activeDpys, pDispEvo); + NvU32 layer; if (pParams->tf.specified) { - const NVDpyEvoRec *pDpyEvo = - nvGetOneArbitraryDpyEvo(pApiHeadState->activeDpys, pDispEvo); - pProposedApiHead->dirty.hdr = TRUE; pProposedApiHead->hdr.tf = pParams->tf.val; + } - // If enabling HDR... - // XXX HDR TODO: Handle other transfer functions - if (pParams->tf.val == NVKMS_OUTPUT_TF_PQ) { - // Cannot be an SLI configuration. - // XXX HDR TODO: Test SLI Mosaic + HDR and remove this check - if (pDispEvo->pDevEvo->numSubDevices > 1) { - return FALSE; + if (pParams->colorimetry.specified) { + pProposedApiHead->dirty.hdr = TRUE; + pProposedApiHead->hdr.colorimetry = pParams->colorimetry.val; + } + + if (pParams->hdrInfoFrame.specified) { + pProposedApiHead->dirty.hdr = TRUE; + pProposedApiHead->hdr.infoFrameOverride = + pParams->hdrInfoFrame.enabled; + } + + for (layer = 0; layer < pDevEvo->apiHead[apiHead].numLayers; layer++) { + if (pParams->layer[layer].hdr.specified) { + pProposedApiHead->dirty.hdr = TRUE; + if (pParams->layer[layer].hdr.enabled) { + pProposedApiHead->hdr.staticMetadataLayerMask |= + 1 << layer; + } else { + pProposedApiHead->hdr.staticMetadataLayerMask &= + ~(1 << layer); } + } + } - // Sink must support HDR. - if (!nvIsHDRCapableHead(pDispEvo, apiHead)) { + if (pProposedApiHead->dirty.hdr) { + // If enabling HDR output TF... + if (pProposedApiHead->hdr.tf == NVKMS_OUTPUT_TF_PQ) { + // Cannot be an SLI configuration. + // XXX HDR TODO: Test SLI Mosaic + HDR and remove this check + if (pDevEvo->numSubDevices > 1) { return FALSE; } @@ -154,7 +178,24 @@ static NvBool UpdateProposedFlipStateOneApiHead( } } - if (!nvChooseColorRangeEvo(pParams->tf.val, + // If enabling HDR signaling... + // XXX HDR TODO: Handle other colorimetries + if (pProposedApiHead->hdr.infoFrameOverride || + (pProposedApiHead->hdr.staticMetadataLayerMask != 0) || + (pProposedApiHead->hdr.colorimetry == NVKMS_OUTPUT_COLORIMETRY_BT2100)) { + const NVDpyEvoRec *pDpyEvoIter; + + // All dpys on apiHead must support HDR. + FOR_ALL_EVO_DPYS(pDpyEvoIter, + pApiHeadState->activeDpys, + pDispEvo) { + if (!nvDpyIsHDRCapable(pDpyEvoIter)) { + return FALSE; + } + } + } + + if (!nvChooseColorRangeEvo(pProposedApiHead->hdr.colorimetry, pDpyEvo->requestedColorRange, pProposedApiHead->hdr.colorSpace, pProposedApiHead->hdr.colorBpc, @@ -168,56 +209,12 @@ static NvBool UpdateProposedFlipStateOneApiHead( pProposedApiHead->viewPortPointIn = pParams->viewPortIn.point; } - return TRUE; -} - -void nvCancelSDRTransitionTimer(NVDispApiHeadStateEvoRec *pApiHeadState) -{ - nvkms_free_timer(pApiHeadState->hdrToSdrTransitionTimer); - pApiHeadState->hdrToSdrTransitionTimer = NULL; -} - -static void SDRTransition(void *dataPtr, NvU32 apiHead) -{ - NvU32 head; - NVDispEvoRec *pDispEvo = dataPtr; - NVDispApiHeadStateEvoRec *pApiHeadState = - &pDispEvo->apiHeadState[apiHead]; - NVDpyEvoPtr pDpyEvo = - nvGetOneArbitraryDpyEvo(pApiHeadState->activeDpys, pDispEvo); - - nvCancelSDRTransitionTimer(pApiHeadState); - - if (pDpyEvo == NULL) { - return; - } - - nvAssert(pApiHeadState->hwHeadsMask != 0); - - FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { - NVDispHeadStateEvoRec *pHeadState = - &pDispEvo->headState[head]; - nvAssert(pHeadState->hdr.outputState == - NVKMS_HDR_OUTPUT_STATE_TRANSITIONING_TO_SDR); - pHeadState->hdr.outputState = NVKMS_HDR_OUTPUT_STATE_SDR; + if (!nvValidateSetLutCommonParams(pDispEvo->pDevEvo, &pParams->lut)) { + return FALSE; } + pProposedApiHead->lut = pParams->lut; - nvUpdateInfoFrames(pDpyEvo); -} - -static -void ScheduleSDRTransitionTimer(NVDispEvoRec *pDispEvo, const NvU32 apiHead) -{ - NVDispApiHeadStateEvoRec *pApiHeadState = - &pDispEvo->apiHeadState[apiHead]; - - nvAssert(!pApiHeadState->hdrToSdrTransitionTimer); - - pApiHeadState->hdrToSdrTransitionTimer = - nvkms_alloc_timer(SDRTransition, - pDispEvo, - apiHead, - 2000000 /* 2 seconds */); + return TRUE; } static NvBool GetAllowVrr(const NVDevEvoRec *pDevEvo, @@ -339,6 +336,11 @@ static void InitNvKmsFlipWorkArea(const NVDevEvoRec *pDevEvo, &pDispEvo->apiHeadState[apiHead]; pProposedApiHead->hdr.tf = pApiHeadState->tf; + pProposedApiHead->hdr.colorimetry = pApiHeadState->colorimetry; + pProposedApiHead->hdr.infoFrameOverride = + pApiHeadState->hdrInfoFrameOverride; + pProposedApiHead->hdr.staticMetadataLayerMask = + pApiHeadState->hdrStaticMetadataLayerMask; pProposedApiHead->hdr.colorSpace = pApiHeadState->attributes.colorSpace; pProposedApiHead->hdr.colorBpc = @@ -348,6 +350,11 @@ static void InitNvKmsFlipWorkArea(const NVDevEvoRec *pDevEvo, pProposedApiHead->viewPortPointIn = pApiHeadState->viewPortPointIn; + + pProposedApiHead->lut.input.specified = + FALSE; + pProposedApiHead->lut.output.specified = + FALSE; } } } @@ -373,6 +380,14 @@ static void FlipEvoOneApiHead(NVDispEvoRec *pDispEvo, nvAssert(nvApiHeadIsActive(pDispEvo, apiHead)); + if (pProposedApiHead->lut.input.specified || + pProposedApiHead->lut.output.specified) { + /* Set LUT settings */ + nvEvoSetLut(pDispEvo, apiHead, FALSE /* kickoff */, + &pProposedApiHead->lut); + nvEvoStageLUTNotifier(pDispEvo, apiHead); + } + FOR_EACH_EVO_HW_HEAD_IN_MASK(pApiHeadState->hwHeadsMask, head) { nvFlipEvoOneHead(pDevEvo, sd, head, pHdrInfo, &pWorkArea->sd[sd].head[head].newState, @@ -384,10 +399,17 @@ static void FlipEvoOneApiHead(NVDispEvoRec *pDispEvo, nvUpdateCurrentHardwareColorSpaceAndRangeEvo( pDispEvo, head, + pProposedApiHead->hdr.colorimetry, pProposedApiHead->hdr.colorSpace, pProposedApiHead->hdr.colorRange, pUpdateState); } + + if (pProposedApiHead->lut.input.specified || + pProposedApiHead->lut.output.specified) { + /* Update current LUT to hardware */ + nvEvoSetLUTContextDma(pDispEvo, head, pUpdateState); + } } if (pProposedApiHead->dirty.hdr) { @@ -398,14 +420,15 @@ static void FlipEvoOneApiHead(NVDispEvoRec *pDispEvo, pApiHeadState->attributes.colorRange = pProposedApiHead->hdr.colorRange; - if (pProposedApiHead->hdr.tf == NVKMS_OUTPUT_TF_PQ) { - nvCancelSDRTransitionTimer(pApiHeadState); - } else if (pApiHeadState->tf == NVKMS_OUTPUT_TF_PQ) { - ScheduleSDRTransitionTimer(pDispEvo, apiHead); - } - pApiHeadState->tf = pProposedApiHead->hdr.tf; + pApiHeadState->colorimetry = pProposedApiHead->hdr.colorimetry; + + pApiHeadState->hdrInfoFrameOverride = + pProposedApiHead->hdr.infoFrameOverride; + pApiHeadState->hdrStaticMetadataLayerMask = + pProposedApiHead->hdr.staticMetadataLayerMask; + nvUpdateInfoFrames(pDpyEvo); } @@ -488,6 +511,7 @@ NvBool nvFlipEvo(NVDevEvoPtr pDevEvo, NvU32 apiHead, sd; NvBool applyAllowVrr = FALSE; NvBool ret = FALSE; + enum NvKmsFlipResult result = NV_KMS_FLIP_RESULT_INVALID_PARAMS; NvBool changed = FALSE; NVDispEvoPtr pDispEvo; const NvBool allowVrr = @@ -565,8 +589,46 @@ NvBool nvFlipEvo(NVDevEvoPtr pDevEvo, goto done; } + /* XXX: Fail flip if LUT update in progress. + * + * Really, we should have a more robust system for this, but currently, the + * only user of the LUT parameter to the flip IOCTL is nvidia-drm, which + * waits for flips to be complete anyways. We should actually find a way to + * properly queue as many LUT-changing flips as we support queued flips in + * general. + * + * This failure returns NV_KMS_FLIP_RESULT_IN_PROGRESS rather than + * NV_KMS_FLIP_RESULT_INVALID_PARAMS. + * + * See bug 4054546 for efforts to update this system. + */ + for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { + pDispEvo = pDevEvo->gpus[sd].pDispEvo; + for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + const NVProposedFlipStateOneApiHead *pProposedApiHead = + &pWorkArea->disp[sd].apiHead[apiHead].proposedFlipState; + + if ((pProposedApiHead->lut.input.specified || + pProposedApiHead->lut.output.specified) && + !nvEvoIsLUTNotifierComplete(pDispEvo, apiHead)) { + + if (commit) { + nvEvoLogDispDebug( + pDispEvo, + EVO_LOG_ERROR, + "Flip request with LUT parameter on API Head %d while LUT update outstanding", + apiHead); + } + + result = NV_KMS_FLIP_RESULT_IN_PROGRESS; + goto done; + } + } + } + if (!commit) { ret = NV_TRUE; + result = NV_KMS_FLIP_RESULT_SUCCESS; goto done; } @@ -582,6 +644,7 @@ NvBool nvFlipEvo(NVDevEvoPtr pDevEvo, */ ret = TRUE; + result = NV_KMS_FLIP_RESULT_SUCCESS; nvPreFlip(pDevEvo, pWorkArea, applyAllowVrr, allowVrr, skipUpdate); @@ -600,6 +663,12 @@ NvBool nvFlipEvo(NVDevEvoPtr pDevEvo, nvkms_memset(&pWorkArea->updateState, 0, sizeof(pWorkArea->updateState)); + /* + * Ensure that we only commit the LUT notifiers staged in this + * nvFlipEvo call. + */ + nvEvoClearStagedLUTNotifiers(pDispEvo); + for (apiHead = 0; apiHead < NVKMS_MAX_HEADS_PER_DISP; apiHead++) { if (!nvApiHeadIsActive(pDispEvo, apiHead) || ((NVBIT(apiHead) & flip2Heads1OrApiHeadsMask) != 0x0)) { @@ -611,8 +680,7 @@ NvBool nvFlipEvo(NVDevEvoPtr pDevEvo, } if (!skipUpdate) { - pDevEvo->hal->Update(pDevEvo, &pWorkArea->updateState, - TRUE /* releaseElv */); + nvEvoFlipUpdate(pDispEvo, &pWorkArea->updateState); } } @@ -626,6 +694,9 @@ NvBool nvFlipEvo(NVDevEvoPtr pDevEvo, done: nvPreallocRelease(pDevEvo, PREALLOC_TYPE_FLIP_WORK_AREA); + if (reply) { + reply->flipResult = result; + } return ret; } @@ -1023,7 +1094,7 @@ void nvIdleLayerChannels(NVDevEvoRec *pDevEvo, } if (!allIdle) { - if (nvExceedsTimeoutUSec(&startTime, timeout)) { + if (nvExceedsTimeoutUSec(pDevEvo, &startTime, timeout)) { break; } nvkms_yield(); diff --git a/src/nvidia-modeset/src/nvkms-framelock.c b/src/nvidia-modeset/src/nvkms-framelock.c index 199bfa2975..6fa3db20b3 100644 --- a/src/nvidia-modeset/src/nvkms-framelock.c +++ b/src/nvidia-modeset/src/nvkms-framelock.c @@ -102,9 +102,9 @@ FrameLockHandleSyncEvent(void *dataPtr, NvU32 dataU32) * This function is registered as a kernel callback function from * resman. * - * However, it is called with resman's context (alternate stack, - * resman locks held, etc). Schedule deferred work, so that we can - * process the event without resman's encumbrances. + * However, it is called with resman's context (resman locks held, etc). + * Schedule deferred work, so that we can process the event without resman's + * encumbrances. */ static void FrameLockEvent(void *arg, void *pEventDataVoid, NvU32 hEvent, diff --git a/src/nvidia-modeset/src/nvkms-hdmi.c b/src/nvidia-modeset/src/nvkms-hdmi.c index c5dc04b907..6414dbcbc3 100644 --- a/src/nvidia-modeset/src/nvkms-hdmi.c +++ b/src/nvidia-modeset/src/nvkms-hdmi.c @@ -47,6 +47,9 @@ #define CAP_HDMI_SUPPORT_GPU 0x00000001 #define CAP_HDMI_SUPPORT_MONITOR 0x00000002 +#define CAP_HDMI_SUPPORT_MONITOR_48_BPP 0x00000004 +#define CAP_HDMI_SUPPORT_MONITOR_36_BPP 0x00000008 +#define CAP_HDMI_SUPPORT_MONITOR_30_BPP 0x00000010 static inline const NVT_EDID_CEA861_INFO *GetExt861(const NVParsedEdidEvoRec *pParsedEdid, int extIndex) @@ -65,15 +68,16 @@ static inline const NVT_EDID_CEA861_INFO *GetExt861(const NVParsedEdidEvoRec *pP */ static void CalculateVideoInfoFrameColorFormat( const NVAttributesSetEvoRec *pAttributesSet, - enum NvKmsOutputTf tf, + enum NvKmsOutputColorimetry colorimetry, const NvU32 hdTimings, NVT_VIDEO_INFOFRAME_CTRL *pCtrl) { /* - * If NVKMS_OUTPUT_TF_PQ is enabled, we expect the colorSpace is RGB. This - * is enforced when the colorSpace is selected. + * If NVKMS_OUTPUT_COLORIMETRY_BT2100 is enabled, we expect the colorSpace + * is RGB. This is enforced when the colorSpace is selected. + * XXX HDR TODO: Support YUV */ - nvAssert((tf != NVKMS_OUTPUT_TF_PQ) || + nvAssert((colorimetry != NVKMS_OUTPUT_COLORIMETRY_BT2100) || (pAttributesSet->colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB)); @@ -99,7 +103,7 @@ static void CalculateVideoInfoFrameColorFormat( // sets video infoframe colorimetry. switch (pAttributesSet->colorSpace) { case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB: - if (tf == NVKMS_OUTPUT_TF_PQ) { + if (colorimetry == NVKMS_OUTPUT_COLORIMETRY_BT2100) { pCtrl->colorimetry = NVT_COLORIMETRY_BT2020RGB; } else { pCtrl->colorimetry = NVT_COLORIMETRY_RGB; @@ -177,7 +181,24 @@ static NvU32 GetHDMISupportCap(const NVDpyEvoRec *pDpyEvo) for (vsdbIndex = 0; vsdbIndex < pExt861->total_vsdb; vsdbIndex++) { if (pExt861->vsdb[vsdbIndex].ieee_id == NVT_CEA861_HDMI_IEEE_ID) { + const NVT_HDMI_LLC_VSDB_PAYLOAD *payload = + (const NVT_HDMI_LLC_VSDB_PAYLOAD *) + &pExt861->vsdb[vsdbIndex].vendor_data; + hdmiCap |= CAP_HDMI_SUPPORT_MONITOR; + + if (payload->DC_48bit) { + hdmiCap |= CAP_HDMI_SUPPORT_MONITOR_48_BPP; + } + + if (payload->DC_36bit) { + hdmiCap |= CAP_HDMI_SUPPORT_MONITOR_36_BPP; + } + + if (payload->DC_30bit) { + hdmiCap |= CAP_HDMI_SUPPORT_MONITOR_30_BPP; + } + return hdmiCap; } } @@ -200,6 +221,20 @@ NvBool nvDpyIsHdmiEvo(const NVDpyEvoRec *pDpyEvo) (hdmiCap & CAP_HDMI_SUPPORT_MONITOR)); } +/*! + * Returns whether the GPU and the display both support HDMI depth 30. + */ +NvBool nvDpyIsHdmiDepth30Evo(const NVDpyEvoRec *pDpyEvo) +{ + const NVDevEvoRec *pDevEvo = pDpyEvo->pDispEvo->pDevEvo; + NvU32 hdmiCap = GetHDMISupportCap(pDpyEvo); + + return nvkms_hdmi_deepcolor() && + nvDpyIsHdmiEvo(pDpyEvo) && + pDevEvo->hal->caps.supportsHDMI10BPC && + (hdmiCap & CAP_HDMI_SUPPORT_MONITOR_30_BPP); +} + /*! * Updates the display's HDMI 2.0 capabilities to the RM. */ @@ -414,6 +449,10 @@ static void SendInfoFrame(const NVDispEvoRec *pDispEvo, hdmiLibType = NVHDMIPKT_TYPE_VENDOR_SPECIFIC_INFOFRAME; hdmiPacketType = hdmi_pktType_VendorSpecInfoFrame; break; + case NVT_INFOFRAME_TYPE_DYNAMIC_RANGE_MASTERING: + hdmiLibType = NVHDMIPKT_TYPE_VENDOR_SPECIFIC_INFOFRAME; + hdmiPacketType = hdmi_pktType_DynamicRangeMasteringInfoFrame; + break; } /* @@ -495,10 +534,11 @@ static void SendVideoInfoFrame(const NVDispEvoRec *pDispEvo, NVT_STATUS status; - CalculateVideoInfoFrameColorFormat(pAttributesSet, - pDispEvo->headState[head].tf, - hdTimings, - &videoCtrl); + CalculateVideoInfoFrameColorFormat( + pAttributesSet, + pDispEvo->headState[head].colorimetry, + hdTimings, + &videoCtrl); status = NvTiming_ConstructVideoInfoframe(pEdidInfo, &videoCtrl, @@ -568,6 +608,68 @@ SendHDMI3DVendorSpecificInfoFrame(const NVDispEvoRec *pDispEvo, sizeof(vendorInfoFrame)); } +static void +SendHDRInfoFrame(const NVDispEvoRec *pDispEvo, const NvU32 head, + NVT_EDID_INFO *pEdidInfo) +{ + const NVDispHeadStateEvoRec *pHeadState = + &pDispEvo->headState[head]; + NVT_HDR_INFOFRAME hdrInfoFrame = { 0 }; + NVHDMIPKT_TC transmitControl; + const NVT_HDR_STATIC_METADATA *pHdrInfo = + &pEdidInfo->hdr_static_metadata_info; + + // Only send the HDMI HDR infoframe if the display supports HDR + if (!pHdrInfo->supported_eotf.smpte_st_2084_eotf || + (pHdrInfo->static_metadata_type != 1)) { + return; + } + + // XXX HDR is not supported with HDMI 3D due to both using VSI infoframes. + if (pEdidInfo->HDMI3DSupported) { + return; + } + + hdrInfoFrame.header.type = NVT_INFOFRAME_TYPE_DYNAMIC_RANGE_MASTERING; + hdrInfoFrame.header.version = NVT_VIDEO_INFOFRAME_VERSION_1; + hdrInfoFrame.header.length = sizeof(NVT_HDR_INFOFRAME) - + sizeof(NVT_INFOFRAME_HEADER); + + if (pHeadState->hdrInfoFrame.state == NVKMS_HDR_INFOFRAME_STATE_ENABLED) { + hdrInfoFrame.payload.eotf = pHeadState->hdrInfoFrame.eotf; + + hdrInfoFrame.payload.static_metadata_desc_id = + NVT_CEA861_STATIC_METADATA_SM0; + + // payload->type1 = static metadata + ct_assert(sizeof(NVT_HDR_INFOFRAME_MASTERING_DATA) == + sizeof(struct NvKmsHDRStaticMetadata)); + nvkms_memcpy(&hdrInfoFrame.payload.type1, + (const NvU16 *) &pHeadState->hdrInfoFrame.staticMetadata, + sizeof(NVT_HDR_INFOFRAME_MASTERING_DATA)); + + transmitControl = NVHDMIPKT_TRANSMIT_CONTROL_ENABLE_EVERY_FRAME; + } else if (pHeadState->hdrInfoFrame.state == + NVKMS_HDR_INFOFRAME_STATE_TRANSITIONING) { + nvDpyAssignSDRInfoFramePayload(&hdrInfoFrame.payload); + + transmitControl = NVHDMIPKT_TRANSMIT_CONTROL_ENABLE_EVERY_FRAME; + } else { + nvAssert(pHeadState->hdrInfoFrame.state == NVKMS_HDR_INFOFRAME_STATE_DISABLED); + + nvDpyAssignSDRInfoFramePayload(&hdrInfoFrame.payload); + + transmitControl = NVHDMIPKT_TRANSMIT_CONTROL_ENABLE_SINGLE_FRAME; + } + + SendInfoFrame(pDispEvo, + head, + transmitControl, + (NVT_INFOFRAME_HEADER *) &hdrInfoFrame.header, + sizeof(hdrInfoFrame)); +} + + /* * Send video and 3D InfoFrames for HDMI. */ @@ -597,6 +699,10 @@ void nvUpdateHdmiInfoFrames(const NVDispEvoRec *pDispEvo, SendHDMI3DVendorSpecificInfoFrame(pDispEvo, head, &pDpyEvo->parsedEdid.info); + + SendHDRInfoFrame(pDispEvo, + head, + &pDpyEvo->parsedEdid.info); } static void SetDpAudioMute(const NVDispEvoRec *pDispEvo, @@ -2015,6 +2121,11 @@ NvBool nvHdmiDpySupportsFrl(const NVDpyEvoRec *pDpyEvo) nvAssert(nvDpyIsHdmiEvo(pDpyEvo)); + /* Can't use FRL if disabled by kernel module param. */ + if (nvkms_disable_hdmi_frl()) { + return FALSE; + } + /* Can't use FRL if the display hardware doesn't support it. */ if (!pDevEvo->hal->caps.supportsHDMIFRL) { return FALSE; @@ -2042,18 +2153,23 @@ NvBool nvHdmiDpySupportsFrl(const NVDpyEvoRec *pDpyEvo) * Returns TRUE if FRL is needed, or FALSE otherwise. * */ NvBool nvHdmiTimingsNeedFrl(const NVDpyEvoRec *pDpyEvo, - const NVHwModeTimingsEvo *pHwTimings) + const NVHwModeTimingsEvo *pHwTimings, + NvU8 bpc) { const NvU32 pixelClock = (pHwTimings->yuv420Mode == NV_YUV420_MODE_HW) ? (pHwTimings->pixelClock / 2) : pHwTimings->pixelClock; nvAssert(nvDpyIsHdmiEvo(pDpyEvo)); + nvAssert(bpc >= 8); /* * For HDMI, maxSingleLinkPixelClockKHz is the maximum non-FRL rate. * If the rate is higher than that, try to use FRL for the mode. + * + * For > 8 BPC, the effective pixel clock is adjusted upwards according to + * the ratio of the given BPC and 8 BPC. */ - return pixelClock > pDpyEvo->maxSingleLinkPixelClockKHz; + return ((pixelClock * bpc) / 8) > pDpyEvo->maxSingleLinkPixelClockKHz; } static NvU64 GetHdmiFrlLinkRate(HDMI_FRL_DATA_RATE frlRate) @@ -2089,13 +2205,15 @@ static NvU64 GetHdmiFrlLinkRate(HDMI_FRL_DATA_RATE frlRate) return hdmiLinkRate; } -NvBool nvHdmiFrlQueryConfig( +static NvBool nvHdmiFrlQueryConfigOneBpc( const NVDpyEvoRec *pDpyEvo, const NvModeTimings *pModeTimings, const NVHwModeTimingsEvo *pHwTimings, const NvBool b2Heads1Or, const struct NvKmsModeValidationParams *pValidationParams, + NvU8 bpc, HDMI_FRL_CONFIG *pConfig, + NvU8 *pHdmiFrlBpc, NVDscInfoEvoRec *pDscInfo) { const NVDispEvoRec *pDispEvo = pDpyEvo->pDispEvo; @@ -2106,6 +2224,8 @@ NvBool nvHdmiFrlQueryConfig( NVT_TIMING nvtTiming = { }; NVHDMIPKT_RESULT ret; + *pHdmiFrlBpc = 0; + if (pHwTimings->protocol != NVKMS_PROTOCOL_SOR_HDMI_FRL) { nvkms_memset(pDscInfo, 0, sizeof(*pDscInfo)); nvkms_memset(pConfig, 0, sizeof(*pConfig)); @@ -2114,7 +2234,7 @@ NvBool nvHdmiFrlQueryConfig( nvAssert(nvDpyIsHdmiEvo(pDpyEvo) && nvHdmiDpySupportsFrl(pDpyEvo) && - nvHdmiTimingsNeedFrl(pDpyEvo, pHwTimings)); + nvHdmiTimingsNeedFrl(pDpyEvo, pHwTimings, bpc)); /* See if we can find an NVT_TIMING for this mode from the EDID. */ pNvtTiming = nvFindEdidNVT_TIMING(pDpyEvo, pModeTimings, pValidationParams); @@ -2156,11 +2276,8 @@ NvBool nvHdmiFrlQueryConfig( * validation, so we can't use that. * This matches the non-DP default assigned later in * nvConstructHwModeTimingsEvo(). - * - * TODO: we should select a higher depth by default and downgrade if not - * possible. */ - videoTransportInfo.bpc = HDMI_BPC8; + videoTransportInfo.bpc = bpc; /* TODO: support YUV/YCbCr 444 and 422 packing modes. */ switch (pModeTimings->yuv420Mode) { case NV_YUV420_MODE_NONE: @@ -2217,41 +2334,45 @@ NvBool nvHdmiFrlQueryConfig( (pHwTimings->yuv420Mode == NV_YUV420_MODE_HW)); } - if (ret == NVHDMIPKT_SUCCESS && (pDscInfo != NULL)) { - const NvU64 hdmiLinkRate = GetHdmiFrlLinkRate(pConfig->frlRate); - - nvAssert((hdmiLinkRate != 0) || - (pConfig->frlRate == HDMI_FRL_DATA_RATE_NONE)); - - nvkms_memset(pDscInfo, 0, sizeof(*pDscInfo)); - - if ((pConfig->frlRate != HDMI_FRL_DATA_RATE_NONE) && - pConfig->dscInfo.bEnableDSC && - (hdmiLinkRate != 0)) { - pDscInfo->type = NV_DSC_INFO_EVO_TYPE_HDMI; - pDscInfo->hdmi.dscMode = b2Heads1Or ? - NV_DSC_EVO_MODE_DUAL : NV_DSC_EVO_MODE_SINGLE; - pDscInfo->hdmi.bitsPerPixelX16 = - pConfig->dscInfo.bitsPerPixelX16; - ct_assert(sizeof(pDscInfo->hdmi.pps) == - sizeof(pConfig->dscInfo.pps)); - nvkms_memcpy(pDscInfo->hdmi.pps, - pConfig->dscInfo.pps, - sizeof(pDscInfo->hdmi.pps)); - pDscInfo->hdmi.dscHActiveBytes = - pConfig->dscInfo.dscHActiveBytes; - pDscInfo->hdmi.dscHActiveTriBytes = - pConfig->dscInfo.dscHActiveTriBytes; - pDscInfo->hdmi.dscHBlankTriBytes = - pConfig->dscInfo.dscHBlankTriBytes; - pDscInfo->hdmi.dscTBlankToTTotalRatioX1k = - pConfig->dscInfo.dscTBlankToTTotalRatioX1k; - pDscInfo->hdmi.hblankMin = - NV_UNSIGNED_DIV_CEIL(((pHwTimings->pixelClock * 1000) * - pConfig->dscInfo.dscHBlankTriBytes), - (hdmiLinkRate / 6)); - } else { - pDscInfo->type = NV_DSC_INFO_EVO_TYPE_DISABLED; + if (ret == NVHDMIPKT_SUCCESS) { + *pHdmiFrlBpc = bpc; + + if (pDscInfo != NULL) { + const NvU64 hdmiLinkRate = GetHdmiFrlLinkRate(pConfig->frlRate); + + nvAssert((hdmiLinkRate != 0) || + (pConfig->frlRate == HDMI_FRL_DATA_RATE_NONE)); + + nvkms_memset(pDscInfo, 0, sizeof(*pDscInfo)); + + if ((pConfig->frlRate != HDMI_FRL_DATA_RATE_NONE) && + pConfig->dscInfo.bEnableDSC && + (hdmiLinkRate != 0)) { + pDscInfo->type = NV_DSC_INFO_EVO_TYPE_HDMI; + pDscInfo->hdmi.dscMode = b2Heads1Or ? + NV_DSC_EVO_MODE_DUAL : NV_DSC_EVO_MODE_SINGLE; + pDscInfo->hdmi.bitsPerPixelX16 = + pConfig->dscInfo.bitsPerPixelX16; + ct_assert(sizeof(pDscInfo->hdmi.pps) == + sizeof(pConfig->dscInfo.pps)); + nvkms_memcpy(pDscInfo->hdmi.pps, + pConfig->dscInfo.pps, + sizeof(pDscInfo->hdmi.pps)); + pDscInfo->hdmi.dscHActiveBytes = + pConfig->dscInfo.dscHActiveBytes; + pDscInfo->hdmi.dscHActiveTriBytes = + pConfig->dscInfo.dscHActiveTriBytes; + pDscInfo->hdmi.dscHBlankTriBytes = + pConfig->dscInfo.dscHBlankTriBytes; + pDscInfo->hdmi.dscTBlankToTTotalRatioX1k = + pConfig->dscInfo.dscTBlankToTTotalRatioX1k; + pDscInfo->hdmi.hblankMin = + NV_UNSIGNED_DIV_CEIL(((pHwTimings->pixelClock * 1000) * + pConfig->dscInfo.dscHBlankTriBytes), + (hdmiLinkRate / 6)); + } else { + pDscInfo->type = NV_DSC_INFO_EVO_TYPE_DISABLED; + } } } @@ -2270,6 +2391,41 @@ void nvHdmiFrlClearConfig(NVDispEvoRec *pDispEvo, NvU32 activeRmId) } } +NvBool nvHdmiFrlQueryConfig( + const NVDpyEvoRec *pDpyEvo, + const NvModeTimings *pModeTimings, + const NVHwModeTimingsEvo *pHwTimings, + const NvBool b2Heads1Or, + const struct NvKmsModeValidationParams *pValidationParams, + HDMI_FRL_CONFIG *pConfig, + NvU8 *pHdmiFrlBpc, + NVDscInfoEvoRec *pDscInfo) +{ + // Try first with 10 BPC + if (nvHdmiFrlQueryConfigOneBpc(pDpyEvo, + pModeTimings, + pHwTimings, + b2Heads1Or, + pValidationParams, + HDMI_BPC10, + pConfig, + pHdmiFrlBpc, + pDscInfo)) { + return TRUE; + } + + // Try again with 8 BPC + return nvHdmiFrlQueryConfigOneBpc(pDpyEvo, + pModeTimings, + pHwTimings, + b2Heads1Or, + pValidationParams, + HDMI_BPC8, + pConfig, + pHdmiFrlBpc, + pDscInfo); +} + void nvHdmiFrlSetConfig(NVDispEvoRec *pDispEvo, NvU32 head) { const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; diff --git a/src/nvidia-modeset/src/nvkms-headsurface-config.c b/src/nvidia-modeset/src/nvkms-headsurface-config.c index cc9c2f70de..21a96f1739 100644 --- a/src/nvidia-modeset/src/nvkms-headsurface-config.c +++ b/src/nvidia-modeset/src/nvkms-headsurface-config.c @@ -271,9 +271,10 @@ static NvBool HsConfigInitModesetOneHeadWarpAndBlendSurface( return TRUE; } - *ppSurface = nvEvoGetSurfaceFromHandleNoCtxDmaOk(pDevEvo, - pOpenDevSurfaceHandles, - handle); + *ppSurface = + nvEvoGetSurfaceFromHandleNoDispHWAccessOk(pDevEvo, + pOpenDevSurfaceHandles, + handle); return *ppSurface != NULL; } @@ -302,9 +303,10 @@ static NvBool HsConfigInitModesetWarpMesh( return TRUE; } - pSurface = nvEvoGetSurfaceFromHandleNoCtxDmaOk(pDevEvo, - pOpenDevSurfaceHandles, - p->warpMesh.surfaceHandle); + pSurface = + nvEvoGetSurfaceFromHandleNoDispHWAccessOk(pDevEvo, + pOpenDevSurfaceHandles, + p->warpMesh.surfaceHandle); if (pSurface == NULL) { return FALSE; } @@ -1435,7 +1437,7 @@ static NvBool HsConfigAllocSurfacesOneBuf( HsConfigAllocSurfacesOneSurface(pDevEvo, pHsConfig, apiHead, - TRUE, /* requireCtxDma */ + TRUE, /* requireDisplayHardwareAccess */ pWorkArea->headSurfaceSize, pWorkArea->format); if (pSurface[eye] == NULL) { @@ -1825,16 +1827,21 @@ static void HsConfigInitFlipQueue( } static void HsConfigUpdateSurfaceRefCount( + NVDevEvoPtr pDevEvo, const NVHsChannelConfig *pChannelConfig, NvBool increase) { - HsChangeSurfaceFlipRefCount(pChannelConfig->warpMesh.pSurface, increase); + HsChangeSurfaceFlipRefCount( + pDevEvo, pChannelConfig->warpMesh.pSurface, increase); - HsChangeSurfaceFlipRefCount(pChannelConfig->pBlendTexSurface, increase); + HsChangeSurfaceFlipRefCount( + pDevEvo, pChannelConfig->pBlendTexSurface, increase); - HsChangeSurfaceFlipRefCount(pChannelConfig->pOffsetTexSurface, increase); + HsChangeSurfaceFlipRefCount( + pDevEvo, pChannelConfig->pOffsetTexSurface, increase); - HsChangeSurfaceFlipRefCount(pChannelConfig->cursor.pSurfaceEvo, increase); + HsChangeSurfaceFlipRefCount( + pDevEvo, pChannelConfig->cursor.pSurfaceEvo, increase); } /*! @@ -2246,6 +2253,7 @@ void nvHsConfigStart( */ if (pHsConfigOneHead->pHsChannel != NULL) { HsConfigUpdateSurfaceRefCount( + pDevEvo, &pHsConfigOneHead->channelConfig, TRUE /* increase */); } @@ -2256,6 +2264,7 @@ void nvHsConfigStart( */ if (pDispEvo->pHsChannel[apiHead] != NULL) { HsConfigUpdateSurfaceRefCount( + pDevEvo, &pDispEvo->pHsChannel[apiHead]->config, FALSE /* increase */); } @@ -2597,7 +2606,7 @@ NvBool nvHsConfigPatchSetModeRequest(const NVDevEvoRec *pDevEvo, NVSurfaceEvoRec *pSurfaceEvo = nvHsGetNvKmsSurface(pDevEvo, pHsSurface->nvKmsHandle, - TRUE /* requireCtxDma */); + TRUE /* requireDisplayHardwareAccess */); nvAssert(pSurfaceEvo != NULL); pRequestHead->flip.layer[layer].surface.handle[eye] = diff --git a/src/nvidia-modeset/src/nvkms-headsurface-ioctl.c b/src/nvidia-modeset/src/nvkms-headsurface-ioctl.c index c3a843cde4..1777ce2ccf 100644 --- a/src/nvidia-modeset/src/nvkms-headsurface-ioctl.c +++ b/src/nvidia-modeset/src/nvkms-headsurface-ioctl.c @@ -169,6 +169,8 @@ static void HsIoctlSetCursorImage( NVHsChannelEvoRec *pHsChannel, NVSurfaceEvoRec *pSurfaceEvo) { + NVDevEvoPtr pDevEvo = pHsChannel->pDispEvo->pDevEvo; + /* * Increment the refcnt of the new surface, and * decrement the refcnt of the old surface. @@ -178,10 +180,10 @@ static void HsIoctlSetCursorImage( */ HsChangeSurfaceFlipRefCount( - pSurfaceEvo, TRUE /* increase */); + pDevEvo, pSurfaceEvo, TRUE /* increase */); HsChangeSurfaceFlipRefCount( - pHsChannel->config.cursor.pSurfaceEvo, FALSE /* increase */); + pDevEvo, pHsChannel->config.cursor.pSurfaceEvo, FALSE /* increase */); pHsChannel->config.cursor.pSurfaceEvo = pSurfaceEvo; @@ -256,7 +258,7 @@ static struct NvKmsFlipRequestOneHead *HsIoctlRemoveHsHeadsFromNvKmsFlipHead( const struct NvKmsFlipRequestOneHead *pFlipHeadOriginal, const NvU32 numFlipHeadsOriginal, const NvU32 numFlipHeads, - const NvU8 hsMask[NVKMS_MAX_SUBDEVICES]) + const NvU8 hsMask[NV_MAX_FLIP_REQUEST_HEADS / 8]) { struct NvKmsFlipRequestOneHead *pFlipHead = NULL; NvU32 i, j; @@ -268,9 +270,7 @@ static struct NvKmsFlipRequestOneHead *HsIoctlRemoveHsHeadsFromNvKmsFlipHead( j = 0; for (i = 0; i < numFlipHeadsOriginal; i++) { - const NvU32 apiHead = pFlipHeadOriginal[i].head; - const NvU32 sd = pFlipHeadOriginal[i].sd; - if ((hsMask[sd] & NVBIT(apiHead)) == 0) { + if ((hsMask[i / 8] & NVBIT(i % 8)) == 0) { pFlipHead[j++] = pFlipHeadOriginal[i]; } } @@ -481,9 +481,8 @@ NvBool nvHsIoctlFlip( struct NvKmsFlipReply *pReply) { NvU32 i; - ct_assert(NVKMS_MAX_HEADS_PER_DISP <= 8); - NvU8 hsMask[NVKMS_MAX_SUBDEVICES] = { }; - NvU8 nonHsMask[NVKMS_MAX_SUBDEVICES] = { }; + ct_assert((NV_MAX_FLIP_REQUEST_HEADS % 8) == 0); + NvU8 hsMask[NV_MAX_FLIP_REQUEST_HEADS / 8] = { }; NvU32 nHsApiHeads = 0; NvU32 nNonHsApiHeads = 0; NvBool ret = FALSE; @@ -503,10 +502,9 @@ NvBool nvHsIoctlFlip( NVDispEvoPtr pDispEvo = pDevEvo->pDispEvo[sd]; if (pDispEvo->pHsChannel[apiHead] == NULL) { - nonHsMask[sd] |= NVBIT(apiHead); nNonHsApiHeads++; } else { - hsMask[sd] |= NVBIT(apiHead); + hsMask[i / 8] |= NVBIT(i % 8); nHsApiHeads++; } } @@ -540,7 +538,7 @@ NvBool nvHsIoctlFlip( const NvU32 sd = pFlipHead[i].sd; NVDispEvoPtr pDispEvo = pDevEvo->pDispEvo[sd]; - if ((hsMask[sd] & NVBIT(apiHead)) == 0) { + if ((hsMask[i / 8] & NVBIT(i % 8)) == 0) { continue; } @@ -637,7 +635,7 @@ NvBool nvHsIoctlFlip( const NvU32 sd = pFlipHead[i].sd; NVDispEvoPtr pDispEvo = pDevEvo->pDispEvo[sd]; - if ((hsMask[sd] & NVBIT(apiHead)) == 0) { + if ((hsMask[i / 8] & NVBIT(i % 8)) == 0) { continue; } @@ -664,7 +662,7 @@ NvBool nvHsIoctlFlip( const NvU32 sd = pFlipHead[i].sd; NVDispEvoPtr pDispEvo = pDevEvo->pDispEvo[sd]; - if ((hsMask[sd] & NVBIT(apiHead)) == 0) { + if ((hsMask[i / 8] & NVBIT(i % 8)) == 0) { continue; } diff --git a/src/nvidia-modeset/src/nvkms-headsurface.c b/src/nvidia-modeset/src/nvkms-headsurface.c index be7fcf7bc7..1ab7cda379 100644 --- a/src/nvidia-modeset/src/nvkms-headsurface.c +++ b/src/nvidia-modeset/src/nvkms-headsurface.c @@ -236,7 +236,7 @@ void nvHsFreeSurface( NVSurfaceEvoRec *nvHsGetNvKmsSurface(const NVDevEvoRec *pDevEvo, NvKmsSurfaceHandle surfaceHandle, - const NvBool requireCtxDma) + const NvBool requireDisplayHardwareAccess) { const NVEvoApiHandlesRec *pNvKmsOpenDevSurfaceHandles; NVSurfaceEvoRec *pKmsSurface; @@ -247,11 +247,11 @@ NVSurfaceEvoRec *nvHsGetNvKmsSurface(const NVDevEvoRec *pDevEvo, nvAssert(pNvKmsOpenDevSurfaceHandles != NULL); pKmsSurface = - nvEvoGetSurfaceFromHandleNoCtxDmaOk(pDevEvo, - pNvKmsOpenDevSurfaceHandles, - surfaceHandle); + nvEvoGetSurfaceFromHandleNoDispHWAccessOk(pDevEvo, + pNvKmsOpenDevSurfaceHandles, + surfaceHandle); nvAssert(pKmsSurface != NULL); - nvAssert(pKmsSurface->requireCtxDma == requireCtxDma); + nvAssert(pKmsSurface->requireDisplayHardwareAccess == requireDisplayHardwareAccess); return pKmsSurface; } @@ -265,18 +265,18 @@ NVSurfaceEvoRec *nvHsGetNvKmsSurface(const NVDevEvoRec *pDevEvo, * Note the video memory is not cleared here, because the corresponding graphics * channel may not be allocated, yet. * - * \param[in] pDevEvo The device. - * \param[in] requireCtxDma Whether display hardware requires access. - * \param[in] format The format of the surface. - * \param[in] widthInPixels The width of the surface, in pixels. - * \param[in] heightInPixels The height of the surface, in pixels. + * \param[in] pDevEvo The device. + * \param[in] requireDisplayHardwareAccess Whether display hardware requires access. + * \param[in] format The format of the surface. + * \param[in] widthInPixels The width of the surface, in pixels. + * \param[in] heightInPixels The height of the surface, in pixels. * * \return On success, an allocate NVHsSurfaceRec structure is returned. * On failure, NULL is returned. */ NVHsSurfaceRec *nvHsAllocSurface( NVDevEvoRec *pDevEvo, - const NvBool requireCtxDma, + const NvBool requireDisplayHardwareAccess, const enum NvKmsSurfaceMemoryFormat format, const NvU32 widthInPixels, const NvU32 heightInPixels) @@ -330,7 +330,7 @@ NVHsSurfaceRec *nvHsAllocSurface( nvKmsParams.request.heightInPixels = heightInPixels; nvKmsParams.request.layout = NvKmsSurfaceMemoryLayoutBlockLinear; nvKmsParams.request.format = format; - nvKmsParams.request.noDisplayHardwareAccess = !requireCtxDma; + nvKmsParams.request.noDisplayHardwareAccess = !requireDisplayHardwareAccess; nvKmsParams.request.log2GobsPerBlockY = log2GobsPerBlockY; nvKmsParams.request.planes[0].u.rmObject = pHsSurface->rmHandle; @@ -347,7 +347,7 @@ NVHsSurfaceRec *nvHsAllocSurface( pHsSurface->nvKmsHandle = nvKmsParams.reply.surfaceHandle; pHsSurface->pSurfaceEvo = - nvHsGetNvKmsSurface(pDevEvo, pHsSurface->nvKmsHandle, requireCtxDma); + nvHsGetNvKmsSurface(pDevEvo, pHsSurface->nvKmsHandle, requireDisplayHardwareAccess); if (pHsSurface->pSurfaceEvo == NULL) { goto fail; @@ -549,21 +549,22 @@ static NvBool HsFlipQueueEntryIsReady( * Update the reference count of all the surfaces described in the pFlipState. */ static void HsUpdateFlipQueueEntrySurfaceRefCount( + NVDevEvoPtr pDevEvo, const NVHsLayerRequestedFlipState *pFlipState, NvBool increase) { HsChangeSurfaceFlipRefCount( - pFlipState->pSurfaceEvo[NVKMS_LEFT], increase); + pDevEvo, pFlipState->pSurfaceEvo[NVKMS_LEFT], increase); HsChangeSurfaceFlipRefCount( - pFlipState->pSurfaceEvo[NVKMS_RIGHT], increase); + pDevEvo, pFlipState->pSurfaceEvo[NVKMS_RIGHT], increase); if (!pFlipState->syncObject.usingSyncpt) { HsChangeSurfaceFlipRefCount( - pFlipState->syncObject.u.semaphores.acquireSurface.pSurfaceEvo, increase); + pDevEvo, pFlipState->syncObject.u.semaphores.acquireSurface.pSurfaceEvo, increase); HsChangeSurfaceFlipRefCount( - pFlipState->syncObject.u.semaphores.releaseSurface.pSurfaceEvo, increase); + pDevEvo, pFlipState->syncObject.u.semaphores.releaseSurface.pSurfaceEvo, increase); } } @@ -602,7 +603,7 @@ static void HsReleaseFlipQueueEntry( * HeadSurface no longer needs to read from the surfaces in pFlipState; * decrement their reference counts. */ - HsUpdateFlipQueueEntrySurfaceRefCount(pFlipState, FALSE); + HsUpdateFlipQueueEntrySurfaceRefCount(pDevEvo, pFlipState, FALSE); } /*! @@ -684,6 +685,7 @@ void nvHsPushFlipQueueEntry( const NvU8 layer, const NVHsLayerRequestedFlipState *pFlipState) { + NVDevEvoPtr pDevEvo = pHsChannel->pDispEvo->pDevEvo; NVListRec *pFlipQueue = &pHsChannel->flipQueue[layer].queue; NVHsChannelFlipQueueEntry *pEntry = nvCalloc(1, sizeof(*pEntry)); @@ -700,7 +702,7 @@ void nvHsPushFlipQueueEntry( /* Increment the ref counts on the surfaces in the flip queue entry. */ - HsUpdateFlipQueueEntrySurfaceRefCount(&pEntry->hwState, TRUE); + HsUpdateFlipQueueEntrySurfaceRefCount(pDevEvo, &pEntry->hwState, TRUE); /* "Fast forward" through existing flip queue entries that are ready. */ @@ -722,7 +724,7 @@ void nvHsPushFlipQueueEntry( * If this function returns TRUE, it is the caller's responsibility to * eventually call * - * HsUpdateFlipQueueEntrySurfaceRefCount(pFlipState, FALSE) + * HsUpdateFlipQueueEntrySurfaceRefCount(pDevEvo, pFlipState, FALSE) * * for the returned pFlipState. * @@ -971,7 +973,7 @@ static NvBool RegisterNotifiersWithNvKms(NVHsDeviceEvoRec *pHsDevice) struct NvKmsRegisterSurfaceParams params = { }; NVHsNotifiersRec *pNotifiers = &pHsDevice->notifiers; NVDevEvoRec *pDevEvo = pHsDevice->pDevEvo; - const NvBool requireCtxDma = TRUE; + const NvBool requireDisplayHardwareAccess = TRUE; params.request.useFd = FALSE; params.request.rmClient = nvEvoGlobal.clientHandle; @@ -998,7 +1000,7 @@ static NvBool RegisterNotifiersWithNvKms(NVHsDeviceEvoRec *pHsDevice) pHsDevice->notifiers.pSurfaceEvo = nvHsGetNvKmsSurface(pDevEvo, pHsDevice->notifiers.nvKmsHandle, - requireCtxDma); + requireDisplayHardwareAccess); return (pHsDevice->notifiers.pSurfaceEvo != NULL); } @@ -1248,10 +1250,12 @@ static void HsFlipHelper( pParamsOneHead->layer[NVKMS_MAIN_LAYER].perEyeStereoFlip = perEyeStereoFlip; pParamsOneHead->layer[NVKMS_MAIN_LAYER].minPresentInterval = 1; pParamsOneHead->layer[NVKMS_MAIN_LAYER].csc.specified = TRUE; + pParamsOneHead->lut.input.specified = FALSE; + pParamsOneHead->lut.output.specified = FALSE; /* * XXX NVKMS HEADSURFACE TODO: Work out in which cases we should use the - * head's current CSC. + * head's current CSC or LUT. */ pParamsOneHead->layer[NVKMS_MAIN_LAYER].csc.matrix = NVKMS_IDENTITY_CSC_MATRIX; diff --git a/src/nvidia-modeset/src/nvkms-hw-flip.c b/src/nvidia-modeset/src/nvkms-hw-flip.c index 1496a0981c..f85751073e 100644 --- a/src/nvidia-modeset/src/nvkms-hw-flip.c +++ b/src/nvidia-modeset/src/nvkms-hw-flip.c @@ -36,6 +36,7 @@ #include "nvkms-dpy.h" #include "nvkms-lut.h" #include "nvkms-softfloat.h" +#include "nvkms-ctxdma.h" #include "nvkms-sync.h" @@ -117,9 +118,17 @@ static NvBool AssignPostSyncptEvoHwState( threshold = pChannel->postSyncpt.syncptMaxVal + 1; /*! each channel associated with one post-syncpt */ - pFlipSyncObject->u.syncpts.postCtxDma = pChannel->postSyncpt.hCtxDma; + pFlipSyncObject->u.syncpts.surfaceDesc = + pChannel->postSyncpt.surfaceDesc; pFlipSyncObject->u.syncpts.postValue = threshold; + /* + * AllocPostSyncptPerChannel()->AllocSyncpt() sets allocated to TRUE + * when postSyncpt is allocated/valid. + */ + pFlipSyncObject->u.syncpts.isPostSyncptSpecified = + pChannel->postSyncpt.allocated; + pFlipSyncObject->usingSyncpt = TRUE; return TRUE; @@ -152,102 +161,6 @@ void nvFillPostSyncptReplyOneChannel( } } -static NvBool GetPreSyncptCtxDma(NVDevEvoRec *pDevEvo, - NVEvoChannel *pChannel, const NvU32 id) -{ - NvU32 hSyncptCtxDma, hSyncpt; - - /*! use id value to check the global table */ - if (pDevEvo->preSyncptTable[id].hCtxDma == 0) { - /*! Register - allocate and bind ctxdma to syncpt*/ - if (!nvRmEvoAllocAndBindSyncpt(pDevEvo, - pChannel, - id, - &hSyncpt, - &hSyncptCtxDma)) { - nvAssert(!"Failed to register pre-syncpt"); - return FALSE; - } - - /*! Fill the Entry in Global Table */ - pDevEvo->preSyncptTable[id].hCtxDma = hSyncptCtxDma; - pDevEvo->preSyncptTable[id].hSyncpt = hSyncpt; - pDevEvo->preSyncptTable[id].channelMask |= pChannel->channelMask; - pDevEvo->preSyncptTable[id].id = id; - } else { - /*! - * syncpt found, just bind the context dma of this syncpt - * to the window if it is not already. - */ - if ((pDevEvo->preSyncptTable[id].channelMask & - pChannel->channelMask) == 0) { - - NvU32 ret = - nvRmEvoBindDispContextDMA(pDevEvo, - pChannel, - pDevEvo->preSyncptTable[id].hCtxDma); - if (ret != NVOS_STATUS_SUCCESS) { - nvAssert(!"Failed to bind pre-syncpt with ctxdma"); - } - pDevEvo->preSyncptTable[id].channelMask |= pChannel->channelMask; - /*! hSyncpt already allocated for id*/ - } - } - - return TRUE; -} - -static NvBool RegisterPreSyncpt(NVDevEvoRec *pDevEvo, - struct NvKmsFlipWorkArea *pWorkArea) -{ - NvU32 sd; - NvU32 ret = TRUE; - const NVDispEvoRec *pDispEvo; - - pDevEvo->pAllSyncptUsedInCurrentFlip = - nvCalloc(1, sizeof(NvBool) * NV_SYNCPT_GLOBAL_TABLE_LENGTH); - if (pDevEvo->pAllSyncptUsedInCurrentFlip == NULL) { - ret = FALSE; - goto done; - } - - FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - NvU32 head; - for (head = 0; head < ARRAY_LEN(pWorkArea->sd[sd].head); head++) { - NVFlipEvoHwState *pFlipState = - &pWorkArea->sd[sd].head[head].newState; - NvU32 layer; - - for (layer = 0; layer < ARRAY_LEN(pFlipState->layer); layer++) { - NVFlipSyncObjectEvoHwState *pFlipSyncObject = - &pFlipState->layer[layer].syncObject; - NvU32 preSyncpt = pFlipSyncObject->u.syncpts.preSyncpt; - - if (!pFlipState->dirty.layerSyncObjects[layer] || - !pFlipSyncObject->usingSyncpt || - !pFlipSyncObject->u.syncpts.isPreSyncptSpecified) { - continue; - } - - if (!GetPreSyncptCtxDma(pDevEvo, - pDevEvo->head[head].layer[layer], - preSyncpt)) { - ret = FALSE; - goto done; - } - - pDevEvo->pAllSyncptUsedInCurrentFlip[preSyncpt] = NV_TRUE; - } - } - } - -done: - nvFree(pDevEvo->pAllSyncptUsedInCurrentFlip); - pDevEvo->pAllSyncptUsedInCurrentFlip = NULL; - - return ret; -} - void nvClearFlipEvoHwState( NVFlipEvoHwState *pFlipState) { @@ -271,6 +184,8 @@ void nvInitFlipEvoHwState( { NVDispEvoRec *pDispEvo = pDevEvo->gpus[sd].pDispEvo; const NVEvoSubDevHeadStateRec *pSdHeadState; + const NVDispHeadStateEvoRec *pHeadState; + NvU32 i; nvClearFlipEvoHwState(pFlipState); @@ -280,6 +195,7 @@ void nvInitFlipEvoHwState( } pSdHeadState = &pDevEvo->gpus[sd].headState[head]; + pHeadState = &pDispEvo->headState[head]; pFlipState->viewPortPointIn = pSdHeadState->viewPortPointIn; pFlipState->cursor = pSdHeadState->cursor; @@ -304,6 +220,15 @@ void nvInitFlipEvoHwState( pFlipState->disableMidFrameAndDWCFWatermark = pSdHeadState->targetDisableMidFrameAndDWCFWatermark; + + pFlipState->tf = pHeadState->tf; + + pFlipState->hdrInfoFrame.enabled = pHeadState->hdrInfoFrameOverride.enabled; + pFlipState->hdrInfoFrame.eotf = pHeadState->hdrInfoFrameOverride.eotf; + pFlipState->hdrInfoFrame.staticMetadata = + pHeadState->hdrInfoFrameOverride.staticMetadata; + + pFlipState->colorimetry = pHeadState->colorimetry; } @@ -319,7 +244,7 @@ NvBool nvIsLayerDirty(const struct NvKmsFlipCommonParams *pParams, pParams->layer[layer].compositionParams.specified || pParams->layer[layer].csc.specified || pParams->layer[layer].hdr.specified || - pParams->layer[layer].colorspace.specified; + pParams->layer[layer].colorSpace.specified; } /*! @@ -608,7 +533,7 @@ static NvBool FlipTimeStampValidForChannel( return TRUE; } -static NvBool UpdateFlipEvoHwStateHDRStaticMetadata( +static NvBool UpdateLayerFlipEvoHwStateHDRStaticMetadata( const NVDevEvoRec *pDevEvo, const struct NvKmsFlipCommonParams *pParams, NVFlipEvoHwState *pFlipState, @@ -804,15 +729,19 @@ static NvBool UpdateLayerFlipEvoHwStateCommon( pParams->layer[layer].compositionParams.val; } - if (!UpdateFlipEvoHwStateHDRStaticMetadata( + if (!UpdateLayerFlipEvoHwStateHDRStaticMetadata( pDevEvo, pParams, pFlipState, pHwState, head, layer)) { return FALSE; } - if (pParams->layer[layer].colorspace.specified) { - pHwState->colorspace = - pParams->layer[layer].colorspace.val; + if (pParams->layer[layer].colorRange.specified) { + pHwState->colorRange = pParams->layer[layer].colorRange.val; + } + + if (pParams->layer[layer].colorSpace.specified) { + pHwState->colorSpace = + pParams->layer[layer].colorSpace.val; } if (pHwState->composition.depth == 0) { @@ -919,6 +848,19 @@ static NvBool UpdateMainLayerFlipEvoHwState( pHwState->tearing = pParams->layer[NVKMS_MAIN_LAYER].tearing; + /* + * XXX: Cludge. Ideally, this would be handled by FlipRequiresNonTearingMode + * recognizing a difference in HW state. However, the new HW LUT state is + * not computed until later, when nvEvoSetLut() and nvEvoSetLUTContextDma() + * are called. See bug 4054546. + */ + if ((pParams->lut.input.specified || + pParams->lut.output.specified) && + !pDevEvo->hal->caps.supportsCoreLut) { + + pHwState->tearing = FALSE; + } + if (!ApplyBaseFlipOverrides(pDevEvo, sd, head, &pFlipState->layer[NVKMS_MAIN_LAYER], allowVrr)) { @@ -1066,6 +1008,24 @@ NvBool nvUpdateFlipEvoHwState( pFlipState->tf = pParams->tf.val; } + if (pParams->colorimetry.specified) { + pFlipState->dirty.colorimetry = TRUE; + pFlipState->colorimetry = pParams->colorimetry.val; + } + + if (pParams->hdrInfoFrame.specified) { + pFlipState->dirty.hdrStaticMetadata = TRUE; + + if (pParams->hdrInfoFrame.enabled) { + pFlipState->hdrInfoFrame.eotf = + pParams->hdrInfoFrame.eotf; + pFlipState->hdrInfoFrame.staticMetadata = + pParams->hdrInfoFrame.staticMetadata; + } + pFlipState->hdrInfoFrame.enabled = + pParams->hdrInfoFrame.enabled; + } + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { if (layer == NVKMS_MAIN_LAYER) { if (!UpdateMainLayerFlipEvoHwState(pOpenDev, pDevEvo, sd, head, @@ -1314,7 +1274,7 @@ ValidateHDR(const NVDevEvoRec *pDevEvo, const NvU32 head, const NVFlipEvoHwState *pFlipState) { - NvU32 staticMetadataCount = 0; + NvU32 layerStaticMetadataCount = 0; NvU32 layerSupportedCount = 0; NvU32 layer; @@ -1325,7 +1285,7 @@ ValidateHDR(const NVDevEvoRec *pDevEvo, } if (pFlipState->layer[layer].hdrStaticMetadata.enabled) { - staticMetadataCount++; + layerStaticMetadataCount++; /* * If HDR static metadata is enabled, we may need TMO. CSC11 will be @@ -1337,26 +1297,31 @@ ValidateHDR(const NVDevEvoRec *pDevEvo, return FALSE; } - // Already checked in UpdateFlipEvoHwStateHDRStaticMetadata() + // Already checked in UpdateLayerFlipEvoHwStateHDRStaticMetadata() nvAssert(pDevEvo->caps.layerCaps[layer].supportsHDR); } } - // If enabling HDR... + // If enabling HDR TF... // XXX HDR TODO: Handle other transfer functions if (pFlipState->tf == NVKMS_OUTPUT_TF_PQ) { - // At least one layer must have static metadata. - if (staticMetadataCount == 0) { + // At least one layer must support HDR. + if (layerSupportedCount == 0) { return FALSE; } - // At least one layer must support HDR, implied above. - nvAssert(layerSupportedCount != 0); + // If HDR metadata is not overridden for the head... + if (!pFlipState->hdrInfoFrame.enabled) { + // At least one layer must have static metadata. + if (layerStaticMetadataCount == 0) { + return FALSE; + } + } } // Only one layer can specify HDR static metadata. // XXX HDR TODO: Support multiple layers with HDR static metadata - if (staticMetadataCount > 1) { + if (layerStaticMetadataCount > 1) { return FALSE; } @@ -1371,7 +1336,7 @@ ValidateColorspace(const NVDevEvoRec *pDevEvo, NvU32 layer; for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - if ((pFlipState->layer[layer].colorspace != + if ((pFlipState->layer[layer].colorSpace != NVKMS_INPUT_COLORSPACE_NONE)) { NVSurfaceEvoPtr pSurfaceEvo = @@ -1386,7 +1351,7 @@ ValidateColorspace(const NVDevEvoRec *pDevEvo, } // FP16 is only for use with scRGB. - if ((pFlipState->layer[layer].colorspace != + if ((pFlipState->layer[layer].colorSpace != NVKMS_INPUT_COLORSPACE_SCRGB_LINEAR) && ((pSurfaceEvo->format == NvKmsSurfaceMemoryFormatRF16GF16BF16AF16) || @@ -1396,7 +1361,7 @@ ValidateColorspace(const NVDevEvoRec *pDevEvo, } // scRGB is only compatible with FP16. - if ((pFlipState->layer[layer].colorspace == + if ((pFlipState->layer[layer].colorSpace == NVKMS_INPUT_COLORSPACE_SCRGB_LINEAR) && !((pSurfaceEvo->format == NvKmsSurfaceMemoryFormatRF16GF16BF16AF16) || @@ -1547,6 +1512,10 @@ static void UpdateUpdateFlipLockState(NVDevEvoPtr pDevEvo, // Adjust from EDID-encoded maxCLL/maxFALL to actual values in units of 1 cd/m2 static inline NvU32 MaxCvToVal(NvU32 cv) { + if (cv == 0) { + return 0; + } + // 50*2^(cv/32) return f64_to_ui32( f64_mul(ui32_to_f64(50), @@ -1581,76 +1550,131 @@ static void UpdateHDR(NVDevEvoPtr pDevEvo, NvBool dirty = FALSE; if (pFlipState->dirty.tf) { - // XXX HDR TODO: Handle other transfer functions - if (pFlipState->tf == NVKMS_OUTPUT_TF_PQ) { - pHeadState->hdr.outputState = NVKMS_HDR_OUTPUT_STATE_HDR; - } else if (pHeadState->hdr.outputState == NVKMS_HDR_OUTPUT_STATE_HDR) { - pHeadState->hdr.outputState = - NVKMS_HDR_OUTPUT_STATE_TRANSITIONING_TO_SDR; - } pHeadState->tf = pFlipState->tf; dirty = TRUE; } if (pFlipState->dirty.hdrStaticMetadata) { - NvU32 layer; NvBool found = FALSE; - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - // Populate head with updated static metadata. - if (pFlipState->layer[layer].hdrStaticMetadata.enabled) { - NvU32 targetMaxCLL = MaxCvToVal(pHdrInfo->max_cll); - // Send this layer's metadata to the display. - pHeadState->hdr.staticMetadata = - pFlipState->layer[layer].hdrStaticMetadata.val; + /* + * Track if HDR static metadata is overridden for the head in order to + * initialize subsequent instances of NVFlipEvoHwState. + */ + pHeadState->hdrInfoFrameOverride.enabled = + pFlipState->hdrInfoFrame.enabled; + pHeadState->hdrInfoFrameOverride.eotf = + pFlipState->hdrInfoFrame.eotf; + pHeadState->hdrInfoFrameOverride.staticMetadata = + pFlipState->hdrInfoFrame.staticMetadata; + + // Populate head with updated static metadata. + + if (pFlipState->hdrInfoFrame.enabled) { + // If HDR static metadata is overridden for the head, use that. + pHeadState->hdrInfoFrame.staticMetadata = + pFlipState->hdrInfoFrame.staticMetadata; + pHeadState->hdrInfoFrame.eotf = + pFlipState->hdrInfoFrame.eotf; + + pHeadState->hdrInfoFrame.state = NVKMS_HDR_INFOFRAME_STATE_ENABLED; + found = TRUE; + } else { + NvU32 layer; - /* - * Prepare for tone mapping. If we expect to tone map and the - * EDID has valid lum values, mirror EDID lum values to prevent - * redundant tone mapping by the display. We will tone map to - * the specified maxCLL. - */ - if (nvNeedsTmoLut(pDevEvo, pDevEvo->head[head].layer[layer], - &pFlipState->layer[layer], - nvGetHDRSrcMaxLum( - &pFlipState->layer[layer]), - targetMaxCLL)) { - NvU32 targetMaxFALL = MaxCvToVal(pHdrInfo->max_fall); - if ((targetMaxCLL > 0) && - (targetMaxCLL <= 10000) && - (targetMaxCLL >= targetMaxFALL)) { - - NvU32 targetMinCLL = MinCvToVal(pHdrInfo->min_cll, - targetMaxCLL); - - pHeadState->hdr.staticMetadata. - maxDisplayMasteringLuminance = targetMaxCLL; - pHeadState->hdr.staticMetadata. - minDisplayMasteringLuminance = targetMinCLL; - pHeadState->hdr.staticMetadata.maxCLL = targetMaxCLL; - pHeadState->hdr.staticMetadata.maxFALL = targetMaxFALL; + /* + * If HDR static metadata is specified for layer(s), construct the + * head's HDR static metadata using those. + */ + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + if (pFlipState->layer[layer].hdrStaticMetadata.enabled) { + NvU32 targetMaxCLL = MaxCvToVal(pHdrInfo->max_cll); + + /* + * Only one layer can currently specify static metadata, + * verified by ValidateHDR(). + * + * XXX HDR TODO: Combine metadata from multiple layers. + */ + nvAssert(!found); + + // Send this layer's metadata to the display. + pHeadState->hdrInfoFrame.staticMetadata = + pFlipState->layer[layer].hdrStaticMetadata.val; + + // Infer metadata eotf from output tf + // XXX HDR TODO: Handle other transfer functions + switch (pHeadState->tf) { + default: + nvAssert(!"Unrecognized output TF"); + // Fall through + case NVKMS_OUTPUT_TF_TRADITIONAL_GAMMA_SDR: + case NVKMS_OUTPUT_TF_NONE: + pHeadState->hdrInfoFrame.eotf = + NVKMS_INFOFRAME_EOTF_SDR_GAMMA; + break; + case NVKMS_OUTPUT_TF_PQ: + pHeadState->hdrInfoFrame.eotf = + NVKMS_INFOFRAME_EOTF_ST2084; + break; } - } - /* - * Only one layer can currently specify static metadata, - * verified by ValidateHDR(). - * - * XXX HDR TODO: Combine metadata from multiple layers. - */ - nvAssert(!found); - found = TRUE; + pHeadState->hdrInfoFrame.state = + NVKMS_HDR_INFOFRAME_STATE_ENABLED; + found = TRUE; + + /* + * Prepare for tone mapping. If we expect to tone map and + * the EDID has valid lum values, mirror EDID lum values to + * prevent redundant tone mapping by the display. We will + * tone map to the specified maxCLL. + */ + if (nvNeedsTmoLut(pDevEvo, pDevEvo->head[head].layer[layer], + &pFlipState->layer[layer], + nvGetHDRSrcMaxLum( + &pFlipState->layer[layer]), + targetMaxCLL)) { + NvU32 targetMaxFALL = MaxCvToVal(pHdrInfo->max_fall); + if ((targetMaxCLL > 0) && + (targetMaxCLL <= 10000) && + (targetMaxCLL >= targetMaxFALL)) { + + NvU32 targetMinCLL = MinCvToVal(pHdrInfo->min_cll, + targetMaxCLL); + + pHeadState->hdrInfoFrame.staticMetadata. + maxDisplayMasteringLuminance = targetMaxCLL; + pHeadState->hdrInfoFrame.staticMetadata. + minDisplayMasteringLuminance = targetMinCLL; + pHeadState->hdrInfoFrame.staticMetadata.maxCLL = + targetMaxCLL; + pHeadState->hdrInfoFrame.staticMetadata.maxFALL = + targetMaxFALL; + } + } + } } } + if (!found) { - nvkms_memset(&pHeadState->hdr.staticMetadata, 0, + nvkms_memset(&pHeadState->hdrInfoFrame.staticMetadata, 0, sizeof(struct NvKmsHDRStaticMetadata)); + if (pHeadState->hdrInfoFrame.state == + NVKMS_HDR_INFOFRAME_STATE_ENABLED) { + pHeadState->hdrInfoFrame.state = + NVKMS_HDR_INFOFRAME_STATE_TRANSITIONING; + } } dirty = TRUE; } + if (pFlipState->dirty.colorimetry) { + pHeadState->colorimetry = pFlipState->colorimetry; + dirty = TRUE; + } + if (dirty) { // Update OCSC / OLUT nvEvoSetLUTContextDma(pDispEvo, head, updateState); @@ -1745,6 +1769,8 @@ void nvFlipEvoOneHead( continue; } + nvPushEvoSubDevMask(pDevEvo, subDeviceMask); + if (pFlipState->dirty.layerPosition[layer]) { /* Ensure position updates are supported on this layer. */ nvAssert(pDevEvo->caps.layerCaps[layer].supportsWindowMode); @@ -1762,8 +1788,6 @@ void nvFlipEvoOneHead( } } - nvPushEvoSubDevMask(pDevEvo, subDeviceMask); - /* Inform DIFR about the upcoming flip. */ if (pDevEvo->pDifrState) { nvDIFRNotifyFlip(pDevEvo->pDifrState); @@ -1796,7 +1820,7 @@ static void ChangeSurfaceFlipRefCount( if (increase) { nvEvoIncrementSurfaceRefCnts(pSurfaceEvo); } else { - nvEvoDecrementSurfaceRefCnts(pSurfaceEvo); + nvEvoDecrementSurfaceRefCnts(pDevEvo, pSurfaceEvo); } } } @@ -2674,6 +2698,98 @@ void nvPostFlip(NVDevEvoRec *pDevEvo, } } +static NvBool AllocPreSyncpt(NVDevEvoRec *pDevEvo, + NVEvoChannel *pChannel, const NvU32 id) +{ + NVSurfaceDescriptor surfaceDesc; + + /*! use id value to check the global table */ + if (!pDevEvo->preSyncptTable[id].allocated) { + /*! Register - allocate and bind surface descriptor for syncpt*/ + if (!nvRmEvoAllocAndBindSyncpt(pDevEvo, + pChannel, + id, + &surfaceDesc, + &pDevEvo->preSyncptTable[id])) { + nvAssert(!"Failed to register pre-syncpt"); + return FALSE; + } + + /*! Fill the Entry in Global Table */ + pDevEvo->preSyncptTable[id].channelMask |= pChannel->channelMask; + } else { + /*! + * syncpt found, just bind the surface descriptor of this syncpt + * to the window if it is not already. + */ + if ((pDevEvo->preSyncptTable[id].channelMask & + pChannel->channelMask) == 0) { + + NvU32 ret = + pDevEvo->hal->BindSurfaceDescriptor(pDevEvo, + pChannel, &pDevEvo->preSyncptTable[id].surfaceDesc); + if (ret != NVOS_STATUS_SUCCESS) { + nvAssert(!"Failed to bind surface descriptor for pre-syncpt"); + } + + pDevEvo->preSyncptTable[id].channelMask |= pChannel->channelMask; + /*! hSyncpt already allocated for id*/ + } + } + + return TRUE; +} + +static NvBool RegisterPreSyncpt(NVDevEvoRec *pDevEvo, + struct NvKmsFlipWorkArea *pWorkArea) +{ + NvU32 sd; + NvU32 ret = TRUE; + const NVDispEvoRec *pDispEvo; + + pDevEvo->pAllSyncptUsedInCurrentFlip = + nvCalloc(1, sizeof(NvBool) * NV_SYNCPT_GLOBAL_TABLE_LENGTH); + if (pDevEvo->pAllSyncptUsedInCurrentFlip == NULL) { + ret = FALSE; + goto done; + } + + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + NvU32 head; + for (head = 0; head < ARRAY_LEN(pWorkArea->sd[sd].head); head++) { + NVFlipEvoHwState *pFlipState = + &pWorkArea->sd[sd].head[head].newState; + NvU32 layer; + + for (layer = 0; layer < ARRAY_LEN(pFlipState->layer); layer++) { + NVFlipSyncObjectEvoHwState *pFlipSyncObject = + &pFlipState->layer[layer].syncObject; + NvU32 preSyncpt = pFlipSyncObject->u.syncpts.preSyncpt; + + if (!pFlipState->dirty.layerSyncObjects[layer] || + !pFlipSyncObject->usingSyncpt || + !pFlipSyncObject->u.syncpts.isPreSyncptSpecified) { + continue; + } + + if (!AllocPreSyncpt(pDevEvo, pDevEvo->head[head].layer[layer], + preSyncpt)) { + ret = FALSE; + goto done; + } + + pDevEvo->pAllSyncptUsedInCurrentFlip[preSyncpt] = NV_TRUE; + } + } + } + +done: + nvFree(pDevEvo->pAllSyncptUsedInCurrentFlip); + pDevEvo->pAllSyncptUsedInCurrentFlip = NULL; + + return ret; +} + NvBool nvPrepareToDoPreFlip(NVDevEvoRec *pDevEvo, struct NvKmsFlipWorkArea *pWorkArea) { @@ -2788,7 +2904,7 @@ void nvIdleMainLayerChannels( } /* Break out of the loop if we exceed the timeout. */ - if (nvExceedsTimeoutUSec(&startTime, timeout)) { + if (nvExceedsTimeoutUSec(pDevEvo, &startTime, timeout)) { break; } @@ -2869,7 +2985,6 @@ void nvToggleFlipLockPerDisp(NVDispEvoRec *pDispEvo, const NvU32 headMask, if (!nvUpdateFlipLockEvoOneHead(pDispEvo, head, &setEnable, TRUE /* set */, - NULL /* needsEarlyUpdate */, &updateState)) { nvEvoLogDev(pDevEvo, EVO_LOG_WARN, "Failed to toggle fliplock for swapgroups."); diff --git a/src/nvidia-modeset/src/nvkms-hw-states.c b/src/nvidia-modeset/src/nvkms-hw-states.c index a227019aa5..aed6fdb775 100644 --- a/src/nvidia-modeset/src/nvkms-hw-states.c +++ b/src/nvidia-modeset/src/nvkms-hw-states.c @@ -245,28 +245,6 @@ * change the pin here, prior to enabling flip lock. */ -NvBool nvEvoLockHWStateNoChange(NVDispEvoPtr pDispEvo, NVEvoSubDevPtr pEvoSubDev, - const NvU32 *pHeads) -{ - return TRUE; -} - -NvBool nvEvoLockHWStateMergeMode(NVDispEvoPtr pDispEvo, NVEvoSubDevPtr pEvoSubDev, - const NvU32 *pHeads) -{ - unsigned int i; - - nvAssert(pHeads != NULL && pHeads[0] != NV_INVALID_HEAD); - - for (i = 0; pHeads[i] != NV_INVALID_HEAD; i++) { - const int head = pHeads[i]; - NVEvoHeadControlPtr pHC = &pEvoSubDev->headControlAssy[head]; - pHC->mergeMode = TRUE; - } - - return TRUE; -} - NvBool nvEvoLockHWStateNoLock(NVDispEvoPtr pDispEvo, NVEvoSubDevPtr pEvoSubDev, const NvU32 *pHeads) { @@ -278,13 +256,22 @@ NvBool nvEvoLockHWStateNoLock(NVDispEvoPtr pDispEvo, NVEvoSubDevPtr pEvoSubDev, const int head = pHeads[i]; NVEvoHeadControlPtr pHC = &pEvoSubDev->headControlAssy[head]; + if (pHC->mergeMode) { + /* MergeMode is currently handled outside of the scanlock state + * machine, so don't touch the HeadControl state for heads with + * mergeMode enabled. (The state machine will be transitioned to + * the 'ProhibitLock' state to prevent other states from being + * reached, so this should be the only HWState function that needs + * this special case.) */ + continue; + } + /* Disable scan lock on this head */ pHC->serverLock = NV_EVO_NO_LOCK; pHC->serverLockPin = NV_EVO_LOCK_PIN_INTERNAL(0); pHC->clientLock = NV_EVO_NO_LOCK; pHC->clientLockPin = NV_EVO_LOCK_PIN_INTERNAL(0); pHC->clientLockoutWindow = 0; - pHC->mergeMode = FALSE; pHC->setLockOffsetX = FALSE; pHC->useStallLockPin = FALSE; pHC->stallLockPin = NV_EVO_LOCK_PIN_INTERNAL(0); @@ -748,7 +735,7 @@ NvBool nvEvoLockHWStateSliSecondary(NVDispEvoPtr pDispEvo, { NVEvoLockPin serverPin = pEvoSubDev->sliServerLockPin; NVEvoLockPin clientPin = pEvoSubDev->sliClientLockPin; - NvU32 clientLockoutWindow = pEvoSubDev->forceZeroClientLockoutWindow ? 0 : 2; + const NvU32 clientLockoutWindow = 2; NVEvoLockPin flPin = nvEvoGetPinForSignal(pDispEvo, pEvoSubDev, NV_EVO_LOCK_SIGNAL_FLIP_LOCK); @@ -803,7 +790,7 @@ NvBool nvEvoLockHWStateSliLastSecondary(NVDispEvoPtr pDispEvo, const NvU32 *pHeads) { NVEvoLockPin clientPin = pEvoSubDev->sliClientLockPin; - NvU32 clientLockoutWindow = pEvoSubDev->forceZeroClientLockoutWindow ? 0 : 2; + const NvU32 clientLockoutWindow = 2; NVEvoLockPin flPin = nvEvoGetPinForSignal(pDispEvo, pEvoSubDev, NV_EVO_LOCK_SIGNAL_FLIP_LOCK); @@ -854,7 +841,7 @@ NvBool nvEvoLockHWStateSliSecondaryLockHeads(NVDispEvoPtr pDispEvo, { NVEvoLockPin serverPin = pEvoSubDev->sliServerLockPin; NVEvoLockPin clientPin = pEvoSubDev->sliClientLockPin; - NvU32 clientLockoutWindow = pEvoSubDev->forceZeroClientLockoutWindow ? 0 : 2; + const NvU32 clientLockoutWindow = 2; NVEvoLockPin flPin = nvEvoGetPinForSignal(pDispEvo, pEvoSubDev, NV_EVO_LOCK_SIGNAL_FLIP_LOCK); unsigned int i; @@ -918,7 +905,7 @@ NvBool nvEvoLockHWStateSliLastSecondaryLockHeads(NVDispEvoPtr pDispEvo, const NvU32 *pHeads) { NVEvoLockPin clientPin = pEvoSubDev->sliClientLockPin; - NvU32 clientLockoutWindow = pEvoSubDev->forceZeroClientLockoutWindow ? 0 : 2; + const NvU32 clientLockoutWindow = 2; NVEvoLockPin flPin = nvEvoGetPinForSignal(pDispEvo, pEvoSubDev, NV_EVO_LOCK_SIGNAL_FLIP_LOCK); unsigned int i; diff --git a/src/nvidia-modeset/src/nvkms-lut.c b/src/nvidia-modeset/src/nvkms-lut.c index 944dcd2e04..bfc6d395e6 100644 --- a/src/nvidia-modeset/src/nvkms-lut.c +++ b/src/nvidia-modeset/src/nvkms-lut.c @@ -52,8 +52,10 @@ static void FreeLutSurfaceEvoInVidmem(NVLutSurfaceEvoPtr pSurfEvo) nvRmEvoUnMapVideoMemory(pDevEvo, pSurfEvo->handle, pSurfEvo->subDeviceAddress); - /* Free display context dmas for the surface, if any */ - nvRmEvoFreeDispContextDMA(pDevEvo, &pSurfEvo->dispCtxDma); + /* Free surface descriptor */ + pDevEvo->hal->FreeSurfaceDescriptor(pDevEvo, + nvEvoGlobal.clientHandle, + &pSurfEvo->surfaceDesc); /* Free the surface */ if (pSurfEvo->handle) { @@ -131,14 +133,15 @@ static NVLutSurfaceEvoPtr AllocLutSurfaceEvoInVidmem(NVDevEvoPtr pDevEvo) goto fail; } - /* Allocate a display context dma */ - pSurfEvo->dispCtxDma = - nvRmEvoAllocateAndBindDispContextDMA(pDevEvo, - pSurfEvo->handle, - NvKmsSurfaceMemoryLayoutPitch, - pSurfEvo->size - 1); - - if (!pSurfEvo->dispCtxDma) { + /* Allocate and bind surface descriptor */ + ret = + nvRmAllocAndBindSurfaceDescriptor( + pDevEvo, + pSurfEvo->handle, + NvKmsSurfaceMemoryLayoutPitch, + pSurfEvo->size - 1, + &pSurfEvo->surfaceDesc); + if (ret != NVOS_STATUS_SUCCESS) { goto fail; } @@ -188,8 +191,10 @@ static void FreeLutSurfaceEvoInSysmem(NVLutSurfaceEvoPtr pSurfEvo) pDevEvo = pSurfEvo->pDevEvo; - /* Free display context dmas for the surface, if any */ - nvRmEvoFreeDispContextDMA(pDevEvo, &pSurfEvo->dispCtxDma); + /* Free surface descriptor */ + pDevEvo->hal->FreeSurfaceDescriptor(pDevEvo, + nvEvoGlobal.clientHandle, + &pSurfEvo->surfaceDesc); /* Free the surface */ if (pSurfEvo->handle) { @@ -232,6 +237,7 @@ static NVLutSurfaceEvoPtr AllocLutSurfaceEvoInSysmem(NVDevEvoPtr pDevEvo) void *pBase = NULL; NvU64 size = 0; NVLutSurfaceEvoPtr pSurfEvo; + NvU32 ret; pSurfEvo = nvCalloc(1, sizeof(*pSurfEvo)); if (pSurfEvo == NULL) { @@ -261,13 +267,16 @@ static NVLutSurfaceEvoPtr AllocLutSurfaceEvoInSysmem(NVDevEvoPtr pDevEvo) pSurfEvo->handle = memoryHandle; - /* Allocate and bind a display context dma */ - pSurfEvo->dispCtxDma = - nvRmEvoAllocateAndBindDispContextDMA(pDevEvo, - pSurfEvo->handle, - NvKmsSurfaceMemoryLayoutPitch, - pSurfEvo->size - 1); - if (!pSurfEvo->dispCtxDma) { + /* Allocate and bind surface descriptor */ + ret = + nvRmAllocAndBindSurfaceDescriptor( + pDevEvo, + pSurfEvo->handle, + NvKmsSurfaceMemoryLayoutPitch, + pSurfEvo->size - 1, + &pSurfEvo->surfaceDesc); + + if (ret != NVOS_STATUS_SUCCESS) { goto fail; } @@ -405,6 +414,10 @@ NvBool nvAllocLutSurfacesEvo(NVDevEvoPtr pDevEvo) } } + // Zero-initalize the LUT notifier state - ensure there's no stale data + nvkms_memset(&pDevEvo->lut.notifierState, 0, + sizeof(pDevEvo->lut.notifierState)); + if (pDevEvo->hal->caps.needDefaultLutSurface) { pDevEvo->lut.defaultLut = AllocLutSurfaceEvo(pDevEvo); if (pDevEvo->lut.defaultLut == NULL) { diff --git a/src/nvidia-modeset/src/nvkms-modepool.c b/src/nvidia-modeset/src/nvkms-modepool.c index d8209c1e14..671e1a6eb4 100644 --- a/src/nvidia-modeset/src/nvkms-modepool.c +++ b/src/nvidia-modeset/src/nvkms-modepool.c @@ -1643,6 +1643,7 @@ static NvBool ValidateMode(NVDpyEvoPtr pDpyEvo, NVKMS_MAX_HEADS_PER_DISP); NvU32 impOutNumHeads = 0x0; NvU32 head; + NvU8 hdmiFrlBpc; NvBool ret = FALSE; if (modeName[0] == '\0') { @@ -1708,6 +1709,7 @@ static NvBool ValidateMode(NVDpyEvoPtr pDpyEvo, b2Heads1Or, pParams, pHdmiFrlConfig, + &hdmiFrlBpc, pDscInfo)) { LogModeValidationEnd(pDispEvo, pInfoString, "Unable to determine HDMI 2.1 Fixed Rate Link configuration."); diff --git a/src/nvidia-modeset/src/nvkms-modeset.c b/src/nvidia-modeset/src/nvkms-modeset.c index 14f9ce87c0..4dd8628539 100644 --- a/src/nvidia-modeset/src/nvkms-modeset.c +++ b/src/nvidia-modeset/src/nvkms-modeset.c @@ -150,63 +150,6 @@ InheritPreviousModesetState(const NVDevEvoRec *pDevEvo, !pDevEvo->modesetOwnerChanged; } -/*! - * Get an allowFlipLockGroup value that is not yet used by pProposed. - * - * Scan through pProposed to find all currently used - * allowFlipLockGroup values, then pick the first allowFlipLockGroup - * value that is not used. - */ -static NvU8 GetAvailableAllowFlipLockGroupValue( - const NVProposedModeSetHwState *pProposed) -{ - NvU32 dispIndex; - NvU64 allowFlipLockGroupMask = 0; - NvU8 allowFlipLockGroup; - - /* - * Find all of the used allowFlipLockGroup values. Note that - * allowFlipLockGroup is 1-based (so that 0 can represent no - * assigned allowFlipLockGroup). Shift to 0-based, to store in - * allowFlipLockGroupMask. - */ - for (dispIndex = 0; dispIndex < ARRAY_LEN(pProposed->disp); dispIndex++) { - NvU32 apiHead; - for (apiHead = 0; - apiHead < ARRAY_LEN(pProposed->disp[dispIndex].apiHead); - apiHead++) { - - const NVProposedModeSetStateOneApiHead *pProposedApiHead = - &pProposed->disp[dispIndex].apiHead[apiHead]; - - if (pProposedApiHead->allowFlipLockGroup != 0) { - nvAssert(pProposedApiHead->allowFlipLockGroup <= 64); - allowFlipLockGroupMask |= - NVBIT64(pProposedApiHead->allowFlipLockGroup - 1); - } - } - } - - /* Find the first available allowFlipLockGroup values. */ - allowFlipLockGroupMask = ~allowFlipLockGroupMask; - if (allowFlipLockGroupMask == 0) { - /* - * For this to be zero, the pProposed would need to already - * have 64 unique allowFlipLockGroup values; 64 unique - * flipLock groups is highly unlikely. - */ - nvAssert(!"allowFlipLockGroupMask is too small"); - return 0; - } - - allowFlipLockGroup = BIT_IDX_64(LOWESTBIT(allowFlipLockGroupMask)); - - /* Shift allowFlipLockGroup back to 1-based. */ - - return allowFlipLockGroup + 1; -} - - /*! * Get the NVHwModeTimingsEvo for the mode requested by the client. * @@ -274,6 +217,7 @@ static NvBool GetColorSpaceAndColorRange( const NVDispEvoPtr pDispEvo, const struct NvKmsSetModeOneHeadRequest *pRequestHead, + const NVProposedModeSetHwStateOneHead *pProposedPrimaryHead, NVProposedModeSetStateOneApiHead *pProposedApiHead) { enum NvKmsDpyAttributeColorRangeValue requestedColorRange; @@ -310,8 +254,9 @@ GetColorSpaceAndColorRange( * timings and the requested color space and range. */ if (!nvChooseCurrentColorSpaceAndRangeEvo(pOneArbitraryDpyEvo, - pProposedApiHead->timings.yuv420Mode, - pProposedApiHead->tf, + &pProposedApiHead->timings, + pProposedPrimaryHead->hdmiFrlBpc, + pProposedApiHead->colorimetry, requestedColorSpace, requestedColorRange, &pProposedApiHead->attributes.colorSpace, @@ -442,14 +387,14 @@ static void AdjustHwModeTimingsForVrr(const NVDispEvoRec *pDispEvo, /* * Return whether headSurface is allowed. But, only honor the requestor's - * setting if they are the modeset owner. Otherwise, inherit the cached value - * in pDevEvo. + * setting if they have modeset owner permission. Otherwise, inherit the cached + * value in pDevEvo. */ NvBool nvGetAllowHeadSurfaceInNvKms(const NVDevEvoRec *pDevEvo, const struct NvKmsPerOpenDev *pOpenDev, const struct NvKmsSetModeRequest *pRequest) { - if (pOpenDev == pDevEvo->modesetOwner || pOpenDev == pDevEvo->pNvKmsOpenDev) { + if (nvKmsOpenDevHasSubOwnerPermissionOrBetter(pOpenDev)) { return pRequest->allowHeadSurfaceInNvKms; } @@ -489,6 +434,11 @@ InitNVProposedModeSetStateOneApiHead( pProposedApiHead->infoFrame = pDispEvo->apiHeadState[apiHead].infoFrame; pProposedApiHead->tf = pDispEvo->apiHeadState[apiHead].tf; + pProposedApiHead->colorimetry = pDispEvo->apiHeadState[apiHead].colorimetry; + pProposedApiHead->hdrInfoFrameOverride = + pDispEvo->apiHeadState[apiHead].hdrInfoFrameOverride; + pProposedApiHead->hdrStaticMetadataLayerMask = + pDispEvo->apiHeadState[apiHead].hdrStaticMetadataLayerMask; pProposedApiHead->viewPortPointIn = pDispEvo->apiHeadState[apiHead].viewPortPointIn; @@ -505,8 +455,6 @@ InitNVProposedModeSetStateOneApiHead( if (hwHeadCount == 0) { pProposedApiHead->dscInfo = pHeadState->dscInfo; pProposedApiHead->activeRmId = pHeadState->activeRmId; - pProposedApiHead->allowFlipLockGroup = - pHeadState->allowFlipLockGroup; pProposedApiHead->modeValidationParams = pHeadState->modeValidationParams; } else { @@ -515,8 +463,6 @@ InitNVProposedModeSetStateOneApiHead( sizeof(pProposedApiHead->dscInfo)) == 0x0); nvAssert(pProposedApiHead->activeRmId == pHeadState->activeRmId); - nvAssert(pProposedApiHead->allowFlipLockGroup == - pHeadState->allowFlipLockGroup); nvAssert(nvkms_memcmp(&pProposedApiHead->modeValidationParams, &pHeadState->modeValidationParams, sizeof(pProposedApiHead->modeValidationParams)) == 0x0); @@ -543,6 +489,9 @@ InitProposedModeSetHwState(const NVDevEvoRec *pDevEvo, for (NvU32 head = 0; head < pDevEvo->numHeads; head++) { NvU32 layer; NVFlipEvoHwState *pFlip = &pProposed->sd[sd].head[head].flip; + pFlip->dirty.tf = TRUE; + pFlip->dirty.hdrStaticMetadata = TRUE; + pFlip->dirty.colorimetry = TRUE; for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { pFlip->dirty.layer[layer] = TRUE; } @@ -576,6 +525,7 @@ InitProposedModeSetHwState(const NVDevEvoRec *pDevEvo, pProposedHead->timings = pHeadState->timings; pProposedHead->pConnectorEvo = pHeadState->pConnectorEvo; pProposedHead->hdmiFrlConfig = pHeadState->hdmiFrlConfig; + pProposedHead->hdmiFrlBpc = pHeadState->hdmiFrlBpc; pProposedHead->audio = pHeadState->audio; } } @@ -615,6 +565,10 @@ AssignProposedModeSetNVFlipEvoHwState( if (commit) { NvU32 layer; + pFlip->dirty.tf = TRUE; + pFlip->dirty.hdrStaticMetadata = TRUE; + pFlip->dirty.colorimetry = TRUE; + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { pFlip->dirty.layer[layer] = TRUE; } @@ -655,8 +609,8 @@ AssignProposedModeSetNVFlipEvoHwState( * XXX NVKMS TODO: Implement separate input programming for * base and overlay layers and remove code block. */ - if ((pRequestHead->lut.input.specified || - pRequestHead->lut.output.specified) && + if ((pRequestHead->flip.lut.input.specified || + pRequestHead->flip.lut.output.specified) && !pDevEvo->hal->caps.supportsCoreLut) { pFlip->layer[NVKMS_MAIN_LAYER].tearing = FALSE; } @@ -1019,7 +973,6 @@ AssignProposedModeSetHwState(NVDevEvoRec *pDevEvo, NvU32 sd; NVDispEvoPtr pDispEvo; NvBool ret = TRUE; - NvU8 allowFlipLockGroup = 0; /* If more than one head will enable VRR on Pascal, disallow Adaptive-Sync */ const enum NvKmsAllowAdaptiveSync prohibitAdaptiveSync = (!pDevEvo->hal->caps.supportsDisplayRate && @@ -1053,6 +1006,7 @@ AssignProposedModeSetHwState(NVDevEvoRec *pDevEvo, NVProposedModeSetStateOneApiHead *pProposedApiHead = &pProposedDisp->apiHead[apiHead]; const NVDpyEvoRec *pDpyEvo; + NvU32 layer; if ((pRequestDisp->requestedHeadsBitMask & (1 << apiHead)) == 0) { /* @@ -1123,18 +1077,9 @@ AssignProposedModeSetHwState(NVDevEvoRec *pDevEvo, pProposedApiHead->infoFrame.hdTimings = nvEvoIsHDQualityVideoTimings(&pProposedApiHead->timings); - pProposedApiHead->allowFlipLockGroup = 0; pProposedApiHead->modeValidationParams = pRequestHead->modeValidationParams; - if (!GetColorSpaceAndColorRange(pDispEvo, pRequestHead, - pProposedApiHead)) { - pReply->disp[sd].head[apiHead].status = - NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_MODE; - ret = FALSE; - continue; - } - pProposedApiHead->attributes.digitalSignal = nvGetDefaultDpyAttributeDigitalSignalValue(pDpyEvo->pConnectorEvo); if (pProposedApiHead->timings.protocol == @@ -1161,23 +1106,94 @@ AssignProposedModeSetHwState(NVDevEvoRec *pDevEvo, * keep them disabled by default. */ if (!InheritPreviousModesetState(pDevEvo, pOpenDev)) { - pProposedApiHead->lut = pRequestHead->lut; + pProposedApiHead->lut = pRequestHead->flip.lut; - if (!pRequestHead->lut.input.specified) { + if (!pRequestHead->flip.lut.input.specified) { pProposedApiHead->lut.input.specified = TRUE; pProposedApiHead->lut.input.end = 0; } - if (!pRequestHead->lut.output.specified) { + if (!pRequestHead->flip.lut.output.specified) { pProposedApiHead->lut.output.specified = TRUE; pProposedApiHead->lut.output.enabled = FALSE; } - } else if (pRequestHead->lut.input.specified) { - pProposedApiHead->lut = pRequestHead->lut; + } else if (pRequestHead->flip.lut.input.specified) { + pProposedApiHead->lut = pRequestHead->flip.lut; } else { pProposedApiHead->lut.input.specified = FALSE; } + if (pRequestHead->flip.tf.specified) { + pProposedApiHead->tf = pRequestHead->flip.tf.val; + + // If enabling HDR TF... + // XXX HDR TODO: Handle other transfer functions + if (pProposedApiHead->tf == NVKMS_OUTPUT_TF_PQ) { + // Cannot be an SLI configuration. + // XXX HDR TODO: Test SLI Mosaic + HDR and remove this check + if (pDevEvo->numSubDevices > 1) { + ret = FALSE; + pReply->disp[sd].head[apiHead].status = + NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_FLIP; + continue; + } + + /* NVKMS_OUTPUT_TF_PQ requires the RGB color space */ + if (pProposedApiHead->attributes.colorSpace != + NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB) { + ret = FALSE; + pReply->disp[sd].head[apiHead].status = + NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_FLIP; + continue; + } + } + } + + if (pRequestHead->flip.colorimetry.specified) { + pProposedApiHead->colorimetry = pRequestHead->flip.colorimetry.val; + } + + if (pRequestHead->flip.hdrInfoFrame.specified) { + pProposedApiHead->hdrInfoFrameOverride = + pRequestHead->flip.hdrInfoFrame.enabled; + } + + for (layer = 0; layer < pDevEvo->apiHead[apiHead].numLayers; layer++) { + if (pRequestHead->flip.layer[layer].hdr.specified) { + if (pRequestHead->flip.layer[layer].hdr.enabled) { + pProposedApiHead->hdrStaticMetadataLayerMask |= + 1 << layer; + } else { + pProposedApiHead->hdrStaticMetadataLayerMask &= + ~(1 << layer); + } + } + } + + // If enabling HDR signaling... + // XXX HDR TODO: Handle other colorimetries + if (pProposedApiHead->hdrInfoFrameOverride || + (pProposedApiHead->hdrStaticMetadataLayerMask != 0) || + (pProposedApiHead->colorimetry == NVKMS_OUTPUT_COLORIMETRY_BT2100)) { + const NVDpyEvoRec *pDpyEvo; + + // All dpys on apiHead must support HDR. + FOR_ALL_EVO_DPYS(pDpyEvo, + pProposedApiHead->dpyIdList, + pDispEvo) { + if (!nvDpyIsHDRCapable(pDpyEvo)) { + ret = FALSE; + pReply->disp[sd].head[apiHead].status = + NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_FLIP; + break; + } + } + + if (ret == FALSE) { + continue; + } + } + if (pRequestHead->flip.viewPortIn.specified) { pProposedApiHead->viewPortPointIn = pRequestHead->flip.viewPortIn.point; @@ -1279,6 +1295,7 @@ AssignProposedModeSetHwState(NVDevEvoRec *pDevEvo, /* b2Heads1Or */, &pProposedApiHead->modeValidationParams, &pProposedPrimaryHead->hdmiFrlConfig, + &pProposedPrimaryHead->hdmiFrlBpc, &pProposedApiHead->dscInfo)) { pReply->disp[sd].head[apiHead].status = NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_MODE; @@ -1286,6 +1303,15 @@ AssignProposedModeSetHwState(NVDevEvoRec *pDevEvo, continue; } + if (!GetColorSpaceAndColorRange(pDispEvo, pRequestHead, + pProposedPrimaryHead, + pProposedApiHead)) { + pReply->disp[sd].head[apiHead].status = + NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_MODE; + ret = FALSE; + continue; + } + /* * Construct the api head audio state, and pass it * to the primary hardware head. @@ -1313,32 +1339,6 @@ AssignProposedModeSetHwState(NVDevEvoRec *pDevEvo, } /* apiHead */ } /* pDispEvo */ - /* Assign allowFlipLockGroup for the heads specified in the request. */ - - allowFlipLockGroup = GetAvailableAllowFlipLockGroupValue(pProposed); - - FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { - if ((pRequest->requestedDispsBitMask & NVBIT(sd)) == 0) { - continue; - } - - for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { - const struct NvKmsSetModeOneHeadRequest *pRequestHead = - &pRequest->disp[sd].head[apiHead]; - NVProposedModeSetStateOneApiHead *pProposedApiHead = - &pProposed->disp[sd].apiHead[apiHead]; - - if ((pRequest->disp[sd].requestedHeadsBitMask & - NVBIT(apiHead)) == 0) { - continue; - } - - if (pRequestHead->allowFlipLock) { - pProposedApiHead->allowFlipLockGroup = allowFlipLockGroup; - } - } - } - if (!ret) { ClearProposedModeSetHwState(pDevEvo, pProposed, FALSE /* committed */); } @@ -1536,7 +1536,7 @@ static NvBool DowngradeColorSpaceAndBpcOneHead( } static NvBool DowngradeColorSpaceAndBpcOneDisp( - NVDispEvoPtr pDispEvo, + const NVDispEvoRec *pDispEvo, NVProposedModeSetHwStateOneDisp *pProposedDisp, const NVConnectorEvoRec *pConnectorEvo) { @@ -1569,33 +1569,19 @@ static NvBool DowngradeColorSpaceAndBpcOneDisp( return ret; } -/*! - * Validate the DisplayPort bandwidth of the proposed disp configuration. - * - * \param[in] pDispEvo The disp to which pProposedDisp is to be applied. - * \param[in] pProposedDisp The requested configuration. - * - * \return If pProposedDisp passes the DP bandwidth check, return - * TRUE. Otherwise, return FALSE. - */ -static NvBool ValidateProposedModeSetHwStateOneDispDPlib( - NVDispEvoPtr pDispEvo, - NVProposedModeSetHwStateOneDisp *pProposedDisp) +static NvU32 SetDpLibImpParamsOneConnectorEvo( + NVProposedModeSetHwStateOneDisp *pProposedDisp, + const NVConnectorEvoRec *pConnectorEvo, + NVDpLibIsModePossibleParamsRec *pParams) { - NvBool bResult = TRUE, bTryAgain = FALSE; + const NVDispEvoRec *pDispEvo = pConnectorEvo->pDispEvo; const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; - -tryAgain: - - bTryAgain = FALSE; - bResult = TRUE; - - nvDPBeginValidation(pDispEvo); + NvU32 attachedHeadsMask = 0x0; for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { NVProposedModeSetStateOneApiHead *pProposedApiHead = &pProposedDisp->apiHead[apiHead]; - const NvU32 primaryHead = + const NvU32 head = nvGetPrimaryHwHeadFromMask(pProposedApiHead->hwHeadsMask); const NVDpyEvoRec *pDpyEvo = nvGetOneArbitraryDpyEvo(pProposedApiHead->dpyIdList, pDispEvo); @@ -1604,62 +1590,153 @@ static NvBool ValidateProposedModeSetHwStateOneDispDPlib( nvAssert(nvPopCount32(pProposedApiHead->hwHeadsMask) <= 2); - if ((pDpyEvo == NULL) || + if ((pDpyEvo == NULL) || (pDpyEvo->pConnectorEvo != pConnectorEvo) || SkipDisplayPortBandwidthCheck(pProposedApiHead)) { continue; } - bResult = !!nvDPLibValidateTimings(pDispEvo, - primaryHead, - pProposedApiHead->activeRmId, - pProposedApiHead->dpyIdList, - pProposedApiHead->attributes.colorSpace, - pProposedApiHead->attributes.colorBpc, - &pProposedApiHead->modeValidationParams, - &pProposedApiHead->timings, - b2Heads1Or, - &pProposedApiHead->dscInfo); + nvAssert((NVBIT(head) & attachedHeadsMask) == 0x0); - if (!bResult && pProposedApiHead->changed) { + pParams->head[head].displayId = pProposedApiHead->activeRmId; + pParams->head[head].dpyIdList = pProposedApiHead->dpyIdList; + pParams->head[head].colorSpace = pProposedApiHead->attributes.colorSpace; + pParams->head[head].colorBpc = pProposedApiHead->attributes.colorBpc; + pParams->head[head].pModeValidationParams = + &pProposedApiHead->modeValidationParams; + pParams->head[head].pTimings = &pProposedApiHead->timings; + pParams->head[head].b2Heads1Or = b2Heads1Or; + pParams->head[head].pDscInfo = &pProposedApiHead->dscInfo; - /* - * First, try to downgrade the pixel depth for this current head. - * If the pixel depth for this current head is not possible to - * downgrade further then try to downgrade the pixel depth of other - * changed heads which are sharing same connector and dp-bandwidth. - */ + attachedHeadsMask |= NVBIT(head); + } - if (DowngradeColorSpaceAndBpcOneHead(pDispEvo, pProposedApiHead) || - DowngradeColorSpaceAndBpcOneDisp(pDispEvo, - pProposedDisp, - pDpyEvo->pConnectorEvo)) { - bTryAgain = TRUE; - } + return attachedHeadsMask; +} - /* - * Cannot downgrade pixelDepth further -- - * This proposed mode-set is not possible on this DP link, so fail. - */ +static NvBool DowngradeColorSpaceAndBpcOneConnectorEvo( + const NVConnectorEvoRec *pConnectorEvo, + const NvU32 failedHeadMask, + NVProposedModeSetHwStateOneDisp *pProposedDisp) +{ + const NVDispEvoRec *pDispEvo = pConnectorEvo->pDispEvo; + const NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; - break; - } else if (!bResult) { + /* + * First, try to downgrade the pixel depth for the failed heads. + * If the pixel depth for the failed current heads is not possible + * to downgrade further then try to downgrade the pixel depth of + * other changed heads which are sharing same connector and + * dp-bandwidth. + */ + + for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { + NVProposedModeSetStateOneApiHead *pProposedApiHead = + &pProposedDisp->apiHead[apiHead]; + + if (((pProposedApiHead->hwHeadsMask & failedHeadMask) == 0x0) || + !pProposedApiHead->changed) { + continue; + } + + if (DowngradeColorSpaceAndBpcOneHead(pDispEvo, pProposedApiHead)) { + return TRUE; + } + } + + + if (DowngradeColorSpaceAndBpcOneDisp(pDispEvo, + pProposedDisp, + pConnectorEvo)) { + return TRUE; + } + + return FALSE; +} + +static NvBool ValidateProposedModeSetHwStateOneConnectorDPlib( + const NVConnectorEvoRec *pConnectorEvo, + NVProposedModeSetHwStateOneDisp *pProposedDisp) +{ + const NVDispEvoRec *pDispEvo = pConnectorEvo->pDispEvo; + NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + NvU32 attachedHeadsMask = 0x0, failedHeadMask = 0x0; + NvBool bResult = TRUE; + NVDpLibIsModePossibleParamsRec *pDpLibImpParams = + nvPreallocGet(pDevEvo, PREALLOC_TYPE_DPLIB_IS_MODE_POSSIBLE_PARAMS, + sizeof(*pDpLibImpParams)); + + nvAssert(pDpLibImpParams != NULL); + + if (!nvConnectorUsesDPLib(pConnectorEvo)) { + goto done; + } + +tryAgain: + nvkms_memset(pDpLibImpParams, 0, sizeof(*pDpLibImpParams)); + + attachedHeadsMask = 0x0; + failedHeadMask = 0x0; + bResult = TRUE; + + attachedHeadsMask = SetDpLibImpParamsOneConnectorEvo(pProposedDisp, + pConnectorEvo, + pDpLibImpParams); + if (attachedHeadsMask == 0x0) { + goto done; + } + + bResult = nvDPLibIsModePossible(pConnectorEvo->pDpLibConnector, + pDpLibImpParams, + &failedHeadMask); + + if (!bResult) { + if (DowngradeColorSpaceAndBpcOneConnectorEvo(pConnectorEvo, + failedHeadMask, + pProposedDisp)) { + goto tryAgain; + } + + /* + * Cannot downgrade pixelDepth further -- + * This proposed mode-set is not possible on this DP link, so fail. + */ + } + +done: + nvPreallocRelease(pDevEvo, PREALLOC_TYPE_DPLIB_IS_MODE_POSSIBLE_PARAMS); + return bResult; +} + +/*! + * Validate the DisplayPort bandwidth of the proposed disp configuration. + * + * \param[in] pDispEvo The disp to which pProposedDisp is to be applied. + * \param[in] pProposedDisp The requested configuration. + * + * \return If pProposedDisp passes the DP bandwidth check, return + * TRUE. Otherwise, return FALSE. + */ +static NvBool ValidateProposedModeSetHwStateOneDispDPlib( + NVDispEvoPtr pDispEvo, + NVProposedModeSetHwStateOneDisp *pProposedDisp) +{ + NvBool dpIsModePossible = TRUE; + NVDevEvoRec *pDevEvo = pDispEvo->pDevEvo; + const NVConnectorEvoRec *pConnectorEvo; + FOR_ALL_EVO_CONNECTORS(pConnectorEvo, pDispEvo) { + if (!ValidateProposedModeSetHwStateOneConnectorDPlib(pConnectorEvo, + pProposedDisp)) { /* * The Dp link bandwidth check fails for an unchanged head -- * This proposed mode-set is not possible on this DP link, so fail. */ - + dpIsModePossible = FALSE; break; } } - bResult = !!nvDPEndValidation(pDispEvo) && bResult; - - if (bTryAgain) { - goto tryAgain; - } - - if (bResult) { + if (dpIsModePossible) { for (NvU32 apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) { const NVProposedModeSetStateOneApiHead *pProposedApiHead = &pProposedDisp->apiHead[apiHead]; @@ -1694,12 +1771,14 @@ static NvBool ValidateProposedModeSetHwStateOneDispDPlib( &pProposedApiHead->timings, &pProposedApiHead->dscInfo); if (pProposedPrimaryHead->pDpLibModesetState == NULL) { - return FALSE; + dpIsModePossible = FALSE; + goto done; } } } - return bResult; +done: + return dpIsModePossible; } static void VBlankCallbackDeferredWork(void *dataPtr, NvU32 data32) @@ -2201,7 +2280,7 @@ static void DisableActiveCoreRGSyncObjects(NVDispEvoRec *pDispEvo, 0, /* rasterLine */ head, i, - 0, /* hCtxDma */ + NULL, /* pSurfaceDesc */ pUpdateState); pApiHeadState->vblankSyncObjects[i].enabled = FALSE; } @@ -2236,8 +2315,6 @@ ApplyProposedModeSetHwStateOneHeadShutDown( nvkms_memset(&pHeadState->timings, 0, sizeof(pHeadState->timings)); pHeadState->activeRmId = 0; - pHeadState->allowFlipLockGroup = 0; - nvkms_memset(&pHeadState->audio, 0, sizeof(pHeadState->audio)); nvkms_memset(&pHeadState->modeValidationParams, 0, @@ -2328,7 +2405,7 @@ ApplyProposedModeSetStateOneApiHeadShutDown( pDpyEvo = nvGetOneArbitraryDpyEvo(pApiHeadState->activeDpys, pDispEvo); - nvCancelSDRTransitionTimer(pApiHeadState); + nvCancelSDRTransitionTimer(pDpyEvo); /* * Identify and disable any active core RG sync objects. @@ -2411,6 +2488,18 @@ ApplyProposedModeSetStateOneDispFlip( } } + pDispEvo->apiHeadState[apiHead].tf = + pProposedApiHead->tf; + + pDispEvo->apiHeadState[apiHead].colorimetry = + pProposedApiHead->colorimetry; + + pDispEvo->apiHeadState[apiHead].hdrInfoFrameOverride = + pProposedApiHead->hdrInfoFrameOverride; + + pDispEvo->apiHeadState[apiHead].hdrStaticMetadataLayerMask = + pProposedApiHead->hdrStaticMetadataLayerMask; + pDispEvo->apiHeadState[apiHead].viewPortPointIn = pProposedApiHead->viewPortPointIn; } @@ -2433,7 +2522,7 @@ static void ReEnableActiveCoreRGSyncObjects(NVDispEvoRec *pDispEvo, pDispEvo->headState[head].timings.rasterBlankStart.y, head, i, - pApiHeadState->vblankSyncObjects[i].evoSyncpt.hCtxDma, + &pApiHeadState->vblankSyncObjects[i].evoSyncpt.surfaceDesc, pUpdateState); pApiHeadState->vblankSyncObjects[i].enabled = TRUE; @@ -2454,7 +2543,6 @@ ApplyProposedModeSetHwStateOneHeadPreUpdate( NVDispHeadStateEvoPtr pHeadState = &pDispEvo->headState[head]; NVEvoUpdateState *updateState = &pModesetUpdateState->updateState; - pHeadState->allowFlipLockGroup = pProposedApiHead->allowFlipLockGroup; pHeadState->modeValidationParams = pProposedApiHead->modeValidationParams; pHeadState->bypassComposition = bypassComposition; pHeadState->activeRmId = pProposedApiHead->activeRmId; @@ -2463,6 +2551,7 @@ ApplyProposedModeSetHwStateOneHeadPreUpdate( pHeadState->timings = pProposedHead->timings; pHeadState->dscInfo = pProposedApiHead->dscInfo; pHeadState->hdmiFrlConfig = pProposedHead->hdmiFrlConfig; + pHeadState->hdmiFrlBpc = pProposedHead->hdmiFrlBpc; pHeadState->pixelDepth = nvEvoColorSpaceBpcToPixelDepth(pProposedApiHead->attributes.colorSpace, pProposedApiHead->attributes.colorBpc); @@ -2483,6 +2572,7 @@ ApplyProposedModeSetHwStateOneHeadPreUpdate( /* Update hardware's current colorSpace and colorRange */ nvUpdateCurrentHardwareColorSpaceAndRangeEvo(pDispEvo, head, + pProposedApiHead->colorimetry, pProposedApiHead->attributes.colorSpace, pProposedApiHead->attributes.colorRange, updateState); @@ -2621,7 +2711,11 @@ ApplyProposedModeSetStateOneApiHeadPreUpdate( nvSendHwModeTimingsToAegisEvo(pDispEvo, apiHead); - /* Set LUT settings */ + /* Set LUT settings + * + * Don't set the LUT notifier because we're already waiting on a core + * notifier for the update. + */ nvEvoSetLut(pDispEvo, apiHead, FALSE /* kickoff */, &pProposedApiHead->lut); FOR_EACH_EVO_HW_HEAD_IN_MASK(pProposedApiHead->hwHeadsMask, head) { @@ -2650,6 +2744,11 @@ ApplyProposedModeSetStateOneApiHeadPreUpdate( pApiHeadState->attributes = pProposedApiHead->attributes; pApiHeadState->tf = pProposedApiHead->tf; + pApiHeadState->colorimetry = pProposedApiHead->colorimetry; + pApiHeadState->hdrInfoFrameOverride = + pProposedApiHead->hdrInfoFrameOverride; + pApiHeadState->hdrStaticMetadataLayerMask = + pProposedApiHead->hdrStaticMetadataLayerMask; pApiHeadState->hs10bpcHint = pProposedApiHead->hs10bpcHint; if (nvPopCount32(pProposedApiHead->hwHeadsMask) > 1) { @@ -3085,8 +3184,6 @@ ApplyProposedModeSetHwStateOneDisp( bypassComposition, pWorkArea); - nvEvoLockStateSetMergeMode(pDispEvo); - /* * This function waits for 2 frames to make sure that the final IMP * arbitration settings have been programmed by the post-SV3 worker thread @@ -3287,7 +3384,7 @@ ValidateRequest(const NVDevEvoRec *pDevEvo, continue; } - if (!nvValidateSetLutCommonParams(pDevEvo, &pRequestHead->lut)) { + if (!nvValidateSetLutCommonParams(pDevEvo, &pRequestHead->flip.lut)) { pReply->disp[dispIndex].head[apiHead].status = NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_LUT; ret = FALSE; @@ -3607,7 +3704,6 @@ NvBool nvSetDispModeEvo(NVDevEvoPtr pDevEvo, sizeof(*pProposed)); NvU32 dispIndex; NVDispEvoPtr pDispEvo; - NvU32 dispNeedsEarlyUpdate; NvBool updateCoreFirst = FALSE; NvBool committed = FALSE; @@ -3681,37 +3777,15 @@ NvBool nvSetDispModeEvo(NVDevEvoPtr pDevEvo, BeginEndModeset(pDevEvo, pProposed, BEGIN_MODESET); - nvEvoLockStatePreModeset(pDevEvo, &dispNeedsEarlyUpdate, &pWorkArea->earlyUpdateState); + nvEvoLockStatePreModeset(pDevEvo); + + nvEvoRemoveOverlappingFlipLockRequestGroupsForModeset(pDevEvo, pRequest); nvDisableVrr(pDevEvo); updateCoreFirst = pDevEvo->coreInitMethodsPending; pDevEvo->coreInitMethodsPending = FALSE; - /* - * If the core channel has assembly state we need to be committed - * before proceeding through the rest of the modeset, kickoff here. - * This is used to disable fliplock before issuing base flips - * in ApplyProposedModeSetHwStateOneDisp. - * - * XXX This violates the assumption (guarded by - * pDevEvo->coreInitMethodsPending) that we aren't kicking - * off until after the assembly core channel state (which we don't - * want to commit) has already been overwritten below and made safe - * for kickoff. Because of this, needsEarlyUpdate should only be set - * when it is safe to kickoff the existing core channel assembly - * state immediately. Currently it is only set when the call - * to nvEvoLockStatePreModeset() above disabled fliplock, at which - * point there should be no invalid state remaining in the - * core channel assembly. - */ - FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { - if (dispNeedsEarlyUpdate & (1 << dispIndex)) { - nvEvoUpdateAndKickOff(pDispEvo, TRUE, &pWorkArea->earlyUpdateState, - TRUE /* releaseElv */); - } - } - FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { ApplyProposedModeSetHwStateOneDisp(pDispEvo, pProposed, @@ -3879,12 +3953,18 @@ void nvApiHeadUnregisterVBlankCallback(NVDispEvoPtr pDispEvo, * Perform a modeset that disables some or all api heads. * * \param[in] pDevEvo The device to shut down. + * \param[in] pOpenDev The pOpenDev of the client doing the disabling. * \param[in] pTestFunc The pointer to test function, identifying heads * targeted to shut down. If NULL then shut down * all heads. + * \param[in] pData Data passed to the test function. + * \param[in] doRasterLock Allow rasterlock to be implicitly enabled */ void nvShutDownApiHeads(NVDevEvoPtr pDevEvo, - NVShutDownApiHeadsTestFunc pTestFunc) + struct NvKmsPerOpenDev *pOpenDev, + NVShutDownApiHeadsTestFunc pTestFunc, + void *pData, + NvBool doRasterLock) { if (pDevEvo->displayHandle != 0) { struct NvKmsSetModeParams *params = @@ -3907,7 +3987,7 @@ void nvShutDownApiHeads(NVDevEvoPtr pDevEvo, * XXX pTestFunc isn't honored by nvSetDispModeEvo()'s * InheritPreviousModesetState() logic. */ - if (pTestFunc && !pTestFunc(pDispEvo, apiHead)) { + if (pTestFunc && !pTestFunc(pDispEvo, apiHead, pData)) { continue; } @@ -3940,9 +4020,9 @@ void nvShutDownApiHeads(NVDevEvoPtr pDevEvo, } } - nvSetDispModeEvo(pDevEvo, pDevEvo->pNvKmsOpenDev, req, + nvSetDispModeEvo(pDevEvo, pOpenDev, req, ¶ms->reply, FALSE /* bypassComposition */, - TRUE /* doRastertLock */); + doRasterLock); } nvPreallocRelease(pDevEvo, PREALLOC_TYPE_SHUT_DOWN_HEADS_SET_MODE); @@ -3967,7 +4047,7 @@ nvApiHeadAddRgLine1Callback(NVDispEvoRec *pDispEvo, */ const NvU32 head = nvGetPrimaryHwHead(pDispEvo, apiHead); if (head == NV_INVALID_HEAD) { - return FALSE; + return NULL; } return nvRmAddRgLine1Callback(pDispEvo, head, pCallbackProc, pUserData); } diff --git a/src/nvidia-modeset/src/nvkms-prealloc.c b/src/nvidia-modeset/src/nvkms-prealloc.c index c1eb1fef5a..fbf661901c 100644 --- a/src/nvidia-modeset/src/nvkms-prealloc.c +++ b/src/nvidia-modeset/src/nvkms-prealloc.c @@ -62,6 +62,8 @@ static size_t GetSizeForType(NVDevEvoPtr pDevEvo, enum NVPreallocType type) return sizeof(NVHwModeTimingsEvo) * NVKMS_MAX_HEADS_PER_DISP; case PREALLOC_TYPE_VALIDATE_MODE_TMP_USAGE_BOUNDS: return sizeof(struct NvKmsUsageBounds); + case PREALLOC_TYPE_DPLIB_IS_MODE_POSSIBLE_PARAMS: + return sizeof(NVDpLibIsModePossibleParamsRec); case PREALLOC_TYPE_MAX: /* Not a real option, but added for -Wswitch-enum */ break; diff --git a/src/nvidia-modeset/src/nvkms-rm.c b/src/nvidia-modeset/src/nvkms-rm.c index 0daf65556b..9e4f913333 100644 --- a/src/nvidia-modeset/src/nvkms-rm.c +++ b/src/nvidia-modeset/src/nvkms-rm.c @@ -43,7 +43,6 @@ #include "nvkms-push.h" #include "nvkms-difr.h" -#include "class/cl0002.h" /* NV01_CONTEXT_DMA */ #include "class/cl0005.h" /* NV01_EVENT */ #include // NV01_MEMORY_VIRTUAL @@ -296,7 +295,7 @@ static void FreeDisplay(NVDispEvoPtr pDispEvo) nvkms_free_ref_ptr(pDispEvo->ref_ptr); - nvInvalidateTopologiesEvo(); + nvInvalidateRasterLockGroupsEvo(); nvFree(pDispEvo); } @@ -1476,9 +1475,9 @@ static void FreeDpys(NVDispEvoPtr pDispEvo) * This function is registered as the kernel callback function from * resman when an NV2080_NOTIFIERS_HOTPLUG event is generated. * - * However, this function is called with resman's context (alternate - * stack, resman locks held, etc). Schedule deferred work, so that we - * can process the hotplug event without resman's encumbrances. + * However, this function is called with resman's context (resman locks held, + * etc). Schedule deferred work, so that we can process the hotplug event + * without resman's encumbrances. */ static void ReceiveHotplugEvent(void *arg, void *pEventDataVoid, NvU32 hEvent, NvU32 Data, NV_STATUS Status) @@ -2379,14 +2378,13 @@ NvBool nvRmAllocSysmem(NVDevEvoPtr pDevEvo, NvU32 memoryHandle, NvBool nvRmAllocEvoDma(NVDevEvoPtr pDevEvo, NVEvoDmaPtr pDma, NvU64 limit, NvU32 ctxDmaFlags, NvU32 subDeviceMask) { - NV_CONTEXT_DMA_ALLOCATION_PARAMS ctxdmaParams = { }; NvBool bufferAllocated = FALSE; NvU32 memoryHandle = 0; void *pBase = NULL; NvBool needBar1Mapping = FALSE; - NvU32 ctxDmaHandle = 0; + NVSurfaceDescriptor surfaceDesc; NvU32 localCtxDmaFlags = ctxDmaFlags | DRF_DEF(OS03, _FLAGS, _ACCESS, _READ_WRITE) | DRF_DEF(OS03, _FLAGS, _HASH_TABLE, _DISABLE); @@ -2454,19 +2452,9 @@ NvBool nvRmAllocEvoDma(NVDevEvoPtr pDevEvo, NVEvoDmaPtr pDma, return FALSE; } - ctxDmaHandle = nvGenerateUnixRmHandle(&pDevEvo->handleAllocator); - - // Create a ctxdma for this allocation. - ctxdmaParams.hMemory = memoryHandle; - ctxdmaParams.flags = localCtxDmaFlags; - ctxdmaParams.offset = 0; - ctxdmaParams.limit = limit; - - ret = nvRmApiAlloc(nvEvoGlobal.clientHandle, - pDevEvo->deviceHandle, - ctxDmaHandle, - NV01_CONTEXT_DMA, - &ctxdmaParams); + // Create surface descriptor for this allocation. + ret = pDevEvo->hal->AllocSurfaceDescriptor(pDevEvo, &surfaceDesc, memoryHandle, + localCtxDmaFlags, limit); if (ret != NVOS_STATUS_SUCCESS) { if (pBase != NULL) { @@ -2480,16 +2468,14 @@ NvBool nvRmAllocEvoDma(NVDevEvoPtr pDevEvo, NVEvoDmaPtr pDma, pDevEvo->deviceHandle, memoryHandle); nvFreeUnixRmHandle(&pDevEvo->handleAllocator, memoryHandle); - nvFreeUnixRmHandle(&pDevEvo->handleAllocator, ctxDmaHandle); - - nvEvoLogDev(pDevEvo, EVO_LOG_ERROR, "Failed to allocate a DMA context"); + nvEvoLogDev(pDevEvo, EVO_LOG_ERROR, "Failed to allocate surface descriptor"); return FALSE; } pDma->memoryHandle = memoryHandle; - pDma->ctxHandle = ctxDmaHandle; + pDma->surfaceDesc = surfaceDesc; pDma->limit = limit; @@ -2523,17 +2509,9 @@ void nvRmFreeEvoDma(NVDevEvoPtr pDevEvo, NVEvoDmaPtr pDma) { NvU32 ret; - if (pDma->ctxHandle != 0) { - ret = nvRmApiFree(nvEvoGlobal.clientHandle, - pDevEvo->deviceHandle, pDma->ctxHandle); - - if (ret != NVOS_STATUS_SUCCESS) { - nvEvoLogDev(pDevEvo, EVO_LOG_ERROR, "Failed to free DMA context"); - } - - nvFreeUnixRmHandle(&pDevEvo->handleAllocator, pDma->ctxHandle); - pDma->ctxHandle = 0; - } + pDevEvo->hal->FreeSurfaceDescriptor(pDevEvo, + pDevEvo->deviceHandle, + &pDma->surfaceDesc); if (pDma->memoryHandle != 0) { if (pDma->isBar1Mapping) { @@ -2677,7 +2655,7 @@ RmAllocEvoChannel(NVDevEvoPtr pDevEvo, // Channel instance (always 0 for CORE - head number otherwise) ChannelAllocParams.channelInstance = instance; // PB CtxDMA Handle - ChannelAllocParams.hObjectBuffer = buffer->dma.ctxHandle; + ChannelAllocParams.hObjectBuffer = buffer->dma.surfaceDesc.ctxDmaHandle; // Initial offset within the PB ChannelAllocParams.offset = 0; @@ -3085,9 +3063,10 @@ NvBool nvRMAllocateOverlayChannels(NVDevEvoPtr pDevEvo) static NvBool AllocSyncpt(NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChannel, NVEvoSyncpt *pEvoSyncptOut) { - NvU32 hSyncptCtxDma, hSyncpt, id; + NvU32 id; NvKmsSyncPtOpParams params = { }; NvBool result; + NVSurfaceDescriptor surfaceDesc; if (!pDevEvo->supportsSyncpts) { return FALSE; @@ -3116,15 +3095,13 @@ static NvBool AllocSyncpt(NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChannel, } result = nvRmEvoAllocAndBindSyncpt(pDevEvo, pChannel, id, - &hSyncpt, &hSyncptCtxDma); + &surfaceDesc, + pEvoSyncptOut); if (!result) { goto failed; } /*! Populate syncpt values to return. */ - pEvoSyncptOut->id = id; - pEvoSyncptOut->hCtxDma = hSyncptCtxDma; - pEvoSyncptOut->hSyncpt = hSyncpt; pEvoSyncptOut->channelMask = pChannel->channelMask; pEvoSyncptOut->syncptMaxVal = params.read_minval.minval; @@ -3192,12 +3169,13 @@ NvBool nvRMAllocateWindowChannels(NVDevEvoPtr pDevEvo) } for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { - NvU32 ret = nvRmEvoBindDispContextDMA(pDevEvo, - pDevEvo->window[window], - pDevEvo->window[window]->notifiersDma[sd].ctxHandle); + NvU32 ret = pDevEvo->hal->BindSurfaceDescriptor( + pDevEvo, + pDevEvo->window[window], + &pDevEvo->window[window]->notifiersDma[sd].surfaceDesc); if (ret != NVOS_STATUS_SUCCESS) { nvEvoLogDev(pDevEvo, EVO_LOG_ERROR, - "Failed to bind(window channel) display engine notify context DMA: 0x%x (%s)", + "Failed to bind(window channel) display engine notify surface descriptor: 0x%x (%s)", ret, nvstatusToString(ret)); return FALSE; } @@ -3351,13 +3329,14 @@ NvBool nvRMSetupEvoCoreChannel(NVDevEvoPtr pDevEvo) } for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { - // Bind the core notifier ctxDma + // Bind the core notifier surface descriptor NvU32 ret = - nvRmEvoBindDispContextDMA(pDevEvo, pDevEvo->core, - pDevEvo->core->notifiersDma[sd].ctxHandle); + pDevEvo->hal->BindSurfaceDescriptor( + pDevEvo, pDevEvo->core, + &pDevEvo->core->notifiersDma[sd].surfaceDesc); if (ret != NVOS_STATUS_SUCCESS) { nvEvoLogDev(pDevEvo, EVO_LOG_ERROR, - "Failed to bind display engine notify context DMA: 0x%x (%s)", + "Failed to bind display engine notify surface descriptor: 0x%x (%s)", ret, nvstatusToString(ret)); nvRMFreeEvoCoreChannel(pDevEvo); return FALSE; @@ -3473,14 +3452,12 @@ static NvBool SyncOneEvoChannel( break; } - if (!nvIsEmulationEvo(pDevEvo)) { - if (nvExceedsTimeoutUSec(&startTime, timeout)) { - nvEvoLogDev(pDevEvo, EVO_LOG_ERROR, - "Idling display engine timed out: 0x%08x:%d:%d:%d", - pChan->hwclass, pChan->instance, - sd, errorToken); - return FALSE; - } + if (nvExceedsTimeoutUSec(pDevEvo, &startTime, timeout)) { + nvEvoLogDev(pDevEvo, EVO_LOG_ERROR, + "Idling display engine timed out: 0x%08x:%d:%d:%d", + pChan->hwclass, pChan->instance, + sd, errorToken); + return FALSE; } nvkms_yield(); @@ -3546,7 +3523,7 @@ NvBool nvRMIdleBaseChannel(NVDevEvoPtr pDevEvo, NvU32 head, NvU32 sd, break; } - if (nvExceedsTimeoutUSec(&startTime, timeout)) { + if (nvExceedsTimeoutUSec(pDevEvo, &startTime, timeout)) { idleTimedOut = TRUE; break; } @@ -3596,13 +3573,13 @@ NvBool nvRmEvoAllocAndBindSyncpt( NVDevEvoRec *pDevEvo, NVEvoChannel *pChannel, NvU32 id, - NvU32 *pSyncptHandle, - NvU32 *pSyncptCtxDmaHandle) + NVSurfaceDescriptor *pSurfaceDesc, + NVEvoSyncpt *pEvoSyncpt) { return FALSE; } -static void FreeSyncptHandle( +void nvRmFreeSyncptHandle( NVDevEvoRec *pDevEvo, NVEvoSyncpt *pSyncpt) { @@ -3613,12 +3590,10 @@ static void FreeSyncptHandle( pSyncpt->hSyncpt); pSyncpt->hSyncpt = 0; - nvRmApiFree(nvEvoGlobal.clientHandle, - pDevEvo->deviceHandle, - pSyncpt->hCtxDma); - nvFreeUnixRmHandle(&pDevEvo->handleAllocator, - pSyncpt->hCtxDma); - pSyncpt->hCtxDma = 0; + pDevEvo->hal->FreeSurfaceDescriptor(pDevEvo, + pDevEvo->deviceHandle, + &pSyncpt->surfaceDesc); + pSyncpt->allocated = FALSE; } /*! @@ -3657,79 +3632,14 @@ void nvRmEvoFreePreSyncpt( pDevEvo->preSyncptTable[i].channelMask &= ~pChannel->channelMask; if (pDevEvo->preSyncptTable[i].channelMask == 0 && - pDevEvo->preSyncptTable[i].hCtxDma != 0) { + pDevEvo->preSyncptTable[i].allocated) { /*! Free handles */ - FreeSyncptHandle(pDevEvo, &pDevEvo->preSyncptTable[i]); + nvRmFreeSyncptHandle(pDevEvo, &pDevEvo->preSyncptTable[i]); } } } -static NvBool GarbageCollectSyncptHelperOneChannel( - NVDevEvoRec *pDevEvo, - NvU32 sd, - NVEvoChannel *pChannel, - NVEvoSyncpt *pSyncpt, - NVEvoChannelMask *pIdledChannelMask) -{ - NvBool isChannelIdle = FALSE; - - if ((pChannel->channelMask & pSyncpt->channelMask) == 0) { - return TRUE; - } - - if ((*pIdledChannelMask) & pChannel->channelMask) { - goto done; - } - - /*! Check whether channel is idle. */ - pDevEvo->hal->IsChannelIdle(pDevEvo, pChannel, sd, &isChannelIdle); - - if (!isChannelIdle) { - return FALSE; - } - - /*! record idle channel mask to use in next check */ - *pIdledChannelMask |= pChannel->channelMask; - -done: - pSyncpt->channelMask &= ~pChannel->channelMask; - return TRUE; -} - -static NvBool GarbageCollectSyncptHelperOneSyncpt( - NVDevEvoRec *pDevEvo, - NVEvoSyncpt *pSyncpt, - NVEvoChannelMask *pIdledChannelMask) -{ - NvBool ret = TRUE; - NvU32 head, sd; - - for (sd = 0; sd < pDevEvo->numSubDevices; sd++) { - - for (head = 0; head < pDevEvo->numHeads; head++) { - NvU32 layer; - - /*! - * If a given channel isn't idle, continue to check if this syncpt - * is used on other channels which may be idle. - */ - for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { - if (!GarbageCollectSyncptHelperOneChannel( - pDevEvo, - sd, - pDevEvo->head[head].layer[layer], - pSyncpt, - &pIdledChannelMask[sd])) { - ret = FALSE; - } - } - } - } - - return ret; -} - /*! * This API is used to unregister the given syncpt object. */ @@ -3748,186 +3658,7 @@ void nvRmEvoFreeSyncpt( nvkms_syncpt_op(NVKMS_SYNCPT_OP_PUT, ¶ms); /*! Free handles */ - FreeSyncptHandle(pDevEvo, pEvoSyncpt); -} - -/*! - * This API try to find free syncpt and then unregisters it. - * It searches global table, and when finds that all channels using this - * syncpt are idle then frees it. It makes sure that syncpt is not part - * of current flip. - */ -NvBool nvRmGarbageCollectSyncpts( - NVDevEvoRec *pDevEvo) -{ - NvU32 i; - NvBool freedSyncpt = FALSE; - NVEvoChannelMask idledChannelMask[NVKMS_MAX_SUBDEVICES] = { 0 }; - - if (!pDevEvo->supportsSyncpts) { - return FALSE; - } - - for (i = 0; i < NV_SYNCPT_GLOBAL_TABLE_LENGTH; i++) { - - NvBool allLayersIdle = NV_TRUE; - - if (pDevEvo->pAllSyncptUsedInCurrentFlip != NULL) { - if (pDevEvo->pAllSyncptUsedInCurrentFlip[i]) { - /*! syncpt is part of current flip, so skip it */ - continue; - } - } - - if (pDevEvo->preSyncptTable[i].hCtxDma == 0) { - /*! syncpt isn't registered, so skip it */ - continue; - } - - allLayersIdle = GarbageCollectSyncptHelperOneSyncpt( - pDevEvo, - &pDevEvo->preSyncptTable[i], - idledChannelMask); - - if (allLayersIdle) { - /*! Free handles */ - FreeSyncptHandle(pDevEvo, &pDevEvo->preSyncptTable[i]); - freedSyncpt = TRUE; - } - } - - return freedSyncpt; -} - -NvU32 nvRmEvoBindDispContextDMA( - NVDevEvoPtr pDevEvo, - NVEvoChannelPtr pChannel, - NvU32 hCtxDma) -{ - NV0002_CTRL_BIND_CONTEXTDMA_PARAMS params = { }; - NvU32 ret; - NvBool retryOnlyOnce = TRUE; - - params.hChannel = pChannel->pb.channel_handle; - -retryOnce: - ret = nvRmApiControl(nvEvoGlobal.clientHandle, - hCtxDma, - NV0002_CTRL_CMD_BIND_CONTEXTDMA, - ¶ms, sizeof(params)); - if (ret != NVOS_STATUS_SUCCESS) { - /*! - * syncpts (lazily freed) occupy space in the disp ctxDma hash - * table, and therefore may cause bind ctxDma to fail. - * Free any unused syncpts and try again. - */ - if (retryOnlyOnce) { - /*! try to free syncpt only once */ - if (nvRmGarbageCollectSyncpts(pDevEvo)) { - retryOnlyOnce = FALSE; - goto retryOnce; - } - } - } - return ret; -} - - -NvU32 nvRmEvoAllocateAndBindDispContextDMA( - NVDevEvoPtr pDevEvo, - NvU32 hMemory, - const enum NvKmsSurfaceMemoryLayout layout, - NvU64 limit) -{ - NV_CONTEXT_DMA_ALLOCATION_PARAMS ctxdmaParams = { }; - NvU32 hDispCtxDma; - NvU32 flags = DRF_DEF(OS03, _FLAGS, _HASH_TABLE, _DISABLE); - NvU32 ret; - int h; - - /* each surface to be displayed needs its own ctx dma. */ - nvAssert(pDevEvo->displayHandle != 0); - - nvAssert(pDevEvo->core); - nvAssert(pDevEvo->core->pb.channel_handle); - - nvAssert(hMemory); - nvAssert(limit); - - switch (layout) { - case NvKmsSurfaceMemoryLayoutBlockLinear: - flags |= DRF_DEF(OS03, _FLAGS, _PTE_KIND, _BL); - break; - case NvKmsSurfaceMemoryLayoutPitch: - flags |= DRF_DEF(OS03, _FLAGS, _PTE_KIND, _PITCH); - break; - } - - hDispCtxDma = nvGenerateUnixRmHandle(&pDevEvo->handleAllocator); - - ctxdmaParams.hMemory = hMemory; - ctxdmaParams.flags = flags; - ctxdmaParams.offset = 0; - ctxdmaParams.limit = limit; - - ret = nvRmApiAlloc(nvEvoGlobal.clientHandle, - pDevEvo->deviceHandle, - hDispCtxDma, - NV01_CONTEXT_DMA, - &ctxdmaParams); - - if (ret != NVOS_STATUS_SUCCESS) { - goto cleanup_this_handle_and_fail; - } - - ret = nvRmEvoBindDispContextDMA(pDevEvo, pDevEvo->core, hDispCtxDma); - - if (ret != NVOS_STATUS_SUCCESS) { - goto free_this_handle_and_fail; - } - - for (h = 0; h < pDevEvo->numHeads; h++) { - NvU32 layer; - - for (layer = 0; layer < pDevEvo->head[h].numLayers; layer++) { - if (pDevEvo->head[h].layer[layer]) { - nvAssert(pDevEvo->head[h].layer[layer]->pb.channel_handle); - - ret = nvRmEvoBindDispContextDMA(pDevEvo, - pDevEvo->head[h].layer[layer], - hDispCtxDma); - - if (ret != NVOS_STATUS_SUCCESS) { - goto free_this_handle_and_fail; - } - } - } - } - - return hDispCtxDma; - -free_this_handle_and_fail: - - nvRmApiFree(nvEvoGlobal.clientHandle, - nvEvoGlobal.clientHandle, hDispCtxDma); - - /* Fall through */ -cleanup_this_handle_and_fail: - - nvFreeUnixRmHandle(&pDevEvo->handleAllocator, hDispCtxDma); - - return 0; -} - -void nvRmEvoFreeDispContextDMA(NVDevEvoPtr pDevEvo, - NvU32 *hDispCtxDma) -{ - if (*hDispCtxDma) { - nvRmApiFree(nvEvoGlobal.clientHandle, - nvEvoGlobal.clientHandle, *hDispCtxDma); - nvFreeUnixRmHandle(&pDevEvo->handleAllocator, *hDispCtxDma); - *hDispCtxDma = 0; - } + nvRmFreeSyncptHandle(pDevEvo, pEvoSyncpt); } void nvRmEvoUnMapVideoMemory(NVDevEvoPtr pDevEvo, NvU32 memoryHandle, @@ -4400,8 +4131,8 @@ static void NonStallInterruptCallback( NV_STATUS status) { /* - * We are called within resman's altstack and locks. Schedule a separate - * callback to execute with the nvkms_lock. + * We are called within resman's locks. Schedule a separate callback to + * execute with the nvkms_lock. * * XXX It might be nice to use a lighter-weight lock here to check if any * requests are pending in any NvKmsDeferredRequestFifo before scheduling @@ -5768,3 +5499,73 @@ void nvRmUnregisterBacklight(NVDispEvoRec *pDispEvo) } pDispEvo->backlightDevice = NULL; } + +NvU32 nvRmAllocAndBindSurfaceDescriptor( + NVDevEvoPtr pDevEvo, + NvU32 hMemory, + const enum NvKmsSurfaceMemoryLayout layout, + NvU64 limit, + NVSurfaceDescriptor *pSurfaceDesc) +{ + NVSurfaceDescriptor surfaceDesc; + NvU32 flags = DRF_DEF(OS03, _FLAGS, _HASH_TABLE, _DISABLE); + NvU32 head, layer; + NvU32 ret; + + switch (layout) { + case NvKmsSurfaceMemoryLayoutBlockLinear: + flags |= DRF_DEF(OS03, _FLAGS, _PTE_KIND, _BL); + break; + case NvKmsSurfaceMemoryLayoutPitch: + flags |= DRF_DEF(OS03, _FLAGS, _PTE_KIND, _PITCH); + break; + } + + /* Each surface to be displayed needs its own surface descriptor */ + nvAssert(pDevEvo->displayHandle != 0); + nvAssert(pDevEvo->core); + nvAssert(pDevEvo->core->pb.channel_handle); + nvAssert(hMemory); + nvAssert(limit); + + ret = + pDevEvo->hal->AllocSurfaceDescriptor(pDevEvo, &surfaceDesc, + hMemory, flags, limit); + + if (ret != NVOS_STATUS_SUCCESS) { + return ret; + } + + ret = + pDevEvo->hal->BindSurfaceDescriptor(pDevEvo, + pDevEvo->core, + &surfaceDesc); + if (ret != NVOS_STATUS_SUCCESS) { + goto free_this_handle_and_fail; + } + + for (head = 0; head < pDevEvo->numHeads; head++) { + for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) { + if (pDevEvo->head[head].layer[layer]) { + nvAssert(pDevEvo->head[head].layer[layer]->pb.channel_handle); + + ret = pDevEvo->hal->BindSurfaceDescriptor(pDevEvo, + pDevEvo->head[head].layer[layer], + &surfaceDesc); + if (ret != NVOS_STATUS_SUCCESS) { + goto free_this_handle_and_fail; + } + } + } + } + + *pSurfaceDesc = surfaceDesc; + + return NVOS_STATUS_SUCCESS; + +free_this_handle_and_fail: + pDevEvo->hal->FreeSurfaceDescriptor(pDevEvo, + nvEvoGlobal.clientHandle, + &surfaceDesc); + return ret; +} diff --git a/src/nvidia-modeset/src/nvkms-rmapi-dgpu.c b/src/nvidia-modeset/src/nvkms-rmapi-dgpu.c index ab3a9f8a8c..2c652441a4 100644 --- a/src/nvidia-modeset/src/nvkms-rmapi-dgpu.c +++ b/src/nvidia-modeset/src/nvkms-rmapi-dgpu.c @@ -25,6 +25,7 @@ #include "nvidia-modeset-os-interface.h" #include "nvkms-rmapi.h" +#include "nv_assert.h" NvU32 nvRmApiAlloc( NvU32 hClient, @@ -99,10 +100,10 @@ NvU32 nvRmApiControl( return ops.params.control.status; } -NvU32 nvRmApiDupObject( +NvU32 nvRmApiDupObject2( NvU32 hClient, NvU32 hParent, - NvU32 hObjectDest, + NvU32 *hObjectDest, NvU32 hClientSrc, NvU32 hObjectSrc, NvU32 flags) @@ -113,16 +114,39 @@ NvU32 nvRmApiDupObject( ops.params.dupObject.hClient = hClient; ops.params.dupObject.hParent = hParent; - ops.params.dupObject.hObject = hObjectDest; + ops.params.dupObject.hObject = *hObjectDest; ops.params.dupObject.hClientSrc = hClientSrc; ops.params.dupObject.hObjectSrc = hObjectSrc; ops.params.dupObject.flags = flags; nvkms_call_rm(&ops); + *hObjectDest = ops.params.dupObject.hObject; + return ops.params.dupObject.status; } +NvU32 nvRmApiDupObject( + NvU32 hClient, + NvU32 hParent, + NvU32 hObjectDest, + NvU32 hClientSrc, + NvU32 hObjectSrc, + NvU32 flags) +{ + NvU32 hObjectLocal = hObjectDest; + NvU32 ret = nvRmApiDupObject2(hClient, + hParent, + &hObjectLocal, + hClientSrc, + hObjectSrc, + flags); + + nvAssert(hObjectLocal == hObjectDest); + + return ret; +} + NvU32 nvRmApiFree( NvU32 hClient, NvU32 hParent, diff --git a/src/nvidia-modeset/src/nvkms-surface.c b/src/nvidia-modeset/src/nvkms-surface.c index 38298a3270..c960505a62 100644 --- a/src/nvidia-modeset/src/nvkms-surface.c +++ b/src/nvidia-modeset/src/nvkms-surface.c @@ -64,8 +64,9 @@ static void FreeSurfaceEvoRm(NVDevEvoPtr pDevEvo, NVSurfaceEvoPtr pSurfaceEvo) nvAssert(pSurfaceEvo->rmRefCnt == 0); FOR_ALL_VALID_PLANES(planeIndex, pSurfaceEvo) { - nvRmEvoFreeDispContextDMA(pDevEvo, - &pSurfaceEvo->planes[planeIndex].ctxDma); + pDevEvo->hal->FreeSurfaceDescriptor(pDevEvo, + nvEvoGlobal.clientHandle, + &pSurfaceEvo->planes[planeIndex].surfaceDesc); } firstPlaneRmHandle = pSurfaceEvo->planes[0].rmHandle; @@ -486,18 +487,16 @@ void nvEvoRegisterSurface(NVDevEvoPtr pDevEvo, /* XXX Validate sizeInBytes: can we query the surface size from RM? */ if (!pRequest->noDisplayHardwareAccess) { - - const NvU32 planeCtxDma = - nvRmEvoAllocateAndBindDispContextDMA( - pDevEvo, - planeRmHandle, - pRequest->layout, - pRequest->planes[planeIndex].rmObjectSizeInBytes - 1); - if (!planeCtxDma) { + NvU32 ret = + nvRmAllocAndBindSurfaceDescriptor( + pDevEvo, + planeRmHandle, + pRequest->layout, + pRequest->planes[planeIndex].rmObjectSizeInBytes - 1, + &pSurfaceEvo->planes[planeIndex].surfaceDesc); + if (ret != NVOS_STATUS_SUCCESS) { goto fail; } - - pSurfaceEvo->planes[planeIndex].ctxDma = planeCtxDma; } pSurfaceEvo->planes[planeIndex].pitch = @@ -508,7 +507,7 @@ void nvEvoRegisterSurface(NVDevEvoPtr pDevEvo, pRequest->planes[planeIndex].rmObjectSizeInBytes; } - pSurfaceEvo->requireCtxDma = !pRequest->noDisplayHardwareAccess; + pSurfaceEvo->requireDisplayHardwareAccess = !pRequest->noDisplayHardwareAccess; pSurfaceEvo->noDisplayCaching = pRequest->noDisplayCaching; /* @@ -958,7 +957,7 @@ void nvEvoFreeClientSurfaces(NVDevEvoPtr pDevEvo, nvEvoDestroyApiHandle(pOpenDevSurfaceHandles, surfaceHandle); if (isOwner) { - nvEvoDecrementSurfaceRefCnts(pSurfaceEvo); + nvEvoDecrementSurfaceRefCnts(pDevEvo, pSurfaceEvo); } else { nvEvoDecrementSurfaceStructRefCnt(pSurfaceEvo); } @@ -1003,7 +1002,7 @@ void nvEvoUnregisterSurface(NVDevEvoPtr pDevEvo, /* Remove the handle from the calling client's namespace. */ nvEvoDestroyApiHandle(pOpenDevSurfaceHandles, surfaceHandle); - nvEvoDecrementSurfaceRefCnts(pSurfaceEvo); + nvEvoDecrementSurfaceRefCnts(pDevEvo, pSurfaceEvo); } void nvEvoReleaseSurface(NVDevEvoPtr pDevEvo, @@ -1041,15 +1040,13 @@ void nvEvoIncrementSurfaceRefCnts(NVSurfaceEvoPtr pSurfaceEvo) pSurfaceEvo->structRefCnt++; } -void nvEvoDecrementSurfaceRefCnts(NVSurfaceEvoPtr pSurfaceEvo) +void nvEvoDecrementSurfaceRefCnts(NVDevEvoPtr pDevEvo, + NVSurfaceEvoPtr pSurfaceEvo) { nvAssert(pSurfaceEvo->rmRefCnt >= 1); pSurfaceEvo->rmRefCnt--; if (pSurfaceEvo->rmRefCnt == 0) { - NVDevEvoPtr pDevEvo = - nvGetDevEvoFromOpenDev(pSurfaceEvo->owner.pOpenDev); - /* * Don't sync if this surface was registered as not requiring display * hardware access, to WAR timeouts that result from OGL unregistering @@ -1057,7 +1054,7 @@ void nvEvoDecrementSurfaceRefCnts(NVSurfaceEvoPtr pSurfaceEvo) * GLS hasn't had the opportunity to release semaphores with pending * flips. (Bug 2050970) */ - if (pSurfaceEvo->requireCtxDma) { + if (pSurfaceEvo->requireDisplayHardwareAccess) { nvEvoClearSurfaceUsage(pDevEvo, pSurfaceEvo); } @@ -1079,12 +1076,12 @@ static NVSurfaceEvoPtr GetSurfaceFromHandle( const NvKmsSurfaceHandle surfaceHandle, const NvBool isUsedByCursorChannel, const NvBool isUsedByLayerChannel, - const NvBool requireCtxDma) + const NvBool requireDisplayHardwareAccess) { NVSurfaceEvoPtr pSurfaceEvo = nvEvoGetPointerFromApiHandle(pOpenDevSurfaceHandles, surfaceHandle); - nvAssert(requireCtxDma || (!isUsedByCursorChannel && !isUsedByLayerChannel)); + nvAssert(requireDisplayHardwareAccess || (!isUsedByCursorChannel && !isUsedByLayerChannel)); if (pSurfaceEvo == NULL) { return NULL; @@ -1094,7 +1091,7 @@ static NVSurfaceEvoPtr GetSurfaceFromHandle( return NULL; } - if (requireCtxDma && !pSurfaceEvo->requireCtxDma) { + if (requireDisplayHardwareAccess && !pSurfaceEvo->requireDisplayHardwareAccess) { return NULL; } @@ -1105,15 +1102,15 @@ static NVSurfaceEvoPtr GetSurfaceFromHandle( } /* - * XXX If !requireCtxDma, fetched surfaces aren't going to be accessed by - * the display hardware, so they shouldn't need to be checked by + * XXX If !requireDisplayHardwareAccess, fetched surfaces aren't going to be + * accessed by the display hardware, so they shouldn't need to be checked by * nvEvoGetHeadSetStoragePitchValue(). These surfaces will be used as a * texture by the 3d engine. But previously all surfaces were checked by * nvEvoGetHeadSetStoragePitchValue() at registration time, and we don't * know if nvEvoGetHeadSetStoragePitchValue() was protecting us from any * surface dimensions that could cause trouble for the 3d engine. */ - if (isUsedByLayerChannel || !requireCtxDma) { + if (isUsedByLayerChannel || !requireDisplayHardwareAccess) { NvU8 planeIndex; FOR_ALL_VALID_PLANES(planeIndex, pSurfaceEvo) { @@ -1141,10 +1138,10 @@ NVSurfaceEvoPtr nvEvoGetSurfaceFromHandle( surfaceHandle, isUsedByCursorChannel, isUsedByLayerChannel, - TRUE /* requireCtxDma */); + TRUE /* requireDisplayHardwareAccess */); } -NVSurfaceEvoPtr nvEvoGetSurfaceFromHandleNoCtxDmaOk( +NVSurfaceEvoPtr nvEvoGetSurfaceFromHandleNoDispHWAccessOk( const NVDevEvoRec *pDevEvo, const NVEvoApiHandlesRec *pOpenDevSurfaceHandles, NvKmsSurfaceHandle surfaceHandle) @@ -1154,7 +1151,7 @@ NVSurfaceEvoPtr nvEvoGetSurfaceFromHandleNoCtxDmaOk( surfaceHandle, FALSE /* isUsedByCursorChannel */, FALSE /* isUsedByLayerChannel */, - FALSE /* requireCtxDma */); + FALSE /* requireDisplayHardwareAccess */); } /*! @@ -1224,7 +1221,7 @@ void nvEvoUnregisterDeferredRequestFifo( pDeferredRequestFifo->fifo, 0); - nvEvoDecrementSurfaceRefCnts(pDeferredRequestFifo->pSurfaceEvo); + nvEvoDecrementSurfaceRefCnts(pDevEvo, pDeferredRequestFifo->pSurfaceEvo); nvFree(pDeferredRequestFifo); } diff --git a/src/nvidia-modeset/src/nvkms-vrr.c b/src/nvidia-modeset/src/nvkms-vrr.c index 59d1801ca4..6fbc0af639 100644 --- a/src/nvidia-modeset/src/nvkms-vrr.c +++ b/src/nvidia-modeset/src/nvkms-vrr.c @@ -779,8 +779,6 @@ static NvBool RmEnableVrr(NVDevEvoPtr pDevEvo) } nvAssert(pDevEvo->hal->caps.supportsDisplayRate); return TRUE; - - return FALSE; } void nvGetDpyMinRefreshRateValidValues( diff --git a/src/nvidia-modeset/src/nvkms.c b/src/nvidia-modeset/src/nvkms.c index d597be7b6e..eb68e672f7 100644 --- a/src/nvidia-modeset/src/nvkms.c +++ b/src/nvidia-modeset/src/nvkms.c @@ -796,7 +796,7 @@ static void FreeSwapGroups(struct NvKmsPerOpenDev *pOpenDev) handle) { nvEvoDestroyApiHandle(&pOpenDev->swapGroupHandles, handle); - if (pDevEvo->modesetOwner == pOpenDev) { + if (nvKmsOpenDevHasSubOwnerPermissionOrBetter(pOpenDev)) { nvHsFreeSwapGroup(pDevEvo, pSwapGroup); } else { nvHsDecrementSwapGroupRefCnt(pSwapGroup); @@ -809,7 +809,8 @@ static void FreeSwapGroups(struct NvKmsPerOpenDev *pOpenDev) */ static NvBool ValidateNvKmsPermissions( const NVDevEvoRec *pDevEvo, - const struct NvKmsPermissions *pPermissions) + const struct NvKmsPermissions *pPermissions, + enum NvKmsClientType clientType) { if (pPermissions->type == NV_KMS_PERMISSIONS_TYPE_FLIPPING) { NvU32 d, h; @@ -870,6 +871,13 @@ static NvBool ValidateNvKmsPermissions( } } } + } else if (pPermissions->type == NV_KMS_PERMISSIONS_TYPE_SUB_OWNER) { + + /* Only kapi uses this permission type, so disallow it from userspace */ + if (clientType != NVKMS_CLIENT_KERNEL_SPACE) { + return FALSE; + } + } else { return FALSE; } @@ -913,6 +921,16 @@ static void AssignFullNvKmsModesetPermissions( } } +static void AssignFullNvKmsPermissions( + struct NvKmsPerOpenDev *pOpenDev +) +{ + NVDevEvoPtr pDevEvo = pOpenDev->pDevEvo; + + AssignFullNvKmsFlipPermissions(pDevEvo, &pOpenDev->flipPermissions); + AssignFullNvKmsModesetPermissions(pDevEvo, &pOpenDev->modesetPermissions); +} + /*! * Set the modeset owner to pOpenDev * @@ -942,9 +960,7 @@ static NvBool GrabModesetOwnership(struct NvKmsPerOpenDev *pOpenDev) pDevEvo->modesetOwner = pOpenDev; pDevEvo->modesetOwnerChanged = TRUE; - AssignFullNvKmsFlipPermissions(pDevEvo, &pOpenDev->flipPermissions); - AssignFullNvKmsModesetPermissions(pDevEvo, &pOpenDev->modesetPermissions); - + AssignFullNvKmsPermissions(pOpenDev); return TRUE; } @@ -1016,7 +1032,7 @@ static NvBool RemoveModesetPermissions(struct NvKmsModesetPermissions *pModeset, */ static void RevokePermissionsInternal( const NvU32 typeBitmask, - const NVDevEvoRec *pDevEvo, + NVDevEvoRec *pDevEvo, const struct NvKmsPerOpenDev *pOpenDevExclude) { struct NvKmsPerOpen *pOpen; @@ -1044,6 +1060,20 @@ static void RevokePermissionsInternal( continue; } + if (pOpenDev == pDevEvo->modesetSubOwner && + (typeBitmask & NVBIT(NV_KMS_PERMISSIONS_TYPE_SUB_OWNER))) { + FreeSwapGroups(pOpenDev); + pDevEvo->modesetSubOwner = NULL; + } + + /* + * Clients with sub-owner permission (or better) don't get flipping + * or modeset permission revoked. + */ + if (nvKmsOpenDevHasSubOwnerPermissionOrBetter(pOpenDev)) { + continue; + } + if (typeBitmask & NVBIT(NV_KMS_PERMISSIONS_TYPE_FLIPPING)) { nvkms_memset(&pOpenDev->flipPermissions, 0, sizeof(pOpenDev->flipPermissions)); @@ -1102,7 +1132,8 @@ static NvBool ReleaseModesetOwnership(struct NvKmsPerOpenDev *pOpenDev) RestoreConsole(pDevEvo); RevokePermissionsInternal(NVBIT(NV_KMS_PERMISSIONS_TYPE_FLIPPING) | - NVBIT(NV_KMS_PERMISSIONS_TYPE_MODESET), + NVBIT(NV_KMS_PERMISSIONS_TYPE_MODESET) | + NVBIT(NV_KMS_PERMISSIONS_TYPE_SUB_OWNER), pDevEvo, NULL /* pOpenDevExclude */); return TRUE; } @@ -1202,10 +1233,7 @@ struct NvKmsPerOpenDev *nvAllocPerOpenDev(struct NvKmsPerOpen *pOpen, pOpenDev->isPrivileged = isPrivileged; if (pOpenDev->isPrivileged) { - AssignFullNvKmsFlipPermissions(pDevEvo, - &pOpenDev->flipPermissions); - AssignFullNvKmsModesetPermissions(pOpenDev->pDevEvo, - &pOpenDev->modesetPermissions); + AssignFullNvKmsPermissions(pOpenDev); } if (!nvEvoInitApiHandles(&pOpenDev->deferredRequestFifoHandles, 4)) { @@ -1548,6 +1576,11 @@ static void FreeDeviceReference(struct NvKmsPerOpen *pOpen, ReleaseModesetOwnership(pOpenDev); nvAssert(pOpenDev->pDevEvo->modesetOwner != pOpenDev); + + // If this pOpenDev is the modeset sub-owner, implicitly release it. + if (pOpenDev->pDevEvo->modesetSubOwner == pOpenDev) { + pOpenDev->pDevEvo->modesetSubOwner = NULL; + } } nvFreePerOpenDev(pOpen, pOpenDev); @@ -2065,7 +2098,7 @@ static NvBool SetModePrepUser( for (disp = 0; disp < ARRAY_LEN(pReq->disp); disp++) { for (apiHead = 0; apiHead < ARRAY_LEN(pReq->disp[disp].head); apiHead++) { struct NvKmsSetLutCommonParams *pCommonLutParams = - &pReq->disp[disp].head[apiHead].lut; + &pReq->disp[disp].head[apiHead].flip.lut; if (!CopyInLutParams(pCommonLutParams)) { /* Remember how far we got through these loops before we @@ -2083,7 +2116,7 @@ static NvBool SetModePrepUser( for (disp = 0; disp < ARRAY_LEN(pReq->disp); disp++) { for (apiHead = 0; apiHead < ARRAY_LEN(pReq->disp[disp].head); apiHead++) { struct NvKmsSetLutCommonParams *pCommonLutParams = - &pReq->disp[disp].head[apiHead].lut; + &pReq->disp[disp].head[apiHead].flip.lut; if (disp > dispFailed || (disp == dispFailed && apiHead >= apiHeadFailed)) { @@ -2111,7 +2144,7 @@ static NvBool SetModeDoneUser( for (disp = 0; disp < ARRAY_LEN(pReq->disp); disp++) { for (apiHead = 0; apiHead < ARRAY_LEN(pReq->disp[disp].head); apiHead++) { struct NvKmsSetLutCommonParams *pCommonLutParams = - &pReq->disp[disp].head[apiHead].lut; + &pReq->disp[disp].head[apiHead].flip.lut; FreeCopiedInLutParams(pCommonLutParams); } @@ -2367,7 +2400,7 @@ static NvBool IdleBaseChannelAll( } /* Break out of the loop if we exceed the timeout. */ - if (nvExceedsTimeoutUSec(&startTime, timeout)) { + if (nvExceedsTimeoutUSec(pDevEvo, &startTime, timeout)) { break; } @@ -2396,9 +2429,9 @@ static NvBool IdleBaseChannel(struct NvKmsPerOpen *pOpen, return FALSE; } - /* Only the modesetOwner can idle base. */ + /* Only a modeset owner can idle base. */ - if (pOpenDev->pDevEvo->modesetOwner != pOpenDev) { + if (!nvKmsOpenDevHasSubOwnerPermissionOrBetter(pOpenDev)) { return FALSE; } @@ -2407,11 +2440,18 @@ static NvBool IdleBaseChannel(struct NvKmsPerOpen *pOpen, } +/* No extra user state needed for Flip; although we lose the user pointers + * for the LUT ramps after copying them in, that's okay because we don't need + * to copy them back out again. */ struct NvKmsFlipExtraUserState { // Nothing needed. }; +/*! + * Copy in any data referenced by pointer for the Flip request. Currently + * this is the flip head request array and the LUT ramps. + */ static NvBool FlipPrepUser( void *pParamsVoid, void *pExtraUserStateVoid) @@ -2421,6 +2461,7 @@ static NvBool FlipPrepUser( struct NvKmsFlipRequestOneHead *pFlipHeadKernel = NULL; NvU64 pFlipHeadUser = pRequest->pFlipHead; size_t size; + NvU32 apiHead, apiHeadFailed; int status; if (!nvKmsNvU64AddressIsSafe(pFlipHeadUser)) { @@ -2444,19 +2485,54 @@ static NvBool FlipPrepUser( return FALSE; } + /* Iterate over all of the common LUT ramp pointers embedded in the Flip + * request, and copy in each one. */ + for (apiHead = 0; apiHead < pRequest->numFlipHeads; apiHead++) { + struct NvKmsSetLutCommonParams *pCommonLutParams = + &pFlipHeadKernel[apiHead].flip.lut; + + if (!CopyInLutParams(pCommonLutParams)) { + /* Remember how far we got through this loop before we + * failed, so that we can undo everything up to this point. */ + apiHeadFailed = apiHead; + goto fail_lut; + } + } + pRequest->pFlipHead = nvKmsPointerToNvU64(pFlipHeadKernel); return TRUE; + +fail_lut: + for (apiHead = 0; apiHead < apiHeadFailed; apiHead++) { + struct NvKmsSetLutCommonParams *pCommonLutParams = + &pFlipHeadKernel[apiHead].flip.lut; + + FreeCopiedInLutParams(pCommonLutParams); + } + nvFree(pFlipHeadKernel); + return FALSE; } +/*! + * Free buffers allocated in FlipPrepUser. + */ static NvBool FlipDoneUser( void *pParamsVoid, void *pExtraUserStateVoid) { struct NvKmsFlipParams *pParams = pParamsVoid; struct NvKmsFlipRequest *pRequest = &pParams->request; + struct NvKmsFlipRequestOneHead *pFlipHead = nvKmsNvU64ToPointer(pRequest->pFlipHead); + NvU32 apiHead; + + for (apiHead = 0; apiHead < pRequest->numFlipHeads; apiHead++) { + struct NvKmsSetLutCommonParams *pCommonLutParams = + &pFlipHead[apiHead].flip.lut; - nvFree(nvKmsNvU64ToPointer(pRequest->pFlipHead)); + FreeCopiedInLutParams(pCommonLutParams); + } + nvFree(pFlipHead); /* The request is not copied back out to userspace (only the reply is), so * we don't need to worry about restoring the user pointer */ pRequest->pFlipHead = 0; @@ -2614,9 +2690,9 @@ static NvBool GrantSurface(struct NvKmsPerOpen *pOpen, void *pParamsVoid) } pSurfaceEvo = - nvEvoGetSurfaceFromHandleNoCtxDmaOk(pOpenDev->pDevEvo, - &pOpenDev->surfaceHandles, - pParams->request.surfaceHandle); + nvEvoGetSurfaceFromHandleNoDispHWAccessOk(pOpenDev->pDevEvo, + &pOpenDev->surfaceHandles, + pParams->request.surfaceHandle); if (pSurfaceEvo == NULL) { return FALSE; } @@ -2743,7 +2819,7 @@ static NvBool GrantSwapGroup(struct NvKmsPerOpen *pOpen, void *pParamsVoid) return FALSE; } - if (pOpenDev->pDevEvo->modesetOwner != pOpenDev) { + if (!nvKmsOpenDevHasSubOwnerPermissionOrBetter(pOpenDev)) { return FALSE; } @@ -3243,14 +3319,15 @@ static NvBool GrantPermissions(struct NvKmsPerOpen *pOpen, void *pParamsVoid) return FALSE; } - /* Only the modesetOwner can grant permissions. */ + /* Only a modeset owner can grant permissions. */ - if (pOpenDev->pDevEvo->modesetOwner != pOpenDev) { + if (!nvKmsOpenDevHasSubOwnerPermissionOrBetter(pOpenDev)) { return FALSE; } if (!ValidateNvKmsPermissions(pOpenDev->pDevEvo, - &pParams->request.permissions)) { + &pParams->request.permissions, + pOpen->clientType)) { return FALSE; } @@ -3328,6 +3405,16 @@ static NvBool AcquirePermissions(struct NvKmsPerOpen *pOpen, void *pParamsVoid) pParams->reply.permissions.modeset = pOpenDev->modesetPermissions; + } else if (type == NV_KMS_PERMISSIONS_TYPE_SUB_OWNER) { + + if (pOpenDev->pDevEvo->modesetSubOwner != NULL) { + /* There can be only one sub-owner */ + return FALSE; + } + + pOpenDev->pDevEvo->modesetSubOwner = pOpenDev; + AssignFullNvKmsPermissions(pOpenDev); + } else { /* * GrantPermissions() should ensure that @@ -3423,6 +3510,16 @@ static NvBool RevokePermissionsSet( return TRUE; } +static NvBool IsHeadRevoked(const NVDispEvoRec *pDispEvo, + const NvU32 apiHead, + void *pData) +{ + const struct NvKmsPermissions *pPermissions = pData; + + return !nvDpyIdListIsEmpty( + pPermissions->modeset.disp[pDispEvo->displayOwner].head[apiHead].dpyIdList); +} + static NvBool RevokePermissions(struct NvKmsPerOpen *pOpen, void *pParamsVoid) { struct NvKmsRevokePermissionsParams *pParams = pParamsVoid; @@ -3430,20 +3527,44 @@ static NvBool RevokePermissions(struct NvKmsPerOpen *pOpen, void *pParamsVoid) GetPerOpenDev(pOpen, pParams->request.deviceHandle); const NvU32 validBitmask = NVBIT(NV_KMS_PERMISSIONS_TYPE_FLIPPING) | - NVBIT(NV_KMS_PERMISSIONS_TYPE_MODESET); + NVBIT(NV_KMS_PERMISSIONS_TYPE_MODESET) | + NVBIT(NV_KMS_PERMISSIONS_TYPE_SUB_OWNER); if (pOpenDev == NULL) { return FALSE; } - /* Only the modeset owner can revoke permissions. */ - if (pOpenDev->pDevEvo->modesetOwner != pOpenDev) { + /* Reject invalid bitmasks. */ + + if ((pParams->request.permissionsTypeBitmask & ~validBitmask) != 0) { return FALSE; } - /* Reject invalid bitmasks. */ + if ((pParams->request.permissionsTypeBitmask & NVBIT(NV_KMS_PERMISSIONS_TYPE_SUB_OWNER)) != 0) { + if (pOpenDev->pDevEvo->modesetOwner != pOpenDev) { + /* Only the modeset owner can revoke sub-owner permissions. */ + return FALSE; + } - if ((pParams->request.permissionsTypeBitmask & ~validBitmask) != 0) { + /* + * When revoking ownership permissions, shut down all heads. + * + * This is necessary to keep the state of nvidia-drm in sync with NVKMS. + * Otherwise, an NVKMS client can leave heads enabled when handing off + * control of the device back to nvidia-drm, and nvidia-drm's flip queue + * handling will get out of sync because it thinks all heads are + * disabled and does not expect flip events on those heads. + */ + nvShutDownApiHeads(pOpenDev->pDevEvo, pOpenDev, NULL /* pTestFunc */, + NULL /* pData */, + TRUE /* doRasterLock */); + } + + /* + * Only a client with sub-owner permissions (or better) can revoke other + * kinds of permissions. + */ + if (!nvKmsOpenDevHasSubOwnerPermissionOrBetter(pOpenDev)) { return FALSE; } @@ -3456,7 +3577,23 @@ static NvBool RevokePermissions(struct NvKmsPerOpen *pOpen, void *pParamsVoid) pOpenDev /* pOpenDevExclude */); } else { /* If not using bitmask, revoke using the set. */ - return RevokePermissionsSet(pOpenDev, &pParams->request.permissions); + if (!RevokePermissionsSet(pOpenDev, &pParams->request.permissions)) { + return FALSE; + } + + /* + * When revoking ownership permissions, shut down those heads. + * + * This is necessary to keep the state of nvidia-drm in sync with NVKMS. + * Otherwise, an NVKMS client can leave heads enabled when handing off + * control of the device back to nvidia-drm, which prevents them from + * being able to be leased again. + */ + if (pParams->request.permissions.type == NV_KMS_PERMISSIONS_TYPE_MODESET) { + nvShutDownApiHeads(pOpenDev->pDevEvo, pOpenDev, IsHeadRevoked, + &pParams->request.permissions, + TRUE /* doRasterLock */); + } } return TRUE; @@ -3477,7 +3614,7 @@ static NvBool RegisterDeferredRequestFifo(struct NvKmsPerOpen *pOpen, return FALSE; } - pSurfaceEvo = nvEvoGetSurfaceFromHandleNoCtxDmaOk( + pSurfaceEvo = nvEvoGetSurfaceFromHandleNoDispHWAccessOk( pOpenDev->pDevEvo, &pOpenDev->surfaceHandles, pParams->request.surfaceHandle); @@ -3499,7 +3636,7 @@ static NvBool RegisterDeferredRequestFifo(struct NvKmsPerOpen *pOpen, * noDisplayHardwareAccess==TRUE, then skip the idle in * nvEvoDecrementSurfaceRefCnts() for these surfaces. */ - if (pSurfaceEvo->requireCtxDma) { + if (pSurfaceEvo->requireDisplayHardwareAccess) { return FALSE; } @@ -3573,8 +3710,8 @@ static NvBool QueryDpyCRC32(struct NvKmsPerOpen *pOpen, return FALSE; } - if (pOpenDev->pDevEvo->modesetOwner != pOpenDev) { - // Only the current owner can query CRC32 values. + if (!nvKmsOpenDevHasSubOwnerPermissionOrBetter(pOpenDev)) { + // Only a current owner can query CRC32 values. return FALSE; } @@ -3623,7 +3760,7 @@ static NvBool AllocSwapGroup( return FALSE; } - if (pOpenDev->pDevEvo->modesetOwner != pOpenDev) { + if (!nvKmsOpenDevHasSubOwnerPermissionOrBetter(pOpenDev)) { return FALSE; } @@ -3660,7 +3797,7 @@ static NvBool FreeSwapGroup( return FALSE; } - if (pOpenDev->pDevEvo->modesetOwner != pOpenDev) { + if (!nvKmsOpenDevHasSubOwnerPermissionOrBetter(pOpenDev)) { return FALSE; } @@ -3930,7 +4067,7 @@ static NvBool SetSwapGroupClipList( return FALSE; } - if (pOpenDev->pDevEvo->modesetOwner != pOpenDev) { + if (!nvKmsOpenDevHasSubOwnerPermissionOrBetter(pOpenDev)) { return FALSE; } @@ -4003,15 +4140,13 @@ static NvBool SwitchMux( struct NvKmsSwitchMuxParams *pParams = pParamsVoid; const struct NvKmsSwitchMuxRequest *r = &pParams->request; NVDpyEvoPtr pDpyEvo; - NVDevEvoPtr pDevEvo; pDpyEvo = GetPerOpenDpy(pOpen, r->deviceHandle, r->dispHandle, r->dpyId); if (pDpyEvo == NULL) { return FALSE; } - pDevEvo = pDpyEvo->pDispEvo->pDevEvo; - if (pDevEvo->modesetOwner != GetPerOpenDev(pOpen, r->deviceHandle)) { + if (!nvKmsOpenDevHasSubOwnerPermissionOrBetter(GetPerOpenDev(pOpen, r->deviceHandle))) { return FALSE; } @@ -4074,7 +4209,7 @@ static void EnableAndSetupVblankSyncObject(NVDispEvoRec *pDispEvo, * code path failes to re-allocate that sync object. */ if (nvApiHeadIsActive(pDispEvo, apiHead) && - (pVblankSyncObject->evoSyncpt.hCtxDma != 0)) { + (pVblankSyncObject->evoSyncpt.surfaceDesc.ctxDmaHandle != 0)) { NvU32 head = nvGetPrimaryHwHead(pDispEvo, apiHead); nvAssert(head != NV_INVALID_HEAD); @@ -4084,7 +4219,7 @@ static void EnableAndSetupVblankSyncObject(NVDispEvoRec *pDispEvo, pDispEvo->headState[head].timings.rasterBlankStart.y, head, pVblankSyncObject->index, - pVblankSyncObject->evoSyncpt.hCtxDma, + &pVblankSyncObject->evoSyncpt.surfaceDesc, pUpdateState); pVblankSyncObject->enabled = TRUE; @@ -4251,7 +4386,7 @@ static void DisableAndCleanVblankSyncObject(NVDispEvoRec *pDispEvo, 0, /* rasterLine */ head, pVblankSyncObject->index, - 0, /* hCtxDma */ + NULL, /* pSurfaceDesc */ pUpdateState); /* * Note: it is the caller's responsibility to call @@ -4442,6 +4577,96 @@ static NvBool NotifyVblank( return NV_TRUE; } +static NvBool SetFlipLockGroup( + struct NvKmsPerOpen *pOpen, + void *pParamsVoid) +{ + struct NvKmsSetFlipLockGroupParams *pParams = pParamsVoid; + const struct NvKmsSetFlipLockGroupRequest *pRequest = &pParams->request; + /* Fill in this array as we look up the pDevEvo from the given device + * handles, so that later processing can use it without converting + * deviceHandle -> pDevEvo again. */ + NVDevEvoPtr pDevEvo[NV_MAX_SUBDEVICES] = { }; + NvU32 dev; + + /* Ensure we don't overrun the pDevEvo array. */ + ct_assert(ARRAY_LEN(pRequest->dev) == NV_MAX_SUBDEVICES); + + for (dev = 0; dev < ARRAY_LEN(pRequest->dev); dev++) { + const struct NvKmsSetFlipLockGroupOneDev *pRequestDev = + &pRequest->dev[dev]; + struct NvKmsPerOpenDev *pOpenDev = NULL; + NVDispEvoPtr pDispEvo; + NvU32 dispIndex; + NvU32 i; + + if (pRequestDev->requestedDispsBitMask == 0) { + break; + } + + pOpenDev = GetPerOpenDev(pOpen, pRequestDev->deviceHandle); + + if (pOpenDev == NULL) { + return FALSE; + } + + pDevEvo[dev] = pOpenDev->pDevEvo; + + /* The caller must be the modeset owner for every specified device. */ + if (!nvKmsOpenDevHasSubOwnerPermissionOrBetter(pOpenDev)) { + return FALSE; + } + + /* Do not allow the same device to be specified twice. */ + for (i = 0; i < dev; i++) { + if (pDevEvo[i] == pDevEvo[dev]) { + return FALSE; + } + } + + /* Check for invalid disps in requestedDispsBitMask. */ + if (nvHasBitAboveMax(pRequestDev->requestedDispsBitMask, + pDevEvo[dev]->nDispEvo)) { + return FALSE; + } + + /* Check for invalid heads in requestedHeadsBitMask. */ + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo[dev]) { + const NvU32 requestedHeadsBitMask = + pRequestDev->disp[dispIndex].requestedHeadsBitMask; + NvU32 apiHead; + + if (requestedHeadsBitMask == 0) { + return FALSE; + } + if (nvHasBitAboveMax(requestedHeadsBitMask, + pDevEvo[dev]->numHeads)) { + return FALSE; + } + + /* + * Verify that all API heads in requestedHeadsBitMask are active. + * The requested fliplock group will be implicitly disabled if any of + * these heads are specified in a modeset. + */ + for (apiHead = 0; apiHead < pDevEvo[dev]->numHeads; apiHead++) { + if ((requestedHeadsBitMask & (1 << apiHead)) != 0) { + if (!nvApiHeadIsActive(pDispEvo, apiHead)) { + return FALSE; + } + } + } + } + } + + /* Verify that at least one device was specified */ + if (pDevEvo[0] == NULL) { + return FALSE; + } + + return nvSetFlipLockGroup(pDevEvo, pRequest); +} + /*! * Perform the ioctl operation requested by the client. * @@ -4563,6 +4788,7 @@ NvBool nvKmsIoctl( ENTRY(NVKMS_IOCTL_ENABLE_VBLANK_SYNC_OBJECT, EnableVblankSyncObject), ENTRY(NVKMS_IOCTL_DISABLE_VBLANK_SYNC_OBJECT, DisableVblankSyncObject), ENTRY(NVKMS_IOCTL_NOTIFY_VBLANK, NotifyVblank), + ENTRY(NVKMS_IOCTL_SET_FLIPLOCK_GROUP, SetFlipLockGroup), }; struct NvKmsPerOpen *pOpen = pOpenVoid; @@ -4792,6 +5018,7 @@ static const char *ProcFsPermissionsTypeString( switch (permissionsType) { case NV_KMS_PERMISSIONS_TYPE_FLIPPING: return "flipping"; case NV_KMS_PERMISSIONS_TYPE_MODESET: return "modeset"; + case NV_KMS_PERMISSIONS_TYPE_SUB_OWNER:return "sub-owner"; } return "unknown"; @@ -4960,7 +5187,7 @@ static void PrintSurfacePlanes( "plane[%u] disp ctxDma:0x%08x pitch:%u offset:%" NvU64_fmtu " rmObjectSizeInBytes:%" NvU64_fmtu, planeIndex, - pSurfaceEvo->planes[planeIndex].ctxDma, + pSurfaceEvo->planes[planeIndex].surfaceDesc.ctxDmaHandle, pSurfaceEvo->planes[planeIndex].pitch, pSurfaceEvo->planes[planeIndex].offset, pSurfaceEvo->planes[planeIndex].rmObjectSizeInBytes); @@ -5425,6 +5652,116 @@ ProcFsPrintDpyCrcs( } } +static const char * +SignalFormatString(NvKmsConnectorSignalFormat signalFormat) +{ + switch (signalFormat) { + case NVKMS_CONNECTOR_SIGNAL_FORMAT_VGA: return "VGA"; + case NVKMS_CONNECTOR_SIGNAL_FORMAT_LVDS: return "LVDS"; + case NVKMS_CONNECTOR_SIGNAL_FORMAT_TMDS: return "TMDS"; + case NVKMS_CONNECTOR_SIGNAL_FORMAT_DP: return "DP"; + case NVKMS_CONNECTOR_SIGNAL_FORMAT_DSI: return "DSI"; + case NVKMS_CONNECTOR_SIGNAL_FORMAT_UNKNOWN: break; + } + + return "unknown"; +} + +static const char * +PixelDepthString(enum nvKmsPixelDepth pixelDepth) +{ + switch (pixelDepth) { + case NVKMS_PIXEL_DEPTH_18_444: return "18bpp 4:4:4"; + case NVKMS_PIXEL_DEPTH_24_444: return "24bpp 4:4:4"; + case NVKMS_PIXEL_DEPTH_30_444: return "30bpp 4:4:4"; + case NVKMS_PIXEL_DEPTH_20_422: return "20bpp 4:2:2"; + case NVKMS_PIXEL_DEPTH_16_422: return "16bpp 4:2:2"; + } + + return "unknown"; +} + +static void +ProcFsPrintHeads( + void *data, + char *buffer, + size_t size, + nvkms_procfs_out_string_func_t *outString) +{ + NVDevEvoPtr pDevEvo; + NVDispEvoPtr pDispEvo; + NvU32 dispIndex, head; + NVEvoInfoStringRec infoString; + + FOR_ALL_EVO_DEVS(pDevEvo) { + + nvInitInfoString(&infoString, buffer, size); + nvEvoLogInfoString(&infoString, + "pDevEvo (deviceId:%02d) : %p", + pDevEvo->deviceId, pDevEvo); + outString(data, buffer); + + FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + + nvInitInfoString(&infoString, buffer, size); + nvEvoLogInfoString(&infoString, + " pDispEvo (dispIndex:%02d) : %p", + dispIndex, pDispEvo); + outString(data, buffer); + + if (pDevEvo->coreInitMethodsPending) { + /* If the core channel has been allocated but no mode has yet + * been set, pConnectorEvo will be non-NULL for heads being + * driven by the console, but data like the mode timings will + * be bogus. */ + nvInitInfoString(&infoString, buffer, size); + nvEvoLogInfoString(&infoString, " (not yet initialized)"); + outString(data, buffer); + continue; + } + + for (head = 0; head < pDevEvo->numHeads; head++) { + const NVDispHeadStateEvoRec *pHeadState = + &pDispEvo->headState[head]; + const NVConnectorEvoRec *pConnectorEvo = + pHeadState->pConnectorEvo; + const NVHwModeTimingsEvo *pHwModeTimings = + &pHeadState->timings; + + nvInitInfoString(&infoString, buffer, size); + if (pConnectorEvo == NULL) { + nvEvoLogInfoString(&infoString, + " head %d : inactive", + head); + } else { + const NvU32 refreshRate10kHz = + nvGetRefreshRate10kHz(pHwModeTimings); + + nvEvoLogInfoString(&infoString, + " head %d : %s", + head, pConnectorEvo->name); + + nvEvoLogInfoString(&infoString, + " protocol : %s", + SignalFormatString(pConnectorEvo->signalFormat)); + + nvEvoLogInfoString(&infoString, + " mode : %u x %u @ %u.%04u Hz", + nvEvoVisibleWidth(pHwModeTimings), + nvEvoVisibleHeight(pHwModeTimings), + refreshRate10kHz / 10000, + refreshRate10kHz % 10000); + + nvEvoLogInfoString(&infoString, + " depth : %s", + PixelDepthString(pHeadState->pixelDepth)); + } + outString(data, buffer); + } + } + } +} + #endif /* NVKMS_PROCFS_ENABLE */ void nvKmsGetProcFiles(const nvkms_procfs_file_t **ppProcFiles) @@ -5436,6 +5773,7 @@ void nvKmsGetProcFiles(const nvkms_procfs_file_t **ppProcFiles) { "headsurface", ProcFsPrintHeadSurface }, { "deferred-request-fifos", ProcFsPrintDeferredRequestFifos }, { "crcs", ProcFsPrintDpyCrcs }, + { "heads", ProcFsPrintHeads }, { NULL, NULL }, }; @@ -5447,7 +5785,7 @@ void nvKmsGetProcFiles(const nvkms_procfs_file_t **ppProcFiles) static void FreeGlobalState(void) { - nvInvalidateTopologiesEvo(); + nvInvalidateRasterLockGroupsEvo(); nvKmsClose(nvEvoGlobal.nvKmsPerOpen); nvEvoGlobal.nvKmsPerOpen = NULL; @@ -5805,8 +6143,8 @@ static void AllocSurfaceCtxDmasForAllOpens(NVDevEvoRec *pDevEvo) continue; } - if (!pSurfaceEvo->requireCtxDma) { - nvAssert(pSurfaceEvo->planes[0].ctxDma == 0); + if (!pSurfaceEvo->requireDisplayHardwareAccess) { + nvAssert(pSurfaceEvo->planes[0].surfaceDesc.ctxDmaHandle == 0); continue; } @@ -5817,16 +6155,16 @@ static void AllocSurfaceCtxDmasForAllOpens(NVDevEvoRec *pDevEvo) nvAssert(pSurfaceEvo->rmRefCnt > 0); FOR_ALL_VALID_PLANES(planeIndex, pSurfaceEvo) { - - pSurfaceEvo->planes[planeIndex].ctxDma = - nvRmEvoAllocateAndBindDispContextDMA( - pDevEvo, - pSurfaceEvo->planes[planeIndex].rmHandle, - pSurfaceEvo->layout, - pSurfaceEvo->planes[planeIndex].rmObjectSizeInBytes - 1); - if (!pSurfaceEvo->planes[planeIndex].ctxDma) { + NvU32 ret = + nvRmAllocAndBindSurfaceDescriptor( + pDevEvo, + pSurfaceEvo->planes[planeIndex].rmHandle, + pSurfaceEvo->layout, + pSurfaceEvo->planes[planeIndex].rmObjectSizeInBytes - 1, + &pSurfaceEvo->planes[planeIndex].surfaceDesc); + if (ret != NVOS_STATUS_SUCCESS) { FreeSurfaceCtxDmasForAllOpens(pDevEvo); - nvAssert(!"Failed to re-allocate surface ctx dma"); + nvAssert(!"Failed to re-allocate surface descriptor"); return; } } @@ -5864,15 +6202,16 @@ static void FreeSurfaceCtxDmasForAllOpens(NVDevEvoRec *pDevEvo) */ nvAssert(pSurfaceEvo->rmRefCnt > 0); - if (!pSurfaceEvo->requireCtxDma) { - nvAssert(pSurfaceEvo->planes[0].ctxDma == 0); + if (!pSurfaceEvo->requireDisplayHardwareAccess) { + nvAssert(pSurfaceEvo->planes[0].surfaceDesc.ctxDmaHandle == 0); continue; } FOR_ALL_VALID_PLANES(planeIndex, pSurfaceEvo) { - nvRmEvoFreeDispContextDMA( + pDevEvo->hal->FreeSurfaceDescriptor( pDevEvo, - &pSurfaceEvo->planes[planeIndex].ctxDma); + nvEvoGlobal.clientHandle, + &pSurfaceEvo->planes[planeIndex].surfaceDesc); } } } @@ -5917,13 +6256,6 @@ NvBool nvSurfaceEvoInAnyOpens(const NVSurfaceEvoRec *pSurfaceEvo) } #endif -NVDevEvoPtr nvGetDevEvoFromOpenDev( - const struct NvKmsPerOpenDev *pOpenDev) -{ - nvAssert(pOpenDev != NULL); - return pOpenDev->pDevEvo; -} - const struct NvKmsFlipPermissions *nvGetFlipPermissionsFromOpenDev( const struct NvKmsPerOpenDev *pOpenDev) { @@ -5987,8 +6319,10 @@ void nvKmsSuspend(NvU32 gpuId) * that becomes stale after suspend. Shutting the heads down here * clears the relevant state explicitly. */ - nvShutDownApiHeads(pDevEvo, - NULL /* pTestFunc, shut down all heads */); + nvShutDownApiHeads(pDevEvo, pDevEvo->pNvKmsOpenDev, + NULL /* pTestFunc, shut down all heads */, + NULL /* pData */, + TRUE /* doRasterLock */); pDevEvo->skipConsoleRestore = TRUE; DisableAndCleanVblankSyncObjectForAllOpens(pDevEvo); @@ -6148,3 +6482,10 @@ NvBool nvKmsSetBacklight(NvU32 display_id, void *drv_priv, NvU32 brightness) return status == NV_OK; } + +NvBool nvKmsOpenDevHasSubOwnerPermissionOrBetter(const struct NvKmsPerOpenDev *pOpenDev) +{ + return pOpenDev->isPrivileged || + pOpenDev->pDevEvo->modesetOwner == pOpenDev || + pOpenDev->pDevEvo->modesetSubOwner == pOpenDev; +} diff --git a/src/nvidia-modeset/src/shaders/g_ampere_shader_info.h b/src/nvidia-modeset/src/shaders/g_ampere_shader_info.h index d080790688..977d0a974e 100644 --- a/src/nvidia-modeset/src/shaders/g_ampere_shader_info.h +++ b/src/nvidia-modeset/src/shaders/g_ampere_shader_info.h @@ -1,4 +1,4 @@ -// Generated using 'Offline GLSL Shader Compiler Version 13.0.0.0.530.00.dev/gpu_drv/dev_a-15624' +// Generated using 'Offline GLSL Shader Compiler Version 13.0.0.0.545.00.dev/gpu_drv/dev_a-16109' // WARNING: This file is auto-generated! Do not hand-edit! // Instead, edit the GLSL shaders and run 'unix-build nvmake @generate'. diff --git a/src/nvidia-modeset/src/shaders/g_hopper_shader_info.h b/src/nvidia-modeset/src/shaders/g_hopper_shader_info.h index d96cf356c2..6fa72c0905 100644 --- a/src/nvidia-modeset/src/shaders/g_hopper_shader_info.h +++ b/src/nvidia-modeset/src/shaders/g_hopper_shader_info.h @@ -1,4 +1,4 @@ -// Generated using 'Offline GLSL Shader Compiler Version 13.0.0.0.530.00.dev/gpu_drv/dev_a-15624' +// Generated using 'Offline GLSL Shader Compiler Version 13.0.0.0.545.00.dev/gpu_drv/dev_a-16109' // WARNING: This file is auto-generated! Do not hand-edit! // Instead, edit the GLSL shaders and run 'unix-build nvmake @generate'. diff --git a/src/nvidia-modeset/src/shaders/g_hopper_shaders b/src/nvidia-modeset/src/shaders/g_hopper_shaders index 449ddc9e2bb5f52043979e5f5319188bb7b0f794..82bff01539da5045faa095afbe4b434bbd79d402 100644 GIT binary patch delta 5972 zcmds5Z)jWB6~BL;^dvn!JxP{i{j>C*UhM2|6t6Xuti*|#$5^0d8~qw*ChSY8<2-3z z>N3k@j4`(2F_At7W7!fY?8{oJ(#KM0v=T}-(zK&r#-Pp+hV8>>81&27Ks)EWrzhEL zY%tai3k*K*+;i_e=lss^o_lvbNbP)(dg-m=+FFX)&dgMXF_vPSvHNuvYh_s(WR`}% z2I_0+BK*rq-voW0RYrQUuV$+t>!=^pVZ4<$Ku)5(-|RI@>-yS_6f+&h@@U7-!a6ul z;lMnmV+geK^(&xHvKbU{A7o!BOrebSgC@+EN#edqzPHjF&h4d_V4Uq_vkCZ`5BFPO zIUI)b(0=ul0{dlqj%44r58?*~4@%z||2+N}A z&)#h=*TlVMcV+nm-|uZN4{KkgB?}RBU7;m0#8C)OVAQ}Zm(nQ^)o{yk2xp)t`{^jU zBvHR#XBRr@QbA!S6Gkn`?sWGqn!MQ?UaSRi<|2;9VVou87Jh;Mn1?WK_tAf4ycl^X z#vW3f^GcXEh;zp|ukp3s-Zwk>4+B28yB`jGc7JvvvqZ7ZWhRmb+RXk=M zB7rgU=!{PK;AFR*X$^amfO()z5Y#3xY7^Z1bpd^X_pmNfL8DMGLgJv4>@X4K^JAhy zB9e!QD5r-+MMNZJNK8OPtDhF%O2$<-ge~1=Dfg)}yy5Dn#KJ!zr>~q6=eXfsKPB48 zQTfk`-&KxaNFH1i+eBHH#coi zl^5jA>X8b^?N#|pohRI9o|YfyntStU`E5AvYYXi<9t~{B znfuzhTr%z$OgOU?MYx?a_wVcSYn>S|X16i3__$zZH6^^f4vd7EO+_bU&?h4yEe(vA znJualGU)XRLdQ-at8;njOhYAa^Q}WF0>U9Kd0KTC_tM4Jx{c zvf@u*X3L3ifxDvPb_c2MIg~i=8H*>R5;>c+7zv78*1RleQ$8+A;(7!AR6t z`59RBxA2EQNTTInQx$j)vh4^~2NgA15UJ%Y5VXFZ7m(3@=N+g?q0J)OoMxtBk@6KhqCe}V%*lK zMlhV8ci-QXbNnSY{|&j?IWvj^MKPZO9QbB5P0D~*u5cRL$>)*N>ERG+cXcS5}r z&jDaV*>>cV0tUkU(f8!>j^*TZD9j19V&HR8)t^2FFR;)?Ggb>^wMD>#z*tncmJ?4w zRwwMKDgdJX_8@R77GTu5BREXkvbH8Yae+d{kA%>~jljdxA;(n3UA@>E#6X8Tm)^^RS~ zai}FyN-1eDRBYy@bg2V*%!Vk5NCH`PS;}^4(uKT~K)kImv=61*Lf#5h&pC6E?DU~f zniLBRK03et%Xhx>{pUa3kJH_c)33f~tgfe7d?Uxo3_cn7+fTEGGdGikf76UJ_Pz=J z0;>f6I{IrF18k1|Q4{QHt_rqBb{lNFpo5)4`_Sw+OKaNdtGG^aGS4W@EQhfI&dV;q zI!*AW*c_U;k5%;R0_P$Bs10_pI1}1?U}safPx9Ys_QwkcnI(UnJbsPyz&Z^lmrKIG z1>6sudw~NN2A3Cjke}Kl|3;{DQj$1?`KdDeJ*~fr{yZo05Lr+M z3mOvABM;_hQ6)m6|4wso|3UsiDr>VyIHn0>g!{pHJ`}bXT)n{mTsa8`z5G4?*Azx> zo1Z8t8t6agpS2db*WczKMuUU5d1v+n3D98g5B#%Mpa9!njQOGf{vL3#H|LcJs+YAB z<>3;tI2tOC#^@#wubvW##6)>!RjfsP<$*FmP?^A}OmN>f1=I*M~NL^B>|X zHSc0kyk}r2ddUbrUnZg#pQsQqL`r&&A|r?)B?YPKi6A~d^Kn!udY&GdgKH%jaQ?X5 zRdr03$-C%y-Bqa^mAkS=?_{dOQ0_|VwA?M8mNhL49ADT-lE(eU)3~*Vl{8}WGpphQ8 za^={R4gPcmDdv^UI$NnIsYZmI8}pjNZlWDE<^y{P>`o=3S@?wr2E@vz0viWZDrp;S z#q(RaIW=71Hu}}Mdf>sbYF?ff#>+4d>o=t-z z>0kTc*mrl=?kV@S6}@*iTV z7$v*~s0}gF6?;>Gtp$+l;4hbu@ev9E&L34F^}7E27cy4vl$eSEU_L+9O3+1X2OcuX zA!B(9Vu%w~N~q?f{$RW7S7dFK15|82jKz`!s1ya>$LHpJsBEWNg_(kdA(ob$j_t~` zQB16JwQ#(uQtOB#cVL~r0bKe@MOs=Az*`Zw?a0NB$%Hdc=?V=X?DW89igg->ab3c= zSiV33{HsqeM7?_ib*#9;%>gL-6j4DZa*YWw4-o``arde;8+HdM9$|882fXUgN6meF zL#}hvy}lurdDGQ5<*$+tZ=M>%7)Y1Fhnup+Q*emc;1KTfTk@29eoIJkD7tsU^jhftAN5C!B~!Jw{_A41zn>(CkN%t>@+G4zy4c z*#D_{dyB*HBBXveyx~Y)0Y4S;a9G>PYmjH5Kej<00L%7!Pzudg4d>I+5chC=!=d~D z+QHsOdI!)?#PDv*cwZ>cpg zw?;3MFj`rU(xI&>A-K1482(xWf8ZmaxOaal^IyOrz8Jxhb;znfj7<1Nq=M|Mc~dHG z<^@?dlsKHoixJ^eF}$|N;A=0)@5e1Th#_&EkOkZLb2jt>W4iaQO8YT9J?fz0@3yrA oC2Io4AQx%cj6$dN(NMSXpY9@C`MY! unverified, 0xa0a0a0a0a0a0a0a0 -> verified @@ -220,4 +223,7 @@ typedef struct #define GSP_FW_HEAP_FREE_LIST_MAGIC 0x4845415046524545ULL +#define GSP_FW_FLAGS 8:0 +#define GSP_FW_FLAGS_CLOCK_BOOST NVBIT(0) + #endif // GSP_FW_WPR_META_H_ diff --git a/src/nvidia/arch/nvalloc/common/inc/inforom/ifrecc.h b/src/nvidia/arch/nvalloc/common/inc/inforom/ifrecc.h index 337537d794..ef2f97024e 100644 --- a/src/nvidia/arch/nvalloc/common/inc/inforom/ifrecc.h +++ b/src/nvidia/arch/nvalloc/common/inc/inforom/ifrecc.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/nvidia/arch/nvalloc/common/inc/inforom/ifrstruct.h b/src/nvidia/arch/nvalloc/common/inc/inforom/ifrstruct.h index f8d90fc8d5..e56b10d795 100644 --- a/src/nvidia/arch/nvalloc/common/inc/inforom/ifrstruct.h +++ b/src/nvidia/arch/nvalloc/common/inc/inforom/ifrstruct.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/nvidia/arch/nvalloc/common/inc/oob/smbpbi.h b/src/nvidia/arch/nvalloc/common/inc/oob/smbpbi.h index f26c717e7b..28f6ef5f1e 100644 --- a/src/nvidia/arch/nvalloc/common/inc/oob/smbpbi.h +++ b/src/nvidia/arch/nvalloc/common/inc/oob/smbpbi.h @@ -135,8 +135,10 @@ #define NV_MSGBOX_CMD_ARG1_PCIE_SPEED_V1 0x00000012 #define NV_MSGBOX_CMD_ARG1_PCIE_WIDTH_V1 0x00000013 #define NV_MSGBOX_CMD_ARG1_TGP_LIMIT_V1 0x00000014 +#define NV_MSGBOX_CMD_ARG1_FRU_PART_NUMBER_V1 0x00000015 #define NV_MSGBOX_CMD_ARG1_MODULE_POWER_LIMIT_V1 0x00000016 -#define NV_MSGBOX_CMD_ARG1_SYS_ID_DATA_TYPE_MAX 0x00000016 /* Adjust, when adding new types */ +#define NV_MSGBOX_CMD_ARG1_MAX_DRAM_CAPACITY_V1 0x00000017 +#define NV_MSGBOX_CMD_ARG1_SYS_ID_DATA_TYPE_MAX 0x00000017 /* Adjust, when adding new types */ #define NV_MSGBOX_CMD_ARG1_REGISTER_ACCESS_WRITE 0x00000000 #define NV_MSGBOX_CMD_ARG1_REGISTER_ACCESS_READ 0x00000001 #define NV_MSGBOX_CMD_ARG1_THERM_PARAM_TEMP_TARGET 0x00000000 @@ -772,9 +774,9 @@ #define NV_MSGBOX_DATA_CAP_1_INFOROM_VER_V1 14:14 #define NV_MSGBOX_DATA_CAP_1_INFOROM_VER_V1_NOT_AVAILABLE 0x00000000 #define NV_MSGBOX_DATA_CAP_1_INFOROM_VER_V1_AVAILABLE 0x00000001 -#define NV_MSGBOX_DATA_CAP_1_MODULE_LIMIT_V1 15:15 -#define NV_MSGBOX_DATA_CAP_1_MODULE_LIMIT_V1_NOT_AVAILABLE 0x00000000 -#define NV_MSGBOX_DATA_CAP_1_MODULE_LIMIT_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_MODULE_POWER_LIMIT_V1 15:15 +#define NV_MSGBOX_DATA_CAP_1_MODULE_POWER_LIMIT_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_MODULE_POWER_LIMIT_V1_AVAILABLE 0x00000001 #define NV_MSGBOX_DATA_CAP_1_ECC_V1 16:16 #define NV_MSGBOX_DATA_CAP_1_ECC_V1_NOT_AVAILABLE 0x00000000 #define NV_MSGBOX_DATA_CAP_1_ECC_V1_AVAILABLE 0x00000001 @@ -902,6 +904,9 @@ #define NV_MSGBOX_DATA_CAP_2_NVLINK_INFO_AVAILABILITY 27:27 #define NV_MSGBOX_DATA_CAP_2_NVLINK_INFO_AVAILABILITY_NOT_AVAILABLE 0x00000000 #define NV_MSGBOX_DATA_CAP_2_NVLINK_INFO_AVAILABILITY_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_2_FRU_PART_NUMBER_V1 31:31 +#define NV_MSGBOX_DATA_CAP_2_FRU_PART_NUMBER_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_2_FRU_PART_NUMBER_V1_AVAILABLE 0x00000001 #define NV_MSGBOX_DATA_CAP_4 4 #define NV_MSGBOX_DATA_CAP_4_HW_VIOLATION_TIME 0:0 @@ -946,9 +951,15 @@ #define NV_MSGBOX_DATA_CAP_4_GPU_PERFORMANCE_MONITORING 24:24 #define NV_MSGBOX_DATA_CAP_4_GPU_PERFORMANCE_MONITORING_NOT_AVAILABLE 0x00000000 #define NV_MSGBOX_DATA_CAP_4_GPU_PERFORMANCE_MONITORING_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_4_DEM_BY_SEQNUM_TIMESTAMP 26:26 +#define NV_MSGBOX_DATA_CAP_4_DEM_BY_SEQNUM_TIMESTAMP_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_4_DEM_BY_SEQNUM_TIMESTAMP_AVAILABLE 0x00000001 #define NV_MSGBOX_DATA_CAP_4_CONFIGURE_PROGRAMMABLE_EDPP 30:30 #define NV_MSGBOX_DATA_CAP_4_CONFIGURE_PROGRAMMABLE_EDPP_NOT_AVAILABLE 0x00000000 #define NV_MSGBOX_DATA_CAP_4_CONFIGURE_PROGRAMMABLE_EDPP_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_4_MAX_DRAM_CAPACITY_V1 31:31 +#define NV_MSGBOX_DATA_CAP_4_MAX_DRAM_CAPACITY_V1_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_4_MAX_DRAM_CAPACITY_V1_AVAILABLE 0x00000001 /* ECC counters */ #define NV_MSGBOX_DATA_ECC_CNT_16BIT_DBE 31:16 @@ -1393,6 +1404,10 @@ #define NV_MSGBOX_SYSID_DATA_SIZE_PRODUCT_HEIGHT_V1 4 #define NV_MSGBOX_SYSID_DATA_SIZE_PCIE_SPEED_V1 1 #define NV_MSGBOX_SYSID_DATA_SIZE_PCIE_WIDTH_V1 1 +#define NV_MSGBOX_SYSID_DATA_SIZE_TGP_LIMIT_V1 4 +#define NV_MSGBOX_SYSID_DATA_SIZE_FRU_PART_NUMBER_V1 20 +#define NV_MSGBOX_SYSID_DATA_SIZE_MODULE_POWER_LIMIT_V1 4 +#define NV_MSGBOX_SYSID_DATA_SIZE_MAX_DRAM_CAPACITY_V1 4 /*! * Response to NV_MSGBOX_CMD_ARG1_GET_POWER_HINT_INFO_CLK diff --git a/src/nvidia/arch/nvalloc/unix/include/nv-chardev-numbers.h b/src/nvidia/arch/nvalloc/unix/include/nv-chardev-numbers.h new file mode 100644 index 0000000000..54ca547e08 --- /dev/null +++ b/src/nvidia/arch/nvalloc/unix/include/nv-chardev-numbers.h @@ -0,0 +1,43 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _NV_CHARDEV_NUMBERS_H_ +#define _NV_CHARDEV_NUMBERS_H_ + +// NVIDIA's reserved major character device number (Linux). +#define NV_MAJOR_DEVICE_NUMBER 195 + +// Minor numbers 0 to 247 reserved for regular devices +#define NV_MINOR_DEVICE_NUMBER_REGULAR_MAX 247 + +// Minor numbers 248 to 253 currently unused + +// Minor number 254 reserved for the modeset device (provided by NVKMS) +#define NV_MINOR_DEVICE_NUMBER_MODESET_DEVICE 254 + +// Minor number 255 reserved for the control device +#define NV_MINOR_DEVICE_NUMBER_CONTROL_DEVICE 255 + +#endif // _NV_CHARDEV_NUMBERS_H_ + diff --git a/src/nvidia/arch/nvalloc/unix/include/nv-ioctl-nvlog.h b/src/nvidia/arch/nvalloc/unix/include/nv-ioctl-lockless-diag.h similarity index 92% rename from src/nvidia/arch/nvalloc/unix/include/nv-ioctl-nvlog.h rename to src/nvidia/arch/nvalloc/unix/include/nv-ioctl-lockless-diag.h index a3ad427b7b..84e3fa745d 100644 --- a/src/nvidia/arch/nvalloc/unix/include/nv-ioctl-nvlog.h +++ b/src/nvidia/arch/nvalloc/unix/include/nv-ioctl-lockless-diag.h @@ -21,15 +21,15 @@ * DEALINGS IN THE SOFTWARE. */ -#if !defined(NV_IOCTL_NVLOG) -#define NV_IOCTL_NVLOG +#if !defined(NV_IOCTL_LOCKLESS_DIAG) +#define NV_IOCTL_LOCKLESS_DIAG #include #include "ctrl/ctrl0000/ctrl0000nvd.h" typedef struct { - NvU32 ctrl; // in + NvU32 cmd; // in NvU32 status; // out union // in/out { @@ -37,7 +37,7 @@ typedef struct NV0000_CTRL_NVD_GET_NVLOG_BUFFER_INFO_PARAMS getNvlogBufferInfo; NV0000_CTRL_NVD_GET_NVLOG_PARAMS getNvlog; } params; -} NV_NVLOG_CTRL_PARAMS; +} NV_LOCKLESS_DIAGNOSTIC_PARAMS; #endif diff --git a/src/nvidia/arch/nvalloc/unix/include/nv-ioctl-numa.h b/src/nvidia/arch/nvalloc/unix/include/nv-ioctl-numa.h new file mode 100644 index 0000000000..0af52675d5 --- /dev/null +++ b/src/nvidia/arch/nvalloc/unix/include/nv-ioctl-numa.h @@ -0,0 +1,81 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef NV_IOCTL_NUMA_H +#define NV_IOCTL_NUMA_H + +#include + +#if defined(NV_KERNEL_INTERFACE_LAYER) && defined(NV_LINUX) +#include +#elif defined (NV_KERNEL_INTERFACE_LAYER) && defined(NV_BSD) +#include +#else + +#include + +#if !defined(__aligned) +#define __aligned(n) __attribute__((aligned(n))) +#endif + +#endif + +#define NV_ESC_NUMA_INFO (NV_IOCTL_BASE + 15) +#define NV_ESC_SET_NUMA_STATUS (NV_IOCTL_BASE + 16) + +#define NV_IOCTL_NUMA_INFO_MAX_OFFLINE_ADDRESSES 64 +typedef struct offline_addresses +{ + uint64_t addresses[NV_IOCTL_NUMA_INFO_MAX_OFFLINE_ADDRESSES] __aligned(8); + uint32_t numEntries; +} nv_offline_addresses_t; + + +/* per-device NUMA memory info as assigned by the system */ +typedef struct nv_ioctl_numa_info +{ + int32_t nid; + int32_t status; + uint64_t memblock_size __aligned(8); + uint64_t numa_mem_addr __aligned(8); + uint64_t numa_mem_size __aligned(8); + uint8_t use_auto_online; + nv_offline_addresses_t offline_addresses __aligned(8); +} nv_ioctl_numa_info_t; + +/* set the status of the device NUMA memory */ +typedef struct nv_ioctl_set_numa_status +{ + int32_t status; +} nv_ioctl_set_numa_status_t; + +#define NV_IOCTL_NUMA_STATUS_DISABLED 0 +#define NV_IOCTL_NUMA_STATUS_OFFLINE 1 +#define NV_IOCTL_NUMA_STATUS_ONLINE_IN_PROGRESS 2 +#define NV_IOCTL_NUMA_STATUS_ONLINE 3 +#define NV_IOCTL_NUMA_STATUS_ONLINE_FAILED 4 +#define NV_IOCTL_NUMA_STATUS_OFFLINE_IN_PROGRESS 5 +#define NV_IOCTL_NUMA_STATUS_OFFLINE_FAILED 6 + +#endif diff --git a/src/nvidia/arch/nvalloc/unix/include/nv-priv.h b/src/nvidia/arch/nvalloc/unix/include/nv-priv.h index 92b46eb62d..dac77ab0dc 100644 --- a/src/nvidia/arch/nvalloc/unix/include/nv-priv.h +++ b/src/nvidia/arch/nvalloc/unix/include/nv-priv.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -77,28 +77,6 @@ typedef struct nv_work_item_s #define NV_WORK_ITEM_FLAGS_REQUIRES_GPU 0x1 #define NV_WORK_ITEM_FLAGS_DONT_FREE_DATA 0x2 -/* - * pseudo-registry data structure - */ - -typedef enum -{ - NV_REGISTRY_ENTRY_TYPE_UNKNOWN = 0, - NV_REGISTRY_ENTRY_TYPE_DWORD, - NV_REGISTRY_ENTRY_TYPE_BINARY, - NV_REGISTRY_ENTRY_TYPE_STRING -} nv_reg_type_t; - -typedef struct nv_reg_entry_s -{ - char *regParmStr; - NvU32 type; - NvU32 data; // used when type == NV_REGISTRY_ENTRY_TYPE_DWORD - NvU8 *pdata; // used when type == NV_REGISTRY_ENTRY_TYPE_{BINARY,STRING} - NvU32 len; // used when type == NV_REGISTRY_ENTRY_TYPE_{BINARY,STRING} - struct nv_reg_entry_s *next; -} nv_reg_entry_t; - #define INVALID_DISP_ID 0xFFFFFFFF #define MAX_DISP_ID_PER_ADAPTER 0x2 diff --git a/src/nvidia/arch/nvalloc/unix/include/nv-reg.h b/src/nvidia/arch/nvalloc/unix/include/nv-reg.h index c8ea2ced09..d552477293 100644 --- a/src/nvidia/arch/nvalloc/unix/include/nv-reg.h +++ b/src/nvidia/arch/nvalloc/unix/include/nv-reg.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2006-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2006-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -771,16 +771,11 @@ /* * Option: OpenRmEnableUnsupportedGpus * - * Open nvidia.ko support for features beyond what is used on Data Center GPUs - * is still fairly immature, so for now require users to opt into use of open - * nvidia.ko with a special registry key, if not on a Data Center GPU. + * This option to require opt in for use of Open RM on non-Data Center + * GPUs is deprecated and no longer required. The kernel module parameter + * is left here, though ignored, for backwards compatibility. */ - #define __NV_OPENRM_ENABLE_UNSUPPORTED_GPUS OpenRmEnableUnsupportedGpus -#define NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS NV_REG_STRING(__NV_OPENRM_ENABLE_UNSUPPORTED_GPUS) -#define NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS_DISABLE 0x00000000 -#define NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS_ENABLE 0x00000001 -#define NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS_DEFAULT NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS_DISABLE /* * Option: NVreg_DmaRemapPeerMmio @@ -853,7 +848,7 @@ NV_DEFINE_REG_ENTRY(__NV_DYNAMIC_POWER_MANAGEMENT, 3); NV_DEFINE_REG_ENTRY(__NV_DYNAMIC_POWER_MANAGEMENT_VIDEO_MEMORY_THRESHOLD, 200); NV_DEFINE_REG_ENTRY(__NV_ENABLE_GPU_FIRMWARE, NV_REG_ENABLE_GPU_FIRMWARE_DEFAULT_VALUE); NV_DEFINE_REG_ENTRY(__NV_ENABLE_GPU_FIRMWARE_LOGS, NV_REG_ENABLE_GPU_FIRMWARE_LOGS_ENABLE_ON_DEBUG); -NV_DEFINE_REG_ENTRY(__NV_OPENRM_ENABLE_UNSUPPORTED_GPUS, NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS_DEFAULT); +NV_DEFINE_REG_ENTRY(__NV_OPENRM_ENABLE_UNSUPPORTED_GPUS, 1); NV_DEFINE_REG_ENTRY_GLOBAL(__NV_ENABLE_USER_NUMA_MANAGEMENT, 1); NV_DEFINE_REG_ENTRY_GLOBAL(__NV_MEMORY_POOL_SIZE, 0); diff --git a/src/nvidia/arch/nvalloc/unix/include/nv.h b/src/nvidia/arch/nvalloc/unix/include/nv.h index 3a71d7e40f..0bcfc49612 100644 --- a/src/nvidia/arch/nvalloc/unix/include/nv.h +++ b/src/nvidia/arch/nvalloc/unix/include/nv.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -42,6 +42,7 @@ #include #include #include +#include #include extern nv_cap_t *nvidia_caps_root; @@ -50,9 +51,6 @@ extern const NvBool nv_is_rm_firmware_supported_os; #include -/* NVIDIA's reserved major character device number (Linux). */ -#define NV_MAJOR_DEVICE_NUMBER 195 - #define GPU_UUID_LEN (16) /* @@ -478,8 +476,6 @@ typedef struct nv_state_t /* Bool to check if dma-buf is supported */ NvBool dma_buf_supported; - NvBool printed_openrm_enable_unsupported_gpus_error; - /* Check if NVPCF DSM function is implemented under NVPCF or GPU device scope */ NvBool nvpcf_dsm_in_gpu_scope; @@ -505,6 +501,7 @@ struct nv_file_private_t NvHandle *handles; NvU16 maxHandles; NvU32 deviceInstance; + NvU32 gpuInstanceId; NvU8 metadata[64]; nv_file_private_t *ctl_nvfp; @@ -765,7 +762,7 @@ nv_state_t* NV_API_CALL nv_get_ctl_state (void); void NV_API_CALL nv_set_dma_address_size (nv_state_t *, NvU32 ); NV_STATUS NV_API_CALL nv_alias_pages (nv_state_t *, NvU32, NvU32, NvU32, NvU64, NvU64 *, void **); -NV_STATUS NV_API_CALL nv_alloc_pages (nv_state_t *, NvU32, NvBool, NvU32, NvBool, NvBool, NvS32, NvU64 *, void **); +NV_STATUS NV_API_CALL nv_alloc_pages (nv_state_t *, NvU32, NvU64, NvBool, NvU32, NvBool, NvBool, NvS32, NvU64 *, void **); NV_STATUS NV_API_CALL nv_free_pages (nv_state_t *, NvU32, NvBool, NvU32, void *); NV_STATUS NV_API_CALL nv_register_user_pages (nv_state_t *, NvU64, NvU64 *, void *, void **); @@ -981,7 +978,7 @@ NV_STATUS NV_API_CALL rm_dma_buf_dup_mem_handle (nvidia_stack_t *, nv_state_t void NV_API_CALL rm_dma_buf_undup_mem_handle(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle); NV_STATUS NV_API_CALL rm_dma_buf_map_mem_handle (nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvU64, NvU64, void *, nv_phys_addr_range_t **, NvU32 *); void NV_API_CALL rm_dma_buf_unmap_mem_handle(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvU64, nv_phys_addr_range_t **, NvU32); -NV_STATUS NV_API_CALL rm_dma_buf_get_client_and_device(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle *, NvHandle *, NvHandle *, void **, NvBool *); +NV_STATUS NV_API_CALL rm_dma_buf_get_client_and_device(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvHandle *, NvHandle *, NvHandle *, void **, NvBool *); void NV_API_CALL rm_dma_buf_put_client_and_device(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvHandle, void *); NV_STATUS NV_API_CALL rm_log_gpu_crash (nv_stack_t *, nv_state_t *); @@ -993,7 +990,7 @@ NvBool NV_API_CALL rm_gpu_need_4k_page_isolation(nv_state_t *); NvBool NV_API_CALL rm_is_chipset_io_coherent(nv_stack_t *); NvBool NV_API_CALL rm_init_event_locks(nvidia_stack_t *, nv_state_t *); void NV_API_CALL rm_destroy_event_locks(nvidia_stack_t *, nv_state_t *); -NV_STATUS NV_API_CALL rm_get_gpu_numa_info(nvidia_stack_t *, nv_state_t *, NvS32 *, NvU64 *, NvU64 *, NvU64 *, NvU32 *); +NV_STATUS NV_API_CALL rm_get_gpu_numa_info(nvidia_stack_t *, nv_state_t *, nv_ioctl_numa_info_t *); NV_STATUS NV_API_CALL rm_gpu_numa_online(nvidia_stack_t *, nv_state_t *); NV_STATUS NV_API_CALL rm_gpu_numa_offline(nvidia_stack_t *, nv_state_t *); NvBool NV_API_CALL rm_is_device_sequestered(nvidia_stack_t *, nv_state_t *); @@ -1008,7 +1005,7 @@ void NV_API_CALL rm_cleanup_dynamic_power_management(nvidia_stack_t *, nv_ void NV_API_CALL rm_enable_dynamic_power_management(nvidia_stack_t *, nv_state_t *); NV_STATUS NV_API_CALL rm_ref_dynamic_power(nvidia_stack_t *, nv_state_t *, nv_dynamic_power_mode_t); void NV_API_CALL rm_unref_dynamic_power(nvidia_stack_t *, nv_state_t *, nv_dynamic_power_mode_t); -NV_STATUS NV_API_CALL rm_transition_dynamic_power(nvidia_stack_t *, nv_state_t *, NvBool); +NV_STATUS NV_API_CALL rm_transition_dynamic_power(nvidia_stack_t *, nv_state_t *, NvBool, NvBool *); const char* NV_API_CALL rm_get_vidmem_power_status(nvidia_stack_t *, nv_state_t *); const char* NV_API_CALL rm_get_dynamic_power_management_status(nvidia_stack_t *, nv_state_t *); const char* NV_API_CALL rm_get_gpu_gcx_support(nvidia_stack_t *, nv_state_t *, NvBool); @@ -1023,7 +1020,8 @@ NV_STATUS NV_API_CALL nv_vgpu_create_request(nvidia_stack_t *, nv_state_t *, c NV_STATUS NV_API_CALL nv_vgpu_delete(nvidia_stack_t *, const NvU8 *, NvU16); NV_STATUS NV_API_CALL nv_vgpu_get_type_ids(nvidia_stack_t *, nv_state_t *, NvU32 *, NvU32 *, NvBool, NvU8, NvBool); NV_STATUS NV_API_CALL nv_vgpu_get_type_info(nvidia_stack_t *, nv_state_t *, NvU32, char *, int, NvU8); -NV_STATUS NV_API_CALL nv_vgpu_get_bar_info(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU64 *, NvU32, void *); +NV_STATUS NV_API_CALL nv_vgpu_get_bar_info(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU64 *, NvU32, void *, NvBool *); +NV_STATUS NV_API_CALL nv_vgpu_get_hbm_info(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU64 *, NvU64 *); NV_STATUS NV_API_CALL nv_vgpu_start(nvidia_stack_t *, const NvU8 *, void *, NvS32 *, NvU8 *, NvU32); NV_STATUS NV_API_CALL nv_vgpu_get_sparse_mmap(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU64 **, NvU64 **, NvU32 *); NV_STATUS NV_API_CALL nv_vgpu_process_vf_info(nvidia_stack_t *, nv_state_t *, NvU8, NvU32, NvU8, NvU8, NvU8, NvBool, void *); diff --git a/src/nvidia/arch/nvalloc/unix/include/nv_escape.h b/src/nvidia/arch/nvalloc/unix/include/nv_escape.h index ecd3edaffc..3310292cd7 100644 --- a/src/nvidia/arch/nvalloc/unix/include/nv_escape.h +++ b/src/nvidia/arch/nvalloc/unix/include/nv_escape.h @@ -50,6 +50,6 @@ #define NV_ESC_RM_EXPORT_OBJECT_TO_FD 0x5C #define NV_ESC_RM_IMPORT_OBJECT_FROM_FD 0x5D #define NV_ESC_RM_UPDATE_DEVICE_MAPPING_INFO 0x5E -#define NV_ESC_RM_NVLOG_CTRL 0x5F +#define NV_ESC_RM_LOCKLESS_DIAGNOSTIC 0x5F #endif // NV_ESCAPE_H_INCLUDED diff --git a/src/nvidia/arch/nvalloc/unix/include/os-interface.h b/src/nvidia/arch/nvalloc/unix/include/os-interface.h index 5249e124e5..ffbf4e1f5a 100644 --- a/src/nvidia/arch/nvalloc/unix/include/os-interface.h +++ b/src/nvidia/arch/nvalloc/unix/include/os-interface.h @@ -162,7 +162,7 @@ NvBool NV_API_CALL os_is_vgx_hyper (void); NV_STATUS NV_API_CALL os_inject_vgx_msi (NvU16, NvU64, NvU32); NvBool NV_API_CALL os_is_grid_supported (void); NvU32 NV_API_CALL os_get_grid_csp_support (void); -void NV_API_CALL os_get_screen_info (NvU64 *, NvU16 *, NvU16 *, NvU16 *, NvU16 *, NvU64, NvU64); +void NV_API_CALL os_get_screen_info (NvU64 *, NvU32 *, NvU32 *, NvU32 *, NvU32 *, NvU64, NvU64); void NV_API_CALL os_bug_check (NvU32, const char *); NV_STATUS NV_API_CALL os_lock_user_pages (void *, NvU64, void **, NvU32); NV_STATUS NV_API_CALL os_lookup_user_io_memory (void *, NvU64, NvU64 **, void**); @@ -230,12 +230,14 @@ extern NvBool os_dma_buf_enabled; * --------------------------------------------------------------------------- */ -#define NV_DBG_INFO 0x0 -#define NV_DBG_SETUP 0x1 -#define NV_DBG_USERERRORS 0x2 +#define NV_DBG_INFO 0x1 +#define NV_DBG_SETUP 0x2 #define NV_DBG_WARNINGS 0x3 #define NV_DBG_ERRORS 0x4 +#define NV_DBG_HW_ERRORS 0x5 +#define NV_DBG_FATAL 0x6 +#define NV_DBG_FORCE_LEVEL(level) ((level) | (1 << 8)) void NV_API_CALL out_string(const char *str); int NV_API_CALL nv_printf(NvU32 debuglevel, const char *printf_format, ...); diff --git a/src/nvidia/arch/nvalloc/unix/include/osfuncs.h b/src/nvidia/arch/nvalloc/unix/include/osfuncs.h index 19f2fa28ac..f6c9e85085 100644 --- a/src/nvidia/arch/nvalloc/unix/include/osfuncs.h +++ b/src/nvidia/arch/nvalloc/unix/include/osfuncs.h @@ -32,13 +32,6 @@ #include -OSQueueWorkItem osQueueWorkItem; -OSQueueWorkItemWithFlags osQueueWorkItemWithFlags; -OSQueueSystemWorkItem osQueueSystemWorkItem; -OSDbgBreakpointEnabled osDbgBreakpointEnabled; - -void* osGetStereoDongleInterface(void); - #if defined(NVCPU_X86_64) OSnv_rdcr4 nv_rdcr4; NvU64 nv_rdcr3(OBJOS *); diff --git a/src/nvidia/arch/nvalloc/unix/include/rmobjexportimport.h b/src/nvidia/arch/nvalloc/unix/include/rmobjexportimport.h index 1330ad8de4..a070c4e0a6 100644 --- a/src/nvidia/arch/nvalloc/unix/include/rmobjexportimport.h +++ b/src/nvidia/arch/nvalloc/unix/include/rmobjexportimport.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2016 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2016-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -36,7 +36,5 @@ void RmFreeObjExportHandle(RmObjExportHandle hObject); NV_STATUS RmImportObject(NvHandle hDstClient, NvHandle hDstParent, NvHandle *phDstObject, RmObjExportHandle hSrcObject, NvU8 *pObjectType); - -NV_STATUS RmGetExportObjectInfo(RmObjExportHandle hSrcObject, NvU32 *deviceInstance); #endif // _RMOBJEXPORTIMPORT_H_ diff --git a/src/nvidia/arch/nvalloc/unix/src/dynamic-power.c b/src/nvidia/arch/nvalloc/unix/src/dynamic-power.c index f7e4bbb7a7..934bff13a3 100644 --- a/src/nvidia/arch/nvalloc/unix/src/dynamic-power.c +++ b/src/nvidia/arch/nvalloc/unix/src/dynamic-power.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -128,7 +128,7 @@ static void RmScheduleCallbackForIdlePreConditions(OBJGPU *); static void RmScheduleCallbackForIdlePreConditionsUnderGpuLock(OBJGPU *); static void RmScheduleCallbackToIndicateIdle(OBJGPU *); -static NvBool RmCheckForGc6SupportOnCurrentState(OBJGPU *); +static NvBool RmCheckForGcxSupportOnCurrentState(OBJGPU *); static void RmScheduleCallbackToRemoveIdleHoldoff(OBJGPU *); static void RmQueueIdleSustainedWorkitem(OBJGPU *); @@ -246,18 +246,36 @@ NvBool nv_dynamic_power_state_transition( * * @return TRUE if the GPU appears to be currently idle; FALSE otherwise. */ -static NvBool RmCheckForGpuIdlenessUnderGpuLock( +static NvBool RmCanEnterGcxUnderGpuLock( OBJGPU *pGpu ) { NV_ASSERT(rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); + /* + * If GPU does not support GC6 and the actual FB utilization is higher than the threshold, + * then the GPU can neither enter GC6 nor GCOFF. So, return from here. + */ + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_RTD3_GC6_SUPPORTED)) + { + NvU64 usedFbSize = 0; + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_priv_t *nvp = NV_GET_NV_PRIV(nv); + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + + if (!((memmgrGetUsedRamSize(pGpu, pMemoryManager, &usedFbSize) == NV_OK) && + (usedFbSize <= nvp->dynamic_power.gcoff_max_fb_size))) + { + return NV_FALSE; + } + } + // Check the instantaneous engine level idleness. - return RmCheckForGc6SupportOnCurrentState(pGpu); + return RmCheckForGcxSupportOnCurrentState(pGpu); } /*! - * @brief: Check if the GPU hardware appears to be idle. + * @brief: Check the feasibility of GPU engaging in a GCx cycle. * * Takes the GPU lock. * @@ -265,7 +283,7 @@ static NvBool RmCheckForGpuIdlenessUnderGpuLock( * * @return TRUE if the GPU appears to be currently idle; FALSE otherwise. */ -static NvBool RmCheckForGpuIdleness( +static NvBool RmCanEnterGcx( OBJGPU *pGpu ) { @@ -279,7 +297,7 @@ static NvBool RmCheckForGpuIdleness( &gpuMask); if (status == NV_OK) { - result = RmCheckForGpuIdlenessUnderGpuLock(pGpu); + result = RmCanEnterGcxUnderGpuLock(pGpu); // UNLOCK: release per device lock rmGpuGroupLockRelease(gpuMask, GPUS_LOCK_FLAGS_NONE); } @@ -365,7 +383,7 @@ static void RmIndicateIdle( if (nv_get_all_mappings_revoked_locked(nv) && nvp->dynamic_power.state == NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED && - RmCheckForGpuIdleness(pGpu)) + RmCanEnterGcx(pGpu)) { nv_set_safe_to_mmap_locked(nv, NV_FALSE); nv_dynamic_power_state_transition(nv, NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED, @@ -400,11 +418,10 @@ NV_STATUS NV_API_CALL rm_schedule_gpu_wakeup( void *fp; NV_STATUS ret; OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv); - OBJOS *pOS = GPU_GET_OS(pGpu); NV_ENTER_RM_RUNTIME(sp, fp); - ret = pOS->osQueueWorkItem(pGpu, RmForceGpuNotIdle, NULL); + ret = osQueueWorkItem(pGpu, RmForceGpuNotIdle, NULL); NV_EXIT_RM_RUNTIME(sp, fp); @@ -1293,36 +1310,36 @@ void osUnrefGpuAccessNeeded( } /*! - * @brief Check if GC6 is supported on current pstate and if engines are idle. + * @brief Check if GCx is supported on current pstate and if engines are idle. * * @param[in] pGpu OBJGPU pointer. */ -static NvBool RmCheckForGc6SupportOnCurrentState( +static NvBool RmCheckForGcxSupportOnCurrentState( OBJGPU *pGpu ) { NV_STATUS status = NV_OK; nv_state_t *nv = NV_GET_NV_STATE(pGpu); RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); - NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS entryPrerequisiteParams; + NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS entryPrerequisiteParams; portMemSet(&entryPrerequisiteParams, 0, sizeof(entryPrerequisiteParams)); status = pRmApi->Control(pRmApi, nv->rmapi.hClient, nv->rmapi.hSubDevice, - NV2080_CTRL_CMD_INTERNAL_GC6_ENTRY_PREREQUISITE, + NV2080_CTRL_CMD_INTERNAL_GCX_ENTRY_PREREQUISITE, (void*)&entryPrerequisiteParams, sizeof(entryPrerequisiteParams)); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "NVRM, Failed to get GC6 pre-requisite, status=0x%x\n", + NV_PRINTF(LEVEL_ERROR, "NVRM, Failed to get GCx pre-requisite, status=0x%x\n", status); return NV_FALSE; } - return entryPrerequisiteParams.bIsSatisfied; + return entryPrerequisiteParams.bIsGC6Satisfied || entryPrerequisiteParams.bIsGCOFFSatisfied; } /*! @@ -1348,7 +1365,7 @@ static void RmRemoveIdleHoldoff( if (nvp->dynamic_power.b_idle_holdoff == NV_TRUE) { - if ((RmCheckForGc6SupportOnCurrentState(pGpu) == NV_TRUE) || + if ((RmCheckForGcxSupportOnCurrentState(pGpu) == NV_TRUE) || (nvp->dynamic_power.idle_precondition_check_callback_scheduled)) { nv_indicate_idle(nv); @@ -1372,12 +1389,11 @@ static void timerCallbackToRemoveIdleHoldoff( ) { OBJGPU *pGpu = reinterpretCast(pCallbackData, OBJGPU *); - OBJOS *pOS = GPU_GET_OS(pGpu); - pOS->osQueueWorkItemWithFlags(pGpu, - RmRemoveIdleHoldoff, - NULL, - OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_SUBDEVICE_RW); + osQueueWorkItemWithFlags(pGpu, + RmRemoveIdleHoldoff, + NULL, + OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_SUBDEVICE_RW); } /*! @@ -1393,15 +1409,14 @@ static void timerCallbackToIndicateIdle( OBJGPU *pGpu = reinterpretCast(pCallbackData, OBJGPU *); nv_state_t *nv = NV_GET_NV_STATE(pGpu); nv_priv_t *nvp = NV_GET_NV_PRIV(nv); - OBJOS *pOS = GPU_GET_OS(pGpu); nv_acquire_mmap_lock(nv); if (nv_get_all_mappings_revoked_locked(nv) && nvp->dynamic_power.state == NV_DYNAMIC_POWER_STATE_IDLE_SUSTAINED && - RmCheckForGpuIdlenessUnderGpuLock(pGpu)) + RmCanEnterGcxUnderGpuLock(pGpu)) { - pOS->osQueueWorkItem(pGpu, RmIndicateIdle, NULL); + osQueueWorkItem(pGpu, RmIndicateIdle, NULL); } else { @@ -1459,7 +1474,7 @@ static void timerCallbackForIdlePreConditions( if (nvp->dynamic_power.state != NV_DYNAMIC_POWER_STATE_IN_USE) { - if (RmCheckForGpuIdlenessUnderGpuLock(pGpu)) + if (RmCanEnterGcxUnderGpuLock(pGpu)) { switch (nvp->dynamic_power.state) { @@ -1927,7 +1942,7 @@ static void RmScheduleCallbackToRemoveIdleHoldoff( * * @param[in] pGpu OBJGPU pointer. */ -static NvBool RmCheckRtd3Gc6Support( +static NvBool RmCheckRtd3GcxSupport( nv_state_t *pNv ) { @@ -1936,6 +1951,8 @@ static NvBool RmCheckRtd3Gc6Support( RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); NV_STATUS status; NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS virtModeParams = { 0 }; + NvBool bGC6Support = NV_FALSE; + NvBool bGCOFFSupport = NV_FALSE; if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_UNIX_DYNAMIC_POWER_SUPPORTED)) { @@ -1943,15 +1960,22 @@ static NvBool RmCheckRtd3Gc6Support( return NV_FALSE; } - if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_RTD3_GC6_SUPPORTED)) + if (nvp->b_mobile_config_enabled) { - NV_PRINTF(LEVEL_NOTICE, "NVRM: RTD3/GC6 is not supported in Vbios\n"); - return NV_FALSE; + bGC6Support = pGpu->getProperty(pGpu, PDB_PROP_GPU_RTD3_GC6_SUPPORTED); + bGCOFFSupport = bGC6Support; + } + else + { + bGC6Support = pGpu->getProperty(pGpu, PDB_PROP_GPU_RTD3_GC6_SUPPORTED); + bGCOFFSupport = pGpu->getProperty(pGpu, PDB_PROP_GPU_RTD3_GCOFF_SUPPORTED); } - if (!nvp->b_mobile_config_enabled) + if (!bGC6Support && !bGCOFFSupport) { - NV_PRINTF(LEVEL_NOTICE, "NVRM: Disabling RTD3/GC6, as it is only supported on Notebook SKU\n"); + NV_PRINTF(LEVEL_NOTICE, + "NVRM: Disabling RTD3. [GC6 support=%d GCOFF support=%d]\n", + bGC6Support, bGCOFFSupport); return NV_FALSE; } @@ -1997,7 +2021,7 @@ void RmInitDeferredDynamicPowerManagement( { OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv); - if (!RmCheckRtd3Gc6Support(nv)) + if (!RmCheckRtd3GcxSupport(nv)) { nvp->dynamic_power.mode = NV_DYNAMIC_PM_NEVER; nvp->dynamic_power.b_fine_not_supported = NV_TRUE; @@ -2221,7 +2245,8 @@ RmPowerManagement( NV_STATUS RmGcxPowerManagement( OBJGPU *pGpu, NvBool bEnter, - NvBool bIsDynamicPM + NvBool bIsDynamicPM, + NvBool *bTryAgain ) { KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); @@ -2245,16 +2270,21 @@ NV_STATUS RmGcxPowerManagement( if (bEnter) { MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); - NvU64 usedFbSize; - NvBool bCanUseGc6; + NvU64 usedFbSize = 0; + NvBool bCanUseGc6 = NV_FALSE; + NV_STATUS fbsrStatus = NV_ERR_GENERIC; // - // Check if GC6 can be used for current power management request. - // For dynamic PM, it can be used always. - // For system PM, it can be used only if current system suspend - // happened with s2idle. + // If the GPU supports GC6, then check if GC6 can be used for + // the current power management request. + // 1. For dynamic PM, GC6 can be used if it is supported by the GPU. + // 2. For system PM with s2idle, GC6 can be used if it is + // supported by the GPU. // - bCanUseGc6 = bIsDynamicPM ? NV_TRUE : nv_s2idle_pm_configured(); + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_RTD3_GC6_SUPPORTED)) + { + bCanUseGc6 = bIsDynamicPM ? NV_TRUE : nv_s2idle_pm_configured(); + } // // If GC6 cannot be used, then no need to compare the used FB size with @@ -2262,8 +2292,8 @@ NV_STATUS RmGcxPowerManagement( // if ((memmgrGetUsedRamSize(pGpu, pMemoryManager, &usedFbSize) == NV_OK) && (!bCanUseGc6 || RmCheckForGcOffPM(pGpu, usedFbSize, bIsDynamicPM)) && - (fbsrReserveSysMemoryForPowerMgmt(pGpu, pMemoryManager->pFbsr[FBSR_TYPE_DMA], - usedFbSize) == NV_OK)) + ((fbsrStatus = fbsrReserveSysMemoryForPowerMgmt(pGpu, pMemoryManager->pFbsr[FBSR_TYPE_DMA], + usedFbSize)) == NV_OK)) { pGpu->setProperty(pGpu, PDB_PROP_GPU_GCOFF_STATE_ENTERING, NV_TRUE); @@ -2330,19 +2360,32 @@ NV_STATUS RmGcxPowerManagement( } } // - // This condition will hit only for systems which support s2idle but - // are currently configured for deep sleep based system power - // management, and that too when sufficient system memory - // is not available. For this case, the suspend request will fail - // and the system will remain in S0. + // The else condition below will hit in the following cases: + // Case 1. During system suspend transition: For systems that support s2idle but are configured + // for deep sleep, this "else" condition will be hit when the system memory + // is not sufficient. In this case, we should unset bTryAgain to abort the current suspend entry. + // Case 2. During runtime suspend transition: For systems that do not support GC6 but support + // GCOFF, this "else" condition will be hit when system memory is not sufficent, In this case, we + // should set bTryagain so that the kernel can reschedule the callback later. // else { - status = NV_ERR_NOT_SUPPORTED; - NV_PRINTF(LEVEL_ERROR, - "NVRM: %s: System suspend failed with current system suspend configuration. " - "Please change the system suspend configuration to s2idle in /sys/power/mem_sleep.\n", - __FUNCTION__); + if (bIsDynamicPM) + { + if (fbsrStatus == NV_ERR_NO_MEMORY) + { + *bTryAgain = NV_TRUE; + } + status = fbsrStatus; + } + else + { + status = NV_ERR_NOT_SUPPORTED; + NV_PRINTF(LEVEL_ERROR, + "NVRM: %s: System suspend failed with current system suspend configuration. " + "Please change the system suspend configuration to s2idle in /sys/power/mem_sleep.\n", + __FUNCTION__); + } } } else @@ -2377,6 +2420,7 @@ NV_STATUS NV_API_CALL rm_power_management( THREAD_STATE_NODE threadState; NV_STATUS rmStatus = NV_OK; void *fp; + NvBool bTryAgain = NV_FALSE; NV_ENTER_RM_RUNTIME(sp,fp); threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); @@ -2421,7 +2465,7 @@ NV_STATUS NV_API_CALL rm_power_management( { rmStatus = RmGcxPowerManagement(pGpu, pmAction == NV_PM_ACTION_STANDBY, - NV_FALSE); + NV_FALSE, &bTryAgain); } else @@ -2461,13 +2505,14 @@ NV_STATUS NV_API_CALL rm_power_management( */ static NV_STATUS RmTransitionDynamicPower( OBJGPU *pGpu, - NvBool bEnter + NvBool bEnter, + NvBool *bTryAgain ) { nv_state_t *nv = NV_GET_NV_STATE(pGpu); NV_STATUS status; - status = RmGcxPowerManagement(pGpu, bEnter, NV_TRUE); + status = RmGcxPowerManagement(pGpu, bEnter, NV_TRUE, bTryAgain); if (!bEnter && status == NV_OK) { @@ -2493,7 +2538,8 @@ static NV_STATUS RmTransitionDynamicPower( NV_STATUS NV_API_CALL rm_transition_dynamic_power( nvidia_stack_t *sp, nv_state_t *nv, - NvBool bEnter + NvBool bEnter, + NvBool *bTryAgain ) { OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv); @@ -2509,7 +2555,7 @@ NV_STATUS NV_API_CALL rm_transition_dynamic_power( status = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DYN_POWER); if (status == NV_OK) { - status = RmTransitionDynamicPower(pGpu, bEnter); + status = RmTransitionDynamicPower(pGpu, bEnter, bTryAgain); // UNLOCK: release GPUs lock rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); @@ -2670,15 +2716,14 @@ static void RmQueueIdleSustainedWorkitem( { nv_state_t *nv = NV_GET_NV_STATE(pGpu); nv_priv_t *nvp = NV_GET_NV_PRIV(nv); - OBJOS *pOS = GPU_GET_OS(pGpu); NV_STATUS status = NV_OK; if (!nvp->dynamic_power.b_idle_sustained_workitem_queued) { - status = pOS->osQueueWorkItemWithFlags(pGpu, - RmHandleIdleSustained, - NULL, - OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_SUBDEVICE_RW); + status = osQueueWorkItemWithFlags(pGpu, + RmHandleIdleSustained, + NULL, + OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_SUBDEVICE_RW); if (status != NV_OK) { NV_PRINTF(LEVEL_WARNING, @@ -2703,10 +2748,16 @@ RmInitS0ixPowerManagement( NvU32 data; NvBool bRtd3Gc6Support = NV_FALSE; + // S0ix-based S2Idle, on desktops, is not supported yet. Return early for desktop SKUs + if (!nvp->b_mobile_config_enabled) + { + return; + } + // LOCK: acquire GPUs lock if (rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_INIT) == NV_OK) { - bRtd3Gc6Support = RmCheckRtd3Gc6Support(nv); + bRtd3Gc6Support = RmCheckRtd3GcxSupport(nv); // UNLOCK: release GPUs lock rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); diff --git a/src/nvidia/arch/nvalloc/unix/src/escape.c b/src/nvidia/arch/nvalloc/unix/src/escape.c index 0dcc375cc9..df36fa7885 100644 --- a/src/nvidia/arch/nvalloc/unix/src/escape.c +++ b/src/nvidia/arch/nvalloc/unix/src/escape.c @@ -48,7 +48,7 @@ #include "rmapi/client_resource.h" #include "nvlog/nvlog.h" -#include +#include #include @@ -70,18 +70,8 @@ } \ } -static NvBool RmIsDeviceRefNeeded(NVOS54_PARAMETERS *pApi) -{ - switch(pApi->cmd) - { - case NV00FD_CTRL_CMD_ATTACH_GPU: - return NV_TRUE; - default: - return NV_FALSE; - } -} - -static NV_STATUS RmGetDeviceFd(NVOS54_PARAMETERS *pApi, NvS32 *pFd) +static NV_STATUS RmGetDeviceFd(NVOS54_PARAMETERS *pApi, NvS32 *pFd, + NvBool *pSkipDeviceRef) { RMAPI_PARAM_COPY paramCopy; void *pKernelParams; @@ -89,6 +79,7 @@ static NV_STATUS RmGetDeviceFd(NVOS54_PARAMETERS *pApi, NvS32 *pFd) NV_STATUS status; *pFd = -1; + *pSkipDeviceRef = NV_TRUE; switch(pApi->cmd) { @@ -96,7 +87,7 @@ static NV_STATUS RmGetDeviceFd(NVOS54_PARAMETERS *pApi, NvS32 *pFd) paramSize = sizeof(NV00FD_CTRL_ATTACH_GPU_PARAMS); break; default: - return NV_ERR_INVALID_ARGUMENT; + return NV_OK; } RMAPI_PARAM_COPY_INIT(paramCopy, pKernelParams, pApi->params, paramSize, 1); @@ -108,7 +99,12 @@ static NV_STATUS RmGetDeviceFd(NVOS54_PARAMETERS *pApi, NvS32 *pFd) switch(pApi->cmd) { case NV00FD_CTRL_CMD_ATTACH_GPU: - *pFd = (NvS32)((NV00FD_CTRL_ATTACH_GPU_PARAMS *)pKernelParams)->devDescriptor; + { + NV00FD_CTRL_ATTACH_GPU_PARAMS *pAttachGpuParams = pKernelParams; + + *pSkipDeviceRef = NV_FALSE; + *pFd = (NvS32)pAttachGpuParams->devDescriptor; + } break; default: NV_ASSERT(0); @@ -761,6 +757,7 @@ NV_STATUS RmIoctl( void *priv = NULL; nv_file_private_t *dev_nvfp = NULL; NvS32 fd; + NvBool bSkipDeviceRef; NV_CTL_DEVICE_ONLY(nv); @@ -770,14 +767,14 @@ NV_STATUS RmIoctl( goto done; } - if (RmIsDeviceRefNeeded(pApi)) + rmStatus = RmGetDeviceFd(pApi, &fd, &bSkipDeviceRef); + if (rmStatus != NV_OK) { - rmStatus = RmGetDeviceFd(pApi, &fd); - if (rmStatus != NV_OK) - { - goto done; - } + goto done; + } + if (!bSkipDeviceRef) + { dev_nvfp = nv_get_file_private(fd, NV_FALSE, &priv); if (dev_nvfp == NULL) { @@ -843,9 +840,9 @@ NV_STATUS RmIoctl( break; } - case NV_ESC_RM_NVLOG_CTRL: + case NV_ESC_RM_LOCKLESS_DIAGNOSTIC: { - NV_NVLOG_CTRL_PARAMS *pParams = data; + NV_LOCKLESS_DIAGNOSTIC_PARAMS *pParams = data; NV_CTL_DEVICE_ONLY(nv); @@ -856,7 +853,7 @@ NV_STATUS RmIoctl( goto done; } - switch (pParams->ctrl) + switch (pParams->cmd) { // Do not use NVOC _DISPATCH here as it dereferences NULL RmClientResource* case NV0000_CTRL_CMD_NVD_GET_NVLOG_INFO: diff --git a/src/nvidia/arch/nvalloc/unix/src/os-hypervisor.c b/src/nvidia/arch/nvalloc/unix/src/os-hypervisor.c index 1d0a128699..b5aa0ffa8b 100644 --- a/src/nvidia/arch/nvalloc/unix/src/os-hypervisor.c +++ b/src/nvidia/arch/nvalloc/unix/src/os-hypervisor.c @@ -46,13 +46,14 @@ #include // NV_PMC_BOOT_1_VGPU #include "nvdevid.h" +#define NV_VFIO_PCI_BAR0_REGION_INDEX 0 #define NV_VFIO_PCI_BAR1_REGION_INDEX 1 #define NV_VFIO_PCI_BAR2_REGION_INDEX 2 #define NV_VFIO_PCI_BAR3_REGION_INDEX 3 static NV_STATUS nv_parse_config_params(const char *, const char *, const char, NvU32 *); -void hypervisorSetHypervVgpuSupported_IMPL(POBJHYPERVISOR pHypervisor) +void hypervisorSetHypervVgpuSupported_IMPL(OBJHYPERVISOR *pHypervisor) { pHypervisor->bIsHypervVgpuSupported = NV_TRUE; } @@ -67,14 +68,14 @@ NvBool hypervisorIsAC_IMPL(void) return NV_FALSE; } -void hypervisorSetACSupported_IMPL(POBJHYPERVISOR pHypervisor) +void hypervisorSetACSupported_IMPL(OBJHYPERVISOR *pHypervisor) { pHypervisor->bIsACSupported = NV_TRUE; } NV_STATUS hypervisorInjectInterrupt_IMPL ( - POBJHYPERVISOR pHypervisor, + OBJHYPERVISOR *pHypervisor, VGPU_NS_INTR *pVgpuNsIntr ) { @@ -98,7 +99,7 @@ NV_STATUS hypervisorInjectInterrupt_IMPL HYPERVISOR_TYPE NV_API_CALL nv_get_hypervisor_type(void) { OBJSYS *pSys = SYS_GET_INSTANCE(); - POBJHYPERVISOR pHypervisor = SYS_GET_HYPERVISOR(pSys); + OBJHYPERVISOR *pHypervisor = SYS_GET_HYPERVISOR(pSys); return hypervisorGetHypervisorType(pHypervisor); } @@ -268,7 +269,7 @@ NV_STATUS NV_API_CALL nv_vgpu_get_type_info( case VGPU_TYPE_DESCRIPTION: os_snprintf(buffer, MAX_STR_LEN, "num_heads=%d, frl_config=%d, " - "framebuffer=%dM, max_resolution=%dx%d, max_instance=%d\n", + "framebuffer=%lluM, max_resolution=%dx%d, max_instance=%d\n", vgpuTypeInfo->numHeads, vgpuTypeInfo->frlConfig, vgpuTypeInfo->profileSize >> 20, vgpuTypeInfo->maxResolutionX, @@ -474,13 +475,56 @@ NV_STATUS NV_API_CALL nv_vgpu_create_request( return rmStatus; } +static NV_STATUS is_bar_64bit( + OBJGPU *pGpu, + NvU32 regionIndex, + NvBool *isBar64bit +) +{ + NV_STATUS rmStatus = NV_OK; + + if (pGpu == NULL) + { + NV_PRINTF(LEVEL_ERROR, "%s GPU handle is not valid \n", __FUNCTION__); + rmStatus = NV_ERR_INVALID_STATE; + goto exit; + } + + switch (regionIndex) + { + case NV_VFIO_PCI_BAR0_REGION_INDEX: + *isBar64bit = pGpu->sriovState.b64bitVFBar0; + break; + + case NV_VFIO_PCI_BAR1_REGION_INDEX: + *isBar64bit = pGpu->sriovState.b64bitVFBar1; + break; + + case NV_VFIO_PCI_BAR2_REGION_INDEX: + *isBar64bit = pGpu->sriovState.b64bitVFBar2; + break; + + default: + NV_PRINTF(LEVEL_ERROR, "BAR%d region doesn't exist!\n", regionIndex); + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto exit; + break; + } + + NV_PRINTF(LEVEL_INFO, "BAR%d region is_64bit: %d\n", regionIndex, *isBar64bit);; + +exit: + return rmStatus; +} + NV_STATUS NV_API_CALL nv_vgpu_get_bar_info( nvidia_stack_t *sp, nv_state_t *pNv, const NvU8 *pMdevUuid, NvU64 *size, NvU32 regionIndex, - void *pVgpuVfioRef + void *pVgpuVfioRef, + NvBool *isBar64bit ) { REQUEST_VGPU_INFO_NODE *pRequestVgpu = NULL; @@ -497,6 +541,16 @@ NV_STATUS NV_API_CALL nv_vgpu_get_bar_info( NV_ENTER_RM_RUNTIME(sp,fp); threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + /* + * This function can be used to query both BAR 64bit state and/or BAR size + * If neither is queried, return with error. + */ + if ((size == NULL) && (isBar64bit == NULL)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto exit; + } + // LOCK: acquire API lock NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_SILENT, rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_HYPERVISOR), exit); @@ -507,6 +561,18 @@ NV_STATUS NV_API_CALL nv_vgpu_get_bar_info( rmStatus = NV_ERR_INVALID_STATE; goto release_lock; } + + /* Get input BAR index 64bit state */ + if (isBar64bit != NULL) + { + NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_SILENT, + is_bar_64bit(pGpu, regionIndex, isBar64bit), release_lock); + + /* Query is only for BAR index 64bit state*/ + if (size == NULL) + goto release_lock; + } + pKernelBus = GPU_GET_KERNEL_BUS(pGpu); *size = kbusGetPciBarSize(pKernelBus, regionIndex); @@ -596,6 +662,71 @@ NV_STATUS NV_API_CALL nv_vgpu_get_bar_info( return rmStatus; } +NV_STATUS NV_API_CALL nv_vgpu_get_hbm_info( + nvidia_stack_t *sp, + nv_state_t *pNv, + const NvU8 *pMdevUuid, + NvU64 *hbmAddr, + NvU64 *size +) +{ + NV_STATUS rmStatus = NV_OK; + THREAD_STATE_NODE threadState; + OBJGPU *pGpu = NULL; + KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice; + void *fp = NULL; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + if ((size == NULL) || (hbmAddr == NULL)) + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto exit; + } + + // LOCK: acquire API lock + NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_SILENT, rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_HYPERVISOR), exit); + + pGpu = NV_GET_NV_PRIV_PGPU(pNv); + if (pGpu == NULL) + { + NV_PRINTF(LEVEL_ERROR, "%s GPU handle is not valid \n", __FUNCTION__); + rmStatus = NV_ERR_INVALID_STATE; + goto release_lock; + } + + NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_SILENT, + kvgpumgrGetHostVgpuDeviceFromMdevUuid(pNv->gpu_id, + pMdevUuid, + &pKernelHostVgpuDevice), release_lock); + if (pKernelHostVgpuDevice->numValidHbmRegions > 1) + { + NV_PRINTF(LEVEL_NOTICE, "non contiguous HBM region is not supported\n"); + NV_ASSERT(0); + } + + if (pKernelHostVgpuDevice->hbmRegionList != NULL) + { + *hbmAddr = pKernelHostVgpuDevice->hbmRegionList[0].hbmBaseAddr; + *size = pKernelHostVgpuDevice->hbmRegionList[0].size; + } + else + { + *hbmAddr = 0; + *size = 0; + } + +release_lock: + // UNLOCK: release API lock + rmapiLockRelease(); +exit: + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + NV_STATUS osVgpuVfioWake( void *waitQueue ) @@ -686,7 +817,7 @@ NV_STATUS NV_API_CALL nv_vgpu_get_sparse_mmap( THREAD_STATE_NODE threadState; NV_STATUS rmStatus = NV_ERR_INVALID_STATE, status; OBJGPU *pGpu = NULL; - POBJTMR pTmr = NULL; + OBJTMR *pTmr = NULL; KernelFifo *pKernelFifo = NULL; void *fp = NULL; REQUEST_VGPU_INFO_NODE *pRequestVgpu = NULL; @@ -1038,7 +1169,7 @@ NV_STATUS rm_is_vgpu_supported_device( ) { OBJSYS *pSys = SYS_GET_INSTANCE(); - POBJHYPERVISOR pHypervisor = SYS_GET_HYPERVISOR(pSys); + OBJHYPERVISOR *pHypervisor = SYS_GET_HYPERVISOR(pSys); NvBool is_sriov_enabled = FLD_TEST_DRF(_PMC, _BOOT_1, _VGPU, _VF, pmc_boot_1); // if not running in vGPU mode (guest VM) return NV_OK diff --git a/src/nvidia/arch/nvalloc/unix/src/os.c b/src/nvidia/arch/nvalloc/unix/src/os.c index a1d7614d16..c994433219 100644 --- a/src/nvidia/arch/nvalloc/unix/src/os.c +++ b/src/nvidia/arch/nvalloc/unix/src/os.c @@ -40,6 +40,8 @@ #include "nverror.h" #include "kernel/gpu/bif/kernel_bif.h" +#include "gpu/mig_mgr/kernel_mig_manager.h" + #include "gpu/mem_sys/kern_mem_sys.h" #include "mem_mgr/io_vaspace.h" @@ -722,11 +724,6 @@ void osDetachFromProcess(void* pProcessInfo) return; } -NvBool osDbgBreakpointEnabled(void) -{ - return NV_TRUE; -} - NV_STATUS osAcquireRmSema(void *pSema) { return NV_OK; @@ -808,15 +805,6 @@ NV_STATUS osQueueWorkItemWithFlags( return status; } -NV_STATUS osQueueWorkItem( - OBJGPU *pGpu, - OSWorkItemFunction pFunction, - void *pParams -) -{ - return osQueueWorkItemWithFlags(pGpu, pFunction, pParams, OS_QUEUE_WORKITEM_FLAGS_NONE); -} - NV_STATUS osQueueSystemWorkItem( OSSystemWorkItemFunction pFunction, void *pParams @@ -909,12 +897,13 @@ NV_STATUS osAllocPagesInternal( MEMORY_DESCRIPTOR *pMemDesc ) { - OBJSYS *pSys = SYS_GET_INSTANCE(); - OBJGPU *pGpu = pMemDesc->pGpu; - nv_state_t *nv = NV_GET_NV_STATE(pGpu); - void *pMemData = NULL; - NV_STATUS status; - NvS32 nodeId = -1; + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPU *pGpu = pMemDesc->pGpu; + nv_state_t *nv = NV_GET_NV_STATE(pGpu); + void *pMemData = NULL; + NV_STATUS status; + NvS32 nodeId = NV0000_CTRL_NO_NUMA_NODE; + NV_ADDRESS_SPACE addrSpace = memdescGetAddressSpace(pMemDesc); memdescSetAddress(pMemDesc, NvP64_NULL); memdescSetMemData(pMemDesc, NULL, NULL); @@ -955,7 +944,11 @@ NV_STATUS osAllocPagesInternal( // unencrypted = memdescGetFlag(pMemDesc, MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY); - if (pMemDesc->_addressSpace == ADDR_EGM) + if (addrSpace == ADDR_SYSMEM) + { + nodeId = memdescGetNumaNode(pMemDesc); + } + else if (addrSpace == ADDR_EGM) { nodeId = GPU_GET_MEMORY_MANAGER(pGpu)->localEgmNodeId; } @@ -966,9 +959,22 @@ NV_STATUS osAllocPagesInternal( } else { + NvU64 pageSize = osGetPageSize(); + + // + // Bug 4270864: Only non-contig EGM memory needs to specify order. Contig memory + // calculates it within nv_alloc_pages. The long term goal is to expand the ability + // to request large page size for all of sysmem. + // + if (memdescIsEgm(pMemDesc) && !memdescGetContiguity(pMemDesc, AT_CPU)) + { + pageSize = memdescGetPageSize(pMemDesc, AT_GPU); + } + status = nv_alloc_pages( NV_GET_NV_STATE(pGpu), NV_RM_PAGES_TO_OS_PAGES(pMemDesc->PageCount), + pageSize, memdescGetContiguity(pMemDesc, AT_CPU), memdescGetCpuCacheAttrib(pMemDesc), pSys->getProperty(pSys, @@ -2018,6 +2024,7 @@ _initializeExportObjectFd RsResourceRef *pResourceRef; Device *pDevice; NvU32 deviceInstance = NV_MAX_DEVICES; + NvU32 gpuInstanceId = NV_U32_MAX; if (nvfp->handles != NULL) { @@ -2026,6 +2033,9 @@ _initializeExportObjectFd if (hDevice != 0) { + OBJGPU *pGpu; + MIG_INSTANCE_REF ref; + status = serverutilGetResourceRef(hClient, hDevice, &pResourceRef); if (status != NV_OK) { @@ -2039,6 +2049,18 @@ _initializeExportObjectFd } deviceInstance = pDevice->deviceInst; + pGpu = GPU_RES_GET_GPU(pDevice); + + if (IS_MIG_IN_USE(pGpu)) + { + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + status = kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + pDevice, &ref); + if (status == NV_OK) + { + gpuInstanceId = ref.pKernelMIGGpuInstance->swizzId; + } + } } NV_ASSERT_OK_OR_RETURN(os_alloc_mem((void **)&nvfp->handles, @@ -2047,8 +2069,9 @@ _initializeExportObjectFd os_mem_set(nvfp->handles, 0, sizeof(nvfp->handles[0]) * maxObjects); - nvfp->maxHandles = maxObjects; - nvfp->deviceInstance = deviceInstance; + nvfp->maxHandles = maxObjects; + nvfp->deviceInstance = deviceInstance; + nvfp->gpuInstanceId = gpuInstanceId; if (metadata != NULL) { @@ -2481,6 +2504,8 @@ cliresCtrlCmdOsUnixGetExportObjectInfo_IMPL pParams->maxObjects = nvfp->maxHandles; pParams->deviceInstance = nvfp->deviceInstance; + pParams->gpuInstanceId = nvfp->gpuInstanceId; + os_mem_copy(pParams->metadata, nvfp->metadata, sizeof(nvfp->metadata)); done: @@ -3877,28 +3902,17 @@ osGetForcedC2CConnection int i, ret; NV_STATUS status; char path[64]; - OBJOS *pOS; - OBJSYS *pSys; NV_ASSERT_OR_RETURN((pLinkConnection != NULL), NV_ERR_INVALID_POINTER); NV_ASSERT_OR_RETURN((maxLinks > 0), NV_ERR_NOT_SUPPORTED); NV_ASSERT_OR_RETURN((pGpu != NULL), NV_ERR_INVALID_ARGUMENT); - pSys = SYS_GET_INSTANCE(); - pOS = SYS_GET_OS(pSys); - if (pOS == NULL || pOS->osSimEscapeRead == NULL) - { - NV_PRINTF(LEVEL_ERROR, "%s: escape reads not supported on platform\n", - __FUNCTION__); - return NV_ERR_NOT_SUPPORTED; - } - for (i = 0; i < maxLinks; i++) { ret = os_snprintf(path, sizeof(path), "CPU_MODEL|CM_ATS_ADDRESS|C2C%u", i); NV_ASSERT((ret > 0) && (ret < (sizeof(path) - 1))); - status = pOS->osSimEscapeRead(pGpu, path, 0, 4, &pLinkConnection[i]); + status = gpuSimEscapeRead(pGpu, path, 0, 4, &pLinkConnection[i]); if (status == NV_OK) { NV_PRINTF(LEVEL_INFO, "%s: %s=0x%X\n", __FUNCTION__, @@ -3906,7 +3920,7 @@ osGetForcedC2CConnection } else { - NV_PRINTF(LEVEL_INFO, "%s: osSimEscapeRead for '%s' failed (%u)\n", + NV_PRINTF(LEVEL_INFO, "%s: gpuSimEscapeRead for '%s' failed (%u)\n", __FUNCTION__, path, status); return NV_ERR_NOT_SUPPORTED; } @@ -5468,14 +5482,6 @@ osDmabufIsSupported(void) return os_dma_buf_enabled; } -void osAllocatedRmClient(void *pOsInfo) -{ - nv_file_private_t* nvfp = (nv_file_private_t*)pOsInfo; - - if (nvfp != NULL) - nvfp->bCleanupRmapi = NV_TRUE; -} - NV_STATUS osGetEgmInfo ( @@ -5502,3 +5508,11 @@ osOfflinePageAtAddress { return os_offline_page_at_address(address); } + +void osAllocatedRmClient(void *pOsInfo) +{ + nv_file_private_t* nvfp = (nv_file_private_t*)pOsInfo; + + if (nvfp != NULL) + nvfp->bCleanupRmapi = NV_TRUE; +} diff --git a/src/nvidia/arch/nvalloc/unix/src/osapi.c b/src/nvidia/arch/nvalloc/unix/src/osapi.c index 4c666d1435..3d88348b36 100644 --- a/src/nvidia/arch/nvalloc/unix/src/osapi.c +++ b/src/nvidia/arch/nvalloc/unix/src/osapi.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -1339,10 +1339,37 @@ RmDmabufVerifyMemHandle( return NV_OK; } +static NV_STATUS +RmDmabufGetParentDevice( + OBJGPU *pGpu, + NvHandle hClient, + NvHandle hMemory, + Device **ppDevice +) +{ + RsClient *pClient; + RsResourceRef *pDeviceRef; + RsResourceRef *pMemoryRef; + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + serverGetClientUnderLock(&g_resServ, hClient, &pClient)); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + clientGetResourceRef(pClient, hMemory, &pMemoryRef)); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + refFindAncestorOfType(pMemoryRef, classId(Device), &pDeviceRef)); + + *ppDevice = dynamicCast(pDeviceRef->pResource, Device); + + return NV_OK; +} + static NV_STATUS RmDmabufGetClientAndDevice( OBJGPU *pGpu, NvHandle hClient, + NvHandle hMemory, NvHandle *phClient, NvHandle *phDevice, NvHandle *phSubdevice, @@ -1355,10 +1382,18 @@ RmDmabufGetClientAndDevice( { NV_STATUS status; MIG_INSTANCE_REF ref; + Device *pParentDevice; KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); - status = kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, - hClient, &ref); + status = RmDmabufGetParentDevice(pGpu, hClient, hMemory, + &pParentDevice); + if (status != NV_OK) + { + return status; + } + + status = kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + pParentDevice, &ref); if (status != NV_OK) { return status; @@ -3067,7 +3102,7 @@ static NV_STATUS RmRunNanoTimerCallback( void *pTmrEvent ) { - POBJTMR pTmr = GPU_GET_TIMER(pGpu); + OBJTMR *pTmr = GPU_GET_TIMER(pGpu); THREAD_STATE_NODE threadState; NV_STATUS status = NV_OK; // LOCK: try to acquire GPUs lock @@ -3285,7 +3320,7 @@ NV_STATUS NV_API_CALL rm_is_supported_device( THREAD_STATE_NODE threadState; NV_STATUS rmStatus; OBJSYS *pSys; - POBJHALMGR pHalMgr; + OBJHALMGR *pHalMgr; GPUHWREG *reg_mapping; NvU32 myHalPublicID; void *fp; @@ -4872,14 +4907,18 @@ rm_gpu_need_4k_page_isolation return nvp->b_4k_page_isolation_required; } +// +// This API updates only the following fields in nv_ioctl_numa_info_t: +// - nid +// - numa_mem_addr +// - numa_mem_size +// - offline_addresses +// +// Rest of the fields should be updated by caller. NV_STATUS NV_API_CALL rm_get_gpu_numa_info( - nvidia_stack_t *sp, - nv_state_t *nv, - NvS32 *pNid, - NvU64 *pNumaMemAddr, - NvU64 *pNumaMemSize, - NvU64 *pOfflineAddresses, - NvU32 *pOfflineAddressesCount + nvidia_stack_t *sp, + nv_state_t *nv, + nv_ioctl_numa_info_t *numa_info ) { NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS *pParams; @@ -4888,14 +4927,12 @@ NV_STATUS NV_API_CALL rm_get_gpu_numa_info( void *fp; NV_STATUS status = NV_OK; - if ((pNid == NULL) || (pNumaMemAddr == NULL) || (pNumaMemSize == NULL)) - { - return NV_ERR_INVALID_ARGUMENT; - } + ct_assert(NV_ARRAY_ELEMENTS(numa_info->offline_addresses.addresses) >= + NV_ARRAY_ELEMENTS(pParams->numaOfflineAddresses)); - if ((pOfflineAddressesCount != NULL) && - ((pOfflineAddresses == NULL) || - (*pOfflineAddressesCount > NV_ARRAY_ELEMENTS(pParams->numaOfflineAddresses)))) + if ((numa_info == NULL) || + (numa_info->offline_addresses.numEntries > + NV_ARRAY_ELEMENTS(pParams->numaOfflineAddresses))) { return NV_ERR_INVALID_ARGUMENT; } @@ -4910,11 +4947,8 @@ NV_STATUS NV_API_CALL rm_get_gpu_numa_info( } portMemSet(pParams, 0, sizeof(*pParams)); - - if (pOfflineAddressesCount != NULL) - { - pParams->numaOfflineAddressesCount = *pOfflineAddressesCount; - } + pParams->numaOfflineAddressesCount = + numa_info->offline_addresses.numEntries; pRmApi = RmUnixRmApiPrologue(nv, &threadState, RM_LOCK_MODULES_MEM); if (pRmApi == NULL) @@ -4933,14 +4967,16 @@ NV_STATUS NV_API_CALL rm_get_gpu_numa_info( { NvU32 i; - *pNid = pParams->numaNodeId; - *pNumaMemAddr = pParams->numaMemAddr; - *pNumaMemSize = pParams->numaMemSize; - *pOfflineAddressesCount = pParams->numaOfflineAddressesCount; + numa_info->nid = pParams->numaNodeId; + numa_info->numa_mem_addr = pParams->numaMemAddr; + numa_info->numa_mem_size = pParams->numaMemSize; + numa_info->offline_addresses.numEntries = + pParams->numaOfflineAddressesCount; for (i = 0; i < pParams->numaOfflineAddressesCount; i++) { - pOfflineAddresses[i] = pParams->numaOfflineAddresses[i]; + numa_info->offline_addresses.addresses[i] = + pParams->numaOfflineAddresses[i]; } } @@ -5126,7 +5162,7 @@ NvBool rm_get_uefi_console_status( nv_state_t *nv ) { - NvU16 fbWidth, fbHeight, fbDepth, fbPitch; + NvU32 fbWidth, fbHeight, fbDepth, fbPitch; NvU64 fbSize; NvU64 fbBaseAddress = 0; NvBool bConsoleDevice = NV_FALSE; @@ -5140,7 +5176,7 @@ NvBool rm_get_uefi_console_status( nv->bars[NV_GPU_BAR_INDEX_FB].cpu_address, nv->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address + 0x1000000); - fbSize = fbHeight * fbPitch; + fbSize = (NvU64)fbHeight * (NvU64)fbPitch; bConsoleDevice = (fbSize != 0); @@ -5152,7 +5188,7 @@ NvU64 rm_get_uefi_console_size( NvU64 *pFbBaseAddress ) { - NvU16 fbWidth, fbHeight, fbDepth, fbPitch; + NvU32 fbWidth, fbHeight, fbDepth, fbPitch; NvU64 fbSize; fbSize = fbWidth = fbHeight = fbDepth = fbPitch = 0; @@ -5166,7 +5202,7 @@ NvU64 rm_get_uefi_console_size( nv->bars[NV_GPU_BAR_INDEX_FB].cpu_address, nv->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address + 0x1000000); - fbSize = fbHeight * fbPitch; + fbSize = (NvU64)fbHeight * (NvU64)fbPitch; return fbSize; } @@ -5545,6 +5581,7 @@ NV_STATUS NV_API_CALL rm_dma_buf_get_client_and_device( nvidia_stack_t *sp, nv_state_t *nv, NvHandle hClient, + NvHandle hMemory, NvHandle *phClient, NvHandle *phDevice, NvHandle *phSubdevice, @@ -5568,7 +5605,8 @@ NV_STATUS NV_API_CALL rm_dma_buf_get_client_and_device( rmStatus = rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI); if (rmStatus == NV_OK) { - rmStatus = RmDmabufGetClientAndDevice(pGpu, hClient, phClient, phDevice, + rmStatus = RmDmabufGetClientAndDevice(pGpu, hClient, hMemory, + phClient, phDevice, phSubdevice, ppGpuInstanceInfo); if (rmStatus == NV_OK) { @@ -5641,7 +5679,7 @@ void NV_API_CALL rm_vgpu_vfio_set_driver_vm( ) { OBJSYS *pSys; - POBJHYPERVISOR pHypervisor; + OBJHYPERVISOR *pHypervisor; void *fp; NV_ENTER_RM_RUNTIME(sp,fp); diff --git a/src/nvidia/arch/nvalloc/unix/src/osinit.c b/src/nvidia/arch/nvalloc/unix/src/osinit.c index 8022c6c347..97bc1d9133 100644 --- a/src/nvidia/arch/nvalloc/unix/src/osinit.c +++ b/src/nvidia/arch/nvalloc/unix/src/osinit.c @@ -841,8 +841,8 @@ RmInitDeviceDma( if (nv->iovaspace_id != NV_IOVA_DOMAIN_NONE) { OBJSYS *pSys = SYS_GET_INSTANCE(); - POBJVMM pVmm = SYS_GET_VMM(pSys); - POBJVASPACE pIOVAS; + OBJVMM *pVmm = SYS_GET_VMM(pSys); + OBJVASPACE *pIOVAS; NV_STATUS status = vmmCreateVaspace(pVmm, IO_VASPACE_A, nv->iovaspace_id, 0, 0ULL, ~0ULL, 0ULL, 0ULL, @@ -865,8 +865,8 @@ RmTeardownDeviceDma( if (nv->iovaspace_id != NV_IOVA_DOMAIN_NONE) { OBJSYS *pSys = SYS_GET_INSTANCE(); - POBJVMM pVmm = SYS_GET_VMM(pSys); - POBJVASPACE pIOVAS; + OBJVMM *pVmm = SYS_GET_VMM(pSys); + OBJVASPACE *pIOVAS; if (NV_OK == vmmGetVaspaceFromId(pVmm, nv->iovaspace_id, IO_VASPACE_A, &pIOVAS)) { @@ -1564,22 +1564,6 @@ NvBool RmInitAdapter( pSys = SYS_GET_INSTANCE(); - // - // WAR: If the below UEFI property is set, display RM will attempt to read - // the state cache during RM init in order to retrieve a snapshot of the - // display state that the UEFI driver has already programmed. On Orin - // (T234D), the UEFI boot flow is being enabled on Linux, but our UEFI - // driver doesn't have any display support right now. As such, our UEFI - // driver won't allocate any of the display channels, which means that RM - // will attempt to read the state cache for uninitialized channels. WAR this - // issue by un-setting the below UEFI property for now. - // - // JIRA task TDS-5094 tracks adding display support to the UEFI driver. - // - if (NV_IS_SOC_DISPLAY_DEVICE(nv)) { - pSys->setProperty(pSys, PDB_PROP_SYS_IS_UEFI, NV_FALSE); - } - // // Get firmware from the OS, if requested, and decide if RM will run as a // firmware client. @@ -1875,38 +1859,6 @@ NvBool RmInitAdapter( } } - { - // OpenRM support for features beyond what is used on Data Center GPUs - // is still fairly immature, so for now require users to opt into use of - // OpenRM with a special registry key, if not on a Data Center GPU. - const GspStaticConfigInfo *pSCI = GPU_GET_GSP_STATIC_INFO(pGpu); - - if (pSCI->computeBranding != COMPUTE_BRANDING_TYPE_TESLA && - ((pGpu->idInfo.PCIDeviceID >> 16) & 0xffff) != NV_PCI_DEVID_DEVICE_PG189_SKU600) - { - NvU32 data = NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS_DEFAULT; - RmReadRegistryDword(nv, NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS, &data); - - if (data == NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS_DISABLE) - { - if (!nv->printed_openrm_enable_unsupported_gpus_error) - { - nv_printf(NV_DBG_ERRORS, - "NVRM: Open nvidia.ko is only ready for use on Data Center GPUs.\n"); - nv_printf(NV_DBG_ERRORS, - "NVRM: To force use of Open nvidia.ko on other GPUs, see the\n"); - nv_printf(NV_DBG_ERRORS, - "NVRM: 'OpenRmEnableUnsupportedGpus' kernel module parameter described\n"); - nv_printf(NV_DBG_ERRORS, - "NVRM: in the README.\n"); - nv->printed_openrm_enable_unsupported_gpus_error = NV_TRUE; - } - RM_SET_ERROR(status, RM_INIT_FIRMWARE_INIT_FAILED); - goto shutdown; - } - } - } - NV_DEV_PRINTF(NV_DBG_SETUP, nv, "RmInitAdapter succeeded!\n"); retVal = NV_TRUE; diff --git a/src/nvidia/arch/nvalloc/unix/src/osmemdesc.c b/src/nvidia/arch/nvalloc/unix/src/osmemdesc.c index db0a43b69c..ca2474fdd5 100644 --- a/src/nvidia/arch/nvalloc/unix/src/osmemdesc.c +++ b/src/nvidia/arch/nvalloc/unix/src/osmemdesc.c @@ -72,7 +72,6 @@ osCreateMemFromOsDescriptor void *pPrivate; pClient = serverutilGetClientUnderLock(hClient); - if ((pDescriptor == NvP64_NULL) || (*pLimit == 0) || (pClient == NULL)) @@ -548,6 +547,7 @@ osCreateOsDescriptorFromPhysAddr ) { NV_STATUS rmStatus; + nv_state_t *nv = NV_GET_NV_STATE(pGpu); MEMORY_DESCRIPTOR *pMemDesc; NvU64 *pPteArray; NvU64 base = 0; @@ -556,6 +556,7 @@ osCreateOsDescriptorFromPhysAddr NvU64 *pPhys_addrs; NvU64 num_os_pages; NvU32 idx; + // Currently only work with contiguous sysmem allocations if (!FLD_TEST_DRF(OS02, _FLAGS, _PHYSICALITY, _CONTIGUOUS, flags)) { @@ -566,6 +567,15 @@ osCreateOsDescriptorFromPhysAddr { // Syncpoint memory is uncached, DMA mapping needs to skip CPU sync. cache_type = NV_MEMORY_UNCACHED; + + // + // Syncpoint memory is NISO. Don't attempt to IOMMU map if the NISO + // IOMMU isn't enabled. + // + if (!NV_SOC_IS_NISO_IOMMU_PRESENT(nv)) + { + memdescFlags |= MEMDESC_FLAGS_SKIP_IOMMU_MAPPING; + } } if (FLD_TEST_DRF(OS02, _FLAGS, _ALLOC_NISO_DISPLAY, _YES, flags)) @@ -597,7 +607,7 @@ osCreateOsDescriptorFromPhysAddr num_os_pages = NV_RM_PAGES_TO_OS_PAGES(pMemDesc->PageCount); pPhys_addrs = portMemAllocNonPaged(sizeof(NvU64) * num_os_pages); if (pPhys_addrs == NULL) - return NV_ERR_NO_MEMORY; + goto cleanup_memdesc; for (idx = 0; idx < num_os_pages; idx++) { @@ -605,20 +615,51 @@ osCreateOsDescriptorFromPhysAddr } *ppPrivate = NULL; - rmStatus = nv_register_phys_pages(NV_GET_NV_STATE(pGpu), pPhys_addrs, - num_os_pages, + rmStatus = nv_register_phys_pages(nv, pPhys_addrs, num_os_pages, memdescGetCpuCacheAttrib(pMemDesc), ppPrivate); if (rmStatus != NV_OK) + goto cleanup_memdesc; + + // + // For syncpoint memory, if IOMMU skip flag wasn't set earlier, + // create IOVA mapping. + // + if (FLD_TEST_DRF(OS02, _FLAGS, _ALLOC_TYPE_SYNCPOINT, _APERTURE, flags) && + !memdescGetFlag(pMemDesc, MEMDESC_FLAGS_SKIP_IOMMU_MAPPING)) { - memdescDestroy(pMemDesc); - goto cleanup; + // + // memdescMapIommu() requires the OS-private data to be set on the memory + // descriptor, but we don't want to wire up the teardown callback just yet: + // that callback needs to unpin the pages, but that will already be done + // as part of failure handling further up the stack if memdescMapIommu() + // fails. So we only set up the priv-data cleanup callback once we're sure + // this call will succeed. + // + memdescSetMemData(pMemDesc, *ppPrivate, NULL); + + rmStatus = memdescMapIommu(pMemDesc, pGpu->busInfo.iovaspaceId); + if (rmStatus != NV_OK) + goto cleanup_pages; } + // All is well - wire up the cleanup callback now memdescSetMemData(pMemDesc, *ppPrivate, osDestroyOsDescriptorFromPhysAddr); -cleanup: + portMemFree(pPhys_addrs); + + return NV_OK; + +cleanup_pages: + if (*ppPrivate != NULL) + { + nv_unregister_phys_pages(NV_GET_NV_STATE(pGpu), *ppPrivate); + } + +cleanup_memdesc: + memdescDestroy(pMemDesc); + portMemFree(pPhys_addrs); return rmStatus; diff --git a/src/nvidia/arch/nvalloc/unix/src/osnvlink.c b/src/nvidia/arch/nvalloc/unix/src/osnvlink.c index b2c17e824d..04c1f4f271 100644 --- a/src/nvidia/arch/nvalloc/unix/src/osnvlink.c +++ b/src/nvidia/arch/nvalloc/unix/src/osnvlink.c @@ -723,28 +723,17 @@ osGetForcedNVLinkConnection int i, ret; NV_STATUS status; char path[64]; - OBJSYS *pSys; - OBJOS *pOS; NV_ASSERT_OR_RETURN((pLinkConnection != NULL), NV_ERR_INVALID_POINTER); NV_ASSERT_OR_RETURN((maxLinks > 0), NV_ERR_NOT_SUPPORTED); NV_ASSERT_OR_RETURN((pGpu != NULL), NV_ERR_INVALID_ARGUMENT); - pSys = SYS_GET_INSTANCE(); - pOS = SYS_GET_OS(pSys); - if (pOS == NULL || pOS->osSimEscapeRead == NULL) - { - NV_PRINTF(LEVEL_ERROR, "%s: escape reads not supported on platform\n", - __FUNCTION__); - return NV_ERR_NOT_SUPPORTED; - } - for (i = 0; i < maxLinks; i++) { ret = os_snprintf(path, sizeof(path), "CPU_MODEL|CM_ATS_ADDRESS|NVLink%u", i); NV_ASSERT((ret > 0) && (ret < (sizeof(path) - 1))); - status = pOS->osSimEscapeRead(pGpu, path, 0, 4, &pLinkConnection[i]); + status = gpuSimEscapeRead(pGpu, path, 0, 4, &pLinkConnection[i]); if (status == NV_OK) { NV_PRINTF(LEVEL_INFO, "%s: %s=0x%X\n", __FUNCTION__, @@ -752,7 +741,7 @@ osGetForcedNVLinkConnection } else { - NV_PRINTF(LEVEL_INFO, "%s: osSimEscapeRead for '%s' failed (%u)\n", + NV_PRINTF(LEVEL_INFO, "%s: gpuSimEscapeRead for '%s' failed (%u)\n", __FUNCTION__, path, status); return NV_ERR_NOT_SUPPORTED; } diff --git a/src/nvidia/arch/nvalloc/unix/src/osunix.c b/src/nvidia/arch/nvalloc/unix/src/osunix.c index cc4502224a..db7e4f6928 100644 --- a/src/nvidia/arch/nvalloc/unix/src/osunix.c +++ b/src/nvidia/arch/nvalloc/unix/src/osunix.c @@ -53,9 +53,6 @@ initOSSpecificFunctionPointers(OBJOS *pOS) static void initMiscOSFunctionPointers(OBJOS *pOS) { - pOS->osQueueWorkItem = osQueueWorkItem; - pOS->osQueueWorkItemWithFlags = osQueueWorkItemWithFlags; - pOS->osQueueSystemWorkItem = osQueueSystemWorkItem; } static void @@ -65,8 +62,6 @@ initUnixOSFunctionPointers(OBJOS *pOS) pOS->osNv_rdcr4 = nv_rdcr4; pOS->osNv_cpuid = nv_cpuid; #endif - - pOS->osDbgBreakpointEnabled = osDbgBreakpointEnabled; } static void diff --git a/src/nvidia/arch/nvalloc/unix/src/rmobjexportimport.c b/src/nvidia/arch/nvalloc/unix/src/rmobjexportimport.c index 10be0f8de3..725d123021 100644 --- a/src/nvidia/arch/nvalloc/unix/src/rmobjexportimport.c +++ b/src/nvidia/arch/nvalloc/unix/src/rmobjexportimport.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2016-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2016-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -48,6 +48,9 @@ #include "rmobjexportimport.h" #include "nvlimits.h" #include "gpu/device/device.h" +#include "gpu/subdevice/subdevice.h" +#include "gpu/mig_mgr/kernel_mig_manager.h" +#include "gpu/mig_mgr/gpu_instance_subscription.h" #include "containers/map.h" #include "rmapi/rmapi.h" @@ -62,11 +65,7 @@ // A reference to an RmObjExportHandle // generated by function RmGenerateObjExportHandle(). // -typedef struct -{ - NvU32 deviceInstance; -} RmObjExportHandleRef; -MAKE_MAP(RmObjExportHandleMap, RmObjExportHandleRef); +MAKE_MAP(RmObjExportHandleMap, NvU8); // // Memory allocator @@ -99,9 +98,11 @@ typedef struct { NvHandle hRmDevice; NvHandle hRmSubDevice; + NvHandle hGpuInstSub; } RmObjExportDevice; +MAKE_MAP(RmObjExportDeviceMap, RmObjExportDevice); -RmObjExportDevice objExportDevice[NV_MAX_DEVICES]; +RmObjExportDeviceMap objExportDeviceMap; // // Usage reference counter for static object in this file like rm client used to @@ -115,7 +116,7 @@ NvU64 objExportImportRefCount; static NV_STATUS RmRefObjExportImport (void); static void RmUnrefObjExportImport (void); -static RmObjExportHandle RmGenerateObjExportHandle (NvU32 deviceInstance); +static RmObjExportHandle RmGenerateObjExportHandle (void); static NV_STATUS RmUnrefObjExportHandle (RmObjExportHandle hObject); // @@ -125,9 +126,7 @@ static NV_STATUS RmUnrefObjExportHandle(RmObjExportHandle hObject) { RM_API *pRmApi = rmapiGetInterface(RMAPI_API_LOCK_INTERNAL); - RmObjExportHandleRef *pHandleRef = - mapFind(&objExportHandleMap, hObject); - + void *pHandleRef = mapFind(&objExportHandleMap, hObject); if (pHandleRef == NULL) { return NV_ERR_OBJECT_NOT_FOUND; @@ -150,7 +149,7 @@ static NV_STATUS RmUnrefObjExportHandle(RmObjExportHandle hObject) // // Generate unique RmObjExportHandle. // -static RmObjExportHandle RmGenerateObjExportHandle(NvU32 deviceInstance) +static RmObjExportHandle RmGenerateObjExportHandle(void) { // // The object export handle belongs to range of 0 to @@ -168,7 +167,7 @@ static RmObjExportHandle RmGenerateObjExportHandle(NvU32 deviceInstance) do { - RmObjExportHandleRef *pHandleRef; + void *pHandleRef; hObject = hObjExportHandleNext++; /* Reset hObjExportHandleNext to next valid handle */ @@ -191,14 +190,9 @@ static RmObjExportHandle RmGenerateObjExportHandle(NvU32 deviceInstance) if (hObject != 0) { - RmObjExportHandleRef *pHandleRef = - mapInsertNew(&objExportHandleMap, hObject); + void *pHandleRef = mapInsertNew(&objExportHandleMap, hObject); - if (pHandleRef != NULL) - { - pHandleRef->deviceInstance = deviceInstance; - } - else + if (pHandleRef == NULL) { hObject = 0; } @@ -215,7 +209,7 @@ static RmObjExportHandle RmGenerateObjExportHandle(NvU32 deviceInstance) // static NvBool RmValidateHandleAgainstInternalHandles(RmObjExportHandle hObject) { - NvU32 i; + RmObjExportDeviceMapIter iter; // // No external RmObjExportHandle could be valid if hObjExportRmClient has @@ -228,11 +222,15 @@ static NvBool RmValidateHandleAgainstInternalHandles(RmObjExportHandle hObject) return NV_FALSE; } - for (i = 0; i < NV_ARRAY_ELEMENTS(objExportDevice); i++) + iter = mapIterAll(&objExportDeviceMap); + while (mapIterNext(&iter)) { - if (objExportDevice[i].hRmDevice != 0 && - (hObject == objExportDevice[i].hRmDevice || - hObject == objExportDevice[i].hRmSubDevice)) + RmObjExportDevice *pRmObjExportDevice = iter.pValue; + + if (pRmObjExportDevice->hRmDevice != 0 && + (hObject == pRmObjExportDevice->hRmDevice || + hObject == pRmObjExportDevice->hRmSubDevice || + hObject == pRmObjExportDevice->hGpuInstSub)) { return NV_FALSE; } @@ -280,6 +278,7 @@ static NV_STATUS RmRefObjExportImport(void) } mapInit(&objExportHandleMap, pMemAllocator); + mapInit(&objExportDeviceMap, pMemAllocator); return NV_OK; @@ -296,7 +295,7 @@ static NV_STATUS RmRefObjExportImport(void) // static void RmUnrefObjExportImport(void) { - RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + RM_API *pRmApi = rmapiGetInterface(RMAPI_API_LOCK_INTERNAL); if ((--objExportImportRefCount) != 0) { @@ -305,19 +304,7 @@ static void RmUnrefObjExportImport(void) if (pMemAllocator != NULL) { - NvU32 i; - - for (i = 0; i < NV_ARRAY_ELEMENTS(objExportDevice); i++) - { - if (objExportDevice[i].hRmDevice != 0) - { - RmUnrefObjExportHandle(objExportDevice[i].hRmSubDevice); - objExportDevice[i].hRmSubDevice = 0; - RmUnrefObjExportHandle(objExportDevice[i].hRmDevice); - objExportDevice[i].hRmDevice = 0; - } - } - + mapDestroy(&objExportDeviceMap); mapDestroy(&objExportHandleMap); portMemAllocatorRelease(pMemAllocator); @@ -338,12 +325,16 @@ static void RmUnrefObjExportImport(void) NV_STATUS RmExportObject(NvHandle hSrcClient, NvHandle hSrcObject, RmObjExportHandle *pDstObject, NvU32 *pDeviceInstance) { - RmObjExportHandle hDstObject; - NvU32 deviceInstance = NV_MAX_DEVICES; - NvHandle hTmpObject; - NvBool bClientAsDstParent = NV_FALSE; - NV_STATUS status; - RM_API *pRmApi = rmapiGetInterface(RMAPI_API_LOCK_INTERNAL); + RmObjExportHandle hDstObject; + NvU32 deviceInstance = NV_MAX_DEVICES; + NvBool bClientAsDstParent = NV_FALSE; + NV_STATUS status; + RM_API *pRmApi = rmapiGetInterface(RMAPI_API_LOCK_INTERNAL); + MIG_INSTANCE_REF ref = kmigmgrMakeNoMIGReference(); + NvU64 deviceMapIdx; + RmObjExportDevice *pObjExportDevice; + RsResourceRef *pSrcResourceRef; + RsResourceRef *pDeviceRef; if (pDstObject == NULL) { @@ -353,27 +344,33 @@ NV_STATUS RmExportObject(NvHandle hSrcClient, NvHandle hSrcObject, // // Find the device instance on which the rm object exists. // - hTmpObject = hSrcObject; - do - { - RsResourceRef *pResourceRef; + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + serverutilGetResourceRef(hSrcClient, hSrcObject, &pSrcResourceRef)); - status = serverutilGetResourceRef(hSrcClient, hTmpObject, &pResourceRef); - if (status != NV_OK) - return status; + status = refFindAncestorOfType(pSrcResourceRef, classId(Device), &pDeviceRef); + if (status == NV_OK) + { + Device *pDevice = dynamicCast(pDeviceRef->pResource, Device); + OBJGPU *pGpu = GPU_RES_GET_GPU(pDevice); + NvU64 swizzId = KMIGMGR_MAX_GPU_SWIZZID; - Device *pDevice = dynamicCast(pResourceRef->pResource, Device); - if (pDevice != NULL) + if (IS_MIG_IN_USE(pGpu)) { - deviceInstance = pDevice->deviceInst; - break; - } + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); - hTmpObject = pResourceRef->pParentRef ? pResourceRef->pParentRef->hResource : 0; - } while (hTmpObject != 0); + status = kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + pDevice, &ref); + if (status == NV_OK) + { + swizzId = ref.pKernelMIGGpuInstance->swizzId; + } + } - // If a memory object is not parented by a device, use client as a parent. - if ((hTmpObject == 0) || (deviceInstance >= NV_MAX_DEVICES)) + deviceMapIdx = pDevice->deviceInst | (swizzId << 32); + deviceInstance = pDevice->deviceInst; + pObjExportDevice = mapFind(&objExportDeviceMap, deviceMapIdx); + } + else { bClientAsDstParent = NV_TRUE; } @@ -386,9 +383,9 @@ NV_STATUS RmExportObject(NvHandle hSrcClient, NvHandle hSrcObject, } if (!bClientAsDstParent && - ((objExportDevice[deviceInstance].hRmDevice == 0) || + ((pObjExportDevice == NULL) || serverutilValidateNewResourceHandle(hObjExportRmClient, - objExportDevice[deviceInstance].hRmDevice))) + pObjExportDevice->hRmDevice))) { // // Device object has not been created or it got destroyed in the @@ -398,21 +395,22 @@ NV_STATUS RmExportObject(NvHandle hSrcClient, NvHandle hSrcObject, NV0080_ALLOC_PARAMETERS params; NV2080_ALLOC_PARAMETERS subdevParams; - if (objExportDevice[deviceInstance].hRmDevice == 0) + if (pObjExportDevice == NULL) { - NV_ASSERT(objExportDevice[deviceInstance].hRmSubDevice == 0); + pObjExportDevice = mapInsertNew(&objExportDeviceMap, deviceMapIdx); - objExportDevice[deviceInstance].hRmDevice = - RmGenerateObjExportHandle(deviceInstance); - objExportDevice[deviceInstance].hRmSubDevice = - RmGenerateObjExportHandle(deviceInstance); + pObjExportDevice->hRmDevice = RmGenerateObjExportHandle(); + pObjExportDevice->hRmSubDevice = RmGenerateObjExportHandle(); + pObjExportDevice->hGpuInstSub = NV01_NULL_OBJECT; - if (objExportDevice[deviceInstance].hRmDevice == 0 || - objExportDevice[deviceInstance].hRmSubDevice == 0) + if (pObjExportDevice->hRmDevice == 0 || + pObjExportDevice->hRmSubDevice == 0) { NV_PRINTF(LEVEL_ERROR, "Failed to allocate object handles in %s\n", __FUNCTION__); + mapRemove(&objExportDeviceMap, pObjExportDevice); + status = NV_ERR_NO_MEMORY; goto done; } @@ -421,11 +419,12 @@ NV_STATUS RmExportObject(NvHandle hSrcClient, NvHandle hSrcObject, portMemSet(¶ms, 0, sizeof(NV0080_ALLOC_PARAMETERS)); params.deviceId = deviceInstance; + params.hClientShare = hObjExportRmClient; status = pRmApi->AllocWithHandle(pRmApi, hObjExportRmClient, hObjExportRmClient, - objExportDevice[deviceInstance].hRmDevice, + pObjExportDevice->hRmDevice, NV01_DEVICE_0, ¶ms, sizeof(params)); @@ -442,8 +441,8 @@ NV_STATUS RmExportObject(NvHandle hSrcClient, NvHandle hSrcObject, status = pRmApi->AllocWithHandle(pRmApi, hObjExportRmClient, - objExportDevice[deviceInstance].hRmDevice, - objExportDevice[deviceInstance].hRmSubDevice, + pObjExportDevice->hRmDevice, + pObjExportDevice->hRmSubDevice, NV20_SUBDEVICE_0, &subdevParams, sizeof(subdevParams)); @@ -453,12 +452,41 @@ NV_STATUS RmExportObject(NvHandle hSrcClient, NvHandle hSrcObject, __FUNCTION__); (void) pRmApi->Free(pRmApi, hObjExportRmClient, - objExportDevice[deviceInstance].hRmDevice); + pObjExportDevice->hRmDevice); goto done; } + + // Allocate MIG subscription, if needed + if ((ref.pKernelMIGGpuInstance != NULL) && + (ref.pKernelMIGGpuInstance->swizzId < KMIGMGR_MAX_GPU_SWIZZID)) + { + NVC637_ALLOCATION_PARAMETERS giSubAllocParams; + + portMemSet(&giSubAllocParams, 0, sizeof(giSubAllocParams)); + giSubAllocParams.swizzId = ref.pKernelMIGGpuInstance->swizzId; + + pObjExportDevice->hGpuInstSub = RmGenerateObjExportHandle(); + + status = pRmApi->AllocWithHandle(pRmApi, + hObjExportRmClient, + pObjExportDevice->hRmSubDevice, + pObjExportDevice->hGpuInstSub, + AMPERE_SMC_PARTITION_REF, + &giSubAllocParams, + sizeof(giSubAllocParams)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Unable to alloc gpu instance subscription in %s\n", + __FUNCTION__); + + (void) pRmApi->Free(pRmApi, hObjExportRmClient, + pObjExportDevice->hRmDevice); + goto done; + } + } } - hDstObject = RmGenerateObjExportHandle(deviceInstance); + hDstObject = RmGenerateObjExportHandle(); if (hDstObject == 0) { @@ -472,7 +500,7 @@ NV_STATUS RmExportObject(NvHandle hSrcClient, NvHandle hSrcObject, status = pRmApi->DupObject(pRmApi, hObjExportRmClient, bClientAsDstParent ? hObjExportRmClient : - objExportDevice[deviceInstance].hRmDevice, + pObjExportDevice->hRmDevice, &hDstObject, hSrcClient, hSrcObject, @@ -488,7 +516,7 @@ NV_STATUS RmExportObject(NvHandle hSrcClient, NvHandle hSrcObject, status = pRmApi->DupObject(pRmApi, hObjExportRmClient, - objExportDevice[deviceInstance].hRmSubDevice, + pObjExportDevice->hRmSubDevice, &hDstObject, hSrcClient, hSrcObject, @@ -565,7 +593,12 @@ NV_STATUS RmImportObject(NvHandle hDstClient, NvHandle hDstParent, if (pObjectType != NULL) { params.hObject = hSrcObject; - params.mapFlags = 0; + // + // rmApiGetEffectiveAddrSpace expect mapping flags to be set as DIRECT for + // GPU cacheable Sysmem for Pre-Ampere chips. We are not doing any mapping + // here, so passing this as workaround to get the expected address space. + // + params.mapFlags = FLD_SET_DRF(OS33, _FLAGS, _MAPPING, _DIRECT, 0); params.addrSpaceType = \ NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE_INVALID; @@ -616,22 +649,3 @@ NV_STATUS RmImportObject(NvHandle hDstClient, NvHandle hDstParent, return NV_OK; } - -NV_STATUS RmGetExportObjectInfo(RmObjExportHandle hSrcObject, NvU32 *deviceInstance) -{ - RmObjExportHandleRef *pHandleRef = NULL; - - if (!RmValidateHandleAgainstInternalHandles(hSrcObject)) - { - return NV_ERR_INVALID_ARGUMENT; - } - - pHandleRef = mapFind(&objExportHandleMap, hSrcObject); - if (pHandleRef == NULL) - { - return NV_ERR_OBJECT_NOT_FOUND; - } - - *deviceInstance = pHandleRef->deviceInstance; - return NV_OK; -} diff --git a/src/nvidia/arch/nvalloc/unix/src/unix_console.c b/src/nvidia/arch/nvalloc/unix/src/unix_console.c index 271769ed3f..91cd331c69 100644 --- a/src/nvidia/arch/nvalloc/unix/src/unix_console.c +++ b/src/nvidia/arch/nvalloc/unix/src/unix_console.c @@ -337,6 +337,7 @@ NV_STATUS deviceCtrlCmdOsUnixVTGetFBInfo_IMPL if ((memmgrGetReservedConsoleMemDesc(pGpu, pMemoryManager) != NULL) && bContinue) { NvU64 baseAddr; + NvU32 width, height, depth, pitch; // There should only be one. NV_ASSERT(pParams->width == 0); @@ -344,12 +345,15 @@ NV_STATUS deviceCtrlCmdOsUnixVTGetFBInfo_IMPL pParams->subDeviceInstance = gpumgrGetSubDeviceInstanceFromGpu(pGpu); // Console is either mapped to BAR1 or BAR2 + 16 MB - os_get_screen_info(&baseAddr, &pParams->width, - &pParams->height, &pParams->depth, - &pParams->pitch, + os_get_screen_info(&baseAddr, &width, &height, &depth, &pitch, nv->bars[NV_GPU_BAR_INDEX_FB].cpu_address, nv->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address + 0x1000000); + pParams->width = (NvU16)width; + pParams->height = (NvU16)height; + pParams->depth = (NvU16)depth; + pParams->pitch = (NvU16)pitch; + if (baseAddr != 0) { bContinue = NV_FALSE; diff --git a/src/nvidia/arch/nvalloc/unix/src/unix_intr.c b/src/nvidia/arch/nvalloc/unix/src/unix_intr.c index 56a2103cb1..11f58efd98 100644 --- a/src/nvidia/arch/nvalloc/unix/src/unix_intr.c +++ b/src/nvidia/arch/nvalloc/unix/src/unix_intr.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -41,7 +41,7 @@ static NvBool osInterruptPending( THREAD_STATE_NODE *pThreadState ) { - POBJDISP pDisp; + OBJDISP *pDisp; KernelDisplay *pKernelDisplay; NvBool pending, sema_release; THREAD_STATE_NODE threadState; @@ -128,7 +128,7 @@ static NvBool osInterruptPending( } intrGetPendingStall_HAL(pGpu, pIntr, &intr0Pending, &threadState); - POBJTMR pTmr = GPU_GET_TIMER(pGpu); + OBJTMR *pTmr = GPU_GET_TIMER(pGpu); *serviced = tmrServiceSwrlWrapper(pGpu, pTmr, &intr0Pending, &threadState); } } @@ -338,18 +338,11 @@ void osEnableInterrupts(OBJGPU *pGpu) intrEn = intrGetIntrEn(pIntr); intrSetIntrEnInHw_HAL(pGpu, pIntr, intrEn, NULL); - - if (pIntr != NULL) - { - intrSetStall_HAL(pGpu, pIntr, intrEn, NULL); - } + intrSetStall_HAL(pGpu, pIntr, intrEn, NULL); if (pGpu->getProperty(pGpu, PDB_PROP_GPU_ALTERNATE_TREE_ENABLED)) { - if (pIntr != NULL) - { - intrRestoreNonStall_HAL(pGpu, pIntr, intrGetIntrEn(pIntr), NULL); - } + intrRestoreNonStall_HAL(pGpu, pIntr, intrGetIntrEn(pIntr), NULL); } } @@ -373,23 +366,17 @@ void osDisableInterrupts( intrSetIntrEnInHw_HAL(pGpu, pIntr, new_intr_en_0, NULL); - if (pIntr != NULL) - { - intrSetStall_HAL(pGpu, pIntr, new_intr_en_0, NULL); - } + intrSetStall_HAL(pGpu, pIntr, new_intr_en_0, NULL); if (pGpu->getProperty(pGpu, PDB_PROP_GPU_ALTERNATE_TREE_ENABLED)) { - if (pIntr != NULL) + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_ALTERNATE_TREE_HANDLE_LOCKLESS)) { - if (pGpu->getProperty(pGpu, PDB_PROP_GPU_ALTERNATE_TREE_HANDLE_LOCKLESS)) - { - intrRestoreNonStall_HAL(pGpu, pIntr, intrGetIntrEn(pIntr), NULL); - } - else - { - intrRestoreNonStall_HAL(pGpu, pIntr, new_intr_en_0, NULL); - } + intrRestoreNonStall_HAL(pGpu, pIntr, intrGetIntrEn(pIntr), NULL); + } + else + { + intrRestoreNonStall_HAL(pGpu, pIntr, new_intr_en_0, NULL); } } } @@ -405,7 +392,7 @@ static void RmIsrBottomHalf( NvU32 gpuMask, gpuInstance; OBJGPU *pDeviceLockGpu = pGpu; Intr *pIntr = NULL; - POBJDISP pDisp = NULL; + OBJDISP *pDisp = NULL; NvU8 stackAllocator[TLS_ISR_ALLOCATOR_SIZE]; // ISR allocations come from this buffer PORT_MEM_ALLOCATOR *pIsrAllocator; diff --git a/src/nvidia/arch/nvalloc/unix/x86emu/prim_ops.c b/src/nvidia/arch/nvalloc/unix/x86emu/prim_ops.c index 4740072230..27c19484b5 100644 --- a/src/nvidia/arch/nvalloc/unix/x86emu/prim_ops.c +++ b/src/nvidia/arch/nvalloc/unix/x86emu/prim_ops.c @@ -1794,20 +1794,20 @@ u8 sbb_byte(u8 d, u8 s) register u32 res; /* all operands in native machine order */ register u32 bc; - if (ACCESS_FLAG(F_CF)) - res = d - s - 1; - else - res = d - s; - CONDITIONAL_SET_FLAG(res & 0x80, F_SF); - CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + if (ACCESS_FLAG(F_CF)) + res = d - s - 1; + else + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - /* calculate the borrow chain. See note at top */ - bc = (res & (~d | s)) | (~d & s); - CONDITIONAL_SET_FLAG(bc & 0x80, F_CF); - CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF); - CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); - return (u8)res; + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x80, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return (u8)res; } /**************************************************************************** @@ -1819,20 +1819,20 @@ u16 sbb_word(u16 d, u16 s) register u32 res; /* all operands in native machine order */ register u32 bc; - if (ACCESS_FLAG(F_CF)) + if (ACCESS_FLAG(F_CF)) res = d - s - 1; else res = d - s; - CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); - CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - /* calculate the borrow chain. See note at top */ - bc = (res & (~d | s)) | (~d & s); - CONDITIONAL_SET_FLAG(bc & 0x8000, F_CF); - CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF); - CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); - return (u16)res; + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x8000, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return (u16)res; } /**************************************************************************** @@ -1841,23 +1841,23 @@ Implements the SBB instruction and side effects. ****************************************************************************/ u32 sbb_long(u32 d, u32 s) { - register u32 res; /* all operands in native machine order */ - register u32 bc; + register u32 res; /* all operands in native machine order */ + register u32 bc; - if (ACCESS_FLAG(F_CF)) + if (ACCESS_FLAG(F_CF)) res = d - s - 1; else res = d - s; - CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); - CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - /* calculate the borrow chain. See note at top */ - bc = (res & (~d | s)) | (~d & s); - CONDITIONAL_SET_FLAG(bc & 0x80000000, F_CF); - CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF); - CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); - return res; + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x80000000, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return res; } /**************************************************************************** diff --git a/src/nvidia/exports_link_command.txt b/src/nvidia/exports_link_command.txt index 182b732394..14b4780c3e 100644 --- a/src/nvidia/exports_link_command.txt +++ b/src/nvidia/exports_link_command.txt @@ -180,6 +180,7 @@ --undefined=nv_vgpu_create_request --undefined=nv_vgpu_delete --undefined=nv_vgpu_get_bar_info +--undefined=nv_vgpu_get_hbm_info --undefined=nv_vgpu_start --undefined=nv_vgpu_get_type_ids --undefined=nv_vgpu_get_type_info diff --git a/src/nvidia/generated/g_access_cntr_buffer_nvoc.h b/src/nvidia/generated/g_access_cntr_buffer_nvoc.h index 5670473f87..db2fe7a185 100644 --- a/src/nvidia/generated/g_access_cntr_buffer_nvoc.h +++ b/src/nvidia/generated/g_access_cntr_buffer_nvoc.h @@ -371,4 +371,5 @@ void accesscntrDestruct_IMPL(struct AccessCounterBuffer *pAccessCounterBuffer); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_ACCESS_CNTR_BUFFER_NVOC_H_ diff --git a/src/nvidia/generated/g_allclasses.h b/src/nvidia/generated/g_allclasses.h index 1ab9f5c3c2..65c1d132fe 100644 --- a/src/nvidia/generated/g_allclasses.h +++ b/src/nvidia/generated/g_allclasses.h @@ -116,6 +116,7 @@ #include // MAXWELL_PROFILER #include // MAXWELL_PROFILER_DEVICE #include // GF100_SUBDEVICE_MASTER +#include // GF100_SUBDEVICE_INFOROM #include // GF100_ZBC_CLEAR #include // GF100_DISP_SW #include // GF100_TIMED_SEMAPHORE_SW @@ -585,6 +586,10 @@ #define GF100_SUBDEVICE_MASTER (0x000090e6) #endif +#ifndef GF100_SUBDEVICE_INFOROM +#define GF100_SUBDEVICE_INFOROM (0x000090e7) +#endif + #ifndef GF100_ZBC_CLEAR #define GF100_ZBC_CLEAR (0x00009096) #endif diff --git a/src/nvidia/generated/g_binary_api_nvoc.h b/src/nvidia/generated/g_binary_api_nvoc.h index 44fa969823..ba9862968b 100644 --- a/src/nvidia/generated/g_binary_api_nvoc.h +++ b/src/nvidia/generated/g_binary_api_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -451,4 +451,5 @@ NV_STATUS binapiprivConstruct_IMPL(struct BinaryApiPrivileged *arg_pResource, st #ifdef __cplusplus } // extern "C" #endif + #endif // _G_BINARY_API_NVOC_H_ diff --git a/src/nvidia/generated/g_bindata.c b/src/nvidia/generated/g_bindata.c index 05337d9358..c41aac3e86 100644 --- a/src/nvidia/generated/g_bindata.c +++ b/src/nvidia/generated/g_bindata.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2016-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -35,6 +35,8 @@ // headers. TODO: consider sharing a list of forward struct declarations with // e.g. eng_desc.h? // + +struct KernelPmu; struct KernelGsp; struct KernelSec2; diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_AD102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_AD102.c index b783298ead..1474fbb910 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_AD102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_AD102.c @@ -34,1906 +34,2016 @@ // VAR NAME: booter_ucode_data_ad10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 55040 -// COMPRESSED SIZE (bytes): 30314 +// DATA SIZE (bytes): 56832 +// COMPRESSED SIZE (bytes): 32065 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_AD102_image_dbg_data[] = { - 0xed, 0xfd, 0x73, 0xac, 0x35, 0x41, 0xff, 0x00, 0x78, 0x5e, 0xdb, 0xb6, 0x6d, 0x1b, 0xcf, 0xb5, - 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0x7e, 0xae, 0x6d, 0xdb, 0xbe, 0x77, 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0xdf, 0xe5, + 0x33, 0xfe, 0x17, 0x99, 0xff, 0x0b, 0xf1, 0xff, 0x85, 0xc4, 0xff, 0x42, 0xf2, 0x7f, 0x21, 0xf5, + 0x7f, 0x79, 0x4f, 0xe6, 0xff, 0x92, 0xca, 0xfe, 0xa7, 0x1e, 0x85, 0xff, 0x6b, 0x3d, 0xba, 0xff, + 0x97, 0xef, 0x00, 0xe0, 0x7f, 0xbb, 0x18, 0x40, 0x59, 0x94, 0x01, 0x40, 0xf8, 0x7f, 0xbb, 0xd7, + 0xd0, 0xc9, 0xd2, 0xc5, 0xc2, 0xd6, 0xd4, 0xc5, 0xd2, 0x98, 0xc0, 0xd4, 0xc9, 0xc9, 0xde, 0x09, + 0xea, 0xff, 0xc9, 0xd2, 0xff, 0xdf, 0xf5, 0x7f, 0x00, 0xcc, 0xd0, 0xd2, 0x32, 0x00, 0xde, 0x00, + 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1943,8 +2053,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_AD102_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 55040, // uncompressed data size (bytes) - 30314, // compressed data size (bytes) + 56832, // uncompressed data size (bytes) + 32065, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_AD102_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1966,8 +2076,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_AD102_image_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_AD102_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x2e, 0x07, 0xe2, 0x04, 0x08, 0x13, 0x4c, 0x94, 0x41, 0x69, - 0x20, 0x00, 0x00, 0x6a, 0x2c, 0xe9, 0x9d, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0xae, 0x03, 0xe2, 0x04, 0x08, 0x13, 0x4c, 0xd4, 0x42, 0x69, + 0x20, 0x00, 0x00, 0xe5, 0x66, 0xc6, 0x12, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1995,1906 +2105,2016 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_AD102_header_dbg_storage_pvt; // VAR NAME: booter_ucode_data_ad10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 55040 -// COMPRESSED SIZE (bytes): 30315 +// DATA SIZE (bytes): 56832 +// COMPRESSED SIZE (bytes): 32067 // static BINDATA_CONST NvU8 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0xfe, 0x2f, 0xd0, 0xfe, 0x0b, 0x82, 0xff, 0xc2, 0xe5, 0xbf, 0x32, + 0xf8, 0xff, 0x8f, 0x65, 0xfd, 0x97, 0x06, 0x02, 0xfc, 0x7f, 0xbc, 0x3d, 0xe5, 0xff, 0x1b, 0x65, + 0xa1, 0x02, 0xfc, 0x9f, 0xdf, 0x7f, 0xf4, 0xff, 0x5d, 0x39, 0x20, 0x10, 0xff, 0xcf, 0xb7, 0x4f, + 0xfd, 0xbf, 0x4b, 0xa7, 0xfd, 0x17, 0xe9, 0xff, 0x85, 0xd8, 0x7f, 0x21, 0xfe, 0x5f, 0x48, 0xfc, + 0x17, 0x92, 0xff, 0x97, 0xe7, 0xa4, 0xff, 0x2f, 0x4b, 0x99, 0xff, 0x29, 0x47, 0xfe, 0xff, 0x5a, + 0x8e, 0xce, 0xff, 0xe5, 0x3b, 0x00, 0xf8, 0x6f, 0x17, 0x03, 0x28, 0x89, 0xd0, 0x03, 0x08, 0xfd, + 0xb7, 0x7b, 0x0d, 0x1c, 0x2d, 0x9c, 0xcd, 0x6d, 0x4c, 0x9c, 0x2d, 0x8c, 0xf0, 0x4d, 0x1c, 0x1d, + 0xed, 0x1c, 0xff, 0xfc, 0x3f, 0x59, 0xfb, 0xff, 0xbb, 0xfe, 0x0f, 0x76, 0x9e, 0x61, 0x50, 0x00, + 0xde, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3904,8 +4124,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_AD102_image_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 55040, // uncompressed data size (bytes) - 30315, // compressed data size (bytes) + 56832, // uncompressed data size (bytes) + 32067, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_AD102_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -3927,8 +4147,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_AD102_image_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_AD102_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x2e, 0x07, 0xe2, 0x04, 0x08, 0x13, 0x4c, 0x94, 0x41, 0x69, - 0x20, 0x00, 0x00, 0x6a, 0x2c, 0xe9, 0x9d, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0xae, 0x03, 0xe2, 0x04, 0x08, 0x13, 0x4c, 0xd4, 0x42, 0x69, + 0x20, 0x00, 0x00, 0xe5, 0x66, 0xc6, 0x12, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3954,62 +4174,61 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_AD102_header_prod_storage_pvt; // FILE NAME: kernel/inc/gsprm/bin/booter/ad10x/load/g_booteruc_load_ad10x_ad10x_rsa3k_0_sig.h // FILE TYPE: TEXT // VAR NAME: booter_load_sig_dbg_ad10x -// COMPRESSION: YES +// COMPRESSION: NO // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 768 -// COMPRESSED SIZE (bytes): 781 +// COMPRESSED SIZE (bytes): N/A // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_AD102_sig_dbg_data[] = { - 0x01, 0x00, 0x03, 0xff, 0xfc, 0xfe, 0x4d, 0x6f, 0xf3, 0xe8, 0x7e, 0x53, 0x08, 0xf5, 0x33, 0x57, - 0x27, 0x5e, 0x73, 0xbd, 0xaa, 0x87, 0xc7, 0xba, 0x9a, 0xfa, 0xdc, 0x2a, 0xa1, 0x11, 0x64, 0xbb, - 0x98, 0x72, 0x5f, 0x5e, 0x57, 0x04, 0xc8, 0x50, 0x34, 0x6e, 0x6b, 0x3c, 0x2c, 0x3c, 0x5a, 0x3f, - 0xd5, 0xf4, 0x7d, 0xc9, 0x94, 0x60, 0xb4, 0x8e, 0xbe, 0xcd, 0x9b, 0x1a, 0x19, 0x26, 0x38, 0xff, - 0x7e, 0xfc, 0x52, 0x64, 0xf4, 0x08, 0x07, 0xaa, 0xda, 0x3c, 0xbe, 0x7b, 0x8d, 0x1d, 0x4a, 0xc9, - 0xc1, 0x46, 0x2f, 0xf0, 0xcf, 0x35, 0x87, 0xbf, 0xbc, 0x09, 0xe8, 0x5f, 0x42, 0xb1, 0x00, 0x1f, - 0xc9, 0x7f, 0x83, 0xcb, 0xf4, 0x5c, 0xcb, 0x4d, 0x00, 0xd4, 0x98, 0x36, 0xb0, 0x2f, 0x8d, 0x76, - 0x5a, 0x1c, 0x32, 0x5a, 0x14, 0xf0, 0xec, 0x37, 0x8e, 0x65, 0x3d, 0x2f, 0xe2, 0xca, 0x0a, 0x39, - 0x56, 0xa6, 0xff, 0x17, 0x60, 0xf4, 0x68, 0x36, 0x9f, 0x6d, 0x9a, 0x52, 0xa4, 0x50, 0x3e, 0xe4, - 0xfe, 0xca, 0x66, 0x83, 0x89, 0xa5, 0x08, 0x07, 0x27, 0xe1, 0xc0, 0x3e, 0x67, 0x91, 0xf4, 0xf9, - 0x37, 0x63, 0xe8, 0xb7, 0x4d, 0x37, 0x17, 0x14, 0x7e, 0x64, 0x67, 0x1f, 0xbd, 0x78, 0xcc, 0x90, - 0x66, 0x45, 0xd0, 0x14, 0x68, 0x3a, 0x0f, 0x52, 0x26, 0x7a, 0x08, 0x1a, 0xca, 0x5f, 0xcf, 0x48, - 0x85, 0x22, 0x10, 0xa6, 0x87, 0x4b, 0xcd, 0x2a, 0xeb, 0x4a, 0x4e, 0xf5, 0xca, 0xb2, 0x8f, 0xda, - 0x93, 0x71, 0xc9, 0x7c, 0xe7, 0xb2, 0x08, 0x40, 0x9b, 0x06, 0xcd, 0x8d, 0xe7, 0xc2, 0x33, 0xa5, - 0x68, 0x80, 0xf0, 0xa1, 0x33, 0x8a, 0xba, 0x7b, 0x0f, 0x0d, 0x05, 0x8d, 0x78, 0x9a, 0x6e, 0x1b, - 0x71, 0xc6, 0x5e, 0xaf, 0x55, 0x0a, 0x8c, 0x06, 0xb8, 0xfe, 0x82, 0x01, 0x97, 0xcb, 0xbe, 0x80, - 0x3a, 0xb7, 0x70, 0x54, 0xb7, 0x01, 0xed, 0xf3, 0xef, 0x4a, 0x24, 0x27, 0x68, 0x18, 0x0b, 0x1e, - 0x0c, 0xb6, 0x4d, 0xc3, 0x6e, 0xed, 0xec, 0xd6, 0xb4, 0x2f, 0xac, 0xe3, 0x9d, 0xdc, 0x92, 0xbc, - 0xdd, 0xad, 0x3c, 0xe7, 0xa1, 0x47, 0x66, 0xe6, 0xb1, 0x5e, 0x37, 0x18, 0x19, 0xc6, 0x5f, 0x91, - 0xb5, 0x44, 0x4f, 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0xed, + 0xc3, 0xb5, 0xd6, 0xe7, 0x43, 0xb8, 0xdb, 0x74, 0x0e, 0x85, 0x22, 0x0a, 0xe7, 0xb7, 0x42, 0x14, + 0x76, 0xea, 0xc9, 0x6c, 0x22, 0xea, 0x03, 0x3c, 0x5a, 0x8d, 0x1f, 0xab, 0x1f, 0xd0, 0xfe, 0x7f, + 0xab, 0x97, 0xd2, 0xb3, 0x7c, 0x77, 0x26, 0xec, 0xa8, 0xf8, 0xc0, 0x39, 0xa2, 0xcb, 0xf5, 0x12, + 0xc7, 0xbb, 0xbe, 0x91, 0x65, 0xda, 0xc9, 0xba, 0xc4, 0x75, 0xe0, 0xc0, 0x42, 0xb2, 0xd2, 0xa9, + 0xba, 0x58, 0xa4, 0x2a, 0xbf, 0x9c, 0xd4, 0x51, 0x04, 0x3d, 0x0c, 0x8d, 0x1a, 0x1e, 0xc3, 0x22, + 0xfa, 0x48, 0x3a, 0x24, 0x1f, 0x47, 0x23, 0x1c, 0x22, 0xa6, 0xfe, 0xf7, 0xff, 0xbb, 0x72, 0x8a, + 0x71, 0x85, 0x58, 0x42, 0x8f, 0xb5, 0x43, 0xdb, 0x9d, 0x74, 0x9d, 0x7f, 0x2d, 0x49, 0x87, 0x20, + 0x9d, 0xa3, 0xc3, 0x07, 0x5f, 0x01, 0xbc, 0xdb, 0xae, 0x93, 0xb3, 0x49, 0x8d, 0xad, 0xe0, 0xb3, + 0x11, 0x4a, 0xda, 0x59, 0x9f, 0xdd, 0x5b, 0x68, 0xa2, 0x59, 0x14, 0xe1, 0x6f, 0xc2, 0x80, 0x20, + 0x53, 0x60, 0x84, 0x0e, 0x22, 0x5b, 0x4d, 0x74, 0x08, 0x6f, 0x3a, 0xb9, 0x65, 0x4f, 0xee, 0x8c, + 0xa0, 0xc5, 0xa6, 0x89, 0xbc, 0x4b, 0x6e, 0x55, 0x63, 0x1a, 0x81, 0xb9, 0x68, 0x1e, 0x58, 0x73, + 0xbf, 0x0b, 0xaf, 0x55, 0xf5, 0xb0, 0x9f, 0x6d, 0x86, 0xc4, 0xdd, 0x9d, 0x22, 0xe8, 0x30, 0x7e, + 0xe1, 0xd5, 0x55, 0xcd, 0xe9, 0x83, 0x94, 0xea, 0x62, 0x6f, 0x35, 0x45, 0xc9, 0x74, 0xf5, 0x46, + 0xb1, 0x74, 0xf2, 0xc4, 0x57, 0x36, 0x02, 0x29, 0x69, 0x50, 0x4a, 0x23, 0x47, 0x6f, 0xf0, 0x52, + 0x59, 0x15, 0xd1, 0x7f, 0x6a, 0xd0, 0x20, 0xcc, 0x79, 0xc0, 0xec, 0xd2, 0x11, 0xe2, 0xdd, 0xa5, + 0xa3, 0xda, 0x5a, 0x7c, 0xe0, 0x53, 0x80, 0xaf, 0x35, 0xa5, 0x0d, 0xb7, 0x5a, 0x3b, 0x6e, 0x01, + 0x3f, 0xec, 0x5e, 0xe8, 0xa2, 0x1b, 0xe5, 0xa4, 0x91, 0x8c, 0x14, 0xa8, 0x76, 0x2c, 0x57, 0xe0, + 0x44, 0x51, 0xb6, 0x1b, 0x0c, 0xbc, 0x66, 0x60, 0xac, 0xf0, 0xd0, 0x6d, 0x00, 0xe0, 0x43, 0x05, + 0x6f, 0xd4, 0x04, 0x1c, 0x93, 0x31, 0x1f, 0x17, 0x33, 0x6c, 0xf5, 0xde, 0xc0, 0x3d, 0x91, 0x88, + 0xc5, 0x3e, 0x9f, 0x39, 0xf7, 0x24, 0x26, 0xa8, 0x6c, 0x5f, 0x24, 0x0b, 0xd0, 0xbf, 0x9c, 0x36, + 0xc7, 0x39, 0xe0, 0x5f, 0x99, 0x5b, 0x9c, 0xee, 0x41, 0x2d, 0x71, 0x0c, 0x56, 0x7b, 0xf6, 0x94, + 0xa3, 0x0c, 0x55, 0x03, 0x64, 0xbc, 0x60, 0xd1, 0xd7, 0x9e, 0x50, 0x1e, 0x21, 0x1e, 0x04, 0x1b, + 0xfe, 0x27, 0xb7, 0x80, 0x5f, 0x6c, 0x53, 0x05, 0x6e, 0x62, 0xe4, 0x80, 0xa4, 0x9f, 0xa9, 0x08, + 0x4b, 0xda, 0x16, 0x92, 0xf8, 0x5d, 0x85, 0xf6, 0x80, 0x39, 0xee, 0x02, 0x56, 0x86, 0x53, 0xa4, + 0x26, 0xd7, 0xb3, 0x3c, 0xdc, 0xea, 0x75, 0xe9, 0x73, 0xcc, 0x88, 0x7c, 0x6f, 0xfa, 0x5d, 0x2e, + 0x3e, 0x40, 0xc0, 0xec, 0xb1, 0x64, 0x76, 0x15, 0xdd, 0xcc, 0x05, 0x17, 0x39, 0x63, 0x30, 0xc0, + 0x6e, 0x79, 0xea, 0x8b, 0xed, 0x62, 0xa0, 0x0d, 0x67, 0x72, 0xde, 0x37, 0x17, 0x92, 0x7a, 0xbb, + 0x8d, 0xfd, 0x1f, 0xf1, 0xa8, 0xb6, 0x46, 0xfa, 0xbd, 0x78, 0x31, 0x98, 0x50, 0xa9, 0x39, 0xe7, + 0x98, 0xb8, 0x68, 0x9b, 0xea, 0x0b, 0x88, 0xf3, 0xcd, 0x05, 0xdf, 0x5f, 0x8a, 0xe9, 0xb3, 0xeb, + 0x5e, 0x88, 0x2d, 0x96, 0x24, 0xcb, 0x0c, 0x09, 0x64, 0x6d, 0x7f, 0x8c, 0xdb, 0x3e, 0x06, 0xd3, + 0x18, 0x83, 0x22, 0xf3, 0x53, 0x85, 0x8c, 0xd7, 0x45, 0x87, 0xce, 0x50, 0xf3, 0xdd, 0x73, 0xdf, + 0xa3, 0xe7, 0xb6, 0x87, 0x5d, 0x88, 0xa4, 0x80, 0x6a, 0x52, 0x3e, 0x39, 0x48, 0x5b, 0xb9, 0xc1, + 0x9d, 0xa4, 0x97, 0xf8, 0x72, 0x3e, 0x6c, 0x11, 0x36, 0xeb, 0x65, 0xbc, 0xea, 0x6e, 0x72, 0x91, + 0x71, 0x4d, 0x89, 0x3a, 0xe9, 0x6d, 0x9f, 0x6f, 0xf9, 0x35, 0x1a, 0x5c, 0xcc, 0x85, 0xd3, 0xe3, + 0xdb, 0x1f, 0x5e, 0x3e, 0xcf, 0x81, 0x73, 0x01, 0x5f, 0x53, 0xd8, 0xe2, 0x09, 0x29, 0x07, 0x95, + 0xe6, 0x6d, 0x07, 0x9f, 0xe6, 0xb5, 0x62, 0x28, 0x5c, 0xcf, 0x50, 0x77, 0x23, 0xa5, 0x5b, 0xaa, + 0xbe, 0x60, 0x03, 0x00, 0x72, 0x0d, 0xb1, 0x64, 0xf2, 0x57, 0xa6, 0x30, 0x41, 0x3e, 0x82, 0xa3, + 0xe1, 0x98, 0x8e, 0xd1, 0x3f, 0x3d, 0x3e, 0xf6, 0x2a, 0x59, 0x0d, 0xff, 0x10, 0x3b, 0xcc, 0x19, + 0xbf, 0x46, 0x18, 0xca, 0x39, 0xea, 0xbc, 0x2e, 0x37, 0xe9, 0xed, 0x39, 0x34, 0xff, 0x74, 0xd1, + 0xd8, 0x82, 0xb8, 0xfd, 0x69, 0x68, 0x9d, 0x7b, 0x9a, 0xed, 0x8e, 0xa5, 0x11, 0x02, 0x82, 0x51, + 0x5a, 0x74, 0x8c, 0xd0, 0x86, 0x4a, 0x32, 0x6c, 0x26, 0x8c, 0x17, 0x6c, 0xaa, 0x5e, 0x3b, 0xf8, + 0x80, 0x53, 0x3d, 0xb8, 0x5c, 0x6a, 0x70, 0x02, 0xbf, 0xfb, 0xb2, 0x1d, 0x63, 0x9e, 0x7b, 0xd3, + 0x7e, 0xb8, 0x9a, 0xfa, 0xd3, 0xb0, 0x38, 0x2c, 0x73, 0xf9, 0xde, 0xfc, 0x70, 0x02, 0x56, 0xef, + 0x4c, 0xc2, 0xe2, 0x7e, 0xab, 0xa0, 0xd6, 0x99, 0x25, 0x18, 0xba, 0x1b, 0x7d, 0xf1, 0x80, 0x47, + 0x3f, 0x1c, 0x3f, 0x41, 0x0f, 0x70, 0xc2, 0xa3, 0xb5, 0x14, 0x90, 0xe8, 0x60, 0xc7, 0x6e, 0xec, + 0x8f, 0x6a, 0xe7, 0x3b, 0x17, 0x2f, 0x9c, 0x6f, 0x8e, 0x21, 0xd1, 0xb8, 0xde, 0x3e, 0xc7, 0x50, + 0x47, 0xc5, 0x98, 0xbb, 0x6f, 0x30, 0xdc, 0x35, 0x1c, 0xcb, 0xf2, 0x2d, 0xd3, 0x1b, 0x97, 0xc2, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -4020,9 +4239,9 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_AD102_sig_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 768, // uncompressed data size (bytes) - 781, // compressed data size (bytes) + 768, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_AD102_sig_dbg_data, // compressed data pointer - NV_TRUE, // is pData compressed? + NV_FALSE, // is pData compressed? NV_TRUE, // contain information for file overriding? NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) }, @@ -4035,62 +4254,61 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_AD102_sig_dbg_storage_pvt; // FILE NAME: kernel/inc/gsprm/bin/booter/ad10x/load/g_booteruc_load_ad10x_ad10x_rsa3k_0_sig.h // FILE TYPE: TEXT // VAR NAME: booter_load_sig_prod_ad10x -// COMPRESSION: YES +// COMPRESSION: NO // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 768 -// COMPRESSED SIZE (bytes): 781 +// COMPRESSED SIZE (bytes): N/A // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_AD102_sig_prod_data[] = { - 0x01, 0x00, 0x03, 0xff, 0xfc, 0x3d, 0x97, 0xd6, 0x98, 0x8b, 0x5a, 0xa0, 0x24, 0xf4, 0x48, 0xc2, - 0xd4, 0x97, 0x34, 0x86, 0xa5, 0x99, 0x3b, 0xfe, 0xe0, 0x53, 0xe4, 0x4c, 0xd7, 0x25, 0xbd, 0xd9, - 0x02, 0x9a, 0xa1, 0xdf, 0xb9, 0xe3, 0xa2, 0xa6, 0xd7, 0x39, 0x34, 0x59, 0x95, 0xda, 0xec, 0x9e, - 0xd2, 0x8c, 0xd9, 0x12, 0x43, 0x9d, 0xa3, 0x1f, 0x95, 0xb1, 0xa4, 0x86, 0x45, 0x14, 0x25, 0x7b, - 0x9c, 0x5d, 0x30, 0x16, 0x11, 0x3c, 0x3c, 0x44, 0x1d, 0x2d, 0x44, 0x61, 0x92, 0xe5, 0xaf, 0x5e, - 0x13, 0xa6, 0xe2, 0x4c, 0xd8, 0x7c, 0x6d, 0xa4, 0x85, 0x39, 0xdc, 0x34, 0xea, 0xd3, 0x13, 0xe7, - 0x83, 0xe4, 0x19, 0x8d, 0x6d, 0x9a, 0xce, 0xa3, 0xab, 0x04, 0xc3, 0x8f, 0xd9, 0xb0, 0x59, 0xb8, - 0x49, 0xe7, 0xe2, 0xe2, 0xeb, 0x85, 0x1f, 0x5f, 0x36, 0xc7, 0xa4, 0xce, 0x36, 0xba, 0xbf, 0xbc, - 0xc3, 0x03, 0xcd, 0x9f, 0x48, 0xe1, 0xf7, 0xd2, 0xc9, 0x72, 0x88, 0x45, 0x3f, 0xb2, 0xc9, 0xdf, - 0x47, 0xfd, 0xbe, 0xd1, 0x4e, 0x40, 0x17, 0xa8, 0xeb, 0x05, 0x25, 0xf4, 0x30, 0x04, 0x52, 0xed, - 0x3f, 0xe4, 0x64, 0x11, 0xfb, 0xe3, 0xcf, 0x97, 0xac, 0xd3, 0xb0, 0x89, 0x0d, 0xc9, 0xb4, 0x92, - 0x0f, 0xaf, 0x01, 0x3d, 0x40, 0x82, 0x2b, 0x7a, 0x7e, 0xbb, 0x22, 0xb0, 0x55, 0x4c, 0x8a, 0x00, - 0xa4, 0xb1, 0x37, 0x95, 0x53, 0x8a, 0xfe, 0x28, 0x70, 0xe7, 0x28, 0x01, 0xb9, 0x76, 0x9a, 0x24, - 0xbd, 0xbe, 0x96, 0xc8, 0x24, 0x02, 0x39, 0x0a, 0x9f, 0xeb, 0xe8, 0x58, 0xda, 0x80, 0x10, 0x42, - 0xa5, 0xcf, 0x28, 0x16, 0x97, 0x41, 0x54, 0xd6, 0x5f, 0xfc, 0x72, 0x96, 0xae, 0x33, 0x52, 0xb5, - 0xea, 0xc9, 0x60, 0x0b, 0x9f, 0x11, 0x90, 0x03, 0xf5, 0x30, 0xb1, 0xb0, 0xf3, 0x43, 0x06, 0x94, - 0x6b, 0x79, 0x80, 0x21, 0x23, 0xb7, 0xe5, 0x1e, 0xf8, 0x3a, 0x72, 0x2c, 0x5d, 0xab, 0x07, 0xf3, - 0x00, 0xde, 0x9c, 0x4e, 0x17, 0x35, 0xab, 0xe1, 0x4b, 0x19, 0x36, 0x36, 0xb9, 0xaf, 0x19, 0xbb, - 0xf1, 0xa0, 0xcd, 0xcb, 0xb6, 0xa9, 0xac, 0x6e, 0x79, 0x82, 0x84, 0x3c, 0x17, 0x81, 0x8e, 0x2c, - 0xf6, 0xd0, 0x7f, 0xbf, 0x23, 0xb2, 0xfc, 0x18, 0x79, 0xc6, 0xf1, 0xdf, 0x7d, 0x64, 0x45, 0x96, - 0x68, 0xfa, 0x27, 0x9e, 0xc6, 0xbe, 0x29, 0xbf, 0xcd, 0xec, 0xd5, 0xac, 0x86, 0xd0, 0x27, 0x4e, - 0xf8, 0x33, 0xb6, 0x1e, 0x0a, 0xbb, 0x15, 0x1a, 0x94, 0xcb, 0x4c, 0x29, 0xb3, 0x5c, 0x59, 0xd1, - 0x8b, 0xef, 0x9e, 0xd4, 0x3a, 0x6a, 0x19, 0x59, 0x7c, 0x42, 0x5a, 0xf9, 0x68, 0xed, 0x42, 0x1d, - 0x69, 0x21, 0x41, 0x82, 0xcd, 0xc2, 0xab, 0x98, 0x60, 0x22, 0xd6, 0xa9, 0x9d, 0x02, 0x7e, 0x12, - 0xac, 0xec, 0x09, 0x9e, 0x41, 0x96, 0xd5, 0x1d, 0x7f, 0xa4, 0x4d, 0xa0, 0xe7, 0x7b, 0xba, 0x94, - 0xde, 0x73, 0x3b, 0x42, 0xfa, 0x8d, 0xb5, 0xa1, 0x77, 0x3b, 0x3a, 0x04, 0xf0, 0xea, 0x53, 0x80, - 0x70, 0x94, 0x3e, 0x41, 0x97, 0x74, 0x59, 0x8d, 0x4a, 0x19, 0xfa, 0xde, 0x9b, 0x58, 0x3b, 0xc7, - 0x30, 0x86, 0x0d, 0x2d, 0xc6, 0x20, 0x33, 0xbb, 0x2f, 0xd3, 0xf0, 0xf1, 0xf9, 0x00, 0x84, 0x04, - 0xb9, 0xda, 0xde, 0x71, 0x35, 0x17, 0xec, 0x6c, 0xd1, 0x50, 0xe1, 0x43, 0xa8, 0x20, 0xc8, 0x7f, - 0xe3, 0xe3, 0x74, 0xc7, 0x88, 0x15, 0x87, 0x7e, 0x89, 0x2b, 0xcc, 0x94, 0xcc, 0x96, 0xdf, 0x51, - 0xb6, 0x09, 0x16, 0x6d, 0xc0, 0xe6, 0xe3, 0xb5, 0x5b, 0xd3, 0x93, 0x68, 0x96, 0xf7, 0xc2, 0xe6, - 0x18, 0xd9, 0xd9, 0x24, 0x35, 0x62, 0xdb, 0x38, 0x3e, 0x06, 0x6b, 0x95, 0x9e, 0x9f, 0x6b, 0xfb, - 0xe7, 0x69, 0xda, 0xa1, 0x9b, 0xde, 0x02, 0x1e, 0xb3, 0x90, 0x01, 0x4b, 0xd1, 0x4b, 0x13, 0xb6, - 0x30, 0xd6, 0x4e, 0x36, 0x99, 0xfc, 0xd1, 0xb5, 0xb4, 0xe3, 0xad, 0x84, 0xe1, 0x63, 0xe8, 0xb2, - 0xa2, 0x0f, 0x1d, 0x48, 0x41, 0xad, 0xef, 0xf7, 0x00, 0x09, 0x88, 0xcd, 0x94, 0x48, 0x20, 0x77, - 0xee, 0xc0, 0xf6, 0xf3, 0xf8, 0x93, 0x2f, 0x8a, 0xc7, 0x04, 0xcf, 0xdf, 0x41, 0xb3, 0xca, 0xd4, - 0x84, 0x80, 0x5c, 0xa9, 0x14, 0x09, 0xc7, 0xf2, 0x45, 0x84, 0x4d, 0xae, 0x40, 0x06, 0x28, 0x41, - 0xe8, 0xa4, 0x2d, 0x66, 0xbe, 0x61, 0x20, 0x4b, 0xec, 0xc6, 0x88, 0xfb, 0x91, 0x4f, 0x19, 0x0a, - 0x62, 0x5a, 0xc4, 0xa7, 0x24, 0xfd, 0x73, 0xfd, 0x70, 0x0b, 0xea, 0xd9, 0xfb, 0x9b, 0x2c, 0x7a, - 0x87, 0x9c, 0xce, 0xb8, 0x87, 0x02, 0x39, 0x53, 0xf2, 0x09, 0x75, 0xc7, 0x12, 0xb9, 0xe3, 0xc4, - 0x43, 0xf6, 0xd2, 0x8d, 0x54, 0x56, 0x6f, 0x29, 0xd7, 0x63, 0x8d, 0x6d, 0xd5, 0x6b, 0x9f, 0xc2, - 0x6c, 0xd3, 0x64, 0xe2, 0x63, 0xaa, 0x22, 0xef, 0x4a, 0x22, 0x3c, 0x22, 0xb0, 0xd3, 0x82, 0xf7, - 0xa0, 0xfb, 0x45, 0x1c, 0x60, 0xc1, 0xd8, 0x45, 0xe1, 0x5b, 0x74, 0xc0, 0xba, 0xf6, 0x37, 0x2f, - 0xd8, 0x8d, 0xc1, 0x5e, 0xf0, 0xec, 0x9e, 0x8a, 0x87, 0x7c, 0xa0, 0x8c, 0x2c, 0x81, 0x63, 0xfc, - 0x6e, 0x3d, 0xf8, 0x6a, 0xdf, 0x22, 0x39, 0x08, 0xb7, 0x32, 0x29, 0xf4, 0x3b, 0x4a, 0x87, 0x05, - 0x07, 0xe7, 0x92, 0x3d, 0x85, 0x44, 0xce, 0x4e, 0x83, 0xa8, 0xb8, 0xf5, 0x0f, 0x15, 0xb7, 0xe7, - 0x5d, 0xdb, 0x0e, 0x5f, 0x68, 0x56, 0x11, 0x18, 0x42, 0x0b, 0x32, 0xd8, 0x47, 0xc5, 0xc6, 0x29, - 0x86, 0x9d, 0xab, 0x6a, 0x31, 0xeb, 0xcb, 0x1e, 0xf9, 0xc7, 0xdd, 0x31, 0x67, 0x31, 0x0b, 0xdc, - 0x45, 0xc1, 0x62, 0x46, 0x2b, 0x6e, 0xc9, 0x26, 0x11, 0x00, 0x03, 0x00, 0x00, + 0x5f, 0x8a, 0x41, 0x9e, 0x07, 0x83, 0x8a, 0xe0, 0xa8, 0x10, 0x61, 0x44, 0x15, 0x1f, 0x45, 0xed, + 0x2a, 0x26, 0x5f, 0x8a, 0x22, 0xf5, 0x94, 0x3e, 0x9d, 0xda, 0xc9, 0x3c, 0xc3, 0x7d, 0xb3, 0xa3, + 0x0e, 0xdc, 0xf5, 0x42, 0xd5, 0x73, 0xad, 0x4d, 0x53, 0xb4, 0x0d, 0x9e, 0xe9, 0x72, 0x58, 0x74, + 0x5d, 0x71, 0x65, 0x31, 0x54, 0xe0, 0x87, 0x32, 0x1c, 0x55, 0x65, 0x96, 0x5c, 0x8a, 0x56, 0xcf, + 0xdf, 0x70, 0xed, 0x9b, 0xd3, 0x7d, 0x8a, 0x5b, 0x3f, 0x5c, 0x27, 0xd5, 0x0d, 0x2e, 0x93, 0x38, + 0xc1, 0xef, 0xf2, 0x31, 0xa9, 0x05, 0x53, 0x4c, 0x2c, 0x58, 0xb6, 0xa2, 0xfb, 0x5b, 0x7c, 0x28, + 0xd5, 0x95, 0xe9, 0xe5, 0x52, 0x11, 0xe3, 0x8b, 0x7a, 0xd8, 0xd5, 0xfe, 0x8f, 0xcc, 0x17, 0x40, + 0x8a, 0x57, 0x7a, 0x70, 0xe2, 0xe2, 0xb0, 0x40, 0x0c, 0x89, 0xda, 0xc4, 0xee, 0x5f, 0xc1, 0x0d, + 0xdb, 0x17, 0x28, 0x2f, 0x9d, 0xe1, 0x92, 0xaf, 0xdf, 0xb0, 0x78, 0x6f, 0xfc, 0xfa, 0x02, 0xb8, + 0x7b, 0x49, 0x9b, 0x65, 0x54, 0x57, 0x47, 0x02, 0xf7, 0xf4, 0x1c, 0xaa, 0x82, 0xd5, 0xff, 0xe2, + 0x63, 0x69, 0x43, 0x42, 0x86, 0x3f, 0xe8, 0xd4, 0x75, 0x41, 0xc6, 0xee, 0x70, 0x5e, 0xde, 0x1d, + 0xa5, 0x08, 0x52, 0x5e, 0x7d, 0x77, 0xc7, 0x55, 0x6a, 0x65, 0xa6, 0x16, 0x2a, 0xb8, 0xc6, 0xab, + 0x25, 0x22, 0xdd, 0x0a, 0x41, 0x56, 0x29, 0xc7, 0x15, 0x59, 0xdd, 0x16, 0x20, 0x1b, 0x4d, 0x45, + 0x9f, 0x09, 0xe6, 0xd3, 0x57, 0xdb, 0x7c, 0xeb, 0x1a, 0x29, 0xc5, 0xbd, 0xc7, 0xc0, 0x03, 0x85, + 0xc2, 0x17, 0xd9, 0xef, 0xf9, 0x75, 0x4c, 0xdf, 0x26, 0xac, 0xe6, 0x9a, 0x48, 0xbc, 0x04, 0x43, + 0xbe, 0x65, 0x55, 0x31, 0x80, 0xfd, 0xff, 0xd5, 0x67, 0x2a, 0x26, 0x81, 0x5c, 0x99, 0xd9, 0x33, + 0x6f, 0x22, 0x98, 0xb4, 0x12, 0xfc, 0x58, 0xb8, 0x75, 0x3d, 0x23, 0x7a, 0x20, 0xdb, 0x3c, 0xb7, + 0xa2, 0x78, 0x98, 0xdc, 0x9a, 0xd3, 0xde, 0xfb, 0x74, 0xbc, 0x33, 0x30, 0x6e, 0x8f, 0x36, 0xbd, + 0xdc, 0xcd, 0xac, 0x1a, 0x06, 0x7e, 0xe5, 0xd1, 0xee, 0xac, 0x68, 0xc9, 0xd8, 0x58, 0xa6, 0xd2, + 0x1c, 0x6d, 0x94, 0x0a, 0x5d, 0x67, 0x05, 0x4f, 0x3d, 0xcd, 0x88, 0xa4, 0x1b, 0xde, 0xe2, 0xcd, + 0x47, 0x19, 0x4d, 0x22, 0xa7, 0xb0, 0xdb, 0x4f, 0xbc, 0x2d, 0xaa, 0xc9, 0x7e, 0xf1, 0xa9, 0x72, + 0xc3, 0x30, 0xe5, 0xf0, 0x7a, 0x84, 0xad, 0x6e, 0x52, 0x9c, 0x55, 0xec, 0x3b, 0xc9, 0x25, 0xe2, + 0x26, 0x56, 0x65, 0x07, 0x0d, 0x24, 0x8f, 0x37, 0xb4, 0x69, 0xeb, 0xf4, 0x2b, 0x7e, 0xd7, 0x13, + 0x2f, 0x0e, 0x64, 0xed, 0xac, 0xa8, 0x03, 0xb7, 0x8c, 0xcc, 0x27, 0x99, 0xf7, 0x58, 0x56, 0x38, + 0x7b, 0xca, 0xe6, 0x99, 0x10, 0xf0, 0xe5, 0x43, 0x07, 0x59, 0x5a, 0x10, 0x86, 0x61, 0x94, 0xef, + 0x1b, 0x80, 0x69, 0xd8, 0xeb, 0xce, 0x50, 0xc2, 0x18, 0x93, 0x93, 0x35, 0x1f, 0x76, 0x96, 0x54, + 0xac, 0xfb, 0x40, 0xe1, 0x5e, 0xee, 0xca, 0x7d, 0x2d, 0x4c, 0x8b, 0x3d, 0x7a, 0xb4, 0xa7, 0x82, + 0xe4, 0x63, 0xc2, 0x7e, 0xb4, 0xa3, 0x82, 0xf6, 0x09, 0xa4, 0x31, 0x74, 0xf0, 0x43, 0x85, 0x17, + 0xa3, 0x46, 0x5e, 0x0a, 0x8a, 0xbf, 0xc2, 0x39, 0x7a, 0x13, 0x96, 0x19, 0xe4, 0x99, 0x06, 0xa7, + 0x05, 0x27, 0x4c, 0x8c, 0xf0, 0x74, 0xb4, 0x86, 0x40, 0xdd, 0xe2, 0xb1, 0xbb, 0x96, 0x69, 0x54, + 0x70, 0xac, 0x72, 0xad, 0xa0, 0x8b, 0x9c, 0x28, 0x65, 0xa5, 0x3c, 0x14, 0x31, 0x98, 0x94, 0x4c, + 0xa0, 0x11, 0x89, 0x4a, 0xe0, 0x11, 0x94, 0x53, 0xd5, 0xca, 0x0b, 0x28, 0xa9, 0x0f, 0xad, 0x02, + 0x40, 0xfd, 0x34, 0x0c, 0x79, 0xbb, 0x1e, 0x05, 0x4e, 0x87, 0xce, 0x14, 0x62, 0x26, 0x3c, 0x04, + 0xec, 0x4d, 0x88, 0xb6, 0x39, 0x63, 0x67, 0xa5, 0x1b, 0xa8, 0x35, 0xa2, 0xcd, 0x7a, 0xbc, 0x56, + 0xbe, 0x84, 0x43, 0x04, 0x9e, 0x1f, 0x58, 0x36, 0x9e, 0xfe, 0xa7, 0xad, 0x84, 0x28, 0xe5, 0xeb, + 0xed, 0x4c, 0x74, 0xff, 0xce, 0xe7, 0x00, 0x9f, 0xaf, 0xb0, 0x7d, 0x6b, 0x44, 0x2a, 0x41, 0xe5, + 0x63, 0xd8, 0x1a, 0xa7, 0x88, 0xfb, 0x8d, 0x5e, 0x09, 0x32, 0x69, 0xe1, 0x41, 0x8d, 0x52, 0xa1, + 0x69, 0x87, 0x2f, 0x1d, 0xcf, 0x7a, 0x67, 0x6b, 0x0f, 0x77, 0xb3, 0xb7, 0x58, 0x25, 0xf9, 0x87, + 0x86, 0x27, 0x3a, 0x03, 0xd6, 0x6d, 0x6c, 0x09, 0x56, 0xa0, 0xc4, 0x14, 0x7d, 0x63, 0xff, 0x7e, + 0x2a, 0x2f, 0xb7, 0x7f, 0xac, 0xe8, 0x52, 0xca, 0x77, 0x4d, 0x2a, 0xc5, 0xfc, 0x66, 0xba, 0xd2, + 0xb3, 0xd4, 0x27, 0x69, 0x8f, 0x31, 0xd4, 0x25, 0xc1, 0x94, 0x26, 0x96, 0xed, 0x99, 0xfa, 0x4c, + 0x76, 0xf6, 0xb1, 0x8d, 0xee, 0x42, 0x73, 0xc1, 0xab, 0x44, 0xe1, 0x9e, 0x93, 0x84, 0x55, 0xb1, + 0xa5, 0x7b, 0x90, 0x1b, 0xb6, 0xa9, 0x73, 0x20, 0x87, 0x69, 0x2e, 0x5a, 0xe2, 0x0e, 0xe0, 0xbb, + 0xb3, 0xb4, 0x93, 0x90, 0x0b, 0xe2, 0x17, 0xd6, 0x1d, 0xcb, 0x50, 0xba, 0xc7, 0x1a, 0xfb, 0x83, + 0x7f, 0x1b, 0x50, 0xe4, 0x80, 0x6a, 0x70, 0xae, 0xa0, 0xde, 0xbd, 0xa7, 0x21, 0x15, 0x1f, 0xd0, + 0x37, 0x3c, 0xc3, 0x78, 0xed, 0x00, 0x8f, 0x26, 0x08, 0xc0, 0x18, 0x27, 0x1f, 0x19, 0xc7, 0x4a, + 0x3b, 0x38, 0xbb, 0xc6, 0x0d, 0x64, 0x65, 0xcd, 0x9e, 0xba, 0xb5, 0x5c, 0x12, 0xe9, 0x28, 0x61, + 0x2e, 0xf2, 0xb4, 0xb5, 0xc7, 0xb9, 0xf8, 0xb9, 0x2f, 0x3e, 0x2f, 0x42, 0x9d, 0x88, 0xb6, 0x6a, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -4101,9 +4319,9 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_AD102_sig_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 768, // uncompressed data size (bytes) - 781, // compressed data size (bytes) + 768, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_AD102_sig_prod_data, // compressed data pointer - NV_TRUE, // is pData compressed? + NV_FALSE, // is pData compressed? NV_TRUE, // contain information for file overriding? NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) }, @@ -4123,7 +4341,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_AD102_sig_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_AD102_patch_loc_data[] = { - 0x10, 0x77, 0x00, 0x00, + 0x10, 0x7e, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c index 7d0817fd4f..ec40be1469 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c @@ -34,2063 +34,2144 @@ // VAR NAME: booter_ucode_data_ga100 // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 58624 -// COMPRESSED SIZE (bytes): 32824 +// DATA SIZE (bytes): 60160 +// COMPRESSED SIZE (bytes): 34118 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_image_dbg_data[] = { - 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0x29, 0x38, 0xd1, 0xb9, 0x0b, 0x5e, 0x4c, 0xe4, 0xae, 0x95, + 0xf9, 0xf2, 0xac, 0xb3, 0xaf, 0xa9, 0x7f, 0xde, 0x5b, 0xfe, 0xac, 0xf0, 0xc3, 0xba, 0xd4, 0xfe, + 0xf4, 0x05, 0x2a, 0xc5, 0xca, 0xa4, 0x03, 0x44, 0x49, 0xff, 0x83, 0xe5, 0x19, 0x23, 0x5f, 0x90, + 0x36, 0x6c, 0xbe, 0x7a, 0x28, 0xed, 0xff, 0xde, 0x66, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x9f, 0xfd, 0x03, 0x1f, 0x77, + 0x6d, 0xda, 0x00, 0xeb, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2100,8 +2181,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA100_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 58624, // uncompressed data size (bytes) - 32824, // compressed data size (bytes) + 60160, // uncompressed data size (bytes) + 34118, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_GA100_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -2123,8 +2204,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA100_image_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x6e, 0x04, 0xe2, 0x14, 0x08, 0x13, 0x4c, 0x34, 0x40, 0x69, - 0x20, 0x00, 0x00, 0x90, 0x7b, 0x92, 0x9e, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x6e, 0x07, 0xe2, 0x14, 0x08, 0x13, 0x4c, 0xb4, 0x41, 0x69, + 0x20, 0x00, 0x00, 0x14, 0xec, 0x7e, 0xca, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2152,2063 +2233,2144 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA100_header_dbg_storage_pvt; // VAR NAME: booter_ucode_data_ga100 // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 58624 -// COMPRESSED SIZE (bytes): 32824 +// DATA SIZE (bytes): 60160 +// COMPRESSED SIZE (bytes): 34118 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_image_prod_data[] = { - 0xed, 0xfd, 0x43, 0x90, 0x28, 0x4d, 0xc3, 0x00, 0x6a, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xbb, 0xfb, - 0xb4, 0x6d, 0xe3, 0xb4, 0x6d, 0x9f, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0xad, 0xf9, 0xfe, - 0x89, 0x98, 0xcd, 0xbb, 0x99, 0xb8, 0x77, 0xdd, 0xcf, 0x26, 0x11, 0x51, 0x55, 0x59, 0x8e, 0x44, - 0x65, 0x49, 0x02, 0x20, 0x4c, 0xa7, 0x01, 0xc4, 0x28, 0x60, 0x00, 0x74, 0x1d, 0xe6, 0xbe, 0x35, - 0x7d, 0x03, 0x4a, 0x02, 0x20, 0xfe, 0x5f, 0x86, 0x3a, 0x06, 0xc0, 0xff, 0x37, 0x19, 0x06, 0x00, - 0x00, 0xf8, 0x9d, 0x08, 0xe0, 0x43, 0x0f, 0x00, 0xf0, 0x0a, 0xf4, 0x0a, 0xf0, 0x06, 0x14, 0x05, - 0x00, 0x04, 0xd0, 0xb3, 0xbd, 0xf3, 0xf3, 0xf3, 0x03, 0x1f, 0x06, 0x00, 0x08, 0xf0, 0x93, 0x03, - 0xd2, 0x70, 0x08, 0xc0, 0x9c, 0xba, 0x06, 0xd8, 0x90, 0x08, 0x40, 0x93, 0xba, 0x06, 0xf4, 0xbf, - 0x80, 0x34, 0x75, 0x0d, 0xf8, 0x7f, 0x01, 0xde, 0xff, 0x96, 0x05, 0x48, 0xcd, 0x01, 0x6e, 0xda, - 0x01, 0xee, 0xc9, 0xc9, 0xdd, 0x49, 0xcd, 0x01, 0x4c, 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0x1d, 0x3e, 0xea, 0x78, + 0xd1, 0x5a, 0xbb, 0x9b, 0xb4, 0x91, 0xf3, 0x64, 0xad, 0xa4, 0x4e, 0x5a, 0x36, 0x5b, 0xdb, 0x6c, + 0x84, 0x7c, 0xc5, 0xef, 0x73, 0x1e, 0xd1, 0xed, 0xb0, 0xe0, 0x8e, 0x7e, 0xeb, 0xd3, 0xf5, 0x8e, + 0x93, 0xf1, 0xf3, 0x31, 0x97, 0x2f, 0x97, 0x3a, 0x28, 0x79, 0xc2, 0x3a, 0xeb, 0xf7, 0x47, 0x17, + 0xed, 0x53, 0x3e, 0xbc, 0x50, 0xf2, 0x7f, 0x6f, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xcf, 0xfe, 0x01, 0xcb, 0x60, + 0x93, 0x51, 0x00, 0xeb, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -4218,8 +4380,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA100_image_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 58624, // uncompressed data size (bytes) - 32824, // compressed data size (bytes) + 60160, // uncompressed data size (bytes) + 34118, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_GA100_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -4241,8 +4403,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA100_image_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x6e, 0x04, 0xe2, 0x14, 0x08, 0x13, 0x4c, 0x34, 0x40, 0x69, - 0x20, 0x00, 0x00, 0x90, 0x7b, 0x92, 0x9e, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x6e, 0x07, 0xe2, 0x14, 0x08, 0x13, 0x4c, 0xb4, 0x41, 0x69, + 0x20, 0x00, 0x00, 0x14, 0xec, 0x7e, 0xca, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -4268,38 +4430,37 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA100_header_prod_storage_pvt; // FILE NAME: kernel/inc/gsprm/bin/booter/ga100/load/g_booteruc_load_ga100_ga100_rsa3k_1_sig.h // FILE TYPE: TEXT // VAR NAME: booter_load_sig_dbg_ga100 -// COMPRESSION: YES +// COMPRESSION: NO // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 384 -// COMPRESSED SIZE (bytes): 397 +// COMPRESSED SIZE (bytes): N/A // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_sig_dbg_data[] = { - 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x7b, 0xff, 0x6d, 0xfb, 0x28, 0x8d, 0x38, 0xe2, 0x29, 0x9b, 0xdc, - 0x72, 0xcc, 0xcb, 0x2b, 0xc7, 0x08, 0x50, 0x40, 0x65, 0xa8, 0xff, 0x6f, 0x6a, 0x21, 0xe2, 0x14, - 0xef, 0xea, 0x9f, 0xa2, 0x97, 0xa5, 0x15, 0x11, 0x72, 0x9d, 0xe8, 0x24, 0xee, 0x29, 0xf0, 0x19, - 0xd0, 0x07, 0x1f, 0x0a, 0x33, 0x8b, 0xdc, 0x2e, 0x2e, 0x72, 0xb9, 0x67, 0x79, 0x48, 0xb0, 0xe7, - 0x23, 0xef, 0xb9, 0xe7, 0x15, 0xbf, 0x50, 0xe3, 0x56, 0xc9, 0x26, 0x28, 0x8a, 0x66, 0xbf, 0xf0, - 0xac, 0xe1, 0x07, 0x39, 0xfd, 0x97, 0x40, 0x2e, 0xb5, 0xa1, 0x49, 0x0c, 0xdf, 0x6a, 0xae, 0x52, - 0x99, 0x20, 0x5f, 0xd9, 0xf1, 0xbc, 0xee, 0x40, 0xc0, 0x04, 0x35, 0x6a, 0x63, 0x6c, 0x97, 0x53, - 0x5c, 0x64, 0x0f, 0x91, 0xa0, 0xac, 0x59, 0x6c, 0xdf, 0x93, 0x31, 0xd4, 0x93, 0xdb, 0xe0, 0x2b, - 0x17, 0x9a, 0x9e, 0x62, 0xb0, 0xf7, 0xbc, 0x62, 0xfe, 0x83, 0x71, 0x86, 0x7c, 0xed, 0x92, 0x67, - 0xba, 0x3c, 0xdf, 0xb6, 0x2e, 0x53, 0x67, 0x6e, 0x81, 0x89, 0xf4, 0xb6, 0xac, 0x2b, 0x74, 0xaa, - 0xad, 0x10, 0x0f, 0x8b, 0xa8, 0xf1, 0x5d, 0x32, 0x42, 0x72, 0xf8, 0xef, 0xbf, 0xb7, 0xcd, 0x7e, - 0xe8, 0x5f, 0xdc, 0xb8, 0xfa, 0x48, 0xb7, 0x71, 0xe7, 0x83, 0x63, 0x35, 0xe2, 0x59, 0xbb, 0x5d, - 0x09, 0x78, 0x9e, 0x18, 0x0b, 0xac, 0xec, 0x58, 0x05, 0xbe, 0x44, 0x0e, 0xc5, 0xf2, 0x4d, 0xc3, - 0x1e, 0x49, 0x52, 0x43, 0x22, 0x63, 0x2d, 0x1c, 0x7b, 0xe3, 0xb1, 0x2e, 0xff, 0x5c, 0x50, 0xe4, - 0xe6, 0x58, 0x9e, 0x00, 0xb6, 0x56, 0xb7, 0xe8, 0xd7, 0xe4, 0x5c, 0xe1, 0x1a, 0x46, 0xe8, 0xbf, - 0x52, 0xe1, 0x27, 0x36, 0x9b, 0x1b, 0x7c, 0xe3, 0xc7, 0x61, 0x5d, 0xbe, 0x03, 0x3a, 0xde, 0xeb, - 0x17, 0xe5, 0x6b, 0xe3, 0x9c, 0x8d, 0x75, 0xeb, 0xed, 0x01, 0xf6, 0xb7, 0x46, 0xb0, 0xd0, 0x4b, - 0xd8, 0x51, 0x6c, 0x80, 0xfe, 0xf6, 0x7a, 0x95, 0x1f, 0x97, 0x35, 0x67, 0x22, 0x6f, 0x21, 0xd6, - 0xbf, 0x3b, 0x12, 0xa6, 0xbb, 0x1f, 0x24, 0x1a, 0x32, 0x36, 0x60, 0xbb, 0xda, 0x2c, 0xf1, 0x6f, - 0x8a, 0xf5, 0x78, 0x02, 0x39, 0x9f, 0xf3, 0x38, 0x38, 0x55, 0x2b, 0x3c, 0x26, 0x39, 0x0d, 0x2b, - 0xb6, 0x8e, 0xd0, 0xdc, 0xa7, 0xf5, 0x6c, 0x00, 0x39, 0xbf, 0x5e, 0xc8, 0x1f, 0x28, 0xbb, 0xe4, - 0x5a, 0xd3, 0x9a, 0x5f, 0x2c, 0xf1, 0xc5, 0x88, 0x2e, 0x79, 0x31, 0x88, 0x12, 0x40, 0xec, 0x0f, - 0xf1, 0x94, 0x78, 0x9e, 0xf4, 0x8e, 0x65, 0x56, 0x0f, 0xd1, 0x0a, 0x89, 0x5a, 0xb8, 0x8e, 0x10, - 0x21, 0x96, 0x37, 0xa9, 0xd4, 0x7b, 0x4b, 0xad, 0x6c, 0x55, 0xcc, 0x8b, 0xc1, 0xb8, 0xb0, 0x93, - 0x6e, 0xda, 0x6c, 0xc8, 0x7f, 0x44, 0x50, 0xac, 0xb1, 0x80, 0x01, 0x00, 0x00, + 0x07, 0x54, 0xf1, 0x04, 0x77, 0x79, 0xfb, 0xfe, 0x7d, 0x9c, 0xd5, 0x2f, 0xd1, 0xf2, 0x5f, 0xe7, + 0xe2, 0xc3, 0x37, 0xd2, 0x9a, 0xed, 0x62, 0xcf, 0xb3, 0x44, 0xf9, 0xdd, 0x07, 0x37, 0xad, 0x02, + 0x56, 0x94, 0x26, 0x42, 0x09, 0x29, 0x9b, 0xa0, 0x7d, 0xaf, 0x0b, 0xdb, 0xa6, 0xbe, 0x48, 0xbd, + 0x52, 0x75, 0x2c, 0xc5, 0x18, 0x9d, 0x6a, 0x86, 0x5d, 0x63, 0x04, 0x7e, 0x45, 0x8e, 0x20, 0xf3, + 0xe4, 0x8f, 0xb0, 0x90, 0x64, 0x5e, 0xf4, 0x04, 0x16, 0xce, 0x3d, 0x51, 0xb5, 0xd4, 0x80, 0xa0, + 0x2f, 0x1d, 0x5a, 0x43, 0xe1, 0x66, 0x7c, 0x1a, 0x49, 0xe1, 0xe3, 0x87, 0xd5, 0x30, 0xe6, 0x2f, + 0x89, 0xc8, 0xc0, 0xf8, 0x1d, 0xe0, 0xe7, 0xf9, 0xa5, 0x08, 0x71, 0xf8, 0x46, 0x07, 0xdd, 0x13, + 0x43, 0x6d, 0x41, 0x14, 0xc3, 0x8c, 0x01, 0x69, 0xda, 0x99, 0x8e, 0xbd, 0x44, 0xd7, 0xde, 0xca, + 0x4c, 0x5e, 0xc1, 0x5c, 0x7f, 0xaf, 0x5b, 0x0b, 0x41, 0x87, 0x1d, 0x90, 0x6c, 0x9e, 0xb9, 0x0b, + 0x33, 0xce, 0xf7, 0xfb, 0xf6, 0x2b, 0xfa, 0x88, 0x38, 0x55, 0x04, 0x25, 0x9f, 0xe3, 0xc5, 0x26, + 0xee, 0xdc, 0xf8, 0x83, 0x7d, 0xf2, 0x10, 0x3f, 0x75, 0x57, 0x79, 0x71, 0xcd, 0xc3, 0x1a, 0x32, + 0xcc, 0x2e, 0xad, 0x91, 0x11, 0x03, 0x86, 0xb6, 0x78, 0xe4, 0x43, 0x51, 0x3a, 0x34, 0xec, 0xf8, + 0x96, 0x1f, 0x6f, 0x9d, 0x19, 0x26, 0x1e, 0xb0, 0xd2, 0xfe, 0xb0, 0x86, 0x91, 0x5e, 0x2f, 0x2c, + 0xb7, 0x63, 0x7d, 0xf4, 0x83, 0x37, 0x3c, 0xd5, 0x8d, 0x9d, 0xac, 0x0b, 0x37, 0x21, 0x9b, 0xa7, + 0xe1, 0x53, 0xb1, 0x51, 0x01, 0x05, 0xeb, 0x48, 0xe4, 0x24, 0x1b, 0xff, 0x37, 0x73, 0xd2, 0xf4, + 0x26, 0xb7, 0x97, 0xb5, 0x33, 0x2e, 0xfc, 0x9a, 0x0a, 0xf7, 0x15, 0x06, 0x4a, 0xd3, 0xf7, 0x35, + 0xef, 0xa1, 0xfe, 0xeb, 0xc9, 0xe7, 0xde, 0x4f, 0xd7, 0x2d, 0x5a, 0xf9, 0xa6, 0x0b, 0x5e, 0x42, + 0x80, 0x31, 0x9c, 0x47, 0xbb, 0xbe, 0x26, 0x47, 0x71, 0x57, 0xe6, 0x86, 0xf4, 0x71, 0x91, 0x3b, + 0xed, 0x9d, 0xf5, 0x45, 0x3a, 0x63, 0x4c, 0xad, 0x85, 0xfa, 0xfb, 0x43, 0x6b, 0x05, 0x3d, 0x97, + 0x9f, 0x0f, 0xd0, 0xee, 0xb8, 0x26, 0x84, 0x65, 0x83, 0x91, 0x04, 0x99, 0x7a, 0x09, 0x31, 0xdc, + 0xdf, 0xc9, 0x16, 0xcd, 0x63, 0x54, 0x84, 0x16, 0xd8, 0x35, 0x79, 0x1f, 0xf0, 0xcb, 0x4b, 0x5a, + 0x41, 0xbd, 0xfb, 0xd1, 0x66, 0x2c, 0x3f, 0xe1, 0xdf, 0xbb, 0xec, 0xab, 0xe2, 0xc8, 0x07, 0x91, + 0x52, 0x9c, 0x3e, 0x2c, 0x65, 0x86, 0xdf, 0xd3, 0xfa, 0x1b, 0xfc, 0x84, 0xfb, 0x44, 0x4f, 0x9b, + 0xe0, 0xe7, 0xbe, 0xc8, 0xa6, 0x84, 0x39, 0x06, 0x04, 0x28, 0x8d, 0x50, 0x07, 0x61, 0xe4, 0x77, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -4310,9 +4471,9 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA100_sig_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 384, // uncompressed data size (bytes) - 397, // compressed data size (bytes) + 384, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_GA100_sig_dbg_data, // compressed data pointer - NV_TRUE, // is pData compressed? + NV_FALSE, // is pData compressed? NV_TRUE, // contain information for file overriding? NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) }, @@ -4325,38 +4486,37 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA100_sig_dbg_storage_pvt; // FILE NAME: kernel/inc/gsprm/bin/booter/ga100/load/g_booteruc_load_ga100_ga100_rsa3k_1_sig.h // FILE TYPE: TEXT // VAR NAME: booter_load_sig_prod_ga100 -// COMPRESSION: YES +// COMPRESSION: NO // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 384 -// COMPRESSED SIZE (bytes): 397 +// COMPRESSED SIZE (bytes): N/A // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_sig_prod_data[] = { - 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x7e, 0x88, 0x43, 0xf1, 0xcc, 0x3a, 0x3f, 0x99, 0x2c, 0x9b, 0x79, - 0x47, 0xd9, 0x1a, 0x17, 0x13, 0xd8, 0x75, 0x94, 0x97, 0x3e, 0xfe, 0x09, 0x8c, 0xa5, 0x1c, 0x48, - 0x0e, 0x0d, 0xed, 0xd4, 0xd9, 0xd4, 0xfa, 0x99, 0xc5, 0x4f, 0xbd, 0x91, 0x48, 0x78, 0x2b, 0x71, - 0xac, 0x51, 0xc5, 0x86, 0x3b, 0xb3, 0xdd, 0xfd, 0x03, 0xc0, 0x44, 0xf3, 0xa1, 0xaf, 0x0e, 0xe8, - 0xff, 0x40, 0x0e, 0x9c, 0x1b, 0x5f, 0xe6, 0xa4, 0x32, 0xe6, 0x3e, 0xe7, 0x52, 0x53, 0xb2, 0x6a, - 0x7b, 0xf2, 0xdc, 0x63, 0xb8, 0x98, 0x03, 0x0b, 0x3f, 0xb5, 0x86, 0xc9, 0xc7, 0xbb, 0xec, 0x12, - 0xd1, 0xf1, 0x5d, 0x20, 0xb6, 0xd7, 0x0e, 0xd3, 0x4a, 0xd2, 0x74, 0xb5, 0x23, 0x3f, 0xca, 0xe2, - 0x49, 0xb0, 0xd7, 0x52, 0x16, 0x73, 0xca, 0x98, 0xc9, 0x99, 0x22, 0x4a, 0x98, 0xe5, 0xc1, 0xa6, - 0xd3, 0xf8, 0x01, 0x0a, 0x42, 0x94, 0xc5, 0x94, 0x67, 0xce, 0x58, 0x66, 0x34, 0xb3, 0x48, 0x99, - 0xc7, 0x11, 0xe8, 0x5a, 0x7a, 0xed, 0x4a, 0x7b, 0x3f, 0xa2, 0xe8, 0x68, 0x52, 0xd9, 0x73, 0x9f, - 0x20, 0xce, 0x0c, 0xd4, 0xc4, 0x19, 0x95, 0xaf, 0x73, 0x4e, 0xa9, 0xc8, 0x3d, 0x9f, 0x58, 0x1d, - 0xcf, 0xb6, 0x9f, 0xe1, 0x0a, 0xe0, 0xb5, 0x56, 0xc2, 0xb1, 0x73, 0x77, 0xb2, 0xb0, 0x93, 0x95, - 0x9f, 0x9f, 0xe2, 0xb4, 0xab, 0xc8, 0xbb, 0xb3, 0xc7, 0x3c, 0xac, 0x66, 0xc3, 0x07, 0xf5, 0x90, - 0x7b, 0x26, 0x1e, 0x94, 0x3c, 0xe2, 0x87, 0xea, 0x1e, 0xc6, 0x92, 0x2b, 0xcf, 0xdd, 0x2e, 0xb4, - 0xfb, 0x60, 0x6f, 0xee, 0x9a, 0x31, 0x8e, 0xa7, 0x0e, 0x90, 0x69, 0xe6, 0xa9, 0xd2, 0x1c, 0x8d, - 0x88, 0x05, 0xb6, 0xa6, 0xdf, 0x89, 0xe1, 0x18, 0x10, 0x93, 0x40, 0x17, 0x9c, 0x4e, 0xd6, 0x1b, - 0x0c, 0x62, 0x3c, 0x32, 0x07, 0xbc, 0x12, 0xd3, 0x5e, 0x2a, 0xe3, 0xbb, 0x5d, 0x8b, 0x23, 0xf9, - 0x3e, 0x67, 0x5b, 0x1d, 0xf0, 0x6a, 0x20, 0x37, 0x03, 0xe4, 0x37, 0x6c, 0x9f, 0x19, 0xd6, 0x36, - 0xd4, 0xc3, 0xcf, 0xef, 0x82, 0x4b, 0x06, 0xf5, 0xd5, 0x8e, 0x62, 0xa2, 0x3a, 0x46, 0xf5, 0xc5, - 0x6c, 0x77, 0x35, 0xb0, 0x18, 0x17, 0x2e, 0xe9, 0xfe, 0xfc, 0x20, 0x60, 0x95, 0x24, 0x93, 0x22, - 0x1e, 0xf3, 0xb8, 0x0a, 0x28, 0x0d, 0xea, 0xc5, 0x26, 0x91, 0x50, 0x66, 0x85, 0x31, 0xf2, 0x06, - 0x67, 0x68, 0x9c, 0x16, 0xbe, 0x44, 0x59, 0x84, 0x7d, 0x5e, 0xe5, 0xfb, 0x34, 0x25, 0xb1, 0xfe, - 0x49, 0x7f, 0x41, 0x3a, 0x0b, 0x54, 0x76, 0x3f, 0x22, 0xa8, 0xcb, 0xf0, 0x92, 0x8b, 0x45, 0x24, - 0x08, 0xa2, 0x5d, 0x0d, 0x4f, 0x49, 0xb2, 0x06, 0xad, 0x27, 0x6e, 0x52, 0xf1, 0xcd, 0xbc, 0x50, - 0x81, 0xbf, 0x61, 0x0b, 0x9f, 0x5c, 0xb9, 0xf1, 0xd2, 0x80, 0x01, 0x00, 0x00, + 0x05, 0x9e, 0x26, 0xca, 0x84, 0x64, 0x4f, 0x75, 0xc7, 0xdb, 0x4c, 0x63, 0x4f, 0x01, 0xb6, 0x28, + 0x12, 0x38, 0xe3, 0x14, 0x88, 0x50, 0x7e, 0xd5, 0x1f, 0xcb, 0xb2, 0xc0, 0x19, 0x00, 0x64, 0xda, + 0x9a, 0x8c, 0xad, 0xcc, 0xf3, 0xe7, 0x25, 0xc3, 0x5a, 0x5f, 0x9c, 0xe5, 0xcf, 0xfc, 0xed, 0x14, + 0x45, 0x25, 0x5e, 0x3b, 0x17, 0xce, 0x49, 0x06, 0xa3, 0xed, 0xfc, 0x00, 0x94, 0xef, 0x37, 0xe9, + 0x9b, 0xcf, 0x7c, 0xc8, 0xcc, 0x12, 0xb1, 0x0c, 0x96, 0xfc, 0x43, 0x9b, 0x00, 0x63, 0x57, 0xb7, + 0x37, 0x94, 0x61, 0xa8, 0xb1, 0x29, 0xd5, 0x62, 0x79, 0x60, 0xd1, 0x85, 0xdc, 0x18, 0x62, 0x04, + 0x8d, 0x15, 0xc3, 0xdf, 0xec, 0xa0, 0x20, 0x28, 0xb8, 0x6b, 0x04, 0x3c, 0x4a, 0xdc, 0x9e, 0x3d, + 0xe6, 0x50, 0x81, 0xee, 0x15, 0x0f, 0x39, 0xcd, 0x63, 0xbb, 0x2b, 0xf3, 0x96, 0xbe, 0x52, 0x37, + 0x8e, 0x83, 0x7b, 0x04, 0xdb, 0xf2, 0x62, 0x02, 0xb1, 0x49, 0xc3, 0x6d, 0x27, 0x80, 0x51, 0x4e, + 0x9a, 0x7e, 0xe1, 0x47, 0xeb, 0x87, 0xf7, 0xd6, 0x58, 0x5f, 0xcc, 0xe7, 0xec, 0x22, 0x4a, 0x2c, + 0xa2, 0x63, 0x4a, 0x2e, 0xed, 0x94, 0xf7, 0x07, 0xe3, 0x41, 0xd9, 0xbb, 0xa5, 0x4e, 0x4a, 0x24, + 0x14, 0xb2, 0x33, 0xfd, 0xaa, 0x72, 0x28, 0x7b, 0x9f, 0xd0, 0x79, 0xb7, 0x75, 0x82, 0xd7, 0x4d, + 0x45, 0x3c, 0xfd, 0xfe, 0x5b, 0x45, 0x1d, 0x76, 0x05, 0x30, 0x21, 0xbd, 0x47, 0x17, 0x16, 0xf2, + 0xcc, 0x77, 0xbe, 0x2c, 0xd7, 0x96, 0x6f, 0x2b, 0x0c, 0x66, 0x2a, 0x31, 0xa8, 0x9c, 0xe6, 0x25, + 0x25, 0x4d, 0xd8, 0x2c, 0xcb, 0x23, 0x82, 0x9c, 0x48, 0xcf, 0x4d, 0x44, 0x94, 0x61, 0xb7, 0x8b, + 0x71, 0x32, 0xab, 0x8d, 0xf8, 0x04, 0x37, 0x4c, 0xc0, 0xff, 0x12, 0x0f, 0x43, 0x25, 0x9a, 0x42, + 0x0a, 0x80, 0x26, 0x9a, 0xa3, 0xaf, 0xc5, 0x9c, 0x4b, 0x7e, 0x4c, 0xe9, 0xb9, 0x2c, 0x89, 0x4d, + 0xa9, 0xd1, 0x10, 0x9b, 0x66, 0xea, 0x4e, 0x4f, 0x7c, 0x80, 0x19, 0x7a, 0x86, 0x3f, 0x96, 0x96, + 0x84, 0xab, 0xb9, 0x7f, 0x8e, 0x2e, 0x96, 0x2b, 0xc3, 0x50, 0xef, 0x90, 0x40, 0x27, 0xb7, 0xa6, + 0x5c, 0xce, 0x52, 0x4c, 0x37, 0x39, 0xed, 0x2d, 0x94, 0xf0, 0x31, 0x4f, 0x46, 0x96, 0xad, 0x21, + 0x91, 0x3e, 0x54, 0xed, 0x5a, 0xf9, 0x50, 0xa9, 0xdf, 0xdc, 0x28, 0x5b, 0x3c, 0xf4, 0xbe, 0x47, + 0x03, 0xf5, 0xc4, 0xa3, 0x52, 0xa9, 0x5b, 0x99, 0xcc, 0xc9, 0x27, 0x3e, 0x5f, 0x7c, 0x2a, 0x1a, + 0x4b, 0xe2, 0xb4, 0xe4, 0x0f, 0x14, 0x03, 0x76, 0x19, 0x35, 0x22, 0x15, 0xb6, 0x1a, 0x32, 0xb5, + 0x68, 0x72, 0x0e, 0xef, 0xbf, 0x88, 0xc5, 0x5d, 0xfc, 0x19, 0x4b, 0xf2, 0x1c, 0xef, 0x35, 0x35, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -4367,9 +4527,9 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA100_sig_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 384, // uncompressed data size (bytes) - 397, // compressed data size (bytes) + 384, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_GA100_sig_prod_data, // compressed data pointer - NV_TRUE, // is pData compressed? + NV_FALSE, // is pData compressed? NV_TRUE, // contain information for file overriding? NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) }, @@ -4389,7 +4549,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA100_sig_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_patch_loc_data[] = { - 0x00, 0x83, 0x00, 0x00, + 0x00, 0x89, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA102.c index 6f49cc5461..08d690ddff 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA102.c @@ -34,2062 +34,2181 @@ // VAR NAME: booter_ucode_data_ga10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 58880 -// COMPRESSED SIZE (bytes): 32804 +// DATA SIZE (bytes): 60416 +// COMPRESSED SIZE (bytes): 34714 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_image_dbg_data[] = { - 0xed, 0xdd, 0x53, 0x93, 0x2c, 0x5d, 0x17, 0x36, 0xea, 0xb6, 0x6d, 0xdb, 0x36, 0x57, 0xdb, 0xb6, - 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xee, 0xd5, 0xc6, 0x6a, 0xdb, 0xdf, 0x7b, 0xfc, - 0x9c, 0xec, 0xf8, 0x62, 0x9f, 0xec, 0x88, 0xdd, 0xd7, 0x1f, 0xa8, 0xa8, 0x8c, 0xcc, 0x31, 0x67, - 0x8e, 0xba, 0x6b, 0x4c, 0x00, 0x80, 0xff, 0x7f, 0xd3, 0x6d, 0xba, 0xa3, 0x04, 0xf9, 0x79, 0x0c, - 0x71, 0x0f, 0x9f, 0x51, 0xce, 0xfe, 0xd1, 0xf1, 0xc1, 0x6d, 0x4c, 0x2d, 0xd7, 0xe9, 0xe2, 0x3e, - 0x6f, 0x38, 0x24, 0xbc, 0x2c, 0x1d, 0xdf, 0x2e, 0xe4, 0x26, 0xcc, 0x99, 0xa8, 0xf5, 0x71, 0x8a, - 0x0e, 0xb1, 0x0d, 0x57, 0x8e, 0x95, 0xbc, 0xed, 0xf0, 0x2f, 0x7a, 0xb4, 0xc7, 0xeb, 0xf2, 0xa5, - 0xfe, 0x67, 0x38, 0x28, 0xf6, 0x9a, 0xf5, 0xd6, 0x75, 0xd2, 0x95, 0x32, 0x16, 0x43, 0x1d, 0xd2, - 0x01, 0x59, 0xed, 0x9d, 0x6a, 0x7d, 0x45, 0xb1, 0xd9, 0xb6, 0x29, 0x64, 0x81, 0x9d, 0xc4, 0x12, - 0x00, 0x59, 0x1f, 0xca, 0xdb, 0x50, 0x83, 0xed, 0xb9, 0x51, 0x56, 0xa8, 0x70, 0x31, 0x5c, 0x7d, - 0x72, 0xf8, 0x4f, 0x5b, 0x88, 0x3b, 0x11, 0x5d, 0xcf, 0x6a, 0xa4, 0xeb, 0x04, 0x52, 0xe3, 0x56, - 0x00, 0x8c, 0x53, 0x7a, 0x30, 0x72, 0x6e, 0xc9, 0x57, 0xf6, 0x80, 0x04, 0x5e, 0xc4, 0x15, 0x8a, - 0x02, 0xc6, 0x60, 0x96, 0x43, 0x03, 0xa3, 0xde, 0x6f, 0x89, 0x63, 0x65, 0x34, 0x34, 0x88, 0x88, - 0xdd, 0xea, 0x62, 0x1d, 0x51, 0xa3, 0x79, 0x42, 0xfc, 0xa0, 0xa5, 0xf4, 0xfe, 0x11, 0xa9, 0xd8, - 0x7c, 0x42, 0x6e, 0xfe, 0x1e, 0x4c, 0xaf, 0xb8, 0x0b, 0xb9, 0x3a, 0xe1, 0x79, 0xb6, 0xf7, 0x3a, - 0x95, 0x0f, 0xec, 0x43, 0x9c, 0xb0, 0x92, 0x86, 0x32, 0x61, 0xa0, 0x86, 0xc1, 0x7f, 0x61, 0x74, - 0x1d, 0x58, 0xdb, 0xba, 0xe0, 0xcc, 0x15, 0x23, 0xe2, 0xab, 0x4d, 0xd0, 0x64, 0xdf, 0xcb, 0x13, - 0x1a, 0x84, 0xa1, 0xb1, 0x80, 0xf7, 0x0f, 0x1f, 0xfa, 0xca, 0xba, 0x2e, 0xdc, 0x06, 0xaa, 0x2a, - 0x11, 0x24, 0x81, 0x63, 0x96, 0x6f, 0x06, 0x20, 0x76, 0xcb, 0x9a, 0x80, 0xf2, 0x58, 0x74, 0xc3, - 0x92, 0xe7, 0xea, 0x9b, 0x75, 0xf2, 0x75, 0x08, 0x33, 0x04, 0x0c, 0xf5, 0xf8, 0xea, 0xa8, 0xcb, - 0xc9, 0x71, 0xb3, 0x3f, 0xa7, 0x53, 0xad, 0x0f, 0x55, 0xc4, 0x77, 0x99, 0xc9, 0x38, 0x84, 0x45, - 0x56, 0x12, 0x3a, 0x38, 0x95, 0x2d, 0x41, 0xbd, 0x80, 0x4e, 0x0f, 0xa9, 0xc0, 0x29, 0x0b, 0x13, - 0x07, 0x58, 0xa9, 0x6b, 0x54, 0xe6, 0x2d, 0x8b, 0x96, 0x44, 0x09, 0xc5, 0xb6, 0x69, 0x35, 0xc1, - 0x30, 0xe4, 0x13, 0xf1, 0xe3, 0xc7, 0x27, 0x82, 0x8d, 0x4a, 0xee, 0xa7, 0xbb, 0x77, 0x39, 0xc7, - 0xfa, 0x66, 0x39, 0xb1, 0x89, 0x15, 0x3e, 0x8a, 0xff, 0x5e, 0xc8, 0xe8, 0xc2, 0xf6, 0xdb, 0x12, - 0x5e, 0xdf, 0xfe, 0x28, 0x65, 0xe0, 0x97, 0x60, 0xe9, 0xfe, 0xdb, 0xbc, 0x75, 0x08, 0x2e, 0xc5, - 0xb6, 0x03, 0xc1, 0xcb, 0xbd, 0x54, 0xf1, 0x2d, 0x40, 0x08, 0x16, 0x71, 0xba, 0x86, 0xfa, 0xe9, - 0xa7, 0x26, 0xcf, 0x1e, 0xdd, 0x73, 0x58, 0xae, 0x99, 0xe6, 0x44, 0xa5, 0xd6, 0x89, 0x04, 0x87, - 0x5a, 0xe8, 0x22, 0x50, 0x8d, 0x9c, 0xd4, 0x4b, 0x1a, 0x4b, 0x3d, 0x4f, 0x2b, 0xe8, 0x56, 0xbd, - 0xc9, 0x88, 0xc2, 0xc9, 0xfb, 0xad, 0xa9, 0x50, 0x6a, 0xdd, 0xd6, 0xd2, 0x96, 0xbb, 0x6b, 0x68, - 0x1b, 0x4f, 0x1b, 0x35, 0xc2, 0x79, 0x25, 0xae, 0x61, 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x3f, + 0xf9, 0x0f, 0x94, 0xa6, 0x6a, 0x41, 0x00, 0xec, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2099,8 +2218,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA102_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 58880, // uncompressed data size (bytes) - 32804, // compressed data size (bytes) + 60416, // uncompressed data size (bytes) + 34714, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_GA102_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -2122,8 +2241,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA102_image_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x6e, 0x01, 0xe2, 0x24, 0x08, 0x13, 0x4c, 0x34, 0x43, 0x69, - 0x20, 0x00, 0x00, 0xef, 0x1f, 0x77, 0xe5, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0xee, 0x02, 0xe2, 0x24, 0x08, 0x13, 0x4c, 0x74, 0x42, 0x69, + 0x20, 0x00, 0x00, 0x26, 0xcc, 0x03, 0x79, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2151,2062 +2270,2181 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA102_header_dbg_storage_pvt; // VAR NAME: booter_ucode_data_ga10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 58880 -// COMPRESSED SIZE (bytes): 32802 +// DATA SIZE (bytes): 60416 +// COMPRESSED SIZE (bytes): 34716 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_image_prod_data[] = { - 0xed, 0xdd, 0x53, 0x93, 0x28, 0x5b, 0x17, 0x2e, 0xe8, 0xb2, 0xed, 0x55, 0xb6, 0x6d, 0xdb, 0xb6, - 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0x5b, 0xab, 0x6c, 0xdb, 0xae, 0xf3, 0x5d, 0xef, 0x9b, - 0x8e, 0x13, 0x7d, 0xd3, 0x11, 0xbd, 0x9e, 0x3f, 0x90, 0x91, 0x9a, 0x39, 0x73, 0xe4, 0x9b, 0x63, - 0x02, 0x00, 0xfc, 0xff, 0xdb, 0x4c, 0x20, 0x0c, 0x12, 0x9b, 0x6b, 0x06, 0x39, 0xaf, 0x20, 0x59, - 0xe1, 0xba, 0x9b, 0x8d, 0x05, 0xde, 0x3a, 0xdf, 0x94, 0x6d, 0x0f, 0xbf, 0x81, 0x75, 0x00, 0x4f, - 0x51, 0x49, 0xa7, 0x0a, 0x62, 0xd7, 0xa3, 0x7e, 0x55, 0x32, 0xc1, 0x11, 0x2b, 0xf2, 0x82, 0x81, - 0xcd, 0x8f, 0x26, 0xc1, 0xc8, 0xde, 0x22, 0x1d, 0x64, 0x10, 0xd0, 0x90, 0x93, 0xb6, 0xe2, 0xd2, - 0x52, 0x03, 0x5b, 0x6f, 0xee, 0xfe, 0x41, 0x49, 0x0c, 0xd1, 0xe5, 0x07, 0x53, 0x76, 0xd1, 0x32, - 0xfe, 0x59, 0x51, 0xf3, 0x53, 0xdb, 0xb1, 0xb8, 0x3d, 0xf2, 0x81, 0x3f, 0x41, 0x39, 0x0c, 0x56, - 0x4e, 0xdf, 0xce, 0x92, 0x7f, 0x1e, 0x3f, 0x6d, 0x6b, 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0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xe0, 0x7f, 0xf2, 0x1f, 0xa7, 0x87, 0x36, 0x2c, 0x00, 0xec, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -4216,8 +4454,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA102_image_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 58880, // uncompressed data size (bytes) - 32802, // compressed data size (bytes) + 60416, // uncompressed data size (bytes) + 34716, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_GA102_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -4239,8 +4477,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA102_image_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x6e, 0x01, 0xe2, 0x24, 0x08, 0x13, 0x4c, 0x34, 0x43, 0x69, - 0x20, 0x00, 0x00, 0xef, 0x1f, 0x77, 0xe5, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0xee, 0x02, 0xe2, 0x24, 0x08, 0x13, 0x4c, 0x74, 0x42, 0x69, + 0x20, 0x00, 0x00, 0x26, 0xcc, 0x03, 0x79, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -4266,62 +4504,61 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA102_header_prod_storage_pvt; // FILE NAME: kernel/inc/gsprm/bin/booter/ga10x/load/g_booteruc_load_ga10x_ga102_rsa3k_0_sig.h // FILE TYPE: TEXT // VAR NAME: booter_load_sig_dbg_ga10x -// COMPRESSION: YES +// COMPRESSION: NO // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 768 -// COMPRESSED SIZE (bytes): 781 +// COMPRESSED SIZE (bytes): N/A // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_sig_dbg_data[] = { - 0x01, 0x00, 0x03, 0xff, 0xfc, 0x20, 0x63, 0x89, 0xa9, 0x68, 0x99, 0x1d, 0xc9, 0x2c, 0x56, 0xcd, - 0xe3, 0x7f, 0xe1, 0x40, 0x26, 0x97, 0x42, 0xf6, 0x0d, 0x36, 0x34, 0x9b, 0xb8, 0x0d, 0x23, 0x15, - 0x9c, 0x4c, 0x9e, 0x49, 0x98, 0x32, 0xe2, 0xfc, 0x8f, 0x01, 0x07, 0xf4, 0x54, 0xad, 0x08, 0x8a, - 0x0a, 0xf0, 0x65, 0xea, 0xbd, 0x07, 0x4b, 0xbf, 0xe3, 0xfd, 0xaa, 0xfd, 0x97, 0x26, 0xc6, 0x7c, - 0x59, 0xb3, 0xef, 0x03, 0xab, 0xb5, 0x1f, 0x2d, 0x86, 0x79, 0x57, 0x22, 0xfd, 0xf0, 0xe1, 0x68, - 0x43, 0x83, 0xa4, 0x0d, 0xf8, 0xce, 0xe5, 0x43, 0x79, 0xa4, 0xaa, 0x4c, 0xad, 0xc9, 0x3b, 0xd1, - 0x39, 0xf8, 0xe7, 0x03, 0xdf, 0xaa, 0x6e, 0x2e, 0xb8, 0x77, 0x4b, 0x2d, 0x31, 0xcf, 0x59, 0x15, - 0x70, 0x66, 0x91, 0xa0, 0xeb, 0x08, 0xad, 0xcd, 0x69, 0x12, 0x7d, 0xf0, 0xdc, 0x01, 0x51, 0x47, - 0x8c, 0xdb, 0xaf, 0xf1, 0xe2, 0x85, 0x01, 0x4b, 0x96, 0x42, 0xf9, 0x48, 0xd4, 0x1d, 0x04, 0x05, - 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pointer - NV_TRUE, // is pData compressed? + NV_FALSE, // is pData compressed? NV_TRUE, // contain information for file overriding? NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) }, @@ -4350,37 +4587,37 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA102_sig_dbg_storage_pvt; // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 768 -// COMPRESSED SIZE (bytes): 421 +// COMPRESSED SIZE (bytes): 420 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_sig_prod_data[] = { - 0x5b, 0x25, 0xa4, 0xae, 0xba, 0xac, 0x71, 0x5e, 0xc4, 0x86, 0x83, 0xfd, 0xdb, 0x67, 0x74, 0x9e, - 0xe0, 0xda, 0x2b, 0x7e, 0xf9, 0xca, 0x82, 0xdf, 0x6b, 0x1f, 0x68, 0x78, 0x5d, 0xf4, 0x3d, 0x1b, - 0xec, 0x6f, 0xeb, 0xed, 0x16, 0x54, 0x77, 0x30, 0xda, 0x6a, 0x7d, 0x44, 0xf6, 0xca, 0xe7, 0x4b, - 0x67, 0xe8, 0xe6, 0xd9, 0xdd, 0x88, 0xfd, 0x1c, 0x1a, 0x10, 0x7b, 0xda, 0xb1, 0xf9, 0x92, 0x8d, - 0xa4, 0x5e, 0xdf, 0x86, 0xff, 0xaa, 0x72, 0xf3, 0xf8, 0x3d, 0x72, 0x03, 0x56, 0x67, 0x64, 0x65, - 0x4c, 0xfe, 0x6a, 0x3f, 0xbd, 0xe4, 0x6b, 0x64, 0xeb, 0xf5, 0x3b, 0xef, 0xfc, 0xa7, 0x9c, 0x3f, - 0xce, 0xdd, 0x34, 0xed, 0xee, 0xa9, 0xf9, 0x27, 0xaf, 0x3d, 0x5e, 0x10, 0xae, 0x50, 0x57, 0xf6, - 0xef, 0xe8, 0xdf, 0xed, 0x75, 0x4e, 0x0f, 0x57, 0xad, 0x58, 0x14, 0xbf, 0x6c, 0xf9, 0x54, 0xbd, - 0x27, 0x37, 0x0e, 0xbd, 0x9a, 0x29, 0x91, 0x58, 0xa2, 0x37, 0x61, 0xea, 0xee, 0x53, 0xeb, 0xb7, - 0x5c, 0x29, 0x6d, 0xf4, 0x2f, 0x14, 0xef, 0xf7, 0xdd, 0x7d, 0x78, 0x09, 0xa7, 0xc6, 0x89, 0x1d, - 0x2e, 0x27, 0x83, 0x15, 0x8a, 0x17, 0x58, 0xae, 0x9a, 0xf7, 0xe7, 0xf7, 0x9b, 0xf0, 0x76, 0xb1, - 0xb5, 0xdb, 0x97, 0xfc, 0xb0, 0xe3, 0x6d, 0xba, 0x28, 0xe3, 0xdd, 0x94, 0xd1, 0xf5, 0x67, 0x4b, - 0x88, 0x78, 0x85, 0xf0, 0x64, 0x03, 0xe3, 0x9f, 0x9c, 0xc7, 0xf3, 0xae, 0xac, 0xfd, 0xb5, 0xee, - 0xf7, 0xec, 0xd2, 0x75, 0x65, 0x1e, 0xce, 0xdf, 0xff, 0xb4, 0x9f, 0xbf, 0x59, 0xc9, 0x25, 0x76, - 0xe0, 0x89, 0xb9, 0x7c, 0xe1, 0x5d, 0xe7, 0xdb, 0xe1, 0x6d, 0x09, 0x1e, 0x2b, 0xae, 0x55, 0xb9, - 0x99, 0x4e, 0x35, 0x4e, 0xee, 0xd8, 0xb7, 0x22, 0x97, 0xd3, 0xf2, 0x57, 0x87, 0x4a, 0x5f, 0x68, - 0xc2, 0x97, 0x0b, 0xea, 0xcf, 0xd7, 0x85, 0x9f, 0x99, 0xf3, 0xac, 0xc1, 0xe1, 0x77, 0xab, 0xed, - 0xad, 0xac, 0xac, 0x29, 0xb9, 0x12, 0x45, 0x97, 0x2b, 0x9f, 0x19, 0x6d, 0xff, 0xe2, 0x2f, 0x73, - 0xb7, 0x65, 0xfe, 0xaf, 0x17, 0x3d, 0x2e, 0x07, 0xcd, 0x16, 0xe8, 0x06, 0x48, 0xdf, 0x5e, 0xa5, - 0xea, 0xf7, 0x76, 0x97, 0x7f, 0xa5, 0xf6, 0xae, 0x0d, 0xaa, 0xa9, 0x7a, 0xc5, 0x7d, 0xdf, 0x13, - 0x0c, 0xe2, 0x2f, 0x4e, 0x12, 0xbf, 0xfa, 0x31, 0xb3, 0x54, 0x2f, 0xec, 0x5b, 0xe6, 0xd4, 0x85, - 0x3a, 0xef, 0x2f, 0x99, 0xb7, 0xac, 0xcf, 0x2b, 0x99, 0xf0, 0x6b, 0xc9, 0x07, 0x9f, 0x64, 0x79, - 0xd1, 0x69, 0xab, 0xc3, 0x8f, 0x14, 0x73, 0xf8, 0x99, 0x94, 0x5a, 0x47, 0x5d, 0x9e, 0x16, 0xb4, - 0x70, 0xb7, 0x39, 0xcb, 0x91, 0x03, 0xcc, 0xa2, 0xff, 0x6a, 0x5e, 0x7c, 0xee, 0x4b, 0x9d, 0xa2, - 0xfc, 0xaa, 0xe7, 0xc1, 0xea, 0x6d, 0x0b, 0x2a, 0xfa, 0x35, 0x94, 0xb7, 0xca, 0x9a, 0xde, 0xbe, - 0x27, 0x18, 0x3a, 0x31, 0x49, 0x87, 0x95, 0x61, 0x14, 0x0c, 0x28, 0x00, 0x00, 0x28, 0xef, 0x46, - 0x84, 0x00, 0x03, 0x00, 0x00, + 0x7b, 0xea, 0xd8, 0xcc, 0x32, 0x67, 0x62, 0x6e, 0xaf, 0x9c, 0xbc, 0x76, 0xca, 0x99, 0x09, 0x1b, + 0x0e, 0x3e, 0x13, 0x2a, 0x50, 0xda, 0x79, 0x78, 0x4f, 0xe7, 0x1d, 0x37, 0xcb, 0x5f, 0x7a, 0x77, + 0x95, 0x83, 0x37, 0xf9, 0x4d, 0xba, 0x77, 0xed, 0xc2, 0x0e, 0x81, 0x10, 0xc1, 0x7b, 0x8c, 0x67, + 0xbb, 0x8c, 0x74, 0x6e, 0xe9, 0xb4, 0x6e, 0x72, 0xf9, 0xab, 0x38, 0xa3, 0xf5, 0x47, 0xd4, 0x3a, + 0xbb, 0xaf, 0x16, 0x7f, 0x16, 0x75, 0x38, 0xb9, 0x4e, 0xbd, 0xe8, 0x70, 0x26, 0xcc, 0xf2, 0x74, + 0x92, 0xd5, 0x06, 0x4b, 0x25, 0xb7, 0x64, 0x46, 0xf1, 0xd4, 0xa9, 0xe1, 0xe5, 0xac, 0x66, 0xb3, + 0x27, 0xcf, 0xff, 0x32, 0xf9, 0xd9, 0x45, 0x47, 0x4d, 0xf3, 0x27, 0x73, 0x2d, 0x1d, 0x1f, 0xbf, + 0x64, 0xfd, 0x18, 0xcb, 0x22, 0xe7, 0xad, 0x2b, 0xbd, 0xbf, 0x9e, 0xdb, 0x55, 0x77, 0xe6, 0xec, + 0xf6, 0x8e, 0x4f, 0x09, 0x9b, 0xec, 0xdf, 0xa9, 0x7c, 0x9a, 0xa4, 0xb3, 0x7e, 0xbf, 0xa9, 0x43, + 0xd2, 0x86, 0x83, 0x7f, 0x3b, 0x4b, 0x8f, 0xba, 0x48, 0xf5, 0x7f, 0xf1, 0x73, 0xfa, 0x99, 0x7e, + 0x7a, 0xd2, 0xc3, 0x93, 0x4f, 0x66, 0x2d, 0x79, 0xb0, 0xf6, 0x9f, 0xb8, 0xe6, 0xdd, 0x53, 0x3d, + 0x65, 0xbb, 0x94, 0x16, 0xbb, 0x5f, 0xb8, 0x56, 0xbf, 0xef, 0xe6, 0xa7, 0x6f, 0xff, 0x25, 0x76, + 0x24, 0xec, 0xea, 0xcc, 0x59, 0xd4, 0x37, 0xf1, 0xa1, 0xcd, 0x62, 0x55, 0x96, 0x05, 0xe5, 0x93, + 0xa4, 0x16, 0xea, 0x09, 0x46, 0x5f, 0x6f, 0x7b, 0x36, 0xef, 0xe4, 0xcd, 0x89, 0xdf, 0xd4, 0x27, + 0x1f, 0xde, 0xbd, 0x33, 0xb7, 0xf3, 0x44, 0xd0, 0x25, 0xf7, 0x99, 0xff, 0x22, 0xbd, 0xfd, 0xa3, + 0x9f, 0x86, 0xad, 0x79, 0x9d, 0x36, 0x63, 0x93, 0xff, 0x09, 0x66, 0x8d, 0x3d, 0xdf, 0x64, 0x7d, + 0x22, 0xd7, 0xe7, 0x73, 0x7d, 0xf9, 0xf1, 0x5a, 0x6b, 0x95, 0x54, 0xab, 0x44, 0x43, 0x5a, 0x64, + 0xa5, 0xc0, 0xda, 0x2b, 0x0c, 0x5d, 0x2c, 0xcf, 0x05, 0x4f, 0xb5, 0x9a, 0x33, 0x2b, 0x4e, 0x38, + 0xeb, 0xac, 0xb2, 0xfc, 0xd7, 0x93, 0x2d, 0xdd, 0x6b, 0x15, 0x39, 0xcd, 0x73, 0xe7, 0xe6, 0x8b, + 0xae, 0x3a, 0x63, 0xb7, 0xd8, 0x43, 0xe2, 0x89, 0x61, 0x8c, 0xad, 0x1c, 0x57, 0xe5, 0x2d, 0xa6, + 0x69, 0xef, 0xbe, 0x5f, 0x7f, 0x53, 0xaf, 0x5e, 0xb0, 0xa4, 0xeb, 0x4d, 0x92, 0x58, 0xa9, 0xd7, + 0xe6, 0xc7, 0x3a, 0x7d, 0xb6, 0xaf, 0xa4, 0x04, 0xf4, 0x8f, 0x8a, 0x14, 0xea, 0x57, 0xee, 0x79, + 0xdf, 0x99, 0x55, 0xc4, 0x1a, 0xb6, 0x37, 0x78, 0xf6, 0xa5, 0xcb, 0xb7, 0xde, 0x4e, 0x14, 0xd2, + 0xb4, 0xc9, 0xe7, 0xbd, 0x9e, 0x7f, 0x79, 0xa3, 0xbb, 0xdb, 0x0d, 0x7e, 0xd3, 0xa2, 0xf8, 0xf7, + 0x8f, 0xe6, 0xa7, 0x6d, 0x65, 0x3e, 0x7d, 0x65, 0xdb, 0xbb, 0xe6, 0x82, 0x26, 0x81, 0x97, 0x1b, + 0x6a, 0x85, 0xe7, 0x55, 0xb2, 0xed, 0x65, 0x18, 0x05, 0x03, 0x0a, 0x00, 0x8d, 0xa3, 0xa2, 0x0b, + 0x00, 0x03, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -4391,7 +4628,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA102_sig_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 768, // uncompressed data size (bytes) - 421, // compressed data size (bytes) + 420, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_GA102_sig_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -4413,7 +4650,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA102_sig_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_patch_loc_data[] = { - 0x10, 0x84, 0x00, 0x00, + 0x10, 0x8a, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_AD102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_AD102.c index 09b9abdd98..87a52b14e9 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_AD102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_AD102.c @@ -34,1169 +34,1278 @@ // VAR NAME: booter_ucode_data_ad10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 38912 -// COMPRESSED SIZE (bytes): 18517 +// DATA SIZE (bytes): 40704 +// COMPRESSED SIZE (bytes): 20270 // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_AD102_image_dbg_data[] = { - 0xed, 0xdc, 0x65, 0x6c, 0x24, 0x4b, 0x1b, 0x18, 0x6a, 0x33, 0x33, 0xaf, 0x99, 0xd9, 0x6b, 0x66, - 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x58, 0x33, 0x33, 0x33, 0x33, 0x33, 0xdb, - 0x6b, 0x66, 0xf6, 0x3d, 0xb9, 0xf9, 0xa2, 0x44, 0x47, 0xc9, 0xaf, 0x44, 0x8a, 0x74, 0xaf, 0x1f, - 0xe9, 0x55, 0x57, 0xf5, 0x94, 0x54, 0x5d, 0xd5, 0xa3, 0x9e, 0xb7, 0xa6, 0x7b, 0x06, 0x00, 0xe0, - 0xff, 0xdf, 0x74, 0x1a, 0x6e, 0x29, 0x40, 0xbe, 0x1f, 0x82, 0xdd, 0xc2, 0xa6, 0x94, 0xb2, 0xbe, - 0xb5, 0xbd, 0x71, 0xea, 0x53, 0xca, 0xb4, 0x3b, 0x38, 0xcf, 0xea, 0x0e, 0x08, 0xfe, 0x96, 0x8c, - 0x6e, 0x16, 0x70, 0x12, 0x64, 0x8f, 0x55, 0x7b, 0x3b, 0x46, 0x05, 0xdb, 0x84, 0x29, 0xc5, 0x48, - 0xdc, 0xb4, 0xf9, 0x15, 0x3e, 0xd8, 0xe1, 0x76, 0xf8, 0x50, 0x5d, 0x18, 0xf4, 0x8b, 0xbe, 0x64, - 0xbe, 0x76, 0x1c, 0x77, 0x24, 0x8f, 0x44, 0x53, 0x05, 0xb7, 0x41, 0x56, 0x7a, 0xa5, 0x58, 0x5d, - 0x92, 0xaf, 0xb7, 0xac, 0x0b, 0x9a, 0x63, 0x25, 0x32, 0xf9, 0x43, 0xd6, 0x86, 0xf0, 0xd4, 0x55, - 0x61, 0x79, 0xac, 0x95, 0x16, 0xc8, 0x9f, 0x0f, 0x56, 0x1e, 0x1f, 0x5c, 0x68, 0x09, 0x72, 0x26, - 0xa0, 0xeb, 0x5a, 0x0e, 0x75, 0x1c, 0x43, 0xaa, 0xdf, 0xf0, 0x83, 0xb1, 0x4b, 0xf5, 0x47, 0xcc, - 0x2c, 0xf8, 0xc8, 0xec, 0x13, 0xc3, 0x0b, 0xbb, 0x40, 0x91, 0xc3, 0xe8, 0x4f, 0xb3, 0xa9, 0x63, - 0xd4, 0xfa, 0x2e, 0xb0, 0x2d, 0x0d, 0x87, 0x04, 0x12, 0xb2, 0x5a, 0x9e, 0xaf, 0x22, 0xaa, 0x37, - 0x8e, 0x89, 0xed, 0x37, 0x95, 0xdc, 0x3d, 0x20, 0x15, 0x99, 0x8d, 0xc9, 0xce, 0xde, 0x81, 0xe9, - 0x16, 0x75, 0x20, 0x57, 0xc6, 0x3f, 0x4d, 0x77, 0x5f, 0xa5, 0xf0, 0x82, 0xbd, 0x8b, 0x11, 0x54, - 0x50, 0x53, 0xc4, 0xf7, 0x55, 0xd1, 0xf9, 0xcd, 0x0d, 0xaf, 0x02, 0x6b, 0x59, 0xe5, 0x9f, 0xba, - 0x60, 0x84, 0x0b, 0x82, 0xc4, 0x4a, 0x36, 0x2e, 0xe2, 0x46, 0x97, 0xc7, 0xee, 0xe3, 0x73, 0x79, - 0xc8, 0x80, 0x2e, 0xad, 0xea, 0xc0, 0xad, 0xa1, 0xaa, 0x10, 0x42, 0xe2, 0x3b, 0x64, 0xfa, 0xa4, - 0x03, 0x62, 0x35, 0xad, 0xf0, 0x2b, 0x8d, 0x44, 0xd5, 0x2d, 0x78, 0x2c, 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defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 38912, // uncompressed data size (bytes) - 18517, // compressed data size (bytes) + 40704, // uncompressed data size (bytes) + 20270, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_AD102_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1229,8 +1338,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_AD102_image_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_AD102_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0xf6, 0x04, 0x62, 0x3f, 0x08, 0x13, 0x4c, 0x78, 0x40, 0x69, - 0x20, 0x00, 0x00, 0x06, 0x07, 0x25, 0x94, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x0e, 0x00, 0x62, 0x3f, 0x08, 0x13, 0x4c, 0xf8, 0x43, 0x69, + 0x20, 0x00, 0x00, 0x1b, 0x74, 0x64, 0x4f, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1258,1169 +1367,1279 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_AD102_header_dbg_storage_pvt // VAR NAME: booter_ucode_data_ad10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 38912 -// COMPRESSED SIZE (bytes): 18515 +// DATA SIZE (bytes): 40704 +// COMPRESSED SIZE (bytes): 20273 // static BINDATA_CONST NvU8 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0xf4, 0x3f, 0x81, 0xf6, + 0x4f, 0x10, 0xfc, 0x13, 0xce, 0xff, 0xb4, 0xc1, 0xf7, 0x5f, 0xda, 0xfa, 0x27, 0x0f, 0x04, 0xf8, + 0xff, 0x5e, 0x9f, 0xf2, 0x7f, 0xa1, 0x2d, 0x54, 0x80, 0xff, 0xfa, 0xfc, 0xa3, 0xfe, 0xbb, 0x76, + 0x40, 0x20, 0xfe, 0xc7, 0xf5, 0x53, 0xfe, 0xbb, 0x7c, 0xea, 0x3f, 0x91, 0xf6, 0x4f, 0x88, 0xfe, + 0x13, 0x62, 0xff, 0x84, 0xf8, 0x3f, 0x21, 0xf1, 0x9f, 0xc7, 0xa4, 0xfe, 0x93, 0x4a, 0xff, 0xab, + 0x1d, 0xb9, 0xff, 0xd6, 0x8e, 0xd4, 0x7f, 0x5e, 0x03, 0x80, 0x7f, 0x4e, 0x31, 0x80, 0xa2, 0x30, + 0xfd, 0xff, 0x42, 0x1f, 0xfe, 0x77, 0xf2, 0x7f, 0x01, 0x5d, 0x79, 0x1b, 0xa0, 0x00, 0x9f, 0x00, + 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2430,8 +2649,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_AD102_image_prod_storage_pvt #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 38912, // uncompressed data size (bytes) - 18515, // compressed data size (bytes) + 40704, // uncompressed data size (bytes) + 20273, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_AD102_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -2453,8 +2672,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_AD102_image_prod_storage_pvt // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_AD102_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0xf6, 0x04, 0x62, 0x3f, 0x08, 0x13, 0x4c, 0x78, 0x40, 0x69, - 0x20, 0x00, 0x00, 0x06, 0x07, 0x25, 0x94, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x0e, 0x00, 0x62, 0x3f, 0x08, 0x13, 0x4c, 0xf8, 0x43, 0x69, + 0x20, 0x00, 0x00, 0x1b, 0x74, 0x64, 0x4f, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2480,62 +2699,61 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_AD102_header_prod_storage_pv // FILE NAME: kernel/inc/gsprm/bin/booter/ad10x/unload/g_booteruc_unload_ad10x_ad10x_rsa3k_0_sig.h // FILE TYPE: TEXT // VAR NAME: booter_unload_sig_dbg_ad10x -// COMPRESSION: YES +// COMPRESSION: NO // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 768 -// COMPRESSED SIZE (bytes): 781 +// COMPRESSED SIZE (bytes): N/A // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_AD102_sig_dbg_data[] = { - 0x01, 0x00, 0x03, 0xff, 0xfc, 0xc7, 0xff, 0xb2, 0xb1, 0x47, 0xa0, 0x6a, 0x45, 0x9a, 0x95, 0x7d, - 0x78, 0x63, 0xf1, 0xc2, 0x85, 0x97, 0x46, 0xdc, 0xa0, 0x4b, 0x5a, 0x01, 0xc6, 0xf5, 0x50, 0x93, - 0x6c, 0x25, 0xe4, 0xc3, 0x25, 0xaf, 0xd9, 0xe6, 0x74, 0xc8, 0x73, 0x8e, 0xfc, 0xe1, 0xca, 0xfc, - 0x4d, 0xc3, 0xca, 0x52, 0xee, 0x53, 0xe1, 0xa4, 0x33, 0x3d, 0xb0, 0xaa, 0x2a, 0x36, 0x92, 0xed, - 0xd2, 0x48, 0xdf, 0x0b, 0x71, 0xdc, 0x78, 0x6f, 0x70, 0xfe, 0x83, 0x78, 0xeb, 0xcc, 0xdb, 0xd9, - 0xf7, 0xf3, 0x13, 0x37, 0xd2, 0xd6, 0x36, 0xd1, 0x62, 0x04, 0xa2, 0x4d, 0x13, 0x44, 0x69, 0x5e, - 0x6b, 0xd2, 0x45, 0x02, 0x9a, 0x46, 0x11, 0x22, 0x19, 0x92, 0x9d, 0x4e, 0x7c, 0x2b, 0xba, 0x24, - 0x0f, 0x8c, 0x3c, 0x8f, 0xd3, 0xf8, 0x77, 0xd7, 0x0f, 0xdf, 0x79, 0x9c, 0x23, 0x0e, 0x10, 0x5e, - 0xd1, 0x43, 0x0d, 0x8f, 0xa2, 0x5b, 0xc4, 0xe0, 0x69, 0x70, 0xf2, 0x18, 0xa5, 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0x61, 0x12, 0x76, 0x9a, 0x2c, 0xbd, 0x66, 0x23, + 0x95, 0xa1, 0x98, 0x72, 0xea, 0x9c, 0xd2, 0x64, 0x8d, 0x29, 0xcf, 0x62, 0x3f, 0x39, 0xb6, 0xb4, + 0xed, 0xd3, 0xc2, 0x45, 0xf5, 0x6b, 0xef, 0xb8, 0x9f, 0xea, 0x24, 0xa7, 0xf2, 0x2d, 0x43, 0xa3, + 0xfc, 0xa9, 0xcc, 0xd0, 0x4d, 0x0d, 0x49, 0xbe, 0xea, 0xed, 0xd0, 0xdb, 0x91, 0xec, 0x69, 0x14, + 0xc7, 0xe2, 0xf1, 0xf4, 0x99, 0x78, 0x97, 0xc2, 0x92, 0x75, 0x6c, 0x4e, 0xf4, 0x74, 0x4e, 0xa8, + 0x9d, 0x0c, 0x5f, 0xcf, 0x02, 0x61, 0x52, 0x52, 0x2f, 0xe2, 0x1f, 0x19, 0x33, 0xaa, 0x0b, 0xf4, + 0x91, 0x8f, 0x57, 0xa9, 0x40, 0x5c, 0xdd, 0x0b, 0x42, 0xb6, 0x4a, 0x3c, 0x33, 0x5f, 0x93, 0x40, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2546,9 +2764,9 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_AD102_sig_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 768, // uncompressed data size (bytes) - 781, // compressed data size (bytes) + 768, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_AD102_sig_dbg_data, // compressed data pointer - NV_TRUE, // is pData compressed? + NV_FALSE, // is pData compressed? NV_TRUE, // contain information for file overriding? NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) }, @@ -2561,62 +2779,61 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_AD102_sig_dbg_storage_pvt; // FILE NAME: kernel/inc/gsprm/bin/booter/ad10x/unload/g_booteruc_unload_ad10x_ad10x_rsa3k_0_sig.h // FILE TYPE: TEXT // VAR NAME: booter_unload_sig_prod_ad10x -// COMPRESSION: YES +// COMPRESSION: NO // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 768 -// COMPRESSED SIZE (bytes): 781 +// COMPRESSED SIZE (bytes): N/A // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_AD102_sig_prod_data[] = { - 0x01, 0x00, 0x03, 0xff, 0xfc, 0xc0, 0x85, 0x1c, 0x47, 0x90, 0x57, 0x66, 0xc8, 0x4b, 0x5f, 0x4c, - 0x5a, 0xee, 0x97, 0xde, 0x6d, 0x28, 0x5c, 0xa5, 0x41, 0xef, 0xd4, 0xd7, 0x81, 0x6d, 0x0f, 0x48, - 0x11, 0x27, 0xd0, 0xb6, 0xf9, 0xc8, 0x6a, 0xa5, 0xfe, 0xb5, 0x5a, 0x3d, 0xeb, 0xbd, 0x5b, 0x14, - 0x5e, 0x81, 0xbb, 0x74, 0x8f, 0x60, 0xd3, 0x16, 0x25, 0x88, 0x15, 0x6f, 0x57, 0x1f, 0x84, 0xb7, - 0xb1, 0x8d, 0xfe, 0x47, 0xaf, 0x50, 0x9f, 0x1a, 0xfe, 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0x41, 0x02, 0xb1, 0xc2, 0x2b, 0x39, 0xe1, 0xc4, 0x03, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2627,9 +2844,9 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_AD102_sig_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 768, // uncompressed data size (bytes) - 781, // compressed data size (bytes) + 768, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_AD102_sig_prod_data, // compressed data pointer - NV_TRUE, // is pData compressed? + NV_FALSE, // is pData compressed? NV_TRUE, // contain information for file overriding? NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) }, @@ -2649,7 +2866,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_AD102_sig_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_AD102_patch_loc_data[] = { - 0x10, 0x49, 0x00, 0x00, + 0x10, 0x50, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA100.c index a96becc551..a80671222e 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA100.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA100.c @@ -34,1141 +34,1223 @@ // VAR NAME: booter_ucode_data_ga100 // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 38400 -// COMPRESSED SIZE (bytes): 18066 +// DATA SIZE (bytes): 39936 +// COMPRESSED SIZE (bytes): 19390 // static BINDATA_CONST NvU8 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0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, - 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, - 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, - 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, - 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0xfe, 0x5f, 0xf0, 0xff, 0x01, 0x9d, 0x80, 0x5b, 0x46, 0x00, 0x96, - 0x00, 0x00, + 0xfd, 0xfa, 0x7f, 0xc0, 0xff, 0x07, 0xc5, 0x08, 0xd3, 0xb2, 0x00, 0x9c, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1178,8 +1260,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA100_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 38400, // uncompressed data size (bytes) - 18066, // compressed data size (bytes) + 39936, // uncompressed data size (bytes) + 19390, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_GA100_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1201,8 +1283,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA100_image_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA100_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x76, 0x07, 0x62, 0x7f, 0x08, 0x13, 0x4c, 0xb8, 0x41, 0x69, - 0x20, 0x00, 0x00, 0x99, 0x4d, 0xfb, 0x23, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0xf6, 0x05, 0x62, 0x7f, 0x08, 0x13, 0x4c, 0xf8, 0x40, 0x69, + 0x20, 0x00, 0x00, 0x15, 0xf5, 0xce, 0xde, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1230,1141 +1312,1223 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA100_header_dbg_storage_pvt // VAR NAME: booter_ucode_data_ga100 // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 38400 -// COMPRESSED SIZE (bytes): 18068 +// DATA SIZE (bytes): 39936 +// COMPRESSED SIZE (bytes): 19386 // static BINDATA_CONST NvU8 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defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 38400, // uncompressed data size (bytes) - 18068, // compressed data size (bytes) + 39936, // uncompressed data size (bytes) + 19386, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_GA100_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -2397,8 +2561,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA100_image_prod_storage_pvt // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA100_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x76, 0x07, 0x62, 0x7f, 0x08, 0x13, 0x4c, 0xb8, 0x41, 0x69, - 0x20, 0x00, 0x00, 0x99, 0x4d, 0xfb, 0x23, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0xf6, 0x05, 0x62, 0x7f, 0x08, 0x13, 0x4c, 0xf8, 0x40, 0x69, + 0x20, 0x00, 0x00, 0x15, 0xf5, 0xce, 0xde, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2424,38 +2588,37 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA100_header_prod_storage_pv // FILE NAME: kernel/inc/gsprm/bin/booter/ga100/unload/g_booteruc_unload_ga100_ga100_rsa3k_1_sig.h // FILE TYPE: TEXT // VAR NAME: booter_unload_sig_dbg_ga100 -// COMPRESSION: YES +// COMPRESSION: NO // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 384 -// COMPRESSED SIZE (bytes): 397 +// COMPRESSED SIZE (bytes): N/A // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA100_sig_dbg_data[] = { - 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0xd0, 0x3b, 0xa4, 0xc1, 0xd8, 0xe1, 0xd2, 0x3b, 0xab, 0x14, 0x64, 0xe1, 0x74, 0x5c, 0x38, 0x9a, - 0x8f, 0xdb, 0x74, 0x48, 0x4a, 0x54, 0xfc, 0xaf, 0x5b, 0x09, 0x32, 0x2e, 0xe7, 0xf2, 0xc7, 0x70, - 0x2a, 0xa9, 0x63, 0x37, 0xbf, 0x4c, 0x1e, 0xdc, 0x67, 0x80, 0x01, 0x00, 0x00, + 0x2c, 0xfb, 0x4d, 0x26, 0x9e, 0xb4, 0x3c, 0x9f, 0xfa, 0x9e, 0x62, 0xa3, 0x02, 0x40, 0x61, 0xda, + 0x5d, 0x68, 0xdf, 0xba, 0xf5, 0x2c, 0xa5, 0x7a, 0xf1, 0x52, 0x12, 0x84, 0x95, 0xf7, 0xa2, 0x1d, + 0x7f, 0x82, 0x42, 0x0a, 0xfd, 0xda, 0xd7, 0x0d, 0xbf, 0xba, 0x99, 0xf8, 0x7d, 0x2b, 0x57, 0x47, + 0x6b, 0xa0, 0x82, 0x6e, 0x26, 0x16, 0x8d, 0x85, 0xe9, 0x31, 0x6a, 0x81, 0x22, 0x5e, 0x80, 0x10, + 0x78, 0xe1, 0xce, 0xea, 0x6b, 0xfd, 0x41, 0x74, 0xbf, 0xdf, 0x20, 0xf5, 0x22, 0x57, 0xf6, 0x04, + 0xa1, 0xcc, 0x02, 0x6a, 0x0f, 0xad, 0xac, 0xb5, 0x57, 0x21, 0xce, 0x8c, 0x2c, 0x41, 0xc8, 0x40, + 0xdf, 0x24, 0xb9, 0x3c, 0x52, 0x26, 0x4d, 0xfe, 0xb6, 0x76, 0xce, 0x11, 0xc8, 0x94, 0x98, 0x84, + 0x56, 0xfa, 0xfc, 0x7c, 0x5e, 0xf4, 0xff, 0x50, 0x71, 0xb5, 0x3d, 0xa0, 0xef, 0xc9, 0xad, 0xe3, + 0x51, 0x24, 0xc9, 0xe4, 0x8d, 0x4f, 0x33, 0xef, 0xd2, 0x98, 0x6e, 0x70, 0xa1, 0xd3, 0x90, 0x6a, + 0x36, 0xc9, 0xab, 0xb4, 0x02, 0xc6, 0xe5, 0xb6, 0xc3, 0x7d, 0x0a, 0x57, 0x47, 0xcd, 0x98, 0x78, + 0xb3, 0xa5, 0x0d, 0xeb, 0x34, 0x6b, 0x6b, 0xa6, 0xc0, 0xd8, 0xb6, 0x30, 0xb5, 0x87, 0x2c, 0x67, + 0x48, 0xec, 0xe6, 0xd3, 0xff, 0x07, 0x39, 0x67, 0x6f, 0x24, 0x3a, 0xab, 0x5e, 0x45, 0x21, 0x26, + 0x3f, 0x9f, 0xef, 0xc6, 0x6a, 0xa0, 0x04, 0xa0, 0x93, 0xef, 0xcc, 0x7c, 0x04, 0x79, 0xc0, 0x1e, + 0x14, 0x27, 0x01, 0xd6, 0x5b, 0xab, 0x31, 0x55, 0x2f, 0x7a, 0xa7, 0x31, 0xe5, 0x1f, 0xab, 0x9b, + 0x6f, 0xd3, 0x0f, 0x8e, 0x2e, 0x7b, 0x7f, 0x79, 0x4f, 0x30, 0x76, 0x51, 0x2c, 0x5a, 0x38, 0xc9, + 0xb1, 0x03, 0xd9, 0xde, 0x0c, 0x31, 0xf1, 0x50, 0x5d, 0xbb, 0x21, 0xd4, 0xed, 0x07, 0x49, 0x26, + 0x59, 0x63, 0xd4, 0x9d, 0x88, 0x31, 0xce, 0xfb, 0x93, 0x4a, 0x0b, 0x5a, 0xda, 0x01, 0x47, 0x6e, + 0x36, 0x31, 0x6f, 0xf9, 0x79, 0xdf, 0xb2, 0xbe, 0xc5, 0xf9, 0x6b, 0xd4, 0xe5, 0x91, 0x14, 0x92, + 0x2f, 0xda, 0x1e, 0xed, 0x26, 0x01, 0x79, 0xad, 0xaa, 0x54, 0x4c, 0x07, 0x99, 0x6f, 0x33, 0xc1, + 0x2f, 0xf7, 0xef, 0x79, 0x32, 0xa6, 0x63, 0xf2, 0x87, 0xbb, 0x45, 0xd1, 0x39, 0x25, 0x62, 0x52, + 0x71, 0x5e, 0x3c, 0xff, 0xdf, 0x6b, 0x62, 0xa9, 0x7f, 0x0d, 0x5a, 0x41, 0x7d, 0x22, 0x94, 0x5c, + 0x84, 0x6b, 0xee, 0xa3, 0x5e, 0x7a, 0x6e, 0x93, 0x43, 0xbd, 0xee, 0x18, 0xda, 0x79, 0xf6, 0x53, + 0x46, 0x02, 0x3b, 0x28, 0xf1, 0x0a, 0x36, 0xe4, 0xa3, 0xf6, 0x62, 0x37, 0x30, 0x88, 0xa1, 0x58, + 0xe1, 0xa0, 0xc9, 0x54, 0xd3, 0xaf, 0x52, 0x85, 0x0d, 0xe9, 0xf6, 0xc5, 0xca, 0x5e, 0x7f, 0xbb, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2466,9 +2629,9 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA100_sig_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 384, // uncompressed data size (bytes) - 397, // compressed data size (bytes) + 384, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_GA100_sig_dbg_data, // compressed data pointer - NV_TRUE, // is pData compressed? + NV_FALSE, // is pData compressed? NV_TRUE, // contain information for file overriding? NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) }, @@ -2481,38 +2644,37 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA100_sig_dbg_storage_pvt; // FILE NAME: kernel/inc/gsprm/bin/booter/ga100/unload/g_booteruc_unload_ga100_ga100_rsa3k_1_sig.h // FILE TYPE: TEXT // VAR NAME: booter_unload_sig_prod_ga100 -// COMPRESSION: YES +// COMPRESSION: NO // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 384 -// COMPRESSED SIZE (bytes): 397 +// COMPRESSED SIZE (bytes): N/A // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA100_sig_prod_data[] = { - 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x15, 0x28, 0xc1, 0x99, 0x80, 0xc0, 0x3e, 0x31, 0xcb, 0x3e, 0xed, - 0x38, 0x17, 0xa4, 0x3c, 0x15, 0x69, 0x05, 0xe6, 0xa8, 0xb3, 0xe3, 0x7a, 0x10, 0xef, 0x32, 0xb9, - 0xa6, 0xb0, 0x3f, 0x12, 0x12, 0xad, 0xf8, 0x93, 0xf9, 0x04, 0x55, 0x0e, 0x42, 0xe6, 0xaa, 0xaf, - 0x0e, 0x06, 0x41, 0x3b, 0x4a, 0x51, 0xb2, 0x89, 0x63, 0xb9, 0x6e, 0x08, 0x5b, 0x4a, 0xa4, 0xbf, - 0x97, 0xe6, 0x64, 0xd4, 0x19, 0x5e, 0xd5, 0x3d, 0xb1, 0xec, 0xb8, 0x23, 0x2c, 0x4c, 0xf6, 0x53, - 0xaf, 0xa1, 0xc1, 0xc0, 0xb9, 0xea, 0x6f, 0x56, 0xfe, 0x0d, 0xa1, 0xcb, 0x2b, 0x84, 0x20, 0xeb, - 0xa4, 0x5b, 0x23, 0x51, 0xa6, 0xac, 0x54, 0x6e, 0x10, 0xa5, 0x8c, 0x7f, 0x76, 0xfa, 0x1f, 0x01, - 0x8c, 0xea, 0x0e, 0x46, 0x18, 0x16, 0xba, 0x41, 0xd8, 0x2c, 0x31, 0x83, 0xa3, 0xe5, 0x3e, 0x0f, - 0x81, 0xb1, 0x31, 0x6d, 0x22, 0x08, 0x8b, 0xf5, 0x01, 0x5d, 0xdf, 0xf6, 0xf6, 0x62, 0x26, 0xaa, - 0xf2, 0x7d, 0x40, 0xd9, 0xf5, 0x70, 0x6d, 0x95, 0x3d, 0xf2, 0x8d, 0x7d, 0x93, 0x85, 0x04, 0x25, - 0xbe, 0xf9, 0xe5, 0x47, 0x6e, 0x80, 0xaf, 0xc0, 0x6a, 0xd4, 0xba, 0x62, 0x94, 0xc3, 0x6b, 0xa8, - 0x58, 0x9b, 0x49, 0xae, 0xaf, 0xf5, 0xaa, 0xd3, 0x52, 0x67, 0xde, 0x9a, 0x64, 0x84, 0xcb, 0x98, - 0x12, 0x53, 0xab, 0x4c, 0xe2, 0xed, 0x6e, 0xce, 0xc1, 0x76, 0x4a, 0xe7, 0x2a, 0x1d, 0x81, 0x60, - 0x2d, 0xb0, 0xdd, 0x8a, 0x91, 0x10, 0x25, 0x60, 0x00, 0x35, 0xe0, 0x40, 0x3c, 0xb1, 0xff, 0x8b, - 0x3a, 0xc7, 0xba, 0x4b, 0xf8, 0xac, 0xfd, 0x2e, 0x76, 0x85, 0xeb, 0x7a, 0xc8, 0x61, 0x58, 0x3e, - 0xc3, 0xfc, 0x2e, 0xf0, 0x50, 0xa4, 0x79, 0x5d, 0x6c, 0xb7, 0xfc, 0xb5, 0x0a, 0x69, 0xfb, 0x5c, - 0xc9, 0x17, 0x17, 0x0c, 0xf1, 0x5e, 0xc1, 0xd4, 0x16, 0xf7, 0x14, 0x38, 0xb7, 0x7f, 0xf7, 0x7c, - 0xc0, 0xf2, 0x0d, 0x70, 0xfd, 0x8f, 0xf2, 0x7d, 0x7b, 0xbb, 0x12, 0x94, 0x0b, 0x2d, 0x43, 0xf2, - 0x3f, 0x46, 0xc7, 0x02, 0x3b, 0x5f, 0xfa, 0x04, 0x20, 0x5a, 0x01, 0x91, 0x4a, 0x5d, 0xc0, 0x02, - 0xc2, 0x12, 0x4d, 0x83, 0xe7, 0x02, 0x27, 0xbb, 0x0d, 0x77, 0x2b, 0xc8, 0x21, 0x69, 0xed, 0x96, - 0xfe, 0x64, 0xbc, 0xa6, 0x64, 0x5c, 0xba, 0x1b, 0xcb, 0xeb, 0x0b, 0x1a, 0xd7, 0x83, 0xb8, 0xb1, - 0xbf, 0x20, 0x21, 0x01, 0x89, 0xfa, 0x53, 0x72, 0x21, 0xe9, 0x50, 0xd9, 0xc6, 0xac, 0x81, 0x8e, - 0xc2, 0x8a, 0x61, 0xe4, 0x4c, 0x3f, 0x85, 0xa4, 0xb3, 0x27, 0x00, 0x3c, 0xbe, 0x76, 0x4a, 0x64, - 0xd1, 0xf9, 0x9a, 0x13, 0xfc, 0xc2, 0x57, 0x39, 0x67, 0x5d, 0xec, 0x58, 0x83, 0xa2, 0x37, 0x9d, - 0x3c, 0xa6, 0xcf, 0xdb, 0x72, 0x5f, 0x2e, 0x4f, 0xa5, 0x80, 0x01, 0x00, 0x00, + 0x17, 0xca, 0x6a, 0xeb, 0x61, 0xb8, 0x00, 0x4f, 0x72, 0xb3, 0x5e, 0xc0, 0xc8, 0x61, 0xad, 0xbd, + 0x62, 0x73, 0x4a, 0x86, 0xa7, 0x9c, 0x60, 0xaf, 0x36, 0x60, 0x86, 0xb4, 0x47, 0x71, 0x30, 0x95, + 0xd6, 0xa2, 0xee, 0xde, 0x0e, 0x8d, 0x0a, 0xea, 0x42, 0xf3, 0xb5, 0xfa, 0xd5, 0xef, 0x3d, 0x0e, + 0xed, 0xc0, 0x18, 0x8e, 0xf3, 0xfd, 0x1c, 0xa3, 0x2c, 0x16, 0x1d, 0xe9, 0xcd, 0x48, 0x56, 0xc6, + 0x73, 0x78, 0x84, 0xb8, 0x55, 0x57, 0x93, 0xa7, 0xf6, 0x73, 0x72, 0x22, 0xb4, 0x18, 0xe1, 0x2e, + 0x83, 0x58, 0xdd, 0x08, 0x87, 0x83, 0x40, 0xe8, 0x67, 0x2b, 0xb3, 0x6c, 0x46, 0x47, 0xf1, 0xa8, + 0x3b, 0xa5, 0xd8, 0x5d, 0xeb, 0x0b, 0x50, 0xfb, 0xde, 0x7c, 0x25, 0xcb, 0xb1, 0x8c, 0x2b, 0xa3, + 0x61, 0x94, 0xee, 0xd4, 0x0e, 0xc5, 0x73, 0xda, 0xa4, 0xa6, 0x71, 0xf1, 0xd1, 0x5c, 0x52, 0x04, + 0xdc, 0x1a, 0x37, 0xf6, 0x25, 0xd6, 0xd1, 0x2d, 0x0b, 0x4c, 0xaa, 0x77, 0x36, 0xae, 0x81, 0x5b, + 0xa3, 0x61, 0x94, 0x4f, 0x7d, 0x6c, 0xe8, 0x2d, 0x7e, 0x5c, 0x02, 0xa3, 0x70, 0x51, 0x5b, 0xc1, + 0xda, 0xc2, 0xdb, 0xeb, 0xb6, 0xe7, 0x16, 0x5c, 0xf7, 0x6e, 0x0d, 0x03, 0x50, 0xb4, 0x70, 0xb6, + 0x57, 0xa9, 0xd0, 0xfe, 0x29, 0x7b, 0x10, 0x77, 0x60, 0xf7, 0x9b, 0x82, 0xfb, 0x70, 0x2f, 0x7d, + 0x10, 0x97, 0x22, 0x2a, 0x96, 0x98, 0xd3, 0xba, 0x0a, 0x11, 0x0e, 0xb7, 0xd2, 0x85, 0xe0, 0xb9, + 0x0d, 0x79, 0x10, 0xcc, 0x6e, 0x73, 0x6e, 0x1f, 0xd4, 0xa1, 0x0a, 0xf8, 0x1e, 0x32, 0x89, 0xa9, + 0x36, 0xa0, 0xf7, 0x26, 0x80, 0x76, 0x98, 0x2f, 0xa1, 0xda, 0xe7, 0xd8, 0xc8, 0x8a, 0x8a, 0x46, + 0x14, 0x67, 0x23, 0xdc, 0x36, 0x51, 0x6c, 0xad, 0x0d, 0x03, 0xc1, 0x64, 0x57, 0xce, 0x9d, 0xe1, + 0x1b, 0x68, 0x0d, 0x55, 0x00, 0xd9, 0x96, 0x3f, 0x08, 0x72, 0xb6, 0x56, 0xbf, 0xb4, 0xeb, 0x61, + 0xc9, 0x4c, 0xbe, 0x57, 0x98, 0x61, 0x27, 0xd4, 0xf2, 0xca, 0x00, 0x8e, 0x78, 0xa7, 0xf5, 0x07, + 0x9d, 0x64, 0xa6, 0xc3, 0xe1, 0xf3, 0x2b, 0xc4, 0x6f, 0xd8, 0x53, 0xbc, 0xb4, 0x4d, 0xbb, 0xc8, + 0xfc, 0xa3, 0xf4, 0xb7, 0x48, 0x67, 0xcb, 0x74, 0xba, 0xfd, 0x88, 0x2e, 0x78, 0x5c, 0xac, 0x2b, + 0x1c, 0xa6, 0x65, 0x81, 0xe2, 0xae, 0xff, 0x2d, 0xb4, 0x24, 0x53, 0x28, 0xb3, 0xae, 0x7e, 0x79, + 0xac, 0xfc, 0x17, 0x11, 0x8a, 0xc8, 0x9b, 0x97, 0x94, 0x6f, 0x70, 0xae, 0xd7, 0xea, 0x41, 0xcf, + 0xed, 0x29, 0x85, 0xf2, 0xe3, 0x37, 0x9f, 0x20, 0x91, 0x2d, 0xed, 0x79, 0xea, 0x7c, 0x28, 0x32, + 0x13, 0x99, 0x5b, 0x77, 0x3b, 0x8e, 0xbc, 0xc8, 0x8a, 0x0b, 0x32, 0xe3, 0x0e, 0x6f, 0x0d, 0x06, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2523,9 +2685,9 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA100_sig_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 384, // uncompressed data size (bytes) - 397, // compressed data size (bytes) + 384, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_GA100_sig_prod_data, // compressed data pointer - NV_TRUE, // is pData compressed? + NV_FALSE, // is pData compressed? NV_TRUE, // contain information for file overriding? NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) }, @@ -2545,7 +2707,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA100_sig_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA100_patch_loc_data[] = { - 0x00, 0x49, 0x00, 0x00, + 0x00, 0x4f, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA102.c index 3e9ae2c6e4..67be5d69b7 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA102.c @@ -34,1171 +34,1258 @@ // VAR NAME: booter_ucode_data_ga10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 38656 -// COMPRESSED SIZE (bytes): 18553 +// DATA SIZE (bytes): 40192 +// COMPRESSED SIZE (bytes): 19944 // static BINDATA_CONST NvU8 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0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xcf, 0xf1, 0xbf, 0x00, + 0x53, 0x6d, 0xc4, 0x4a, 0x00, 0x9d, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1208,8 +1295,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA102_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 38656, // uncompressed data size (bytes) - 18553, // compressed data size (bytes) + 40192, // uncompressed data size (bytes) + 19944, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_GA102_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1231,8 +1318,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA102_image_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA102_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0xf6, 0x02, 0x62, 0x5f, 0x08, 0x13, 0x4c, 0x78, 0x42, 0x69, - 0x20, 0x00, 0x00, 0x38, 0xcc, 0xda, 0x90, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x0e, 0x00, 0x62, 0x5f, 0x08, 0x13, 0x4c, 0xf8, 0x43, 0x69, + 0x20, 0x00, 0x00, 0x26, 0x4d, 0x81, 0x39, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1260,1171 +1347,1258 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA102_header_dbg_storage_pvt // VAR NAME: booter_ucode_data_ga10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 38656 -// COMPRESSED SIZE (bytes): 18557 +// DATA SIZE (bytes): 40192 +// COMPRESSED SIZE (bytes): 19945 // static BINDATA_CONST NvU8 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0xfd, 0xfa, 0xf5, + 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, + 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xff, 0x3f, 0xfe, + 0x17, 0x2c, 0x54, 0xc4, 0x21, 0x00, 0x9d, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2434,8 +2608,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA102_image_prod_storage_pvt #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 38656, // uncompressed data size (bytes) - 18557, // compressed data size (bytes) + 40192, // uncompressed data size (bytes) + 19945, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_GA102_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -2457,8 +2631,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA102_image_prod_storage_pvt // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA102_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0xf6, 0x02, 0x62, 0x5f, 0x08, 0x13, 0x4c, 0x78, 0x42, 0x69, - 0x20, 0x00, 0x00, 0x38, 0xcc, 0xda, 0x90, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x0e, 0x00, 0x62, 0x5f, 0x08, 0x13, 0x4c, 0xf8, 0x43, 0x69, + 0x20, 0x00, 0x00, 0x26, 0x4d, 0x81, 0x39, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2484,62 +2658,61 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA102_header_prod_storage_pv // FILE NAME: kernel/inc/gsprm/bin/booter/ga10x/unload/g_booteruc_unload_ga10x_ga102_rsa3k_0_sig.h // FILE TYPE: TEXT // VAR NAME: booter_unload_sig_dbg_ga10x -// COMPRESSION: YES +// COMPRESSION: NO // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 768 -// COMPRESSED SIZE (bytes): 781 +// COMPRESSED SIZE (bytes): N/A // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA102_sig_dbg_data[] = { - 0x01, 0x00, 0x03, 0xff, 0xfc, 0xce, 0x95, 0x28, 0xc6, 0x33, 0x65, 0x8b, 0xea, 0x4a, 0x62, 0x3f, - 0xbc, 0x9b, 0x1f, 0xbc, 0x7a, 0xef, 0x0d, 0x4d, 0x6a, 0x17, 0x62, 0xc4, 0xd9, 0x34, 0x37, 0x38, - 0x19, 0x0d, 0x23, 0x36, 0x11, 0x1d, 0x03, 0x6a, 0xab, 0xd4, 0x09, 0xf0, 0xf5, 0xf8, 0x87, 0xda, - 0xf5, 0x2c, 0x54, 0x57, 0x07, 0x53, 0x5e, 0x70, 0xf7, 0x65, 0x7c, 0x73, 0x22, 0x11, 0xc4, 0x65, - 0xab, 0xed, 0x53, 0x14, 0x56, 0x42, 0xf3, 0xc9, 0xa9, 0xe2, 0x31, 0x2b, 0x66, 0x26, 0xf1, 0xe4, - 0xc3, 0x7a, 0x1f, 0x8c, 0x1a, 0x4e, 0x39, 0x62, 0xaa, 0x4c, 0x3a, 0x3f, 0x08, 0x1c, 0xe9, 0x21, - 0x2b, 0x9e, 0x4c, 0xa5, 0xe1, 0x40, 0x5a, 0x14, 0x72, 0xdb, 0x17, 0x69, 0x5d, 0x18, 0xb2, 0xa4, - 0x0d, 0xd9, 0x30, 0xa0, 0x70, 0x89, 0x68, 0x7b, 0x6d, 0x64, 0x3f, 0x60, 0x2e, 0x1c, 0x2e, 0xd5, - 0x8a, 0x8a, 0x2b, 0x7c, 0x3f, 0xfc, 0x66, 0xd4, 0xb5, 0xa0, 0x82, 0x1f, 0xd7, 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0x00, + 0x83, 0xc0, 0x0f, 0x2e, 0x51, 0x55, 0x1d, 0x2c, 0x5d, 0x55, 0xdf, 0x5e, 0xd1, 0x21, 0x69, 0xe1, + 0x93, 0xe4, 0xca, 0xaf, 0xec, 0xbe, 0x03, 0x2b, 0x9b, 0xe3, 0x3a, 0x7d, 0x6c, 0x77, 0x4a, 0x17, + 0x33, 0x59, 0x25, 0x41, 0x94, 0x4a, 0xae, 0x01, 0x9c, 0x8e, 0x00, 0xe8, 0x54, 0x7b, 0xea, 0xec, + 0xb9, 0x30, 0x05, 0xa4, 0x27, 0x16, 0x79, 0x47, 0x3a, 0x6a, 0x65, 0x86, 0x0d, 0xd8, 0x88, 0x79, + 0x56, 0xaa, 0xb8, 0xa0, 0x56, 0xf4, 0x80, 0xda, 0xfe, 0x6a, 0xc7, 0x30, 0x05, 0x59, 0x11, 0x2f, + 0xd9, 0xe9, 0x5b, 0xe6, 0xa6, 0xfb, 0x4a, 0xab, 0x12, 0x29, 0xd0, 0xc1, 0x66, 0x04, 0x75, 0x23, + 0x7d, 0xe4, 0xfc, 0xab, 0xe2, 0x34, 0xfd, 0x02, 0x7a, 0x5c, 0x94, 0x84, 0xa5, 0x09, 0xed, 0x90, + 0xd8, 0xf5, 0x0c, 0xec, 0x92, 0x23, 0x66, 0xfe, 0x85, 0x20, 0x9d, 0x7a, 0x58, 0x2f, 0x0f, 0xfd, + 0x39, 0x6f, 0x00, 0x69, 0xcf, 0x9e, 0xb1, 0xd7, 0xfc, 0x95, 0x16, 0xdd, 0x4c, 0xd5, 0xd3, 0x47, + 0xc6, 0x00, 0x46, 0xa9, 0xc2, 0xc4, 0x8d, 0x81, 0x95, 0xa5, 0xba, 0x78, 0x12, 0x94, 0xa9, 0xae, + 0x96, 0xf6, 0x6a, 0x8d, 0x17, 0x2d, 0x41, 0x8e, 0x64, 0x14, 0x6c, 0xea, 0x7a, 0xb4, 0x0f, 0x57, + 0xf0, 0x33, 0x68, 0x62, 0xa9, 0x9e, 0x69, 0xb0, 0x61, 0x8a, 0xe0, 0xc3, 0x3d, 0x53, 0xf1, 0x73, + 0x39, 0xf7, 0x20, 0xf0, 0xf6, 0xd5, 0x9a, 0xad, 0xd8, 0x9a, 0xe2, 0x6a, 0xcb, 0x8b, 0x14, 0x68, + 0xb0, 0xc1, 0xf0, 0xee, 0xe9, 0x3f, 0x1d, 0xd6, 0x94, 0x95, 0x5c, 0xb2, 0xe5, 0x52, 0xd2, 0xd8, + 0xa9, 0xa8, 0xe6, 0xc2, 0x74, 0xf2, 0x50, 0xdb, 0x1d, 0x6c, 0x22, 0xf3, 0x2d, 0xbe, 0x05, 0x53, + 0x9d, 0x11, 0x67, 0xfa, 0x09, 0xe7, 0x61, 0x3c, 0x98, 0xd4, 0x54, 0x41, 0x92, 0x3c, 0x9d, 0x35, + 0x95, 0x49, 0x82, 0x53, 0xdf, 0x37, 0xc6, 0x05, 0x65, 0xb0, 0x9d, 0x13, 0x06, 0x3b, 0x87, 0x5c, + 0xc3, 0xdc, 0xad, 0x14, 0xf2, 0xd9, 0xdc, 0x03, 0x24, 0x85, 0x12, 0xa1, 0xad, 0x71, 0xaa, 0x43, + 0xcf, 0x78, 0xd2, 0x92, 0x71, 0xf2, 0x54, 0x9b, 0xdf, 0x26, 0x0c, 0x41, 0x57, 0x1f, 0x63, 0x9d, + 0xe0, 0x7d, 0xb0, 0x53, 0xf7, 0x17, 0x27, 0xb6, 0xf5, 0xcf, 0xf1, 0xd2, 0x18, 0xc0, 0xb6, 0x1a, + 0x0f, 0x9e, 0xbd, 0xd3, 0xc2, 0xe6, 0x9e, 0xc9, 0x59, 0x3a, 0x51, 0xe9, 0x68, 0x6c, 0xcc, 0x71, + 0x5f, 0x69, 0x4a, 0x70, 0xfa, 0x50, 0x9c, 0xd8, 0x53, 0x72, 0xe3, 0xb2, 0x04, 0x00, 0x9b, 0xa7, + 0x15, 0x9f, 0xcf, 0x65, 0x70, 0xfb, 0x04, 0x3a, 0x38, 0x0d, 0xa6, 0x45, 0xb6, 0x50, 0xa8, 0x2e, + 0x4a, 0x8f, 0xf3, 0xd8, 0x9c, 0x08, 0x67, 0x25, 0xab, 0x75, 0x13, 0xdf, 0x29, 0x7e, 0x07, 0xd5, + 0xb0, 0x7a, 0xbd, 0x91, 0x71, 0x4a, 0x9e, 0x57, 0x4f, 0x0f, 0x5c, 0x72, 0x82, 0x1d, 0xd8, 0x9f, + 0x95, 0x47, 0x09, 0x5b, 0x35, 0xde, 0x9b, 0x04, 0x3e, 0x45, 0xfb, 0x09, 0x97, 0xbb, 0x79, 0x5c, + 0xf7, 0x58, 0x07, 0xfb, 0xd8, 0x5a, 0x86, 0x7b, 0x61, 0x60, 0xfb, 0xd0, 0x9c, 0x6c, 0xd2, 0x8a, + 0xe8, 0xd4, 0xbd, 0x58, 0x04, 0x32, 0x39, 0x9b, 0xf7, 0x48, 0xce, 0x28, 0xcf, 0x48, 0xe3, 0xa2, + 0x71, 0x0a, 0x60, 0x77, 0x24, 0xcf, 0x32, 0xed, 0x06, 0x2f, 0xc0, 0xec, 0xc4, 0x4e, 0x5e, 0x70, + 0x1f, 0x33, 0xf8, 0x61, 0xbd, 0x2e, 0xa0, 0xe1, 0x09, 0xea, 0x6b, 0x61, 0x97, 0x6e, 0xab, 0xb5, + 0xb9, 0x87, 0x61, 0x3d, 0xa0, 0x50, 0x25, 0x15, 0xb7, 0xab, 0x77, 0x76, 0x31, 0x84, 0x5f, 0xf3, + 0x1d, 0x0c, 0x7d, 0x3b, 0xb1, 0xc9, 0x9d, 0xc4, 0xf5, 0x6c, 0x28, 0xc4, 0xff, 0xc7, 0xd3, 0xf5, + 0x49, 0x31, 0x9c, 0x6c, 0x41, 0x72, 0x59, 0x0e, 0xd7, 0x36, 0x4a, 0x66, 0x20, 0x4b, 0xf5, 0x18, + 0x16, 0x86, 0x20, 0xc5, 0xa9, 0xe5, 0xf4, 0x45, 0xf5, 0x04, 0xf1, 0x8f, 0xde, 0x42, 0x39, 0x88, + 0x59, 0xc8, 0x02, 0x22, 0xcc, 0xae, 0xcc, 0xfc, 0x22, 0xd7, 0x2e, 0x12, 0x3a, 0x56, 0x83, 0xc4, + 0x59, 0x72, 0x65, 0x82, 0xd8, 0x30, 0xe1, 0xd6, 0x90, 0x4d, 0x89, 0xdf, 0x5d, 0xf3, 0xf8, 0x13, + 0xb4, 0xe5, 0xc8, 0xaf, 0xf1, 0x1a, 0x8b, 0x78, 0x43, 0x43, 0x28, 0xc9, 0x4d, 0x8c, 0x8c, 0xc2, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2550,9 +2723,9 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA102_sig_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 768, // uncompressed data size (bytes) - 781, // compressed data size (bytes) + 768, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_GA102_sig_dbg_data, // compressed data pointer - NV_TRUE, // is pData compressed? + NV_FALSE, // is pData compressed? NV_TRUE, // contain information for file overriding? NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) }, @@ -2568,37 +2741,37 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA102_sig_dbg_storage_pvt; // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 768 -// COMPRESSED SIZE (bytes): 419 +// COMPRESSED SIZE (bytes): 421 // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA102_sig_prod_data[] = { - 0x7b, 0x1c, 0x61, 0xff, 0xf0, 0x81, 0x02, 0x5f, 0xd2, 0x19, 0xf7, 0xa9, 0x6a, 0xdc, 0xb7, 0x8a, - 0xbe, 0xa5, 0xcc, 0x72, 0x0e, 0xf4, 0x3f, 0x91, 0xf0, 0xa2, 0xe9, 0xfa, 0x8f, 0xaf, 0xb7, 0xe6, - 0x67, 0x6e, 0xfe, 0xd3, 0x5a, 0xbd, 0xe9, 0xd5, 0xe6, 0x8c, 0xd8, 0x1e, 0x6d, 0x95, 0x55, 0x81, - 0x22, 0x1e, 0xaf, 0x9c, 0xa6, 0xdd, 0x39, 0x14, 0x91, 0xfe, 0xa5, 0xc9, 0x55, 0xf6, 0xa2, 0xd9, - 0xef, 0xd7, 0x99, 0xa5, 0xc7, 0xa5, 0x3d, 0x2c, 0xae, 0xad, 0xbc, 0x17, 0xaf, 0x7f, 0xfc, 0x6a, - 0x9d, 0x3c, 0x5b, 0x7e, 0xf5, 0x43, 0xc6, 0x89, 0x49, 0xcf, 0x3f, 0xbc, 0x52, 0x5c, 0x51, 0xc9, - 0xde, 0x16, 0xae, 0xbd, 0x78, 0x8d, 0xf9, 0x11, 0xaf, 0x2f, 0xaa, 0x4e, 0xdf, 0x52, 0xd7, 0x37, - 0x6c, 0xae, 0x97, 0x71, 0xd0, 0xe6, 0x79, 0x35, 0xc7, 0xf9, 0xf5, 0x2f, 0x77, 0xc1, 0x45, 0xbb, - 0x9e, 0x68, 0xd6, 0x1f, 0xbf, 0x6d, 0x70, 0x63, 0x8b, 0x93, 0xda, 0x9b, 0xd6, 0x5f, 0x53, 0xee, - 0xb9, 0xac, 0xe7, 0xfa, 0xa6, 0xff, 0xd4, 0x53, 0xdb, 0x8d, 0xd1, 0x24, 0x27, 0x54, 0x39, 0x6a, - 0xe1, 0x4b, 0xb5, 0x1d, 0x5e, 0x6f, 0x6b, 0x0e, 0x9c, 0xad, 0x90, 0x33, 0xbf, 0x9f, 0xfa, 0xed, - 0xd1, 0xa9, 0xb9, 0x46, 0xb5, 0x26, 0x2f, 0xed, 0x8f, 0x84, 0xdc, 0x0c, 0xb2, 0xfd, 0xc2, 0xa1, - 0xb0, 0xb8, 0x4a, 0xac, 0xe9, 0xda, 0x4d, 0xa5, 0x5b, 0xd7, 0x75, 0x77, 0x8a, 0xe9, 0x9b, 0x1e, - 0xb0, 0xe4, 0x30, 0xbd, 0xe1, 0xbf, 0xfe, 0xcb, 0xa1, 0xe9, 0x15, 0x4b, 0x05, 0x64, 0x7d, 0x9e, - 0xf8, 0x04, 0x58, 0x98, 0xec, 0xcd, 0xb1, 0x8f, 0xc9, 0xdf, 0x24, 0xc1, 0x62, 0xe1, 0x77, 0x3a, - 0x68, 0x5e, 0x45, 0x60, 0x5c, 0xd7, 0x9c, 0x47, 0xda, 0xe2, 0x22, 0xfd, 0x02, 0x77, 0x4e, 0xf7, - 0xe7, 0x18, 0x3d, 0x9e, 0xbb, 0x7e, 0xcb, 0xb7, 0x34, 0x33, 0x05, 0xee, 0x65, 0x8c, 0xdd, 0xf6, - 0xe7, 0xab, 0xa6, 0x57, 0x9f, 0xf9, 0x6c, 0x7e, 0x90, 0xf3, 0xfc, 0xce, 0xdf, 0xa1, 0x3b, 0x75, - 0x12, 0xd3, 0x78, 0x7e, 0x3e, 0x79, 0x9a, 0x9e, 0x34, 0xf5, 0xca, 0xbe, 0xed, 0xab, 0xd8, 0xd9, - 0xca, 0x27, 0x7e, 0x64, 0x78, 0xe4, 0xf0, 0xf0, 0xd2, 0xf3, 0xf2, 0xff, 0xe1, 0xdf, 0x8f, 0xc4, - 0x4f, 0x2e, 0x9a, 0xcd, 0xd4, 0x77, 0x3b, 0x2c, 0xeb, 0xb1, 0xe5, 0xd6, 0x9a, 0x6b, 0xf6, 0x07, - 0xb9, 0xe4, 0x54, 0xb3, 0x2e, 0xf1, 0xf2, 0xb3, 0xc9, 0xcf, 0x53, 0xb9, 0xfa, 0xa0, 0x2a, 0x4d, - 0xae, 0x37, 0x73, 0xe3, 0x2f, 0x31, 0xcd, 0x87, 0x81, 0x9a, 0xbc, 0x5f, 0x03, 0x7f, 0x3d, 0x4d, - 0xaa, 0x36, 0xd0, 0x8d, 0x7a, 0x77, 0xfe, 0x0d, 0x53, 0x1e, 0xc7, 0xf3, 0x05, 0xef, 0xed, 0x7f, - 0x33, 0x3d, 0x60, 0x09, 0xf9, 0xb1, 0x63, 0x63, 0x99, 0x28, 0x9b, 0x7f, 0xd7, 0xea, 0x2b, 0xd2, - 0x19, 0x36, 0x4b, 0x36, 0x3c, 0x62, 0x18, 0x05, 0x03, 0x0a, 0x00, 0x9b, 0xe7, 0x55, 0xd9, 0x00, - 0x03, 0x00, 0x00, + 0xe3, 0xfb, 0xa6, 0xcb, 0xd7, 0x9d, 0x24, 0xb3, 0x5e, 0x74, 0x97, 0x60, 0x9c, 0xfb, 0x9e, 0x2d, + 0xae, 0x75, 0x4f, 0x9e, 0x6c, 0x9b, 0x6e, 0x3d, 0xf9, 0xc4, 0xcb, 0x33, 0x7f, 0x63, 0xc5, 0x63, + 0x23, 0x6f, 0xbb, 0x5f, 0xe5, 0x9e, 0xb6, 0xe7, 0x9f, 0xe5, 0x86, 0x5a, 0x01, 0x8b, 0x1b, 0x3f, + 0xfa, 0x5c, 0xb7, 0x4a, 0x5d, 0x9e, 0xad, 0xb6, 0xeb, 0xe9, 0xcd, 0x05, 0x8f, 0x95, 0xe2, 0xa6, + 0x35, 0xdb, 0x1c, 0x4d, 0xf4, 0xbc, 0x23, 0xfd, 0xbf, 0xe0, 0xe0, 0x6e, 0x53, 0x87, 0xf3, 0x87, + 0xda, 0xe3, 0x73, 0x12, 0xd7, 0x9c, 0x67, 0xbc, 0x5a, 0x22, 0xd1, 0xb6, 0xa3, 0xf1, 0xc0, 0xa7, + 0x35, 0xe7, 0x77, 0x9e, 0x50, 0xe4, 0xfb, 0x5b, 0x11, 0xf1, 0xf6, 0xff, 0xe9, 0xed, 0x4b, 0x99, + 0x7c, 0x12, 0x66, 0x9f, 0xea, 0xf1, 0x9e, 0xf6, 0xa9, 0x34, 0x28, 0xfa, 0xf0, 0x46, 0xd6, 0x23, + 0x1b, 0x04, 0x37, 0x89, 0x2e, 0xe7, 0x10, 0x74, 0x64, 0xf9, 0xb0, 0x27, 0x85, 0x4d, 0x3a, 0xa0, + 0xbc, 0x35, 0xe0, 0x50, 0xd3, 0xce, 0x02, 0xc5, 0x75, 0xca, 0x27, 0xce, 0x48, 0xff, 0xcf, 0x0a, + 0x96, 0x8d, 0x5d, 0x20, 0x7f, 0xea, 0xb8, 0xf8, 0x8f, 0x0c, 0x73, 0xeb, 0x79, 0x8b, 0x96, 0x2a, + 0xc7, 0xed, 0x5f, 0x25, 0xf9, 0xd7, 0x66, 0xe7, 0xf4, 0x8c, 0xc2, 0xc8, 0x9e, 0x1d, 0x3f, 0xd6, + 0xfa, 0xcd, 0xbb, 0x99, 0x21, 0xd5, 0xb6, 0xef, 0x84, 0xff, 0xe9, 0x73, 0x7d, 0x82, 0x31, 0x67, + 0x6c, 0xbd, 0xd5, 0x6f, 0xf2, 0x98, 0xf5, 0xcb, 0xde, 0x96, 0x54, 0xed, 0xda, 0xb5, 0x44, 0xab, + 0x70, 0x1f, 0x53, 0xfd, 0x8f, 0x9f, 0x4b, 0x53, 0xd9, 0x98, 0xd6, 0xcc, 0x35, 0x37, 0x7a, 0xe1, + 0x7c, 0x66, 0x5d, 0x97, 0xf0, 0xd9, 0x13, 0xaf, 0xfe, 0xdf, 0xe7, 0xda, 0x36, 0xc3, 0xe1, 0xf6, + 0x06, 0xf9, 0xf5, 0x8e, 0xc1, 0x8c, 0xc1, 0xff, 0x2e, 0x16, 0x97, 0xa4, 0x39, 0xbe, 0xf0, 0x08, + 0xee, 0x2f, 0x39, 0xe0, 0xef, 0xcb, 0x3b, 0xeb, 0x93, 0xd3, 0x63, 0x87, 0x85, 0x9e, 0xbf, 0x2f, + 0x7c, 0x37, 0x29, 0xf9, 0x1b, 0xbd, 0x34, 0x7f, 0x79, 0xa8, 0xfe, 0xb4, 0xc3, 0x77, 0x7a, 0xee, + 0xcc, 0x09, 0x5d, 0x35, 0x73, 0xe5, 0x8a, 0x7d, 0x89, 0x3d, 0x6e, 0x7e, 0xa2, 0xaf, 0x5f, 0x1f, + 0x7a, 0x76, 0x32, 0xe3, 0xf1, 0x93, 0xd2, 0xab, 0x2e, 0x66, 0xa9, 0x29, 0xbe, 0x55, 0x1b, 0xcf, + 0xed, 0xe7, 0x5d, 0x2d, 0x37, 0xd5, 0xa6, 0x39, 0x29, 0x23, 0xfa, 0x88, 0xcf, 0xb4, 0xc6, 0xb6, + 0xab, 0xbc, 0xcd, 0x5e, 0x59, 0x0c, 0x0b, 0xff, 0x25, 0x2a, 0x87, 0x9c, 0x3d, 0x19, 0xf6, 0xd7, + 0x3d, 0xee, 0xe7, 0xda, 0xb5, 0x4d, 0x5d, 0x1f, 0x54, 0x58, 0xaf, 0xad, 0x97, 0x3d, 0xbe, 0xd4, + 0x23, 0x3c, 0x32, 0x46, 0x49, 0xd0, 0x6e, 0x79, 0xdf, 0xff, 0x9d, 0x4b, 0x3f, 0x29, 0xaa, 0x7c, + 0x91, 0x9d, 0x23, 0xf0, 0x63, 0xbf, 0x3d, 0xc3, 0x28, 0x18, 0x50, 0x00, 0x00, 0xb9, 0x70, 0x4b, + 0xc1, 0x00, 0x03, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2609,7 +2782,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA102_sig_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 768, // uncompressed data size (bytes) - 419, // compressed data size (bytes) + 421, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_GA102_sig_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -2631,7 +2804,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA102_sig_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA102_patch_loc_data[] = { - 0x10, 0x4a, 0x00, 0x00, + 0x10, 0x50, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveConcatenatedFMC_GH100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveConcatenatedFMC_GH100.c index 92f908f116..fe660dd1a9 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveConcatenatedFMC_GH100.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveConcatenatedFMC_GH100.c @@ -32,22693 +32,23053 @@ // FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_cc_concatenated_fmc_prod_image.bin // FILE TYPE: BINARY // VAR NAME: N/A -// COMPRESSION: YES +// COMPRESSION: NO // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 368640 -// COMPRESSED SIZE (bytes): 362878 +// COMPRESSED SIZE (bytes): N/A // static BINDATA_CONST NvU8 kgspBinArchiveConcatenatedFMC_GH100_ucode_image_prod_data[] = { - 0x9c, 0x57, 0xc3, 0x62, 0x28, 0x0a, 0x74, 0x8c, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, - 0xb6, 0x6d, 0xdb, 0xb6, 0xcd, 0x1b, 0xdb, 0xb6, 0x9d, 0xf4, 0xfd, 0x40, 0xbb, 0xe8, 0xac, 0xcf, - 0xec, 0xce, 0x88, 0xe2, 0x29, 0xb7, 0x98, 0xd8, 0x79, 0xfc, 0x04, 0x41, 0xa1, 0xe3, 0x80, 0x30, - 0x6d, 0xc3, 0xbd, 0xe7, 0x6d, 0x6e, 0x3b, 0xb9, 0x77, 0xc7, 0xaf, 0x1e, 0x81, 0xc0, 0x0a, 0x63, - 0xa9, 0xc6, 0x51, 0x27, 0x16, 0x8a, 0x35, 0x93, 0x46, 0x29, 0xe0, 0xfe, 0x95, 0xc5, 0xb1, 0xe6, - 0x79, 0x8f, 0x4c, 0x32, 0xf2, 0x6d, 0x3c, 0xae, 0x5a, 0xc7, 0xe2, 0xc4, 0x4a, 0x64, 0x7b, 0x4b, - 0x75, 0x3c, 0x28, 0x3a, 0xb8, 0x87, 0x5d, 0x7d, 0x7d, 0x16, 0x24, 0xc1, 0x71, 0x08, 0xfe, 0x4e, - 0x82, 0x77, 0x56, 0x83, 0x9c, 0xb3, 0xf8, 0x52, 0x0a, 0x11, 0x88, 0x9c, 0x3a, 0x5f, 0x0f, 0xa5, - 0x0e, 0xda, 0x0b, 0x85, 0xd8, 0x5f, 0xe5, 0xb9, 0xcf, 0x38, 0xf0, 0x24, 0x44, 0x35, 0x0b, 0x7a, - 0xfb, 0x45, 0xcf, 0x20, 0x52, 0xd8, 0x3e, 0x87, 0x48, 0x79, 0xe0, 0x54, 0x90, 0x72, 0x36, 0x7a, - 0x90, 0x70, 0x53, 0x62, 0x06, 0xcb, 0x4d, 0x5f, 0x0f, 0xa4, 0x73, 0x99, 0x45, 0x12, 0x9e, 0x81, - 0x15, 0xf5, 0x0b, 0x65, 0x81, 0xfa, 0xa4, 0x7f, 0x00, 0x31, 0x7d, 0x87, 0x26, 0x20, 0xea, 0x6d, - 0x07, 0x23, 0xd1, 0x09, 0x62, 0xbf, 0x4e, 0xc3, 0xbe, 0xa5, 0x5e, 0x96, 0x03, 0xa1, 0xc3, 0xc7, - 0x55, 0xfb, 0x75, 0xee, 0xd6, 0x69, 0x64, 0x43, 0x94, 0x13, 0xaf, 0x3d, 0xbb, 0xa0, 0x7b, 0x39, - 0x2e, 0xf4, 0x6b, 0x2c, 0xd3, 0xf2, 0x1b, 0x9c, 0x7b, 0x5f, 0x52, 0xf6, 0xe6, 0x2f, 0x2f, 0x6e, - 0x62, 0xf7, 0xa7, 0xd1, 0xe3, 0x8b, 0xe5, 0xcf, 0x77, 0x47, 0x15, 0x7c, 0x45, 0x53, 0x0d, 0x63, - 0x1b, 0x65, 0xbf, 0x12, 0x3c, 0x47, 0x29, 0x41, 0xb9, 0x4a, 0x23, 0xd6, 0xc6, 0xcb, 0x9b, 0x6c, - 0x58, 0x28, 0x44, 0x8a, 0xc3, 0x87, 0x61, 0x92, 0x3d, 0xbb, 0xee, 0x88, 0xc5, 0xf8, 0x66, 0xe1, - 0xb2, 0x14, 0xab, 0x4d, 0x29, 0x9e, 0x51, 0x26, 0x40, 0x2f, 0x02, 0x6a, 0xf5, 0x82, 0x59, 0x20, - 0x54, 0xeb, 0x77, 0xb6, 0x0f, 0xed, 0x38, 0x73, 0x5d, 0x90, 0x6d, 0x73, 0xe6, 0xad, 0x80, 0xc6, - 0xb0, 0x0d, 0x01, 0x5a, 0x30, 0xac, 0x1e, 0xda, 0xb4, 0xbc, 0xa5, 0x8c, 0x18, 0x05, 0xd8, 0x2d, - 0x2d, 0xf0, 0x51, 0x96, 0xb5, 0x5a, 0x32, 0x5a, 0x09, 0xfd, 0x7a, 0xa9, 0x45, 0x3f, 0x11, 0x14, - 0x12, 0xfa, 0x3b, 0xd1, 0xf5, 0x88, 0x9c, 0x2a, 0x31, 0x86, 0x44, 0x85, 0x4c, 0x92, 0xf8, 0x05, - 0x4a, 0x92, 0xc8, 0xcb, 0xcb, 0xd5, 0x32, 0x2a, 0x5f, 0x93, 0x4b, 0xd6, 0x75, 0xbe, 0xfa, 0x36, - 0x43, 0xe7, 0x86, 0x01, 0x2b, 0xda, 0x80, 0x6d, 0x5e, 0xfa, 0x32, 0x98, 0xe2, 0x55, 0x87, 0x4c, - 0x92, 0x79, 0x84, 0x2f, 0xe0, 0x3e, 0xbb, 0xa1, 0x1d, 0x1a, 0xf4, 0x3d, 0x4e, 0x8b, 0x50, 0x6e, - 0xbc, 0x24, 0x5a, 0xab, 0xec, 0x70, 0x04, 0x47, 0x2c, 0xfd, 0x84, 0x6d, 0x95, 0x4a, 0xdf, 0x93, - 0x59, 0xb7, 0x5a, 0xb8, 0xcd, 0xd4, 0xf3, 0x3c, 0x69, 0xf9, 0x45, 0x21, 0xee, 0x68, 0xb3, 0xe7, - 0x4e, 0x96, 0xbd, 0x31, 0x06, 0xbd, 0xdf, 0x34, 0x36, 0xc5, 0xf6, 0xb9, 0xdf, 0x37, 0xe4, 0x74, - 0x00, 0x29, 0x85, 0xe7, 0xb0, 0xd5, 0x30, 0x8f, 0x4d, 0x86, 0x00, 0x66, 0x08, 0x24, 0x2c, 0xf6, - 0xdf, 0x79, 0xdf, 0x0c, 0xf0, 0x9b, 0x0c, 0x0a, 0xfa, 0xbb, 0x76, 0x14, 0xec, 0xe4, 0xc2, 0xdc, - 0x51, 0x32, 0x78, 0x68, 0x4d, 0xa3, 0x8c, 0x62, 0x12, 0x4a, 0xd3, 0x50, 0x07, 0x3f, 0x88, 0xad, - 0x06, 0x26, 0x41, 0x52, 0x97, 0xb2, 0x09, 0xd0, 0x31, 0x5f, 0xbe, 0xd4, 0x40, 0x4f, 0x5c, 0x62, - 0xc5, 0x33, 0xcf, 0xa3, 0xce, 0x95, 0x60, 0x81, 0x04, 0x06, 0xe8, 0xd9, 0x2a, 0x9d, 0xb4, 0xfd, - 0x29, 0xb8, 0xe0, 0x16, 0x4b, 0x9b, 0xc5, 0xdb, 0x9b, 0xcb, 0x76, 0x28, 0x6b, 0x6f, 0xd3, 0x4a, - 0x9b, 0x52, 0x2e, 0x5d, 0x7a, 0xcd, 0xb6, 0x8d, 0x15, 0x6b, 0xc7, 0xc3, 0x78, 0x4c, 0xe0, 0x81, - 0xb4, 0xf4, 0xac, 0xb6, 0xa1, 0x82, 0x00, 0x6e, 0x59, 0x67, 0x57, 0x97, 0x00, 0xff, 0x9b, 0x70, - 0x60, 0xa5, 0x3f, 0xf0, 0xf4, 0xc7, 0x21, 0xe5, 0x28, 0xe4, 0x77, 0x21, 0xa5, 0xc0, 0x1c, 0x83, - 0xb0, 0x6e, 0x59, 0x55, 0x6c, 0x4b, 0xa6, 0xf0, 0xc1, 0x2b, 0xd6, 0x40, 0xbc, 0x75, 0x34, 0x8a, - 0x59, 0x36, 0x10, 0xe8, 0xc7, 0xf3, 0xac, 0xf7, 0x9d, 0xc8, 0xec, 0xcb, 0x9b, 0x8d, 0x3d, 0xc7, - 0x65, 0xc0, 0xae, 0xdb, 0xca, 0x61, 0x49, 0x6d, 0xdd, 0xb5, 0x0e, 0x78, 0x25, 0x62, 0xb2, 0x72, - 0x54, 0x9e, 0x1e, 0x69, 0xe5, 0xe0, 0xe7, 0x4c, 0xd5, 0x15, 0x30, 0x1f, 0xad, 0x05, 0x5c, 0x70, - 0xfe, 0xec, 0x51, 0xfc, 0x19, 0xa1, 0xbc, 0x64, 0x05, 0xcb, 0x3f, 0xdd, 0x57, 0x28, 0xeb, 0xc1, - 0xb3, 0x3d, 0xcf, 0x8a, 0x6b, 0xb7, 0x1e, 0x7e, 0xa5, 0x84, 0xa6, 0xbd, 0xde, 0x13, 0x22, 0x02, - 0xc0, 0xc8, 0x69, 0x78, 0x59, 0xd6, 0xe7, 0x25, 0x05, 0xb5, 0xab, 0xd2, 0x9d, 0xa0, 0x4e, 0x9e, - 0xa8, 0x02, 0xd7, 0xf6, 0xce, 0xb6, 0x67, 0xe2, 0x3c, 0x1a, 0x77, 0x6f, 0x3c, 0xcb, 0x72, 0x4a, - 0x02, 0xcb, 0xe8, 0x58, 0xec, 0x03, 0xe6, 0xb3, 0x16, 0xf2, 0xfd, 0xf8, 0x39, 0xab, 0x48, 0x13, - 0x08, 0x55, 0x10, 0x5a, 0xee, 0xeb, 0x54, 0xda, 0x29, 0xc6, 0x32, 0xa3, 0x02, 0xb4, 0x4d, 0xcd, - 0x9a, 0xd7, 0x6b, 0x16, 0xf7, 0xc3, 0x31, 0xad, 0x85, 0xe9, 0x82, 0x0b, 0x29, 0x46, 0xc4, 0xcb, - 0xb7, 0xf5, 0x00, 0x81, 0xc8, 0xf1, 0x2a, 0x6f, 0x5b, 0xe7, 0x5c, 0x92, 0xae, 0xd2, 0xa0, 0xae, - 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0x17, 0x3c, 0x89, 0xa8, 0xd2, 0x8b, 0xa6, 0x6d, + 0x32, 0x44, 0x95, 0x3a, 0x3c, 0xc8, 0x49, 0x67, 0x84, 0x70, 0xe1, 0x02, 0xd0, 0x3c, 0x09, 0x82, + 0xfd, 0x40, 0x50, 0x0b, 0xc6, 0x96, 0xd4, 0x8f, 0x3c, 0x06, 0x63, 0x61, 0x4d, 0xa7, 0x4d, 0x9b, + 0xf7, 0xa8, 0x15, 0xe2, 0xcf, 0x29, 0xa4, 0x30, 0x48, 0x67, 0xdd, 0x6c, 0xf1, 0x2e, 0x3a, 0xd5, + 0xb2, 0x7c, 0x63, 0x86, 0xe0, 0x76, 0x54, 0xfe, 0x5d, 0x5a, 0x54, 0x44, 0x06, 0x74, 0x0f, 0x01, + 0x50, 0xde, 0xdd, 0x4c, 0xbe, 0xba, 0x05, 0x8c, 0xdd, 0x17, 0x4d, 0x19, 0xcd, 0x46, 0x15, 0x69, + 0x24, 0xba, 0xbf, 0x40, 0xe5, 0x8e, 0xfc, 0xba, 0xba, 0x1d, 0xe3, 0xa0, 0x8c, 0xd5, 0xd0, 0x19, + 0x40, 0xf0, 0xcd, 0x5d, 0x84, 0x2f, 0x93, 0x8b, 0x24, 0xd1, 0xd9, 0x76, 0xe0, 0xa8, 0x2f, 0x20, + 0x65, 0xcb, 0x62, 0xc7, 0x64, 0x45, 0x50, 0x59, 0xd9, 0x24, 0x06, 0x22, 0x91, 0x35, 0xba, 0xec, + 0x42, 0xcb, 0x33, 0x30, 0x14, 0x0a, 0xd8, 0x47, 0x1c, 0x16, 0xe9, 0x13, 0x29, 0x3e, 0x53, 0x52, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -22729,9 +23089,9 @@ BINDATA_STORAGE_PVT kgspBinArchiveConcatenatedFMC_GH100_ucode_image_prod_storage #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 368640, // uncompressed data size (bytes) - 362878, // compressed data size (bytes) + 368640, // compressed data size (bytes) kgspBinArchiveConcatenatedFMC_GH100_ucode_image_prod_data, // compressed data pointer - NV_TRUE, // is pData compressed? + NV_FALSE, // is pData compressed? NV_TRUE, // contain information for file overriding? NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) }, diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c index d0f3acf2a3..391372c51f 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c @@ -32,10329 +32,10509 @@ // FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_dbg_image.bin // FILE TYPE: BINARY // VAR NAME: N/A -// COMPRESSION: YES +// COMPRESSION: NO // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 167936 -// COMPRESSED SIZE (bytes): 165043 +// COMPRESSED SIZE (bytes): N/A // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GH100_ucode_image_dbg_data[] = { - 0xec, 0x97, 0x43, 0x92, 0x28, 0x0a, 0x80, 0x20, 0xcb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, - 0x6d, 0xdb, 0xae, 0x57, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xf3, 0xe7, 0x02, 0xb3, 0x9a, 0x88, - 0xde, 0x74, 0x5e, 0x21, 0x37, 0x99, 0x00, 0x00, 0xff, 0xcb, 0xff, 0x24, 0x95, 0x66, 0x31, 0x4c, - 0x51, 0xd0, 0xde, 0x80, 0x97, 0xf3, 0x74, 0x1b, 0xd8, 0x1f, 0x8c, 0xe5, 0xe7, 0xc7, 0x01, 0xbd, - 0x17, 0x42, 0x82, 0x40, 0xa8, 0x01, 0xb0, 0x39, 0x1c, 0x91, 0xe9, 0x8b, 0xe9, 0x68, 0xb3, 0x5e, - 0x24, 0x34, 0x4a, 0xea, 0x5e, 0x6b, 0x6d, 0xa6, 0x4f, 0xc9, 0x66, 0x3a, 0xfc, 0xf2, 0xb6, 0xda, - 0x14, 0x49, 0xdc, 0x05, 0xa0, 0x89, 0x38, 0x61, 0x5a, 0xc8, 0xbb, 0xa6, 0x93, 0xbc, 0x46, 0x72, - 0x3c, 0x2a, 0xe4, 0x73, 0xfb, 0xc1, 0x94, 0x21, 0x8a, 0xe1, 0x4a, 0x95, 0xa3, 0xbc, 0x73, 0x0b, - 0x52, 0xc9, 0x23, 0x8e, 0xe1, 0xb4, 0xb7, 0x20, 0x31, 0x2a, 0x3e, 0x97, 0xad, 0x33, 0x92, 0x13, - 0x26, 0x3b, 0x69, 0xbe, 0xec, 0xde, 0xe4, 0xb9, 0xd1, 0x98, 0x1e, 0x32, 0xf1, 0x8a, 0xc1, 0xc4, - 0x22, 0x2b, 0x2d, 0xf7, 0x4d, 0xf3, 0x30, 0x76, 0x29, 0xaf, 0xfe, 0x1d, 0xde, 0xf1, 0xcc, 0x74, - 0xc0, 0xbb, 0x1d, 0x89, 0x83, 0x32, 0xb4, 0x8a, 0xe9, 0x14, 0xf7, 0x8a, 0xe3, 0xf4, 0xd2, 0x80, - 0xda, 0x6b, 0xc5, 0x90, 0xc6, 0xe2, 0x35, 0x3c, 0xcb, 0x60, 0xc6, 0x32, 0xab, 0xee, 0x58, 0x3d, - 0xc3, 0xbf, 0x6f, 0xe1, 0x43, 0x01, 0xd3, 0x90, 0x4b, 0x68, 0xd7, 0x5a, 0xd6, 0x1b, 0x5f, 0x47, - 0xae, 0x66, 0x3d, 0x63, 0x1a, 0x1f, 0xa7, 0xf0, 0x26, 0x71, 0x73, 0xd7, 0x4e, 0xab, 0xd8, 0x78, - 0x48, 0x18, 0xbf, 0x49, 0x20, 0x31, 0xef, 0xaa, 0x6e, 0x6b, 0xaa, 0x04, 0x63, 0x81, 0xbf, 0x21, - 0xe6, 0x99, 0xaf, 0x12, 0x51, 0x06, 0x6c, 0x58, 0xc2, 0x73, 0x16, 0x49, 0xac, 0x8c, 0x4a, 0x78, - 0xf4, 0x7a, 0xad, 0x38, 0x73, 0x54, 0x56, 0x6b, 0x3a, 0x0e, 0x32, 0xdd, 0x72, 0x01, 0xaf, 0xbe, - 0x86, 0x77, 0xec, 0xc1, 0x79, 0xca, 0xf4, 0xcd, 0x01, 0xe0, 0x13, 0xa4, 0xf5, 0xb9, 0x69, 0x04, - 0x94, 0x68, 0x88, 0x9f, 0x1a, 0xb1, 0xb4, 0x55, 0x4e, 0x3d, 0x10, 0xc4, 0x8f, 0xa4, 0xd8, 0xac, - 0x09, 0x0c, 0x98, 0x26, 0x8c, 0x54, 0x8c, 0x78, 0xa7, 0xc0, 0xbe, 0x5e, 0xde, 0x74, 0x9a, 0xd8, - 0x7a, 0x7a, 0xef, 0xfd, 0xda, 0xf9, 0x84, 0xdf, 0x23, 0xef, 0xda, 0xa9, 0x25, 0x72, 0x82, 0xe1, - 0xdd, 0xb4, 0x66, 0x36, 0xa7, 0x75, 0xc4, 0x59, 0x26, 0xe2, 0xc2, 0x36, 0xfb, 0xfe, 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -10365,9 +10545,9 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GH100_ucode_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 167936, // uncompressed data size (bytes) - 165043, // compressed data size (bytes) + 167936, // compressed data size (bytes) kgspBinArchiveGspRmBoot_GH100_ucode_image_dbg_data, // compressed data pointer - NV_TRUE, // is pData compressed? + NV_FALSE, // is pData compressed? NV_TRUE, // contain information for file overriding? NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) }, @@ -10414,10352 +10594,10509 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GH100_ucode_desc_dbg_storage_pvt; // FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_prd_image.bin // FILE TYPE: BINARY // VAR NAME: N/A -// COMPRESSION: YES +// COMPRESSION: NO // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 167936 -// COMPRESSED SIZE (bytes): 165420 +// COMPRESSED SIZE (bytes): N/A // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GH100_ucode_image_prod_data[] = { - 0x9c, 0x97, 0xc3, 0x96, 0x28, 0x0a, 0x94, 0x43, 0xcb, 0xb6, 0x6d, 0xbb, 0xea, 0x96, 0x6d, 0xdb, - 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0xd9, 0xef, 0x07, 0xba, 0x07, 0x9d, - 0x71, 0x06, 0x19, 0x9c, 0x75, 0xb2, 0xd3, 0xd7, 0x4e, 0xb9, 0xce, 0x91, 0x26, 0x64, 0x7a, 0x1d, - 0xca, 0xed, 0xf2, 0x82, 0x93, 0x00, 0x9a, 0xf9, 0xe0, 0xd0, 0x66, 0xd4, 0x58, 0x33, 0x8b, 0x2a, - 0x88, 0xdf, 0x4e, 0x76, 0x85, 0xef, 0x45, 0x85, 0x87, 0xff, 0x40, 0x1f, 0xa6, 0xd9, 0x71, 0xef, - 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kgspBinArchiveGspRmBoot_GH100_ucode_image_prod_data, // compressed data pointer - NV_TRUE, // is pData compressed? + NV_FALSE, // is pData compressed? NV_TRUE, // contain information for file overriding? NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) }, diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100.c index 4bd57bfeb0..fc82174fd3 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100.c @@ -32,10401 +32,10402 @@ // FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_cc_prd_gfw_image.bin // FILE TYPE: BINARY // VAR NAME: N/A -// COMPRESSION: YES +// COMPRESSION: NO // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 166216 -// COMPRESSED SIZE (bytes): 166202 +// COMPRESSED SIZE (bytes): N/A // static BINDATA_CONST NvU8 kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_image_data[] = { - 0x8c, 0x98, 0x43, 0x96, 0x28, 0x80, 0x82, 0x43, 0xcb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, - 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0x78, 0xa5, 0xfe, 0x8d, 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0x6e, 0xeb, 0xce, 0xc0, 0xaf, 0x00, 0x9f, 0x3f, 0xfd, 0x2a, 0x4d, 0x74, + 0xc2, 0x5e, 0x31, 0x64, 0x2c, 0x73, 0x12, 0x47, 0x47, 0x7c, 0xcd, 0xed, 0x2f, 0xae, 0x3b, 0x13, + 0xc7, 0xa1, 0x02, 0x8b, 0x86, 0xcd, 0xae, 0x7d, 0x9d, 0x70, 0x64, 0xfe, 0xd4, 0xaa, 0x77, 0x7d, + 0xe0, 0x17, 0x57, 0x8c, 0xd7, 0xdc, 0x18, 0x68, 0xa6, 0xd8, 0x9b, 0xc2, 0xdf, 0x8f, 0x3a, 0xa0, + 0xc9, 0x68, 0x70, 0x5a, 0x72, 0x1f, 0xf4, 0x2d, 0x16, 0x5b, 0x3f, 0xd0, 0x79, 0xb8, 0x97, 0xdf, + 0xb8, 0xd5, 0x04, 0x63, 0xfa, 0xc0, 0xcc, 0xe0, 0xf8, 0xf9, 0xd7, 0x9f, 0x39, 0x20, 0xed, 0xe6, + 0x11, 0x01, 0x10, 0x9e, 0x24, 0x3e, 0xca, 0xbf, 0xfe, 0x55, 0xa7, 0x36, 0xcd, 0xda, 0x91, 0x03, + 0x5d, 0xe5, 0x4c, 0x99, 0xc1, 0x07, 0x31, 0x86, 0x67, 0xd7, 0x87, 0x60, 0xa0, 0x2d, 0x4c, 0x93, + 0x87, 0xc6, 0x59, 0xe1, 0xa4, 0x57, 0x47, 0x56, 0x09, 0xe3, 0x74, 0x67, 0x59, 0x77, 0x95, 0xb3, + 0xa6, 0xfc, 0x18, 0xa3, 0x69, 0x16, 0xeb, 0xa6, 0x83, 0xb2, 0x30, 0x71, 0x05, 0xb6, 0x3c, 0xf8, + 0x5f, 0x20, 0x6d, 0x39, 0xab, 0xf5, 0xc3, 0x65, 0xbe, 0x33, 0xc5, 0xa8, 0x25, 0x89, 0x24, 0xce, + 0xc9, 0xa3, 0x96, 0x0f, 0x3a, 0x12, 0xe2, 0x5c, 0x09, 0x85, 0x40, 0xf1, 0x5b, 0x86, 0x50, 0xfa, + 0x20, 0x14, 0x1d, 0xc5, 0x3c, 0x2f, 0x7f, 0x7e, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -10437,9 +10438,9 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_image_stor #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 166216, // uncompressed data size (bytes) - 166202, // compressed data size (bytes) + 166216, // compressed data size (bytes) kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_image_data, // compressed data pointer - NV_TRUE, // is pData compressed? + NV_FALSE, // is pData compressed? NV_TRUE, // contain information for file overriding? NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) }, @@ -10452,17 +10453,16 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_image_stor // FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_cc_prd_gfw_hash.bin // FILE TYPE: BINARY // VAR NAME: N/A -// COMPRESSION: YES +// COMPRESSION: NO // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 48 -// COMPRESSED SIZE (bytes): 61 +// COMPRESSED SIZE (bytes): N/A // static BINDATA_CONST NvU8 kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_hash_data[] = { - 0x01, 0x30, 0x00, 0xcf, 0xff, 0x33, 0x70, 0xb6, 0xfa, 0x32, 0x9f, 0xb8, 0xe3, 0x6a, 0xaa, 0x2b, - 0x47, 0xd3, 0x31, 0x28, 0x07, 0x21, 0x15, 0x0b, 0xf1, 0x56, 0x7b, 0x88, 0x0e, 0x57, 0xc2, 0x6f, - 0x9f, 0x60, 0x96, 0xfa, 0xba, 0xbb, 0xac, 0x60, 0x92, 0x2f, 0x8d, 0x0b, 0x57, 0xca, 0x68, 0x04, - 0x4f, 0xc4, 0xc6, 0xc4, 0x75, 0x19, 0x1b, 0xbf, 0x3f, 0x30, 0x00, 0x00, 0x00, + 0xa1, 0x93, 0x1e, 0x90, 0x92, 0x3a, 0x33, 0x50, 0x5c, 0xe1, 0x32, 0x92, 0x8b, 0xcf, 0x80, 0x55, + 0x66, 0x11, 0x7d, 0xc2, 0x7e, 0xe1, 0xd6, 0x18, 0x9c, 0x14, 0xe9, 0x2f, 0xb3, 0xcb, 0x05, 0xc1, + 0x20, 0xc4, 0xb2, 0x26, 0xa0, 0x7c, 0x1a, 0xaf, 0x8e, 0x4c, 0x0f, 0x0f, 0xea, 0x4a, 0xf2, 0x4d, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -10473,9 +10473,9 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_hash_stora #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 48, // uncompressed data size (bytes) - 61, // compressed data size (bytes) + 48, // compressed data size (bytes) kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_hash_data, // compressed data pointer - NV_TRUE, // is pData compressed? + NV_FALSE, // is pData compressed? NV_TRUE, // contain information for file overriding? NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) }, @@ -10488,38 +10488,37 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_hash_stora // FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_cc_prd_gfw_sig.bin // FILE TYPE: BINARY // VAR NAME: N/A -// COMPRESSION: YES +// COMPRESSION: NO // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 384 -// COMPRESSED SIZE (bytes): 397 +// COMPRESSED SIZE (bytes): N/A // static BINDATA_CONST NvU8 kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_sig_data[] = { - 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x30, 0xbd, 0x34, 0xb2, 0x70, 0x25, 0x20, 0x8c, 0x58, 0xb7, 0x65, - 0x4c, 0x15, 0x74, 0xdd, 0x18, 0xcf, 0xff, 0x7b, 0xa3, 0x90, 0x03, 0x08, 0x31, 0xf9, 0xba, 0x5b, - 0x23, 0x32, 0x5a, 0xb8, 0x01, 0xa2, 0x7a, 0x21, 0x8e, 0x2f, 0x2d, 0xba, 0x9e, 0xe8, 0xcb, 0x11, - 0xad, 0x05, 0xe3, 0x4d, 0xd3, 0xaf, 0xcb, 0xbc, 0xec, 0x1b, 0xf5, 0xc1, 0xa1, 0xab, 0x72, 0x3c, - 0xb8, 0x28, 0x5d, 0x76, 0x14, 0x80, 0x4d, 0x84, 0x02, 0x67, 0xc0, 0x31, 0x25, 0xa4, 0x67, 0x22, - 0xef, 0x86, 0x6e, 0x8a, 0x2b, 0x39, 0x3a, 0x8d, 0x01, 0xf6, 0x5c, 0x0c, 0xfb, 0xa8, 0x92, 0x8a, - 0x6e, 0x03, 0xcd, 0x50, 0xe9, 0x8d, 0x5f, 0xaa, 0xbd, 0x7a, 0x36, 0x1b, 0x9c, 0x53, 0x7c, 0x57, - 0x8c, 0xc2, 0xf7, 0xc5, 0x44, 0x3f, 0x59, 0xf4, 0xac, 0x97, 0xfa, 0x8b, 0x2b, 0x3d, 0xc1, 0x3c, - 0x30, 0x7d, 0xf9, 0x3d, 0xeb, 0xda, 0xb2, 0x29, 0x5b, 0xc9, 0x7c, 0xc7, 0x4e, 0x25, 0x9f, 0x19, - 0x2c, 0x82, 0x0f, 0xb2, 0x35, 0x7a, 0x7c, 0x2b, 0x20, 0x7d, 0x3a, 0x72, 0x95, 0x1d, 0xc4, 0xbd, - 0x41, 0x0c, 0x00, 0x25, 0x46, 0x9b, 0xa0, 0x3c, 0x07, 0x4d, 0xd2, 0x3c, 0x58, 0x2c, 0xd3, 0x48, - 0x2f, 0x5f, 0x44, 0x28, 0x13, 0x86, 0xff, 0xf1, 0xae, 0x7d, 0x6e, 0x51, 0x93, 0x50, 0xbc, 0xef, - 0xc9, 0xf5, 0xed, 0xd0, 0xc1, 0x6d, 0x05, 0x0a, 0xea, 0xca, 0x8e, 0x54, 0xf5, 0x08, 0xa4, 0x83, - 0x3a, 0xa6, 0xf7, 0x69, 0xc1, 0x09, 0x60, 0x28, 0xd3, 0x78, 0x99, 0xda, 0x9a, 0x00, 0x3c, 0x87, - 0xa1, 0x40, 0x38, 0xf3, 0xde, 0x67, 0x1e, 0xdb, 0x7b, 0x70, 0x4a, 0x7b, 0x22, 0xc2, 0x52, 0xba, - 0x90, 0x67, 0x57, 0xdd, 0x8d, 0x19, 0xd3, 0x91, 0x90, 0xf9, 0x3f, 0xf3, 0x4b, 0xff, 0xe7, 0x1c, - 0x7b, 0x32, 0x35, 0x6f, 0x1e, 0x77, 0x47, 0x3f, 0xb9, 0xcc, 0x22, 0x28, 0xaf, 0x6c, 0x46, 0x7c, - 0x3f, 0xc8, 0x26, 0x29, 0xab, 0x08, 0x0a, 0xf5, 0xac, 0xa9, 0x0b, 0xea, 0xcf, 0x07, 0xe5, 0xc2, - 0x4e, 0xe3, 0xc4, 0x51, 0xf4, 0x2f, 0x61, 0xa4, 0x4b, 0x37, 0x1b, 0x2d, 0x5d, 0x53, 0x6d, 0x75, - 0x7f, 0xbd, 0x3a, 0x90, 0xf2, 0x39, 0x7b, 0x20, 0x9d, 0x21, 0x8e, 0x02, 0xb6, 0x9b, 0x2e, 0xb1, - 0x72, 0xa3, 0x05, 0x05, 0x13, 0x98, 0x3b, 0x45, 0xac, 0x59, 0x64, 0xf0, 0xc0, 0xb8, 0xb5, 0x61, - 0xba, 0xcb, 0x35, 0x48, 0x58, 0x5f, 0x00, 0xff, 0xfd, 0x39, 0xb3, 0xae, 0xee, 0xd9, 0xe6, 0xbe, - 0xa6, 0x4b, 0xe3, 0xe7, 0x7f, 0x31, 0xf6, 0xc5, 0xbe, 0xfc, 0xe7, 0xb1, 0xa7, 0xc3, 0x1d, 0xbf, - 0x18, 0xd2, 0x19, 0xc4, 0xfd, 0xa0, 0x1e, 0xba, 0x9a, 0x60, 0xaa, 0x55, 0x4b, 0xc0, 0x78, 0x9d, - 0x36, 0x06, 0x09, 0xab, 0xcd, 0xbb, 0x92, 0xab, 0x37, 0x80, 0x01, 0x00, 0x00, + 0x80, 0xaf, 0xa9, 0x02, 0xb2, 0xb3, 0x77, 0xf8, 0xa3, 0x6d, 0x35, 0x24, 0x7f, 0x44, 0x39, 0x42, + 0x93, 0x08, 0xc8, 0xf1, 0xfd, 0x74, 0xfa, 0xe3, 0x11, 0x11, 0x64, 0xc4, 0x1f, 0x2c, 0xf4, 0x6b, + 0x3c, 0xd5, 0x7a, 0xaf, 0x33, 0x79, 0x9e, 0xf7, 0xf5, 0x78, 0xdc, 0xbe, 0xb7, 0x99, 0xea, 0x30, + 0x25, 0x21, 0xe7, 0x1b, 0xa4, 0x80, 0xa4, 0x6e, 0x57, 0xe1, 0x65, 0x3b, 0x3f, 0xe6, 0xc5, 0x40, + 0x03, 0x27, 0xf9, 0x91, 0x3c, 0xa7, 0xee, 0xe9, 0x15, 0xe3, 0x20, 0x1d, 0x72, 0xd4, 0x01, 0x14, + 0x10, 0xb5, 0x1d, 0x30, 0xe5, 0x99, 0x09, 0xf7, 0x5e, 0x77, 0x2a, 0xb3, 0x89, 0xbb, 0x24, 0x9d, + 0x45, 0x3f, 0xf8, 0x85, 0x8c, 0x6c, 0xa9, 0x63, 0xc0, 0x63, 0x09, 0x06, 0x71, 0x2c, 0xaa, 0x7c, + 0x98, 0xf6, 0x4d, 0x41, 0xf2, 0xa4, 0xc9, 0x25, 0x58, 0xc1, 0x61, 0x8b, 0xb7, 0x05, 0xfd, 0x57, + 0x24, 0x0b, 0x10, 0xb6, 0x1e, 0xf9, 0x91, 0x2f, 0xfa, 0xcd, 0x9a, 0x30, 0x69, 0x0f, 0x26, 0x8f, + 0xdc, 0x1e, 0x77, 0x0a, 0xcf, 0xcd, 0xeb, 0x11, 0x9f, 0xe6, 0x13, 0xc6, 0x98, 0x6b, 0x6b, 0x2d, + 0x35, 0xc6, 0x7d, 0x17, 0x5d, 0xac, 0x17, 0xc4, 0x3d, 0x38, 0x21, 0x94, 0x5e, 0x4e, 0x70, 0x11, + 0x19, 0x6b, 0xf8, 0x28, 0x1f, 0xed, 0xf3, 0x2f, 0xbc, 0x22, 0x13, 0x84, 0xd7, 0xef, 0xbe, 0x38, + 0x96, 0x18, 0x81, 0xe9, 0x61, 0x6b, 0x54, 0x16, 0x92, 0xa5, 0xf3, 0xb9, 0x0b, 0x16, 0x53, 0xe2, + 0x1f, 0xd5, 0xd7, 0x90, 0x41, 0x81, 0xc2, 0x53, 0x07, 0xad, 0x5c, 0x3f, 0xce, 0xa3, 0x83, 0xf2, + 0x63, 0x7e, 0xba, 0xdf, 0x8d, 0x79, 0x59, 0x8d, 0x55, 0x6e, 0xab, 0x2c, 0x8f, 0xf8, 0xed, 0x54, + 0xc4, 0x78, 0x76, 0x62, 0xdb, 0x07, 0x9f, 0x87, 0xd4, 0x99, 0x13, 0xc7, 0xf3, 0x60, 0x83, 0x96, + 0x91, 0x0b, 0xba, 0xbf, 0x0b, 0x61, 0xad, 0xd0, 0xf4, 0xaa, 0xcd, 0xba, 0x63, 0xb4, 0xae, 0xb7, + 0xbf, 0xb0, 0xdf, 0x63, 0x3c, 0xdc, 0xfa, 0xea, 0xe6, 0x3c, 0xcd, 0x0a, 0xa5, 0xc9, 0x3c, 0x04, + 0x9b, 0x80, 0x0f, 0x32, 0x38, 0x11, 0xdf, 0x26, 0xf7, 0xc2, 0xba, 0x5f, 0xe7, 0xdb, 0xb0, 0x97, + 0x72, 0x94, 0x11, 0x8b, 0x4e, 0x81, 0xdd, 0xf8, 0x7f, 0x74, 0x55, 0xdd, 0x0c, 0xc2, 0xe4, 0xd3, + 0xb9, 0x41, 0xe9, 0xd4, 0x98, 0x0f, 0x65, 0x16, 0xa7, 0x38, 0x99, 0x2f, 0x9e, 0xf3, 0x55, 0x41, + 0xa5, 0x6c, 0xc6, 0xc1, 0x1b, 0xb9, 0x16, 0xbb, 0x62, 0x2e, 0x96, 0xad, 0x94, 0xd2, 0xe3, 0x75, + 0xc2, 0x0b, 0xf4, 0x86, 0xac, 0x22, 0xc9, 0x4f, 0x8f, 0x9d, 0x11, 0xe9, 0x4e, 0x09, 0x95, 0x71, + 0x3d, 0xc7, 0x5a, 0x6c, 0x52, 0x94, 0x6d, 0x2e, 0x8c, 0xf4, 0xce, 0xa6, 0x87, 0xa1, 0xf2, 0xd0, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -10530,9 +10529,9 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_sig_storag #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 384, // uncompressed data size (bytes) - 397, // compressed data size (bytes) + 384, // compressed data size (bytes) kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_sig_data, // compressed data pointer - NV_TRUE, // is pData compressed? + NV_FALSE, // is pData compressed? NV_TRUE, // contain information for file overriding? NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) }, @@ -10545,38 +10544,37 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_sig_storag // FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_cc_prd_gfw_pub_key.bin // FILE TYPE: BINARY // VAR NAME: N/A -// COMPRESSION: YES +// COMPRESSION: NO // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 384 -// COMPRESSED SIZE (bytes): 397 +// COMPRESSED SIZE (bytes): N/A // static BINDATA_CONST NvU8 kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_pkey_data[] = { - 0x01, 0x80, 0x01, 0x7f, 0xfe, 0xb6, 0x61, 0x74, 0x8c, 0x50, 0xfd, 0x5d, 0x6b, 0xbc, 0x71, 0xe9, - 0xcf, 0x5e, 0xf6, 0x8b, 0x5d, 0xd5, 0x36, 0xe8, 0xaf, 0xca, 0x7a, 0x14, 0x6a, 0x3d, 0x1f, 0xa6, - 0x8b, 0x37, 0xf9, 0x3e, 0x5a, 0x44, 0xec, 0xb6, 0x6a, 0x39, 0x25, 0x78, 0xce, 0xd6, 0xf0, 0xe2, - 0xa1, 0x40, 0xae, 0x82, 0x22, 0x60, 0xaa, 0xf3, 0x6a, 0xd3, 0x4d, 0xe6, 0xc1, 0x38, 0x18, 0x4e, - 0xfc, 0xd6, 0x6c, 0x61, 0x38, 0x73, 0x13, 0x26, 0x71, 0xa8, 0xb8, 0x9c, 0xeb, 0x07, 0x28, 0x4e, - 0x86, 0x2b, 0xe2, 0x5e, 0xf8, 0xfd, 0x2c, 0x01, 0x51, 0x6f, 0x1c, 0xf9, 0x47, 0x36, 0x62, 0xcc, - 0x59, 0x24, 0x67, 0xf8, 0x5d, 0x13, 0x39, 0x52, 0xd9, 0x0b, 0xbf, 0x92, 0x98, 0xad, 0x98, 0x2b, - 0x53, 0x4d, 0x35, 0xda, 0x06, 0x7e, 0x89, 0x07, 0x2f, 0xb0, 0x0f, 0x12, 0x44, 0x1d, 0xe8, 0xa8, - 0xed, 0x40, 0x9c, 0x84, 0x8a, 0x99, 0x7e, 0x09, 0x05, 0xee, 0x9c, 0x62, 0x2a, 0x6e, 0xdb, 0xe3, - 0xc2, 0x7c, 0x39, 0x7c, 0xdb, 0x30, 0x49, 0x26, 0x58, 0xf1, 0x94, 0xa6, 0xd1, 0x8b, 0xda, 0x79, - 0x18, 0xed, 0x12, 0xdf, 0x72, 0xfd, 0x5b, 0x3d, 0x13, 0xab, 0xcc, 0xce, 0x20, 0x80, 0xd8, 0xe7, - 0x5d, 0x6c, 0xcf, 0x3e, 0x3a, 0x7c, 0x29, 0xda, 0xf4, 0xdb, 0x7a, 0xc0, 0x2a, 0x4d, 0xc7, 0xdc, - 0xe8, 0x09, 0xe6, 0x2a, 0xca, 0x6c, 0x33, 0xed, 0xf1, 0x96, 0xe5, 0x26, 0xb0, 0xc6, 0xcc, 0x22, - 0x15, 0xd2, 0x42, 0x47, 0x71, 0xe5, 0x6d, 0x2e, 0xda, 0xcd, 0x1d, 0x28, 0x59, 0xe9, 0x4d, 0x48, - 0xca, 0x36, 0xd4, 0x85, 0x6a, 0x26, 0x8e, 0x3e, 0xc7, 0xd7, 0x14, 0x77, 0x5e, 0x54, 0xda, 0x98, - 0xf8, 0x65, 0xaf, 0xea, 0x63, 0x46, 0xcd, 0xca, 0xd0, 0xbf, 0x9e, 0x31, 0xb2, 0x24, 0x7f, 0x4e, - 0xe5, 0xa3, 0x32, 0x5e, 0x22, 0x3a, 0xed, 0xed, 0xbe, 0xad, 0x5e, 0xa2, 0x36, 0x07, 0x41, 0x7f, - 0x94, 0x7b, 0x6f, 0x77, 0xea, 0xf6, 0xf3, 0x4e, 0xd3, 0x47, 0x39, 0x9c, 0xd0, 0x96, 0x70, 0x78, - 0x0c, 0x30, 0x9a, 0xa7, 0xe7, 0x85, 0x7e, 0xa6, 0xce, 0x00, 0x86, 0xfb, 0x91, 0xef, 0xe3, 0x31, - 0x1f, 0xc1, 0x5e, 0xda, 0xf3, 0x59, 0xdd, 0x36, 0xfe, 0x19, 0x2b, 0xca, 0xa4, 0x46, 0x5a, 0x52, - 0xaa, 0x65, 0x31, 0x00, 0x0b, 0x61, 0x57, 0x30, 0x8b, 0x0d, 0x13, 0xe6, 0xdc, 0xb3, 0x64, 0x61, - 0x98, 0x07, 0x52, 0xbc, 0x3e, 0x05, 0x26, 0x84, 0x96, 0xd0, 0x85, 0x62, 0x72, 0xd3, 0x9f, 0x60, - 0xf9, 0xc1, 0x33, 0x69, 0x1b, 0x49, 0x3e, 0x74, 0x08, 0x51, 0x2e, 0x97, 0x1b, 0x45, 0x54, 0x7c, - 0x4b, 0xd1, 0x51, 0x83, 0xaa, 0xf0, 0x9b, 0xff, 0x0c, 0xfb, 0x2f, 0x33, 0xcd, 0xe5, 0x1b, 0xcf, - 0x4f, 0x02, 0x0d, 0xf6, 0x1b, 0xdb, 0x48, 0x80, 0x58, 0x80, 0x01, 0x00, 0x00, + 0xb6, 0x61, 0x74, 0x8c, 0x50, 0xfd, 0x5d, 0x6b, 0xbc, 0x71, 0xe9, 0xcf, 0x5e, 0xf6, 0x8b, 0x5d, + 0xd5, 0x36, 0xe8, 0xaf, 0xca, 0x7a, 0x14, 0x6a, 0x3d, 0x1f, 0xa6, 0x8b, 0x37, 0xf9, 0x3e, 0x5a, + 0x44, 0xec, 0xb6, 0x6a, 0x39, 0x25, 0x78, 0xce, 0xd6, 0xf0, 0xe2, 0xa1, 0x40, 0xae, 0x82, 0x22, + 0x60, 0xaa, 0xf3, 0x6a, 0xd3, 0x4d, 0xe6, 0xc1, 0x38, 0x18, 0x4e, 0xfc, 0xd6, 0x6c, 0x61, 0x38, + 0x73, 0x13, 0x26, 0x71, 0xa8, 0xb8, 0x9c, 0xeb, 0x07, 0x28, 0x4e, 0x86, 0x2b, 0xe2, 0x5e, 0xf8, + 0xfd, 0x2c, 0x01, 0x51, 0x6f, 0x1c, 0xf9, 0x47, 0x36, 0x62, 0xcc, 0x59, 0x24, 0x67, 0xf8, 0x5d, + 0x13, 0x39, 0x52, 0xd9, 0x0b, 0xbf, 0x92, 0x98, 0xad, 0x98, 0x2b, 0x53, 0x4d, 0x35, 0xda, 0x06, + 0x7e, 0x89, 0x07, 0x2f, 0xb0, 0x0f, 0x12, 0x44, 0x1d, 0xe8, 0xa8, 0xed, 0x40, 0x9c, 0x84, 0x8a, + 0x99, 0x7e, 0x09, 0x05, 0xee, 0x9c, 0x62, 0x2a, 0x6e, 0xdb, 0xe3, 0xc2, 0x7c, 0x39, 0x7c, 0xdb, + 0x30, 0x49, 0x26, 0x58, 0xf1, 0x94, 0xa6, 0xd1, 0x8b, 0xda, 0x79, 0x18, 0xed, 0x12, 0xdf, 0x72, + 0xfd, 0x5b, 0x3d, 0x13, 0xab, 0xcc, 0xce, 0x20, 0x80, 0xd8, 0xe7, 0x5d, 0x6c, 0xcf, 0x3e, 0x3a, + 0x7c, 0x29, 0xda, 0xf4, 0xdb, 0x7a, 0xc0, 0x2a, 0x4d, 0xc7, 0xdc, 0xe8, 0x09, 0xe6, 0x2a, 0xca, + 0x6c, 0x33, 0xed, 0xf1, 0x96, 0xe5, 0x26, 0xb0, 0xc6, 0xcc, 0x22, 0x15, 0xd2, 0x42, 0x47, 0x71, + 0xe5, 0x6d, 0x2e, 0xda, 0xcd, 0x1d, 0x28, 0x59, 0xe9, 0x4d, 0x48, 0xca, 0x36, 0xd4, 0x85, 0x6a, + 0x26, 0x8e, 0x3e, 0xc7, 0xd7, 0x14, 0x77, 0x5e, 0x54, 0xda, 0x98, 0xf8, 0x65, 0xaf, 0xea, 0x63, + 0x46, 0xcd, 0xca, 0xd0, 0xbf, 0x9e, 0x31, 0xb2, 0x24, 0x7f, 0x4e, 0xe5, 0xa3, 0x32, 0x5e, 0x22, + 0x3a, 0xed, 0xed, 0xbe, 0xad, 0x5e, 0xa2, 0x36, 0x07, 0x41, 0x7f, 0x94, 0x7b, 0x6f, 0x77, 0xea, + 0xf6, 0xf3, 0x4e, 0xd3, 0x47, 0x39, 0x9c, 0xd0, 0x96, 0x70, 0x78, 0x0c, 0x30, 0x9a, 0xa7, 0xe7, + 0x85, 0x7e, 0xa6, 0xce, 0x00, 0x86, 0xfb, 0x91, 0xef, 0xe3, 0x31, 0x1f, 0xc1, 0x5e, 0xda, 0xf3, + 0x59, 0xdd, 0x36, 0xfe, 0x19, 0x2b, 0xca, 0xa4, 0x46, 0x5a, 0x52, 0xaa, 0x65, 0x31, 0x00, 0x0b, + 0x61, 0x57, 0x30, 0x8b, 0x0d, 0x13, 0xe6, 0xdc, 0xb3, 0x64, 0x61, 0x98, 0x07, 0x52, 0xbc, 0x3e, + 0x05, 0x26, 0x84, 0x96, 0xd0, 0x85, 0x62, 0x72, 0xd3, 0x9f, 0x60, 0xf9, 0xc1, 0x33, 0x69, 0x1b, + 0x49, 0x3e, 0x74, 0x08, 0x51, 0x2e, 0x97, 0x1b, 0x45, 0x54, 0x7c, 0x4b, 0xd1, 0x51, 0x83, 0xaa, + 0xf0, 0x9b, 0xff, 0x0c, 0xfb, 0x2f, 0x33, 0xcd, 0xe5, 0x1b, 0xcf, 0x4f, 0x02, 0x0d, 0xf6, 0x1b, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -10587,9 +10585,9 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_pkey_stora #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 384, // uncompressed data size (bytes) - 397, // compressed data size (bytes) + 384, // compressed data size (bytes) kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_pkey_data, // compressed data pointer - NV_TRUE, // is pData compressed? + NV_FALSE, // is pData compressed? NV_TRUE, // contain information for file overriding? NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) }, diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100.c index 346f7e4b05..ea1a5ec7f4 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100.c @@ -32,10329 +32,10354 @@ // FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_dbg_gfw_image.bin // FILE TYPE: BINARY // VAR NAME: N/A -// COMPRESSION: YES +// COMPRESSION: NO // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 165448 -// COMPRESSED SIZE (bytes): 165052 +// COMPRESSED SIZE (bytes): N/A // static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_image_data[] = { - 0x00, 0x3a, 0x80, 0xc5, 0x7f, 0x03, 0x04, 0x48, 0x00, 0x00, 0x86, 0x02, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0xd5, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7, 0x00, 0x00, 0x04, 0x01, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x03, 0x04, 0x48, 0x00, 0x00, 0x86, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd5, 0x01, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7, 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x4b, 0x0c, 0x6e, - 0x6f, 0x33, 0x11, 0xa5, 0x5a, 0x0c, 0x36, 0x41, 0x93, 0xb7, 0xdb, 0x27, 0x54, 0x5b, 0x60, 0x84, - 0xa6, 0x2d, 0x3e, 0xc2, 0x42, 0xbb, 0xb3, 0x10, 0x64, 0x4e, 0x7d, 0xa0, 0x34, 0x85, 0xd4, 0xb8, - 0x82, 0x47, 0x08, 0xf9, 0x4e, 0x9d, 0xa6, 0xca, 0x46, 0xbc, 0x2e, 0xb8, 0x31, 0x0a, 0xf4, 0xc2, - 0xab, 0xe7, 0x84, 0x86, 0xea, 0x28, 0x8b, 0x9b, 0x37, 0x70, 0x0b, 0x32, 0x2f, 0x2d, 0xd6, 0xe5, - 0x23, 0x1b, 0x99, 0xef, 0x06, 0x4a, 0x28, 0x7d, 0x6d, 0xcf, 0x58, 0xc8, 0x23, 0xa3, 0x6e, 0x74, - 0x7c, 0xa8, 0x6d, 0x77, 0x20, 0xda, 0x1d, 0x11, 0x1b, 0x4f, 0xc6, 0xd8, 0xdb, 0xc9, 0xc6, 0x37, - 0xba, 0x6f, 0x36, 0xa3, 0xcb, 0xb4, 0xde, 0x93, 0x57, 0x42, 0xc1, 0xd6, 0x53, 0x4e, 0x8a, 0x9b, - 0x07, 0xbb, 0x90, 0x38, 0xae, 0x93, 0x27, 0xf1, 0x45, 0x48, 0xa4, 0x4c, 0x20, 0xf9, 0x7f, 0xda, - 0x4a, 0xde, 0xe0, 0x98, 0x07, 0xc9, 0x5b, 0xe9, 0xe9, 0xbb, 0xf9, 0x2a, 0x81, 0xf5, 0xdf, 0x63, - 0xb0, 0xaf, 0x19, 0x35, 0x72, 0xde, 0xda, 0xc6, 0x55, 0x90, 0x9c, 0x62, 0xe3, 0x2e, 0x6f, 0x4d, - 0xb2, 0x9a, 0x2f, 0x7a, 0xea, 0xba, 0xe7, 0xac, 0x42, 0xa9, 0xca, 0xdf, 0x6f, 0xcf, 0xa8, 0x4c, - 0xb1, 0x27, 0x65, 0xae, 0xcd, 0x3a, 0x39, 0x8c, 0x57, 0xbb, 0x6e, 0xb2, 0xff, 0x82, 0xe7, 0x32, - 0xdc, 0x4a, 0x62, 0x24, 0x3c, 0xb3, 0xbb, 0x79, 0xef, 0xc8, 0xdd, 0xc6, 0xe5, 0x62, 0x09, 0xf4, - 0x68, 0x05, 0xaa, 0x33, 0x02, 0x51, 0xc6, 0x64, 0x54, 0x68, 0x02, 0xa7, 0xd0, 0x2d, 0xcc, 0xa4, - 0x2a, 0x47, 0x42, 0x83, 0x02, 0x0f, 0x37, 0xfb, 0xaf, 0xde, 0xbd, 0x94, 0x03, 0x89, 0x4b, 0x68, - 0xe3, 0xe3, 0xd0, 0xf3, 0x32, 0xe6, 0xc2, 0xac, 0x72, 0x76, 0x38, 0xc9, 0xc3, 0x5e, 0x3a, 0x67, - 0x57, 0xf8, 0x92, 0x56, 0x0d, 0x06, 0x7f, 0x92, 0xc0, 0xc1, 0xb2, 0x83, 0x11, 0x7a, 0x44, 0x6a, - 0xf0, 0xf0, 0x21, 0x2c, 0x8e, 0x9c, 0x6b, 0x89, 0x9d, 0x29, 0xe3, 0x4f, 0x67, 0x81, 0x14, 0x42, - 0x14, 0x68, 0x91, 0x9c, 0x2f, 0xd4, 0xec, 0xfc, 0x45, 0xd3, 0xe1, 0x4d, 0x6f, 0x4d, 0x3d, 0xe8, - 0xae, 0xb9, 0x23, 0xa1, 0x18, 0x66, 0xe7, 0x74, 0xd9, 0x82, 0x99, 0xd0, 0x29, 0x8e, 0x96, 0x04, - 0xda, 0xa0, 0xe8, 0x6d, 0x5b, 0xfe, 0xfe, 0x60, 0xac, 0xae, 0x5e, 0xac, 0xfc, 0x5c, 0x1a, 0x15, - 0xb8, 0x18, 0xa6, 0x03, 0x52, 0x49, 0x70, 0xae, 0xad, 0xe5, 0x8c, 0x2b, 0xe7, 0x05, 0xd0, 0x52, - 0x45, 0xea, 0xd6, 0x15, 0x76, 0x33, 0x84, 0xc5, 0x7b, 0x77, 0x1d, 0xa5, 0xc2, 0x9a, 0x9b, 0xbd, - 0x43, 0x9a, 0x11, 0x52, 0x24, 0xa5, 0x43, 0xbb, 0x87, 0xb0, 0x9a, 0x0b, 0x86, 0x06, 0xc4, 0xfd, - 0x0f, 0xb8, 0x60, 0xb1, 0x5f, 0x94, 0x29, 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0xb7, 0x66, 0xb9, 0xf8, 0x88, 0x49, 0x62, 0x4a, 0x43, 0x4f, 0x90, 0x3e, 0x76, + 0x06, 0x65, 0x5d, 0x42, 0xa5, 0xe2, 0x05, 0x2c, 0xf6, 0x56, 0x99, 0xa7, 0x5b, 0xcc, 0x31, 0x77, + 0x4c, 0x41, 0x63, 0x9e, 0x73, 0x5d, 0x72, 0xd4, 0xc2, 0x1f, 0x67, 0x5d, 0x2e, 0xf0, 0x47, 0x15, + 0xd5, 0x81, 0xa3, 0x14, 0xba, 0x06, 0x79, 0x84, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -10365,9 +10390,9 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_image_stora #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 165448, // uncompressed data size (bytes) - 165052, // compressed data size (bytes) + 165448, // compressed data size (bytes) kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_image_data, // compressed data pointer - NV_TRUE, // is pData compressed? + NV_FALSE, // is pData compressed? NV_TRUE, // contain information for file overriding? NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) }, @@ -10380,17 +10405,16 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_image_stora // FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_dbg_gfw_hash.bin // FILE TYPE: BINARY // VAR NAME: N/A -// COMPRESSION: YES +// COMPRESSION: NO // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 48 -// COMPRESSED SIZE (bytes): 61 +// COMPRESSED SIZE (bytes): N/A // static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_hash_data[] = { - 0x01, 0x30, 0x00, 0xcf, 0xff, 0x60, 0xb9, 0x62, 0x09, 0xb1, 0xef, 0xf4, 0xee, 0xec, 0x2e, 0xf9, - 0x0a, 0x1f, 0xc1, 0x16, 0x10, 0xf2, 0x41, 0x06, 0xf5, 0x6b, 0xe5, 0x48, 0x15, 0x95, 0x62, 0xdf, - 0x64, 0x91, 0x61, 0x4e, 0x33, 0xb5, 0xf4, 0xe4, 0x61, 0xaf, 0xc2, 0x0a, 0xaf, 0x92, 0x6a, 0xe4, - 0x63, 0x20, 0x56, 0x12, 0x27, 0xc1, 0xe6, 0xe2, 0x0b, 0x30, 0x00, 0x00, 0x00, + 0x36, 0x00, 0x33, 0x10, 0xa8, 0xcd, 0x15, 0x1f, 0xf7, 0xb0, 0x68, 0xe2, 0xb8, 0x70, 0x81, 0x0a, + 0x03, 0x81, 0x25, 0xa8, 0x4d, 0x6e, 0x50, 0xb5, 0xf7, 0x87, 0x10, 0x61, 0xc9, 0xa8, 0x0e, 0x42, + 0xbd, 0xa5, 0x5a, 0x43, 0x7d, 0x0a, 0xd2, 0xd8, 0xb1, 0x06, 0x64, 0x1a, 0xae, 0x0c, 0x72, 0x39, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -10401,9 +10425,9 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_hash_storag #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 48, // uncompressed data size (bytes) - 61, // compressed data size (bytes) + 48, // compressed data size (bytes) kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_hash_data, // compressed data pointer - NV_TRUE, // is pData compressed? + NV_FALSE, // is pData compressed? NV_TRUE, // contain information for file overriding? NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) }, @@ -10416,38 +10440,37 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_hash_storag // FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_dbg_gfw_sig.bin // FILE TYPE: BINARY // VAR NAME: N/A -// COMPRESSION: YES +// COMPRESSION: NO // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 384 -// COMPRESSED SIZE (bytes): 397 +// COMPRESSED SIZE (bytes): N/A // static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_sig_data[] = { - 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x2c, 0x92, 0xee, 0x99, 0x44, 0x6d, 0xc1, 0x10, 0xd4, 0x4c, 0xf7, - 0xfb, 0xe8, 0xa3, 0x56, 0x64, 0x13, 0x42, 0x3f, 0xac, 0xf7, 0x76, 0x80, 0x9d, 0x58, 0x01, 0x9b, - 0xfa, 0x5f, 0x2f, 0xf5, 0x9d, 0x6a, 0x98, 0xce, 0x9e, 0x71, 0x33, 0x0a, 0xe7, 0xea, 0x2c, 0x8f, - 0x34, 0x13, 0x72, 0x7f, 0xcf, 0x2b, 0xfc, 0x61, 0x8d, 0x02, 0xcd, 0x7a, 0xc7, 0x85, 0xd7, 0x05, - 0x48, 0x1f, 0x6b, 0xdf, 0x6a, 0xf5, 0x08, 0xe0, 0x8d, 0x08, 0xc4, 0xf3, 0x0b, 0x64, 0x9b, 0xc4, - 0x40, 0x7a, 0x54, 0x7b, 0xab, 0x81, 0x37, 0xba, 0x87, 0x8c, 0x2b, 0x52, 0x04, 0xcb, 0xe7, 0xd2, - 0x21, 0xe1, 0xa4, 0xbb, 0xb4, 0x77, 0x97, 0x45, 0x3c, 0x62, 0x05, 0xc9, 0x33, 0xe6, 0x7f, 0xeb, - 0xc6, 0x73, 0x8a, 0xa0, 0x8d, 0xe9, 0xc4, 0xd1, 0x7a, 0x9f, 0xcf, 0x8b, 0xc1, 0x8e, 0x38, 0xa0, - 0x08, 0x3c, 0xc6, 0x41, 0x0c, 0x25, 0x0e, 0xef, 0x48, 0xa4, 0x58, 0x36, 0x69, 0x93, 0x34, 0x0f, - 0x9a, 0x38, 0xe9, 0x67, 0xdf, 0x26, 0x99, 0x0d, 0x27, 0xcd, 0xed, 0x47, 0xc7, 0x77, 0x79, 0x34, - 0xd7, 0xc7, 0x48, 0x07, 0x49, 0xd8, 0x81, 0xbe, 0x6f, 0xf4, 0xbb, 0x7d, 0x51, 0xdc, 0xbb, 0x55, - 0x1b, 0xd8, 0x7f, 0x73, 0xc5, 0xb9, 0x5d, 0x4a, 0xbc, 0x0f, 0xd0, 0x0f, 0xf6, 0x90, 0xbb, 0xe2, - 0xa8, 0x91, 0x34, 0x97, 0xf5, 0xec, 0x9e, 0x26, 0xc1, 0xa3, 0x36, 0x64, 0xbc, 0x25, 0x1d, 0x0c, - 0xa5, 0xc5, 0x13, 0x8f, 0x7d, 0x81, 0x03, 0x1e, 0x97, 0x03, 0x42, 0x1f, 0xb3, 0x43, 0xa6, 0x32, - 0xeb, 0xd4, 0x93, 0xdb, 0xb6, 0x60, 0xa1, 0x54, 0xda, 0xd0, 0xae, 0x48, 0x22, 0xce, 0xb6, 0xd3, - 0x87, 0xd2, 0x42, 0x75, 0x03, 0x91, 0x56, 0xc7, 0xeb, 0x0c, 0x0f, 0xe0, 0x42, 0x5a, 0x02, 0xf5, - 0xf8, 0xd2, 0x4d, 0x4c, 0x45, 0x1f, 0x91, 0x8d, 0xdf, 0x19, 0xff, 0xb7, 0x91, 0xec, 0x26, 0xc1, - 0xa8, 0x29, 0xee, 0x05, 0xc6, 0x34, 0x10, 0xef, 0x78, 0x87, 0x8e, 0x4c, 0xff, 0x40, 0x16, 0x96, - 0xc9, 0x78, 0xf6, 0xc2, 0xef, 0x48, 0xd1, 0xc0, 0xe3, 0x5b, 0x2e, 0x3d, 0xc5, 0x3a, 0x41, 0xab, - 0xf4, 0x60, 0xf4, 0x9e, 0xa7, 0xa5, 0x08, 0xec, 0x61, 0xbf, 0x64, 0x57, 0xcd, 0x50, 0x97, 0x77, - 0x5a, 0xfc, 0xb6, 0xfe, 0x88, 0x80, 0x8c, 0xba, 0x31, 0x26, 0x72, 0x4c, 0x51, 0x7d, 0x84, 0xfb, - 0xba, 0x36, 0x34, 0x9d, 0x9e, 0xe0, 0x76, 0x01, 0xc6, 0x97, 0x96, 0x7f, 0x80, 0x42, 0xf8, 0x83, - 0xdc, 0xc8, 0xa5, 0x38, 0x67, 0x1a, 0xb1, 0x31, 0x1a, 0x96, 0xf9, 0x43, 0x74, 0x57, 0xfd, 0xa0, - 0x6a, 0x00, 0x70, 0x80, 0xef, 0x84, 0x89, 0x19, 0xaa, 0x20, 0xb1, 0x59, 0x3e, 0x23, 0xa2, 0x4b, - 0xee, 0xd4, 0x3e, 0xdb, 0x5c, 0xb0, 0x3c, 0x53, 0x46, 0x80, 0x01, 0x00, 0x00, + 0x3a, 0xeb, 0xf2, 0x68, 0x7f, 0x35, 0x78, 0xef, 0x56, 0x3e, 0x5a, 0xa3, 0x0c, 0x93, 0x6a, 0x5c, + 0xa0, 0x33, 0xab, 0xee, 0x34, 0x34, 0x48, 0x0f, 0x99, 0x6d, 0x19, 0x13, 0x4a, 0x75, 0x51, 0xaf, + 0x8c, 0x12, 0x8b, 0x3c, 0x55, 0x1a, 0x9a, 0x54, 0x62, 0xc5, 0x51, 0xfa, 0x65, 0xdf, 0xbc, 0x85, + 0x9d, 0x67, 0x9d, 0x73, 0xa2, 0x9d, 0xe2, 0xc6, 0xb4, 0x04, 0xd0, 0xe8, 0x76, 0xe3, 0x3a, 0xcf, + 0x2e, 0xb0, 0x35, 0x62, 0x05, 0x95, 0xc2, 0x6b, 0x94, 0x84, 0xa9, 0x20, 0x9f, 0xa5, 0x1d, 0xc1, + 0x65, 0xe7, 0x02, 0xd9, 0x82, 0xe9, 0xd5, 0x02, 0x6f, 0xd5, 0x3b, 0x51, 0x9b, 0xe5, 0xcc, 0x59, + 0x2f, 0xc9, 0xf0, 0x84, 0xd2, 0x15, 0x1d, 0xaf, 0xdb, 0xe6, 0x8a, 0x61, 0x95, 0x7d, 0x49, 0x1f, + 0x17, 0xf2, 0x4d, 0xfc, 0x2a, 0xcf, 0x57, 0x2b, 0x8a, 0x68, 0x1b, 0xd7, 0x98, 0x6c, 0x47, 0xb0, + 0x76, 0xd0, 0xd5, 0xb4, 0xf4, 0xbf, 0x26, 0x9c, 0xba, 0xd9, 0x23, 0x40, 0xe7, 0x47, 0x17, 0xb7, + 0x49, 0xa6, 0x1f, 0x90, 0x31, 0xa8, 0xea, 0x22, 0x53, 0x81, 0xe9, 0x9b, 0xae, 0xb9, 0x92, 0x8f, + 0x2c, 0x44, 0x64, 0x6c, 0x1c, 0x58, 0x90, 0x28, 0x6f, 0xdd, 0xb2, 0x32, 0x2f, 0x35, 0x01, 0xbe, + 0xda, 0xcb, 0x50, 0xfa, 0xd9, 0x0c, 0x47, 0x30, 0xaa, 0x80, 0x98, 0xe2, 0xb6, 0x03, 0x73, 0x94, + 0x2f, 0x5e, 0xfb, 0x2c, 0xe9, 0xf7, 0x9c, 0xff, 0x30, 0x9e, 0xa0, 0xfa, 0x54, 0xc1, 0xe6, 0xb7, + 0x66, 0x21, 0x3b, 0x5e, 0xc9, 0x60, 0xd9, 0x9e, 0xc1, 0xc4, 0xda, 0x6c, 0x54, 0xce, 0x27, 0x92, + 0xde, 0x1f, 0x4a, 0xc4, 0x53, 0xd8, 0x17, 0xca, 0xce, 0xaa, 0x3d, 0x4d, 0x70, 0xf2, 0xf0, 0xdb, + 0xd6, 0xe3, 0xa2, 0x63, 0x9b, 0x45, 0xaf, 0x8c, 0xb1, 0x4f, 0x6c, 0x4f, 0x5a, 0xde, 0xc2, 0x49, + 0xab, 0x4a, 0x83, 0x25, 0xa6, 0x97, 0x25, 0x0e, 0xe6, 0xd1, 0x2d, 0xd3, 0xce, 0xa5, 0xd2, 0x17, + 0x5d, 0x46, 0xc0, 0x0a, 0xe7, 0x5c, 0x10, 0x6f, 0xf2, 0xfe, 0x7f, 0x77, 0x2e, 0x4d, 0x64, 0xfa, + 0xf0, 0x1b, 0xab, 0x99, 0xde, 0x44, 0x36, 0x22, 0xe0, 0x5a, 0x45, 0x2e, 0xaa, 0x71, 0x46, 0xca, + 0x51, 0x09, 0x9a, 0x22, 0x72, 0x8f, 0xe0, 0xe3, 0xb9, 0x56, 0xe0, 0xa3, 0xf5, 0x6f, 0x7a, 0x00, + 0x1c, 0x2f, 0x9c, 0x48, 0x1b, 0x9d, 0xac, 0xd1, 0x5b, 0x33, 0x15, 0x13, 0x09, 0x8a, 0xc6, 0x30, + 0xd9, 0x7d, 0x5b, 0x74, 0x6b, 0x7b, 0x18, 0x13, 0x6f, 0x83, 0xd7, 0x93, 0xf2, 0x42, 0xe8, 0x9a, + 0xbf, 0x35, 0xb9, 0xf2, 0x55, 0x3a, 0x2f, 0x15, 0x8b, 0xf2, 0xee, 0x5c, 0x95, 0xcb, 0x92, 0x21, + 0xf5, 0x8d, 0xb5, 0xa9, 0x43, 0x0c, 0x75, 0xc7, 0x27, 0xe7, 0xc5, 0x84, 0x45, 0xf4, 0x0f, 0x04, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -10458,9 +10481,9 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_sig_storage #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 384, // uncompressed data size (bytes) - 397, // compressed data size (bytes) + 384, // compressed data size (bytes) kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_sig_data, // compressed data pointer - NV_TRUE, // is pData compressed? + NV_FALSE, // is pData compressed? NV_TRUE, // contain information for file overriding? NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) }, @@ -10473,38 +10496,37 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_sig_storage // FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_dbg_gfw_pub_key.bin // FILE TYPE: BINARY // VAR NAME: N/A -// COMPRESSION: YES +// COMPRESSION: NO // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 384 -// COMPRESSED SIZE (bytes): 397 +// COMPRESSED SIZE (bytes): N/A // static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_pkey_data[] = { - 0x01, 0x80, 0x01, 0x7f, 0xfe, 0xb1, 0xb2, 0x7a, 0x80, 0x2b, 0x7d, 0x7c, 0xc5, 0x65, 0x9b, 0x93, - 0x52, 0x4d, 0x36, 0x1d, 0xf9, 0x78, 0x50, 0xd6, 0x3f, 0x24, 0xad, 0x30, 0x50, 0x48, 0x5e, 0xe7, - 0x17, 0xea, 0xa5, 0x90, 0xd0, 0x16, 0xf8, 0xb2, 0xf2, 0x8e, 0x5c, 0x85, 0x38, 0x65, 0xab, 0xa7, - 0x28, 0x02, 0xef, 0x55, 0x9f, 0x32, 0x16, 0x19, 0x49, 0xc8, 0x71, 0x8e, 0x5f, 0x2d, 0xf7, 0x48, - 0x75, 0x47, 0xc1, 0x7f, 0xd7, 0x17, 0xb7, 0x8c, 0xbb, 0xad, 0xa7, 0xf2, 0x8b, 0xcb, 0x0f, 0xad, - 0xef, 0x3d, 0x09, 0x88, 0x47, 0x0f, 0x43, 0xdc, 0x6b, 0x0f, 0xc6, 0xac, 0x9e, 0x9e, 0x76, 0x09, - 0xa8, 0xbd, 0xc6, 0xe5, 0x9c, 0x20, 0xc2, 0x60, 0x3f, 0x10, 0xa8, 0xe1, 0x62, 0x91, 0x97, 0x4f, - 0x95, 0x52, 0x3a, 0xd3, 0xa8, 0xfe, 0x66, 0xe4, 0xe4, 0xef, 0xbb, 0xab, 0x20, 0xd8, 0x1b, 0xf2, - 0xc9, 0x04, 0x01, 0x1d, 0x39, 0xe6, 0x3c, 0x1a, 0xe4, 0xfd, 0xb6, 0xd1, 0x18, 0x81, 0x5e, 0x78, - 0xec, 0xee, 0x63, 0xd4, 0x91, 0x3a, 0x05, 0x2c, 0x36, 0x84, 0xbd, 0xb1, 0xfa, 0xb7, 0xf4, 0x5a, - 0xf6, 0xd0, 0x7f, 0x78, 0xe4, 0x16, 0x00, 0x2b, 0xc0, 0xac, 0x9e, 0x89, 0x50, 0x78, 0xbb, 0xe7, - 0x4d, 0x9d, 0xf4, 0xc9, 0xfe, 0xb7, 0x29, 0x65, 0x6f, 0x33, 0x91, 0x2c, 0x3a, 0x7d, 0x8e, 0xc5, - 0x84, 0xd6, 0x55, 0x3b, 0x79, 0x0c, 0xea, 0x93, 0x9f, 0x64, 0x49, 0x1a, 0xf5, 0x2c, 0xc8, 0x10, - 0x92, 0x90, 0xb1, 0xe3, 0x0e, 0xd0, 0xf4, 0xad, 0x11, 0x3b, 0x20, 0xb1, 0x2d, 0xc7, 0xa6, 0x6e, - 0xd3, 0x9c, 0x67, 0x49, 0x3e, 0xad, 0xea, 0x44, 0x09, 0x96, 0x96, 0xce, 0x1e, 0x7a, 0xcd, 0x40, - 0x30, 0xa2, 0xdb, 0xce, 0x60, 0x19, 0xd8, 0x8d, 0x96, 0x5e, 0x0c, 0x30, 0xcd, 0xe3, 0xcb, 0x02, - 0x3e, 0x2b, 0x26, 0x38, 0x2b, 0x2c, 0x09, 0xa6, 0xc8, 0xad, 0xbb, 0xde, 0x67, 0x33, 0xaf, 0x53, - 0x72, 0x7c, 0x77, 0xe2, 0xb8, 0xe2, 0xe0, 0x11, 0xb8, 0x26, 0xe7, 0x92, 0x29, 0x8b, 0xe1, 0xef, - 0x6a, 0x7e, 0x49, 0x09, 0x37, 0xde, 0x61, 0xc5, 0xeb, 0x11, 0x72, 0x47, 0x85, 0x2a, 0x66, 0x6c, - 0x5f, 0x02, 0xb5, 0x86, 0x82, 0x81, 0x56, 0x8e, 0x1c, 0xa4, 0xf8, 0xab, 0x7e, 0x1f, 0x9b, 0x84, - 0x5b, 0xdd, 0xc1, 0x7d, 0x62, 0xa1, 0xd2, 0x96, 0xc8, 0x1e, 0x2f, 0x32, 0xcd, 0x18, 0x0d, 0x6c, - 0x4a, 0x1c, 0xa0, 0x82, 0x74, 0x28, 0x15, 0xf9, 0xa1, 0x65, 0x52, 0x03, 0x8a, 0x7f, 0x0d, 0xff, - 0xd1, 0x15, 0x04, 0x99, 0x7d, 0xd8, 0xa3, 0x04, 0xe3, 0x22, 0x60, 0x40, 0x74, 0xf6, 0x08, 0x48, - 0x24, 0xe8, 0xbc, 0x54, 0x19, 0x3c, 0xc4, 0x38, 0xfc, 0xa9, 0x5e, 0x92, 0xa4, 0xae, 0x0a, 0x8a, - 0xef, 0xca, 0x63, 0x96, 0x9d, 0xf3, 0x87, 0x94, 0x2b, 0x80, 0x01, 0x00, 0x00, + 0xb1, 0xb2, 0x7a, 0x80, 0x2b, 0x7d, 0x7c, 0xc5, 0x65, 0x9b, 0x93, 0x52, 0x4d, 0x36, 0x1d, 0xf9, + 0x78, 0x50, 0xd6, 0x3f, 0x24, 0xad, 0x30, 0x50, 0x48, 0x5e, 0xe7, 0x17, 0xea, 0xa5, 0x90, 0xd0, + 0x16, 0xf8, 0xb2, 0xf2, 0x8e, 0x5c, 0x85, 0x38, 0x65, 0xab, 0xa7, 0x28, 0x02, 0xef, 0x55, 0x9f, + 0x32, 0x16, 0x19, 0x49, 0xc8, 0x71, 0x8e, 0x5f, 0x2d, 0xf7, 0x48, 0x75, 0x47, 0xc1, 0x7f, 0xd7, + 0x17, 0xb7, 0x8c, 0xbb, 0xad, 0xa7, 0xf2, 0x8b, 0xcb, 0x0f, 0xad, 0xef, 0x3d, 0x09, 0x88, 0x47, + 0x0f, 0x43, 0xdc, 0x6b, 0x0f, 0xc6, 0xac, 0x9e, 0x9e, 0x76, 0x09, 0xa8, 0xbd, 0xc6, 0xe5, 0x9c, + 0x20, 0xc2, 0x60, 0x3f, 0x10, 0xa8, 0xe1, 0x62, 0x91, 0x97, 0x4f, 0x95, 0x52, 0x3a, 0xd3, 0xa8, + 0xfe, 0x66, 0xe4, 0xe4, 0xef, 0xbb, 0xab, 0x20, 0xd8, 0x1b, 0xf2, 0xc9, 0x04, 0x01, 0x1d, 0x39, + 0xe6, 0x3c, 0x1a, 0xe4, 0xfd, 0xb6, 0xd1, 0x18, 0x81, 0x5e, 0x78, 0xec, 0xee, 0x63, 0xd4, 0x91, + 0x3a, 0x05, 0x2c, 0x36, 0x84, 0xbd, 0xb1, 0xfa, 0xb7, 0xf4, 0x5a, 0xf6, 0xd0, 0x7f, 0x78, 0xe4, + 0x16, 0x00, 0x2b, 0xc0, 0xac, 0x9e, 0x89, 0x50, 0x78, 0xbb, 0xe7, 0x4d, 0x9d, 0xf4, 0xc9, 0xfe, + 0xb7, 0x29, 0x65, 0x6f, 0x33, 0x91, 0x2c, 0x3a, 0x7d, 0x8e, 0xc5, 0x84, 0xd6, 0x55, 0x3b, 0x79, + 0x0c, 0xea, 0x93, 0x9f, 0x64, 0x49, 0x1a, 0xf5, 0x2c, 0xc8, 0x10, 0x92, 0x90, 0xb1, 0xe3, 0x0e, + 0xd0, 0xf4, 0xad, 0x11, 0x3b, 0x20, 0xb1, 0x2d, 0xc7, 0xa6, 0x6e, 0xd3, 0x9c, 0x67, 0x49, 0x3e, + 0xad, 0xea, 0x44, 0x09, 0x96, 0x96, 0xce, 0x1e, 0x7a, 0xcd, 0x40, 0x30, 0xa2, 0xdb, 0xce, 0x60, + 0x19, 0xd8, 0x8d, 0x96, 0x5e, 0x0c, 0x30, 0xcd, 0xe3, 0xcb, 0x02, 0x3e, 0x2b, 0x26, 0x38, 0x2b, + 0x2c, 0x09, 0xa6, 0xc8, 0xad, 0xbb, 0xde, 0x67, 0x33, 0xaf, 0x53, 0x72, 0x7c, 0x77, 0xe2, 0xb8, + 0xe2, 0xe0, 0x11, 0xb8, 0x26, 0xe7, 0x92, 0x29, 0x8b, 0xe1, 0xef, 0x6a, 0x7e, 0x49, 0x09, 0x37, + 0xde, 0x61, 0xc5, 0xeb, 0x11, 0x72, 0x47, 0x85, 0x2a, 0x66, 0x6c, 0x5f, 0x02, 0xb5, 0x86, 0x82, + 0x81, 0x56, 0x8e, 0x1c, 0xa4, 0xf8, 0xab, 0x7e, 0x1f, 0x9b, 0x84, 0x5b, 0xdd, 0xc1, 0x7d, 0x62, + 0xa1, 0xd2, 0x96, 0xc8, 0x1e, 0x2f, 0x32, 0xcd, 0x18, 0x0d, 0x6c, 0x4a, 0x1c, 0xa0, 0x82, 0x74, + 0x28, 0x15, 0xf9, 0xa1, 0x65, 0x52, 0x03, 0x8a, 0x7f, 0x0d, 0xff, 0xd1, 0x15, 0x04, 0x99, 0x7d, + 0xd8, 0xa3, 0x04, 0xe3, 0x22, 0x60, 0x40, 0x74, 0xf6, 0x08, 0x48, 0x24, 0xe8, 0xbc, 0x54, 0x19, + 0x3c, 0xc4, 0x38, 0xfc, 0xa9, 0x5e, 0x92, 0xa4, 0xae, 0x0a, 0x8a, 0xef, 0xca, 0x63, 0x96, 0x9d, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -10515,9 +10537,9 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_pkey_storag #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 384, // uncompressed data size (bytes) - 397, // compressed data size (bytes) + 384, // compressed data size (bytes) kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_pkey_data, // compressed data pointer - NV_TRUE, // is pData compressed? + NV_FALSE, // is pData compressed? NV_TRUE, // contain information for file overriding? NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) }, diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100.c index a0ec3651b5..188d0b52a6 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100.c @@ -32,10353 +32,10354 @@ // FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_prd_gfw_image.bin // FILE TYPE: BINARY // VAR NAME: N/A -// COMPRESSION: YES +// COMPRESSION: NO // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 165448 -// COMPRESSED SIZE (bytes): 165428 +// COMPRESSED SIZE (bytes): N/A // static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_image_data[] = { - 0x8c, 0x99, 0x53, 0x96, 0x28, 0x0a, 0x80, 0x24, 0xcb, 0xb6, 0x6d, 0xdb, 0xbc, 0x65, 0xdb, 0xb6, - 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x5d, 0x35, 0x6f, 0x66, 0x7a, 0x01, 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0x03, 0xe3, 0x42, 0x9f, 0x88, 0x13, 0x24, + 0x98, 0x70, 0x63, 0x9e, 0x64, 0xa5, 0x05, 0x9e, 0x97, 0x66, 0xab, 0x5b, 0x2f, 0x9d, 0xbe, 0xec, + 0x6a, 0x71, 0x50, 0x41, 0x54, 0x4c, 0x6a, 0x98, 0xc1, 0x6f, 0xf0, 0x46, 0x1a, 0x61, 0xe2, 0xc6, + 0x22, 0x9d, 0x24, 0x74, 0x43, 0xdc, 0xef, 0xb3, 0xbb, 0xc5, 0xc6, 0xa7, 0xc4, 0x7e, 0xca, 0xc7, + 0x09, 0xe4, 0x07, 0xdb, 0x3d, 0x5a, 0xd9, 0x32, 0x9c, 0x26, 0xd3, 0xb6, 0x4a, 0xd3, 0x80, 0xa2, + 0xa3, 0xf9, 0xf4, 0x77, 0xbd, 0x98, 0x4f, 0xd0, 0x3b, 0xfc, 0x1f, 0x7b, 0x1e, 0xfd, 0xa4, 0x56, + 0xe2, 0xb8, 0xb7, 0xf2, 0xdc, 0xe9, 0x05, 0x3c, 0x19, 0xea, 0xbb, 0x49, 0x57, 0x3d, 0xe5, 0x60, + 0x51, 0xc6, 0xd0, 0x7e, 0x1d, 0x44, 0xb2, 0x06, 0xc1, 0x85, 0x0c, 0xd2, 0x07, 0xe6, 0x45, 0x94, + 0xdc, 0xd4, 0x4c, 0x47, 0x5d, 0x76, 0x0f, 0xf7, 0xea, 0x13, 0x34, 0x33, 0x34, 0x9b, 0x4d, 0xad, + 0x8a, 0x69, 0xd2, 0x7e, 0x02, 0x60, 0x8e, 0x2b, 0xdb, 0x25, 0xea, 0x99, 0x9a, 0x87, 0x75, 0x39, + 0x5c, 0x6f, 0x12, 0xa5, 0x6c, 0xcd, 0xae, 0x29, 0x56, 0x4e, 0xab, 0x51, 0xf9, 0x0d, 0xf2, 0x83, + 0x5d, 0xfa, 0x6a, 0x14, 0xbc, 0xf9, 0x85, 0xab, 0xc6, 0x48, 0x71, 0x8b, 0xd9, 0x43, 0xd4, 0x5b, + 0x37, 0xe2, 0x93, 0x64, 0x5b, 0x03, 0x06, 0x5c, 0x0e, 0xaf, 0xca, 0x6a, 0x55, 0xdc, 0xd1, 0xab, + 0x9c, 0x5a, 0x28, 0xdb, 0x89, 0xbf, 0xef, 0x58, 0xb5, 0x6d, 0x1d, 0x25, 0x48, 0x70, 0x0a, 0x57, + 0xfd, 0xbe, 0x06, 0x2d, 0x45, 0x3d, 0x00, 0xc1, 0xba, 0xbe, 0x3c, 0x5f, 0x7c, 0x34, 0x98, 0xe8, + 0xd1, 0xf0, 0x28, 0x9b, 0x3f, 0x37, 0x66, 0x60, 0xce, 0x74, 0x8f, 0x31, 0x16, 0x6c, 0x82, 0x57, + 0x5c, 0xa8, 0xe3, 0x5d, 0x19, 0x77, 0xff, 0xd7, 0x17, 0x1a, 0x73, 0x38, 0xd9, 0x07, 0x9f, 0x49, + 0x83, 0x04, 0x16, 0x2d, 0xbc, 0xf9, 0x0f, 0x18, 0x17, 0xad, 0xfb, 0x76, 0x1d, 0xcd, 0x77, 0xeb, + 0xbc, 0xe5, 0xde, 0x1c, 0x42, 0x79, 0xa3, 0x16, 0xba, 0xc6, 0xa2, 0xad, 0x67, 0x4f, 0x00, 0x98, + 0x5f, 0xe0, 0xae, 0xc3, 0xa1, 0x5d, 0x2f, 0x1a, 0x95, 0xce, 0x87, 0xa2, 0x6b, 0xbb, 0x97, 0x03, + 0x66, 0xd8, 0xf6, 0x55, 0x1c, 0xde, 0xb9, 0x7f, 0x76, 0x06, 0xfa, 0x2d, 0xf8, 0x1a, 0x7d, 0xd4, + 0xf4, 0x29, 0x70, 0xad, 0xfd, 0x41, 0x32, 0x1d, 0xf0, 0x66, 0xbe, 0xf7, 0x06, 0xaf, 0x20, 0xe7, + 0xca, 0xc8, 0xf8, 0x01, 0xc0, 0xde, 0xbc, 0x31, 0xd7, 0xa5, 0x85, 0x34, 0x39, 0xc4, 0xb2, 0x1f, + 0x8e, 0x5f, 0x40, 0x95, 0xf4, 0xc4, 0xbe, 0xa4, 0x7c, 0xd0, 0x7b, 0x9c, 0x15, 0x82, 0x49, 0x00, + 0xdb, 0x2c, 0x00, 0xe4, 0x3b, 0xa1, 0x6d, 0xd2, 0x96, 0x43, 0x01, 0x97, 0x5b, 0x3b, 0x42, 0xe8, + 0x5a, 0x48, 0xf3, 0x9d, 0xb7, 0xd7, 0x12, 0x20, 0x32, 0xf9, 0x45, 0xc2, 0x21, 0x2f, 0xe6, 0x87, + 0xca, 0xae, 0x84, 0xcf, 0xd5, 0xe6, 0x85, 0xc1, 0x66, 0x52, 0x54, 0x99, 0x4d, 0x49, 0xb5, 0x38, + 0x46, 0xbe, 0x89, 0xac, 0x83, 0xb5, 0x25, 0xef, 0xd3, 0xfa, 0x2c, 0x41, 0x1d, 0x88, 0x71, 0x07, + 0xf9, 0x5d, 0x0e, 0x79, 0xc5, 0x05, 0xde, 0x7c, 0xdd, 0xa2, 0xcd, 0x88, 0xd3, 0xfe, 0x73, 0xd4, + 0x3a, 0x90, 0x2c, 0x83, 0x3a, 0x19, 0xd2, 0x12, 0x13, 0x24, 0x7b, 0x10, 0x87, 0x64, 0x73, 0xc5, + 0xde, 0x93, 0x17, 0xe2, 0x72, 0x6c, 0x77, 0x8b, 0x86, 0x0c, 0xca, 0x48, 0xb3, 0x32, 0xa7, 0x39, + 0xb1, 0xcf, 0xf6, 0x66, 0xb3, 0x26, 0xac, 0x4f, 0xfb, 0xb8, 0xa3, 0xb0, 0x1d, 0x65, 0x52, 0x83, + 0xcd, 0x9a, 0xf3, 0xe3, 0xed, 0x39, 0xf9, 0xdd, 0x3f, 0x1b, 0x60, 0xc6, 0x47, 0x12, 0x37, 0x33, + 0x4d, 0xae, 0x59, 0xf8, 0x3a, 0xb8, 0x9d, 0x51, 0x98, 0xff, 0x48, 0x23, 0xd5, 0x47, 0x8e, 0x30, + 0xfe, 0x7e, 0x95, 0x04, 0x19, 0x03, 0x00, 0x67, 0xc5, 0x76, 0x82, 0x29, 0xb5, 0x54, 0x60, 0xcb, + 0x3d, 0xc8, 0x6e, 0x3d, 0x02, 0x9f, 0x1f, 0xe6, 0x4f, 0x26, 0x22, 0xe7, 0xbe, 0x77, 0xa2, 0xf7, + 0x86, 0x76, 0x46, 0x80, 0x64, 0x1d, 0x31, 0xe4, 0xa3, 0x3f, 0xb9, 0xf7, 0x96, 0x2c, 0x65, 0xab, + 0xb7, 0x34, 0xb6, 0xd2, 0xf7, 0x75, 0x69, 0x42, 0x78, 0x60, 0x65, 0xe3, 0xf4, 0x9e, 0x19, 0x9c, + 0x0b, 0x88, 0x40, 0xfb, 0x9d, 0x8c, 0x26, 0x6c, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -10389,9 +10390,9 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_image_storag #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 165448, // uncompressed data size (bytes) - 165428, // compressed data size (bytes) + 165448, // compressed data size (bytes) kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_image_data, // compressed data pointer - NV_TRUE, // is pData compressed? + NV_FALSE, // is pData compressed? NV_TRUE, // contain information for file overriding? NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) }, @@ -10404,17 +10405,16 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_image_storag // FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_prd_gfw_hash.bin // FILE TYPE: BINARY // VAR NAME: N/A -// COMPRESSION: YES +// COMPRESSION: NO // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 48 -// COMPRESSED SIZE (bytes): 61 +// COMPRESSED SIZE (bytes): N/A // static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_hash_data[] = { - 0x01, 0x30, 0x00, 0xcf, 0xff, 0x80, 0x7e, 0xcb, 0x2f, 0x5b, 0x40, 0xe7, 0x0f, 0x5a, 0xc9, 0x1e, - 0x72, 0x3e, 0xa9, 0xbc, 0xb7, 0x12, 0x38, 0x94, 0x6e, 0xe4, 0x83, 0x87, 0x9f, 0xa2, 0x36, 0x4e, - 0x37, 0xd0, 0x5b, 0xdb, 0x48, 0x24, 0x75, 0x30, 0xf6, 0x38, 0xc5, 0xa1, 0x73, 0xf5, 0x52, 0xae, - 0xd5, 0x29, 0xe7, 0xb0, 0xce, 0xa7, 0x6b, 0x27, 0xe4, 0x30, 0x00, 0x00, 0x00, + 0x11, 0x06, 0xc0, 0x0f, 0x68, 0xd6, 0xf8, 0x5f, 0xc4, 0xdc, 0x3d, 0x53, 0x62, 0x76, 0x9a, 0xee, + 0x68, 0xe3, 0xb4, 0xf9, 0x53, 0x5f, 0x3a, 0xb9, 0xd0, 0xa9, 0x25, 0x40, 0x2e, 0x5f, 0xc8, 0x69, + 0x3d, 0x67, 0x43, 0x03, 0xf8, 0x4f, 0x23, 0xc7, 0x73, 0xbe, 0x53, 0x31, 0xfb, 0xed, 0x4f, 0x27, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -10425,9 +10425,9 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_hash_storage #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 48, // uncompressed data size (bytes) - 61, // compressed data size (bytes) + 48, // compressed data size (bytes) kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_hash_data, // compressed data pointer - NV_TRUE, // is pData compressed? + NV_FALSE, // is pData compressed? NV_TRUE, // contain information for file overriding? NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) }, @@ -10440,38 +10440,37 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_hash_storage // FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_prd_gfw_sig.bin // FILE TYPE: BINARY // VAR NAME: N/A -// COMPRESSION: YES +// COMPRESSION: NO // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 384 -// COMPRESSED SIZE (bytes): 397 +// COMPRESSED SIZE (bytes): N/A // static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_sig_data[] = { - 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x6a, 0xac, 0x8d, 0x4b, 0x4d, 0x33, 0x4e, 0x67, 0x18, 0x87, 0x74, - 0x52, 0xfe, 0x62, 0xa6, 0x16, 0x4d, 0x17, 0xf2, 0xbf, 0x4e, 0x4f, 0xdb, 0xec, 0x17, 0x18, 0x5e, - 0x20, 0xfb, 0xe2, 0x55, 0x55, 0x8f, 0xe5, 0x62, 0x70, 0x38, 0xfd, 0x8d, 0xbc, 0x18, 0x86, 0x86, - 0x21, 0x7e, 0x6e, 0xcf, 0x92, 0xc4, 0x69, 0x99, 0xda, 0x0b, 0x85, 0x3c, 0xf2, 0xaf, 0xca, 0xe5, - 0x86, 0x74, 0xb5, 0x2e, 0xe4, 0x3a, 0xe8, 0x68, 0x98, 0x04, 0x3f, 0x47, 0x57, 0x55, 0x88, 0xbc, - 0x6e, 0x3f, 0xda, 0x4d, 0x12, 0x05, 0x9c, 0x5f, 0x98, 0xde, 0x99, 0x87, 0xdd, 0x02, 0x49, 0x85, - 0xe6, 0x69, 0xf4, 0x4e, 0x7b, 0xaa, 0x44, 0x37, 0x9a, 0x18, 0xd2, 0x6c, 0xbe, 0xbe, 0x3d, 0xc3, - 0x4e, 0x5c, 0x33, 0x4d, 0x4e, 0xf6, 0x14, 0x1f, 0x0c, 0x2e, 0xbd, 0xb3, 0x69, 0x33, 0x8e, 0xb4, - 0x52, 0x7d, 0x10, 0x3b, 0x75, 0xf4, 0xaf, 0xc8, 0x0a, 0x19, 0x36, 0x31, 0xb9, 0xdc, 0xda, 0x98, - 0xa8, 0x88, 0xfc, 0x78, 0x13, 0xdf, 0xda, 0x2a, 0x7c, 0x84, 0xf2, 0xa6, 0xf9, 0xb1, 0x37, 0x61, - 0xa7, 0xc5, 0x80, 0x48, 0xc1, 0xfb, 0xff, 0x79, 0x7c, 0x2a, 0xeb, 0xcc, 0x6b, 0xba, 0x5b, 0xc4, - 0x27, 0x80, 0xe7, 0x90, 0x02, 0xba, 0x96, 0x69, 0x54, 0x3f, 0xfb, 0x39, 0xc8, 0x8b, 0x38, 0x4a, - 0x44, 0x9c, 0xfe, 0x70, 0xd8, 0xa0, 0xa8, 0xa1, 0xb4, 0x98, 0x28, 0x70, 0x75, 0x46, 0xae, 0xad, - 0x04, 0xc2, 0x47, 0x54, 0x39, 0x14, 0x44, 0xa5, 0x87, 0x5f, 0x3a, 0x6e, 0x8c, 0x0d, 0x2d, 0x2b, - 0xf2, 0x3d, 0x53, 0x4a, 0x38, 0xb8, 0xd2, 0x9f, 0x42, 0x52, 0xbe, 0x9a, 0x07, 0x79, 0x93, 0xfe, - 0xd3, 0x27, 0x4c, 0x2a, 0x4a, 0x46, 0xa3, 0xa8, 0x76, 0x66, 0x99, 0x94, 0x47, 0xdb, 0x5f, 0x0d, - 0xb0, 0x74, 0x67, 0x79, 0x08, 0xe3, 0x91, 0xf1, 0x68, 0x3c, 0x1e, 0x12, 0x35, 0x43, 0xbb, 0x02, - 0x9f, 0xe4, 0xbf, 0xbb, 0x0b, 0x22, 0x48, 0x06, 0xe6, 0xe9, 0xbe, 0x74, 0x99, 0xab, 0xb8, 0xd9, - 0x8c, 0x47, 0xf5, 0xcd, 0x4e, 0x2b, 0xcb, 0x5d, 0x73, 0xb1, 0x10, 0x53, 0x8b, 0xaa, 0x43, 0xa1, - 0x51, 0xa6, 0x9b, 0xab, 0x1d, 0xda, 0xc7, 0x01, 0x77, 0xce, 0xb7, 0x17, 0xc1, 0x09, 0xe7, 0xac, - 0xc2, 0x67, 0x4a, 0xf4, 0x64, 0x0b, 0xff, 0x3b, 0x4d, 0x56, 0x04, 0xeb, 0xe4, 0xdd, 0xd1, 0x18, - 0x38, 0x49, 0x97, 0x74, 0x00, 0xaf, 0x64, 0x99, 0xac, 0x99, 0xd1, 0xbd, 0xbb, 0x8f, 0xe2, 0xba, - 0xd5, 0x3d, 0x33, 0xd7, 0x50, 0xa5, 0x73, 0x50, 0xab, 0x6b, 0x19, 0xd5, 0xe1, 0x3e, 0xc2, 0x8d, - 0x1c, 0xf7, 0x17, 0x11, 0xf5, 0x33, 0x35, 0x2d, 0x3a, 0x78, 0x18, 0x8c, 0xa8, 0xe2, 0x0c, 0x69, - 0x41, 0x23, 0x74, 0xa9, 0x3e, 0x2b, 0xfb, 0xf2, 0xb6, 0x80, 0x01, 0x00, 0x00, + 0x5a, 0x1a, 0x0a, 0xc7, 0x55, 0x52, 0x15, 0x22, 0xa1, 0xe9, 0xf9, 0xc7, 0x95, 0xd2, 0xb0, 0x19, + 0xaa, 0x73, 0x57, 0xe3, 0xc3, 0x13, 0x79, 0x1f, 0x5d, 0x37, 0x9f, 0x97, 0x4d, 0x85, 0x8f, 0x4b, + 0x29, 0x4c, 0x86, 0x37, 0xa2, 0x1c, 0x05, 0x98, 0x6d, 0xf8, 0x70, 0x1a, 0x0a, 0x9a, 0xc1, 0xd2, + 0x17, 0xba, 0x51, 0x99, 0x1f, 0xd8, 0x26, 0x93, 0xb6, 0x87, 0x65, 0x10, 0x7b, 0xc6, 0xc1, 0x79, + 0x37, 0x1c, 0xa4, 0x57, 0xa8, 0x06, 0xb9, 0x3f, 0xbd, 0xa9, 0xbf, 0xc6, 0xd0, 0xf2, 0xa2, 0xbf, + 0x4a, 0xb2, 0x7b, 0xfc, 0x78, 0x89, 0x20, 0x9d, 0x1e, 0xf6, 0xdf, 0x5d, 0x66, 0x12, 0x16, 0xdb, + 0x41, 0x71, 0xe0, 0x9c, 0xd4, 0xd7, 0xf1, 0x24, 0xfd, 0xbb, 0x4f, 0x39, 0x75, 0x34, 0x4e, 0x52, + 0x44, 0x5b, 0xa8, 0xa6, 0x53, 0x0b, 0x64, 0x35, 0x0a, 0xbf, 0x3c, 0xd3, 0xdf, 0x02, 0x48, 0xfa, + 0xf4, 0xae, 0x4d, 0xee, 0x50, 0xc8, 0x4a, 0x0e, 0x84, 0x63, 0x8d, 0xd8, 0x53, 0x5d, 0x64, 0x9f, + 0x3a, 0x29, 0xe9, 0x8e, 0xdc, 0xfa, 0xc2, 0x54, 0xb5, 0x67, 0xef, 0x21, 0x5d, 0xcf, 0xf9, 0x29, + 0xae, 0x9d, 0x6d, 0x92, 0xb1, 0x7d, 0x47, 0x4e, 0xe2, 0xe1, 0x5c, 0x13, 0x95, 0x4a, 0x8d, 0x41, + 0x02, 0xb4, 0xce, 0x26, 0x30, 0x95, 0x92, 0x58, 0x83, 0xff, 0x5a, 0x05, 0x88, 0x25, 0x5b, 0xc6, + 0xca, 0x26, 0xdc, 0x9b, 0x3b, 0xf7, 0x0c, 0x74, 0xd4, 0xc0, 0x8d, 0xcd, 0x33, 0xb8, 0xd0, 0x7a, + 0x3b, 0xa2, 0x3b, 0xe7, 0x72, 0xe8, 0x38, 0x42, 0x3d, 0x88, 0xa1, 0x10, 0x01, 0xae, 0xb1, 0xa0, + 0xb6, 0x86, 0x16, 0xe9, 0x35, 0xee, 0x30, 0x3d, 0x83, 0xbe, 0x1b, 0x4f, 0xae, 0xba, 0xa2, 0x82, + 0x7e, 0x85, 0xe9, 0x18, 0xe6, 0xa8, 0x43, 0xda, 0xbe, 0x56, 0x72, 0x81, 0x8c, 0x7d, 0xe5, 0xf2, + 0xf0, 0x9f, 0xdc, 0x87, 0xc5, 0x38, 0x38, 0x52, 0x9d, 0x22, 0x2d, 0x65, 0x4f, 0xee, 0xab, 0x22, + 0x96, 0xcc, 0xe8, 0xe7, 0xb7, 0xf0, 0xe9, 0x5d, 0x19, 0x62, 0x9f, 0x06, 0xbb, 0xa5, 0xcd, 0x91, + 0x8e, 0xbe, 0x04, 0x83, 0x5b, 0x85, 0x66, 0x98, 0x71, 0xed, 0xf9, 0x25, 0x5e, 0xd4, 0x5c, 0xd6, + 0x0b, 0x78, 0x40, 0x30, 0xad, 0x29, 0x0d, 0x8d, 0xb0, 0x5b, 0xf8, 0xe8, 0xb8, 0xb8, 0xdd, 0xc3, + 0xb3, 0x6c, 0xfb, 0x0d, 0xd0, 0x5f, 0x05, 0x09, 0xdf, 0x06, 0x81, 0x33, 0x61, 0xce, 0x01, 0x39, + 0x86, 0xa1, 0x1e, 0xca, 0x4b, 0x98, 0x88, 0x8d, 0xd5, 0xb5, 0x1d, 0xcd, 0x67, 0x99, 0xa1, 0x22, + 0x72, 0xd2, 0x0b, 0xed, 0x8e, 0x39, 0x09, 0x7a, 0xa6, 0x92, 0xe2, 0xf1, 0xe9, 0x0f, 0x99, 0xe0, + 0xb8, 0x93, 0x35, 0x5d, 0x98, 0x2d, 0x06, 0xa0, 0x44, 0x6b, 0xfd, 0xb4, 0x6a, 0xcc, 0x42, 0xd9, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -10482,9 +10481,9 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_sig_storage_ #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 384, // uncompressed data size (bytes) - 397, // compressed data size (bytes) + 384, // compressed data size (bytes) kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_sig_data, // compressed data pointer - NV_TRUE, // is pData compressed? + NV_FALSE, // is pData compressed? NV_TRUE, // contain information for file overriding? NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) }, @@ -10497,38 +10496,37 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_sig_storage_ // FILE NAME: kernel/inc/gspcc/bin/g_gsp_gh100_dyn_prd_gfw_pub_key.bin // FILE TYPE: BINARY // VAR NAME: N/A -// COMPRESSION: YES +// COMPRESSION: NO // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 384 -// COMPRESSED SIZE (bytes): 397 +// COMPRESSED SIZE (bytes): N/A // static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_pkey_data[] = { - 0x01, 0x80, 0x01, 0x7f, 0xfe, 0xb6, 0x61, 0x74, 0x8c, 0x50, 0xfd, 0x5d, 0x6b, 0xbc, 0x71, 0xe9, - 0xcf, 0x5e, 0xf6, 0x8b, 0x5d, 0xd5, 0x36, 0xe8, 0xaf, 0xca, 0x7a, 0x14, 0x6a, 0x3d, 0x1f, 0xa6, - 0x8b, 0x37, 0xf9, 0x3e, 0x5a, 0x44, 0xec, 0xb6, 0x6a, 0x39, 0x25, 0x78, 0xce, 0xd6, 0xf0, 0xe2, - 0xa1, 0x40, 0xae, 0x82, 0x22, 0x60, 0xaa, 0xf3, 0x6a, 0xd3, 0x4d, 0xe6, 0xc1, 0x38, 0x18, 0x4e, - 0xfc, 0xd6, 0x6c, 0x61, 0x38, 0x73, 0x13, 0x26, 0x71, 0xa8, 0xb8, 0x9c, 0xeb, 0x07, 0x28, 0x4e, - 0x86, 0x2b, 0xe2, 0x5e, 0xf8, 0xfd, 0x2c, 0x01, 0x51, 0x6f, 0x1c, 0xf9, 0x47, 0x36, 0x62, 0xcc, - 0x59, 0x24, 0x67, 0xf8, 0x5d, 0x13, 0x39, 0x52, 0xd9, 0x0b, 0xbf, 0x92, 0x98, 0xad, 0x98, 0x2b, - 0x53, 0x4d, 0x35, 0xda, 0x06, 0x7e, 0x89, 0x07, 0x2f, 0xb0, 0x0f, 0x12, 0x44, 0x1d, 0xe8, 0xa8, - 0xed, 0x40, 0x9c, 0x84, 0x8a, 0x99, 0x7e, 0x09, 0x05, 0xee, 0x9c, 0x62, 0x2a, 0x6e, 0xdb, 0xe3, - 0xc2, 0x7c, 0x39, 0x7c, 0xdb, 0x30, 0x49, 0x26, 0x58, 0xf1, 0x94, 0xa6, 0xd1, 0x8b, 0xda, 0x79, - 0x18, 0xed, 0x12, 0xdf, 0x72, 0xfd, 0x5b, 0x3d, 0x13, 0xab, 0xcc, 0xce, 0x20, 0x80, 0xd8, 0xe7, - 0x5d, 0x6c, 0xcf, 0x3e, 0x3a, 0x7c, 0x29, 0xda, 0xf4, 0xdb, 0x7a, 0xc0, 0x2a, 0x4d, 0xc7, 0xdc, - 0xe8, 0x09, 0xe6, 0x2a, 0xca, 0x6c, 0x33, 0xed, 0xf1, 0x96, 0xe5, 0x26, 0xb0, 0xc6, 0xcc, 0x22, - 0x15, 0xd2, 0x42, 0x47, 0x71, 0xe5, 0x6d, 0x2e, 0xda, 0xcd, 0x1d, 0x28, 0x59, 0xe9, 0x4d, 0x48, - 0xca, 0x36, 0xd4, 0x85, 0x6a, 0x26, 0x8e, 0x3e, 0xc7, 0xd7, 0x14, 0x77, 0x5e, 0x54, 0xda, 0x98, - 0xf8, 0x65, 0xaf, 0xea, 0x63, 0x46, 0xcd, 0xca, 0xd0, 0xbf, 0x9e, 0x31, 0xb2, 0x24, 0x7f, 0x4e, - 0xe5, 0xa3, 0x32, 0x5e, 0x22, 0x3a, 0xed, 0xed, 0xbe, 0xad, 0x5e, 0xa2, 0x36, 0x07, 0x41, 0x7f, - 0x94, 0x7b, 0x6f, 0x77, 0xea, 0xf6, 0xf3, 0x4e, 0xd3, 0x47, 0x39, 0x9c, 0xd0, 0x96, 0x70, 0x78, - 0x0c, 0x30, 0x9a, 0xa7, 0xe7, 0x85, 0x7e, 0xa6, 0xce, 0x00, 0x86, 0xfb, 0x91, 0xef, 0xe3, 0x31, - 0x1f, 0xc1, 0x5e, 0xda, 0xf3, 0x59, 0xdd, 0x36, 0xfe, 0x19, 0x2b, 0xca, 0xa4, 0x46, 0x5a, 0x52, - 0xaa, 0x65, 0x31, 0x00, 0x0b, 0x61, 0x57, 0x30, 0x8b, 0x0d, 0x13, 0xe6, 0xdc, 0xb3, 0x64, 0x61, - 0x98, 0x07, 0x52, 0xbc, 0x3e, 0x05, 0x26, 0x84, 0x96, 0xd0, 0x85, 0x62, 0x72, 0xd3, 0x9f, 0x60, - 0xf9, 0xc1, 0x33, 0x69, 0x1b, 0x49, 0x3e, 0x74, 0x08, 0x51, 0x2e, 0x97, 0x1b, 0x45, 0x54, 0x7c, - 0x4b, 0xd1, 0x51, 0x83, 0xaa, 0xf0, 0x9b, 0xff, 0x0c, 0xfb, 0x2f, 0x33, 0xcd, 0xe5, 0x1b, 0xcf, - 0x4f, 0x02, 0x0d, 0xf6, 0x1b, 0xdb, 0x48, 0x80, 0x58, 0x80, 0x01, 0x00, 0x00, + 0xb6, 0x61, 0x74, 0x8c, 0x50, 0xfd, 0x5d, 0x6b, 0xbc, 0x71, 0xe9, 0xcf, 0x5e, 0xf6, 0x8b, 0x5d, + 0xd5, 0x36, 0xe8, 0xaf, 0xca, 0x7a, 0x14, 0x6a, 0x3d, 0x1f, 0xa6, 0x8b, 0x37, 0xf9, 0x3e, 0x5a, + 0x44, 0xec, 0xb6, 0x6a, 0x39, 0x25, 0x78, 0xce, 0xd6, 0xf0, 0xe2, 0xa1, 0x40, 0xae, 0x82, 0x22, + 0x60, 0xaa, 0xf3, 0x6a, 0xd3, 0x4d, 0xe6, 0xc1, 0x38, 0x18, 0x4e, 0xfc, 0xd6, 0x6c, 0x61, 0x38, + 0x73, 0x13, 0x26, 0x71, 0xa8, 0xb8, 0x9c, 0xeb, 0x07, 0x28, 0x4e, 0x86, 0x2b, 0xe2, 0x5e, 0xf8, + 0xfd, 0x2c, 0x01, 0x51, 0x6f, 0x1c, 0xf9, 0x47, 0x36, 0x62, 0xcc, 0x59, 0x24, 0x67, 0xf8, 0x5d, + 0x13, 0x39, 0x52, 0xd9, 0x0b, 0xbf, 0x92, 0x98, 0xad, 0x98, 0x2b, 0x53, 0x4d, 0x35, 0xda, 0x06, + 0x7e, 0x89, 0x07, 0x2f, 0xb0, 0x0f, 0x12, 0x44, 0x1d, 0xe8, 0xa8, 0xed, 0x40, 0x9c, 0x84, 0x8a, + 0x99, 0x7e, 0x09, 0x05, 0xee, 0x9c, 0x62, 0x2a, 0x6e, 0xdb, 0xe3, 0xc2, 0x7c, 0x39, 0x7c, 0xdb, + 0x30, 0x49, 0x26, 0x58, 0xf1, 0x94, 0xa6, 0xd1, 0x8b, 0xda, 0x79, 0x18, 0xed, 0x12, 0xdf, 0x72, + 0xfd, 0x5b, 0x3d, 0x13, 0xab, 0xcc, 0xce, 0x20, 0x80, 0xd8, 0xe7, 0x5d, 0x6c, 0xcf, 0x3e, 0x3a, + 0x7c, 0x29, 0xda, 0xf4, 0xdb, 0x7a, 0xc0, 0x2a, 0x4d, 0xc7, 0xdc, 0xe8, 0x09, 0xe6, 0x2a, 0xca, + 0x6c, 0x33, 0xed, 0xf1, 0x96, 0xe5, 0x26, 0xb0, 0xc6, 0xcc, 0x22, 0x15, 0xd2, 0x42, 0x47, 0x71, + 0xe5, 0x6d, 0x2e, 0xda, 0xcd, 0x1d, 0x28, 0x59, 0xe9, 0x4d, 0x48, 0xca, 0x36, 0xd4, 0x85, 0x6a, + 0x26, 0x8e, 0x3e, 0xc7, 0xd7, 0x14, 0x77, 0x5e, 0x54, 0xda, 0x98, 0xf8, 0x65, 0xaf, 0xea, 0x63, + 0x46, 0xcd, 0xca, 0xd0, 0xbf, 0x9e, 0x31, 0xb2, 0x24, 0x7f, 0x4e, 0xe5, 0xa3, 0x32, 0x5e, 0x22, + 0x3a, 0xed, 0xed, 0xbe, 0xad, 0x5e, 0xa2, 0x36, 0x07, 0x41, 0x7f, 0x94, 0x7b, 0x6f, 0x77, 0xea, + 0xf6, 0xf3, 0x4e, 0xd3, 0x47, 0x39, 0x9c, 0xd0, 0x96, 0x70, 0x78, 0x0c, 0x30, 0x9a, 0xa7, 0xe7, + 0x85, 0x7e, 0xa6, 0xce, 0x00, 0x86, 0xfb, 0x91, 0xef, 0xe3, 0x31, 0x1f, 0xc1, 0x5e, 0xda, 0xf3, + 0x59, 0xdd, 0x36, 0xfe, 0x19, 0x2b, 0xca, 0xa4, 0x46, 0x5a, 0x52, 0xaa, 0x65, 0x31, 0x00, 0x0b, + 0x61, 0x57, 0x30, 0x8b, 0x0d, 0x13, 0xe6, 0xdc, 0xb3, 0x64, 0x61, 0x98, 0x07, 0x52, 0xbc, 0x3e, + 0x05, 0x26, 0x84, 0x96, 0xd0, 0x85, 0x62, 0x72, 0xd3, 0x9f, 0x60, 0xf9, 0xc1, 0x33, 0x69, 0x1b, + 0x49, 0x3e, 0x74, 0x08, 0x51, 0x2e, 0x97, 0x1b, 0x45, 0x54, 0x7c, 0x4b, 0xd1, 0x51, 0x83, 0xaa, + 0xf0, 0x9b, 0xff, 0x0c, 0xfb, 0x2f, 0x33, 0xcd, 0xe5, 0x1b, 0xcf, 0x4f, 0x02, 0x0d, 0xf6, 0x1b, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -10539,9 +10537,9 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_pkey_storage #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 384, // uncompressed data size (bytes) - 397, // compressed data size (bytes) + 384, // compressed data size (bytes) kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_pkey_data, // compressed data pointer - NV_TRUE, // is pData compressed? + NV_FALSE, // is pData compressed? NV_TRUE, // contain information for file overriding? NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) }, diff --git a/src/nvidia/generated/g_bindata_ksec2GetBinArchiveSecurescrubUcode_AD10X.c b/src/nvidia/generated/g_bindata_ksec2GetBinArchiveSecurescrubUcode_AD10X.c index a4b89a8c26..567195e016 100644 --- a/src/nvidia/generated/g_bindata_ksec2GetBinArchiveSecurescrubUcode_AD10X.c +++ b/src/nvidia/generated/g_bindata_ksec2GetBinArchiveSecurescrubUcode_AD10X.c @@ -946,62 +946,61 @@ BINDATA_STORAGE_PVT ksec2BinArchiveSecurescrubUcode_AD10X_header_prod_storage_pv // FILE NAME: kernel/inc/securescrub/bin/ad10x/g_securescrubuc_sec2_ad10x_boot_from_hs_ad10x_rsa3k_0_sig.h // FILE TYPE: TEXT // VAR NAME: securescrub_sig_dbg_ad10x -// COMPRESSION: YES +// COMPRESSION: NO // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 768 -// COMPRESSED SIZE (bytes): 781 +// COMPRESSED SIZE (bytes): N/A // static BINDATA_CONST NvU8 ksec2BinArchiveSecurescrubUcode_AD10X_sig_dbg_data[] = { - 0x01, 0x00, 0x03, 0xff, 0xfc, 0xd0, 0x17, 0xc0, 0x36, 0x32, 0xbc, 0x2a, 0xbc, 0x68, 0x11, 0xa0, - 0x27, 0x05, 0x9d, 0x73, 0xff, 0x55, 0xe0, 0x63, 0x92, 0x06, 0x82, 0xbd, 0xfd, 0xc3, 0xf5, 0xcf, - 0x46, 0xa8, 0xbc, 0x9f, 0xec, 0x0c, 0x78, 0x57, 0x79, 0xbf, 0x79, 0x07, 0xa3, 0x8b, 0x27, 0x33, - 0x8c, 0x71, 0x98, 0x44, 0x42, 0x9b, 0x1b, 0xae, 0x39, 0xf4, 0x18, 0xbd, 0x9b, 0xc3, 0xb0, 0xca, - 0x44, 0x22, 0xb8, 0x5a, 0x50, 0x18, 0x27, 0x0d, 0x09, 0x44, 0xc1, 0x6d, 0xfd, 0x35, 0x11, 0xfe, - 0x9f, 0xe8, 0x98, 0x37, 0xb5, 0xb6, 0xca, 0x4c, 0xf5, 0x64, 0x05, 0x24, 0x3f, 0x7c, 0xaf, 0x4a, - 0x25, 0x11, 0x3d, 0x03, 0xda, 0x0b, 0x74, 0xef, 0x37, 0xe9, 0xf9, 0x73, 0xaa, 0xe4, 0x1f, 0xa9, - 0xf5, 0x19, 0x8b, 0x29, 0xb9, 0x38, 0x15, 0x7a, 0xac, 0xe5, 0xe1, 0x58, 0x46, 0x19, 0xfb, 0x9b, - 0xaf, 0xfc, 0x4a, 0x0b, 0x7e, 0x31, 0xf2, 0xc6, 0x19, 0x38, 0x7f, 0xfa, 0x54, 0x7e, 0xc0, 0x79, - 0x8f, 0xcb, 0x72, 0x22, 0x7c, 0x99, 0x49, 0xcc, 0x43, 0xb4, 0x4f, 0x74, 0x77, 0x2a, 0x4e, 0x9c, - 0x3d, 0x4b, 0x88, 0x38, 0xb5, 0x3f, 0x8a, 0xba, 0xf7, 0x53, 0xdf, 0x77, 0x8e, 0xbc, 0xb3, 0x34, - 0x53, 0x24, 0xb1, 0x53, 0x73, 0xf7, 0xb1, 0xd9, 0x8d, 0x52, 0x75, 0xcc, 0xd6, 0xf6, 0xf8, 0x34, - 0x87, 0xaa, 0xf5, 0x0c, 0x29, 0x39, 0xea, 0x95, 0x18, 0x31, 0x4d, 0xcc, 0x7e, 0x12, 0x24, 0xed, - 0x05, 0x3f, 0x98, 0x62, 0x08, 0x03, 0xa8, 0xd3, 0x85, 0x70, 0xbe, 0x8f, 0xcb, 0x0a, 0xa4, 0x28, - 0xed, 0x71, 0x37, 0xb3, 0xf1, 0xe3, 0x18, 0x73, 0xaf, 0x71, 0xb5, 0xbb, 0x4b, 0x35, 0xb4, 0x19, - 0xdb, 0x1b, 0x72, 0x0a, 0x7e, 0xeb, 0x3b, 0x09, 0xc9, 0x08, 0x2b, 0xef, 0x30, 0x6c, 0xda, 0x08, - 0x24, 0xfa, 0x9c, 0x42, 0x09, 0xbd, 0xf7, 0xc5, 0xfc, 0x89, 0x86, 0xdd, 0x18, 0xa5, 0x43, 0x88, - 0xa6, 0xba, 0x43, 0x07, 0xd4, 0xb7, 0xdb, 0x69, 0xb6, 0xf6, 0xaa, 0x4c, 0x54, 0x17, 0x44, 0xa6, - 0x48, 0xa2, 0x69, 0xbc, 0x8f, 0x6d, 0x3c, 0x43, 0x1c, 0xc3, 0x8c, 0xc0, 0xcb, 0xa4, 0x5e, 0xd5, - 0xd4, 0x6f, 0xd9, 0xdc, 0x77, 0xe7, 0xa2, 0x74, 0xd0, 0xfd, 0x78, 0x1c, 0xff, 0x80, 0x1d, 0x6d, - 0x68, 0x5f, 0x21, 0xb7, 0x0a, 0xaa, 0x77, 0xe2, 0xd8, 0xdf, 0x0d, 0xd6, 0xf3, 0x76, 0x13, 0x9b, - 0x8a, 0xa9, 0x67, 0x18, 0x2d, 0x4e, 0xac, 0xcc, 0x5d, 0xab, 0x6e, 0xa0, 0xdd, 0x95, 0xce, 0xf3, - 0x07, 0x90, 0xc9, 0x21, 0x5b, 0x1c, 0x2d, 0xc2, 0x3c, 0xe6, 0x22, 0x18, 0x24, 0x65, 0xcb, 0x36, - 0xf7, 0xab, 0x2f, 0x84, 0x30, 0x02, 0x61, 0x4b, 0xd5, 0xfb, 0x14, 0x3f, 0xbc, 0x1a, 0xd7, 0x7b, - 0x49, 0x62, 0x26, 0xb4, 0x53, 0x3a, 0x8f, 0xa9, 0xc8, 0xd9, 0xde, 0xe2, 0x00, 0x25, 0x91, 0x4f, - 0x66, 0x68, 0x92, 0x0b, 0x63, 0x39, 0xb4, 0x72, 0xbf, 0x0b, 0xca, 0x70, 0x16, 0x1d, 0xa5, 0x3e, - 0x6d, 0x7c, 0xd4, 0xc4, 0x65, 0x87, 0x09, 0x1e, 0x3d, 0xb1, 0x62, 0x5e, 0x23, 0xa5, 0xb0, 0x94, - 0xb0, 0x89, 0x60, 0x0a, 0xa3, 0xea, 0xfb, 0x83, 0x64, 0xb3, 0x77, 0x23, 0x29, 0x41, 0xe1, 0xdf, - 0x72, 0x34, 0x26, 0x3c, 0x9c, 0x41, 0xb2, 0x50, 0x3a, 0x5e, 0x23, 0xe9, 0x1e, 0x37, 0xe9, 0x72, - 0xa7, 0x09, 0x69, 0xd4, 0x37, 0x17, 0x88, 0xab, 0x32, 0xef, 0x55, 0x66, 0x77, 0x3a, 0xbe, 0x2a, - 0x47, 0xdf, 0xee, 0x72, 0x27, 0x91, 0xe5, 0xc9, 0xe3, 0xf7, 0x11, 0x9a, 0xd4, 0x9e, 0x8c, 0x3c, - 0x60, 0x42, 0xf4, 0x4e, 0x97, 0x49, 0xd6, 0xbf, 0x20, 0x5d, 0xea, 0x2f, 0xcb, 0x2f, 0xfe, 0xa7, - 0x89, 0xce, 0xe4, 0x72, 0x7c, 0xbd, 0x57, 0xf1, 0xbc, 0x38, 0xe6, 0x96, 0xa8, 0x85, 0xb9, 0x35, - 0x4b, 0xbd, 0x30, 0xa1, 0x3d, 0xdb, 0x86, 0xb0, 0xee, 0x7c, 0xf4, 0x3f, 0xbf, 0xf2, 0x4b, 0x1c, - 0xa1, 0x96, 0xd5, 0xf7, 0x52, 0x8f, 0xe5, 0x07, 0xb9, 0xdb, 0xde, 0x13, 0x51, 0x61, 0x60, 0x3c, - 0x5b, 0x7b, 0x27, 0xa0, 0x7c, 0x7a, 0x9d, 0xc4, 0xc2, 0xd0, 0xfb, 0x3c, 0x3b, 0x45, 0x1c, 0x6f, - 0xb7, 0x9a, 0x5a, 0x54, 0xb3, 0x47, 0x38, 0x14, 0xaa, 0x30, 0x67, 0x10, 0x75, 0x96, 0xf9, 0x22, - 0x0a, 0x09, 0x7b, 0x25, 0x48, 0x68, 0x75, 0x8b, 0xfe, 0x35, 0x6b, 0xee, 0x57, 0x68, 0x08, 0x4f, - 0x86, 0xeb, 0x39, 0x03, 0xde, 0x6e, 0x3f, 0x1b, 0xe3, 0x3c, 0x9a, 0x13, 0x84, 0xe5, 0x6b, 0x0c, - 0x3d, 0xd6, 0xd3, 0xaa, 0x03, 0xce, 0xcb, 0xb9, 0x83, 0xf9, 0x6b, 0xfb, 0x87, 0x30, 0xb4, 0xff, - 0xec, 0x60, 0xb2, 0xf6, 0xaf, 0x9e, 0xc1, 0x39, 0x85, 0xad, 0x2d, 0xdc, 0x67, 0x00, 0x2c, 0x27, - 0xe7, 0x33, 0xd3, 0x31, 0xd5, 0x98, 0xec, 0xb0, 0x7e, 0xb9, 0x0d, 0xb6, 0x78, 0x02, 0xf2, 0x7a, - 0xe7, 0x6a, 0x6e, 0x78, 0x38, 0x47, 0x85, 0xca, 0x95, 0x6a, 0xa4, 0x2b, 0xdb, 0xee, 0xe3, 0x69, - 0x5f, 0x49, 0x07, 0x1b, 0x05, 0xfa, 0x95, 0xaa, 0xb8, 0xd3, 0xa3, 0x58, 0x0b, 0x29, 0x3c, 0x2c, - 0x86, 0xc7, 0x3a, 0xbb, 0xe6, 0xbf, 0x1b, 0x9a, 0xed, 0x32, 0x6d, 0x5c, 0x94, 0xe3, 0x3f, 0x70, - 0x28, 0x0f, 0x99, 0xb8, 0x78, 0x9a, 0x53, 0xab, 0x0f, 0x2e, 0x96, 0x3f, 0x38, 0x7c, 0xca, 0xfb, - 0x18, 0x53, 0xf0, 0xa2, 0xcf, 0x6e, 0x60, 0xbf, 0xda, 0x23, 0xe5, 0xa8, 0xf2, 0xc4, 0x73, 0x20, - 0xe7, 0x84, 0x5c, 0x66, 0x0c, 0xe2, 0x05, 0x5f, 0x94, 0x74, 0xa4, 0x8a, 0xc4, 0xeb, 0x4e, 0x4d, - 0x93, 0xd2, 0xea, 0xa3, 0x4c, 0x88, 0x2e, 0x97, 0x16, 0x00, 0x03, 0x00, 0x00, + 0xd0, 0x17, 0xc0, 0x36, 0x32, 0xbc, 0x2a, 0xbc, 0x68, 0x11, 0xa0, 0x27, 0x05, 0x9d, 0x73, 0xff, + 0x55, 0xe0, 0x63, 0x92, 0x06, 0x82, 0xbd, 0xfd, 0xc3, 0xf5, 0xcf, 0x46, 0xa8, 0xbc, 0x9f, 0xec, + 0x0c, 0x78, 0x57, 0x79, 0xbf, 0x79, 0x07, 0xa3, 0x8b, 0x27, 0x33, 0x8c, 0x71, 0x98, 0x44, 0x42, + 0x9b, 0x1b, 0xae, 0x39, 0xf4, 0x18, 0xbd, 0x9b, 0xc3, 0xb0, 0xca, 0x44, 0x22, 0xb8, 0x5a, 0x50, + 0x18, 0x27, 0x0d, 0x09, 0x44, 0xc1, 0x6d, 0xfd, 0x35, 0x11, 0xfe, 0x9f, 0xe8, 0x98, 0x37, 0xb5, + 0xb6, 0xca, 0x4c, 0xf5, 0x64, 0x05, 0x24, 0x3f, 0x7c, 0xaf, 0x4a, 0x25, 0x11, 0x3d, 0x03, 0xda, + 0x0b, 0x74, 0xef, 0x37, 0xe9, 0xf9, 0x73, 0xaa, 0xe4, 0x1f, 0xa9, 0xf5, 0x19, 0x8b, 0x29, 0xb9, + 0x38, 0x15, 0x7a, 0xac, 0xe5, 0xe1, 0x58, 0x46, 0x19, 0xfb, 0x9b, 0xaf, 0xfc, 0x4a, 0x0b, 0x7e, + 0x31, 0xf2, 0xc6, 0x19, 0x38, 0x7f, 0xfa, 0x54, 0x7e, 0xc0, 0x79, 0x8f, 0xcb, 0x72, 0x22, 0x7c, + 0x99, 0x49, 0xcc, 0x43, 0xb4, 0x4f, 0x74, 0x77, 0x2a, 0x4e, 0x9c, 0x3d, 0x4b, 0x88, 0x38, 0xb5, + 0x3f, 0x8a, 0xba, 0xf7, 0x53, 0xdf, 0x77, 0x8e, 0xbc, 0xb3, 0x34, 0x53, 0x24, 0xb1, 0x53, 0x73, + 0xf7, 0xb1, 0xd9, 0x8d, 0x52, 0x75, 0xcc, 0xd6, 0xf6, 0xf8, 0x34, 0x87, 0xaa, 0xf5, 0x0c, 0x29, + 0x39, 0xea, 0x95, 0x18, 0x31, 0x4d, 0xcc, 0x7e, 0x12, 0x24, 0xed, 0x05, 0x3f, 0x98, 0x62, 0x08, + 0x03, 0xa8, 0xd3, 0x85, 0x70, 0xbe, 0x8f, 0xcb, 0x0a, 0xa4, 0x28, 0xed, 0x71, 0x37, 0xb3, 0xf1, + 0xe3, 0x18, 0x73, 0xaf, 0x71, 0xb5, 0xbb, 0x4b, 0x35, 0xb4, 0x19, 0xdb, 0x1b, 0x72, 0x0a, 0x7e, + 0xeb, 0x3b, 0x09, 0xc9, 0x08, 0x2b, 0xef, 0x30, 0x6c, 0xda, 0x08, 0x24, 0xfa, 0x9c, 0x42, 0x09, + 0xbd, 0xf7, 0xc5, 0xfc, 0x89, 0x86, 0xdd, 0x18, 0xa5, 0x43, 0x88, 0xa6, 0xba, 0x43, 0x07, 0xd4, + 0xb7, 0xdb, 0x69, 0xb6, 0xf6, 0xaa, 0x4c, 0x54, 0x17, 0x44, 0xa6, 0x48, 0xa2, 0x69, 0xbc, 0x8f, + 0x6d, 0x3c, 0x43, 0x1c, 0xc3, 0x8c, 0xc0, 0xcb, 0xa4, 0x5e, 0xd5, 0xd4, 0x6f, 0xd9, 0xdc, 0x77, + 0xe7, 0xa2, 0x74, 0xd0, 0xfd, 0x78, 0x1c, 0xff, 0x80, 0x1d, 0x6d, 0x68, 0x5f, 0x21, 0xb7, 0x0a, + 0xaa, 0x77, 0xe2, 0xd8, 0xdf, 0x0d, 0xd6, 0xf3, 0x76, 0x13, 0x9b, 0x8a, 0xa9, 0x67, 0x18, 0x2d, + 0x4e, 0xac, 0xcc, 0x5d, 0xab, 0x6e, 0xa0, 0xdd, 0x95, 0xce, 0xf3, 0x07, 0x90, 0xc9, 0x21, 0x5b, + 0x1c, 0x2d, 0xc2, 0x3c, 0xe6, 0x22, 0x18, 0x24, 0x65, 0xcb, 0x36, 0xf7, 0xab, 0x2f, 0x84, 0x30, + 0x02, 0x61, 0x4b, 0xd5, 0xfb, 0x14, 0x3f, 0xbc, 0x1a, 0xd7, 0x7b, 0x49, 0x62, 0x26, 0xb4, 0x53, + 0x3a, 0x8f, 0xa9, 0xc8, 0xd9, 0xde, 0xe2, 0x00, 0x25, 0x91, 0x4f, 0x66, 0x68, 0x92, 0x0b, 0x63, + 0x39, 0xb4, 0x72, 0xbf, 0x0b, 0xca, 0x70, 0x16, 0x1d, 0xa5, 0x3e, 0x6d, 0x7c, 0xd4, 0xc4, 0x65, + 0x87, 0x09, 0x1e, 0x3d, 0xb1, 0x62, 0x5e, 0x23, 0xa5, 0xb0, 0x94, 0xb0, 0x89, 0x60, 0x0a, 0xa3, + 0xea, 0xfb, 0x83, 0x64, 0xb3, 0x77, 0x23, 0x29, 0x41, 0xe1, 0xdf, 0x72, 0x34, 0x26, 0x3c, 0x9c, + 0x41, 0xb2, 0x50, 0x3a, 0x5e, 0x23, 0xe9, 0x1e, 0x37, 0xe9, 0x72, 0xa7, 0x09, 0x69, 0xd4, 0x37, + 0x17, 0x88, 0xab, 0x32, 0xef, 0x55, 0x66, 0x77, 0x3a, 0xbe, 0x2a, 0x47, 0xdf, 0xee, 0x72, 0x27, + 0x91, 0xe5, 0xc9, 0xe3, 0xf7, 0x11, 0x9a, 0xd4, 0x9e, 0x8c, 0x3c, 0x60, 0x42, 0xf4, 0x4e, 0x97, + 0x49, 0xd6, 0xbf, 0x20, 0x5d, 0xea, 0x2f, 0xcb, 0x2f, 0xfe, 0xa7, 0x89, 0xce, 0xe4, 0x72, 0x7c, + 0xbd, 0x57, 0xf1, 0xbc, 0x38, 0xe6, 0x96, 0xa8, 0x85, 0xb9, 0x35, 0x4b, 0xbd, 0x30, 0xa1, 0x3d, + 0xdb, 0x86, 0xb0, 0xee, 0x7c, 0xf4, 0x3f, 0xbf, 0xf2, 0x4b, 0x1c, 0xa1, 0x96, 0xd5, 0xf7, 0x52, + 0x8f, 0xe5, 0x07, 0xb9, 0xdb, 0xde, 0x13, 0x51, 0x61, 0x60, 0x3c, 0x5b, 0x7b, 0x27, 0xa0, 0x7c, + 0x7a, 0x9d, 0xc4, 0xc2, 0xd0, 0xfb, 0x3c, 0x3b, 0x45, 0x1c, 0x6f, 0xb7, 0x9a, 0x5a, 0x54, 0xb3, + 0x47, 0x38, 0x14, 0xaa, 0x30, 0x67, 0x10, 0x75, 0x96, 0xf9, 0x22, 0x0a, 0x09, 0x7b, 0x25, 0x48, + 0x68, 0x75, 0x8b, 0xfe, 0x35, 0x6b, 0xee, 0x57, 0x68, 0x08, 0x4f, 0x86, 0xeb, 0x39, 0x03, 0xde, + 0x6e, 0x3f, 0x1b, 0xe3, 0x3c, 0x9a, 0x13, 0x84, 0xe5, 0x6b, 0x0c, 0x3d, 0xd6, 0xd3, 0xaa, 0x03, + 0xce, 0xcb, 0xb9, 0x83, 0xf9, 0x6b, 0xfb, 0x87, 0x30, 0xb4, 0xff, 0xec, 0x60, 0xb2, 0xf6, 0xaf, + 0x9e, 0xc1, 0x39, 0x85, 0xad, 0x2d, 0xdc, 0x67, 0x00, 0x2c, 0x27, 0xe7, 0x33, 0xd3, 0x31, 0xd5, + 0x98, 0xec, 0xb0, 0x7e, 0xb9, 0x0d, 0xb6, 0x78, 0x02, 0xf2, 0x7a, 0xe7, 0x6a, 0x6e, 0x78, 0x38, + 0x47, 0x85, 0xca, 0x95, 0x6a, 0xa4, 0x2b, 0xdb, 0xee, 0xe3, 0x69, 0x5f, 0x49, 0x07, 0x1b, 0x05, + 0xfa, 0x95, 0xaa, 0xb8, 0xd3, 0xa3, 0x58, 0x0b, 0x29, 0x3c, 0x2c, 0x86, 0xc7, 0x3a, 0xbb, 0xe6, + 0xbf, 0x1b, 0x9a, 0xed, 0x32, 0x6d, 0x5c, 0x94, 0xe3, 0x3f, 0x70, 0x28, 0x0f, 0x99, 0xb8, 0x78, + 0x9a, 0x53, 0xab, 0x0f, 0x2e, 0x96, 0x3f, 0x38, 0x7c, 0xca, 0xfb, 0x18, 0x53, 0xf0, 0xa2, 0xcf, + 0x6e, 0x60, 0xbf, 0xda, 0x23, 0xe5, 0xa8, 0xf2, 0xc4, 0x73, 0x20, 0xe7, 0x84, 0x5c, 0x66, 0x0c, + 0xe2, 0x05, 0x5f, 0x94, 0x74, 0xa4, 0x8a, 0xc4, 0xeb, 0x4e, 0x4d, 0x93, 0xd2, 0xea, 0xa3, 0x4c, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1012,9 +1011,9 @@ BINDATA_STORAGE_PVT ksec2BinArchiveSecurescrubUcode_AD10X_sig_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 768, // uncompressed data size (bytes) - 781, // compressed data size (bytes) + 768, // compressed data size (bytes) ksec2BinArchiveSecurescrubUcode_AD10X_sig_dbg_data, // compressed data pointer - NV_TRUE, // is pData compressed? + NV_FALSE, // is pData compressed? NV_TRUE, // contain information for file overriding? NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) }, @@ -1027,62 +1026,61 @@ BINDATA_STORAGE_PVT ksec2BinArchiveSecurescrubUcode_AD10X_sig_dbg_storage_pvt; // FILE NAME: kernel/inc/securescrub/bin/ad10x/g_securescrubuc_sec2_ad10x_boot_from_hs_ad10x_rsa3k_0_sig.h // FILE TYPE: TEXT // VAR NAME: securescrub_sig_prod_ad10x -// COMPRESSION: YES +// COMPRESSION: NO // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 768 -// COMPRESSED SIZE (bytes): 781 +// COMPRESSED SIZE (bytes): N/A // static BINDATA_CONST NvU8 ksec2BinArchiveSecurescrubUcode_AD10X_sig_prod_data[] = { - 0x01, 0x00, 0x03, 0xff, 0xfc, 0x4e, 0x2a, 0xb9, 0x75, 0xf3, 0x2d, 0x67, 0x09, 0x14, 0x97, 0xe7, - 0x51, 0x0a, 0x28, 0x03, 0xa1, 0x59, 0xd7, 0xe7, 0xd5, 0xeb, 0x40, 0xce, 0xf0, 0x63, 0x89, 0x7f, - 0x19, 0xdf, 0xc9, 0x0e, 0x57, 0x3d, 0x11, 0xf6, 0x97, 0xd5, 0x0e, 0xf3, 0x57, 0x3b, 0xdc, 0xd9, - 0x37, 0xb6, 0x7b, 0xba, 0x3b, 0x25, 0x4f, 0x69, 0x80, 0x07, 0xf9, 0x96, 0xe6, 0x41, 0x4d, 0x63, - 0xd8, 0xbd, 0x9e, 0x6a, 0xe5, 0xab, 0x71, 0xf3, 0x86, 0xbb, 0xae, 0xea, 0x26, 0xae, 0x47, 0x70, - 0x57, 0x7a, 0xe1, 0x47, 0x00, 0x6c, 0x24, 0x6c, 0x9a, 0x8d, 0x27, 0x9c, 0xb4, 0xeb, 0x18, 0x01, - 0x72, 0x96, 0xe2, 0xc2, 0x3e, 0xdc, 0x01, 0xad, 0xfd, 0xcc, 0x64, 0x77, 0xe7, 0xcd, 0x95, 0x02, - 0xe8, 0x26, 0xaa, 0xd1, 0x3b, 0x03, 0x64, 0x9f, 0xed, 0x04, 0x38, 0xb1, 0x49, 0xce, 0xec, 0xc6, - 0x3f, 0xd0, 0x5f, 0x49, 0xff, 0xda, 0xfe, 0xdf, 0x12, 0x6b, 0x67, 0x65, 0x8f, 0x14, 0x6e, 0x6f, - 0x83, 0xbd, 0x7b, 0xc6, 0xcd, 0x6a, 0x1c, 0x87, 0xad, 0x3d, 0xa6, 0xb8, 0x42, 0x02, 0x99, 0x58, - 0x4b, 0x5a, 0xc1, 0xcf, 0xab, 0xf9, 0xe3, 0x84, 0xae, 0xda, 0x75, 0xd5, 0x71, 0x06, 0x5b, 0xe0, - 0x97, 0x54, 0x95, 0xae, 0x3c, 0x82, 0xad, 0x56, 0x5f, 0x25, 0x82, 0x5d, 0x66, 0x51, 0x38, 0x24, - 0x1b, 0xa9, 0x73, 0x9c, 0xb4, 0x4d, 0xc4, 0x2e, 0x85, 0x4d, 0x68, 0x05, 0x1a, 0x19, 0x86, 0xba, - 0x24, 0xe3, 0x42, 0xd7, 0x64, 0xbd, 0x28, 0xc7, 0x04, 0x42, 0x29, 0x15, 0x18, 0xa2, 0x1f, 0x36, - 0x6c, 0x37, 0x9c, 0xbf, 0x92, 0x62, 0xd6, 0xd6, 0x95, 0x4d, 0xb2, 0xb4, 0x6d, 0x01, 0xc3, 0x07, - 0xc0, 0x90, 0x8e, 0xf1, 0x42, 0x71, 0x77, 0x93, 0x5a, 0x8a, 0x8f, 0x1d, 0xa0, 0x34, 0xc2, 0xc7, - 0xcb, 0x94, 0xb0, 0xe8, 0x4e, 0x0d, 0xed, 0x72, 0xc9, 0xbc, 0xf2, 0xd3, 0xde, 0x66, 0x2a, 0x3b, - 0xc4, 0xfd, 0x03, 0x50, 0xe4, 0x6d, 0xa5, 0x53, 0x0b, 0x6e, 0x1f, 0xfc, 0xbd, 0x20, 0xf1, 0x0e, - 0x44, 0x8c, 0x73, 0x2b, 0x11, 0xed, 0x28, 0x21, 0xc0, 0x17, 0xf4, 0xef, 0xbb, 0x38, 0x01, 0xdf, - 0x2f, 0xf1, 0xb4, 0x17, 0x92, 0x95, 0x81, 0xc0, 0xad, 0x23, 0xb2, 0x3c, 0xd1, 0xc9, 0xd9, 0xde, - 0x40, 0x0f, 0xf9, 0x79, 0x43, 0xd7, 0xa9, 0x4d, 0xe9, 0x2a, 0x40, 0x8b, 0x35, 0xc9, 0xe6, 0x8c, - 0x53, 0x93, 0x9d, 0x95, 0x6a, 0xf6, 0x43, 0xf6, 0x38, 0xa0, 0x96, 0x1e, 0x66, 0xbe, 0x30, 0xeb, - 0xc0, 0xe9, 0xb4, 0x25, 0x07, 0xb7, 0x08, 0x01, 0x49, 0xbe, 0xcf, 0x5a, 0x5f, 0xb1, 0x7e, 0x51, - 0xc2, 0x74, 0x8e, 0xbf, 0x67, 0xc1, 0x82, 0x4f, 0xdf, 0x36, 0x0e, 0xe1, 0x1f, 0xb0, 0x79, 0x82, - 0x5b, 0x83, 0xf1, 0x2d, 0x30, 0x1f, 0x29, 0xe3, 0x7b, 0x90, 0x77, 0xe8, 0x92, 0x50, 0x69, 0xc8, - 0xba, 0xf4, 0x66, 0xc6, 0x9a, 0x76, 0x6b, 0x29, 0xf1, 0x4c, 0x1e, 0x6e, 0x16, 0x1c, 0xb1, 0xd8, - 0x5b, 0xd7, 0x13, 0x5b, 0x85, 0xd9, 0x20, 0xb9, 0xf1, 0xec, 0x14, 0xa8, 0x9a, 0x01, 0x28, 0xee, - 0x5f, 0x09, 0x13, 0xc4, 0x2d, 0xe7, 0x2e, 0xd1, 0x77, 0x5c, 0x9d, 0x30, 0x73, 0xff, 0xd3, 0xdf, - 0xb0, 0x5d, 0x2a, 0x53, 0x94, 0x42, 0x89, 0xa2, 0x88, 0xe9, 0x5e, 0xd8, 0x75, 0x4a, 0x9c, 0xb4, - 0x85, 0xfc, 0xb7, 0x28, 0xdf, 0x1b, 0x88, 0x96, 0x5f, 0xb7, 0xd0, 0xf1, 0x08, 0x77, 0x75, 0xd0, - 0x3c, 0x38, 0x59, 0x94, 0x9a, 0x10, 0xad, 0x84, 0xaf, 0x1e, 0x92, 0x5d, 0x43, 0x0a, 0x84, 0x0f, - 0xaa, 0xa7, 0x1f, 0x91, 0x9e, 0xe5, 0x9c, 0xfe, 0x48, 0x75, 0x8f, 0x28, 0xba, 0xc4, 0x7b, 0x0d, - 0x70, 0x77, 0x7e, 0x9a, 0x78, 0x4a, 0x04, 0x3c, 0x66, 0xd7, 0x1d, 0x76, 0x11, 0xa3, 0x54, 0x02, - 0x2c, 0x76, 0xb5, 0xbb, 0x50, 0x2b, 0x8b, 0xc8, 0x79, 0x84, 0xd3, 0x2b, 0x87, 0x64, 0x49, 0x7e, - 0xc6, 0x6a, 0x34, 0x59, 0x90, 0x1c, 0xbd, 0xe3, 0xdc, 0x9c, 0x2e, 0x43, 0xc8, 0x02, 0x8a, 0xf3, - 0x42, 0xbe, 0xfc, 0x6f, 0xa4, 0x60, 0xce, 0x23, 0x52, 0xda, 0xf2, 0x51, 0x51, 0xe2, 0xcf, 0x9b, - 0xca, 0x25, 0x97, 0xc4, 0xf9, 0x97, 0x64, 0x39, 0xcf, 0x62, 0xb3, 0xca, 0x5d, 0xf0, 0x6b, 0xa2, - 0x79, 0x83, 0x7a, 0xa5, 0xb5, 0xf0, 0xf2, 0x0d, 0x45, 0x02, 0x42, 0x51, 0xeb, 0xbd, 0x59, 0xa7, - 0x8d, 0xf3, 0xc6, 0x32, 0x05, 0x25, 0x7f, 0x2a, 0x10, 0x04, 0x83, 0x6c, 0x3c, 0xfd, 0x48, 0x63, - 0x65, 0x05, 0x45, 0x63, 0xd0, 0x76, 0x0a, 0x6b, 0x0e, 0xa7, 0x4d, 0xa3, 0x6e, 0x86, 0xb2, 0x08, - 0x67, 0xc1, 0x90, 0x58, 0xc2, 0x30, 0x9a, 0x92, 0xb9, 0x0a, 0x75, 0x76, 0xce, 0xba, 0x1a, 0xc4, - 0xfb, 0xde, 0xe4, 0x38, 0x25, 0x5c, 0x02, 0x0a, 0x47, 0x38, 0x9f, 0x82, 0x87, 0x46, 0xf6, 0x75, - 0x7a, 0x2a, 0xd3, 0x4c, 0x3e, 0xcc, 0x08, 0xfd, 0xe5, 0x11, 0x5e, 0x91, 0x0d, 0x3a, 0xa7, 0xf0, - 0xdd, 0x48, 0x82, 0x34, 0x1d, 0xe7, 0xd1, 0x9f, 0x96, 0x26, 0xec, 0xee, 0x32, 0x8b, 0x04, 0x2c, - 0x85, 0x9c, 0x93, 0x1f, 0x12, 0x6e, 0x1d, 0x0c, 0xd3, 0xa0, 0x28, 0xc9, 0x7c, 0xa6, 0xe4, 0x46, - 0x33, 0xf4, 0x9b, 0x2e, 0xd3, 0x23, 0xb0, 0x85, 0x78, 0x0f, 0xf1, 0xb0, 0x8e, 0x42, 0x5e, 0x0c, - 0xf7, 0x5a, 0x3f, 0xd2, 0x62, 0x78, 0xfa, 0xc3, 0x1d, 0x69, 0x57, 0xfc, 0x75, 0xfb, 0xfc, 0x83, - 0x22, 0x86, 0xfe, 0x48, 0x8d, 0x27, 0x0b, 0xa9, 0x01, 0x0e, 0x2d, 0x5a, 0x76, 0x7f, 0xc7, 0x08, - 0x22, 0x61, 0x8f, 0xf5, 0x71, 0xc3, 0x0b, 0x28, 0xe8, 0x00, 0x03, 0x00, 0x00, + 0x4e, 0x2a, 0xb9, 0x75, 0xf3, 0x2d, 0x67, 0x09, 0x14, 0x97, 0xe7, 0x51, 0x0a, 0x28, 0x03, 0xa1, + 0x59, 0xd7, 0xe7, 0xd5, 0xeb, 0x40, 0xce, 0xf0, 0x63, 0x89, 0x7f, 0x19, 0xdf, 0xc9, 0x0e, 0x57, + 0x3d, 0x11, 0xf6, 0x97, 0xd5, 0x0e, 0xf3, 0x57, 0x3b, 0xdc, 0xd9, 0x37, 0xb6, 0x7b, 0xba, 0x3b, + 0x25, 0x4f, 0x69, 0x80, 0x07, 0xf9, 0x96, 0xe6, 0x41, 0x4d, 0x63, 0xd8, 0xbd, 0x9e, 0x6a, 0xe5, + 0xab, 0x71, 0xf3, 0x86, 0xbb, 0xae, 0xea, 0x26, 0xae, 0x47, 0x70, 0x57, 0x7a, 0xe1, 0x47, 0x00, + 0x6c, 0x24, 0x6c, 0x9a, 0x8d, 0x27, 0x9c, 0xb4, 0xeb, 0x18, 0x01, 0x72, 0x96, 0xe2, 0xc2, 0x3e, + 0xdc, 0x01, 0xad, 0xfd, 0xcc, 0x64, 0x77, 0xe7, 0xcd, 0x95, 0x02, 0xe8, 0x26, 0xaa, 0xd1, 0x3b, + 0x03, 0x64, 0x9f, 0xed, 0x04, 0x38, 0xb1, 0x49, 0xce, 0xec, 0xc6, 0x3f, 0xd0, 0x5f, 0x49, 0xff, + 0xda, 0xfe, 0xdf, 0x12, 0x6b, 0x67, 0x65, 0x8f, 0x14, 0x6e, 0x6f, 0x83, 0xbd, 0x7b, 0xc6, 0xcd, + 0x6a, 0x1c, 0x87, 0xad, 0x3d, 0xa6, 0xb8, 0x42, 0x02, 0x99, 0x58, 0x4b, 0x5a, 0xc1, 0xcf, 0xab, + 0xf9, 0xe3, 0x84, 0xae, 0xda, 0x75, 0xd5, 0x71, 0x06, 0x5b, 0xe0, 0x97, 0x54, 0x95, 0xae, 0x3c, + 0x82, 0xad, 0x56, 0x5f, 0x25, 0x82, 0x5d, 0x66, 0x51, 0x38, 0x24, 0x1b, 0xa9, 0x73, 0x9c, 0xb4, + 0x4d, 0xc4, 0x2e, 0x85, 0x4d, 0x68, 0x05, 0x1a, 0x19, 0x86, 0xba, 0x24, 0xe3, 0x42, 0xd7, 0x64, + 0xbd, 0x28, 0xc7, 0x04, 0x42, 0x29, 0x15, 0x18, 0xa2, 0x1f, 0x36, 0x6c, 0x37, 0x9c, 0xbf, 0x92, + 0x62, 0xd6, 0xd6, 0x95, 0x4d, 0xb2, 0xb4, 0x6d, 0x01, 0xc3, 0x07, 0xc0, 0x90, 0x8e, 0xf1, 0x42, + 0x71, 0x77, 0x93, 0x5a, 0x8a, 0x8f, 0x1d, 0xa0, 0x34, 0xc2, 0xc7, 0xcb, 0x94, 0xb0, 0xe8, 0x4e, + 0x0d, 0xed, 0x72, 0xc9, 0xbc, 0xf2, 0xd3, 0xde, 0x66, 0x2a, 0x3b, 0xc4, 0xfd, 0x03, 0x50, 0xe4, + 0x6d, 0xa5, 0x53, 0x0b, 0x6e, 0x1f, 0xfc, 0xbd, 0x20, 0xf1, 0x0e, 0x44, 0x8c, 0x73, 0x2b, 0x11, + 0xed, 0x28, 0x21, 0xc0, 0x17, 0xf4, 0xef, 0xbb, 0x38, 0x01, 0xdf, 0x2f, 0xf1, 0xb4, 0x17, 0x92, + 0x95, 0x81, 0xc0, 0xad, 0x23, 0xb2, 0x3c, 0xd1, 0xc9, 0xd9, 0xde, 0x40, 0x0f, 0xf9, 0x79, 0x43, + 0xd7, 0xa9, 0x4d, 0xe9, 0x2a, 0x40, 0x8b, 0x35, 0xc9, 0xe6, 0x8c, 0x53, 0x93, 0x9d, 0x95, 0x6a, + 0xf6, 0x43, 0xf6, 0x38, 0xa0, 0x96, 0x1e, 0x66, 0xbe, 0x30, 0xeb, 0xc0, 0xe9, 0xb4, 0x25, 0x07, + 0xb7, 0x08, 0x01, 0x49, 0xbe, 0xcf, 0x5a, 0x5f, 0xb1, 0x7e, 0x51, 0xc2, 0x74, 0x8e, 0xbf, 0x67, + 0xc1, 0x82, 0x4f, 0xdf, 0x36, 0x0e, 0xe1, 0x1f, 0xb0, 0x79, 0x82, 0x5b, 0x83, 0xf1, 0x2d, 0x30, + 0x1f, 0x29, 0xe3, 0x7b, 0x90, 0x77, 0xe8, 0x92, 0x50, 0x69, 0xc8, 0xba, 0xf4, 0x66, 0xc6, 0x9a, + 0x76, 0x6b, 0x29, 0xf1, 0x4c, 0x1e, 0x6e, 0x16, 0x1c, 0xb1, 0xd8, 0x5b, 0xd7, 0x13, 0x5b, 0x85, + 0xd9, 0x20, 0xb9, 0xf1, 0xec, 0x14, 0xa8, 0x9a, 0x01, 0x28, 0xee, 0x5f, 0x09, 0x13, 0xc4, 0x2d, + 0xe7, 0x2e, 0xd1, 0x77, 0x5c, 0x9d, 0x30, 0x73, 0xff, 0xd3, 0xdf, 0xb0, 0x5d, 0x2a, 0x53, 0x94, + 0x42, 0x89, 0xa2, 0x88, 0xe9, 0x5e, 0xd8, 0x75, 0x4a, 0x9c, 0xb4, 0x85, 0xfc, 0xb7, 0x28, 0xdf, + 0x1b, 0x88, 0x96, 0x5f, 0xb7, 0xd0, 0xf1, 0x08, 0x77, 0x75, 0xd0, 0x3c, 0x38, 0x59, 0x94, 0x9a, + 0x10, 0xad, 0x84, 0xaf, 0x1e, 0x92, 0x5d, 0x43, 0x0a, 0x84, 0x0f, 0xaa, 0xa7, 0x1f, 0x91, 0x9e, + 0xe5, 0x9c, 0xfe, 0x48, 0x75, 0x8f, 0x28, 0xba, 0xc4, 0x7b, 0x0d, 0x70, 0x77, 0x7e, 0x9a, 0x78, + 0x4a, 0x04, 0x3c, 0x66, 0xd7, 0x1d, 0x76, 0x11, 0xa3, 0x54, 0x02, 0x2c, 0x76, 0xb5, 0xbb, 0x50, + 0x2b, 0x8b, 0xc8, 0x79, 0x84, 0xd3, 0x2b, 0x87, 0x64, 0x49, 0x7e, 0xc6, 0x6a, 0x34, 0x59, 0x90, + 0x1c, 0xbd, 0xe3, 0xdc, 0x9c, 0x2e, 0x43, 0xc8, 0x02, 0x8a, 0xf3, 0x42, 0xbe, 0xfc, 0x6f, 0xa4, + 0x60, 0xce, 0x23, 0x52, 0xda, 0xf2, 0x51, 0x51, 0xe2, 0xcf, 0x9b, 0xca, 0x25, 0x97, 0xc4, 0xf9, + 0x97, 0x64, 0x39, 0xcf, 0x62, 0xb3, 0xca, 0x5d, 0xf0, 0x6b, 0xa2, 0x79, 0x83, 0x7a, 0xa5, 0xb5, + 0xf0, 0xf2, 0x0d, 0x45, 0x02, 0x42, 0x51, 0xeb, 0xbd, 0x59, 0xa7, 0x8d, 0xf3, 0xc6, 0x32, 0x05, + 0x25, 0x7f, 0x2a, 0x10, 0x04, 0x83, 0x6c, 0x3c, 0xfd, 0x48, 0x63, 0x65, 0x05, 0x45, 0x63, 0xd0, + 0x76, 0x0a, 0x6b, 0x0e, 0xa7, 0x4d, 0xa3, 0x6e, 0x86, 0xb2, 0x08, 0x67, 0xc1, 0x90, 0x58, 0xc2, + 0x30, 0x9a, 0x92, 0xb9, 0x0a, 0x75, 0x76, 0xce, 0xba, 0x1a, 0xc4, 0xfb, 0xde, 0xe4, 0x38, 0x25, + 0x5c, 0x02, 0x0a, 0x47, 0x38, 0x9f, 0x82, 0x87, 0x46, 0xf6, 0x75, 0x7a, 0x2a, 0xd3, 0x4c, 0x3e, + 0xcc, 0x08, 0xfd, 0xe5, 0x11, 0x5e, 0x91, 0x0d, 0x3a, 0xa7, 0xf0, 0xdd, 0x48, 0x82, 0x34, 0x1d, + 0xe7, 0xd1, 0x9f, 0x96, 0x26, 0xec, 0xee, 0x32, 0x8b, 0x04, 0x2c, 0x85, 0x9c, 0x93, 0x1f, 0x12, + 0x6e, 0x1d, 0x0c, 0xd3, 0xa0, 0x28, 0xc9, 0x7c, 0xa6, 0xe4, 0x46, 0x33, 0xf4, 0x9b, 0x2e, 0xd3, + 0x23, 0xb0, 0x85, 0x78, 0x0f, 0xf1, 0xb0, 0x8e, 0x42, 0x5e, 0x0c, 0xf7, 0x5a, 0x3f, 0xd2, 0x62, + 0x78, 0xfa, 0xc3, 0x1d, 0x69, 0x57, 0xfc, 0x75, 0xfb, 0xfc, 0x83, 0x22, 0x86, 0xfe, 0x48, 0x8d, + 0x27, 0x0b, 0xa9, 0x01, 0x0e, 0x2d, 0x5a, 0x76, 0x7f, 0xc7, 0x08, 0x22, 0x61, 0x8f, 0xf5, 0x71, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1093,9 +1091,9 @@ BINDATA_STORAGE_PVT ksec2BinArchiveSecurescrubUcode_AD10X_sig_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 768, // uncompressed data size (bytes) - 781, // compressed data size (bytes) + 768, // compressed data size (bytes) ksec2BinArchiveSecurescrubUcode_AD10X_sig_prod_data, // compressed data pointer - NV_TRUE, // is pData compressed? + NV_FALSE, // is pData compressed? NV_TRUE, // contain information for file overriding? NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) }, diff --git a/src/nvidia/generated/g_ccsl_nvoc.h b/src/nvidia/generated/g_ccsl_nvoc.h index 3231f6d9ab..0e8146facb 100644 --- a/src/nvidia/generated/g_ccsl_nvoc.h +++ b/src/nvidia/generated/g_ccsl_nvoc.h @@ -159,4 +159,5 @@ NV_STATUS NVOC_PRIVATE_FUNCTION(ccslIncrementCounter)(pCcslContext pCtx, NvU8 *c #ifdef __cplusplus } // extern "C" #endif + #endif // _G_CCSL_NVOC_H_ diff --git a/src/nvidia/generated/g_ce_utils_nvoc.h b/src/nvidia/generated/g_ce_utils_nvoc.h index 4b575c8988..f25b85c6cf 100644 --- a/src/nvidia/generated/g_ce_utils_nvoc.h +++ b/src/nvidia/generated/g_ce_utils_nvoc.h @@ -61,6 +61,18 @@ typedef struct NvU64 submittedWorkId; // Payload to poll for async completion } CEUTILS_MEMCOPY_PARAMS; +struct KernelChannel; + +#ifndef __NVOC_CLASS_KernelChannel_TYPEDEF__ +#define __NVOC_CLASS_KernelChannel_TYPEDEF__ +typedef struct KernelChannel KernelChannel; +#endif /* __NVOC_CLASS_KernelChannel_TYPEDEF__ */ + +#ifndef __nvoc_class_id_KernelChannel +#define __nvoc_class_id_KernelChannel 0x5d8d70 +#endif /* __nvoc_class_id_KernelChannel */ + + #ifdef NVOC_CE_UTILS_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x @@ -82,6 +94,7 @@ struct CeUtils { NvU32 hTdCopyClass; NvU64 lastSubmittedPayload; NvU64 lastCompletedPayload; + struct KernelChannel *pLiteKernelChannel; }; #ifndef __NVOC_CLASS_CeUtils_TYPEDEF__ @@ -198,4 +211,5 @@ NVOC_PREFIX(ceutilsapi) class CeUtilsApi : GpuResource #ifdef __cplusplus } // extern "C" #endif + #endif // _G_CE_UTILS_NVOC_H_ diff --git a/src/nvidia/generated/g_channel_descendant_nvoc.h b/src/nvidia/generated/g_channel_descendant_nvoc.h index d1abac8a46..b3a38bfe28 100644 --- a/src/nvidia/generated/g_channel_descendant_nvoc.h +++ b/src/nvidia/generated/g_channel_descendant_nvoc.h @@ -407,4 +407,5 @@ NV_STATUS mthdNoOperation(OBJGPU *, struct ChannelDescendant *, NvU32, NvU32); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_CHANNEL_DESCENDANT_NVOC_H_ diff --git a/src/nvidia/generated/g_chips2halspec_nvoc.c b/src/nvidia/generated/g_chips2halspec_nvoc.c index 87adce7f78..aa5805511b 100644 --- a/src/nvidia/generated/g_chips2halspec_nvoc.c +++ b/src/nvidia/generated/g_chips2halspec_nvoc.c @@ -96,6 +96,20 @@ void __nvoc_init_halspec_ChipHal(ChipHal *pChipHal, NvU32 arch, NvU32 impl, NvU3 } } +void __nvoc_init_halspec_TegraChipHal(TegraChipHal *pTegraChipHal, TEGRA_CHIP_TYPE tegraType) +{ + // TEGRA_PCIE + if(tegraType == 0x0) + { + pTegraChipHal->__nvoc_HalVarIdx = 0; + } + // TEGRA_SOC + else if(tegraType == 0x1) + { + pTegraChipHal->__nvoc_HalVarIdx = 1; + } +} + void __nvoc_init_halspec_RmVariantHal(RmVariantHal *pRmVariantHal, RM_RUNTIME_VARIANT rmVariant) { // PF_KERNEL_ONLY diff --git a/src/nvidia/generated/g_chips2halspec_nvoc.h b/src/nvidia/generated/g_chips2halspec_nvoc.h index 00cb4ffae7..76c6220d0d 100644 --- a/src/nvidia/generated/g_chips2halspec_nvoc.h +++ b/src/nvidia/generated/g_chips2halspec_nvoc.h @@ -31,6 +31,38 @@ struct ChipHal { typedef struct ChipHal ChipHal; void __nvoc_init_halspec_ChipHal(ChipHal*, NvU32, NvU32, NvU32); +/* + * Tegra Chip Type Halspec + * + * For Legacy iGPUs, we have two type Tegra chips in Chips.pm + * TEGRA_DGPU : The iGPU Core inside the Tegra Soc Chip with PCIE interface. + * The behavior is more like a dGPU. Such chip is generally + * added to dGPU (CLASSIC-GPUS) chip family. E.g. GA10B + * This is generally the test chip used in MODS Arch validation + * that shares the test infrastructure with dGPU. + * + * TEGRA : The SoC chip. The chips do not share dGPU HAL on PCIE related + * implementation. + * + * The Tegra chip after Ampere arch is using PCIE interface which connects + * iGPU to SoC for BAR and control accesses (interrupt). + * The code between TEGRA_CHIP_TYPE_PCIE and TEGRA_CHIP_TYPE_SOC + * shares same dGPU ARCH specific HAL mostly except manual differences due to + * latency of manual updates between nvgpu (Standlone iGPU/Full Chip Verification) + * and nvmobile (SOC) trees. + * */ +typedef enum _TEGRA_CHIP_TYPE { + // Default TEGRA_CHIP_TYPE is TEGRA_PCIE + TEGRA_CHIP_TYPE_DEFAULT = 0, + TEGRA_CHIP_TYPE_SOC = 1, +} TEGRA_CHIP_TYPE; + +struct TegraChipHal { + unsigned short __nvoc_HalVarIdx; +}; +typedef struct TegraChipHal TegraChipHal; +void __nvoc_init_halspec_TegraChipHal(TegraChipHal*, TEGRA_CHIP_TYPE); + /* * RM Runtime Variant Halspec * @@ -119,4 +151,5 @@ void __nvoc_init_halspec_DpuIpHal(DpuIpHal*, NvU32); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_CHIPS2HALSPEC_NVOC_H_ diff --git a/src/nvidia/generated/g_chipset_nvoc.h b/src/nvidia/generated/g_chipset_nvoc.h index b712a21f64..c12d133125 100644 --- a/src/nvidia/generated/g_chipset_nvoc.h +++ b/src/nvidia/generated/g_chipset_nvoc.h @@ -285,7 +285,6 @@ struct OBJCL { NvBool PDB_PROP_CL_UPSTREAM_LTR_SUPPORTED; NvBool PDB_PROP_CL_BUG_1340801_DISABLE_GEN3_ON_GIGABYTE_SNIPER_3; NvBool PDB_PROP_CL_BUG_1681803_WAR_DISABLE_MSCG; - NvBool PDB_PROP_CL_ON_HASWELL_HOST_BRIDGE; NvBool PDB_PROP_CL_PCIE_NON_COHERENT_USE_TC0_ONLY; NvBool PDB_PROP_CL_UNSUPPORTED_CHIPSET; NvBool PDB_PROP_CL_IS_CHIPSET_IO_COHERENT; @@ -395,8 +394,6 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJCL; #define PDB_PROP_CL_ASPM_L0S_CHIPSET_ENABLED_MOBILE_ONLY_BASE_NAME PDB_PROP_CL_ASPM_L0S_CHIPSET_ENABLED_MOBILE_ONLY #define PDB_PROP_CL_BUG_3751839_GEN_SPEED_WAR_BASE_CAST #define PDB_PROP_CL_BUG_3751839_GEN_SPEED_WAR_BASE_NAME PDB_PROP_CL_BUG_3751839_GEN_SPEED_WAR -#define PDB_PROP_CL_ON_HASWELL_HOST_BRIDGE_BASE_CAST -#define PDB_PROP_CL_ON_HASWELL_HOST_BRIDGE_BASE_NAME PDB_PROP_CL_ON_HASWELL_HOST_BRIDGE #define PDB_PROP_CL_PCIE_NON_COHERENT_USE_TC0_ONLY_BASE_CAST #define PDB_PROP_CL_PCIE_NON_COHERENT_USE_TC0_ONLY_BASE_NAME PDB_PROP_CL_PCIE_NON_COHERENT_USE_TC0_ONLY #define PDB_PROP_CL_HAS_RESIZABLE_BAR_ISSUE_BASE_CAST @@ -785,48 +782,6 @@ static inline NV_STATUS clSetPortPcieCapOffset(struct OBJCL *arg0, void *arg1, N #define clSetPortPcieCapOffset_HAL(arg0, arg1, arg2) clSetPortPcieCapOffset(arg0, arg1, arg2) -NV_STATUS clGetRsdtXsdtTablesAddr_IMPL(struct OBJCL *arg0, NvU32 *arg1, NvU64 *arg2); - - -#ifdef __nvoc_chipset_h_disabled -static inline NV_STATUS clGetRsdtXsdtTablesAddr(struct OBJCL *arg0, NvU32 *arg1, NvU64 *arg2) { - NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_chipset_h_disabled -#define clGetRsdtXsdtTablesAddr(arg0, arg1, arg2) clGetRsdtXsdtTablesAddr_IMPL(arg0, arg1, arg2) -#endif //__nvoc_chipset_h_disabled - -#define clGetRsdtXsdtTablesAddr_HAL(arg0, arg1, arg2) clGetRsdtXsdtTablesAddr(arg0, arg1, arg2) - -NvBool clGetMcfgTableFromOS_IMPL(struct OBJCL *arg0, struct OBJOS *arg1, void **arg2, NvU32 *arg3); - - -#ifdef __nvoc_chipset_h_disabled -static inline NvBool clGetMcfgTableFromOS(struct OBJCL *arg0, struct OBJOS *arg1, void **arg2, NvU32 *arg3) { - NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); - return NV_FALSE; -} -#else //__nvoc_chipset_h_disabled -#define clGetMcfgTableFromOS(arg0, arg1, arg2, arg3) clGetMcfgTableFromOS_IMPL(arg0, arg1, arg2, arg3) -#endif //__nvoc_chipset_h_disabled - -#define clGetMcfgTableFromOS_HAL(arg0, arg1, arg2, arg3) clGetMcfgTableFromOS(arg0, arg1, arg2, arg3) - -NvU64 clScanForTable_IMPL(struct OBJCL *arg0, struct OBJOS *arg1, NvU64 arg2, NvU64 arg3, NvU32 arg4); - - -#ifdef __nvoc_chipset_h_disabled -static inline NvU64 clScanForTable(struct OBJCL *arg0, struct OBJOS *arg1, NvU64 arg2, NvU64 arg3, NvU32 arg4) { - NV_ASSERT_FAILED_PRECOMP("OBJCL was disabled!"); - return 0; -} -#else //__nvoc_chipset_h_disabled -#define clScanForTable(arg0, arg1, arg2, arg3, arg4) clScanForTable_IMPL(arg0, arg1, arg2, arg3, arg4) -#endif //__nvoc_chipset_h_disabled - -#define clScanForTable_HAL(arg0, arg1, arg2, arg3, arg4) clScanForTable(arg0, arg1, arg2, arg3, arg4) - NV_STATUS clStorePcieConfigSpaceBaseFromMcfg_IMPL(struct OBJCL *pCl); @@ -1195,4 +1150,5 @@ static inline void clSyncWithGsp(struct OBJCL *arg0, GspSystemInfo *arg1) { #ifdef __cplusplus } // extern "C" #endif + #endif // _G_CHIPSET_NVOC_H_ diff --git a/src/nvidia/generated/g_client_nvoc.h b/src/nvidia/generated/g_client_nvoc.h index 59534b5a82..5269682367 100644 --- a/src/nvidia/generated/g_client_nvoc.h +++ b/src/nvidia/generated/g_client_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2016-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2016-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -313,6 +313,7 @@ extern OsInfoMap g_osInfoList; // RS_PRIV_LEVEL rmclientGetCachedPrivilegeByHandle(NvHandle hClient); NvBool rmclientIsAdminByHandle(NvHandle hClient, RS_PRIV_LEVEL privLevel); +NvBool rmclientIsKernelOnlyByHandle(NvHandle hClient); NvBool rmclientSetClientFlagsByHandle(NvHandle hClient, NvU32 clientFlags); void rmclientPromoteDebuggerStateByHandle(NvHandle hClient, NvU32 newMinimumState); void *rmclientGetSecurityTokenByHandle(NvHandle hClient); @@ -325,4 +326,5 @@ NvBool rmclientIsCapableByHandle(NvHandle hClient, NvU32 capability); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_CLIENT_NVOC_H_ diff --git a/src/nvidia/generated/g_client_resource_nvoc.c b/src/nvidia/generated/g_client_resource_nvoc.c index 87fbd21dd6..2594be91b7 100644 --- a/src/nvidia/generated/g_client_resource_nvoc.c +++ b/src/nvidia/generated/g_client_resource_nvoc.c @@ -201,12 +201,12 @@ static NV_STATUS __nvoc_thunk_Notifier_cliresGetOrAllocNotifShare(struct RmClien static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClientResource[] = { { /* [0] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemGetCpuInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) - /*flags=*/ 0x13u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) + /*flags=*/ 0x813u, /*accessRight=*/0x0u, /*methodId=*/ 0x102u, /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS), @@ -261,6 +261,21 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient #endif }, { /* [4] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x805u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemGetLockTimes_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x805u) + /*flags=*/ 0x805u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x109u, + /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdSystemGetLockTimes" +#endif + }, + { /* [5] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -275,7 +290,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemNotifyEvent" #endif }, - { /* [5] */ + { /* [6] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -290,7 +305,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGetPlatformType" #endif }, - { /* [6] */ + { /* [7] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -305,7 +320,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemDebugCtrlRmMsg" #endif }, - { /* [7] */ + { /* [8] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -320,7 +335,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGpsControl" #endif }, - { /* [8] */ + { /* [9] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -335,7 +350,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGpsBatchControl" #endif }, - { /* [9] */ + { /* [10] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -350,7 +365,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGetHwbcInfo" #endif }, - { /* [10] */ + { /* [11] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -365,7 +380,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGetP2pCaps" #endif }, - { /* [11] */ + { /* [12] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -380,7 +395,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGpsCtrl" #endif }, - { /* [12] */ + { /* [13] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -395,7 +410,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGetP2pCapsV2" #endif }, - { /* [13] */ + { /* [14] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -410,7 +425,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGetPerfSensorCounters" #endif }, - { /* [14] */ + { /* [15] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -425,7 +440,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGpsCallAcpi" #endif }, - { /* [15] */ + { /* [16] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -440,7 +455,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGetExtendedPerfSensorCounters" #endif }, - { /* [16] */ + { /* [17] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -455,7 +470,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGpsGetFrmData" #endif }, - { /* [17] */ + { /* [18] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -470,7 +485,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemExecuteAcpiMethod" #endif }, - { /* [18] */ + { /* [19] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -485,7 +500,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGpsSetFrmData" #endif }, - { /* [19] */ + { /* [20] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -500,7 +515,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGetGpusPowerStatus" #endif }, - { /* [20] */ + { /* [21] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -515,7 +530,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGetPrivilegedStatus" #endif }, - { /* [21] */ + { /* [22] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -530,7 +545,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGetFabricStatus" #endif }, - { /* [22] */ + { /* [23] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -545,7 +560,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdVgpuGetVgpuVersion" #endif }, - { /* [23] */ + { /* [24] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -560,7 +575,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdVgpuSetVgpuVersion" #endif }, - { /* [24] */ + { /* [25] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -575,7 +590,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGetRmInstanceId" #endif }, - { /* [25] */ + { /* [26] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -590,7 +605,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGetP2pCapsMatrix" #endif }, - { /* [26] */ + { /* [27] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -605,7 +620,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemNVPCFGetPowerModeInfo" #endif }, - { /* [27] */ + { /* [28] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -620,7 +635,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemSyncExternalFabricMgmt" #endif }, - { /* [28] */ + { /* [29] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x807u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -635,7 +650,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGetClientDatabaseInfo" #endif }, - { /* [29] */ + { /* [30] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -650,7 +665,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGetBuildVersionV2" #endif }, - { /* [30] */ + { /* [31] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -665,7 +680,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemRmctrlCacheModeCtrl" #endif }, - { /* [31] */ + { /* [32] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -680,7 +695,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemPfmreqhndlrControl" #endif }, - { /* [32] */ + { /* [33] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -695,7 +710,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemPfmreqhndlrBatchControl" #endif }, - { /* [33] */ + { /* [34] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -710,7 +725,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemPfmreqhndlrCtrl" #endif }, - { /* [34] */ + { /* [35] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -725,7 +740,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemPfmreqhndlrCallAcpi" #endif }, - { /* [35] */ + { /* [36] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -740,7 +755,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemPfmreqhndlrGetFrmData" #endif }, - { /* [36] */ + { /* [37] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -755,7 +770,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemPfmreqhndlrSetFrmData" #endif }, - { /* [37] */ + { /* [38] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -770,7 +785,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemPfmreqhndlrGetPerfSensorCounters" #endif }, - { /* [38] */ + { /* [39] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -785,7 +800,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemPfmreqhndlrGetExtendedPerfSensorCounters" #endif }, - { /* [39] */ + { /* [40] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -800,7 +815,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGetFeatures" #endif }, - { /* [40] */ + { /* [41] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -815,7 +830,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuGetAttachedIds" #endif }, - { /* [41] */ + { /* [42] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -830,7 +845,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuGetIdInfo" #endif }, - { /* [42] */ + { /* [43] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -845,7 +860,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuGetInitStatus" #endif }, - { /* [43] */ + { /* [44] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -860,7 +875,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuGetDeviceIds" #endif }, - { /* [44] */ + { /* [45] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -875,7 +890,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuGetIdInfoV2" #endif }, - { /* [45] */ + { /* [46] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -890,7 +905,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuGetProbedIds" #endif }, - { /* [46] */ + { /* [47] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -905,7 +920,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuAttachIds" #endif }, - { /* [47] */ + { /* [48] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -920,7 +935,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuDetachIds" #endif }, - { /* [48] */ + { /* [49] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -935,7 +950,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuGetVideoLinks" #endif }, - { /* [49] */ + { /* [50] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -950,7 +965,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuGetPciInfo" #endif }, - { /* [50] */ + { /* [51] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -965,7 +980,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuGetSvmSize" #endif }, - { /* [51] */ + { /* [52] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -980,7 +995,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuGetUuidInfo" #endif }, - { /* [52] */ + { /* [53] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -995,7 +1010,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuGetUuidFromGpuId" #endif }, - { /* [53] */ + { /* [54] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1010,7 +1025,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuModifyGpuDrainState" #endif }, - { /* [54] */ + { /* [55] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1025,7 +1040,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuQueryGpuDrainState" #endif }, - { /* [55] */ + { /* [56] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1040,7 +1055,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuGetMemOpEnable" #endif }, - { /* [56] */ + { /* [57] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1055,7 +1070,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuDisableNvlinkInit" #endif }, - { /* [57] */ + { /* [58] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1070,13 +1085,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdLegacyConfig" #endif }, - { /* [58] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) + { /* [59] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdIdleChannels_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) - /*flags=*/ 0x11u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0x283u, /*paramSize=*/ sizeof(NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS), @@ -1085,7 +1100,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdIdleChannels" #endif }, - { /* [59] */ + { /* [60] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1100,7 +1115,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdPushGspUcode" #endif }, - { /* [60] */ + { /* [61] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1115,7 +1130,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuSetNvlinkBwMode" #endif }, - { /* [61] */ + { /* [62] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1130,13 +1145,28 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuGetNvlinkBwMode" #endif }, - { /* [62] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [63] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdGpuGetActiveDeviceIds_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) + /*flags=*/ 0x813u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x288u, + /*paramSize=*/ sizeof(NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdGpuGetActiveDeviceIds" +#endif + }, + { /* [64] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdGsyncGetAttachedIds_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + /*flags=*/ 0x810u, /*accessRight=*/0x0u, /*methodId=*/ 0x301u, /*paramSize=*/ sizeof(NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS), @@ -1145,7 +1175,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGsyncGetAttachedIds" #endif }, - { /* [63] */ + { /* [65] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1160,7 +1190,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGsyncGetIdInfo" #endif }, - { /* [64] */ + { /* [66] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1175,7 +1205,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdEventSetNotification" #endif }, - { /* [65] */ + { /* [67] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1190,7 +1220,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdEventGetSystemEventStatus" #endif }, - { /* [66] */ + { /* [68] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1205,7 +1235,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdNvdGetDumpSize" #endif }, - { /* [67] */ + { /* [69] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1220,7 +1250,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdNvdGetDump" #endif }, - { /* [68] */ + { /* [70] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1235,7 +1265,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdNvdGetTimestamp" #endif }, - { /* [69] */ + { /* [71] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1250,7 +1280,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdNvdGetNvlogInfo" #endif }, - { /* [70] */ + { /* [72] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1265,7 +1295,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdNvdGetNvlogBufferInfo" #endif }, - { /* [71] */ + { /* [73] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1280,7 +1310,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdNvdGetNvlog" #endif }, - { /* [72] */ + { /* [74] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1295,7 +1325,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdNvdGetRcerrRpt" #endif }, - { /* [73] */ + { /* [75] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1310,7 +1340,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSetSubProcessID" #endif }, - { /* [74] */ + { /* [76] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1325,7 +1355,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdDisableSubProcessUserdIsolation" #endif }, - { /* [75] */ + { /* [77] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1340,7 +1370,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSyncGpuBoostInfo" #endif }, - { /* [76] */ + { /* [78] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x5u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1355,7 +1385,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSyncGpuBoostGroupCreate" #endif }, - { /* [77] */ + { /* [79] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x5u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1370,7 +1400,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSyncGpuBoostGroupDestroy" #endif }, - { /* [78] */ + { /* [80] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1385,7 +1415,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSyncGpuBoostGroupInfo" #endif }, - { /* [79] */ + { /* [81] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x140004u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1400,7 +1430,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuAcctSetAccountingState" #endif }, - { /* [80] */ + { /* [82] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1415,7 +1445,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuAcctGetAccountingState" #endif }, - { /* [81] */ + { /* [83] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1430,7 +1460,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuAcctGetProcAccountingInfo" #endif }, - { /* [82] */ + { /* [84] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1445,7 +1475,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuAcctGetAccountingPids" #endif }, - { /* [83] */ + { /* [85] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x140004u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1460,7 +1490,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuAcctClearAccountingData" #endif }, - { /* [84] */ + { /* [86] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1475,7 +1505,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdVgpuGetStartData" #endif }, - { /* [85] */ + { /* [87] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1490,7 +1520,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdClientGetAddrSpaceType" #endif }, - { /* [86] */ + { /* [88] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1505,7 +1535,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdClientGetHandleInfo" #endif }, - { /* [87] */ + { /* [89] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1520,7 +1550,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdClientGetAccessRights" #endif }, - { /* [88] */ + { /* [90] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1535,7 +1565,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdClientSetInheritedSharePolicy" #endif }, - { /* [89] */ + { /* [91] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1550,7 +1580,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdClientGetChildHandle" #endif }, - { /* [90] */ + { /* [92] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1565,7 +1595,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdClientShareObject" #endif }, - { /* [91] */ + { /* [93] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1580,7 +1610,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdObjectsAreDuplicates" #endif }, - { /* [92] */ + { /* [94] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1595,7 +1625,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdOsUnixFlushUserCache" #endif }, - { /* [93] */ + { /* [95] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1610,7 +1640,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdOsUnixExportObjectToFd" #endif }, - { /* [94] */ + { /* [96] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1625,7 +1655,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdOsUnixImportObjectFromFd" #endif }, - { /* [95] */ + { /* [97] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1640,7 +1670,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdOsUnixGetExportObjectInfo" #endif }, - { /* [96] */ + { /* [98] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1655,7 +1685,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdOsUnixCreateExportObjectFd" #endif }, - { /* [97] */ + { /* [99] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1670,7 +1700,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdOsUnixExportObjectsToFd" #endif }, - { /* [98] */ + { /* [100] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1690,7 +1720,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient const struct NVOC_EXPORT_INFO __nvoc_export_info_RmClientResource = { - /*numEntries=*/ 99, + /*numEntries=*/ 101, /*pExportEntries=*/ __nvoc_exported_method_def_RmClientResource }; @@ -1749,7 +1779,7 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) { pThis->__cliresControl_Epilogue__ = &cliresControl_Epilogue_IMPL; -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) pThis->__cliresCtrlCmdSystemGetCpuInfo__ = &cliresCtrlCmdSystemGetCpuInfo_IMPL; #endif @@ -1773,6 +1803,10 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) { pThis->__cliresCtrlCmdSystemSetMemorySize__ = &cliresCtrlCmdSystemSetMemorySize_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x805u) + pThis->__cliresCtrlCmdSystemGetLockTimes__ = &cliresCtrlCmdSystemGetLockTimes_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__cliresCtrlCmdSystemGetClassList__ = &cliresCtrlCmdSystemGetClassList_IMPL; #endif @@ -1937,6 +1971,10 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) { pThis->__cliresCtrlCmdGpuGetDeviceIds__ = &cliresCtrlCmdGpuGetDeviceIds_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) + pThis->__cliresCtrlCmdGpuGetActiveDeviceIds__ = &cliresCtrlCmdGpuGetActiveDeviceIds_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__cliresCtrlCmdGpuGetProbedIds__ = &cliresCtrlCmdGpuGetProbedIds_IMPL; #endif @@ -1993,7 +2031,7 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) { pThis->__cliresCtrlCmdLegacyConfig__ = &cliresCtrlCmdLegacyConfig_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__cliresCtrlCmdIdleChannels__ = &cliresCtrlCmdIdleChannels_IMPL; #endif @@ -2005,7 +2043,7 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) { pThis->__cliresCtrlCmdGpuGetVideoLinks__ = &cliresCtrlCmdGpuGetVideoLinks_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) pThis->__cliresCtrlCmdGsyncGetAttachedIds__ = &cliresCtrlCmdGsyncGetAttachedIds_IMPL; #endif diff --git a/src/nvidia/generated/g_client_resource_nvoc.h b/src/nvidia/generated/g_client_resource_nvoc.h index e53cfa0980..469d25be55 100644 --- a/src/nvidia/generated/g_client_resource_nvoc.h +++ b/src/nvidia/generated/g_client_resource_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2016-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -84,6 +84,7 @@ struct RmClientResource { NV_STATUS (*__cliresCtrlCmdSystemExecuteAcpiMethod__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemGetChipsetInfo__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemSetMemorySize__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS *); + NV_STATUS (*__cliresCtrlCmdSystemGetLockTimes__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemGetClassList__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemNotifyEvent__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemGetPlatformType__)(struct RmClientResource *, NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS *); @@ -125,6 +126,7 @@ struct RmClientResource { NV_STATUS (*__cliresCtrlCmdGpuGetIdInfoV2__)(struct RmClientResource *, NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS *); NV_STATUS (*__cliresCtrlCmdGpuGetInitStatus__)(struct RmClientResource *, NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS *); NV_STATUS (*__cliresCtrlCmdGpuGetDeviceIds__)(struct RmClientResource *, NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS *); + NV_STATUS (*__cliresCtrlCmdGpuGetActiveDeviceIds__)(struct RmClientResource *, NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS *); NV_STATUS (*__cliresCtrlCmdGpuGetProbedIds__)(struct RmClientResource *, NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS *); NV_STATUS (*__cliresCtrlCmdGpuAttachIds__)(struct RmClientResource *, NV0000_CTRL_GPU_ATTACH_IDS_PARAMS *); NV_STATUS (*__cliresCtrlCmdGpuDetachIds__)(struct RmClientResource *, NV0000_CTRL_GPU_DETACH_IDS_PARAMS *); @@ -236,6 +238,7 @@ NV_STATUS __nvoc_objCreate_RmClientResource(RmClientResource**, Dynamic*, NvU32, #define cliresCtrlCmdSystemExecuteAcpiMethod(pRmCliRes, pAcpiMethodParams) cliresCtrlCmdSystemExecuteAcpiMethod_DISPATCH(pRmCliRes, pAcpiMethodParams) #define cliresCtrlCmdSystemGetChipsetInfo(pRmCliRes, pChipsetInfo) cliresCtrlCmdSystemGetChipsetInfo_DISPATCH(pRmCliRes, pChipsetInfo) #define cliresCtrlCmdSystemSetMemorySize(pRmCliRes, pParams) cliresCtrlCmdSystemSetMemorySize_DISPATCH(pRmCliRes, pParams) +#define cliresCtrlCmdSystemGetLockTimes(pRmCliRes, pParams) cliresCtrlCmdSystemGetLockTimes_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdSystemGetClassList(pRmCliRes, pParams) cliresCtrlCmdSystemGetClassList_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdSystemNotifyEvent(pRmCliRes, pParams) cliresCtrlCmdSystemNotifyEvent_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdSystemGetPlatformType(pRmCliRes, pSysParams) cliresCtrlCmdSystemGetPlatformType_DISPATCH(pRmCliRes, pSysParams) @@ -277,6 +280,7 @@ NV_STATUS __nvoc_objCreate_RmClientResource(RmClientResource**, Dynamic*, NvU32, #define cliresCtrlCmdGpuGetIdInfoV2(pRmCliRes, pGpuIdInfoParams) cliresCtrlCmdGpuGetIdInfoV2_DISPATCH(pRmCliRes, pGpuIdInfoParams) #define cliresCtrlCmdGpuGetInitStatus(pRmCliRes, pGpuInitStatusParams) cliresCtrlCmdGpuGetInitStatus_DISPATCH(pRmCliRes, pGpuInitStatusParams) #define cliresCtrlCmdGpuGetDeviceIds(pRmCliRes, pDeviceIdsParams) cliresCtrlCmdGpuGetDeviceIds_DISPATCH(pRmCliRes, pDeviceIdsParams) +#define cliresCtrlCmdGpuGetActiveDeviceIds(pRmCliRes, pActiveDeviceIdsParams) cliresCtrlCmdGpuGetActiveDeviceIds_DISPATCH(pRmCliRes, pActiveDeviceIdsParams) #define cliresCtrlCmdGpuGetProbedIds(pRmCliRes, pGpuProbedIds) cliresCtrlCmdGpuGetProbedIds_DISPATCH(pRmCliRes, pGpuProbedIds) #define cliresCtrlCmdGpuAttachIds(pRmCliRes, pGpuAttachIds) cliresCtrlCmdGpuAttachIds_DISPATCH(pRmCliRes, pGpuAttachIds) #define cliresCtrlCmdGpuDetachIds(pRmCliRes, pGpuDetachIds) cliresCtrlCmdGpuDetachIds_DISPATCH(pRmCliRes, pGpuDetachIds) @@ -408,6 +412,12 @@ static inline NV_STATUS cliresCtrlCmdSystemSetMemorySize_DISPATCH(struct RmClien return pRmCliRes->__cliresCtrlCmdSystemSetMemorySize__(pRmCliRes, pParams); } +NV_STATUS cliresCtrlCmdSystemGetLockTimes_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS *pParams); + +static inline NV_STATUS cliresCtrlCmdSystemGetLockTimes_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS *pParams) { + return pRmCliRes->__cliresCtrlCmdSystemGetLockTimes__(pRmCliRes, pParams); +} + NV_STATUS cliresCtrlCmdSystemGetClassList_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS *pParams); static inline NV_STATUS cliresCtrlCmdSystemGetClassList_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS *pParams) { @@ -654,6 +664,12 @@ static inline NV_STATUS cliresCtrlCmdGpuGetDeviceIds_DISPATCH(struct RmClientRes return pRmCliRes->__cliresCtrlCmdGpuGetDeviceIds__(pRmCliRes, pDeviceIdsParams); } +NV_STATUS cliresCtrlCmdGpuGetActiveDeviceIds_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS *pActiveDeviceIdsParams); + +static inline NV_STATUS cliresCtrlCmdGpuGetActiveDeviceIds_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS *pActiveDeviceIdsParams) { + return pRmCliRes->__cliresCtrlCmdGpuGetActiveDeviceIds__(pRmCliRes, pActiveDeviceIdsParams); +} + NV_STATUS cliresCtrlCmdGpuGetProbedIds_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS *pGpuProbedIds); static inline NV_STATUS cliresCtrlCmdGpuGetProbedIds_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS *pGpuProbedIds) { @@ -1064,4 +1080,5 @@ NV_STATUS CliGetSystemP2pCaps(NvU32 *gpuIds, #ifdef __cplusplus } // extern "C" #endif + #endif // _G_CLIENT_RESOURCE_NVOC_H_ diff --git a/src/nvidia/generated/g_compute_instance_subscription_nvoc.h b/src/nvidia/generated/g_compute_instance_subscription_nvoc.h index 652f757d49..bffa743f80 100644 --- a/src/nvidia/generated/g_compute_instance_subscription_nvoc.h +++ b/src/nvidia/generated/g_compute_instance_subscription_nvoc.h @@ -94,6 +94,45 @@ struct ComputeInstanceSubscription { NvU64 PRIVATE_FIELD(dupedCapDescriptor); }; +struct ComputeInstanceSubscription_PRIVATE { + const struct NVOC_RTTI *__nvoc_rtti; + struct GpuResource __nvoc_base_GpuResource; + struct Object *__nvoc_pbase_Object; + struct RsResource *__nvoc_pbase_RsResource; + struct RmResourceCommon *__nvoc_pbase_RmResourceCommon; + struct RmResource *__nvoc_pbase_RmResource; + struct GpuResource *__nvoc_pbase_GpuResource; + struct ComputeInstanceSubscription *__nvoc_pbase_ComputeInstanceSubscription; + NvBool (*__cisubscriptionCanCopy__)(struct ComputeInstanceSubscription *); + NV_STATUS (*__cisubscriptionCtrlCmdGetUuid__)(struct ComputeInstanceSubscription *, NVC638_CTRL_GET_UUID_PARAMS *); + NvBool (*__cisubscriptionShareCallback__)(struct ComputeInstanceSubscription *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__cisubscriptionCheckMemInterUnmap__)(struct ComputeInstanceSubscription *, NvBool); + NV_STATUS (*__cisubscriptionMapTo__)(struct ComputeInstanceSubscription *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__cisubscriptionGetMapAddrSpace__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__cisubscriptionGetRefCount__)(struct ComputeInstanceSubscription *); + void (*__cisubscriptionAddAdditionalDependants__)(struct RsClient *, struct ComputeInstanceSubscription *, RsResourceRef *); + NV_STATUS (*__cisubscriptionControl_Prologue__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__cisubscriptionGetRegBaseOffsetAndSize__)(struct ComputeInstanceSubscription *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__cisubscriptionInternalControlForward__)(struct ComputeInstanceSubscription *, NvU32, void *, NvU32); + NV_STATUS (*__cisubscriptionUnmapFrom__)(struct ComputeInstanceSubscription *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__cisubscriptionControl_Epilogue__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__cisubscriptionControlLookup__)(struct ComputeInstanceSubscription *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NvHandle (*__cisubscriptionGetInternalObjectHandle__)(struct ComputeInstanceSubscription *); + NV_STATUS (*__cisubscriptionControl__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__cisubscriptionUnmap__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RsCpuMapping *); + NV_STATUS (*__cisubscriptionGetMemInterMapParams__)(struct ComputeInstanceSubscription *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__cisubscriptionGetMemoryMappingDescriptor__)(struct ComputeInstanceSubscription *, struct MEMORY_DESCRIPTOR **); + NV_STATUS (*__cisubscriptionControlFilter__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__cisubscriptionControlSerialization_Prologue__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + void (*__cisubscriptionPreDestruct__)(struct ComputeInstanceSubscription *); + NV_STATUS (*__cisubscriptionIsDuplicate__)(struct ComputeInstanceSubscription *, NvHandle, NvBool *); + void (*__cisubscriptionControlSerialization_Epilogue__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__cisubscriptionMap__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); + NvBool (*__cisubscriptionAccessCallback__)(struct ComputeInstanceSubscription *, struct RsClient *, void *, RsAccessRight); + MIG_COMPUTE_INSTANCE *pMIGComputeInstance; + NvU64 dupedCapDescriptor; +}; + #ifndef __NVOC_CLASS_ComputeInstanceSubscription_TYPEDEF__ #define __NVOC_CLASS_ComputeInstanceSubscription_TYPEDEF__ typedef struct ComputeInstanceSubscription ComputeInstanceSubscription; @@ -256,6 +295,11 @@ static inline NvBool cisubscriptionAccessCallback_DISPATCH(struct ComputeInstanc return pResource->__cisubscriptionAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); } +static inline MIG_COMPUTE_INSTANCE *cisubscriptionGetMIGComputeInstance(struct ComputeInstanceSubscription *pComputeInstanceSubscription) { + struct ComputeInstanceSubscription_PRIVATE *pComputeInstanceSubscription_PRIVATE = (struct ComputeInstanceSubscription_PRIVATE *)pComputeInstanceSubscription; + return pComputeInstanceSubscription_PRIVATE->pMIGComputeInstance; +} + NV_STATUS cisubscriptionGetComputeInstanceSubscription_IMPL(struct RsClient *arg0, NvHandle arg1, struct ComputeInstanceSubscription **arg2); #define cisubscriptionGetComputeInstanceSubscription(arg0, arg1, arg2) cisubscriptionGetComputeInstanceSubscription_IMPL(arg0, arg1, arg2) @@ -285,4 +329,5 @@ void cisubscriptionDestruct_IMPL(struct ComputeInstanceSubscription *arg0); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_COMPUTE_INSTANCE_SUBSCRIPTION_NVOC_H_ diff --git a/src/nvidia/generated/g_conf_compute_api_nvoc.h b/src/nvidia/generated/g_conf_compute_api_nvoc.h index 8268bd3bc8..560c8bd49a 100644 --- a/src/nvidia/generated/g_conf_compute_api_nvoc.h +++ b/src/nvidia/generated/g_conf_compute_api_nvoc.h @@ -294,4 +294,5 @@ void confComputeApiDestruct_IMPL(struct ConfidentialComputeApi *pConfComputeApi) #ifdef __cplusplus } // extern "C" #endif + #endif // _G_CONF_COMPUTE_API_NVOC_H_ diff --git a/src/nvidia/generated/g_conf_compute_nvoc.h b/src/nvidia/generated/g_conf_compute_nvoc.h index e553056dd3..a5de3246f8 100644 --- a/src/nvidia/generated/g_conf_compute_nvoc.h +++ b/src/nvidia/generated/g_conf_compute_nvoc.h @@ -534,4 +534,5 @@ NV_STATUS spdmCtrlSpdmPartition(struct OBJGPU *pGpu, NV2080_CTRL_INTERNAL_SPDM_P #ifdef __cplusplus } // extern "C" #endif + #endif // _G_CONF_COMPUTE_NVOC_H_ diff --git a/src/nvidia/generated/g_console_mem_nvoc.c b/src/nvidia/generated/g_console_mem_nvoc.c index ed96fb0f25..6a38d1988c 100644 --- a/src/nvidia/generated/g_console_mem_nvoc.c +++ b/src/nvidia/generated/g_console_mem_nvoc.c @@ -113,6 +113,10 @@ static NV_STATUS __nvoc_thunk_Memory_conmemGetMapAddrSpace(struct ConsoleMemory return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); } +static NvBool __nvoc_thunk_Memory_conmemIsExportAllowed(struct ConsoleMemory *pMemory) { + return memIsExportAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset)); +} + static NvU32 __nvoc_thunk_RsResource_conmemGetRefCount(struct ConsoleMemory *pResource) { return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RsResource.offset)); } @@ -243,6 +247,8 @@ static void __nvoc_init_funcTable_ConsoleMemory_1(ConsoleMemory *pThis) { pThis->__conmemGetMapAddrSpace__ = &__nvoc_thunk_Memory_conmemGetMapAddrSpace; + pThis->__conmemIsExportAllowed__ = &__nvoc_thunk_Memory_conmemIsExportAllowed; + pThis->__conmemGetRefCount__ = &__nvoc_thunk_RsResource_conmemGetRefCount; pThis->__conmemAddAdditionalDependants__ = &__nvoc_thunk_RsResource_conmemAddAdditionalDependants; diff --git a/src/nvidia/generated/g_console_mem_nvoc.h b/src/nvidia/generated/g_console_mem_nvoc.h index ddab10389d..d24312b218 100644 --- a/src/nvidia/generated/g_console_mem_nvoc.h +++ b/src/nvidia/generated/g_console_mem_nvoc.h @@ -58,6 +58,7 @@ struct ConsoleMemory { NvBool (*__conmemShareCallback__)(struct ConsoleMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__conmemMapTo__)(struct ConsoleMemory *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__conmemGetMapAddrSpace__)(struct ConsoleMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvBool (*__conmemIsExportAllowed__)(struct ConsoleMemory *); NvU32 (*__conmemGetRefCount__)(struct ConsoleMemory *); void (*__conmemAddAdditionalDependants__)(struct RsClient *, struct ConsoleMemory *, RsResourceRef *); NV_STATUS (*__conmemControl_Prologue__)(struct ConsoleMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -113,6 +114,7 @@ NV_STATUS __nvoc_objCreate_ConsoleMemory(ConsoleMemory**, Dynamic*, NvU32, CALL_ #define conmemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) conmemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define conmemMapTo(pResource, pParams) conmemMapTo_DISPATCH(pResource, pParams) #define conmemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) conmemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define conmemIsExportAllowed(pMemory) conmemIsExportAllowed_DISPATCH(pMemory) #define conmemGetRefCount(pResource) conmemGetRefCount_DISPATCH(pResource) #define conmemAddAdditionalDependants(pClient, pResource, pReference) conmemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define conmemControl_Prologue(pResource, pCallContext, pParams) conmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) @@ -155,6 +157,10 @@ static inline NV_STATUS conmemGetMapAddrSpace_DISPATCH(struct ConsoleMemory *pMe return pMemory->__conmemGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); } +static inline NvBool conmemIsExportAllowed_DISPATCH(struct ConsoleMemory *pMemory) { + return pMemory->__conmemIsExportAllowed__(pMemory); +} + static inline NvU32 conmemGetRefCount_DISPATCH(struct ConsoleMemory *pResource) { return pResource->__conmemGetRefCount__(pResource); } @@ -246,4 +252,5 @@ NV_STATUS conmemConstruct_IMPL(struct ConsoleMemory *arg_pConsoleMemory, CALL_CO #ifdef __cplusplus } // extern "C" #endif + #endif // _G_CONSOLE_MEM_NVOC_H_ diff --git a/src/nvidia/generated/g_context_dma_nvoc.h b/src/nvidia/generated/g_context_dma_nvoc.h index 01bafb7799..56232ee02a 100644 --- a/src/nvidia/generated/g_context_dma_nvoc.h +++ b/src/nvidia/generated/g_context_dma_nvoc.h @@ -375,4 +375,5 @@ NV_STATUS CliGetContextDma(NvHandle hClient, NvHandle hContextDma, struct Contex #ifdef __cplusplus } // extern "C" #endif + #endif // _G_CONTEXT_DMA_NVOC_H_ diff --git a/src/nvidia/generated/g_crashcat_engine_nvoc.h b/src/nvidia/generated/g_crashcat_engine_nvoc.h index a3721018ce..d866da5afc 100644 --- a/src/nvidia/generated/g_crashcat_engine_nvoc.h +++ b/src/nvidia/generated/g_crashcat_engine_nvoc.h @@ -284,4 +284,5 @@ void crashcatEnginePrintf(struct CrashCatEngine *, NvBool, const char *, ...); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_CRASHCAT_ENGINE_NVOC_H_ diff --git a/src/nvidia/generated/g_crashcat_queue_nvoc.h b/src/nvidia/generated/g_crashcat_queue_nvoc.h index 9a1c762ec4..d4f19ebc15 100644 --- a/src/nvidia/generated/g_crashcat_queue_nvoc.h +++ b/src/nvidia/generated/g_crashcat_queue_nvoc.h @@ -144,4 +144,5 @@ void crashcatQueueDestruct_IMPL(struct CrashCatQueue *arg0); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_CRASHCAT_QUEUE_NVOC_H_ diff --git a/src/nvidia/generated/g_crashcat_report_nvoc.h b/src/nvidia/generated/g_crashcat_report_nvoc.h index ac2befbfbe..af03bb060e 100644 --- a/src/nvidia/generated/g_crashcat_report_nvoc.h +++ b/src/nvidia/generated/g_crashcat_report_nvoc.h @@ -385,4 +385,5 @@ const char *crashcatReportRiscvCauseToString(NvU64 xcause); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_CRASHCAT_REPORT_NVOC_H_ diff --git a/src/nvidia/generated/g_crashcat_wayfinder_nvoc.h b/src/nvidia/generated/g_crashcat_wayfinder_nvoc.h index 0573ca8313..1ea98b9dea 100644 --- a/src/nvidia/generated/g_crashcat_wayfinder_nvoc.h +++ b/src/nvidia/generated/g_crashcat_wayfinder_nvoc.h @@ -167,4 +167,5 @@ void NVOC_PRIVATE_FUNCTION(crashcatWayfinderSetWFL0)(struct CrashCatWayfinder *a #ifdef __cplusplus } // extern "C" #endif + #endif // _G_CRASHCAT_WAYFINDER_NVOC_H_ diff --git a/src/nvidia/generated/g_dbgbuffer_nvoc.h b/src/nvidia/generated/g_dbgbuffer_nvoc.h index 35af3c50d8..5e1bd7a644 100644 --- a/src/nvidia/generated/g_dbgbuffer_nvoc.h +++ b/src/nvidia/generated/g_dbgbuffer_nvoc.h @@ -264,4 +264,5 @@ void dbgbufDestruct_IMPL(struct DebugBufferApi *pDebugBufferApi); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_DBGBUFFER_NVOC_H_ diff --git a/src/nvidia/generated/g_dce_client_nvoc.h b/src/nvidia/generated/g_dce_client_nvoc.h index 21338e8bcc..f03e892198 100644 --- a/src/nvidia/generated/g_dce_client_nvoc.h +++ b/src/nvidia/generated/g_dce_client_nvoc.h @@ -186,6 +186,9 @@ static inline NvBool dceclientIsPresent_DISPATCH(POBJGPU pGpu, struct OBJDCECLIE return pEngstate->__dceclientIsPresent__(pGpu, pEngstate); } +void dceclientDestruct_IMPL(struct OBJDCECLIENTRM *arg0); + +#define __nvoc_dceclientDestruct(arg0) dceclientDestruct_IMPL(arg0) NV_STATUS dceclientInitRpcInfra_IMPL(struct OBJGPU *arg0, struct OBJDCECLIENTRM *arg1); #ifdef __nvoc_dce_client_h_disabled @@ -250,4 +253,5 @@ NV_STATUS rpcDceRmInit_dce(RM_API *pRmApi, NvBool bInit); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_DCE_CLIENT_NVOC_H_ diff --git a/src/nvidia/generated/g_deferred_api_nvoc.h b/src/nvidia/generated/g_deferred_api_nvoc.h index 6a5457317d..17843b5b43 100644 --- a/src/nvidia/generated/g_deferred_api_nvoc.h +++ b/src/nvidia/generated/g_deferred_api_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -47,7 +47,6 @@ typedef struct _def_deferred_api_info { NODE Node; NvHandle Handle; - NvHandle Client; NvU32 Flags; // see DEFERRED_API_INFO_FLAGS_* defines RS_PRIV_LEVEL privLevel; // privilege level of the client that initiated deferred call. void * pDeferredApiInfo; @@ -341,4 +340,5 @@ void defapiDestruct_IMPL(struct DeferredApiObject *pDeferredApi); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_DEFERRED_API_NVOC_H_ diff --git a/src/nvidia/generated/g_device_nvoc.c b/src/nvidia/generated/g_device_nvoc.c index 6b9e2989ee..67edd39ddc 100644 --- a/src/nvidia/generated/g_device_nvoc.c +++ b/src/nvidia/generated/g_device_nvoc.c @@ -410,12 +410,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] #endif }, { /* [14] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) deviceCtrlCmdGpuGetFindSubDeviceHandle_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) - /*flags=*/ 0x13u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) + /*flags=*/ 0x813u, /*accessRight=*/0x0u, /*methodId=*/ 0x800293u, /*paramSize=*/ sizeof(NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM), @@ -650,12 +650,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] #endif }, { /* [30] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2a10u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) deviceCtrlCmdFifoGetEngineContextProperties_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) - /*flags=*/ 0x2210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2a10u) + /*flags=*/ 0x2a10u, /*accessRight=*/0x0u, /*methodId=*/ 0x801707u, /*paramSize=*/ sizeof(NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS), @@ -860,12 +860,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] #endif }, { /* [44] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) deviceCtrlCmdDmaGetCaps_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) - /*flags=*/ 0x11u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0x80180du, /*paramSize=*/ sizeof(NV0080_CTRL_DMA_GET_CAPS_PARAMS), @@ -965,12 +965,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] #endif }, { /* [51] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) deviceCtrlCmdMsencGetCaps_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + /*flags=*/ 0x810u, /*accessRight=*/0x0u, /*methodId=*/ 0x801b01u, /*paramSize=*/ sizeof(NV0080_CTRL_MSENC_GET_CAPS_PARAMS), @@ -980,12 +980,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] #endif }, { /* [52] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa10u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) deviceCtrlCmdBspGetCapsV2_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa10u) + /*flags=*/ 0xa10u, /*accessRight=*/0x0u, /*methodId=*/ 0x801c02u, /*paramSize=*/ sizeof(NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2), @@ -1182,7 +1182,7 @@ static void __nvoc_init_funcTable_Device_1(Device *pThis) { pThis->__deviceCtrlCmdDmaInvalidateTLB__ = &deviceCtrlCmdDmaInvalidateTLB_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__deviceCtrlCmdDmaGetCaps__ = &deviceCtrlCmdDmaGetCaps_IMPL; #endif @@ -1246,7 +1246,7 @@ static void __nvoc_init_funcTable_Device_1(Device *pThis) { pThis->__deviceCtrlCmdFifoStartSelectedChannels__ = &deviceCtrlCmdFifoStartSelectedChannels_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2a10u) pThis->__deviceCtrlCmdFifoGetEngineContextProperties__ = &deviceCtrlCmdFifoGetEngineContextProperties_IMPL; #endif @@ -1342,15 +1342,15 @@ static void __nvoc_init_funcTable_Device_1(Device *pThis) { pThis->__deviceCtrlCmdGpuGetSriovCaps__ = &deviceCtrlCmdGpuGetSriovCaps_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) pThis->__deviceCtrlCmdGpuGetFindSubDeviceHandle__ = &deviceCtrlCmdGpuGetFindSubDeviceHandle_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) pThis->__deviceCtrlCmdMsencGetCaps__ = &deviceCtrlCmdMsencGetCaps_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa10u) pThis->__deviceCtrlCmdBspGetCapsV2__ = &deviceCtrlCmdBspGetCapsV2_IMPL; #endif diff --git a/src/nvidia/generated/g_device_nvoc.h b/src/nvidia/generated/g_device_nvoc.h index 6f58d1f22a..03bc22c868 100644 --- a/src/nvidia/generated/g_device_nvoc.h +++ b/src/nvidia/generated/g_device_nvoc.h @@ -761,17 +761,6 @@ NV_STATUS deviceConstruct_IMPL(struct Device *arg_pResource, struct CALL_CONTEXT void deviceDestruct_IMPL(struct Device *pResource); #define __nvoc_deviceDestruct(pResource) deviceDestruct_IMPL(pResource) -NV_STATUS deviceInit_IMPL(struct Device *pDevice, struct CALL_CONTEXT *pCallContext, NvHandle hClient, NvHandle hDevice, NvU32 deviceInst, NvHandle hClientShare, NvHandle hTargetClient, NvHandle hTargetDevice, NvU64 vaSize, NvU64 vaStartInternal, NvU64 vaLimitInternal, NvU32 allocFlags, NvU32 vaMode); - -#ifdef __nvoc_device_h_disabled -static inline NV_STATUS deviceInit(struct Device *pDevice, struct CALL_CONTEXT *pCallContext, NvHandle hClient, NvHandle hDevice, NvU32 deviceInst, NvHandle hClientShare, NvHandle hTargetClient, NvHandle hTargetDevice, NvU64 vaSize, NvU64 vaStartInternal, NvU64 vaLimitInternal, NvU32 allocFlags, NvU32 vaMode) { - NV_ASSERT_FAILED_PRECOMP("Device was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_device_h_disabled -#define deviceInit(pDevice, pCallContext, hClient, hDevice, deviceInst, hClientShare, hTargetClient, hTargetDevice, vaSize, vaStartInternal, vaLimitInternal, allocFlags, vaMode) deviceInit_IMPL(pDevice, pCallContext, hClient, hDevice, deviceInst, hClientShare, hTargetClient, hTargetDevice, vaSize, vaStartInternal, vaLimitInternal, allocFlags, vaMode) -#endif //__nvoc_device_h_disabled - NV_STATUS deviceGetByHandle_IMPL(struct RsClient *pClient, NvHandle hDevice, struct Device **ppDevice); #define deviceGetByHandle(pClient, hDevice, ppDevice) deviceGetByHandle_IMPL(pClient, hDevice, ppDevice) @@ -872,4 +861,5 @@ OBJGPU *CliGetGpuFromHandle(NvHandle hClient, NvHandle hResource, NvBool *pbBroa #ifdef __cplusplus } // extern "C" #endif + #endif // _G_DEVICE_NVOC_H_ diff --git a/src/nvidia/generated/g_disp_capabilities_nvoc.h b/src/nvidia/generated/g_disp_capabilities_nvoc.h index 4869f54902..e1bf07f37d 100644 --- a/src/nvidia/generated/g_disp_capabilities_nvoc.h +++ b/src/nvidia/generated/g_disp_capabilities_nvoc.h @@ -255,4 +255,5 @@ NV_STATUS dispcapConstruct_IMPL(struct DispCapabilities *arg_pDispCapabilities, #ifdef __cplusplus } // extern "C" #endif + #endif // _G_DISP_CAPABILITIES_NVOC_H_ diff --git a/src/nvidia/generated/g_disp_channel_nvoc.h b/src/nvidia/generated/g_disp_channel_nvoc.h index f5a9770958..f57fde60c2 100644 --- a/src/nvidia/generated/g_disp_channel_nvoc.h +++ b/src/nvidia/generated/g_disp_channel_nvoc.h @@ -838,4 +838,5 @@ NV_STATUS dispchndmaConstruct_IMPL(struct DispChannelDma *arg_pDispChannelDma, s #ifdef __cplusplus } // extern "C" #endif + #endif // _G_DISP_CHANNEL_NVOC_H_ diff --git a/src/nvidia/generated/g_disp_inst_mem_nvoc.h b/src/nvidia/generated/g_disp_inst_mem_nvoc.h index 7cf0e2d941..1125df9b2d 100644 --- a/src/nvidia/generated/g_disp_inst_mem_nvoc.h +++ b/src/nvidia/generated/g_disp_inst_mem_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -340,28 +340,6 @@ static inline void instmemUnbindDispChannelContextDmas(OBJGPU *pGpu, struct Disp #define instmemUnbindDispChannelContextDmas(pGpu, pInstMem, pDispChannel) instmemUnbindDispChannelContextDmas_IMPL(pGpu, pInstMem, pDispChannel) #endif //__nvoc_disp_inst_mem_h_disabled -NV_STATUS instmemReserveContextDma_IMPL(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, NvU32 *offset); - -#ifdef __nvoc_disp_inst_mem_h_disabled -static inline NV_STATUS instmemReserveContextDma(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, NvU32 *offset) { - NV_ASSERT_FAILED_PRECOMP("DisplayInstanceMemory was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_disp_inst_mem_h_disabled -#define instmemReserveContextDma(pGpu, pInstMem, offset) instmemReserveContextDma_IMPL(pGpu, pInstMem, offset) -#endif //__nvoc_disp_inst_mem_h_disabled - -NV_STATUS instmemFreeContextDma_IMPL(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, NvU32 offset); - -#ifdef __nvoc_disp_inst_mem_h_disabled -static inline NV_STATUS instmemFreeContextDma(OBJGPU *pGpu, struct DisplayInstanceMemory *pInstMem, NvU32 offset) { - NV_ASSERT_FAILED_PRECOMP("DisplayInstanceMemory was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_disp_inst_mem_h_disabled -#define instmemFreeContextDma(pGpu, pInstMem, offset) instmemFreeContextDma_IMPL(pGpu, pInstMem, offset) -#endif //__nvoc_disp_inst_mem_h_disabled - #undef PRIVATE_FIELD @@ -370,4 +348,5 @@ static inline NV_STATUS instmemFreeContextDma(OBJGPU *pGpu, struct DisplayInstan #ifdef __cplusplus } // extern "C" #endif + #endif // _G_DISP_INST_MEM_NVOC_H_ diff --git a/src/nvidia/generated/g_disp_objs_nvoc.c b/src/nvidia/generated/g_disp_objs_nvoc.c index e3f0e9d39c..c8fa41b62b 100644 --- a/src/nvidia/generated/g_disp_objs_nvoc.c +++ b/src/nvidia/generated/g_disp_objs_nvoc.c @@ -2579,12 +2579,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm #endif }, { /* [2] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdSystemGetVblankCounter_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, /*accessRight=*/0x0u, /*methodId=*/ 0x730109u, /*paramSize=*/ sizeof(NV0073_CTRL_SYSTEM_GET_VBLANK_COUNTER_PARAMS), @@ -4449,7 +4449,7 @@ NV_STATUS __nvoc_ctor_DispCommon(DispCommon *pThis, RmHalspecOwner *pRmhalspecow static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) { PORT_UNREFERENCED_VARIABLE(pThis); -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__dispcmnCtrlCmdSystemGetVblankCounter__ = &dispcmnCtrlCmdSystemGetVblankCounter_IMPL; #endif diff --git a/src/nvidia/generated/g_disp_objs_nvoc.h b/src/nvidia/generated/g_disp_objs_nvoc.h index 7a407ca2e5..4952c8ec23 100644 --- a/src/nvidia/generated/g_disp_objs_nvoc.h +++ b/src/nvidia/generated/g_disp_objs_nvoc.h @@ -47,17 +47,6 @@ extern "C" { #include "gpu/gpu_halspec.h" -/* - * On T234, RM is in kernel mode, so when RM is running in kernel mode it - * does not allow usermode clients like MODs to call control calls that are - * marked as KERNEL_PRIVILEGED. - * So defining new macro DISPLAY_PRIVILEGED(i.e PRIVILEGED) for Tegra and mark - * control calls needed by MODs with this so that MODs running as root can call - * these control calls. However keeping same privilege level for DGPUs which - * does not change the current behaviour. - */ -#define DISPLAY_PRIVILEGED KERNEL_PRIVILEGED - #include "ctrl/ctrl0073.h" #include "ctrl/ctrl5070/ctrl5070event.h" #include "ctrl/ctrl5070/ctrl5070or.h" @@ -2602,4 +2591,5 @@ struct DisplayApi *CliGetDispFromDispHandle(NvHandle hClient, NvHandle hDisp); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_DISP_OBJS_NVOC_H_ diff --git a/src/nvidia/generated/g_disp_sf_user_nvoc.h b/src/nvidia/generated/g_disp_sf_user_nvoc.h index 8878a8f043..275e88d969 100644 --- a/src/nvidia/generated/g_disp_sf_user_nvoc.h +++ b/src/nvidia/generated/g_disp_sf_user_nvoc.h @@ -255,4 +255,5 @@ NV_STATUS dispsfConstruct_IMPL(struct DispSfUser *arg_pDispSfUser, struct CALL_C #ifdef __cplusplus } // extern "C" #endif + #endif // _G_DISP_SF_USER_NVOC_H_ diff --git a/src/nvidia/generated/g_dispsw_nvoc.h b/src/nvidia/generated/g_dispsw_nvoc.h index 8e9a7bd7bd..8b0f0c8fe1 100644 --- a/src/nvidia/generated/g_dispsw_nvoc.h +++ b/src/nvidia/generated/g_dispsw_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -99,8 +99,7 @@ NV_STATUS dispswReleaseSemaphoreAndNotifierFill(struct OBJGPU *pGpu, NvU32 releasevalue, NvU32 flags, NvU32 completionStatus, - struct RsClient *pClient, - NvHandle hEvent); + struct Device *pDevice); /*! * RM internal class representing GF100_DISP_SW @@ -375,4 +374,5 @@ void dispswDestruct_IMPL(struct DispSwObject *pDispSw); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_DISPSW_NVOC_H_ diff --git a/src/nvidia/generated/g_egm_mem_nvoc.c b/src/nvidia/generated/g_egm_mem_nvoc.c index ad97458e35..284d4b967d 100644 --- a/src/nvidia/generated/g_egm_mem_nvoc.c +++ b/src/nvidia/generated/g_egm_mem_nvoc.c @@ -118,6 +118,10 @@ static NV_STATUS __nvoc_thunk_Memory_egmmemGetMapAddrSpace(struct ExtendedGpuMem return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ExtendedGpuMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); } +static NvBool __nvoc_thunk_Memory_egmmemIsExportAllowed(struct ExtendedGpuMemory *pMemory) { + return memIsExportAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ExtendedGpuMemory_Memory.offset)); +} + static NvU32 __nvoc_thunk_RsResource_egmmemGetRefCount(struct ExtendedGpuMemory *pResource) { return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ExtendedGpuMemory_RsResource.offset)); } @@ -248,6 +252,8 @@ static void __nvoc_init_funcTable_ExtendedGpuMemory_1(ExtendedGpuMemory *pThis) pThis->__egmmemGetMapAddrSpace__ = &__nvoc_thunk_Memory_egmmemGetMapAddrSpace; + pThis->__egmmemIsExportAllowed__ = &__nvoc_thunk_Memory_egmmemIsExportAllowed; + pThis->__egmmemGetRefCount__ = &__nvoc_thunk_RsResource_egmmemGetRefCount; pThis->__egmmemAddAdditionalDependants__ = &__nvoc_thunk_RsResource_egmmemAddAdditionalDependants; diff --git a/src/nvidia/generated/g_egm_mem_nvoc.h b/src/nvidia/generated/g_egm_mem_nvoc.h index b9a5cc6eda..eb5aed7e21 100644 --- a/src/nvidia/generated/g_egm_mem_nvoc.h +++ b/src/nvidia/generated/g_egm_mem_nvoc.h @@ -61,6 +61,7 @@ struct ExtendedGpuMemory { NvBool (*__egmmemShareCallback__)(struct ExtendedGpuMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__egmmemMapTo__)(struct ExtendedGpuMemory *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__egmmemGetMapAddrSpace__)(struct ExtendedGpuMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvBool (*__egmmemIsExportAllowed__)(struct ExtendedGpuMemory *); NvU32 (*__egmmemGetRefCount__)(struct ExtendedGpuMemory *); void (*__egmmemAddAdditionalDependants__)(struct RsClient *, struct ExtendedGpuMemory *, RsResourceRef *); NV_STATUS (*__egmmemControl_Prologue__)(struct ExtendedGpuMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -116,6 +117,7 @@ NV_STATUS __nvoc_objCreate_ExtendedGpuMemory(ExtendedGpuMemory**, Dynamic*, NvU3 #define egmmemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) egmmemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define egmmemMapTo(pResource, pParams) egmmemMapTo_DISPATCH(pResource, pParams) #define egmmemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) egmmemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define egmmemIsExportAllowed(pMemory) egmmemIsExportAllowed_DISPATCH(pMemory) #define egmmemGetRefCount(pResource) egmmemGetRefCount_DISPATCH(pResource) #define egmmemAddAdditionalDependants(pClient, pResource, pReference) egmmemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define egmmemControl_Prologue(pResource, pCallContext, pParams) egmmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) @@ -153,6 +155,10 @@ static inline NV_STATUS egmmemGetMapAddrSpace_DISPATCH(struct ExtendedGpuMemory return pMemory->__egmmemGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); } +static inline NvBool egmmemIsExportAllowed_DISPATCH(struct ExtendedGpuMemory *pMemory) { + return pMemory->__egmmemIsExportAllowed__(pMemory); +} + static inline NvU32 egmmemGetRefCount_DISPATCH(struct ExtendedGpuMemory *pResource) { return pResource->__egmmemGetRefCount__(pResource); } @@ -254,4 +260,5 @@ NV_STATUS egmmemAllocResources(OBJGPU *pGpu, struct MemoryManager *pMemoryManage #ifdef __cplusplus } // extern "C" #endif + #endif // _G_EGM_MEM_NVOC_H_ diff --git a/src/nvidia/generated/g_eng_desc_nvoc.h b/src/nvidia/generated/g_eng_desc_nvoc.h index a311f40563..4d1e65d50b 100644 --- a/src/nvidia/generated/g_eng_desc_nvoc.h +++ b/src/nvidia/generated/g_eng_desc_nvoc.h @@ -1449,7 +1449,6 @@ typedef struct KernelCcu KernelCcu; #define ENG_GSP MKENGDESC(classId(Gsp), 0) #define ENG_FSP MKENGDESC(classId(OBJFSP), 0) #define ENG_KERNEL_FSP MKENGDESC(classId(KernelFsp), 0) -#define ENG_OFA MKENGDESC(classId(OBJOFA), 0) #define ENG_KERNEL_GSP MKENGDESC(classId(KernelGsp), 0) #define ENG_KERNEL_SEC2 MKENGDESC(classId(KernelSec2), 0) #define ENG_DISPMACRO MKENGDESC(classId(OBJDISPMACRO), 0) @@ -1524,9 +1523,15 @@ typedef struct KernelCcu KernelCcu; #define IS_KERNEL_IOCTRL(engDesc) (ENGDESC_FIELD(engDesc, _CLASS) == classId(KernelIoctrl)) #define GET_KERNEL_IOCTRL_IDX(engDesc) ENGDESC_FIELD(engDesc, _INST) +// Indexed OFA engine tag reference +#define ENG_OFA(x) MKENGDESC(classId(OBJOFA), x) +#define ENG_OFA__SIZE_1 1 +#define IS_OFA(engDesc) (ENGDESC_FIELD(engDesc, _CLASS) == classId(OBJOFA)) +#define GET_OFA_IDX(engDesc) ENGDESC_FIELD(engDesc, _INST) #endif // _ENG_DESC_H_ #ifdef __cplusplus } // extern "C" #endif + #endif // _G_ENG_DESC_NVOC_H_ diff --git a/src/nvidia/generated/g_eng_state_nvoc.h b/src/nvidia/generated/g_eng_state_nvoc.h index 09d1ba7178..72d5f8c45b 100644 --- a/src/nvidia/generated/g_eng_state_nvoc.h +++ b/src/nvidia/generated/g_eng_state_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -73,6 +73,15 @@ typedef struct ENGSTATE_TRANSITION_DATA NvU64 transitionStartTimeNs; } ENGSTATE_TRANSITION_DATA; +// Engine status for each state +typedef struct ENGSTATE_STATUS +{ + NV_STATUS engStatus; +#if NV_PRINTF_STRINGS_ALLOWED + char name[100]; +#endif +} ENGSTATE_STATUS; + typedef struct OBJENGSTATE *POBJENGSTATE; #define ENG_GET_FIFO(p) (engstateGetFifo(staticCast((p), OBJENGSTATE))) @@ -112,6 +121,7 @@ struct OBJENGSTATE { struct OBJGPU *pGpu; ENGSTATE_STATE currentState; ENGSTATE_STATS stats[11]; + ENGSTATE_STATUS status[11]; char name[100]; }; @@ -274,6 +284,16 @@ static inline void engstateLogStateTransitionPost(struct OBJENGSTATE *arg0, ENGS #define engstateLogStateTransitionPost(arg0, arg1, arg2) engstateLogStateTransitionPost_IMPL(arg0, arg1, arg2) #endif //__nvoc_eng_state_h_disabled +void engstateLogStateStatus_IMPL(struct OBJENGSTATE *arg0, ENGSTATE_STATE arg1, NV_STATUS status); + +#ifdef __nvoc_eng_state_h_disabled +static inline void engstateLogStateStatus(struct OBJENGSTATE *arg0, ENGSTATE_STATE arg1, NV_STATUS status) { + NV_ASSERT_FAILED_PRECOMP("OBJENGSTATE was disabled!"); +} +#else //__nvoc_eng_state_h_disabled +#define engstateLogStateStatus(arg0, arg1, status) engstateLogStateStatus_IMPL(arg0, arg1, status) +#endif //__nvoc_eng_state_h_disabled + const char *engstateGetName_IMPL(struct OBJENGSTATE *arg0); #ifdef __nvoc_eng_state_h_disabled @@ -342,4 +362,5 @@ static inline struct OBJFIFO *engstateGetFifo(POBJENGSTATE pEngstate) { #ifdef __cplusplus } // extern "C" #endif + #endif // _G_ENG_STATE_NVOC_H_ diff --git a/src/nvidia/generated/g_event_buffer_nvoc.h b/src/nvidia/generated/g_event_buffer_nvoc.h index b82b398245..545d77172f 100644 --- a/src/nvidia/generated/g_event_buffer_nvoc.h +++ b/src/nvidia/generated/g_event_buffer_nvoc.h @@ -305,4 +305,5 @@ NV_STATUS eventBufferAdd(struct EventBuffer *pEventBuffer, void* pEventData, NvU #ifdef __cplusplus } // extern "C" #endif + #endif // _G_EVENT_BUFFER_NVOC_H_ diff --git a/src/nvidia/generated/g_event_nvoc.h b/src/nvidia/generated/g_event_nvoc.h index cff1aa55de..098ca2d670 100644 --- a/src/nvidia/generated/g_event_nvoc.h +++ b/src/nvidia/generated/g_event_nvoc.h @@ -560,4 +560,5 @@ void gpuEngineEventNotificationListDestroy(OBJGPU *, GpuEngineEventNotifica #ifdef __cplusplus } // extern "C" #endif + #endif // _G_EVENT_NVOC_H_ diff --git a/src/nvidia/generated/g_fabric_nvoc.h b/src/nvidia/generated/g_fabric_nvoc.h index 8727dce4f9..5cda67c475 100644 --- a/src/nvidia/generated/g_fabric_nvoc.h +++ b/src/nvidia/generated/g_fabric_nvoc.h @@ -70,10 +70,6 @@ MAKE_MULTIMAP(FabricCache, FabricCacheEntry); #include "nvlink_inband_msg.h" -NV_STATUS fabricInitInbandMsgHdr(nvlink_inband_msg_header_t *pMsgHdr, - NvU32 type, - NvU32 len); - void fabricMulticastWaitOnTeamCleanupCallback(void *pCbData); // @@ -241,4 +237,5 @@ static inline void *fabricMulticastCleanupCacheGetUnderLock(struct Fabric *pFabr #ifdef __cplusplus } // extern "C" #endif + #endif // _G_FABRIC_NVOC_H_ diff --git a/src/nvidia/generated/g_fabric_vaspace_nvoc.c b/src/nvidia/generated/g_fabric_vaspace_nvoc.c index 19c0e893f2..1ecfc0ed4e 100644 --- a/src/nvidia/generated/g_fabric_vaspace_nvoc.c +++ b/src/nvidia/generated/g_fabric_vaspace_nvoc.c @@ -114,10 +114,6 @@ static NvBool __nvoc_thunk_OBJVASPACE_fabricvaspaceIsExternallyOwned(struct FABR return vaspaceIsExternallyOwned((struct OBJVASPACE *)(((unsigned char *)pVAS) + __nvoc_rtti_FABRIC_VASPACE_OBJVASPACE.offset)); } -static NvBool __nvoc_thunk_OBJVASPACE_fabricvaspaceIsInternalVaRestricted(struct FABRIC_VASPACE *pVAS) { - return vaspaceIsInternalVaRestricted((struct OBJVASPACE *)(((unsigned char *)pVAS) + __nvoc_rtti_FABRIC_VASPACE_OBJVASPACE.offset)); -} - static NvU32 __nvoc_thunk_OBJVASPACE_fabricvaspaceGetFlags(struct FABRIC_VASPACE *pVAS) { return vaspaceGetFlags((struct OBJVASPACE *)(((unsigned char *)pVAS) + __nvoc_rtti_FABRIC_VASPACE_OBJVASPACE.offset)); } @@ -182,8 +178,8 @@ static NV_STATUS __nvoc_thunk_OBJVASPACE_fabricvaspaceGetPageTableInfo(struct FA return vaspaceGetPageTableInfo((struct OBJVASPACE *)(((unsigned char *)pVAS) + __nvoc_rtti_FABRIC_VASPACE_OBJVASPACE.offset), pParams); } -static NV_STATUS __nvoc_thunk_OBJVASPACE_fabricvaspaceReserveMempool(struct FABRIC_VASPACE *pVAS, struct OBJGPU *pGpu, NvHandle hClient, NvU64 size, NvU64 pageSizeLockMask, NvU32 flags) { - return vaspaceReserveMempool((struct OBJVASPACE *)(((unsigned char *)pVAS) + __nvoc_rtti_FABRIC_VASPACE_OBJVASPACE.offset), pGpu, hClient, size, pageSizeLockMask, flags); +static NV_STATUS __nvoc_thunk_OBJVASPACE_fabricvaspaceReserveMempool(struct FABRIC_VASPACE *pVAS, struct OBJGPU *pGpu, struct Device *pDevice, NvU64 size, NvU64 pageSizeLockMask, NvU32 flags) { + return vaspaceReserveMempool((struct OBJVASPACE *)(((unsigned char *)pVAS) + __nvoc_rtti_FABRIC_VASPACE_OBJVASPACE.offset), pGpu, pDevice, size, pageSizeLockMask, flags); } const struct NVOC_EXPORT_INFO __nvoc_export_info_FABRIC_VASPACE = @@ -264,8 +260,6 @@ static void __nvoc_init_funcTable_FABRIC_VASPACE_1(FABRIC_VASPACE *pThis) { pThis->__fabricvaspaceIsExternallyOwned__ = &__nvoc_thunk_OBJVASPACE_fabricvaspaceIsExternallyOwned; - pThis->__fabricvaspaceIsInternalVaRestricted__ = &__nvoc_thunk_OBJVASPACE_fabricvaspaceIsInternalVaRestricted; - pThis->__fabricvaspaceGetFlags__ = &__nvoc_thunk_OBJVASPACE_fabricvaspaceGetFlags; pThis->__fabricvaspaceIsAtsEnabled__ = &__nvoc_thunk_OBJVASPACE_fabricvaspaceIsAtsEnabled; diff --git a/src/nvidia/generated/g_fabric_vaspace_nvoc.h b/src/nvidia/generated/g_fabric_vaspace_nvoc.h index 5aee210e9f..97a51e9a3c 100644 --- a/src/nvidia/generated/g_fabric_vaspace_nvoc.h +++ b/src/nvidia/generated/g_fabric_vaspace_nvoc.h @@ -90,7 +90,6 @@ struct FABRIC_VASPACE { void (*__fabricvaspaceInvalidateTlb__)(struct FABRIC_VASPACE *, struct OBJGPU *, VAS_PTE_UPDATE_TYPE); NvBool (*__fabricvaspaceIsMirrored__)(struct FABRIC_VASPACE *); NvBool (*__fabricvaspaceIsExternallyOwned__)(struct FABRIC_VASPACE *); - NvBool (*__fabricvaspaceIsInternalVaRestricted__)(struct FABRIC_VASPACE *); NvU32 (*__fabricvaspaceGetFlags__)(struct FABRIC_VASPACE *); NvBool (*__fabricvaspaceIsAtsEnabled__)(struct FABRIC_VASPACE *); NvU64 (*__fabricvaspaceGetBigPageSize__)(struct FABRIC_VASPACE *); @@ -107,7 +106,7 @@ struct FABRIC_VASPACE { NV_STATUS (*__fabricvaspaceFreeV2__)(struct FABRIC_VASPACE *, NvU64, NvU64 *); NV_STATUS (*__fabricvaspaceGetPasid__)(struct FABRIC_VASPACE *, NvU32 *); NV_STATUS (*__fabricvaspaceGetPageTableInfo__)(struct FABRIC_VASPACE *, NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS *); - NV_STATUS (*__fabricvaspaceReserveMempool__)(struct FABRIC_VASPACE *, struct OBJGPU *, NvHandle, NvU64, NvU64, NvU32); + NV_STATUS (*__fabricvaspaceReserveMempool__)(struct FABRIC_VASPACE *, struct OBJGPU *, struct Device *, NvU64, NvU64, NvU32); struct OBJVASPACE *pGVAS; NvU32 flags; NvHandle hClient; @@ -161,7 +160,6 @@ NV_STATUS __nvoc_objCreate_FABRIC_VASPACE(FABRIC_VASPACE**, Dynamic*, NvU32); #define fabricvaspaceInvalidateTlb(pFabricVAS, pGpu, type) fabricvaspaceInvalidateTlb_DISPATCH(pFabricVAS, pGpu, type) #define fabricvaspaceIsMirrored(pVAS) fabricvaspaceIsMirrored_DISPATCH(pVAS) #define fabricvaspaceIsExternallyOwned(pVAS) fabricvaspaceIsExternallyOwned_DISPATCH(pVAS) -#define fabricvaspaceIsInternalVaRestricted(pVAS) fabricvaspaceIsInternalVaRestricted_DISPATCH(pVAS) #define fabricvaspaceGetFlags(pVAS) fabricvaspaceGetFlags_DISPATCH(pVAS) #define fabricvaspaceIsAtsEnabled(pVAS) fabricvaspaceIsAtsEnabled_DISPATCH(pVAS) #define fabricvaspaceGetBigPageSize(pVAS) fabricvaspaceGetBigPageSize_DISPATCH(pVAS) @@ -178,7 +176,7 @@ NV_STATUS __nvoc_objCreate_FABRIC_VASPACE(FABRIC_VASPACE**, Dynamic*, NvU32); #define fabricvaspaceFreeV2(pVAS, vAddr, pSize) fabricvaspaceFreeV2_DISPATCH(pVAS, vAddr, pSize) #define fabricvaspaceGetPasid(pVAS, pPasid) fabricvaspaceGetPasid_DISPATCH(pVAS, pPasid) #define fabricvaspaceGetPageTableInfo(pVAS, pParams) fabricvaspaceGetPageTableInfo_DISPATCH(pVAS, pParams) -#define fabricvaspaceReserveMempool(pVAS, pGpu, hClient, size, pageSizeLockMask, flags) fabricvaspaceReserveMempool_DISPATCH(pVAS, pGpu, hClient, size, pageSizeLockMask, flags) +#define fabricvaspaceReserveMempool(pVAS, pGpu, pDevice, size, pageSizeLockMask, flags) fabricvaspaceReserveMempool_DISPATCH(pVAS, pGpu, pDevice, size, pageSizeLockMask, flags) NV_STATUS fabricvaspaceConstruct__IMPL(struct FABRIC_VASPACE *pFabricVAS, NvU32 classId, NvU32 vaspaceId, NvU64 vaStart, NvU64 vaLimit, NvU64 vaStartInternal, NvU64 vaLimitInternal, NvU32 flags); static inline NV_STATUS fabricvaspaceConstruct__DISPATCH(struct FABRIC_VASPACE *pFabricVAS, NvU32 classId, NvU32 vaspaceId, NvU64 vaStart, NvU64 vaLimit, NvU64 vaStartInternal, NvU64 vaLimitInternal, NvU32 flags) { @@ -247,10 +245,6 @@ static inline NvBool fabricvaspaceIsExternallyOwned_DISPATCH(struct FABRIC_VASPA return pVAS->__fabricvaspaceIsExternallyOwned__(pVAS); } -static inline NvBool fabricvaspaceIsInternalVaRestricted_DISPATCH(struct FABRIC_VASPACE *pVAS) { - return pVAS->__fabricvaspaceIsInternalVaRestricted__(pVAS); -} - static inline NvU32 fabricvaspaceGetFlags_DISPATCH(struct FABRIC_VASPACE *pVAS) { return pVAS->__fabricvaspaceGetFlags__(pVAS); } @@ -315,8 +309,8 @@ static inline NV_STATUS fabricvaspaceGetPageTableInfo_DISPATCH(struct FABRIC_VAS return pVAS->__fabricvaspaceGetPageTableInfo__(pVAS, pParams); } -static inline NV_STATUS fabricvaspaceReserveMempool_DISPATCH(struct FABRIC_VASPACE *pVAS, struct OBJGPU *pGpu, NvHandle hClient, NvU64 size, NvU64 pageSizeLockMask, NvU32 flags) { - return pVAS->__fabricvaspaceReserveMempool__(pVAS, pGpu, hClient, size, pageSizeLockMask, flags); +static inline NV_STATUS fabricvaspaceReserveMempool_DISPATCH(struct FABRIC_VASPACE *pVAS, struct OBJGPU *pGpu, struct Device *pDevice, NvU64 size, NvU64 pageSizeLockMask, NvU32 flags) { + return pVAS->__fabricvaspaceReserveMempool__(pVAS, pGpu, pDevice, size, pageSizeLockMask, flags); } static inline NvU64 fabricvaspaceGetUCFlaStart(struct FABRIC_VASPACE *pFabricVAS) { @@ -487,4 +481,5 @@ static inline NvBool fabricvaspaceIsInUse(struct FABRIC_VASPACE *pFabricVAS) { #ifdef __cplusplus } // extern "C" #endif + #endif // _G_FABRIC_VASPACE_NVOC_H_ diff --git a/src/nvidia/generated/g_fbsr_nvoc.c b/src/nvidia/generated/g_fbsr_nvoc.c index c0d8ba2d77..ef154762a7 100644 --- a/src/nvidia/generated/g_fbsr_nvoc.c +++ b/src/nvidia/generated/g_fbsr_nvoc.c @@ -70,16 +70,16 @@ void __nvoc_dtor_OBJFBSR(OBJFBSR *pThis) { } void __nvoc_init_dataField_OBJFBSR(OBJFBSR *pThis, RmHalspecOwner *pRmhalspecowner) { - RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; - const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; ChipHal *chipHal = &pRmhalspecowner->chipHal; const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; + RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; + const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; PORT_UNREFERENCED_VARIABLE(pThis); PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); - PORT_UNREFERENCED_VARIABLE(rmVariantHal); - PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); PORT_UNREFERENCED_VARIABLE(chipHal); PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); + PORT_UNREFERENCED_VARIABLE(rmVariantHal); + PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); } NV_STATUS __nvoc_ctor_Object(Object* ); @@ -97,16 +97,16 @@ NV_STATUS __nvoc_ctor_OBJFBSR(OBJFBSR *pThis, RmHalspecOwner *pRmhalspecowner) { } static void __nvoc_init_funcTable_OBJFBSR_1(OBJFBSR *pThis, RmHalspecOwner *pRmhalspecowner) { - RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; - const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; ChipHal *chipHal = &pRmhalspecowner->chipHal; const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; + RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; + const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; PORT_UNREFERENCED_VARIABLE(pThis); PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); - PORT_UNREFERENCED_VARIABLE(rmVariantHal); - PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); PORT_UNREFERENCED_VARIABLE(chipHal); PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); + PORT_UNREFERENCED_VARIABLE(rmVariantHal); + PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); // Hal function -- fbsrBegin if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x100003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GH100 */ diff --git a/src/nvidia/generated/g_fbsr_nvoc.h b/src/nvidia/generated/g_fbsr_nvoc.h index 2472a65b16..477749c6df 100644 --- a/src/nvidia/generated/g_fbsr_nvoc.h +++ b/src/nvidia/generated/g_fbsr_nvoc.h @@ -161,38 +161,6 @@ NV_STATUS __nvoc_objCreate_OBJFBSR(OBJFBSR**, Dynamic*, NvU32); #define fbsrEnd_HAL(pGpu, pFbsr) fbsrEnd_DISPATCH(pGpu, pFbsr) #define fbsrSendMemsysProgramRawCompressionMode(pGpu, pFbsr, bRawMode) fbsrSendMemsysProgramRawCompressionMode_DISPATCH(pGpu, pFbsr, bRawMode) #define fbsrSendMemsysProgramRawCompressionMode_HAL(pGpu, pFbsr, bRawMode) fbsrSendMemsysProgramRawCompressionMode_DISPATCH(pGpu, pFbsr, bRawMode) -static inline NV_STATUS fbsrCreateChannelForCopy_46f6a7(struct OBJGPU *pGpu, struct OBJFBSR *pFbsr) { - return NV_ERR_NOT_SUPPORTED; -} - - -#ifdef __nvoc_fbsr_h_disabled -static inline NV_STATUS fbsrCreateChannelForCopy(struct OBJGPU *pGpu, struct OBJFBSR *pFbsr) { - NV_ASSERT_FAILED_PRECOMP("OBJFBSR was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_fbsr_h_disabled -#define fbsrCreateChannelForCopy(pGpu, pFbsr) fbsrCreateChannelForCopy_46f6a7(pGpu, pFbsr) -#endif //__nvoc_fbsr_h_disabled - -#define fbsrCreateChannelForCopy_HAL(pGpu, pFbsr) fbsrCreateChannelForCopy(pGpu, pFbsr) - -static inline NV_STATUS fbsrDestroyChannelForCopy_46f6a7(struct OBJGPU *pGpu, struct OBJFBSR *pFbsr) { - return NV_ERR_NOT_SUPPORTED; -} - - -#ifdef __nvoc_fbsr_h_disabled -static inline NV_STATUS fbsrDestroyChannelForCopy(struct OBJGPU *pGpu, struct OBJFBSR *pFbsr) { - NV_ASSERT_FAILED_PRECOMP("OBJFBSR was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_fbsr_h_disabled -#define fbsrDestroyChannelForCopy(pGpu, pFbsr) fbsrDestroyChannelForCopy_46f6a7(pGpu, pFbsr) -#endif //__nvoc_fbsr_h_disabled - -#define fbsrDestroyChannelForCopy_HAL(pGpu, pFbsr) fbsrDestroyChannelForCopy(pGpu, pFbsr) - NV_STATUS fbsrInit_GM107(struct OBJGPU *pGpu, struct OBJFBSR *pFbsr); @@ -327,4 +295,5 @@ static inline void fbsrFreeReservedSysMemoryForPowerMgmt(struct OBJFBSR *pFbsr) #ifdef __cplusplus } // extern "C" #endif + #endif // _G_FBSR_NVOC_H_ diff --git a/src/nvidia/generated/g_fecs_event_list_nvoc.h b/src/nvidia/generated/g_fecs_event_list_nvoc.h index d14386741d..8294b64aa7 100644 --- a/src/nvidia/generated/g_fecs_event_list_nvoc.h +++ b/src/nvidia/generated/g_fecs_event_list_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -72,6 +72,18 @@ typedef struct EventBuffer EventBuffer; #endif /* __nvoc_class_id_EventBuffer */ +struct Subdevice; + +#ifndef __NVOC_CLASS_Subdevice_TYPEDEF__ +#define __NVOC_CLASS_Subdevice_TYPEDEF__ +typedef struct Subdevice Subdevice; +#endif /* __NVOC_CLASS_Subdevice_TYPEDEF__ */ + +#ifndef __nvoc_class_id_Subdevice +#define __nvoc_class_id_Subdevice 0x4b01b3 +#endif /* __nvoc_class_id_Subdevice */ + + // TODO move to cl90cdfecs.h #define NV_EVENT_BUFFER_INVALID_MIG_GI 0xFF @@ -130,7 +142,7 @@ NV_STATUS fecsAddBindpoint OBJGPU *pGpu, struct RmClient *pClient, RsResourceRef *pEventBufferRef, - NvHandle hNotifier, + struct Subdevice *pNotifier, NvBool bAllUsers, NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD levelOfDetail, NvU32 eventFilter, @@ -250,4 +262,5 @@ void fecsSetVgpuStagingBuffer #ifdef __cplusplus } // extern "C" #endif + #endif // _G_FECS_EVENT_LIST_NVOC_H_ diff --git a/src/nvidia/generated/g_fla_mem_nvoc.c b/src/nvidia/generated/g_fla_mem_nvoc.c index 4eb683b598..a15846913b 100644 --- a/src/nvidia/generated/g_fla_mem_nvoc.c +++ b/src/nvidia/generated/g_fla_mem_nvoc.c @@ -113,6 +113,10 @@ static NV_STATUS __nvoc_thunk_Memory_flamemGetMapAddrSpace(struct FlaMemory *pMe return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_FlaMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); } +static NvBool __nvoc_thunk_Memory_flamemIsExportAllowed(struct FlaMemory *pMemory) { + return memIsExportAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_FlaMemory_Memory.offset)); +} + static NvU32 __nvoc_thunk_RsResource_flamemGetRefCount(struct FlaMemory *pResource) { return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RsResource.offset)); } @@ -246,6 +250,8 @@ static void __nvoc_init_funcTable_FlaMemory_1(FlaMemory *pThis) { pThis->__flamemGetMapAddrSpace__ = &__nvoc_thunk_Memory_flamemGetMapAddrSpace; + pThis->__flamemIsExportAllowed__ = &__nvoc_thunk_Memory_flamemIsExportAllowed; + pThis->__flamemGetRefCount__ = &__nvoc_thunk_RsResource_flamemGetRefCount; pThis->__flamemAddAdditionalDependants__ = &__nvoc_thunk_RsResource_flamemAddAdditionalDependants; diff --git a/src/nvidia/generated/g_fla_mem_nvoc.h b/src/nvidia/generated/g_fla_mem_nvoc.h index 57ce040512..30f743b1c9 100644 --- a/src/nvidia/generated/g_fla_mem_nvoc.h +++ b/src/nvidia/generated/g_fla_mem_nvoc.h @@ -59,6 +59,7 @@ struct FlaMemory { NvBool (*__flamemShareCallback__)(struct FlaMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__flamemMapTo__)(struct FlaMemory *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__flamemGetMapAddrSpace__)(struct FlaMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvBool (*__flamemIsExportAllowed__)(struct FlaMemory *); NvU32 (*__flamemGetRefCount__)(struct FlaMemory *); void (*__flamemAddAdditionalDependants__)(struct RsClient *, struct FlaMemory *, RsResourceRef *); NV_STATUS (*__flamemControl_Prologue__)(struct FlaMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -118,6 +119,7 @@ NV_STATUS __nvoc_objCreate_FlaMemory(FlaMemory**, Dynamic*, NvU32, CALL_CONTEXT #define flamemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) flamemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define flamemMapTo(pResource, pParams) flamemMapTo_DISPATCH(pResource, pParams) #define flamemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) flamemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define flamemIsExportAllowed(pMemory) flamemIsExportAllowed_DISPATCH(pMemory) #define flamemGetRefCount(pResource) flamemGetRefCount_DISPATCH(pResource) #define flamemAddAdditionalDependants(pClient, pResource, pReference) flamemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define flamemControl_Prologue(pResource, pCallContext, pParams) flamemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) @@ -166,6 +168,10 @@ static inline NV_STATUS flamemGetMapAddrSpace_DISPATCH(struct FlaMemory *pMemory return pMemory->__flamemGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); } +static inline NvBool flamemIsExportAllowed_DISPATCH(struct FlaMemory *pMemory) { + return pMemory->__flamemIsExportAllowed__(pMemory); +} + static inline NvU32 flamemGetRefCount_DISPATCH(struct FlaMemory *pResource) { return pResource->__flamemGetRefCount__(pResource); } @@ -260,4 +266,5 @@ void flamemDestruct_IMPL(struct FlaMemory *pFlaMemory); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_FLA_MEM_NVOC_H_ diff --git a/src/nvidia/generated/g_fm_session_api_nvoc.c b/src/nvidia/generated/g_fm_session_api_nvoc.c index ce018ae695..e02f9452c8 100644 --- a/src/nvidia/generated/g_fm_session_api_nvoc.c +++ b/src/nvidia/generated/g_fm_session_api_nvoc.c @@ -21,10 +21,6 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResourceCommon; extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResource; -extern const struct NVOC_CLASS_DEF __nvoc_class_def_INotifier; - -extern const struct NVOC_CLASS_DEF __nvoc_class_def_Notifier; - void __nvoc_init_FmSessionApi(FmSessionApi*); void __nvoc_init_funcTable_FmSessionApi(FmSessionApi*); NV_STATUS __nvoc_ctor_FmSessionApi(FmSessionApi*, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); @@ -62,24 +58,10 @@ static const struct NVOC_RTTI __nvoc_rtti_FmSessionApi_RmResource = { /*offset=*/ NV_OFFSETOF(FmSessionApi, __nvoc_base_RmResource), }; -static const struct NVOC_RTTI __nvoc_rtti_FmSessionApi_INotifier = { - /*pClassDef=*/ &__nvoc_class_def_INotifier, - /*dtor=*/ &__nvoc_destructFromBase, - /*offset=*/ NV_OFFSETOF(FmSessionApi, __nvoc_base_Notifier.__nvoc_base_INotifier), -}; - -static const struct NVOC_RTTI __nvoc_rtti_FmSessionApi_Notifier = { - /*pClassDef=*/ &__nvoc_class_def_Notifier, - /*dtor=*/ &__nvoc_destructFromBase, - /*offset=*/ NV_OFFSETOF(FmSessionApi, __nvoc_base_Notifier), -}; - static const struct NVOC_CASTINFO __nvoc_castinfo_FmSessionApi = { - /*numRelatives=*/ 7, + /*numRelatives=*/ 5, /*relatives=*/ { &__nvoc_rtti_FmSessionApi_FmSessionApi, - &__nvoc_rtti_FmSessionApi_Notifier, - &__nvoc_rtti_FmSessionApi_INotifier, &__nvoc_rtti_FmSessionApi_RmResource, &__nvoc_rtti_FmSessionApi_RmResourceCommon, &__nvoc_rtti_FmSessionApi_RsResource, @@ -110,78 +92,58 @@ static NV_STATUS __nvoc_thunk_RmResource_fmsessionapiCheckMemInterUnmap(struct F return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_FmSessionApi_RmResource.offset), bSubdeviceHandleProvided); } -static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiMapTo(struct FmSessionApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pParams); +static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiControl(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControl((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pCallContext, pParams); } -static NvBool __nvoc_thunk_RmResource_fmsessionapiAccessCallback(struct FmSessionApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { - return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RmResource.offset), pInvokingClient, pAllocParams, accessRight); +static NV_STATUS __nvoc_thunk_RmResource_fmsessionapiGetMemInterMapParams(struct FmSessionApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_FmSessionApi_RmResource.offset), pParams); } -static void __nvoc_thunk_Notifier_fmsessionapiSetNotificationShare(struct FmSessionApi *pNotifier, struct NotifShare *pNotifShare) { - notifySetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_FmSessionApi_Notifier.offset), pNotifShare); +static NV_STATUS __nvoc_thunk_RmResource_fmsessionapiGetMemoryMappingDescriptor(struct FmSessionApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_FmSessionApi_RmResource.offset), ppMemDesc); } static NvU32 __nvoc_thunk_RsResource_fmsessionapiGetRefCount(struct FmSessionApi *pResource) { return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset)); } -static void __nvoc_thunk_RsResource_fmsessionapiAddAdditionalDependants(struct RsClient *pClient, struct FmSessionApi *pResource, RsResourceRef *pReference) { - resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pReference); +static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiControlFilter(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RmResource_fmsessionapiControl_Prologue(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RmResource.offset), pCallContext, pParams); +static void __nvoc_thunk_RsResource_fmsessionapiAddAdditionalDependants(struct RsClient *pClient, struct FmSessionApi *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pReference); } static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiUnmapFrom(struct FmSessionApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pParams); } -static void __nvoc_thunk_RmResource_fmsessionapiControl_Epilogue(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RmResource.offset), pCallContext, pParams); +static NV_STATUS __nvoc_thunk_RmResource_fmsessionapiControlSerialization_Prologue(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiControlLookup(struct FmSessionApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pParams, ppEntry); +static NV_STATUS __nvoc_thunk_RmResource_fmsessionapiControl_Prologue(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiControl(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControl((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pCallContext, pParams); +static NvBool __nvoc_thunk_RsResource_fmsessionapiCanCopy(struct FmSessionApi *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset)); } static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiUnmap(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pCallContext, pCpuMapping); } -static NV_STATUS __nvoc_thunk_RmResource_fmsessionapiGetMemInterMapParams(struct FmSessionApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_FmSessionApi_RmResource.offset), pParams); -} - -static NV_STATUS __nvoc_thunk_RmResource_fmsessionapiGetMemoryMappingDescriptor(struct FmSessionApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_FmSessionApi_RmResource.offset), ppMemDesc); -} - -static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiControlFilter(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pCallContext, pParams); -} - -static NV_STATUS __nvoc_thunk_Notifier_fmsessionapiUnregisterEvent(struct FmSessionApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { - return notifyUnregisterEvent((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_FmSessionApi_Notifier.offset), hNotifierClient, hNotifierResource, hEventClient, hEvent); -} - -static NV_STATUS __nvoc_thunk_RmResource_fmsessionapiControlSerialization_Prologue(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RmResource.offset), pCallContext, pParams); -} - -static NvBool __nvoc_thunk_RsResource_fmsessionapiCanCopy(struct FmSessionApi *pResource) { - return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset)); -} - static void __nvoc_thunk_RsResource_fmsessionapiPreDestruct(struct FmSessionApi *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset)); } +static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiMapTo(struct FmSessionApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pParams); +} + static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiIsDuplicate(struct FmSessionApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), hMemory, pDuplicate); } @@ -190,20 +152,20 @@ static void __nvoc_thunk_RmResource_fmsessionapiControlSerialization_Epilogue(st rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RmResource.offset), pCallContext, pParams); } -static PEVENTNOTIFICATION *__nvoc_thunk_Notifier_fmsessionapiGetNotificationListPtr(struct FmSessionApi *pNotifier) { - return notifyGetNotificationListPtr((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_FmSessionApi_Notifier.offset)); +static void __nvoc_thunk_RmResource_fmsessionapiControl_Epilogue(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RmResource.offset), pCallContext, pParams); } -static struct NotifShare *__nvoc_thunk_Notifier_fmsessionapiGetNotificationShare(struct FmSessionApi *pNotifier) { - return notifyGetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_FmSessionApi_Notifier.offset)); +static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiControlLookup(struct FmSessionApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pParams, ppEntry); } static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiMap(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { return resMap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pCallContext, pParams, pCpuMapping); } -static NV_STATUS __nvoc_thunk_Notifier_fmsessionapiGetOrAllocNotifShare(struct FmSessionApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { - return notifyGetOrAllocNotifShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_FmSessionApi_Notifier.offset), hNotifierClient, hNotifierResource, ppNotifShare); +static NvBool __nvoc_thunk_RmResource_fmsessionapiAccessCallback(struct FmSessionApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RmResource.offset), pInvokingClient, pAllocParams, accessRight); } #if !defined(NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG) @@ -252,11 +214,9 @@ const struct NVOC_EXPORT_INFO __nvoc_export_info_FmSessionApi = }; void __nvoc_dtor_RmResource(RmResource*); -void __nvoc_dtor_Notifier(Notifier*); void __nvoc_dtor_FmSessionApi(FmSessionApi *pThis) { __nvoc_fmsessionapiDestruct(pThis); __nvoc_dtor_RmResource(&pThis->__nvoc_base_RmResource); - __nvoc_dtor_Notifier(&pThis->__nvoc_base_Notifier); PORT_UNREFERENCED_VARIABLE(pThis); } @@ -265,13 +225,10 @@ void __nvoc_init_dataField_FmSessionApi(FmSessionApi *pThis) { } NV_STATUS __nvoc_ctor_RmResource(RmResource* , struct CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); -NV_STATUS __nvoc_ctor_Notifier(Notifier* , struct CALL_CONTEXT *); NV_STATUS __nvoc_ctor_FmSessionApi(FmSessionApi *pThis, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { NV_STATUS status = NV_OK; status = __nvoc_ctor_RmResource(&pThis->__nvoc_base_RmResource, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_ctor_FmSessionApi_fail_RmResource; - status = __nvoc_ctor_Notifier(&pThis->__nvoc_base_Notifier, arg_pCallContext); - if (status != NV_OK) goto __nvoc_ctor_FmSessionApi_fail_Notifier; __nvoc_init_dataField_FmSessionApi(pThis); status = __nvoc_fmsessionapiConstruct(pThis, arg_pCallContext, arg_pParams); @@ -279,8 +236,6 @@ NV_STATUS __nvoc_ctor_FmSessionApi(FmSessionApi *pThis, struct CALL_CONTEXT * ar goto __nvoc_ctor_FmSessionApi_exit; // Success __nvoc_ctor_FmSessionApi_fail__init: - __nvoc_dtor_Notifier(&pThis->__nvoc_base_Notifier); -__nvoc_ctor_FmSessionApi_fail_Notifier: __nvoc_dtor_RmResource(&pThis->__nvoc_base_RmResource); __nvoc_ctor_FmSessionApi_fail_RmResource: __nvoc_ctor_FmSessionApi_exit: @@ -303,53 +258,43 @@ static void __nvoc_init_funcTable_FmSessionApi_1(FmSessionApi *pThis) { pThis->__fmsessionapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_fmsessionapiCheckMemInterUnmap; - pThis->__fmsessionapiMapTo__ = &__nvoc_thunk_RsResource_fmsessionapiMapTo; + pThis->__fmsessionapiControl__ = &__nvoc_thunk_RsResource_fmsessionapiControl; - pThis->__fmsessionapiAccessCallback__ = &__nvoc_thunk_RmResource_fmsessionapiAccessCallback; + pThis->__fmsessionapiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_fmsessionapiGetMemInterMapParams; - pThis->__fmsessionapiSetNotificationShare__ = &__nvoc_thunk_Notifier_fmsessionapiSetNotificationShare; + pThis->__fmsessionapiGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_fmsessionapiGetMemoryMappingDescriptor; pThis->__fmsessionapiGetRefCount__ = &__nvoc_thunk_RsResource_fmsessionapiGetRefCount; - pThis->__fmsessionapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_fmsessionapiAddAdditionalDependants; + pThis->__fmsessionapiControlFilter__ = &__nvoc_thunk_RsResource_fmsessionapiControlFilter; - pThis->__fmsessionapiControl_Prologue__ = &__nvoc_thunk_RmResource_fmsessionapiControl_Prologue; + pThis->__fmsessionapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_fmsessionapiAddAdditionalDependants; pThis->__fmsessionapiUnmapFrom__ = &__nvoc_thunk_RsResource_fmsessionapiUnmapFrom; - pThis->__fmsessionapiControl_Epilogue__ = &__nvoc_thunk_RmResource_fmsessionapiControl_Epilogue; + pThis->__fmsessionapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_fmsessionapiControlSerialization_Prologue; - pThis->__fmsessionapiControlLookup__ = &__nvoc_thunk_RsResource_fmsessionapiControlLookup; + pThis->__fmsessionapiControl_Prologue__ = &__nvoc_thunk_RmResource_fmsessionapiControl_Prologue; - pThis->__fmsessionapiControl__ = &__nvoc_thunk_RsResource_fmsessionapiControl; + pThis->__fmsessionapiCanCopy__ = &__nvoc_thunk_RsResource_fmsessionapiCanCopy; pThis->__fmsessionapiUnmap__ = &__nvoc_thunk_RsResource_fmsessionapiUnmap; - pThis->__fmsessionapiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_fmsessionapiGetMemInterMapParams; - - pThis->__fmsessionapiGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_fmsessionapiGetMemoryMappingDescriptor; - - pThis->__fmsessionapiControlFilter__ = &__nvoc_thunk_RsResource_fmsessionapiControlFilter; - - pThis->__fmsessionapiUnregisterEvent__ = &__nvoc_thunk_Notifier_fmsessionapiUnregisterEvent; - - pThis->__fmsessionapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_fmsessionapiControlSerialization_Prologue; - - pThis->__fmsessionapiCanCopy__ = &__nvoc_thunk_RsResource_fmsessionapiCanCopy; - pThis->__fmsessionapiPreDestruct__ = &__nvoc_thunk_RsResource_fmsessionapiPreDestruct; + pThis->__fmsessionapiMapTo__ = &__nvoc_thunk_RsResource_fmsessionapiMapTo; + pThis->__fmsessionapiIsDuplicate__ = &__nvoc_thunk_RsResource_fmsessionapiIsDuplicate; pThis->__fmsessionapiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_fmsessionapiControlSerialization_Epilogue; - pThis->__fmsessionapiGetNotificationListPtr__ = &__nvoc_thunk_Notifier_fmsessionapiGetNotificationListPtr; + pThis->__fmsessionapiControl_Epilogue__ = &__nvoc_thunk_RmResource_fmsessionapiControl_Epilogue; - pThis->__fmsessionapiGetNotificationShare__ = &__nvoc_thunk_Notifier_fmsessionapiGetNotificationShare; + pThis->__fmsessionapiControlLookup__ = &__nvoc_thunk_RsResource_fmsessionapiControlLookup; pThis->__fmsessionapiMap__ = &__nvoc_thunk_RsResource_fmsessionapiMap; - pThis->__fmsessionapiGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_fmsessionapiGetOrAllocNotifShare; + pThis->__fmsessionapiAccessCallback__ = &__nvoc_thunk_RmResource_fmsessionapiAccessCallback; } void __nvoc_init_funcTable_FmSessionApi(FmSessionApi *pThis) { @@ -357,17 +302,13 @@ void __nvoc_init_funcTable_FmSessionApi(FmSessionApi *pThis) { } void __nvoc_init_RmResource(RmResource*); -void __nvoc_init_Notifier(Notifier*); void __nvoc_init_FmSessionApi(FmSessionApi *pThis) { pThis->__nvoc_pbase_FmSessionApi = pThis; pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object; pThis->__nvoc_pbase_RsResource = &pThis->__nvoc_base_RmResource.__nvoc_base_RsResource; pThis->__nvoc_pbase_RmResourceCommon = &pThis->__nvoc_base_RmResource.__nvoc_base_RmResourceCommon; pThis->__nvoc_pbase_RmResource = &pThis->__nvoc_base_RmResource; - pThis->__nvoc_pbase_INotifier = &pThis->__nvoc_base_Notifier.__nvoc_base_INotifier; - pThis->__nvoc_pbase_Notifier = &pThis->__nvoc_base_Notifier; __nvoc_init_RmResource(&pThis->__nvoc_base_RmResource); - __nvoc_init_Notifier(&pThis->__nvoc_base_Notifier); __nvoc_init_funcTable_FmSessionApi(pThis); } diff --git a/src/nvidia/generated/g_fm_session_api_nvoc.h b/src/nvidia/generated/g_fm_session_api_nvoc.h index 3afc8083f8..03a312a1a6 100644 --- a/src/nvidia/generated/g_fm_session_api_nvoc.h +++ b/src/nvidia/generated/g_fm_session_api_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -43,7 +43,6 @@ extern "C" { #include "rmapi/resource.h" #include "rmapi/event.h" - #include "ctrl/ctrl000f.h" // **************************************************************************** @@ -72,42 +71,34 @@ extern "C" { struct FmSessionApi { const struct NVOC_RTTI *__nvoc_rtti; struct RmResource __nvoc_base_RmResource; - struct Notifier __nvoc_base_Notifier; struct Object *__nvoc_pbase_Object; struct RsResource *__nvoc_pbase_RsResource; struct RmResourceCommon *__nvoc_pbase_RmResourceCommon; struct RmResource *__nvoc_pbase_RmResource; - struct INotifier *__nvoc_pbase_INotifier; - struct Notifier *__nvoc_pbase_Notifier; struct FmSessionApi *__nvoc_pbase_FmSessionApi; NV_STATUS (*__fmsessionapiCtrlCmdSetFmState__)(struct FmSessionApi *); NV_STATUS (*__fmsessionapiCtrlCmdClearFmState__)(struct FmSessionApi *); NvBool (*__fmsessionapiShareCallback__)(struct FmSessionApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__fmsessionapiCheckMemInterUnmap__)(struct FmSessionApi *, NvBool); - NV_STATUS (*__fmsessionapiMapTo__)(struct FmSessionApi *, RS_RES_MAP_TO_PARAMS *); - NvBool (*__fmsessionapiAccessCallback__)(struct FmSessionApi *, struct RsClient *, void *, RsAccessRight); - void (*__fmsessionapiSetNotificationShare__)(struct FmSessionApi *, struct NotifShare *); - NvU32 (*__fmsessionapiGetRefCount__)(struct FmSessionApi *); - void (*__fmsessionapiAddAdditionalDependants__)(struct RsClient *, struct FmSessionApi *, RsResourceRef *); - NV_STATUS (*__fmsessionapiControl_Prologue__)(struct FmSessionApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__fmsessionapiUnmapFrom__)(struct FmSessionApi *, RS_RES_UNMAP_FROM_PARAMS *); - void (*__fmsessionapiControl_Epilogue__)(struct FmSessionApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__fmsessionapiControlLookup__)(struct FmSessionApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__fmsessionapiControl__)(struct FmSessionApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__fmsessionapiUnmap__)(struct FmSessionApi *, struct CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__fmsessionapiGetMemInterMapParams__)(struct FmSessionApi *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__fmsessionapiGetMemoryMappingDescriptor__)(struct FmSessionApi *, struct MEMORY_DESCRIPTOR **); + NvU32 (*__fmsessionapiGetRefCount__)(struct FmSessionApi *); NV_STATUS (*__fmsessionapiControlFilter__)(struct FmSessionApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__fmsessionapiUnregisterEvent__)(struct FmSessionApi *, NvHandle, NvHandle, NvHandle, NvHandle); + void (*__fmsessionapiAddAdditionalDependants__)(struct RsClient *, struct FmSessionApi *, RsResourceRef *); + NV_STATUS (*__fmsessionapiUnmapFrom__)(struct FmSessionApi *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__fmsessionapiControlSerialization_Prologue__)(struct FmSessionApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__fmsessionapiControl_Prologue__)(struct FmSessionApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__fmsessionapiCanCopy__)(struct FmSessionApi *); + NV_STATUS (*__fmsessionapiUnmap__)(struct FmSessionApi *, struct CALL_CONTEXT *, RsCpuMapping *); void (*__fmsessionapiPreDestruct__)(struct FmSessionApi *); + NV_STATUS (*__fmsessionapiMapTo__)(struct FmSessionApi *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__fmsessionapiIsDuplicate__)(struct FmSessionApi *, NvHandle, NvBool *); void (*__fmsessionapiControlSerialization_Epilogue__)(struct FmSessionApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - PEVENTNOTIFICATION *(*__fmsessionapiGetNotificationListPtr__)(struct FmSessionApi *); - struct NotifShare *(*__fmsessionapiGetNotificationShare__)(struct FmSessionApi *); + void (*__fmsessionapiControl_Epilogue__)(struct FmSessionApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__fmsessionapiControlLookup__)(struct FmSessionApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__fmsessionapiMap__)(struct FmSessionApi *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); - NV_STATUS (*__fmsessionapiGetOrAllocNotifShare__)(struct FmSessionApi *, NvHandle, NvHandle, struct NotifShare **); + NvBool (*__fmsessionapiAccessCallback__)(struct FmSessionApi *, struct RsClient *, void *, RsAccessRight); NvU64 dupedCapDescriptor; }; @@ -143,30 +134,25 @@ NV_STATUS __nvoc_objCreate_FmSessionApi(FmSessionApi**, Dynamic*, NvU32, struct #define fmsessionapiCtrlCmdClearFmState(pFmSessionApi) fmsessionapiCtrlCmdClearFmState_DISPATCH(pFmSessionApi) #define fmsessionapiShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) fmsessionapiShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define fmsessionapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) fmsessionapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) -#define fmsessionapiMapTo(pResource, pParams) fmsessionapiMapTo_DISPATCH(pResource, pParams) -#define fmsessionapiAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) fmsessionapiAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) -#define fmsessionapiSetNotificationShare(pNotifier, pNotifShare) fmsessionapiSetNotificationShare_DISPATCH(pNotifier, pNotifShare) -#define fmsessionapiGetRefCount(pResource) fmsessionapiGetRefCount_DISPATCH(pResource) -#define fmsessionapiAddAdditionalDependants(pClient, pResource, pReference) fmsessionapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define fmsessionapiControl_Prologue(pResource, pCallContext, pParams) fmsessionapiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) -#define fmsessionapiUnmapFrom(pResource, pParams) fmsessionapiUnmapFrom_DISPATCH(pResource, pParams) -#define fmsessionapiControl_Epilogue(pResource, pCallContext, pParams) fmsessionapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define fmsessionapiControlLookup(pResource, pParams, ppEntry) fmsessionapiControlLookup_DISPATCH(pResource, pParams, ppEntry) #define fmsessionapiControl(pResource, pCallContext, pParams) fmsessionapiControl_DISPATCH(pResource, pCallContext, pParams) -#define fmsessionapiUnmap(pResource, pCallContext, pCpuMapping) fmsessionapiUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) #define fmsessionapiGetMemInterMapParams(pRmResource, pParams) fmsessionapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define fmsessionapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) fmsessionapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) +#define fmsessionapiGetRefCount(pResource) fmsessionapiGetRefCount_DISPATCH(pResource) #define fmsessionapiControlFilter(pResource, pCallContext, pParams) fmsessionapiControlFilter_DISPATCH(pResource, pCallContext, pParams) -#define fmsessionapiUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) fmsessionapiUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) +#define fmsessionapiAddAdditionalDependants(pClient, pResource, pReference) fmsessionapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define fmsessionapiUnmapFrom(pResource, pParams) fmsessionapiUnmapFrom_DISPATCH(pResource, pParams) #define fmsessionapiControlSerialization_Prologue(pResource, pCallContext, pParams) fmsessionapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define fmsessionapiControl_Prologue(pResource, pCallContext, pParams) fmsessionapiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define fmsessionapiCanCopy(pResource) fmsessionapiCanCopy_DISPATCH(pResource) +#define fmsessionapiUnmap(pResource, pCallContext, pCpuMapping) fmsessionapiUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) #define fmsessionapiPreDestruct(pResource) fmsessionapiPreDestruct_DISPATCH(pResource) +#define fmsessionapiMapTo(pResource, pParams) fmsessionapiMapTo_DISPATCH(pResource, pParams) #define fmsessionapiIsDuplicate(pResource, hMemory, pDuplicate) fmsessionapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define fmsessionapiControlSerialization_Epilogue(pResource, pCallContext, pParams) fmsessionapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define fmsessionapiGetNotificationListPtr(pNotifier) fmsessionapiGetNotificationListPtr_DISPATCH(pNotifier) -#define fmsessionapiGetNotificationShare(pNotifier) fmsessionapiGetNotificationShare_DISPATCH(pNotifier) +#define fmsessionapiControl_Epilogue(pResource, pCallContext, pParams) fmsessionapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define fmsessionapiControlLookup(pResource, pParams, ppEntry) fmsessionapiControlLookup_DISPATCH(pResource, pParams, ppEntry) #define fmsessionapiMap(pResource, pCallContext, pParams, pCpuMapping) fmsessionapiMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) -#define fmsessionapiGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) fmsessionapiGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) +#define fmsessionapiAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) fmsessionapiAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS fmsessionapiCtrlCmdSetFmState_IMPL(struct FmSessionApi *pFmSessionApi); static inline NV_STATUS fmsessionapiCtrlCmdSetFmState_DISPATCH(struct FmSessionApi *pFmSessionApi) { @@ -187,78 +173,58 @@ static inline NV_STATUS fmsessionapiCheckMemInterUnmap_DISPATCH(struct FmSession return pRmResource->__fmsessionapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); } -static inline NV_STATUS fmsessionapiMapTo_DISPATCH(struct FmSessionApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { - return pResource->__fmsessionapiMapTo__(pResource, pParams); +static inline NV_STATUS fmsessionapiControl_DISPATCH(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__fmsessionapiControl__(pResource, pCallContext, pParams); } -static inline NvBool fmsessionapiAccessCallback_DISPATCH(struct FmSessionApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { - return pResource->__fmsessionapiAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); +static inline NV_STATUS fmsessionapiGetMemInterMapParams_DISPATCH(struct FmSessionApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__fmsessionapiGetMemInterMapParams__(pRmResource, pParams); } -static inline void fmsessionapiSetNotificationShare_DISPATCH(struct FmSessionApi *pNotifier, struct NotifShare *pNotifShare) { - pNotifier->__fmsessionapiSetNotificationShare__(pNotifier, pNotifShare); +static inline NV_STATUS fmsessionapiGetMemoryMappingDescriptor_DISPATCH(struct FmSessionApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__fmsessionapiGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); } static inline NvU32 fmsessionapiGetRefCount_DISPATCH(struct FmSessionApi *pResource) { return pResource->__fmsessionapiGetRefCount__(pResource); } -static inline void fmsessionapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct FmSessionApi *pResource, RsResourceRef *pReference) { - pResource->__fmsessionapiAddAdditionalDependants__(pClient, pResource, pReference); +static inline NV_STATUS fmsessionapiControlFilter_DISPATCH(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__fmsessionapiControlFilter__(pResource, pCallContext, pParams); } -static inline NV_STATUS fmsessionapiControl_Prologue_DISPATCH(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__fmsessionapiControl_Prologue__(pResource, pCallContext, pParams); +static inline void fmsessionapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct FmSessionApi *pResource, RsResourceRef *pReference) { + pResource->__fmsessionapiAddAdditionalDependants__(pClient, pResource, pReference); } static inline NV_STATUS fmsessionapiUnmapFrom_DISPATCH(struct FmSessionApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { return pResource->__fmsessionapiUnmapFrom__(pResource, pParams); } -static inline void fmsessionapiControl_Epilogue_DISPATCH(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - pResource->__fmsessionapiControl_Epilogue__(pResource, pCallContext, pParams); +static inline NV_STATUS fmsessionapiControlSerialization_Prologue_DISPATCH(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__fmsessionapiControlSerialization_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS fmsessionapiControlLookup_DISPATCH(struct FmSessionApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__fmsessionapiControlLookup__(pResource, pParams, ppEntry); +static inline NV_STATUS fmsessionapiControl_Prologue_DISPATCH(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__fmsessionapiControl_Prologue__(pResource, pCallContext, pParams); } -static inline NV_STATUS fmsessionapiControl_DISPATCH(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__fmsessionapiControl__(pResource, pCallContext, pParams); +static inline NvBool fmsessionapiCanCopy_DISPATCH(struct FmSessionApi *pResource) { + return pResource->__fmsessionapiCanCopy__(pResource); } static inline NV_STATUS fmsessionapiUnmap_DISPATCH(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { return pResource->__fmsessionapiUnmap__(pResource, pCallContext, pCpuMapping); } -static inline NV_STATUS fmsessionapiGetMemInterMapParams_DISPATCH(struct FmSessionApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pRmResource->__fmsessionapiGetMemInterMapParams__(pRmResource, pParams); -} - -static inline NV_STATUS fmsessionapiGetMemoryMappingDescriptor_DISPATCH(struct FmSessionApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { - return pRmResource->__fmsessionapiGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); -} - -static inline NV_STATUS fmsessionapiControlFilter_DISPATCH(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__fmsessionapiControlFilter__(pResource, pCallContext, pParams); -} - -static inline NV_STATUS fmsessionapiUnregisterEvent_DISPATCH(struct FmSessionApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, NvHandle hEventClient, NvHandle hEvent) { - return pNotifier->__fmsessionapiUnregisterEvent__(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent); -} - -static inline NV_STATUS fmsessionapiControlSerialization_Prologue_DISPATCH(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { - return pResource->__fmsessionapiControlSerialization_Prologue__(pResource, pCallContext, pParams); -} - -static inline NvBool fmsessionapiCanCopy_DISPATCH(struct FmSessionApi *pResource) { - return pResource->__fmsessionapiCanCopy__(pResource); -} - static inline void fmsessionapiPreDestruct_DISPATCH(struct FmSessionApi *pResource) { pResource->__fmsessionapiPreDestruct__(pResource); } +static inline NV_STATUS fmsessionapiMapTo_DISPATCH(struct FmSessionApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__fmsessionapiMapTo__(pResource, pParams); +} + static inline NV_STATUS fmsessionapiIsDuplicate_DISPATCH(struct FmSessionApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__fmsessionapiIsDuplicate__(pResource, hMemory, pDuplicate); } @@ -267,20 +233,20 @@ static inline void fmsessionapiControlSerialization_Epilogue_DISPATCH(struct FmS pResource->__fmsessionapiControlSerialization_Epilogue__(pResource, pCallContext, pParams); } -static inline PEVENTNOTIFICATION *fmsessionapiGetNotificationListPtr_DISPATCH(struct FmSessionApi *pNotifier) { - return pNotifier->__fmsessionapiGetNotificationListPtr__(pNotifier); +static inline void fmsessionapiControl_Epilogue_DISPATCH(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__fmsessionapiControl_Epilogue__(pResource, pCallContext, pParams); } -static inline struct NotifShare *fmsessionapiGetNotificationShare_DISPATCH(struct FmSessionApi *pNotifier) { - return pNotifier->__fmsessionapiGetNotificationShare__(pNotifier); +static inline NV_STATUS fmsessionapiControlLookup_DISPATCH(struct FmSessionApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + return pResource->__fmsessionapiControlLookup__(pResource, pParams, ppEntry); } static inline NV_STATUS fmsessionapiMap_DISPATCH(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { return pResource->__fmsessionapiMap__(pResource, pCallContext, pParams, pCpuMapping); } -static inline NV_STATUS fmsessionapiGetOrAllocNotifShare_DISPATCH(struct FmSessionApi *pNotifier, NvHandle hNotifierClient, NvHandle hNotifierResource, struct NotifShare **ppNotifShare) { - return pNotifier->__fmsessionapiGetOrAllocNotifShare__(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare); +static inline NvBool fmsessionapiAccessCallback_DISPATCH(struct FmSessionApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return pResource->__fmsessionapiAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); } NV_STATUS fmsessionapiConstruct_IMPL(struct FmSessionApi *arg_pFmSessionApi, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); @@ -297,4 +263,5 @@ void fmsessionapiDestruct_IMPL(struct FmSessionApi *pFmSessionApi); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_FM_SESSION_API_NVOC_H_ diff --git a/src/nvidia/generated/g_generic_engine_nvoc.c b/src/nvidia/generated/g_generic_engine_nvoc.c index 8c05ba103d..feb297172b 100644 --- a/src/nvidia/generated/g_generic_engine_nvoc.c +++ b/src/nvidia/generated/g_generic_engine_nvoc.c @@ -227,6 +227,21 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_GenericE /*pClassInfo=*/ &(__nvoc_class_def_GenericEngineApi.classInfo), #if NV_PRINTF_STRINGS_ALLOWED /*func=*/ "genapiCtrlCmdMasterGetVirtualFunctionErrorContIntrMask" +#endif + }, + { /* [2] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x250u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) genapiCtrlCmdBBXGetLastFlushTime_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x250u) + /*flags=*/ 0x250u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x90e70113u, + /*paramSize=*/ sizeof(NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_GenericEngineApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "genapiCtrlCmdBBXGetLastFlushTime" #endif }, @@ -234,7 +249,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_GenericE const struct NVOC_EXPORT_INFO __nvoc_export_info_GenericEngineApi = { - /*numEntries=*/ 2, + /*numEntries=*/ 3, /*pExportEntries=*/ __nvoc_exported_method_def_GenericEngineApi }; @@ -285,6 +300,10 @@ static void __nvoc_init_funcTable_GenericEngineApi_1(GenericEngineApi *pThis) { pThis->__genapiCtrlCmdMasterGetVirtualFunctionErrorContIntrMask__ = &genapiCtrlCmdMasterGetVirtualFunctionErrorContIntrMask_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x250u) + pThis->__genapiCtrlCmdBBXGetLastFlushTime__ = &genapiCtrlCmdBBXGetLastFlushTime_IMPL; +#endif + pThis->__nvoc_base_GpuResource.__gpuresMap__ = &__nvoc_thunk_GenericEngineApi_gpuresMap; pThis->__nvoc_base_GpuResource.__gpuresGetMapAddrSpace__ = &__nvoc_thunk_GenericEngineApi_gpuresGetMapAddrSpace; diff --git a/src/nvidia/generated/g_generic_engine_nvoc.h b/src/nvidia/generated/g_generic_engine_nvoc.h index b3ac4bccb7..9cf3e8cf09 100644 --- a/src/nvidia/generated/g_generic_engine_nvoc.h +++ b/src/nvidia/generated/g_generic_engine_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2016-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -35,6 +35,7 @@ extern "C" { #include "gpu/gpu_resource.h" #include "ctrl/ctrl90e6.h" +#include "ctrl/ctrl90e7.h" #include "rmapi/resource.h" // for macro RMCTRL_EXPORT etc. /*! @@ -61,6 +62,7 @@ struct GenericEngineApi { NV_STATUS (*__genapiControl__)(struct GenericEngineApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__genapiCtrlCmdMasterGetErrorIntrOffsetMask__)(struct GenericEngineApi *, NV90E6_CTRL_MASTER_GET_ERROR_INTR_OFFSET_MASK_PARAMS *); NV_STATUS (*__genapiCtrlCmdMasterGetVirtualFunctionErrorContIntrMask__)(struct GenericEngineApi *, NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS *); + NV_STATUS (*__genapiCtrlCmdBBXGetLastFlushTime__)(struct GenericEngineApi *, NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS *); NvBool (*__genapiShareCallback__)(struct GenericEngineApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__genapiCheckMemInterUnmap__)(struct GenericEngineApi *, NvBool); NV_STATUS (*__genapiMapTo__)(struct GenericEngineApi *, RS_RES_MAP_TO_PARAMS *); @@ -118,6 +120,7 @@ NV_STATUS __nvoc_objCreate_GenericEngineApi(GenericEngineApi**, Dynamic*, NvU32, #define genapiControl(pGenericEngineApi, pCallContext, pParams) genapiControl_DISPATCH(pGenericEngineApi, pCallContext, pParams) #define genapiCtrlCmdMasterGetErrorIntrOffsetMask(pGenericEngineApi, pParams) genapiCtrlCmdMasterGetErrorIntrOffsetMask_DISPATCH(pGenericEngineApi, pParams) #define genapiCtrlCmdMasterGetVirtualFunctionErrorContIntrMask(pGenericEngineApi, pParams) genapiCtrlCmdMasterGetVirtualFunctionErrorContIntrMask_DISPATCH(pGenericEngineApi, pParams) +#define genapiCtrlCmdBBXGetLastFlushTime(pGenericEngineApi, pParams) genapiCtrlCmdBBXGetLastFlushTime_DISPATCH(pGenericEngineApi, pParams) #define genapiShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) genapiShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) #define genapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) genapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define genapiMapTo(pResource, pParams) genapiMapTo_DISPATCH(pResource, pParams) @@ -170,6 +173,12 @@ static inline NV_STATUS genapiCtrlCmdMasterGetVirtualFunctionErrorContIntrMask_D return pGenericEngineApi->__genapiCtrlCmdMasterGetVirtualFunctionErrorContIntrMask__(pGenericEngineApi, pParams); } +NV_STATUS genapiCtrlCmdBBXGetLastFlushTime_IMPL(struct GenericEngineApi *pGenericEngineApi, NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS *pParams); + +static inline NV_STATUS genapiCtrlCmdBBXGetLastFlushTime_DISPATCH(struct GenericEngineApi *pGenericEngineApi, NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS *pParams) { + return pGenericEngineApi->__genapiCtrlCmdBBXGetLastFlushTime__(pGenericEngineApi, pParams); +} + static inline NvBool genapiShareCallback_DISPATCH(struct GenericEngineApi *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { return pGpuResource->__genapiShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } @@ -272,4 +281,5 @@ void genapiDestruct_IMPL(struct GenericEngineApi *pGenericEngineApi); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_GENERIC_ENGINE_NVOC_H_ diff --git a/src/nvidia/generated/g_gpu_access_nvoc.h b/src/nvidia/generated/g_gpu_access_nvoc.h index 26e77e7155..10457ddcca 100644 --- a/src/nvidia/generated/g_gpu_access_nvoc.h +++ b/src/nvidia/generated/g_gpu_access_nvoc.h @@ -89,6 +89,9 @@ typedef union GPUHWREG GPUHWREG; #define REGISTER_FILTER_FLAGS_VIRTUAL (0) #define REGISTER_FILTER_FLAGS_READ_WRITE (REGISTER_FILTER_FLAGS_READ | REGISTER_FILTER_FLAGS_WRITE) +// Do not warn if attempting to add a filter on GSP [CORERM-5356] +#define REGISTER_FILTER_FLAGS_NO_GSP_WARNING (NVBIT(3)) + typedef struct REGISTER_FILTER REGISTER_FILTER; struct REGISTER_FILTER @@ -630,4 +633,5 @@ NV_STATUS swbcaprtConstruct_IMPL(struct SwBcAperture *arg_pAperture, struct IoAp #ifdef __cplusplus } // extern "C" #endif + #endif // _G_GPU_ACCESS_NVOC_H_ diff --git a/src/nvidia/generated/g_gpu_acct_nvoc.h b/src/nvidia/generated/g_gpu_acct_nvoc.h index a91f0e6ea0..96debcb13f 100644 --- a/src/nvidia/generated/g_gpu_acct_nvoc.h +++ b/src/nvidia/generated/g_gpu_acct_nvoc.h @@ -293,4 +293,5 @@ void gpuacctProcessGpuUtil(GPUACCT_GPU_INSTANCE_INFO *, NV2080_CTRL_PERF_GPUMON_ #ifdef __cplusplus } // extern "C" #endif + #endif // _G_GPU_ACCT_NVOC_H_ diff --git a/src/nvidia/generated/g_gpu_boost_mgr_nvoc.h b/src/nvidia/generated/g_gpu_boost_mgr_nvoc.h index ba8b620b9d..4e72d95358 100644 --- a/src/nvidia/generated/g_gpu_boost_mgr_nvoc.h +++ b/src/nvidia/generated/g_gpu_boost_mgr_nvoc.h @@ -263,4 +263,5 @@ static inline NvBool gpuboostmgrIsBoostGrpActive(struct OBJGPUBOOSTMGR *pBoostMg #ifdef __cplusplus } // extern "C" #endif + #endif // _G_GPU_BOOST_MGR_NVOC_H_ diff --git a/src/nvidia/generated/g_gpu_class_list.c b/src/nvidia/generated/g_gpu_class_list.c index e29b5b36f0..a579eda6f9 100644 --- a/src/nvidia/generated/g_gpu_class_list.c +++ b/src/nvidia/generated/g_gpu_class_list.c @@ -39,6 +39,7 @@ gpuGetClassDescriptorList_TU102(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -103,6 +104,7 @@ gpuGetClassDescriptorList_TU104(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -168,6 +170,7 @@ gpuGetClassDescriptorList_TU106(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -234,6 +237,7 @@ gpuGetClassDescriptorList_TU116(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -298,6 +302,7 @@ gpuGetClassDescriptorList_TU117(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -381,6 +386,7 @@ gpuGetClassDescriptorList_GA100(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { FERMI_TWOD_A, ENG_GR(0) }, { FERMI_VASPACE_A, ENG_DMA }, { G84_PERFBUFFER, ENG_BUS }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -403,7 +409,7 @@ gpuGetClassDescriptorList_GA100(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { NVC6B0_VIDEO_DECODER, ENG_NVDEC(2) }, { NVC6B0_VIDEO_DECODER, ENG_NVDEC(3) }, { NVC6B0_VIDEO_DECODER, ENG_NVDEC(4) }, - { NVC6FA_VIDEO_OFA, ENG_OFA }, + { NVC6FA_VIDEO_OFA, ENG_OFA(0) }, { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE }, { RM_USER_SHARED_DATA, ENG_GPU }, { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, @@ -444,6 +450,7 @@ gpuGetClassDescriptorList_GA102(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -473,7 +480,7 @@ gpuGetClassDescriptorList_GA102(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { NVC7B0_VIDEO_DECODER, ENG_NVDEC(0) }, { NVC7B0_VIDEO_DECODER, ENG_NVDEC(1) }, { NVC7B7_VIDEO_ENCODER, ENG_MSENC(0) }, - { NVC7FA_VIDEO_OFA, ENG_OFA }, + { NVC7FA_VIDEO_OFA, ENG_OFA(0) }, { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE }, { RM_USER_SHARED_DATA, ENG_GPU }, { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, @@ -514,6 +521,7 @@ gpuGetClassDescriptorList_GA103(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -543,7 +551,7 @@ gpuGetClassDescriptorList_GA103(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { NVC7B0_VIDEO_DECODER, ENG_NVDEC(0) }, { NVC7B0_VIDEO_DECODER, ENG_NVDEC(1) }, { NVC7B7_VIDEO_ENCODER, ENG_MSENC(0) }, - { NVC7FA_VIDEO_OFA, ENG_OFA }, + { NVC7FA_VIDEO_OFA, ENG_OFA(0) }, { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE }, { RM_USER_SHARED_DATA, ENG_GPU }, { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, @@ -584,6 +592,7 @@ gpuGetClassDescriptorList_GA104(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -613,7 +622,7 @@ gpuGetClassDescriptorList_GA104(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { NVC7B0_VIDEO_DECODER, ENG_NVDEC(0) }, { NVC7B0_VIDEO_DECODER, ENG_NVDEC(1) }, { NVC7B7_VIDEO_ENCODER, ENG_MSENC(0) }, - { NVC7FA_VIDEO_OFA, ENG_OFA }, + { NVC7FA_VIDEO_OFA, ENG_OFA(0) }, { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE }, { RM_USER_SHARED_DATA, ENG_GPU }, { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, @@ -654,6 +663,7 @@ gpuGetClassDescriptorList_GA106(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -683,7 +693,7 @@ gpuGetClassDescriptorList_GA106(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { NVC7B0_VIDEO_DECODER, ENG_NVDEC(0) }, { NVC7B0_VIDEO_DECODER, ENG_NVDEC(1) }, { NVC7B7_VIDEO_ENCODER, ENG_MSENC(0) }, - { NVC7FA_VIDEO_OFA, ENG_OFA }, + { NVC7FA_VIDEO_OFA, ENG_OFA(0) }, { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE }, { RM_USER_SHARED_DATA, ENG_GPU }, { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, @@ -724,6 +734,7 @@ gpuGetClassDescriptorList_GA107(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -753,7 +764,7 @@ gpuGetClassDescriptorList_GA107(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { NVC7B0_VIDEO_DECODER, ENG_NVDEC(0) }, { NVC7B0_VIDEO_DECODER, ENG_NVDEC(1) }, { NVC7B7_VIDEO_ENCODER, ENG_MSENC(0) }, - { NVC7FA_VIDEO_OFA, ENG_OFA }, + { NVC7FA_VIDEO_OFA, ENG_OFA(0) }, { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE }, { RM_USER_SHARED_DATA, ENG_GPU }, { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, @@ -794,6 +805,7 @@ gpuGetClassDescriptorList_AD102(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -831,7 +843,7 @@ gpuGetClassDescriptorList_AD102(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(1) }, { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(2) }, { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(3) }, - { NVC9FA_VIDEO_OFA, ENG_OFA }, + { NVC9FA_VIDEO_OFA, ENG_OFA(0) }, { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE }, { RM_USER_SHARED_DATA, ENG_GPU }, { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, @@ -872,6 +884,7 @@ gpuGetClassDescriptorList_AD103(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -909,7 +922,7 @@ gpuGetClassDescriptorList_AD103(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(1) }, { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(2) }, { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(3) }, - { NVC9FA_VIDEO_OFA, ENG_OFA }, + { NVC9FA_VIDEO_OFA, ENG_OFA(0) }, { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE }, { RM_USER_SHARED_DATA, ENG_GPU }, { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, @@ -950,6 +963,7 @@ gpuGetClassDescriptorList_AD104(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -987,7 +1001,7 @@ gpuGetClassDescriptorList_AD104(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(1) }, { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(2) }, { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(3) }, - { NVC9FA_VIDEO_OFA, ENG_OFA }, + { NVC9FA_VIDEO_OFA, ENG_OFA(0) }, { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE }, { RM_USER_SHARED_DATA, ENG_GPU }, { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, @@ -1028,6 +1042,7 @@ gpuGetClassDescriptorList_AD106(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -1065,7 +1080,7 @@ gpuGetClassDescriptorList_AD106(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(1) }, { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(2) }, { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(3) }, - { NVC9FA_VIDEO_OFA, ENG_OFA }, + { NVC9FA_VIDEO_OFA, ENG_OFA(0) }, { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE }, { RM_USER_SHARED_DATA, ENG_GPU }, { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, @@ -1106,6 +1121,7 @@ gpuGetClassDescriptorList_AD107(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { G84_PERFBUFFER, ENG_BUS }, { GF100_DISP_SW, ENG_SW }, { GF100_HDACODEC, ENG_HDACODEC }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -1143,7 +1159,7 @@ gpuGetClassDescriptorList_AD107(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(1) }, { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(2) }, { NVC9D1_VIDEO_NVJPG, ENG_NVJPEG(3) }, - { NVC9FA_VIDEO_OFA, ENG_OFA }, + { NVC9FA_VIDEO_OFA, ENG_OFA(0) }, { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE }, { RM_USER_SHARED_DATA, ENG_GPU }, { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, @@ -1175,6 +1191,7 @@ gpuGetClassDescriptorList_GH100(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { FERMI_TWOD_A, ENG_GR(0) }, { FERMI_VASPACE_A, ENG_DMA }, { G84_PERFBUFFER, ENG_BUS }, + { GF100_SUBDEVICE_INFOROM, ENG_GPU }, { GF100_SUBDEVICE_MASTER, ENG_GPU }, { GF100_TIMED_SEMAPHORE_SW, ENG_SW }, { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, @@ -1229,7 +1246,7 @@ gpuGetClassDescriptorList_GH100(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { NVB8D1_VIDEO_NVJPG, ENG_NVJPEG(5) }, { NVB8D1_VIDEO_NVJPG, ENG_NVJPEG(6) }, { NVB8D1_VIDEO_NVJPG, ENG_NVJPEG(7) }, - { NVB8FA_VIDEO_OFA, ENG_OFA }, + { NVB8FA_VIDEO_OFA, ENG_OFA(0) }, { NV_CONFIDENTIAL_COMPUTE, ENG_CONF_COMPUTE }, { RM_USER_SHARED_DATA, ENG_GPU }, { TURING_CHANNEL_GPFIFO_A, ENG_KERNEL_FIFO }, diff --git a/src/nvidia/generated/g_gpu_db_nvoc.h b/src/nvidia/generated/g_gpu_db_nvoc.h index 38c4b0a1c4..90f25eaf41 100644 --- a/src/nvidia/generated/g_gpu_db_nvoc.h +++ b/src/nvidia/generated/g_gpu_db_nvoc.h @@ -153,4 +153,5 @@ NV_STATUS gpudbSetShutdownState(const NvU8 *pUuid); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_GPU_DB_NVOC_H_ diff --git a/src/nvidia/generated/g_gpu_group_nvoc.h b/src/nvidia/generated/g_gpu_group_nvoc.h index 43a55ce603..4d1886d034 100644 --- a/src/nvidia/generated/g_gpu_group_nvoc.h +++ b/src/nvidia/generated/g_gpu_group_nvoc.h @@ -317,4 +317,5 @@ static inline NV_STATUS gpugrpGetGpuFromSubDeviceInstance(struct OBJGPUGRP *pGpu #ifdef __cplusplus } // extern "C" #endif + #endif // _G_GPU_GROUP_NVOC_H_ diff --git a/src/nvidia/generated/g_gpu_halspec_nvoc.c b/src/nvidia/generated/g_gpu_halspec_nvoc.c index 90b0c909b5..4e4362f54d 100644 --- a/src/nvidia/generated/g_gpu_halspec_nvoc.c +++ b/src/nvidia/generated/g_gpu_halspec_nvoc.c @@ -16,6 +16,7 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmHalspecOwner; void __nvoc_init_RmHalspecOwner(RmHalspecOwner*, NvU32 ChipHal_arch, NvU32 ChipHal_impl, NvU32 ChipHal_hidrev, RM_RUNTIME_VARIANT RmVariantHal_rmVariant, + TEGRA_CHIP_TYPE TegraChipHal_tegraType, NvU32 DispIpHal_ipver); void __nvoc_init_funcTable_RmHalspecOwner(RmHalspecOwner*); NV_STATUS __nvoc_ctor_RmHalspecOwner(RmHalspecOwner*); @@ -87,10 +88,12 @@ void __nvoc_init_funcTable_RmHalspecOwner(RmHalspecOwner *pThis) { void __nvoc_init_RmHalspecOwner(RmHalspecOwner *pThis, NvU32 ChipHal_arch, NvU32 ChipHal_impl, NvU32 ChipHal_hidrev, RM_RUNTIME_VARIANT RmVariantHal_rmVariant, + TEGRA_CHIP_TYPE TegraChipHal_tegraType, NvU32 DispIpHal_ipver) { pThis->__nvoc_pbase_RmHalspecOwner = pThis; __nvoc_init_halspec_ChipHal(&pThis->chipHal, ChipHal_arch, ChipHal_impl, ChipHal_hidrev); __nvoc_init_halspec_RmVariantHal(&pThis->rmVariantHal, RmVariantHal_rmVariant); + __nvoc_init_halspec_TegraChipHal(&pThis->tegraChipHal, TegraChipHal_tegraType); __nvoc_init_halspec_DispIpHal(&pThis->dispIpHal, DispIpHal_ipver); __nvoc_init_funcTable_RmHalspecOwner(pThis); } diff --git a/src/nvidia/generated/g_gpu_halspec_nvoc.h b/src/nvidia/generated/g_gpu_halspec_nvoc.h index 8b7d5d35e1..2889c83ba7 100644 --- a/src/nvidia/generated/g_gpu_halspec_nvoc.h +++ b/src/nvidia/generated/g_gpu_halspec_nvoc.h @@ -46,6 +46,7 @@ struct RmHalspecOwner { struct RmHalspecOwner *__nvoc_pbase_RmHalspecOwner; struct ChipHal chipHal; struct RmVariantHal rmVariantHal; + struct TegraChipHal tegraChipHal; struct DispIpHal dispIpHal; }; @@ -76,9 +77,10 @@ NV_STATUS __nvoc_objCreateDynamic_RmHalspecOwner(RmHalspecOwner**, Dynamic*, NvU NV_STATUS __nvoc_objCreate_RmHalspecOwner(RmHalspecOwner**, Dynamic*, NvU32, NvU32 ChipHal_arch, NvU32 ChipHal_impl, NvU32 ChipHal_hidrev, RM_RUNTIME_VARIANT RmVariantHal_rmVariant, + TEGRA_CHIP_TYPE TegraChipHal_tegraType, NvU32 DispIpHal_ipver); -#define __objCreate_RmHalspecOwner(ppNewObj, pParent, createFlags, ChipHal_arch, ChipHal_impl, ChipHal_hidrev, RmVariantHal_rmVariant, DispIpHal_ipver) \ - __nvoc_objCreate_RmHalspecOwner((ppNewObj), staticCast((pParent), Dynamic), (createFlags), ChipHal_arch, ChipHal_impl, ChipHal_hidrev, RmVariantHal_rmVariant, DispIpHal_ipver) +#define __objCreate_RmHalspecOwner(ppNewObj, pParent, createFlags, ChipHal_arch, ChipHal_impl, ChipHal_hidrev, RmVariantHal_rmVariant, TegraChipHal_tegraType, DispIpHal_ipver) \ + __nvoc_objCreate_RmHalspecOwner((ppNewObj), staticCast((pParent), Dynamic), (createFlags), ChipHal_arch, ChipHal_impl, ChipHal_hidrev, RmVariantHal_rmVariant, TegraChipHal_tegraType, DispIpHal_ipver) #undef PRIVATE_FIELD @@ -88,4 +90,5 @@ NV_STATUS __nvoc_objCreate_RmHalspecOwner(RmHalspecOwner**, Dynamic*, NvU32, #ifdef __cplusplus } // extern "C" #endif + #endif // _G_GPU_HALSPEC_NVOC_H_ diff --git a/src/nvidia/generated/g_gpu_instance_subscription_nvoc.h b/src/nvidia/generated/g_gpu_instance_subscription_nvoc.h index ab23e7929c..9d766eef22 100644 --- a/src/nvidia/generated/g_gpu_instance_subscription_nvoc.h +++ b/src/nvidia/generated/g_gpu_instance_subscription_nvoc.h @@ -100,6 +100,7 @@ struct GPUInstanceSubscription { NvBool PRIVATE_FIELD(bIsDuped); NvU64 PRIVATE_FIELD(dupedCapDescriptor); }; + struct GPUInstanceSubscription_PRIVATE { const struct NVOC_RTTI *__nvoc_rtti; struct GpuResource __nvoc_base_GpuResource; @@ -356,6 +357,11 @@ static inline NvBool gisubscriptionIsDeviceProfiling(struct GPUInstanceSubscript return pGPUInstanceSubscription_PRIVATE->bDeviceProfiling; } +static inline KERNEL_MIG_GPU_INSTANCE *gisubscriptionGetMIGGPUInstance(struct GPUInstanceSubscription *pGPUInstanceSubscription) { + struct GPUInstanceSubscription_PRIVATE *pGPUInstanceSubscription_PRIVATE = (struct GPUInstanceSubscription_PRIVATE *)pGPUInstanceSubscription; + return pGPUInstanceSubscription_PRIVATE->pKernelMIGGpuInstance; +} + NV_STATUS gisubscriptionGetGPUInstanceSubscription_IMPL(struct RsClient *arg0, NvHandle arg1, struct GPUInstanceSubscription **arg2); #define gisubscriptionGetGPUInstanceSubscription(arg0, arg1, arg2) gisubscriptionGetGPUInstanceSubscription_IMPL(arg0, arg1, arg2) @@ -402,4 +408,5 @@ static inline NvBool gisubscriptionIsDuped(struct GPUInstanceSubscription *arg0) #ifdef __cplusplus } // extern "C" #endif + #endif // _G_GPU_INSTANCE_SUBSCRIPTION_NVOC_H_ diff --git a/src/nvidia/generated/g_gpu_mgmt_api_nvoc.h b/src/nvidia/generated/g_gpu_mgmt_api_nvoc.h index 3013a2178a..4d8ca1b5c1 100644 --- a/src/nvidia/generated/g_gpu_mgmt_api_nvoc.h +++ b/src/nvidia/generated/g_gpu_mgmt_api_nvoc.h @@ -238,4 +238,5 @@ void gpumgmtapiDestruct_IMPL(struct GpuManagementApi *pGpuMgmt); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_GPU_MGMT_API_NVOC_H_ diff --git a/src/nvidia/generated/g_gpu_mgr_nvoc.h b/src/nvidia/generated/g_gpu_mgr_nvoc.h index 1ed26c67ca..1a84702be6 100644 --- a/src/nvidia/generated/g_gpu_mgr_nvoc.h +++ b/src/nvidia/generated/g_gpu_mgr_nvoc.h @@ -244,6 +244,21 @@ typedef struct GPUMGR_SAVE_MIG_INSTANCE_TOPOLOGY GPUMGR_SAVE_GPU_INSTANCE saveGI[GPUMGR_MAX_GPU_INSTANCES]; } GPUMGR_SAVE_MIG_INSTANCE_TOPOLOGY; +typedef struct GPUMGR_CACHED_MIG_GPU_INSTANCE +{ + NvBool bValid; + NvU32 swizzId; + NvBool bValidComputeInstances[GPUMGR_MAX_COMPUTE_INSTANCES]; +} GPUMGR_CACHED_MIG_GPU_INSTANCE; + +typedef struct GPUMGR_CACHED_MIG_STATE +{ + NvBool bValid; + NvBool bMIGEnabled; + NvU32 gpuId; + GPUMGR_CACHED_MIG_GPU_INSTANCE gpuInstances[GPUMGR_MAX_GPU_INSTANCES]; +} GPUMGR_CACHED_MIG_STATE; + #include "containers/list.h" typedef struct PCIEP2PCAPSINFO @@ -284,6 +299,8 @@ struct OBJGPUMGR { NVLINK_TOPOLOGY_INFO nvlinkTopologyInfo[32]; NvU8 nvlinkBwMode; GPUMGR_SAVE_MIG_INSTANCE_TOPOLOGY MIGTopologyInfo[32]; + void *cachedMIGInfoLock; + GPUMGR_CACHED_MIG_STATE cachedMIGInfo[32]; GPU_HANDLE_ID gpuHandleIDList[32]; NvU32 numGpuHandles; CONF_COMPUTE_CAPS ccCaps; @@ -397,6 +414,24 @@ void gpumgrSetSystemMIGEnabled_IMPL(NvU64 domainBusDevice, NvBool bMIGEnabled); void gpumgrUnregisterRmCapsForMIGGI_IMPL(NvU64 gpuDomainBusDevice); #define gpumgrUnregisterRmCapsForMIGGI(gpuDomainBusDevice) gpumgrUnregisterRmCapsForMIGGI_IMPL(gpuDomainBusDevice) +void gpumgrCacheCreateGpuInstance_IMPL(struct OBJGPU *pGpu, NvU32 swizzId); + +#define gpumgrCacheCreateGpuInstance(pGpu, swizzId) gpumgrCacheCreateGpuInstance_IMPL(pGpu, swizzId) +void gpumgrCacheDestroyGpuInstance_IMPL(struct OBJGPU *pGpu, NvU32 swizzId); + +#define gpumgrCacheDestroyGpuInstance(pGpu, swizzId) gpumgrCacheDestroyGpuInstance_IMPL(pGpu, swizzId) +void gpumgrCacheCreateComputeInstance_IMPL(struct OBJGPU *pGpu, NvU32 swizzId, NvU32 ciId); + +#define gpumgrCacheCreateComputeInstance(pGpu, swizzId, ciId) gpumgrCacheCreateComputeInstance_IMPL(pGpu, swizzId, ciId) +void gpumgrCacheDestroyComputeInstance_IMPL(struct OBJGPU *pGpu, NvU32 swizzId, NvU32 ciId); + +#define gpumgrCacheDestroyComputeInstance(pGpu, swizzId, ciId) gpumgrCacheDestroyComputeInstance_IMPL(pGpu, swizzId, ciId) +void gpumgrCacheSetMIGEnabled_IMPL(struct OBJGPU *pGpu, NvBool bMIGEnabled); + +#define gpumgrCacheSetMIGEnabled(pGpu, bMIGEnabled) gpumgrCacheSetMIGEnabled_IMPL(pGpu, bMIGEnabled) +NV_STATUS gpumgrCacheGetActiveDeviceIds_IMPL(NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS *pActiveDeviceIdsParams); + +#define gpumgrCacheGetActiveDeviceIds(pActiveDeviceIdsParams) gpumgrCacheGetActiveDeviceIds_IMPL(pActiveDeviceIdsParams) void gpumgrUpdateBoardId_IMPL(struct OBJGPU *arg0); #define gpumgrUpdateBoardId(arg0) gpumgrUpdateBoardId_IMPL(arg0) @@ -557,4 +592,5 @@ gpumgrIsParentGPU(OBJGPU *pGpu) #ifdef __cplusplus } // extern "C" #endif + #endif // _G_GPU_MGR_NVOC_H_ diff --git a/src/nvidia/generated/g_gpu_nvoc.c b/src/nvidia/generated/g_gpu_nvoc.c index 29896f711e..4406ae6da9 100644 --- a/src/nvidia/generated/g_gpu_nvoc.c +++ b/src/nvidia/generated/g_gpu_nvoc.c @@ -22,6 +22,7 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJTRACEABLE; void __nvoc_init_OBJGPU(OBJGPU*, NvU32 ChipHal_arch, NvU32 ChipHal_impl, NvU32 ChipHal_hidrev, RM_RUNTIME_VARIANT RmVariantHal_rmVariant, + TEGRA_CHIP_TYPE TegraChipHal_tegraType, NvU32 DispIpHal_ipver); void __nvoc_init_funcTable_OBJGPU(OBJGPU*); NV_STATUS __nvoc_ctor_OBJGPU(OBJGPU*, NvU32 arg_gpuInstance); @@ -136,16 +137,16 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) { pThis->setProperty(pThis, PDB_PROP_GPU_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE, ((NvBool)(0 != 0))); } - // NVOC Property Hal field -- PDB_PROP_GPU_IS_UEFI + // NVOC Property Hal field -- PDB_PROP_GPU_ZERO_FB // default { - pThis->setProperty(pThis, PDB_PROP_GPU_IS_UEFI, ((NvBool)(0 != 0))); + pThis->setProperty(pThis, PDB_PROP_GPU_ZERO_FB, ((NvBool)(0 != 0))); } - // NVOC Property Hal field -- PDB_PROP_GPU_ZERO_FB + // NVOC Property Hal field -- PDB_PROP_GPU_BAR1_BAR2_DISABLED // default { - pThis->setProperty(pThis, PDB_PROP_GPU_ZERO_FB, ((NvBool)(0 != 0))); + pThis->setProperty(pThis, PDB_PROP_GPU_BAR1_BAR2_DISABLED, ((NvBool)(0 != 0))); } // NVOC Property Hal field -- PDB_PROP_GPU_CAN_OPTIMIZE_COMPUTE_USE_CASE @@ -226,7 +227,6 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) { pThis->setProperty(pThis, PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK, ((NvBool)(0 == 0))); } pThis->setProperty(pThis, PDB_PROP_GPU_OPTIMUS_GOLD_CFG_SPACE_RESTORE, ((NvBool)(0 == 0))); - pThis->setProperty(pThis, PDB_PROP_GPU_SRIOV_HEAVY_FORCE_INVALIDATE_ALL_PDBS_WAR_BUG3896322, ((NvBool)(0 != 0))); // NVOC Property Hal field -- PDB_PROP_GPU_CC_FEATURE_CAPABLE if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ @@ -266,7 +266,12 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) { { pThis->setProperty(pThis, PDB_PROP_GPU_CHIP_SUPPORTS_RTD3_DEF, ((NvBool)(0 == 0))); } - pThis->setProperty(pThis, PDB_PROP_GPU_FASTPATH_SEQ_ENABLED, ((NvBool)(0 != 0))); + + // NVOC Property Hal field -- PDB_PROP_GPU_IS_SOC_SDM + // default + { + pThis->setProperty(pThis, PDB_PROP_GPU_IS_SOC_SDM, ((NvBool)(0 != 0))); + } pThis->boardId = ~0; @@ -301,6 +306,9 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) { // Hal field -- bWarBug200577889SriovHeavyEnabled pThis->bWarBug200577889SriovHeavyEnabled = ((NvBool)(0 != 0)); + // Hal field -- bNonPowerOf2ChannelCountSupported + pThis->bNonPowerOf2ChannelCountSupported = ((NvBool)(0 != 0)); + // Hal field -- bNeed4kPageIsolation // default { @@ -330,6 +338,8 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) { pThis->bClientRmAllocatedCtxBuffer = ((NvBool)(0 != 0)); } + pThis->bIterativeMmuWalker = ((NvBool)(0 == 0)); + // Hal field -- bVidmemPreservationBrokenBug3172217 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { @@ -367,17 +377,23 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) { pThis->bRecheckSliSupportAtResume = ((NvBool)(0 == 0)); } - pThis->bIsGspOwnedFaultBuffersEnabled = ((NvBool)(0 != 0)); - - // Hal field -- bEnableBar1SparseForFillPteMemUnmap - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + // Hal field -- bGpuNvEncAv1Supported + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ { - pThis->bEnableBar1SparseForFillPteMemUnmap = ((NvBool)(0 == 0)); + pThis->bGpuNvEncAv1Supported = ((NvBool)(0 == 0)); } // default else { - pThis->bEnableBar1SparseForFillPteMemUnmap = ((NvBool)(0 != 0)); + pThis->bGpuNvEncAv1Supported = ((NvBool)(0 != 0)); + } + + pThis->bIsGspOwnedFaultBuffersEnabled = ((NvBool)(0 != 0)); + + // Hal field -- bVideoTraceLogSupported + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + { + pThis->bVideoTraceLogSupported = ((NvBool)(0 == 0)); } } @@ -625,8 +641,9 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { // Hal function -- gpuClearFbhubPoisonIntrForBug2924523 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ { - pThis->__gpuClearFbhubPoisonIntrForBug2924523__ = &gpuClearFbhubPoisonIntrForBug2924523_GA100_KERNEL; + pThis->__gpuClearFbhubPoisonIntrForBug2924523__ = &gpuClearFbhubPoisonIntrForBug2924523_GA100; } + // default else { pThis->__gpuClearFbhubPoisonIntrForBug2924523__ = &gpuClearFbhubPoisonIntrForBug2924523_56cd7a; @@ -739,18 +756,19 @@ void __nvoc_init_funcTable_OBJGPU(OBJGPU *pThis) { } void __nvoc_init_Object(Object*); -void __nvoc_init_RmHalspecOwner(RmHalspecOwner*, NvU32, NvU32, NvU32, RM_RUNTIME_VARIANT, NvU32); +void __nvoc_init_RmHalspecOwner(RmHalspecOwner*, NvU32, NvU32, NvU32, RM_RUNTIME_VARIANT, TEGRA_CHIP_TYPE, NvU32); void __nvoc_init_OBJTRACEABLE(OBJTRACEABLE*); void __nvoc_init_OBJGPU(OBJGPU *pThis, NvU32 ChipHal_arch, NvU32 ChipHal_impl, NvU32 ChipHal_hidrev, RM_RUNTIME_VARIANT RmVariantHal_rmVariant, + TEGRA_CHIP_TYPE TegraChipHal_tegraType, NvU32 DispIpHal_ipver) { pThis->__nvoc_pbase_OBJGPU = pThis; pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_Object; pThis->__nvoc_pbase_RmHalspecOwner = &pThis->__nvoc_base_RmHalspecOwner; pThis->__nvoc_pbase_OBJTRACEABLE = &pThis->__nvoc_base_OBJTRACEABLE; __nvoc_init_Object(&pThis->__nvoc_base_Object); - __nvoc_init_RmHalspecOwner(&pThis->__nvoc_base_RmHalspecOwner, ChipHal_arch, ChipHal_impl, ChipHal_hidrev, RmVariantHal_rmVariant, DispIpHal_ipver); + __nvoc_init_RmHalspecOwner(&pThis->__nvoc_base_RmHalspecOwner, ChipHal_arch, ChipHal_impl, ChipHal_hidrev, RmVariantHal_rmVariant, TegraChipHal_tegraType, DispIpHal_ipver); __nvoc_init_OBJTRACEABLE(&pThis->__nvoc_base_OBJTRACEABLE); __nvoc_init_funcTable_OBJGPU(pThis); } @@ -758,6 +776,7 @@ void __nvoc_init_OBJGPU(OBJGPU *pThis, NV_STATUS __nvoc_objCreate_OBJGPU(OBJGPU **ppThis, Dynamic *pParent, NvU32 createFlags, NvU32 ChipHal_arch, NvU32 ChipHal_impl, NvU32 ChipHal_hidrev, RM_RUNTIME_VARIANT RmVariantHal_rmVariant, + TEGRA_CHIP_TYPE TegraChipHal_tegraType, NvU32 DispIpHal_ipver, NvU32 arg_gpuInstance) { NV_STATUS status; Object *pParentObj; @@ -783,7 +802,7 @@ NV_STATUS __nvoc_objCreate_OBJGPU(OBJGPU **ppThis, Dynamic *pParent, NvU32 creat pThis->__nvoc_base_Object.pParent = NULL; } - __nvoc_init_OBJGPU(pThis, ChipHal_arch, ChipHal_impl, ChipHal_hidrev, RmVariantHal_rmVariant, DispIpHal_ipver); + __nvoc_init_OBJGPU(pThis, ChipHal_arch, ChipHal_impl, ChipHal_hidrev, RmVariantHal_rmVariant, TegraChipHal_tegraType, DispIpHal_ipver); status = __nvoc_ctor_OBJGPU(pThis, arg_gpuInstance); if (status != NV_OK) goto __nvoc_objCreate_OBJGPU_cleanup; @@ -808,10 +827,11 @@ NV_STATUS __nvoc_objCreateDynamic_OBJGPU(OBJGPU **ppThis, Dynamic *pParent, NvU3 NvU32 ChipHal_impl = va_arg(args, NvU32); NvU32 ChipHal_hidrev = va_arg(args, NvU32); RM_RUNTIME_VARIANT RmVariantHal_rmVariant = va_arg(args, RM_RUNTIME_VARIANT); + TEGRA_CHIP_TYPE TegraChipHal_tegraType = va_arg(args, TEGRA_CHIP_TYPE); NvU32 DispIpHal_ipver = va_arg(args, NvU32); NvU32 arg_gpuInstance = va_arg(args, NvU32); - status = __nvoc_objCreate_OBJGPU(ppThis, pParent, createFlags, ChipHal_arch, ChipHal_impl, ChipHal_hidrev, RmVariantHal_rmVariant, DispIpHal_ipver, arg_gpuInstance); + status = __nvoc_objCreate_OBJGPU(ppThis, pParent, createFlags, ChipHal_arch, ChipHal_impl, ChipHal_hidrev, RmVariantHal_rmVariant, TegraChipHal_tegraType, DispIpHal_ipver, arg_gpuInstance); return status; } diff --git a/src/nvidia/generated/g_gpu_nvoc.h b/src/nvidia/generated/g_gpu_nvoc.h index c1cce99f6b..e15f865417 100644 --- a/src/nvidia/generated/g_gpu_nvoc.h +++ b/src/nvidia/generated/g_gpu_nvoc.h @@ -216,6 +216,18 @@ typedef struct KernelFalcon KernelFalcon; #endif /* __nvoc_class_id_KernelFalcon */ +struct KernelVideoEngine; + +#ifndef __NVOC_CLASS_KernelVideoEngine_TYPEDEF__ +#define __NVOC_CLASS_KernelVideoEngine_TYPEDEF__ +typedef struct KernelVideoEngine KernelVideoEngine; +#endif /* __NVOC_CLASS_KernelVideoEngine_TYPEDEF__ */ + +#ifndef __nvoc_class_id_KernelVideoEngine +#define __nvoc_class_id_KernelVideoEngine 0x9e2f3e +#endif /* __nvoc_class_id_KernelVideoEngine */ + + struct KernelChannel; #ifndef __NVOC_CLASS_KernelChannel_TYPEDEF__ @@ -253,6 +265,18 @@ typedef struct Subdevice Subdevice; #endif /* __nvoc_class_id_Subdevice */ +struct Device; + +#ifndef __NVOC_CLASS_Device_TYPEDEF__ +#define __NVOC_CLASS_Device_TYPEDEF__ +typedef struct Device Device; +#endif /* __NVOC_CLASS_Device_TYPEDEF__ */ + +#ifndef __nvoc_class_id_Device +#define __nvoc_class_id_Device 0xe0ac20 +#endif /* __nvoc_class_id_Device */ + + struct RsClient; #ifndef __NVOC_CLASS_RsClient_TYPEDEF__ @@ -793,6 +817,7 @@ typedef struct #define GPU_MAX_NVDECS NV2080_CTRL_CMD_INTERNAL_MAX_BSPS #define GPU_MAX_NVJPGS 8 #define GPU_MAX_HSHUBS 5 +#define GPU_MAX_OFAS 1 // // Macro defines for OBJGPU fields -- Macro defines inside NVOC class block is @@ -813,6 +838,12 @@ typedef struct ENG_MSENC__SIZE_1 + \ 32 +#define GPU_MAX_VIDEO_ENGINES \ + (ENG_NVJPEG__SIZE_1 + \ + ENG_NVDEC__SIZE_1 + \ + ENG_MSENC__SIZE_1 + \ + ENG_OFA__SIZE_1) + // for OBJGPU::pRmCtrlDeferredCmd #define MAX_DEFERRED_CMDS 2 @@ -853,6 +884,7 @@ typedef struct NV2080_CTRL_INTERNAL_DEVICE_INFO DEVICE_INFO2_ENTRY; #define GPU_IS_NVSWITCH_DETECTED(pGpu) \ (pGpu->nvswitchSupport == NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_SUPPORTED) + // // The actual GPU object definition // @@ -931,6 +963,7 @@ struct OBJGPU { NvBool PDB_PROP_GPU_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE; NvBool PDB_PROP_GPU_IS_UEFI; NvBool PDB_PROP_GPU_ZERO_FB; + NvBool PDB_PROP_GPU_BAR1_BAR2_DISABLED; NvBool PDB_PROP_GPU_CAN_OPTIMIZE_COMPUTE_USE_CASE; NvBool PDB_PROP_GPU_MIG_SUPPORTED; NvBool PDB_PROP_GPU_VC_CAPABILITY_SUPPORTED; @@ -955,7 +988,6 @@ struct OBJGPU { NvBool PDB_PROP_GPU_DO_NOT_CHECK_REG_ACCESS_IN_PM_CODEPATH; NvBool PDB_PROP_GPU_EXTERNAL_HEAP_CONTROL; NvBool PDB_PROP_GPU_IS_MOBILE; - NvBool PDB_PROP_GPU_READ_MULTIPLE_EDID_BLOCKS_VIA_ACPI_DDC; NvBool PDB_PROP_GPU_RTD3_GC6_SUPPORTED; NvBool PDB_PROP_GPU_RTD3_GC6_ACTIVE; NvBool PDB_PROP_GPU_FAST_GC6_ACTIVE; @@ -986,19 +1018,18 @@ struct OBJGPU { NvBool PDB_PROP_GPU_IS_MXM_3X; NvBool PDB_PROP_GPU_GSYNC_III_ATTACHED; NvBool PDB_PROP_GPU_QSYNC_II_ATTACHED; - NvBool PDB_PROP_GPU_SRIOV_HEAVY_FORCE_INVALIDATE_ALL_PDBS_WAR_BUG3896322; NvBool PDB_PROP_GPU_CC_FEATURE_CAPABLE; NvBool PDB_PROP_GPU_APM_FEATURE_CAPABLE; NvBool PDB_PROP_GPU_EXTENDED_GSP_RM_INITIALIZATION_TIMEOUT_FOR_VGX; NvBool PDB_PROP_GPU_SKIP_TABLE_CE_MAP; NvBool PDB_PROP_GPU_CHIP_SUPPORTS_RTD3_DEF; + NvBool PDB_PROP_GPU_IS_SOC_SDM; NvBool PDB_PROP_GPU_FORCE_PERF_BIOS_LEVEL; - NvBool PDB_PROP_GPU_FASTPATH_SEQ_ENABLED; OS_GPU_INFO *pOsGpuInfo; OS_RM_CAPS *pOsRmCaps; NvU32 halImpl; void *hPci; - GpuEngineEventNotificationList *engineNonstallIntrEventNotifications[62]; + GpuEngineEventNotificationList *engineNonstallIntrEventNotifications[63]; NvBool bIsSOC; NvU32 gpuInstance; NvU32 gpuDisabled; @@ -1017,6 +1048,8 @@ struct OBJGPU { GPUIDINFO idInfo; _GPU_CHIP_INFO chipInfo; GPUBUSINFO busInfo; + const GPUCHILDPRESENT *pChildrenPresent; + NvU32 numChildrenPresent; GPU_ENGINE_ORDER engineOrder; GPUCLASSDB classDB; NvU32 chipId0; @@ -1096,6 +1129,8 @@ struct OBJGPU { NvU32 numConstructedFalcons; struct GenericKernelFalcon *genericKernelFalcons[70]; NvU32 numGenericKernelFalcons; + struct KernelVideoEngine *kernelVideoEngines[20]; + NvU32 numKernelVideoEngines; NvU8 *pUserRegisterAccessMap; NvU8 *pUnrestrictedRegisterAccessMap; NvU32 userRegisterAccessMapSize; @@ -1148,6 +1183,7 @@ struct OBJGPU { NvBool bUnifiedMemorySpaceEnabled; NvBool bSriovEnabled; NvBool bWarBug200577889SriovHeavyEnabled; + NvBool bNonPowerOf2ChannelCountSupported; NvBool bCacheOnlyMode; NvBool bNeed4kPageIsolation; NvBool bSplitVasManagementServerClientRm; @@ -1162,6 +1198,7 @@ struct OBJGPU { NvS16 videoCtxswLogConsumerCount; EventBufferMap vgpuFecsTraceStagingBindings; FecsEventBufferBindMultiMap fecsEventBufferBindingsUid; + TMR_EVENT *pFecsTimerEvent; struct OBJVASPACE *pFabricVAS; NvBool bPipelinedPteMemEnabled; NvBool bIsBarPteInSysmemSupported; @@ -1171,6 +1208,7 @@ struct OBJGPU { NvBool bEccPageRetirementWithSliAllowed; NvBool bVidmemPreservationBrokenBug3172217; NvBool bInstanceMemoryAlwaysCached; + NvBool bUseRpcSimEscapes; NvBool bRmProfilingPrivileged; NvBool bGeforceSmb; NvBool bIsGeforce; @@ -1190,9 +1228,10 @@ struct OBJGPU { NvBool bVgpuGspPluginOffloadEnabled; NvBool bSriovCapable; NvBool bRecheckSliSupportAtResume; + NvBool bGpuNvEncAv1Supported; _GPU_SLI_PEER peer[2]; NvBool bIsGspOwnedFaultBuffersEnabled; - NvBool bEnableBar1SparseForFillPteMemUnmap; + NvBool bVideoTraceLogSupported; _GPU_GC6_STATE gc6State; }; @@ -1265,20 +1304,16 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU; #define PDB_PROP_GPU_RESETLESS_MIG_SUPPORTED_BASE_NAME PDB_PROP_GPU_RESETLESS_MIG_SUPPORTED #define PDB_PROP_GPU_MSHYBRID_GC6_ACTIVE_BASE_CAST #define PDB_PROP_GPU_MSHYBRID_GC6_ACTIVE_BASE_NAME PDB_PROP_GPU_MSHYBRID_GC6_ACTIVE -#define PDB_PROP_GPU_READ_MULTIPLE_EDID_BLOCKS_VIA_ACPI_DDC_BASE_CAST -#define PDB_PROP_GPU_READ_MULTIPLE_EDID_BLOCKS_VIA_ACPI_DDC_BASE_NAME PDB_PROP_GPU_READ_MULTIPLE_EDID_BLOCKS_VIA_ACPI_DDC +#define PDB_PROP_GPU_SKIP_TABLE_CE_MAP_BASE_CAST +#define PDB_PROP_GPU_SKIP_TABLE_CE_MAP_BASE_NAME PDB_PROP_GPU_SKIP_TABLE_CE_MAP #define PDB_PROP_GPU_VC_CAPABILITY_SUPPORTED_BASE_CAST #define PDB_PROP_GPU_VC_CAPABILITY_SUPPORTED_BASE_NAME PDB_PROP_GPU_VC_CAPABILITY_SUPPORTED #define PDB_PROP_GPU_RM_UNLINKED_SLI_BASE_CAST #define PDB_PROP_GPU_RM_UNLINKED_SLI_BASE_NAME PDB_PROP_GPU_RM_UNLINKED_SLI #define PDB_PROP_GPU_FORCE_PERF_BIOS_LEVEL_BASE_CAST #define PDB_PROP_GPU_FORCE_PERF_BIOS_LEVEL_BASE_NAME PDB_PROP_GPU_FORCE_PERF_BIOS_LEVEL -#define PDB_PROP_GPU_FASTPATH_SEQ_ENABLED_BASE_CAST -#define PDB_PROP_GPU_FASTPATH_SEQ_ENABLED_BASE_NAME PDB_PROP_GPU_FASTPATH_SEQ_ENABLED #define PDB_PROP_GPU_IS_UEFI_BASE_CAST #define PDB_PROP_GPU_IS_UEFI_BASE_NAME PDB_PROP_GPU_IS_UEFI -#define PDB_PROP_GPU_SKIP_TABLE_CE_MAP_BASE_CAST -#define PDB_PROP_GPU_SKIP_TABLE_CE_MAP_BASE_NAME PDB_PROP_GPU_SKIP_TABLE_CE_MAP #define PDB_PROP_GPU_IN_SECONDARY_BUS_RESET_BASE_CAST #define PDB_PROP_GPU_IN_SECONDARY_BUS_RESET_BASE_NAME PDB_PROP_GPU_IN_SECONDARY_BUS_RESET #define PDB_PROP_GPU_OPTIMIZE_SPARSE_TEXTURE_BY_DEFAULT_BASE_CAST @@ -1313,20 +1348,20 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU; #define PDB_PROP_GPU_MIG_SUPPORTED_BASE_NAME PDB_PROP_GPU_MIG_SUPPORTED #define PDB_PROP_GPU_IN_BUGCHECK_CALLBACK_ROUTINE_BASE_CAST #define PDB_PROP_GPU_IN_BUGCHECK_CALLBACK_ROUTINE_BASE_NAME PDB_PROP_GPU_IN_BUGCHECK_CALLBACK_ROUTINE -#define PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE_BASE_CAST -#define PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE_BASE_NAME PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE +#define PDB_PROP_GPU_BAR1_BAR2_DISABLED_BASE_CAST +#define PDB_PROP_GPU_BAR1_BAR2_DISABLED_BASE_NAME PDB_PROP_GPU_BAR1_BAR2_DISABLED #define PDB_PROP_GPU_CAN_OPTIMIZE_COMPUTE_USE_CASE_BASE_CAST #define PDB_PROP_GPU_CAN_OPTIMIZE_COMPUTE_USE_CASE_BASE_NAME PDB_PROP_GPU_CAN_OPTIMIZE_COMPUTE_USE_CASE -#define PDB_PROP_GPU_GCOFF_STATE_ENTERING_BASE_CAST -#define PDB_PROP_GPU_GCOFF_STATE_ENTERING_BASE_NAME PDB_PROP_GPU_GCOFF_STATE_ENTERING +#define PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE_BASE_CAST +#define PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE_BASE_NAME PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE #define PDB_PROP_GPU_ACCOUNTING_ON_BASE_CAST #define PDB_PROP_GPU_ACCOUNTING_ON_BASE_NAME PDB_PROP_GPU_ACCOUNTING_ON #define PDB_PROP_GPU_IN_HIBERNATE_BASE_CAST #define PDB_PROP_GPU_IN_HIBERNATE_BASE_NAME PDB_PROP_GPU_IN_HIBERNATE #define PDB_PROP_GPU_BROKEN_FB_BASE_CAST #define PDB_PROP_GPU_BROKEN_FB_BASE_NAME PDB_PROP_GPU_BROKEN_FB -#define PDB_PROP_GPU_ENABLE_IOMMU_SUPPORT_BASE_CAST -#define PDB_PROP_GPU_ENABLE_IOMMU_SUPPORT_BASE_NAME PDB_PROP_GPU_ENABLE_IOMMU_SUPPORT +#define PDB_PROP_GPU_GCOFF_STATE_ENTERING_BASE_CAST +#define PDB_PROP_GPU_GCOFF_STATE_ENTERING_BASE_NAME PDB_PROP_GPU_GCOFF_STATE_ENTERING #define PDB_PROP_GPU_IN_TIMEOUT_RECOVERY_BASE_CAST #define PDB_PROP_GPU_IN_TIMEOUT_RECOVERY_BASE_NAME PDB_PROP_GPU_IN_TIMEOUT_RECOVERY #define PDB_PROP_GPU_GCOFF_STATE_ENTERED_BASE_CAST @@ -1351,12 +1386,12 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU; #define PDB_PROP_GPU_STATE_INITIALIZED_BASE_NAME PDB_PROP_GPU_STATE_INITIALIZED #define PDB_PROP_GPU_NV_USERMODE_ENABLED_BASE_CAST #define PDB_PROP_GPU_NV_USERMODE_ENABLED_BASE_NAME PDB_PROP_GPU_NV_USERMODE_ENABLED -#define PDB_PROP_GPU_IS_MXM_3X_BASE_CAST -#define PDB_PROP_GPU_IS_MXM_3X_BASE_NAME PDB_PROP_GPU_IS_MXM_3X +#define PDB_PROP_GPU_ENABLE_IOMMU_SUPPORT_BASE_CAST +#define PDB_PROP_GPU_ENABLE_IOMMU_SUPPORT_BASE_NAME PDB_PROP_GPU_ENABLE_IOMMU_SUPPORT #define PDB_PROP_GPU_ALTERNATE_TREE_HANDLE_LOCKLESS_BASE_CAST #define PDB_PROP_GPU_ALTERNATE_TREE_HANDLE_LOCKLESS_BASE_NAME PDB_PROP_GPU_ALTERNATE_TREE_HANDLE_LOCKLESS -#define PDB_PROP_GPU_SRIOV_HEAVY_FORCE_INVALIDATE_ALL_PDBS_WAR_BUG3896322_BASE_CAST -#define PDB_PROP_GPU_SRIOV_HEAVY_FORCE_INVALIDATE_ALL_PDBS_WAR_BUG3896322_BASE_NAME PDB_PROP_GPU_SRIOV_HEAVY_FORCE_INVALIDATE_ALL_PDBS_WAR_BUG3896322 +#define PDB_PROP_GPU_IS_MXM_3X_BASE_CAST +#define PDB_PROP_GPU_IS_MXM_3X_BASE_NAME PDB_PROP_GPU_IS_MXM_3X #define PDB_PROP_GPU_GSYNC_III_ATTACHED_BASE_CAST #define PDB_PROP_GPU_GSYNC_III_ATTACHED_BASE_NAME PDB_PROP_GPU_GSYNC_III_ATTACHED #define PDB_PROP_GPU_QSYNC_II_ATTACHED_BASE_CAST @@ -1367,6 +1402,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU; #define PDB_PROP_GPU_CHIP_SUPPORTS_RTD3_DEF_BASE_NAME PDB_PROP_GPU_CHIP_SUPPORTS_RTD3_DEF #define PDB_PROP_GPU_OPTIMUS_GOLD_CFG_SPACE_RESTORE_BASE_CAST #define PDB_PROP_GPU_OPTIMUS_GOLD_CFG_SPACE_RESTORE_BASE_NAME PDB_PROP_GPU_OPTIMUS_GOLD_CFG_SPACE_RESTORE +#define PDB_PROP_GPU_IS_SOC_SDM_BASE_CAST +#define PDB_PROP_GPU_IS_SOC_SDM_BASE_NAME PDB_PROP_GPU_IS_SOC_SDM #define PDB_PROP_GPU_IS_ALL_INST_IN_SYSMEM_BASE_CAST #define PDB_PROP_GPU_IS_ALL_INST_IN_SYSMEM_BASE_NAME PDB_PROP_GPU_IS_ALL_INST_IN_SYSMEM #define PDB_PROP_GPU_NVLINK_P2P_LOOPBACK_DISABLED_BASE_CAST @@ -1413,9 +1450,10 @@ NV_STATUS __nvoc_objCreateDynamic_OBJGPU(OBJGPU**, Dynamic*, NvU32, va_list); NV_STATUS __nvoc_objCreate_OBJGPU(OBJGPU**, Dynamic*, NvU32, NvU32 ChipHal_arch, NvU32 ChipHal_impl, NvU32 ChipHal_hidrev, RM_RUNTIME_VARIANT RmVariantHal_rmVariant, + TEGRA_CHIP_TYPE TegraChipHal_tegraType, NvU32 DispIpHal_ipver, NvU32 arg_gpuInstance); -#define __objCreate_OBJGPU(ppNewObj, pParent, createFlags, ChipHal_arch, ChipHal_impl, ChipHal_hidrev, RmVariantHal_rmVariant, DispIpHal_ipver, arg_gpuInstance) \ - __nvoc_objCreate_OBJGPU((ppNewObj), staticCast((pParent), Dynamic), (createFlags), ChipHal_arch, ChipHal_impl, ChipHal_hidrev, RmVariantHal_rmVariant, DispIpHal_ipver, arg_gpuInstance) +#define __objCreate_OBJGPU(ppNewObj, pParent, createFlags, ChipHal_arch, ChipHal_impl, ChipHal_hidrev, RmVariantHal_rmVariant, TegraChipHal_tegraType, DispIpHal_ipver, arg_gpuInstance) \ + __nvoc_objCreate_OBJGPU((ppNewObj), staticCast((pParent), Dynamic), (createFlags), ChipHal_arch, ChipHal_impl, ChipHal_hidrev, RmVariantHal_rmVariant, TegraChipHal_tegraType, DispIpHal_ipver, arg_gpuInstance) #define gpuConstructDeviceInfoTable(pGpu) gpuConstructDeviceInfoTable_DISPATCH(pGpu) #define gpuConstructDeviceInfoTable_HAL(pGpu) gpuConstructDeviceInfoTable_DISPATCH(pGpu) @@ -1887,6 +1925,60 @@ static inline void gpuDestroyGenericKernelFalconList(struct OBJGPU *pGpu) { #define gpuDestroyGenericKernelFalconList_HAL(pGpu) gpuDestroyGenericKernelFalconList(pGpu) +NV_STATUS gpuBuildKernelVideoEngineList_IMPL(struct OBJGPU *pGpu); + + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuBuildKernelVideoEngineList(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuBuildKernelVideoEngineList(pGpu) gpuBuildKernelVideoEngineList_IMPL(pGpu) +#endif //__nvoc_gpu_h_disabled + +#define gpuBuildKernelVideoEngineList_HAL(pGpu) gpuBuildKernelVideoEngineList(pGpu) + +NV_STATUS gpuInitVideoLogging_IMPL(struct OBJGPU *pGpu); + + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuInitVideoLogging(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuInitVideoLogging(pGpu) gpuInitVideoLogging_IMPL(pGpu) +#endif //__nvoc_gpu_h_disabled + +#define gpuInitVideoLogging_HAL(pGpu) gpuInitVideoLogging(pGpu) + +void gpuFreeVideoLogging_IMPL(struct OBJGPU *pGpu); + + +#ifdef __nvoc_gpu_h_disabled +static inline void gpuFreeVideoLogging(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); +} +#else //__nvoc_gpu_h_disabled +#define gpuFreeVideoLogging(pGpu) gpuFreeVideoLogging_IMPL(pGpu) +#endif //__nvoc_gpu_h_disabled + +#define gpuFreeVideoLogging_HAL(pGpu) gpuFreeVideoLogging(pGpu) + +void gpuDestroyKernelVideoEngineList_IMPL(struct OBJGPU *pGpu); + + +#ifdef __nvoc_gpu_h_disabled +static inline void gpuDestroyKernelVideoEngineList(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); +} +#else //__nvoc_gpu_h_disabled +#define gpuDestroyKernelVideoEngineList(pGpu) gpuDestroyKernelVideoEngineList_IMPL(pGpu) +#endif //__nvoc_gpu_h_disabled + +#define gpuDestroyKernelVideoEngineList_HAL(pGpu) gpuDestroyKernelVideoEngineList(pGpu) + struct GenericKernelFalcon *gpuGetGenericKernelFalconForEngine_IMPL(struct OBJGPU *pGpu, ENGDESCRIPTOR arg0); @@ -2415,18 +2507,21 @@ static inline void gpuDestroyDefaultClientShare(struct OBJGPU *pGpu) { #define gpuDestroyDefaultClientShare_HAL(pGpu) gpuDestroyDefaultClientShare(pGpu) -void gpuUpdateUserSharedData_KERNEL(struct OBJGPU *pGpu); +static inline NvU64 gpuGetVmmuSegmentSize_72c522(struct OBJGPU *pGpu) { + return pGpu->vmmuSegmentSize; +} #ifdef __nvoc_gpu_h_disabled -static inline void gpuUpdateUserSharedData(struct OBJGPU *pGpu) { +static inline NvU64 gpuGetVmmuSegmentSize(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return 0; } #else //__nvoc_gpu_h_disabled -#define gpuUpdateUserSharedData(pGpu) gpuUpdateUserSharedData_KERNEL(pGpu) +#define gpuGetVmmuSegmentSize(pGpu) gpuGetVmmuSegmentSize_72c522(pGpu) #endif //__nvoc_gpu_h_disabled -#define gpuUpdateUserSharedData_HAL(pGpu) gpuUpdateUserSharedData(pGpu) +#define gpuGetVmmuSegmentSize_HAL(pGpu) gpuGetVmmuSegmentSize(pGpu) void gpuGetTerminatedLinkMask_GA100(struct OBJGPU *pGpu, NvU32 arg0); @@ -2921,6 +3016,22 @@ static inline GPU_P2P_PEER_GPU_CAPS *gpuFindP2PPeerGpuCapsByGpuId(struct OBJGPU #define gpuFindP2PPeerGpuCapsByGpuId_HAL(pGpu, peerGpuId) gpuFindP2PPeerGpuCapsByGpuId(pGpu, peerGpuId) +static inline NV_STATUS gpuLoadFailurePathTest_56cd7a(struct OBJGPU *pGpu, NvU32 engStage, NvU32 engDescIdx, NvBool bStopTest) { + return NV_OK; +} + + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuLoadFailurePathTest(struct OBJGPU *pGpu, NvU32 engStage, NvU32 engDescIdx, NvBool bStopTest) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuLoadFailurePathTest(pGpu, engStage, engDescIdx, bStopTest) gpuLoadFailurePathTest_56cd7a(pGpu, engStage, engDescIdx, bStopTest) +#endif //__nvoc_gpu_h_disabled + +#define gpuLoadFailurePathTest_HAL(pGpu, engStage, engDescIdx, bStopTest) gpuLoadFailurePathTest(pGpu, engStage, engDescIdx, bStopTest) + NV_STATUS gpuConstructDeviceInfoTable_FWCLIENT(struct OBJGPU *pGpu); static inline NV_STATUS gpuConstructDeviceInfoTable_56cd7a(struct OBJGPU *pGpu) { @@ -3083,14 +3194,12 @@ static inline NvBool gpuFuseSupportsDisplay_DISPATCH(struct OBJGPU *pGpu) { return pGpu->__gpuFuseSupportsDisplay__(pGpu); } -NV_STATUS gpuClearFbhubPoisonIntrForBug2924523_GA100_KERNEL(struct OBJGPU *pGpu); +NV_STATUS gpuClearFbhubPoisonIntrForBug2924523_GA100(struct OBJGPU *pGpu); static inline NV_STATUS gpuClearFbhubPoisonIntrForBug2924523_56cd7a(struct OBJGPU *pGpu) { return NV_OK; } -NV_STATUS gpuClearFbhubPoisonIntrForBug2924523_GA100_PHYSICAL(struct OBJGPU *pGpu); - static inline NV_STATUS gpuClearFbhubPoisonIntrForBug2924523_DISPATCH(struct OBJGPU *pGpu) { return pGpu->__gpuClearFbhubPoisonIntrForBug2924523__(pGpu); } @@ -3270,10 +3379,6 @@ static inline NvU32 gpuGetChipMinExtRev(struct OBJGPU *pGpu) { return pGpu->chipInfo.pmcBoot42.minorExtRev; } -static inline NvU64 gpuGetVmmuSegmentSize(struct OBJGPU *pGpu) { - return pGpu->vmmuSegmentSize; -} - static inline NvBool gpuIsVideoLinkDisabled(struct OBJGPU *pGpu) { return pGpu->bVideoLinkDisabled; } @@ -3422,6 +3527,10 @@ static inline NvBool gpuIsSriovCapable(struct OBJGPU *pGpu) { return pGpu->bSriovCapable; } +static inline NvBool gpuIsNonPowerOf2ChannelCountSupported(struct OBJGPU *pGpu) { + return pGpu->bNonPowerOf2ChannelCountSupported; +} + static inline NvBool gpuIsSelfHosted(struct OBJGPU *pGpu) { return pGpu->bIsSelfHosted; } @@ -3964,6 +4073,17 @@ static inline NV_STATUS gpuGetConstructedFalcon(struct OBJGPU *pGpu, NvU32 arg0, #define gpuGetConstructedFalcon(pGpu, arg0, arg1) gpuGetConstructedFalcon_IMPL(pGpu, arg0, arg1) #endif //__nvoc_gpu_h_disabled +NvBool gpuIsVideoTraceLogSupported_IMPL(struct OBJGPU *pGpu); + +#ifdef __nvoc_gpu_h_disabled +static inline NvBool gpuIsVideoTraceLogSupported(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_FALSE; +} +#else //__nvoc_gpu_h_disabled +#define gpuIsVideoTraceLogSupported(pGpu) gpuIsVideoTraceLogSupported_IMPL(pGpu) +#endif //__nvoc_gpu_h_disabled + NV_STATUS gpuGetSparseTextureComputeMode_IMPL(struct OBJGPU *pGpu, NvU32 *arg0, NvU32 *arg1, NvU32 *arg2); #ifdef __nvoc_gpu_h_disabled @@ -4386,6 +4506,16 @@ static inline NV_STATUS gpuSanityCheckRegisterAccess(struct OBJGPU *pGpu, NvU32 #define gpuSanityCheckRegisterAccess(pGpu, addr, pRetVal) gpuSanityCheckRegisterAccess_IMPL(pGpu, addr, pRetVal) #endif //__nvoc_gpu_h_disabled +void gpuUpdateUserSharedData_IMPL(struct OBJGPU *pGpu); + +#ifdef __nvoc_gpu_h_disabled +static inline void gpuUpdateUserSharedData(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); +} +#else //__nvoc_gpu_h_disabled +#define gpuUpdateUserSharedData(pGpu) gpuUpdateUserSharedData_IMPL(pGpu) +#endif //__nvoc_gpu_h_disabled + NV_STATUS gpuValidateRegOffset_IMPL(struct OBJGPU *pGpu, NvU32 arg0); #ifdef __nvoc_gpu_h_disabled @@ -4668,9 +4798,15 @@ VGPU_STATIC_INFO *gpuGetStaticInfo(struct OBJGPU *pGpu); GspStaticConfigInfo *gpuGetGspStaticInfo(struct OBJGPU *pGpu); #define GPU_GET_GSP_STATIC_INFO(pGpu) gpuGetGspStaticInfo(pGpu) +NV_STATUS gpuSimEscapeWrite(struct OBJGPU *, const char *path, NvU32 Index, NvU32 Size, NvU32 Value); +NV_STATUS gpuSimEscapeWriteBuffer(struct OBJGPU *, const char *path, NvU32 Index, NvU32 Size, void* pBuffer); +NV_STATUS gpuSimEscapeRead(struct OBJGPU *, const char *path, NvU32 Index, NvU32 Size, NvU32 *Value); +NV_STATUS gpuSimEscapeReadBuffer(struct OBJGPU *, const char *path, NvU32 Index, NvU32 Size, void* pBuffer); + #endif // _OBJGPU_H_ #ifdef __cplusplus } // extern "C" #endif + #endif // _G_GPU_NVOC_H_ diff --git a/src/nvidia/generated/g_gpu_resource_nvoc.h b/src/nvidia/generated/g_gpu_resource_nvoc.h index 00f658439b..74efd213dd 100644 --- a/src/nvidia/generated/g_gpu_resource_nvoc.h +++ b/src/nvidia/generated/g_gpu_resource_nvoc.h @@ -347,4 +347,5 @@ NV_STATUS gpuresGetByDeviceOrSubdeviceHandle_IMPL(struct RsClient *pClient, NvHa #ifdef __cplusplus } // extern "C" #endif + #endif // _G_GPU_RESOURCE_NVOC_H_ diff --git a/src/nvidia/generated/g_gpu_user_shared_data_nvoc.c b/src/nvidia/generated/g_gpu_user_shared_data_nvoc.c index 02992a5f0f..f06581b0c8 100644 --- a/src/nvidia/generated/g_gpu_user_shared_data_nvoc.c +++ b/src/nvidia/generated/g_gpu_user_shared_data_nvoc.c @@ -113,6 +113,10 @@ static NV_STATUS __nvoc_thunk_Memory_gpushareddataGetMapAddrSpace(struct GpuUser return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_GpuUserSharedData_Memory.offset), pCallContext, mapFlags, pAddrSpace); } +static NvBool __nvoc_thunk_Memory_gpushareddataIsExportAllowed(struct GpuUserSharedData *pMemory) { + return memIsExportAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_GpuUserSharedData_Memory.offset)); +} + static NvU32 __nvoc_thunk_RsResource_gpushareddataGetRefCount(struct GpuUserSharedData *pResource) { return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset)); } @@ -193,14 +197,39 @@ static NvBool __nvoc_thunk_RmResource_gpushareddataAccessCallback(struct GpuUser return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RmResource.offset), pInvokingClient, pAllocParams, accessRight); } +#if !defined(NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG) +#define NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(x) (0) +#endif + +static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_GpuUserSharedData[] = +{ + { /* [0] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) gpushareddataCtrlCmdRequestDataPoll_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xde0001u, + /*paramSize=*/ sizeof(NV00DE_CTRL_REQUEST_DATA_POLL_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_GpuUserSharedData.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "gpushareddataCtrlCmdRequestDataPoll" +#endif + }, + +}; + const struct NVOC_EXPORT_INFO __nvoc_export_info_GpuUserSharedData = { - /*numEntries=*/ 0, - /*pExportEntries=*/ 0 + /*numEntries=*/ 1, + /*pExportEntries=*/ __nvoc_exported_method_def_GpuUserSharedData }; void __nvoc_dtor_Memory(Memory*); void __nvoc_dtor_GpuUserSharedData(GpuUserSharedData *pThis) { + __nvoc_gpushareddataDestruct(pThis); __nvoc_dtor_Memory(&pThis->__nvoc_base_Memory); PORT_UNREFERENCED_VARIABLE(pThis); } @@ -233,6 +262,10 @@ static void __nvoc_init_funcTable_GpuUserSharedData_1(GpuUserSharedData *pThis) pThis->__gpushareddataCanCopy__ = &gpushareddataCanCopy_IMPL; +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__gpushareddataCtrlCmdRequestDataPoll__ = &gpushareddataCtrlCmdRequestDataPoll_IMPL; +#endif + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__resCanCopy__ = &__nvoc_thunk_GpuUserSharedData_resCanCopy; pThis->__gpushareddataCheckMemInterUnmap__ = &__nvoc_thunk_Memory_gpushareddataCheckMemInterUnmap; @@ -243,6 +276,8 @@ static void __nvoc_init_funcTable_GpuUserSharedData_1(GpuUserSharedData *pThis) pThis->__gpushareddataGetMapAddrSpace__ = &__nvoc_thunk_Memory_gpushareddataGetMapAddrSpace; + pThis->__gpushareddataIsExportAllowed__ = &__nvoc_thunk_Memory_gpushareddataIsExportAllowed; + pThis->__gpushareddataGetRefCount__ = &__nvoc_thunk_RsResource_gpushareddataGetRefCount; pThis->__gpushareddataAddAdditionalDependants__ = &__nvoc_thunk_RsResource_gpushareddataAddAdditionalDependants; diff --git a/src/nvidia/generated/g_gpu_user_shared_data_nvoc.h b/src/nvidia/generated/g_gpu_user_shared_data_nvoc.h index 3893723156..89c9750be8 100644 --- a/src/nvidia/generated/g_gpu_user_shared_data_nvoc.h +++ b/src/nvidia/generated/g_gpu_user_shared_data_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -38,6 +38,7 @@ extern "C" { #include "mem_mgr/mem.h" #include "gpu/gpu.h" #include "nvoc/utility.h" +#include "ctrl/ctrl00de.h" // **************************************************************************** // Type definitions @@ -61,10 +62,12 @@ struct GpuUserSharedData { struct Memory *__nvoc_pbase_Memory; struct GpuUserSharedData *__nvoc_pbase_GpuUserSharedData; NvBool (*__gpushareddataCanCopy__)(struct GpuUserSharedData *); + NV_STATUS (*__gpushareddataCtrlCmdRequestDataPoll__)(struct GpuUserSharedData *, NV00DE_CTRL_REQUEST_DATA_POLL_PARAMS *); NV_STATUS (*__gpushareddataCheckMemInterUnmap__)(struct GpuUserSharedData *, NvBool); NvBool (*__gpushareddataShareCallback__)(struct GpuUserSharedData *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__gpushareddataMapTo__)(struct GpuUserSharedData *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__gpushareddataGetMapAddrSpace__)(struct GpuUserSharedData *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvBool (*__gpushareddataIsExportAllowed__)(struct GpuUserSharedData *); NvU32 (*__gpushareddataGetRefCount__)(struct GpuUserSharedData *); void (*__gpushareddataAddAdditionalDependants__)(struct RsClient *, struct GpuUserSharedData *, RsResourceRef *); NV_STATUS (*__gpushareddataControl_Prologue__)(struct GpuUserSharedData *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -85,6 +88,7 @@ struct GpuUserSharedData { void (*__gpushareddataControlSerialization_Epilogue__)(struct GpuUserSharedData *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__gpushareddataMap__)(struct GpuUserSharedData *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__gpushareddataAccessCallback__)(struct GpuUserSharedData *, struct RsClient *, void *, RsAccessRight); + NvU64 polledDataMask; }; #ifndef __NVOC_CLASS_GpuUserSharedData_TYPEDEF__ @@ -116,10 +120,12 @@ NV_STATUS __nvoc_objCreate_GpuUserSharedData(GpuUserSharedData**, Dynamic*, NvU3 __nvoc_objCreate_GpuUserSharedData((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) #define gpushareddataCanCopy(pData) gpushareddataCanCopy_DISPATCH(pData) +#define gpushareddataCtrlCmdRequestDataPoll(pData, pParams) gpushareddataCtrlCmdRequestDataPoll_DISPATCH(pData, pParams) #define gpushareddataCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) gpushareddataCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) #define gpushareddataShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) gpushareddataShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define gpushareddataMapTo(pResource, pParams) gpushareddataMapTo_DISPATCH(pResource, pParams) #define gpushareddataGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) gpushareddataGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define gpushareddataIsExportAllowed(pMemory) gpushareddataIsExportAllowed_DISPATCH(pMemory) #define gpushareddataGetRefCount(pResource) gpushareddataGetRefCount_DISPATCH(pResource) #define gpushareddataAddAdditionalDependants(pClient, pResource, pReference) gpushareddataAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define gpushareddataControl_Prologue(pResource, pCallContext, pParams) gpushareddataControl_Prologue_DISPATCH(pResource, pCallContext, pParams) @@ -146,6 +152,12 @@ static inline NvBool gpushareddataCanCopy_DISPATCH(struct GpuUserSharedData *pDa return pData->__gpushareddataCanCopy__(pData); } +NV_STATUS gpushareddataCtrlCmdRequestDataPoll_IMPL(struct GpuUserSharedData *pData, NV00DE_CTRL_REQUEST_DATA_POLL_PARAMS *pParams); + +static inline NV_STATUS gpushareddataCtrlCmdRequestDataPoll_DISPATCH(struct GpuUserSharedData *pData, NV00DE_CTRL_REQUEST_DATA_POLL_PARAMS *pParams) { + return pData->__gpushareddataCtrlCmdRequestDataPoll__(pData, pParams); +} + static inline NV_STATUS gpushareddataCheckMemInterUnmap_DISPATCH(struct GpuUserSharedData *pMemory, NvBool bSubdeviceHandleProvided) { return pMemory->__gpushareddataCheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); } @@ -162,6 +174,10 @@ static inline NV_STATUS gpushareddataGetMapAddrSpace_DISPATCH(struct GpuUserShar return pMemory->__gpushareddataGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); } +static inline NvBool gpushareddataIsExportAllowed_DISPATCH(struct GpuUserSharedData *pMemory) { + return pMemory->__gpushareddataIsExportAllowed__(pMemory); +} + static inline NvU32 gpushareddataGetRefCount_DISPATCH(struct GpuUserSharedData *pResource) { return pResource->__gpushareddataGetRefCount__(pResource); } @@ -245,13 +261,16 @@ static inline NvBool gpushareddataAccessCallback_DISPATCH(struct GpuUserSharedDa NV_STATUS gpushareddataConstruct_IMPL(struct GpuUserSharedData *arg_pData, CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); #define __nvoc_gpushareddataConstruct(arg_pData, arg_pCallContext, arg_pParams) gpushareddataConstruct_IMPL(arg_pData, arg_pCallContext, arg_pParams) +void gpushareddataDestruct_IMPL(struct GpuUserSharedData *pData); + +#define __nvoc_gpushareddataDestruct(pData) gpushareddataDestruct_IMPL(pData) #undef PRIVATE_FIELD #endif // GPU_USER_SHARED_DATA_H - #ifdef __cplusplus } // extern "C" #endif + #endif // _G_GPU_USER_SHARED_DATA_NVOC_H_ diff --git a/src/nvidia/generated/g_gpu_vaspace_nvoc.c b/src/nvidia/generated/g_gpu_vaspace_nvoc.c index e4740e01ee..0ceee5a36b 100644 --- a/src/nvidia/generated/g_gpu_vaspace_nvoc.c +++ b/src/nvidia/generated/g_gpu_vaspace_nvoc.c @@ -70,8 +70,8 @@ static NV_STATUS __nvoc_thunk_OBJGVASPACE_vaspaceConstruct_(struct OBJVASPACE *p return gvaspaceConstruct_((struct OBJGVASPACE *)(((unsigned char *)pGVAS) - __nvoc_rtti_OBJGVASPACE_OBJVASPACE.offset), classId, vaspaceId, vaStart, vaLimit, vaStartInternal, vaLimitInternal, flags); } -static NV_STATUS __nvoc_thunk_OBJGVASPACE_vaspaceReserveMempool(struct OBJVASPACE *pGVAS, struct OBJGPU *pGpu, NvHandle hClient, NvU64 size, NvU64 pageSizeLockMask, NvU32 flags) { - return gvaspaceReserveMempool((struct OBJGVASPACE *)(((unsigned char *)pGVAS) - __nvoc_rtti_OBJGVASPACE_OBJVASPACE.offset), pGpu, hClient, size, pageSizeLockMask, flags); +static NV_STATUS __nvoc_thunk_OBJGVASPACE_vaspaceReserveMempool(struct OBJVASPACE *pGVAS, struct OBJGPU *pGpu, struct Device *pDevice, NvU64 size, NvU64 pageSizeLockMask, NvU32 flags) { + return gvaspaceReserveMempool((struct OBJGVASPACE *)(((unsigned char *)pGVAS) - __nvoc_rtti_OBJGVASPACE_OBJVASPACE.offset), pGpu, pDevice, size, pageSizeLockMask, flags); } static NV_STATUS __nvoc_thunk_OBJGVASPACE_vaspaceAlloc(struct OBJVASPACE *pVAS, NvU64 size, NvU64 align, NvU64 rangeLo, NvU64 rangeHi, NvU64 pageSizeLockMask, VAS_ALLOC_FLAGS flags, NvU64 *pAddr) { @@ -170,10 +170,6 @@ static NV_STATUS __nvoc_thunk_OBJGVASPACE_vaspaceSetPteInfo(struct OBJVASPACE *p return gvaspaceSetPteInfo((struct OBJGVASPACE *)(((unsigned char *)pVAS) - __nvoc_rtti_OBJGVASPACE_OBJVASPACE.offset), pGpu, pParams); } -static NvBool __nvoc_thunk_OBJGVASPACE_vaspaceIsInternalVaRestricted(struct OBJVASPACE *pGVAS) { - return gvaspaceIsInternalVaRestricted((struct OBJGVASPACE *)(((unsigned char *)pGVAS) - __nvoc_rtti_OBJGVASPACE_OBJVASPACE.offset)); -} - static NV_STATUS __nvoc_thunk_OBJGVASPACE_vaspaceFreeV2(struct OBJVASPACE *pGVAS, NvU64 vAddr, NvU64 *pSize) { return gvaspaceFreeV2((struct OBJGVASPACE *)(((unsigned char *)pGVAS) - __nvoc_rtti_OBJGVASPACE_OBJVASPACE.offset), vAddr, pSize); } @@ -272,8 +268,6 @@ static void __nvoc_init_funcTable_OBJGVASPACE_1(OBJGVASPACE *pThis) { pThis->__gvaspaceSetPteInfo__ = &gvaspaceSetPteInfo_IMPL; - pThis->__gvaspaceIsInternalVaRestricted__ = &gvaspaceIsInternalVaRestricted_IMPL; - pThis->__gvaspaceFreeV2__ = &gvaspaceFreeV2_IMPL; pThis->__nvoc_base_OBJVASPACE.__vaspaceConstruct___ = &__nvoc_thunk_OBJGVASPACE_vaspaceConstruct_; @@ -328,8 +322,6 @@ static void __nvoc_init_funcTable_OBJGVASPACE_1(OBJGVASPACE *pThis) { pThis->__nvoc_base_OBJVASPACE.__vaspaceSetPteInfo__ = &__nvoc_thunk_OBJGVASPACE_vaspaceSetPteInfo; - pThis->__nvoc_base_OBJVASPACE.__vaspaceIsInternalVaRestricted__ = &__nvoc_thunk_OBJGVASPACE_vaspaceIsInternalVaRestricted; - pThis->__nvoc_base_OBJVASPACE.__vaspaceFreeV2__ = &__nvoc_thunk_OBJGVASPACE_vaspaceFreeV2; pThis->__gvaspaceGetVaLimit__ = &__nvoc_thunk_OBJVASPACE_gvaspaceGetVaLimit; diff --git a/src/nvidia/generated/g_gpu_vaspace_nvoc.h b/src/nvidia/generated/g_gpu_vaspace_nvoc.h index e1fa9d77b3..e9fb7a1b38 100644 --- a/src/nvidia/generated/g_gpu_vaspace_nvoc.h +++ b/src/nvidia/generated/g_gpu_vaspace_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -88,6 +88,9 @@ typedef struct KernelChannelGroup KernelChannelGroup; #define SPLIT_VAS_SERVER_RM_MANAGED_VA_START 0x100000000ULL // 4GB #define SPLIT_VAS_SERVER_RM_MANAGED_VA_SIZE 0x20000000ULL // 512MB +// Size of Host RM managed VA space required when Full SRIOV or GSP-RM are enabled +#define VA_SIZE_FULL_SRIOV_OR_GSP 0x20000000ULL // 512MB + /*! * Tracks ranges currently mapped (per-GPU). */ @@ -219,7 +222,7 @@ struct OBJGVASPACE { struct OBJVASPACE *__nvoc_pbase_OBJVASPACE; struct OBJGVASPACE *__nvoc_pbase_OBJGVASPACE; NV_STATUS (*__gvaspaceConstruct___)(struct OBJGVASPACE *, NvU32, NvU32, NvU64, NvU64, NvU64, NvU64, NvU32); - NV_STATUS (*__gvaspaceReserveMempool__)(struct OBJGVASPACE *, struct OBJGPU *, NvHandle, NvU64, NvU64, NvU32); + NV_STATUS (*__gvaspaceReserveMempool__)(struct OBJGVASPACE *, struct OBJGPU *, struct Device *, NvU64, NvU64, NvU32); NV_STATUS (*__gvaspaceAlloc__)(struct OBJGVASPACE *, NvU64, NvU64, NvU64, NvU64, NvU64, VAS_ALLOC_FLAGS, NvU64 *); NV_STATUS (*__gvaspaceFree__)(struct OBJGVASPACE *, NvU64); NV_STATUS (*__gvaspaceApplyDefaultAlignment__)(struct OBJGVASPACE *, const FB_ALLOC_INFO *, NvU64 *, NvU64 *, NvU64 *); @@ -244,7 +247,6 @@ struct OBJGVASPACE { NV_STATUS (*__gvaspaceGetPageTableInfo__)(struct OBJGVASPACE *, NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS *); NV_STATUS (*__gvaspaceGetPteInfo__)(struct OBJGVASPACE *, struct OBJGPU *, NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS *, RmPhysAddr *); NV_STATUS (*__gvaspaceSetPteInfo__)(struct OBJGVASPACE *, struct OBJGPU *, NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS *); - NvBool (*__gvaspaceIsInternalVaRestricted__)(struct OBJGVASPACE *); NV_STATUS (*__gvaspaceFreeV2__)(struct OBJGVASPACE *, NvU64, NvU64 *); NvU64 (*__gvaspaceGetVaLimit__)(struct OBJGVASPACE *); NvU64 (*__gvaspaceGetVaStart__)(struct OBJGVASPACE *); @@ -302,7 +304,7 @@ NV_STATUS __nvoc_objCreate_OBJGVASPACE(OBJGVASPACE**, Dynamic*, NvU32); __nvoc_objCreate_OBJGVASPACE((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) #define gvaspaceConstruct_(pGVAS, classId, vaspaceId, vaStart, vaLimit, vaStartInternal, vaLimitInternal, flags) gvaspaceConstruct__DISPATCH(pGVAS, classId, vaspaceId, vaStart, vaLimit, vaStartInternal, vaLimitInternal, flags) -#define gvaspaceReserveMempool(pGVAS, pGpu, hClient, size, pageSizeLockMask, flags) gvaspaceReserveMempool_DISPATCH(pGVAS, pGpu, hClient, size, pageSizeLockMask, flags) +#define gvaspaceReserveMempool(pGVAS, pGpu, pDevice, size, pageSizeLockMask, flags) gvaspaceReserveMempool_DISPATCH(pGVAS, pGpu, pDevice, size, pageSizeLockMask, flags) #define gvaspaceAlloc(pVAS, size, align, rangeLo, rangeHi, pageSizeLockMask, flags, pAddr) gvaspaceAlloc_DISPATCH(pVAS, size, align, rangeLo, rangeHi, pageSizeLockMask, flags, pAddr) #define gvaspaceFree(pVAS, vAddr) gvaspaceFree_DISPATCH(pVAS, vAddr) #define gvaspaceApplyDefaultAlignment(pVAS, pAllocInfo, pAlign, pSize, pPageSizeLockMask) gvaspaceApplyDefaultAlignment_DISPATCH(pVAS, pAllocInfo, pAlign, pSize, pPageSizeLockMask) @@ -327,7 +329,6 @@ NV_STATUS __nvoc_objCreate_OBJGVASPACE(OBJGVASPACE**, Dynamic*, NvU32); #define gvaspaceGetPageTableInfo(pVAS, pParams) gvaspaceGetPageTableInfo_DISPATCH(pVAS, pParams) #define gvaspaceGetPteInfo(pVAS, pGpu, pParams, pPhysAddr) gvaspaceGetPteInfo_DISPATCH(pVAS, pGpu, pParams, pPhysAddr) #define gvaspaceSetPteInfo(pVAS, pGpu, pParams) gvaspaceSetPteInfo_DISPATCH(pVAS, pGpu, pParams) -#define gvaspaceIsInternalVaRestricted(pGVAS) gvaspaceIsInternalVaRestricted_DISPATCH(pGVAS) #define gvaspaceFreeV2(pGVAS, vAddr, pSize) gvaspaceFreeV2_DISPATCH(pGVAS, vAddr, pSize) #define gvaspaceGetVaLimit(pVAS) gvaspaceGetVaLimit_DISPATCH(pVAS) #define gvaspaceGetVaStart(pVAS) gvaspaceGetVaStart_DISPATCH(pVAS) @@ -337,10 +338,10 @@ static inline NV_STATUS gvaspaceConstruct__DISPATCH(struct OBJGVASPACE *pGVAS, N return pGVAS->__gvaspaceConstruct___(pGVAS, classId, vaspaceId, vaStart, vaLimit, vaStartInternal, vaLimitInternal, flags); } -NV_STATUS gvaspaceReserveMempool_IMPL(struct OBJGVASPACE *pGVAS, struct OBJGPU *pGpu, NvHandle hClient, NvU64 size, NvU64 pageSizeLockMask, NvU32 flags); +NV_STATUS gvaspaceReserveMempool_IMPL(struct OBJGVASPACE *pGVAS, struct OBJGPU *pGpu, struct Device *pDevice, NvU64 size, NvU64 pageSizeLockMask, NvU32 flags); -static inline NV_STATUS gvaspaceReserveMempool_DISPATCH(struct OBJGVASPACE *pGVAS, struct OBJGPU *pGpu, NvHandle hClient, NvU64 size, NvU64 pageSizeLockMask, NvU32 flags) { - return pGVAS->__gvaspaceReserveMempool__(pGVAS, pGpu, hClient, size, pageSizeLockMask, flags); +static inline NV_STATUS gvaspaceReserveMempool_DISPATCH(struct OBJGVASPACE *pGVAS, struct OBJGPU *pGpu, struct Device *pDevice, NvU64 size, NvU64 pageSizeLockMask, NvU32 flags) { + return pGVAS->__gvaspaceReserveMempool__(pGVAS, pGpu, pDevice, size, pageSizeLockMask, flags); } NV_STATUS gvaspaceAlloc_IMPL(struct OBJGVASPACE *pVAS, NvU64 size, NvU64 align, NvU64 rangeLo, NvU64 rangeHi, NvU64 pageSizeLockMask, VAS_ALLOC_FLAGS flags, NvU64 *pAddr); @@ -487,12 +488,6 @@ static inline NV_STATUS gvaspaceSetPteInfo_DISPATCH(struct OBJGVASPACE *pVAS, st return pVAS->__gvaspaceSetPteInfo__(pVAS, pGpu, pParams); } -NvBool gvaspaceIsInternalVaRestricted_IMPL(struct OBJGVASPACE *pGVAS); - -static inline NvBool gvaspaceIsInternalVaRestricted_DISPATCH(struct OBJGVASPACE *pGVAS) { - return pGVAS->__gvaspaceIsInternalVaRestricted__(pGVAS); -} - NV_STATUS gvaspaceFreeV2_IMPL(struct OBJGVASPACE *pGVAS, NvU64 vAddr, NvU64 *pSize); static inline NV_STATUS gvaspaceFreeV2_DISPATCH(struct OBJGVASPACE *pGVAS, NvU64 vAddr, NvU64 *pSize) { @@ -735,6 +730,17 @@ static inline NV_STATUS gvaspaceReserveSplitVaSpace(struct OBJGVASPACE *pGVAS, s #define gvaspaceReserveSplitVaSpace(pGVAS, pGpu) gvaspaceReserveSplitVaSpace_IMPL(pGVAS, pGpu) #endif //__nvoc_gpu_vaspace_h_disabled +NvBool gvaspaceIsInternalVaRestricted_IMPL(struct OBJGVASPACE *pGVAS); + +#ifdef __nvoc_gpu_vaspace_h_disabled +static inline NvBool gvaspaceIsInternalVaRestricted(struct OBJGVASPACE *pGVAS) { + NV_ASSERT_FAILED_PRECOMP("OBJGVASPACE was disabled!"); + return NV_FALSE; +} +#else //__nvoc_gpu_vaspace_h_disabled +#define gvaspaceIsInternalVaRestricted(pGVAS) gvaspaceIsInternalVaRestricted_IMPL(pGVAS) +#endif //__nvoc_gpu_vaspace_h_disabled + NV_STATUS gvaspaceCopyServerReservedPdes_IMPL(struct OBJGVASPACE *pGVAS, struct OBJGPU *pGpu, NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS *pCopyServerReservedPdesParams); #ifdef __nvoc_gpu_vaspace_h_disabled @@ -754,4 +760,5 @@ static inline NV_STATUS gvaspaceCopyServerReservedPdes(struct OBJGVASPACE *pGVAS #ifdef __cplusplus } // extern "C" #endif + #endif // _G_GPU_VASPACE_NVOC_H_ diff --git a/src/nvidia/generated/g_gsync_api_nvoc.c b/src/nvidia/generated/g_gsync_api_nvoc.c index 14b264be51..cb4f80aea1 100644 --- a/src/nvidia/generated/g_gsync_api_nvoc.c +++ b/src/nvidia/generated/g_gsync_api_nvoc.c @@ -258,12 +258,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_GSyncApi #endif }, { /* [3] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) gsyncapiCtrlCmdGsyncSetControlParams_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*flags=*/ 0x4u, /*accessRight=*/0x0u, /*methodId=*/ 0x30f10104u, /*paramSize=*/ sizeof(NV30F1_CTRL_GSYNC_SET_CONTROL_PARAMS_PARAMS), @@ -318,12 +318,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_GSyncApi #endif }, { /* [7] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) gsyncapiCtrlCmdGsyncSetControlSync_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*flags=*/ 0x4u, /*accessRight=*/0x0u, /*methodId=*/ 0x30f10111u, /*paramSize=*/ sizeof(NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_PARAMS), @@ -333,12 +333,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_GSyncApi #endif }, { /* [8] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) gsyncapiCtrlCmdGsyncSetControlUnsync_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*flags=*/ 0x4u, /*accessRight=*/0x0u, /*methodId=*/ 0x30f10112u, /*paramSize=*/ sizeof(NV30F1_CTRL_GSYNC_SET_CONTROL_UNSYNC_PARAMS), @@ -438,12 +438,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_GSyncApi #endif }, { /* [15] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) gsyncapiCtrlCmdGsyncSetControlInterlaceMode_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*flags=*/ 0x4u, /*accessRight=*/0x0u, /*methodId=*/ 0x30f10141u, /*paramSize=*/ sizeof(NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS), @@ -528,12 +528,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_GSyncApi #endif }, { /* [21] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) gsyncapiCtrlCmdGsyncSetControlStereoLockMode_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*flags=*/ 0x4u, /*accessRight=*/0x0u, /*methodId=*/ 0x30f10172u, /*paramSize=*/ sizeof(NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS), @@ -558,12 +558,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_GSyncApi #endif }, { /* [23] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) gsyncapiCtrlCmdGsyncReadRegister_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*flags=*/ 0x4u, /*accessRight=*/0x0u, /*methodId=*/ 0x30f10180u, /*paramSize=*/ sizeof(NV30F1_CTRL_GSYNC_READ_REGISTER_PARAMS), @@ -588,12 +588,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_GSyncApi #endif }, { /* [25] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) gsyncapiCtrlCmdGsyncSetLocalSync_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*flags=*/ 0x4u, /*accessRight=*/0x0u, /*methodId=*/ 0x30f10185u, /*paramSize=*/ sizeof(NV30F1_CTRL_GSYNC_SET_LOCAL_SYNC_PARAMS), @@ -603,12 +603,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_GSyncApi #endif }, { /* [26] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) gsyncapiCtrlCmdGsyncConfigFlash_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*flags=*/ 0x4u, /*accessRight=*/0x0u, /*methodId=*/ 0x30f10186u, /*paramSize=*/ sizeof(NV30F1_CTRL_CMD_GSYNC_CONFIG_FLASH_PARAMS), @@ -633,12 +633,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_GSyncApi #endif }, { /* [28] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) gsyncapiCtrlCmdGsyncSetHouseSyncMode_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*flags=*/ 0x4u, /*accessRight=*/0x0u, /*methodId=*/ 0x30f10188u, /*paramSize=*/ sizeof(NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_PARAMS), @@ -713,7 +713,7 @@ static void __nvoc_init_funcTable_GSyncApi_1(GSyncApi *pThis) { pThis->__gsyncapiCtrlCmdGsyncGetControlParams__ = &gsyncapiCtrlCmdGsyncGetControlParams_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) pThis->__gsyncapiCtrlCmdGsyncSetControlParams__ = &gsyncapiCtrlCmdGsyncSetControlParams_IMPL; #endif @@ -721,11 +721,11 @@ static void __nvoc_init_funcTable_GSyncApi_1(GSyncApi *pThis) { pThis->__gsyncapiCtrlCmdGsyncGetControlSync__ = &gsyncapiCtrlCmdGsyncGetControlSync_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) pThis->__gsyncapiCtrlCmdGsyncSetControlSync__ = &gsyncapiCtrlCmdGsyncSetControlSync_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) pThis->__gsyncapiCtrlCmdGsyncSetControlUnsync__ = &gsyncapiCtrlCmdGsyncSetControlUnsync_IMPL; #endif @@ -753,7 +753,7 @@ static void __nvoc_init_funcTable_GSyncApi_1(GSyncApi *pThis) { pThis->__gsyncapiCtrlCmdGsyncGetControlInterlaceMode__ = &gsyncapiCtrlCmdGsyncGetControlInterlaceMode_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) pThis->__gsyncapiCtrlCmdGsyncSetControlInterlaceMode__ = &gsyncapiCtrlCmdGsyncSetControlInterlaceMode_IMPL; #endif @@ -785,11 +785,11 @@ static void __nvoc_init_funcTable_GSyncApi_1(GSyncApi *pThis) { pThis->__gsyncapiCtrlCmdGsyncGetControlStereoLockMode__ = &gsyncapiCtrlCmdGsyncGetControlStereoLockMode_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) pThis->__gsyncapiCtrlCmdGsyncSetControlStereoLockMode__ = &gsyncapiCtrlCmdGsyncSetControlStereoLockMode_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) pThis->__gsyncapiCtrlCmdGsyncReadRegister__ = &gsyncapiCtrlCmdGsyncReadRegister_IMPL; #endif @@ -797,11 +797,11 @@ static void __nvoc_init_funcTable_GSyncApi_1(GSyncApi *pThis) { pThis->__gsyncapiCtrlCmdGsyncWriteRegister__ = &gsyncapiCtrlCmdGsyncWriteRegister_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) pThis->__gsyncapiCtrlCmdGsyncSetLocalSync__ = &gsyncapiCtrlCmdGsyncSetLocalSync_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) pThis->__gsyncapiCtrlCmdGsyncConfigFlash__ = &gsyncapiCtrlCmdGsyncConfigFlash_IMPL; #endif @@ -809,7 +809,7 @@ static void __nvoc_init_funcTable_GSyncApi_1(GSyncApi *pThis) { pThis->__gsyncapiCtrlCmdGsyncGetHouseSyncMode__ = &gsyncapiCtrlCmdGsyncGetHouseSyncMode_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) pThis->__gsyncapiCtrlCmdGsyncSetHouseSyncMode__ = &gsyncapiCtrlCmdGsyncSetHouseSyncMode_IMPL; #endif diff --git a/src/nvidia/generated/g_gsync_api_nvoc.h b/src/nvidia/generated/g_gsync_api_nvoc.h index 78d6bf0e3c..a6b6bc2870 100644 --- a/src/nvidia/generated/g_gsync_api_nvoc.h +++ b/src/nvidia/generated/g_gsync_api_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2006-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -498,4 +498,5 @@ void CliNotifyGsyncEvent (NvU32, NvU32); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_GSYNC_API_NVOC_H_ diff --git a/src/nvidia/generated/g_gsync_nvoc.h b/src/nvidia/generated/g_gsync_nvoc.h index cf9ad3fa95..bf46da9a75 100644 --- a/src/nvidia/generated/g_gsync_nvoc.h +++ b/src/nvidia/generated/g_gsync_nvoc.h @@ -288,9 +288,9 @@ NvBool gsyncAreAllGpusInConfigAttachedToSameGsyncBoard(struct OBJGPU **pGpu OBJGSYNC *gsyncmgrGetGsync(struct OBJGPU *); #ifdef DEBUG -void gsyncDbgPrintGsyncEvents(NvU32 DebugLevel, NvU32 events, NvU32 iface); +void gsyncDbgPrintGsyncEvents(NvU32 events, NvU32 iface); #else -#define gsyncDbgPrintGsyncEvents(DebugLevel, events, iface) +#define gsyncDbgPrintGsyncEvents(events, iface) #endif #endif // GSYNC_H_ @@ -298,4 +298,5 @@ void gsyncDbgPrintGsyncEvents(NvU32 DebugLevel, NvU32 events, NvU32 iface #ifdef __cplusplus } // extern "C" #endif + #endif // _G_GSYNC_NVOC_H_ diff --git a/src/nvidia/generated/g_hal.h b/src/nvidia/generated/g_hal.h index 2434e90802..63f98f2914 100644 --- a/src/nvidia/generated/g_hal.h +++ b/src/nvidia/generated/g_hal.h @@ -123,6 +123,7 @@ typedef enum HAL_IMPL_AD106, HAL_IMPL_AD107, HAL_IMPL_GH100, + HAL_IMPL_GH202, HAL_IMPL_T001_FERMI_NOT_EXIST, HAL_IMPL_T124, HAL_IMPL_T132, @@ -131,8 +132,8 @@ typedef enum HAL_IMPL_T194, HAL_IMPL_T002_TURING_NOT_EXIST, HAL_IMPL_T234, - HAL_IMPL_T003_HOPPER_NOT_EXIST, - HAL_IMPL_T004_ADA_NOT_EXIST, + HAL_IMPL_T003_ADA_NOT_EXIST, + HAL_IMPL_T004_HOPPER_NOT_EXIST, HAL_IMPL_T234D, HAL_IMPL_AMODEL, diff --git a/src/nvidia/generated/g_hal_archimpl.h b/src/nvidia/generated/g_hal_archimpl.h index e29767c6ce..18a41bdcab 100644 --- a/src/nvidia/generated/g_hal_archimpl.h +++ b/src/nvidia/generated/g_hal_archimpl.h @@ -83,6 +83,7 @@ const struct ChipID { NV_PMC_BOOT_0_ARCHITECTURE_AD100, NV_PMC_BOOT_0_IMPLEMENTATION_6, 0x0 } , // AD106 { NV_PMC_BOOT_0_ARCHITECTURE_AD100, NV_PMC_BOOT_0_IMPLEMENTATION_7, 0x0 } , // AD107 { NV_PMC_BOOT_0_ARCHITECTURE_GH100, NV_PMC_BOOT_0_IMPLEMENTATION_0, 0x0 } , // GH100 + { 0x0, 0x0, 0x0 } , // GH202 (disabled) { 0x0, 0x0, 0x0 } , // T001_FERMI_NOT_EXIST (disabled) { 0x0, 0x0, 0x0 } , // T124 (disabled) { 0x0, 0x0, 0x0 } , // T132 (disabled) @@ -91,8 +92,8 @@ const struct ChipID { 0x0, 0x0, 0x0 } , // T194 (disabled) { 0x0, 0x0, 0x0 } , // T002_TURING_NOT_EXIST (disabled) { 0x0, 0x0, 0x0 } , // T234 (disabled) - { 0x0, 0x0, 0x0 } , // T003_HOPPER_NOT_EXIST (disabled) - { 0x0, 0x0, 0x0 } , // T004_ADA_NOT_EXIST (disabled) + { 0x0, 0x0, 0x0 } , // T003_ADA_NOT_EXIST (disabled) + { 0x0, 0x0, 0x0 } , // T004_HOPPER_NOT_EXIST (disabled) { 0x0, 0x0, 0x0 } , // T234D (disabled) { 0x0, 0x0, 0x0 } , // AMODEL (disabled) diff --git a/src/nvidia/generated/g_hal_mgr_nvoc.h b/src/nvidia/generated/g_hal_mgr_nvoc.h index 435e420701..4a4bd80776 100644 --- a/src/nvidia/generated/g_hal_mgr_nvoc.h +++ b/src/nvidia/generated/g_hal_mgr_nvoc.h @@ -63,7 +63,7 @@ struct OBJHALMGR { struct Object __nvoc_base_Object; struct Object *__nvoc_pbase_Object; struct OBJHALMGR *__nvoc_pbase_OBJHALMGR; - struct OBJHAL *pHalList[68]; + struct OBJHAL *pHalList[69]; }; #ifndef __NVOC_CLASS_OBJHALMGR_TYPEDEF__ @@ -141,4 +141,5 @@ static inline struct OBJHAL *halmgrGetHal(struct OBJHALMGR *arg0, NvU32 arg1) { #ifdef __cplusplus } // extern "C" #endif + #endif // _G_HAL_MGR_NVOC_H_ diff --git a/src/nvidia/generated/g_hal_nvoc.h b/src/nvidia/generated/g_hal_nvoc.h index 481d61fdfc..ee7711340f 100644 --- a/src/nvidia/generated/g_hal_nvoc.h +++ b/src/nvidia/generated/g_hal_nvoc.h @@ -138,4 +138,5 @@ static inline PMODULEDESCRIPTOR objhalGetModuleDescriptor(struct OBJHAL *pHal) { #ifdef __cplusplus } // extern "C" #endif + #endif // _G_HAL_NVOC_H_ diff --git a/src/nvidia/generated/g_hda_codec_api_nvoc.h b/src/nvidia/generated/g_hda_codec_api_nvoc.h index 9efd542907..0fb4cc5c04 100644 --- a/src/nvidia/generated/g_hda_codec_api_nvoc.h +++ b/src/nvidia/generated/g_hda_codec_api_nvoc.h @@ -245,4 +245,5 @@ NV_STATUS hdacodecConstruct_IMPL(struct Hdacodec *arg_pHdacodecApi, struct CALL_ #ifdef __cplusplus } // extern "C" #endif + #endif // _G_HDA_CODEC_API_NVOC_H_ diff --git a/src/nvidia/generated/g_heap_nvoc.h b/src/nvidia/generated/g_heap_nvoc.h index 91a9ab319f..2c7ad137a8 100644 --- a/src/nvidia/generated/g_heap_nvoc.h +++ b/src/nvidia/generated/g_heap_nvoc.h @@ -381,15 +381,15 @@ static inline NV_STATUS heapAlloc(struct OBJGPU *arg0, NvHandle arg1, struct Hea #define heapAlloc(arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9, arg10) heapAlloc_IMPL(arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9, arg10) #endif //__nvoc_heap_h_disabled -NV_STATUS heapFree_IMPL(struct OBJGPU *pGpu, struct Heap *pHeap, NvU32 owner, MEMORY_DESCRIPTOR *pMemDesc); +NV_STATUS heapFree_IMPL(struct OBJGPU *arg0, struct Heap *arg1, NvHandle hClient, NvHandle hDevice, NvU32 owner, MEMORY_DESCRIPTOR *pMemDesc); #ifdef __nvoc_heap_h_disabled -static inline NV_STATUS heapFree(struct OBJGPU *pGpu, struct Heap *pHeap, NvU32 owner, MEMORY_DESCRIPTOR *pMemDesc) { +static inline NV_STATUS heapFree(struct OBJGPU *arg0, struct Heap *arg1, NvHandle hClient, NvHandle hDevice, NvU32 owner, MEMORY_DESCRIPTOR *pMemDesc) { NV_ASSERT_FAILED_PRECOMP("Heap was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_heap_h_disabled -#define heapFree(pGpu, pHeap, owner, pMemDesc) heapFree_IMPL(pGpu, pHeap, owner, pMemDesc) +#define heapFree(arg0, arg1, hClient, hDevice, owner, pMemDesc) heapFree_IMPL(arg0, arg1, hClient, hDevice, owner, pMemDesc) #endif //__nvoc_heap_h_disabled NV_STATUS heapReference_IMPL(struct OBJGPU *arg0, struct Heap *arg1, NvU32 arg2, MEMORY_DESCRIPTOR *arg3); @@ -695,4 +695,5 @@ static inline NV_STATUS heapStorePendingBlackList(struct OBJGPU *arg0, struct He #ifdef __cplusplus } // extern "C" #endif + #endif // _G_HEAP_NVOC_H_ diff --git a/src/nvidia/generated/g_host_eng_nvoc.h b/src/nvidia/generated/g_host_eng_nvoc.h index 0fcfed85c8..050909957a 100644 --- a/src/nvidia/generated/g_host_eng_nvoc.h +++ b/src/nvidia/generated/g_host_eng_nvoc.h @@ -103,4 +103,5 @@ static inline NV_STATUS hostengHaltAndReset_DISPATCH(struct OBJGPU *pGpu, struct #ifdef __cplusplus } // extern "C" #endif + #endif // _G_HOST_ENG_NVOC_H_ diff --git a/src/nvidia/generated/g_hw_resources_nvoc.c b/src/nvidia/generated/g_hw_resources_nvoc.c index 61e32e807d..b634caa793 100644 --- a/src/nvidia/generated/g_hw_resources_nvoc.c +++ b/src/nvidia/generated/g_hw_resources_nvoc.c @@ -113,6 +113,10 @@ static NV_STATUS __nvoc_thunk_Memory_hwresGetMapAddrSpace(struct MemoryHwResourc return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryHwResources_Memory.offset), pCallContext, mapFlags, pAddrSpace); } +static NvBool __nvoc_thunk_Memory_hwresIsExportAllowed(struct MemoryHwResources *pMemory) { + return memIsExportAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryHwResources_Memory.offset)); +} + static NvU32 __nvoc_thunk_RsResource_hwresGetRefCount(struct MemoryHwResources *pResource) { return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RsResource.offset)); } @@ -244,6 +248,8 @@ static void __nvoc_init_funcTable_MemoryHwResources_1(MemoryHwResources *pThis) pThis->__hwresGetMapAddrSpace__ = &__nvoc_thunk_Memory_hwresGetMapAddrSpace; + pThis->__hwresIsExportAllowed__ = &__nvoc_thunk_Memory_hwresIsExportAllowed; + pThis->__hwresGetRefCount__ = &__nvoc_thunk_RsResource_hwresGetRefCount; pThis->__hwresAddAdditionalDependants__ = &__nvoc_thunk_RsResource_hwresAddAdditionalDependants; diff --git a/src/nvidia/generated/g_hw_resources_nvoc.h b/src/nvidia/generated/g_hw_resources_nvoc.h index 3f7d3fa51b..b8052b7fbe 100644 --- a/src/nvidia/generated/g_hw_resources_nvoc.h +++ b/src/nvidia/generated/g_hw_resources_nvoc.h @@ -58,6 +58,7 @@ struct MemoryHwResources { NvBool (*__hwresShareCallback__)(struct MemoryHwResources *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__hwresMapTo__)(struct MemoryHwResources *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__hwresGetMapAddrSpace__)(struct MemoryHwResources *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvBool (*__hwresIsExportAllowed__)(struct MemoryHwResources *); NvU32 (*__hwresGetRefCount__)(struct MemoryHwResources *); void (*__hwresAddAdditionalDependants__)(struct RsClient *, struct MemoryHwResources *, RsResourceRef *); NV_STATUS (*__hwresControl_Prologue__)(struct MemoryHwResources *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -113,6 +114,7 @@ NV_STATUS __nvoc_objCreate_MemoryHwResources(MemoryHwResources**, Dynamic*, NvU3 #define hwresShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) hwresShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define hwresMapTo(pResource, pParams) hwresMapTo_DISPATCH(pResource, pParams) #define hwresGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) hwresGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define hwresIsExportAllowed(pMemory) hwresIsExportAllowed_DISPATCH(pMemory) #define hwresGetRefCount(pResource) hwresGetRefCount_DISPATCH(pResource) #define hwresAddAdditionalDependants(pClient, pResource, pReference) hwresAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define hwresControl_Prologue(pResource, pCallContext, pParams) hwresControl_Prologue_DISPATCH(pResource, pCallContext, pParams) @@ -155,6 +157,10 @@ static inline NV_STATUS hwresGetMapAddrSpace_DISPATCH(struct MemoryHwResources * return pMemory->__hwresGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); } +static inline NvBool hwresIsExportAllowed_DISPATCH(struct MemoryHwResources *pMemory) { + return pMemory->__hwresIsExportAllowed__(pMemory); +} + static inline NvU32 hwresGetRefCount_DISPATCH(struct MemoryHwResources *pResource) { return pResource->__hwresGetRefCount__(pResource); } @@ -249,4 +255,5 @@ void hwresDestruct_IMPL(struct MemoryHwResources *pMemoryHwResources); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_HW_RESOURCES_NVOC_H_ diff --git a/src/nvidia/generated/g_hypervisor_nvoc.h b/src/nvidia/generated/g_hypervisor_nvoc.h index 80c55dc5c4..5d66a5672e 100644 --- a/src/nvidia/generated/g_hypervisor_nvoc.h +++ b/src/nvidia/generated/g_hypervisor_nvoc.h @@ -273,4 +273,5 @@ extern HYPERVISOR_OPS vmwareHypervisorOps; #ifdef __cplusplus } // extern "C" #endif + #endif // _G_HYPERVISOR_NVOC_H_ diff --git a/src/nvidia/generated/g_i2c_api_nvoc.h b/src/nvidia/generated/g_i2c_api_nvoc.h index 9ee62c7621..23f546cef8 100644 --- a/src/nvidia/generated/g_i2c_api_nvoc.h +++ b/src/nvidia/generated/g_i2c_api_nvoc.h @@ -288,4 +288,5 @@ void i2capiDestruct_IMPL(struct I2cApi *pI2cApi); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_I2C_API_NVOC_H_ diff --git a/src/nvidia/generated/g_intr_nvoc.h b/src/nvidia/generated/g_intr_nvoc.h index e4b6095136..9acb41e1c3 100644 --- a/src/nvidia/generated/g_intr_nvoc.h +++ b/src/nvidia/generated/g_intr_nvoc.h @@ -69,6 +69,8 @@ extern "C" { /** * @brief Each entry corresponds to a top level interrupt + * + * This structure will eventually be replaced by #InterruptEntry. */ typedef struct { @@ -92,6 +94,57 @@ typedef struct MAKE_VECTOR(InterruptTable, INTR_TABLE_ENTRY); + +/*! + * Mapping from leaf level interrupt to conceptual interrupt name. + * + * - The interrupt vector is implicit from the tree / index of an array which + * contains this struct. + * - The target is a conceptual name that represents the interrupt identified by + * (MC_ENGINE_IDX*, INTR_KIND*) pair. + * - A service routine may or may not be actually registered to handle the + * interrupt. + * - Multiple physical vectors can map to the same conceptual interrupt. + */ +typedef struct +{ + /*! + * MC_ENGINE_IDX* value. + * + * A value of #MC_ENGINE_IDX_NULL means that the vector corresponding to + * this entry is unused. Use #interruptEntryIsEmpty to check this. + */ + NvU16 mcEngine; + + /*! + * INTR_KIND_* value. + * + * This allows multiple logically separate interrupts to map to a service + * routine via a common mcEngine value. + */ + INTR_KIND intrKind; + + /*! + * If the interrupt should be handled. + * + * If this is false: + * - The interrupt may need to be visible for clients, VF, etc (error + * containment). + * - It can be an interrupt to be triggered to notify RM running in a + * different environment: doorbell, GSP triggered notifications to CPU. + * - The interrupt does not need to be serviced. There should be no + * corresponding entry in the #intrServiceTable. + */ + NvBool bService; +} InterruptEntry; + +static NV_FORCEINLINE NvBool +interruptEntryIsEmpty(const InterruptEntry *pEntry) +{ + return pEntry->mcEngine == MC_ENGINE_IDX_NULL; +} + + // // Default value for intrStuckThreshold #define INTR_STUCK_THRESHOLD 1000 @@ -170,6 +223,19 @@ typedef struct } INTR_MASK_CTX; +//! +//! List of interrupt trees that RM sees. +//! +//! Kernel RM should determine number of implemented vectors using the actual +//! interrupt table fetched. +//! +typedef enum +{ + INTR_TREE_CPU, + INTR_TREE_COUNT +} INTR_TREE; + + // // IntrMask Locking Flag Defines // @@ -244,10 +310,12 @@ struct Intr { NvU32 accessCntrIntrVector; NvU32 displayIntrVector; NvU64 intrTopEnMask; - IntrServiceRecord intrServiceTable[167]; + InterruptTable intrTable; + IntrServiceRecord intrServiceTable[168]; + InterruptEntry *(vectorToMcIdx[1]); + NvLength vectorToMcIdxCounts[1]; NvBool bDefaultNonstallNotify; NvBool bUseLegacyVectorAssignment; - InterruptTable intrTable; NV2080_INTR_CATEGORY_SUBTREE_MAP subtreeMap[7]; NvBool bDpcStarted; union MC_ENGINE_BITVECTOR pmcIntrPending; @@ -625,6 +693,40 @@ static inline void intrClearLeafVector(OBJGPU *pGpu, struct Intr *pIntr, NvU32 v #define intrClearLeafVector_HAL(pGpu, pIntr, vector, pThreadState) intrClearLeafVector(pGpu, pIntr, vector, pThreadState) +static inline void intrClearCpuLeafVector_b3696a(OBJGPU *pGpu, struct Intr *pIntr, NvU32 vector, struct THREAD_STATE_NODE *pThreadState) { + return; +} + +void intrClearCpuLeafVector_GH100(OBJGPU *pGpu, struct Intr *pIntr, NvU32 vector, struct THREAD_STATE_NODE *pThreadState); + + +#ifdef __nvoc_intr_h_disabled +static inline void intrClearCpuLeafVector(OBJGPU *pGpu, struct Intr *pIntr, NvU32 vector, struct THREAD_STATE_NODE *pThreadState) { + NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); +} +#else //__nvoc_intr_h_disabled +#define intrClearCpuLeafVector(pGpu, pIntr, vector, pThreadState) intrClearCpuLeafVector_b3696a(pGpu, pIntr, vector, pThreadState) +#endif //__nvoc_intr_h_disabled + +#define intrClearCpuLeafVector_HAL(pGpu, pIntr, vector, pThreadState) intrClearCpuLeafVector(pGpu, pIntr, vector, pThreadState) + +static inline void intrWriteCpuRegLeaf_b3696a(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2) { + return; +} + +void intrWriteCpuRegLeaf_GH100(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2); + + +#ifdef __nvoc_intr_h_disabled +static inline void intrWriteCpuRegLeaf(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2) { + NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); +} +#else //__nvoc_intr_h_disabled +#define intrWriteCpuRegLeaf(pGpu, pIntr, arg0, arg1, arg2) intrWriteCpuRegLeaf_b3696a(pGpu, pIntr, arg0, arg1, arg2) +#endif //__nvoc_intr_h_disabled + +#define intrWriteCpuRegLeaf_HAL(pGpu, pIntr, arg0, arg1, arg2) intrWriteCpuRegLeaf(pGpu, pIntr, arg0, arg1, arg2) + NvBool intrIsVectorPending_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 vector, struct THREAD_STATE_NODE *pThreadState); @@ -1696,6 +1798,17 @@ static inline NvU64 intrGetIntrTopCategoryMask(struct Intr *pIntr, NV2080_INTR_C #define intrGetIntrTopCategoryMask(pIntr, category) intrGetIntrTopCategoryMask_IMPL(pIntr, category) #endif //__nvoc_intr_h_disabled +NV_STATUS intrSetInterruptEntry_IMPL(struct Intr *pIntr, INTR_TREE tree, NvU32 vector, const InterruptEntry *pEntry); + +#ifdef __nvoc_intr_h_disabled +static inline NV_STATUS intrSetInterruptEntry(struct Intr *pIntr, INTR_TREE tree, NvU32 vector, const InterruptEntry *pEntry) { + NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_intr_h_disabled +#define intrSetInterruptEntry(pIntr, tree, vector, pEntry) intrSetInterruptEntry_IMPL(pIntr, tree, vector, pEntry) +#endif //__nvoc_intr_h_disabled + void intrServiceStallListAllGpusCond_IMPL(OBJGPU *pGpu, struct Intr *pIntr, union MC_ENGINE_BITVECTOR *arg0, NvBool arg1); #ifdef __nvoc_intr_h_disabled @@ -1926,4 +2039,5 @@ static inline void intrGetGmmuInterrupts(OBJGPU *pGpu, struct Intr *pIntr, union #ifdef __cplusplus } // extern "C" #endif + #endif // _G_INTR_NVOC_H_ diff --git a/src/nvidia/generated/g_intr_service_nvoc.h b/src/nvidia/generated/g_intr_service_nvoc.h index 1476bd2413..d2b7cbe785 100644 --- a/src/nvidia/generated/g_intr_service_nvoc.h +++ b/src/nvidia/generated/g_intr_service_nvoc.h @@ -122,9 +122,9 @@ NV_STATUS __nvoc_objCreate_IntrService(IntrService**, Dynamic*, NvU32); #define intrservClearInterrupt(pGpu, pIntrService, pParams) intrservClearInterrupt_DISPATCH(pGpu, pIntrService, pParams) #define intrservServiceInterrupt(pGpu, pIntrService, pParams) intrservServiceInterrupt_DISPATCH(pGpu, pIntrService, pParams) #define intrservServiceNotificationInterrupt(pGpu, pIntrService, pParams) intrservServiceNotificationInterrupt_DISPATCH(pGpu, pIntrService, pParams) -void intrservRegisterIntrService_IMPL(struct OBJGPU *pGpu, struct IntrService *pIntrService, IntrServiceRecord pRecords[167]); +void intrservRegisterIntrService_IMPL(struct OBJGPU *pGpu, struct IntrService *pIntrService, IntrServiceRecord pRecords[168]); -static inline void intrservRegisterIntrService_DISPATCH(struct OBJGPU *pGpu, struct IntrService *pIntrService, IntrServiceRecord pRecords[167]) { +static inline void intrservRegisterIntrService_DISPATCH(struct OBJGPU *pGpu, struct IntrService *pIntrService, IntrServiceRecord pRecords[168]) { pIntrService->__intrservRegisterIntrService__(pGpu, pIntrService, pRecords); } @@ -154,4 +154,5 @@ static inline NV_STATUS intrservServiceNotificationInterrupt_DISPATCH(struct OBJ #ifdef __cplusplus } // extern "C" #endif + #endif // _G_INTR_SERVICE_NVOC_H_ diff --git a/src/nvidia/generated/g_io_vaspace_nvoc.c b/src/nvidia/generated/g_io_vaspace_nvoc.c index 66009efdd9..e6fbc65856 100644 --- a/src/nvidia/generated/g_io_vaspace_nvoc.c +++ b/src/nvidia/generated/g_io_vaspace_nvoc.c @@ -106,10 +106,6 @@ static NvBool __nvoc_thunk_OBJVASPACE_iovaspaceIsExternallyOwned(struct OBJIOVAS return vaspaceIsExternallyOwned((struct OBJVASPACE *)(((unsigned char *)pVAS) + __nvoc_rtti_OBJIOVASPACE_OBJVASPACE.offset)); } -static NvBool __nvoc_thunk_OBJVASPACE_iovaspaceIsInternalVaRestricted(struct OBJIOVASPACE *pVAS) { - return vaspaceIsInternalVaRestricted((struct OBJVASPACE *)(((unsigned char *)pVAS) + __nvoc_rtti_OBJIOVASPACE_OBJVASPACE.offset)); -} - static NvU32 __nvoc_thunk_OBJVASPACE_iovaspaceGetFlags(struct OBJIOVASPACE *pVAS) { return vaspaceGetFlags((struct OBJVASPACE *)(((unsigned char *)pVAS) + __nvoc_rtti_OBJIOVASPACE_OBJVASPACE.offset)); } @@ -178,8 +174,8 @@ static NV_STATUS __nvoc_thunk_OBJVASPACE_iovaspaceGetPageTableInfo(struct OBJIOV return vaspaceGetPageTableInfo((struct OBJVASPACE *)(((unsigned char *)pVAS) + __nvoc_rtti_OBJIOVASPACE_OBJVASPACE.offset), pParams); } -static NV_STATUS __nvoc_thunk_OBJVASPACE_iovaspaceReserveMempool(struct OBJIOVASPACE *pVAS, struct OBJGPU *pGpu, NvHandle hClient, NvU64 size, NvU64 pageSizeLockMask, NvU32 flags) { - return vaspaceReserveMempool((struct OBJVASPACE *)(((unsigned char *)pVAS) + __nvoc_rtti_OBJIOVASPACE_OBJVASPACE.offset), pGpu, hClient, size, pageSizeLockMask, flags); +static NV_STATUS __nvoc_thunk_OBJVASPACE_iovaspaceReserveMempool(struct OBJIOVASPACE *pVAS, struct OBJGPU *pGpu, struct Device *pDevice, NvU64 size, NvU64 pageSizeLockMask, NvU32 flags) { + return vaspaceReserveMempool((struct OBJVASPACE *)(((unsigned char *)pVAS) + __nvoc_rtti_OBJIOVASPACE_OBJVASPACE.offset), pGpu, pDevice, size, pageSizeLockMask, flags); } static NV_STATUS __nvoc_thunk_OBJVASPACE_iovaspaceMap(struct OBJIOVASPACE *pVAS, struct OBJGPU *pGpu, const NvU64 vaLo, const NvU64 vaHi, const MMU_MAP_TARGET *pTarget, const VAS_MAP_FLAGS flags) { @@ -256,8 +252,6 @@ static void __nvoc_init_funcTable_OBJIOVASPACE_1(OBJIOVASPACE *pThis) { pThis->__iovaspaceIsExternallyOwned__ = &__nvoc_thunk_OBJVASPACE_iovaspaceIsExternallyOwned; - pThis->__iovaspaceIsInternalVaRestricted__ = &__nvoc_thunk_OBJVASPACE_iovaspaceIsInternalVaRestricted; - pThis->__iovaspaceGetFlags__ = &__nvoc_thunk_OBJVASPACE_iovaspaceGetFlags; pThis->__iovaspaceIsAtsEnabled__ = &__nvoc_thunk_OBJVASPACE_iovaspaceIsAtsEnabled; diff --git a/src/nvidia/generated/g_io_vaspace_nvoc.h b/src/nvidia/generated/g_io_vaspace_nvoc.h index 10376ebe28..0e1af752b6 100644 --- a/src/nvidia/generated/g_io_vaspace_nvoc.h +++ b/src/nvidia/generated/g_io_vaspace_nvoc.h @@ -156,7 +156,6 @@ struct OBJIOVASPACE { NV_STATUS (*__iovaspaceGetVasInfo__)(struct OBJIOVASPACE *, NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS *); NvBool (*__iovaspaceIsMirrored__)(struct OBJIOVASPACE *); NvBool (*__iovaspaceIsExternallyOwned__)(struct OBJIOVASPACE *); - NvBool (*__iovaspaceIsInternalVaRestricted__)(struct OBJIOVASPACE *); NvU32 (*__iovaspaceGetFlags__)(struct OBJIOVASPACE *); NvBool (*__iovaspaceIsAtsEnabled__)(struct OBJIOVASPACE *); NvU64 (*__iovaspaceGetBigPageSize__)(struct OBJIOVASPACE *); @@ -174,7 +173,7 @@ struct OBJIOVASPACE { NV_STATUS (*__iovaspaceFreeV2__)(struct OBJIOVASPACE *, NvU64, NvU64 *); NV_STATUS (*__iovaspaceGetPasid__)(struct OBJIOVASPACE *, NvU32 *); NV_STATUS (*__iovaspaceGetPageTableInfo__)(struct OBJIOVASPACE *, NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS *); - NV_STATUS (*__iovaspaceReserveMempool__)(struct OBJIOVASPACE *, struct OBJGPU *, NvHandle, NvU64, NvU64, NvU32); + NV_STATUS (*__iovaspaceReserveMempool__)(struct OBJIOVASPACE *, struct OBJGPU *, struct Device *, NvU64, NvU64, NvU32); NV_STATUS (*__iovaspaceMap__)(struct OBJIOVASPACE *, struct OBJGPU *, const NvU64, const NvU64, const MMU_MAP_TARGET *, const VAS_MAP_FLAGS); NvU64 mappingCount; }; @@ -217,7 +216,6 @@ NV_STATUS __nvoc_objCreate_OBJIOVASPACE(OBJIOVASPACE**, Dynamic*, NvU32); #define iovaspaceGetVasInfo(pVAS, pParams) iovaspaceGetVasInfo_DISPATCH(pVAS, pParams) #define iovaspaceIsMirrored(pVAS) iovaspaceIsMirrored_DISPATCH(pVAS) #define iovaspaceIsExternallyOwned(pVAS) iovaspaceIsExternallyOwned_DISPATCH(pVAS) -#define iovaspaceIsInternalVaRestricted(pVAS) iovaspaceIsInternalVaRestricted_DISPATCH(pVAS) #define iovaspaceGetFlags(pVAS) iovaspaceGetFlags_DISPATCH(pVAS) #define iovaspaceIsAtsEnabled(pVAS) iovaspaceIsAtsEnabled_DISPATCH(pVAS) #define iovaspaceGetBigPageSize(pVAS) iovaspaceGetBigPageSize_DISPATCH(pVAS) @@ -235,7 +233,7 @@ NV_STATUS __nvoc_objCreate_OBJIOVASPACE(OBJIOVASPACE**, Dynamic*, NvU32); #define iovaspaceFreeV2(pVAS, vAddr, pSize) iovaspaceFreeV2_DISPATCH(pVAS, vAddr, pSize) #define iovaspaceGetPasid(pVAS, pPasid) iovaspaceGetPasid_DISPATCH(pVAS, pPasid) #define iovaspaceGetPageTableInfo(pVAS, pParams) iovaspaceGetPageTableInfo_DISPATCH(pVAS, pParams) -#define iovaspaceReserveMempool(pVAS, pGpu, hClient, size, pageSizeLockMask, flags) iovaspaceReserveMempool_DISPATCH(pVAS, pGpu, hClient, size, pageSizeLockMask, flags) +#define iovaspaceReserveMempool(pVAS, pGpu, pDevice, size, pageSizeLockMask, flags) iovaspaceReserveMempool_DISPATCH(pVAS, pGpu, pDevice, size, pageSizeLockMask, flags) #define iovaspaceMap(pVAS, pGpu, vaLo, vaHi, pTarget, flags) iovaspaceMap_DISPATCH(pVAS, pGpu, vaLo, vaHi, pTarget, flags) NV_STATUS iovaspaceConstruct__IMPL(struct OBJIOVASPACE *pVAS, NvU32 classId, NvU32 vaspaceId, NvU64 vaStart, NvU64 vaLimit, NvU64 vaStartInternal, NvU64 vaLimitInternal, NvU32 flags); @@ -293,10 +291,6 @@ static inline NvBool iovaspaceIsExternallyOwned_DISPATCH(struct OBJIOVASPACE *pV return pVAS->__iovaspaceIsExternallyOwned__(pVAS); } -static inline NvBool iovaspaceIsInternalVaRestricted_DISPATCH(struct OBJIOVASPACE *pVAS) { - return pVAS->__iovaspaceIsInternalVaRestricted__(pVAS); -} - static inline NvU32 iovaspaceGetFlags_DISPATCH(struct OBJIOVASPACE *pVAS) { return pVAS->__iovaspaceGetFlags__(pVAS); } @@ -365,8 +359,8 @@ static inline NV_STATUS iovaspaceGetPageTableInfo_DISPATCH(struct OBJIOVASPACE * return pVAS->__iovaspaceGetPageTableInfo__(pVAS, pParams); } -static inline NV_STATUS iovaspaceReserveMempool_DISPATCH(struct OBJIOVASPACE *pVAS, struct OBJGPU *pGpu, NvHandle hClient, NvU64 size, NvU64 pageSizeLockMask, NvU32 flags) { - return pVAS->__iovaspaceReserveMempool__(pVAS, pGpu, hClient, size, pageSizeLockMask, flags); +static inline NV_STATUS iovaspaceReserveMempool_DISPATCH(struct OBJIOVASPACE *pVAS, struct OBJGPU *pGpu, struct Device *pDevice, NvU64 size, NvU64 pageSizeLockMask, NvU32 flags) { + return pVAS->__iovaspaceReserveMempool__(pVAS, pGpu, pDevice, size, pageSizeLockMask, flags); } static inline NV_STATUS iovaspaceMap_DISPATCH(struct OBJIOVASPACE *pVAS, struct OBJGPU *pGpu, const NvU64 vaLo, const NvU64 vaHi, const MMU_MAP_TARGET *pTarget, const VAS_MAP_FLAGS flags) { @@ -424,4 +418,5 @@ void iovaMappingDestroy(PIOVAMAPPING pIovaMapping); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_IO_VASPACE_NVOC_H_ diff --git a/src/nvidia/generated/g_ioaccess_nvoc.h b/src/nvidia/generated/g_ioaccess_nvoc.h index 348a9a6fa2..ed83014794 100644 --- a/src/nvidia/generated/g_ioaccess_nvoc.h +++ b/src/nvidia/generated/g_ioaccess_nvoc.h @@ -233,4 +233,5 @@ NV_STATUS ioaccessInitIOAperture #ifdef __cplusplus } // extern "C" #endif + #endif // _G_IOACCESS_NVOC_H_ diff --git a/src/nvidia/generated/g_journal_nvoc.h b/src/nvidia/generated/g_journal_nvoc.h index 4968511d59..ec95e134ae 100644 --- a/src/nvidia/generated/g_journal_nvoc.h +++ b/src/nvidia/generated/g_journal_nvoc.h @@ -539,4 +539,5 @@ NV_STATUS rcdbNocatJournalReportTestFill(void); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_JOURNAL_NVOC_H_ diff --git a/src/nvidia/generated/g_kern_bus_nvoc.c b/src/nvidia/generated/g_kern_bus_nvoc.c index c2927afc75..bea3643f30 100644 --- a/src/nvidia/generated/g_kern_bus_nvoc.c +++ b/src/nvidia/generated/g_kern_bus_nvoc.c @@ -66,44 +66,44 @@ const struct NVOC_CLASS_DEF __nvoc_class_def_KernelBus = /*pExportInfo=*/ &__nvoc_export_info_KernelBus }; -static NV_STATUS __nvoc_thunk_KernelBus_engstateConstructEngine(OBJGPU *pGpu, struct OBJENGSTATE *pKernelBus, ENGDESCRIPTOR arg0) { +static NV_STATUS __nvoc_thunk_KernelBus_engstateConstructEngine(struct OBJGPU *pGpu, struct OBJENGSTATE *pKernelBus, ENGDESCRIPTOR arg0) { return kbusConstructEngine(pGpu, (struct KernelBus *)(((unsigned char *)pKernelBus) - __nvoc_rtti_KernelBus_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_KernelBus_engstateStatePreInitLocked(OBJGPU *pGpu, struct OBJENGSTATE *pKernelBus) { +static NV_STATUS __nvoc_thunk_KernelBus_engstateStatePreInitLocked(struct OBJGPU *pGpu, struct OBJENGSTATE *pKernelBus) { return kbusStatePreInitLocked(pGpu, (struct KernelBus *)(((unsigned char *)pKernelBus) - __nvoc_rtti_KernelBus_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_KernelBus_engstateStateInitLocked(OBJGPU *pGpu, struct OBJENGSTATE *pKernelBus) { +static NV_STATUS __nvoc_thunk_KernelBus_engstateStateInitLocked(struct OBJGPU *pGpu, struct OBJENGSTATE *pKernelBus) { return kbusStateInitLocked(pGpu, (struct KernelBus *)(((unsigned char *)pKernelBus) - __nvoc_rtti_KernelBus_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_KernelBus_engstateStatePreLoad(OBJGPU *pGpu, struct OBJENGSTATE *pKernelBus, NvU32 arg0) { +static NV_STATUS __nvoc_thunk_KernelBus_engstateStatePreLoad(struct OBJGPU *pGpu, struct OBJENGSTATE *pKernelBus, NvU32 arg0) { return kbusStatePreLoad(pGpu, (struct KernelBus *)(((unsigned char *)pKernelBus) - __nvoc_rtti_KernelBus_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_KernelBus_engstateStateLoad(OBJGPU *pGpu, struct OBJENGSTATE *pKernelBus, NvU32 arg0) { +static NV_STATUS __nvoc_thunk_KernelBus_engstateStateLoad(struct OBJGPU *pGpu, struct OBJENGSTATE *pKernelBus, NvU32 arg0) { return kbusStateLoad(pGpu, (struct KernelBus *)(((unsigned char *)pKernelBus) - __nvoc_rtti_KernelBus_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_KernelBus_engstateStatePostLoad(OBJGPU *pGpu, struct OBJENGSTATE *pKernelBus, NvU32 arg0) { +static NV_STATUS __nvoc_thunk_KernelBus_engstateStatePostLoad(struct OBJGPU *pGpu, struct OBJENGSTATE *pKernelBus, NvU32 arg0) { return kbusStatePostLoad(pGpu, (struct KernelBus *)(((unsigned char *)pKernelBus) - __nvoc_rtti_KernelBus_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_KernelBus_engstateStatePreUnload(OBJGPU *pGpu, struct OBJENGSTATE *pKernelBus, NvU32 arg0) { +static NV_STATUS __nvoc_thunk_KernelBus_engstateStatePreUnload(struct OBJGPU *pGpu, struct OBJENGSTATE *pKernelBus, NvU32 arg0) { return kbusStatePreUnload(pGpu, (struct KernelBus *)(((unsigned char *)pKernelBus) - __nvoc_rtti_KernelBus_OBJENGSTATE.offset), arg0); } -static NV_STATUS __nvoc_thunk_KernelBus_engstateStateUnload(OBJGPU *pGpu, struct OBJENGSTATE *pKernelBus, NvU32 flags) { +static NV_STATUS __nvoc_thunk_KernelBus_engstateStateUnload(struct OBJGPU *pGpu, struct OBJENGSTATE *pKernelBus, NvU32 flags) { return kbusStateUnload(pGpu, (struct KernelBus *)(((unsigned char *)pKernelBus) - __nvoc_rtti_KernelBus_OBJENGSTATE.offset), flags); } -static void __nvoc_thunk_KernelBus_engstateStateDestroy(OBJGPU *pGpu, struct OBJENGSTATE *pKernelBus) { - kbusStateDestroy(pGpu, (struct KernelBus *)(((unsigned char *)pKernelBus) - __nvoc_rtti_KernelBus_OBJENGSTATE.offset)); +static NV_STATUS __nvoc_thunk_KernelBus_engstateStatePostUnload(struct OBJGPU *pGpu, struct OBJENGSTATE *pKernelBus, NvU32 flags) { + return kbusStatePostUnload(pGpu, (struct KernelBus *)(((unsigned char *)pKernelBus) - __nvoc_rtti_KernelBus_OBJENGSTATE.offset), flags); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kbusStatePostUnload(POBJGPU pGpu, struct KernelBus *pEngstate, NvU32 arg0) { - return engstateStatePostUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBus_OBJENGSTATE.offset), arg0); +static void __nvoc_thunk_KernelBus_engstateStateDestroy(struct OBJGPU *pGpu, struct OBJENGSTATE *pKernelBus) { + kbusStateDestroy(pGpu, (struct KernelBus *)(((unsigned char *)pKernelBus) - __nvoc_rtti_KernelBus_OBJENGSTATE.offset)); } static NV_STATUS __nvoc_thunk_OBJENGSTATE_kbusStateInitUnlocked(POBJGPU pGpu, struct KernelBus *pEngstate) { @@ -176,18 +176,6 @@ void __nvoc_init_dataField_KernelBus(KernelBus *pThis, RmHalspecOwner *pRmhalspe pThis->bAllowReflectedMappingAccess = ((NvBool)(0 != 0)); } - // Hal field -- bBar2Tunnelled - // default - { - pThis->bBar2Tunnelled = ((NvBool)(0 != 0)); - } - - // Hal field -- bBar2InternalOnly - // default - { - pThis->bBar2InternalOnly = ((NvBool)(0 != 0)); - } - // Hal field -- bIsEntireBar2RegionVirtuallyAddressible if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { @@ -227,6 +215,17 @@ void __nvoc_init_dataField_KernelBus(KernelBus *pThis, RmHalspecOwner *pRmhalspe { pThis->setProperty(pThis, PDB_PROP_KBUS_IS_MISSING, ((NvBool)(0 != 0))); } + + // NVOC Property Hal field -- PDB_PROP_KBUS_RESTORE_BAR1_SIZE_BUG_3249028_WAR + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + { + pThis->setProperty(pThis, PDB_PROP_KBUS_RESTORE_BAR1_SIZE_BUG_3249028_WAR, ((NvBool)(0 == 0))); + } + // default + else + { + pThis->setProperty(pThis, PDB_PROP_KBUS_RESTORE_BAR1_SIZE_BUG_3249028_WAR, ((NvBool)(0 != 0))); + } } NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* ); @@ -263,7 +262,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * pThis->__kbusStateInitLocked__ = &kbusStateInitLocked_IMPL; // Hal function -- kbusStatePreLoad - pThis->__kbusStatePreLoad__ = &kbusStatePreLoad_56cd7a; + pThis->__kbusStatePreLoad__ = &kbusStatePreLoad_GM107; // Hal function -- kbusStateLoad pThis->__kbusStateLoad__ = &kbusStateLoad_GM107; @@ -277,6 +276,9 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * // Hal function -- kbusStateUnload pThis->__kbusStateUnload__ = &kbusStateUnload_GM107; + // Hal function -- kbusStatePostUnload + pThis->__kbusStatePostUnload__ = &kbusStatePostUnload_GM107; + // Hal function -- kbusStateDestroy pThis->__kbusStateDestroy__ = &kbusStateDestroy_GM107; @@ -448,15 +450,15 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * pThis->__kbusUnreserveP2PPeerIds__ = &kbusUnreserveP2PPeerIds_GP100; } - // Hal function -- kbusNeedStaticBar1Mapping + // Hal function -- kbusIsBar1P2PCapable if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbusNeedStaticBar1Mapping__ = &kbusNeedStaticBar1Mapping_GH100; + pThis->__kbusIsBar1P2PCapable__ = &kbusIsBar1P2PCapable_GH100; } // default else { - pThis->__kbusNeedStaticBar1Mapping__ = &kbusNeedStaticBar1Mapping_bf6dfa; + pThis->__kbusIsBar1P2PCapable__ = &kbusIsBar1P2PCapable_bf6dfa; } // Hal function -- kbusEnableStaticBar1Mapping @@ -467,7 +469,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * // default else { - pThis->__kbusEnableStaticBar1Mapping__ = &kbusEnableStaticBar1Mapping_46f6a7; + pThis->__kbusEnableStaticBar1Mapping__ = &kbusEnableStaticBar1Mapping_395e98; } // Hal function -- kbusDisableStaticBar1Mapping @@ -478,7 +480,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * // default else { - pThis->__kbusDisableStaticBar1Mapping__ = &kbusDisableStaticBar1Mapping_56cd7a; + pThis->__kbusDisableStaticBar1Mapping__ = &kbusDisableStaticBar1Mapping_d44104; } // Hal function -- kbusGetBar1P2PDmaInfo @@ -492,26 +494,26 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * pThis->__kbusGetBar1P2PDmaInfo__ = &kbusGetBar1P2PDmaInfo_395e98; } - // Hal function -- kbusStaticMapFbAperture + // Hal function -- kbusUpdateStaticBar1VAMapping if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbusStaticMapFbAperture__ = &kbusStaticMapFbAperture_GH100; + pThis->__kbusUpdateStaticBar1VAMapping__ = &kbusUpdateStaticBar1VAMapping_GH100; } // default else { - pThis->__kbusStaticMapFbAperture__ = &kbusStaticMapFbAperture_395e98; + pThis->__kbusUpdateStaticBar1VAMapping__ = &kbusUpdateStaticBar1VAMapping_395e98; } - // Hal function -- kbusStaticUnmapFbAperture + // Hal function -- kbusGetStaticFbAperture if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kbusStaticUnmapFbAperture__ = &kbusStaticUnmapFbAperture_GH100; + pThis->__kbusGetStaticFbAperture__ = &kbusGetStaticFbAperture_GH100; } // default else { - pThis->__kbusStaticUnmapFbAperture__ = &kbusStaticUnmapFbAperture_395e98; + pThis->__kbusGetStaticFbAperture__ = &kbusGetStaticFbAperture_395e98; } // Hal function -- kbusCreateP2PMappingForBar1P2P @@ -522,7 +524,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * // default else { - pThis->__kbusCreateP2PMappingForBar1P2P__ = &kbusCreateP2PMappingForBar1P2P_46f6a7; + pThis->__kbusCreateP2PMappingForBar1P2P__ = &kbusCreateP2PMappingForBar1P2P_395e98; } // Hal function -- kbusRemoveP2PMappingForBar1P2P @@ -533,7 +535,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * // default else { - pThis->__kbusRemoveP2PMappingForBar1P2P__ = &kbusRemoveP2PMappingForBar1P2P_46f6a7; + pThis->__kbusRemoveP2PMappingForBar1P2P__ = &kbusRemoveP2PMappingForBar1P2P_395e98; } // Hal function -- kbusHasPcieBar1P2PMapping @@ -544,7 +546,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * // default else { - pThis->__kbusHasPcieBar1P2PMapping__ = &kbusHasPcieBar1P2PMapping_491d52; + pThis->__kbusHasPcieBar1P2PMapping__ = &kbusHasPcieBar1P2PMapping_bf6dfa; } // Hal function -- kbusIsPcieBar1P2PMappingSupported @@ -555,18 +557,7 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * // default else { - pThis->__kbusIsPcieBar1P2PMappingSupported__ = &kbusIsPcieBar1P2PMappingSupported_491d52; - } - - // Hal function -- kbusSetupBar1P2PCapability - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kbusSetupBar1P2PCapability__ = &kbusSetupBar1P2PCapability_GH100; - } - // default - else - { - pThis->__kbusSetupBar1P2PCapability__ = &kbusSetupBar1P2PCapability_b3696a; + pThis->__kbusIsPcieBar1P2PMappingSupported__ = &kbusIsPcieBar1P2PMappingSupported_bf6dfa; } // Hal function -- kbusCheckFlaSupportedAndInit @@ -747,6 +738,34 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * pThis->__kbusSetupBindFla__ = &kbusSetupBindFla_46f6a7; } + // Hal function -- kbusCacheBAR1ResizeSize_WAR_BUG_3249028 + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusCacheBAR1ResizeSize_WAR_BUG_3249028__ = &kbusCacheBAR1ResizeSize_WAR_BUG_3249028_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__kbusCacheBAR1ResizeSize_WAR_BUG_3249028__ = &kbusCacheBAR1ResizeSize_WAR_BUG_3249028_d44104; + } + else + { + pThis->__kbusCacheBAR1ResizeSize_WAR_BUG_3249028__ = &kbusCacheBAR1ResizeSize_WAR_BUG_3249028_GA100; + } + + // Hal function -- kbusRestoreBAR1ResizeSize_WAR_BUG_3249028 + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusRestoreBAR1ResizeSize_WAR_BUG_3249028__ = &kbusRestoreBAR1ResizeSize_WAR_BUG_3249028_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__kbusRestoreBAR1ResizeSize_WAR_BUG_3249028__ = &kbusRestoreBAR1ResizeSize_WAR_BUG_3249028_ac1694; + } + else + { + pThis->__kbusRestoreBAR1ResizeSize_WAR_BUG_3249028__ = &kbusRestoreBAR1ResizeSize_WAR_BUG_3249028_GA100; + } + // Hal function -- kbusIsDirectMappingAllowed if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { @@ -908,9 +927,9 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * pThis->__nvoc_base_OBJENGSTATE.__engstateStateUnload__ = &__nvoc_thunk_KernelBus_engstateStateUnload; - pThis->__nvoc_base_OBJENGSTATE.__engstateStateDestroy__ = &__nvoc_thunk_KernelBus_engstateStateDestroy; + pThis->__nvoc_base_OBJENGSTATE.__engstateStatePostUnload__ = &__nvoc_thunk_KernelBus_engstateStatePostUnload; - pThis->__kbusStatePostUnload__ = &__nvoc_thunk_OBJENGSTATE_kbusStatePostUnload; + pThis->__nvoc_base_OBJENGSTATE.__engstateStateDestroy__ = &__nvoc_thunk_KernelBus_engstateStateDestroy; pThis->__kbusStateInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kbusStateInitUnlocked; @@ -925,7 +944,7 @@ void __nvoc_init_funcTable_KernelBus(KernelBus *pThis, RmHalspecOwner *pRmhalspe __nvoc_init_funcTable_KernelBus_1(pThis, pRmhalspecowner); } -NvU32 kbusGetP2PWriteMailboxAddressSize_STATIC_DISPATCH(OBJGPU *pGpu) { +NvU32 kbusGetP2PWriteMailboxAddressSize_STATIC_DISPATCH(struct OBJGPU *pGpu) { ChipHal *chipHal = &staticCast(pGpu, RmHalspecOwner)->chipHal; const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; diff --git a/src/nvidia/generated/g_kern_bus_nvoc.h b/src/nvidia/generated/g_kern_bus_nvoc.h index 13981ff486..230a870606 100644 --- a/src/nvidia/generated/g_kern_bus_nvoc.h +++ b/src/nvidia/generated/g_kern_bus_nvoc.h @@ -44,6 +44,7 @@ extern "C" { #include "mmu/mmu_walk.h" // MMU_WALK #include "mmu/gmmu_fmt.h" // GMMU_FMT #include "mem_mgr/vaspace.h" +#include "kernel/gpu/mem_mgr/mem_mgr.h" // TRANSFER_FLAGS_* #include "ctrl/ctrl0000/ctrl0000system.h" // NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS #include "ctrl/ctrl2080/ctrl2080bus.h" @@ -120,7 +121,6 @@ typedef enum // #define BUS_FLUSH_VIDEO_MEMORY NVBIT(0) #define BUS_FLUSH_SYSTEM_MEMORY NVBIT(1) -#define BUS_FLUSH_USE_PCIE_READ NVBIT(2) // // Peer to peer (P2P) defines @@ -202,7 +202,6 @@ struct __nvoc_inner_struc_KernelBus_1__ { struct { MEMORY_DESCRIPTOR *pVidMemDesc; MEMORY_DESCRIPTOR *pDmaMemDesc; - NvU64 base; NvU64 size; } staticBar1; }; @@ -237,6 +236,7 @@ struct __nvoc_inner_struc_KernelBus_2__ { NvBool bIsBar2SizeReduced; NvU32 pageDirInit; NvU32 pageTblInit; + NvU32 cpuVisiblePgTblSize; }; struct __nvoc_inner_struc_KernelBus_3__ { @@ -316,72 +316,73 @@ struct KernelBus { struct Object *__nvoc_pbase_Object; struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; struct KernelBus *__nvoc_pbase_KernelBus; - NV_STATUS (*__kbusConstructEngine__)(OBJGPU *, struct KernelBus *, ENGDESCRIPTOR); - NV_STATUS (*__kbusStatePreInitLocked__)(OBJGPU *, struct KernelBus *); - NV_STATUS (*__kbusStateInitLocked__)(OBJGPU *, struct KernelBus *); - NV_STATUS (*__kbusStatePreLoad__)(OBJGPU *, struct KernelBus *, NvU32); - NV_STATUS (*__kbusStateLoad__)(OBJGPU *, struct KernelBus *, NvU32); - NV_STATUS (*__kbusStatePostLoad__)(OBJGPU *, struct KernelBus *, NvU32); - NV_STATUS (*__kbusStatePreUnload__)(OBJGPU *, struct KernelBus *, NvU32); - NV_STATUS (*__kbusStateUnload__)(OBJGPU *, struct KernelBus *, NvU32); - void (*__kbusStateDestroy__)(OBJGPU *, struct KernelBus *); - NV_STATUS (*__kbusTeardownBar2CpuAperture__)(OBJGPU *, struct KernelBus *, NvU32); - void (*__kbusGetP2PMailboxAttributes__)(OBJGPU *, struct KernelBus *, NvU32 *, NvU32 *, NvU32 *); - NV_STATUS (*__kbusCreateP2PMapping__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *, NvU32 *, NvU32 *, NvU32); - NV_STATUS (*__kbusRemoveP2PMapping__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *, NvU32, NvU32, NvU32); - NvU32 (*__kbusGetEgmPeerId__)(OBJGPU *, struct KernelBus *, OBJGPU *); - NvU32 (*__kbusGetPeerId__)(OBJGPU *, struct KernelBus *, OBJGPU *); - NvU32 (*__kbusGetNvSwitchPeerId__)(OBJGPU *, struct KernelBus *); - NvU32 (*__kbusGetUnusedPciePeerId__)(OBJGPU *, struct KernelBus *); - NV_STATUS (*__kbusIsPeerIdValid__)(OBJGPU *, struct KernelBus *, NvU32); - NV_STATUS (*__kbusGetNvlinkP2PPeerId__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *, NvU32 *, NvU32); - void (*__kbusWriteP2PWmbTag__)(OBJGPU *, struct KernelBus *, NvU32, NvU64); - RmPhysAddr (*__kbusSetupP2PDomainAccess__)(OBJGPU *, struct KernelBus *, OBJGPU *, PMEMORY_DESCRIPTOR *); - NvBool (*__kbusNeedWarForBug999673__)(OBJGPU *, struct KernelBus *, OBJGPU *); - NV_STATUS (*__kbusCreateP2PMappingForC2C__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *, NvU32 *, NvU32 *, NvU32); - NV_STATUS (*__kbusRemoveP2PMappingForC2C__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *, NvU32, NvU32, NvU32); - NV_STATUS (*__kbusUnreserveP2PPeerIds__)(OBJGPU *, struct KernelBus *, NvU32); - NvBool (*__kbusNeedStaticBar1Mapping__)(OBJGPU *, struct KernelBus *); - NV_STATUS (*__kbusEnableStaticBar1Mapping__)(OBJGPU *, struct KernelBus *, NvU64, NvU32); - NV_STATUS (*__kbusDisableStaticBar1Mapping__)(OBJGPU *, struct KernelBus *, NvU32); - NV_STATUS (*__kbusGetBar1P2PDmaInfo__)(OBJGPU *, OBJGPU *, struct KernelBus *, NvU64 *, NvU64 *); - NV_STATUS (*__kbusStaticMapFbAperture__)(OBJGPU *, struct KernelBus *, MEMORY_DESCRIPTOR *, NvU64, NvU64 *, NvU64 *, NvU32); - NV_STATUS (*__kbusStaticUnmapFbAperture__)(OBJGPU *, struct KernelBus *, MEMORY_DESCRIPTOR *, NvU32); - NV_STATUS (*__kbusCreateP2PMappingForBar1P2P__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *, NvU32); - NV_STATUS (*__kbusRemoveP2PMappingForBar1P2P__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *, NvU32); - NvBool (*__kbusHasPcieBar1P2PMapping__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *); - NvBool (*__kbusIsPcieBar1P2PMappingSupported__)(OBJGPU *, struct KernelBus *, OBJGPU *, struct KernelBus *); - void (*__kbusSetupBar1P2PCapability__)(OBJGPU *, struct KernelBus *); - NV_STATUS (*__kbusCheckFlaSupportedAndInit__)(OBJGPU *, struct KernelBus *, NvU64, NvU64); - NV_STATUS (*__kbusDetermineFlaRangeAndAllocate__)(OBJGPU *, struct KernelBus *, NvU64, NvU64); - NV_STATUS (*__kbusAllocateFlaVaspace__)(OBJGPU *, struct KernelBus *, NvU64, NvU64); - NV_STATUS (*__kbusGetFlaRange__)(OBJGPU *, struct KernelBus *, NvU64 *, NvU64 *, NvBool); - NV_STATUS (*__kbusAllocateLegacyFlaVaspace__)(OBJGPU *, struct KernelBus *, NvU64, NvU64); - NV_STATUS (*__kbusAllocateHostManagedFlaVaspace__)(OBJGPU *, struct KernelBus *, NvHandle, NvHandle, NvHandle, NvHandle, NvU64, NvU64, NvU32); - void (*__kbusDestroyFla__)(OBJGPU *, struct KernelBus *); - NV_STATUS (*__kbusGetFlaVaspace__)(OBJGPU *, struct KernelBus *, struct OBJVASPACE **); - void (*__kbusDestroyHostManagedFlaVaspace__)(OBJGPU *, struct KernelBus *, NvU32); - NvBool (*__kbusVerifyFlaRange__)(OBJGPU *, struct KernelBus *, NvU64, NvU64); - NV_STATUS (*__kbusConstructFlaInstBlk__)(OBJGPU *, struct KernelBus *, NvU32); - void (*__kbusDestructFlaInstBlk__)(OBJGPU *, struct KernelBus *); - NV_STATUS (*__kbusValidateFlaBaseAddress__)(OBJGPU *, struct KernelBus *, NvU64); - NV_STATUS (*__kbusSetupUnbindFla__)(OBJGPU *, struct KernelBus *); - NV_STATUS (*__kbusSetupBindFla__)(OBJGPU *, struct KernelBus *, NvU32); - NV_STATUS (*__kbusIsDirectMappingAllowed__)(OBJGPU *, struct KernelBus *, PMEMORY_DESCRIPTOR, NvU32, NvBool *); - NV_STATUS (*__kbusUseDirectSysmemMap__)(OBJGPU *, struct KernelBus *, MEMORY_DESCRIPTOR *, NvBool *); - NV_STATUS (*__kbusWriteBAR0WindowBase__)(OBJGPU *, struct KernelBus *, NvU32); - NvU32 (*__kbusReadBAR0WindowBase__)(OBJGPU *, struct KernelBus *); - NvBool (*__kbusValidateBAR0WindowBase__)(OBJGPU *, struct KernelBus *, NvU32); - NV_STATUS (*__kbusSetBAR0WindowVidOffset__)(OBJGPU *, struct KernelBus *, NvU64); - NvU64 (*__kbusGetBAR0WindowVidOffset__)(OBJGPU *, struct KernelBus *); - NV_STATUS (*__kbusVerifyBar2__)(OBJGPU *, struct KernelBus *, PMEMORY_DESCRIPTOR, NvU8 *, NvU64, NvU64); - NV_STATUS (*__kbusVerifyCoherentLink__)(OBJGPU *, struct KernelBus *); - NV_STATUS (*__kbusFlushPcieForBar0Doorbell__)(OBJGPU *, struct KernelBus *); - NV_STATUS (*__kbusCreateCoherentCpuMapping__)(OBJGPU *, struct KernelBus *, NvU64, NvBool); - NvU8 *(*__kbusMapCoherentCpuMapping__)(OBJGPU *, struct KernelBus *, PMEMORY_DESCRIPTOR); - void (*__kbusUnmapCoherentCpuMapping__)(OBJGPU *, struct KernelBus *, PMEMORY_DESCRIPTOR); - void (*__kbusTeardownCoherentCpuMapping__)(OBJGPU *, struct KernelBus *, NvBool); - NV_STATUS (*__kbusStatePostUnload__)(POBJGPU, struct KernelBus *, NvU32); + NV_STATUS (*__kbusConstructEngine__)(struct OBJGPU *, struct KernelBus *, ENGDESCRIPTOR); + NV_STATUS (*__kbusStatePreInitLocked__)(struct OBJGPU *, struct KernelBus *); + NV_STATUS (*__kbusStateInitLocked__)(struct OBJGPU *, struct KernelBus *); + NV_STATUS (*__kbusStatePreLoad__)(struct OBJGPU *, struct KernelBus *, NvU32); + NV_STATUS (*__kbusStateLoad__)(struct OBJGPU *, struct KernelBus *, NvU32); + NV_STATUS (*__kbusStatePostLoad__)(struct OBJGPU *, struct KernelBus *, NvU32); + NV_STATUS (*__kbusStatePreUnload__)(struct OBJGPU *, struct KernelBus *, NvU32); + NV_STATUS (*__kbusStateUnload__)(struct OBJGPU *, struct KernelBus *, NvU32); + NV_STATUS (*__kbusStatePostUnload__)(struct OBJGPU *, struct KernelBus *, NvU32); + void (*__kbusStateDestroy__)(struct OBJGPU *, struct KernelBus *); + NV_STATUS (*__kbusTeardownBar2CpuAperture__)(struct OBJGPU *, struct KernelBus *, NvU32); + void (*__kbusGetP2PMailboxAttributes__)(struct OBJGPU *, struct KernelBus *, NvU32 *, NvU32 *, NvU32 *); + NV_STATUS (*__kbusCreateP2PMapping__)(struct OBJGPU *, struct KernelBus *, struct OBJGPU *, struct KernelBus *, NvU32 *, NvU32 *, NvU32); + NV_STATUS (*__kbusRemoveP2PMapping__)(struct OBJGPU *, struct KernelBus *, struct OBJGPU *, struct KernelBus *, NvU32, NvU32, NvU32); + NvU32 (*__kbusGetEgmPeerId__)(struct OBJGPU *, struct KernelBus *, struct OBJGPU *); + NvU32 (*__kbusGetPeerId__)(struct OBJGPU *, struct KernelBus *, struct OBJGPU *); + NvU32 (*__kbusGetNvSwitchPeerId__)(struct OBJGPU *, struct KernelBus *); + NvU32 (*__kbusGetUnusedPciePeerId__)(struct OBJGPU *, struct KernelBus *); + NV_STATUS (*__kbusIsPeerIdValid__)(struct OBJGPU *, struct KernelBus *, NvU32); + NV_STATUS (*__kbusGetNvlinkP2PPeerId__)(struct OBJGPU *, struct KernelBus *, struct OBJGPU *, struct KernelBus *, NvU32 *, NvU32); + void (*__kbusWriteP2PWmbTag__)(struct OBJGPU *, struct KernelBus *, NvU32, NvU64); + RmPhysAddr (*__kbusSetupP2PDomainAccess__)(struct OBJGPU *, struct KernelBus *, struct OBJGPU *, PMEMORY_DESCRIPTOR *); + NvBool (*__kbusNeedWarForBug999673__)(struct OBJGPU *, struct KernelBus *, struct OBJGPU *); + NV_STATUS (*__kbusCreateP2PMappingForC2C__)(struct OBJGPU *, struct KernelBus *, struct OBJGPU *, struct KernelBus *, NvU32 *, NvU32 *, NvU32); + NV_STATUS (*__kbusRemoveP2PMappingForC2C__)(struct OBJGPU *, struct KernelBus *, struct OBJGPU *, struct KernelBus *, NvU32, NvU32, NvU32); + NV_STATUS (*__kbusUnreserveP2PPeerIds__)(struct OBJGPU *, struct KernelBus *, NvU32); + NvBool (*__kbusIsBar1P2PCapable__)(struct OBJGPU *, struct KernelBus *, NvU32); + NV_STATUS (*__kbusEnableStaticBar1Mapping__)(struct OBJGPU *, struct KernelBus *, NvU32); + void (*__kbusDisableStaticBar1Mapping__)(struct OBJGPU *, struct KernelBus *, NvU32); + NV_STATUS (*__kbusGetBar1P2PDmaInfo__)(struct OBJGPU *, struct OBJGPU *, struct KernelBus *, NvU64 *, NvU64 *); + NV_STATUS (*__kbusUpdateStaticBar1VAMapping__)(struct OBJGPU *, struct KernelBus *, MEMORY_DESCRIPTOR *, NvU64, NvU64, NvBool); + NV_STATUS (*__kbusGetStaticFbAperture__)(struct OBJGPU *, struct KernelBus *, MEMORY_DESCRIPTOR *, NvU64, NvU64 *, NvU64 *, NvU32); + NV_STATUS (*__kbusCreateP2PMappingForBar1P2P__)(struct OBJGPU *, struct KernelBus *, struct OBJGPU *, struct KernelBus *, NvU32); + NV_STATUS (*__kbusRemoveP2PMappingForBar1P2P__)(struct OBJGPU *, struct KernelBus *, struct OBJGPU *, struct KernelBus *, NvU32); + NvBool (*__kbusHasPcieBar1P2PMapping__)(struct OBJGPU *, struct KernelBus *, struct OBJGPU *, struct KernelBus *); + NvBool (*__kbusIsPcieBar1P2PMappingSupported__)(struct OBJGPU *, struct KernelBus *, struct OBJGPU *, struct KernelBus *); + NV_STATUS (*__kbusCheckFlaSupportedAndInit__)(struct OBJGPU *, struct KernelBus *, NvU64, NvU64); + NV_STATUS (*__kbusDetermineFlaRangeAndAllocate__)(struct OBJGPU *, struct KernelBus *, NvU64, NvU64); + NV_STATUS (*__kbusAllocateFlaVaspace__)(struct OBJGPU *, struct KernelBus *, NvU64, NvU64); + NV_STATUS (*__kbusGetFlaRange__)(struct OBJGPU *, struct KernelBus *, NvU64 *, NvU64 *, NvBool); + NV_STATUS (*__kbusAllocateLegacyFlaVaspace__)(struct OBJGPU *, struct KernelBus *, NvU64, NvU64); + NV_STATUS (*__kbusAllocateHostManagedFlaVaspace__)(struct OBJGPU *, struct KernelBus *, NvHandle, NvHandle, NvHandle, NvHandle, NvU64, NvU64, NvU32); + void (*__kbusDestroyFla__)(struct OBJGPU *, struct KernelBus *); + NV_STATUS (*__kbusGetFlaVaspace__)(struct OBJGPU *, struct KernelBus *, struct OBJVASPACE **); + void (*__kbusDestroyHostManagedFlaVaspace__)(struct OBJGPU *, struct KernelBus *, NvU32); + NvBool (*__kbusVerifyFlaRange__)(struct OBJGPU *, struct KernelBus *, NvU64, NvU64); + NV_STATUS (*__kbusConstructFlaInstBlk__)(struct OBJGPU *, struct KernelBus *, NvU32); + void (*__kbusDestructFlaInstBlk__)(struct OBJGPU *, struct KernelBus *); + NV_STATUS (*__kbusValidateFlaBaseAddress__)(struct OBJGPU *, struct KernelBus *, NvU64); + NV_STATUS (*__kbusSetupUnbindFla__)(struct OBJGPU *, struct KernelBus *); + NV_STATUS (*__kbusSetupBindFla__)(struct OBJGPU *, struct KernelBus *, NvU32); + void (*__kbusCacheBAR1ResizeSize_WAR_BUG_3249028__)(struct OBJGPU *, struct KernelBus *); + NV_STATUS (*__kbusRestoreBAR1ResizeSize_WAR_BUG_3249028__)(struct OBJGPU *, struct KernelBus *); + NV_STATUS (*__kbusIsDirectMappingAllowed__)(struct OBJGPU *, struct KernelBus *, PMEMORY_DESCRIPTOR, NvU32, NvBool *); + NV_STATUS (*__kbusUseDirectSysmemMap__)(struct OBJGPU *, struct KernelBus *, MEMORY_DESCRIPTOR *, NvBool *); + NV_STATUS (*__kbusWriteBAR0WindowBase__)(struct OBJGPU *, struct KernelBus *, NvU32); + NvU32 (*__kbusReadBAR0WindowBase__)(struct OBJGPU *, struct KernelBus *); + NvBool (*__kbusValidateBAR0WindowBase__)(struct OBJGPU *, struct KernelBus *, NvU32); + NV_STATUS (*__kbusSetBAR0WindowVidOffset__)(struct OBJGPU *, struct KernelBus *, NvU64); + NvU64 (*__kbusGetBAR0WindowVidOffset__)(struct OBJGPU *, struct KernelBus *); + NV_STATUS (*__kbusVerifyBar2__)(struct OBJGPU *, struct KernelBus *, PMEMORY_DESCRIPTOR, NvU8 *, NvU64, NvU64); + NV_STATUS (*__kbusVerifyCoherentLink__)(struct OBJGPU *, struct KernelBus *); + NV_STATUS (*__kbusFlushPcieForBar0Doorbell__)(struct OBJGPU *, struct KernelBus *); + NV_STATUS (*__kbusCreateCoherentCpuMapping__)(struct OBJGPU *, struct KernelBus *, NvU64, NvBool); + NvU8 *(*__kbusMapCoherentCpuMapping__)(struct OBJGPU *, struct KernelBus *, PMEMORY_DESCRIPTOR); + void (*__kbusUnmapCoherentCpuMapping__)(struct OBJGPU *, struct KernelBus *, PMEMORY_DESCRIPTOR); + void (*__kbusTeardownCoherentCpuMapping__)(struct OBJGPU *, struct KernelBus *, NvBool); NV_STATUS (*__kbusStateInitUnlocked__)(POBJGPU, struct KernelBus *); void (*__kbusInitMissing__)(POBJGPU, struct KernelBus *); NV_STATUS (*__kbusStatePreInitUnlocked__)(POBJGPU, struct KernelBus *); @@ -402,6 +403,7 @@ struct KernelBus { NvBool bFlaSupported; NvBool bFlaEnabled; NvBool bFlaDummyPageEnabled; + NvU8 bar1ResizeSizeIndex; struct __nvoc_inner_struc_KernelBus_5__ coherentCpuMapping; NvU64 coherentLinkTestBufferBase; struct __nvoc_inner_struc_KernelBus_6__ p2p; @@ -415,7 +417,6 @@ struct KernelBus { NvBool bP2pInitialized; NvBool bP2pMailboxClientAllocated; NvBool bP2pMailboxClientAllocatedBug3466714VoltaAndUp; - NvBool bBar1P2pCapable; NvBool bBar1Force64KBMapping; NvBool bBar1PhysicalModeEnabled; NvBool bIsBar2Initialized; @@ -428,8 +429,6 @@ struct KernelBus { NvBool bBarAccessBlocked; NvBool bBug2751296LimitBar2PtSize; NvBool bAllowReflectedMappingAccess; - NvBool bBar2Tunnelled; - NvBool bBar2InternalOnly; NvBool bIsEntireBar2RegionVirtuallyAddressible; NvBool bSkipBar2TestOnGc6Exit; NvBool bFbFlushDisabled; @@ -437,6 +436,7 @@ struct KernelBus { NvU8 *pReadToFlush; NvBool bReadCpuPointerToFlush; NvBool PDB_PROP_KBUS_NVLINK_DECONFIG_HSHUB_ON_NO_MAPPING; + NvBool PDB_PROP_KBUS_RESTORE_BAR1_SIZE_BUG_3249028_WAR; NvU32 PTEBAR2Aperture; NvU32 PTEBAR2Attr; NvU32 PDEBAR2Aperture; @@ -466,6 +466,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelBus; ((KernelBus*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(KernelBus))) #endif //__nvoc_kern_bus_h_disabled +#define PDB_PROP_KBUS_RESTORE_BAR1_SIZE_BUG_3249028_WAR_BASE_CAST +#define PDB_PROP_KBUS_RESTORE_BAR1_SIZE_BUG_3249028_WAR_BASE_NAME PDB_PROP_KBUS_RESTORE_BAR1_SIZE_BUG_3249028_WAR #define PDB_PROP_KBUS_IS_MISSING_BASE_CAST __nvoc_base_OBJENGSTATE. #define PDB_PROP_KBUS_IS_MISSING_BASE_NAME PDB_PROP_ENGSTATE_IS_MISSING #define PDB_PROP_KBUS_NVLINK_DECONFIG_HSHUB_ON_NO_MAPPING_BASE_CAST @@ -491,6 +493,8 @@ NV_STATUS __nvoc_objCreate_KernelBus(KernelBus**, Dynamic*, NvU32); #define kbusStatePreUnload_HAL(pGpu, pKernelBus, arg0) kbusStatePreUnload_DISPATCH(pGpu, pKernelBus, arg0) #define kbusStateUnload(pGpu, pKernelBus, flags) kbusStateUnload_DISPATCH(pGpu, pKernelBus, flags) #define kbusStateUnload_HAL(pGpu, pKernelBus, flags) kbusStateUnload_DISPATCH(pGpu, pKernelBus, flags) +#define kbusStatePostUnload(pGpu, pKernelBus, flags) kbusStatePostUnload_DISPATCH(pGpu, pKernelBus, flags) +#define kbusStatePostUnload_HAL(pGpu, pKernelBus, flags) kbusStatePostUnload_DISPATCH(pGpu, pKernelBus, flags) #define kbusStateDestroy(pGpu, pKernelBus) kbusStateDestroy_DISPATCH(pGpu, pKernelBus) #define kbusStateDestroy_HAL(pGpu, pKernelBus) kbusStateDestroy_DISPATCH(pGpu, pKernelBus) #define kbusTeardownBar2CpuAperture(pGpu, pKernelBus, gfid) kbusTeardownBar2CpuAperture_DISPATCH(pGpu, pKernelBus, gfid) @@ -527,18 +531,18 @@ NV_STATUS __nvoc_objCreate_KernelBus(KernelBus**, Dynamic*, NvU32); #define kbusRemoveP2PMappingForC2C_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) kbusRemoveP2PMappingForC2C_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) #define kbusUnreserveP2PPeerIds(pGpu, pKernelBus, peerMask) kbusUnreserveP2PPeerIds_DISPATCH(pGpu, pKernelBus, peerMask) #define kbusUnreserveP2PPeerIds_HAL(pGpu, pKernelBus, peerMask) kbusUnreserveP2PPeerIds_DISPATCH(pGpu, pKernelBus, peerMask) -#define kbusNeedStaticBar1Mapping(pGpu, pKernelBus) kbusNeedStaticBar1Mapping_DISPATCH(pGpu, pKernelBus) -#define kbusNeedStaticBar1Mapping_HAL(pGpu, pKernelBus) kbusNeedStaticBar1Mapping_DISPATCH(pGpu, pKernelBus) -#define kbusEnableStaticBar1Mapping(pGpu, pKernelBus, reservedFbSize, gfid) kbusEnableStaticBar1Mapping_DISPATCH(pGpu, pKernelBus, reservedFbSize, gfid) -#define kbusEnableStaticBar1Mapping_HAL(pGpu, pKernelBus, reservedFbSize, gfid) kbusEnableStaticBar1Mapping_DISPATCH(pGpu, pKernelBus, reservedFbSize, gfid) +#define kbusIsBar1P2PCapable(pGpu, pKernelBus, gfid) kbusIsBar1P2PCapable_DISPATCH(pGpu, pKernelBus, gfid) +#define kbusIsBar1P2PCapable_HAL(pGpu, pKernelBus, gfid) kbusIsBar1P2PCapable_DISPATCH(pGpu, pKernelBus, gfid) +#define kbusEnableStaticBar1Mapping(pGpu, pKernelBus, gfid) kbusEnableStaticBar1Mapping_DISPATCH(pGpu, pKernelBus, gfid) +#define kbusEnableStaticBar1Mapping_HAL(pGpu, pKernelBus, gfid) kbusEnableStaticBar1Mapping_DISPATCH(pGpu, pKernelBus, gfid) #define kbusDisableStaticBar1Mapping(pGpu, pKernelBus, gfid) kbusDisableStaticBar1Mapping_DISPATCH(pGpu, pKernelBus, gfid) #define kbusDisableStaticBar1Mapping_HAL(pGpu, pKernelBus, gfid) kbusDisableStaticBar1Mapping_DISPATCH(pGpu, pKernelBus, gfid) #define kbusGetBar1P2PDmaInfo(pSrcGpu, pPeerGpu, pPeerKernelBus, dma_addr, dma_size) kbusGetBar1P2PDmaInfo_DISPATCH(pSrcGpu, pPeerGpu, pPeerKernelBus, dma_addr, dma_size) #define kbusGetBar1P2PDmaInfo_HAL(pSrcGpu, pPeerGpu, pPeerKernelBus, dma_addr, dma_size) kbusGetBar1P2PDmaInfo_DISPATCH(pSrcGpu, pPeerGpu, pPeerKernelBus, dma_addr, dma_size) -#define kbusStaticMapFbAperture(pGpu, pKernelBus, pMemDesc, offset, pAperOffset, pLength, gfid) kbusStaticMapFbAperture_DISPATCH(pGpu, pKernelBus, pMemDesc, offset, pAperOffset, pLength, gfid) -#define kbusStaticMapFbAperture_HAL(pGpu, pKernelBus, pMemDesc, offset, pAperOffset, pLength, gfid) kbusStaticMapFbAperture_DISPATCH(pGpu, pKernelBus, pMemDesc, offset, pAperOffset, pLength, gfid) -#define kbusStaticUnmapFbAperture(pGpu, pKernelBus, pMemDesc, gfid) kbusStaticUnmapFbAperture_DISPATCH(pGpu, pKernelBus, pMemDesc, gfid) -#define kbusStaticUnmapFbAperture_HAL(pGpu, pKernelBus, pMemDesc, gfid) kbusStaticUnmapFbAperture_DISPATCH(pGpu, pKernelBus, pMemDesc, gfid) +#define kbusUpdateStaticBar1VAMapping(pGpu, pKernelBus, pMemDesc, offset, length, bRelease) kbusUpdateStaticBar1VAMapping_DISPATCH(pGpu, pKernelBus, pMemDesc, offset, length, bRelease) +#define kbusUpdateStaticBar1VAMapping_HAL(pGpu, pKernelBus, pMemDesc, offset, length, bRelease) kbusUpdateStaticBar1VAMapping_DISPATCH(pGpu, pKernelBus, pMemDesc, offset, length, bRelease) +#define kbusGetStaticFbAperture(pGpu, pKernelBus, pMemDesc, offset, pAperOffset, pLength, gfid) kbusGetStaticFbAperture_DISPATCH(pGpu, pKernelBus, pMemDesc, offset, pAperOffset, pLength, gfid) +#define kbusGetStaticFbAperture_HAL(pGpu, pKernelBus, pMemDesc, offset, pAperOffset, pLength, gfid) kbusGetStaticFbAperture_DISPATCH(pGpu, pKernelBus, pMemDesc, offset, pAperOffset, pLength, gfid) #define kbusCreateP2PMappingForBar1P2P(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes) kbusCreateP2PMappingForBar1P2P_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes) #define kbusCreateP2PMappingForBar1P2P_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes) kbusCreateP2PMappingForBar1P2P_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes) #define kbusRemoveP2PMappingForBar1P2P(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes) kbusRemoveP2PMappingForBar1P2P_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes) @@ -547,8 +551,6 @@ NV_STATUS __nvoc_objCreate_KernelBus(KernelBus**, Dynamic*, NvU32); #define kbusHasPcieBar1P2PMapping_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1) kbusHasPcieBar1P2PMapping_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1) #define kbusIsPcieBar1P2PMappingSupported(pGpu0, pKernelBus0, pGpu1, pKernelBus1) kbusIsPcieBar1P2PMappingSupported_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1) #define kbusIsPcieBar1P2PMappingSupported_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1) kbusIsPcieBar1P2PMappingSupported_DISPATCH(pGpu0, pKernelBus0, pGpu1, pKernelBus1) -#define kbusSetupBar1P2PCapability(pGpu, pKernelBus) kbusSetupBar1P2PCapability_DISPATCH(pGpu, pKernelBus) -#define kbusSetupBar1P2PCapability_HAL(pGpu, pKernelBus) kbusSetupBar1P2PCapability_DISPATCH(pGpu, pKernelBus) #define kbusCheckFlaSupportedAndInit(pGpu, pKernelBus, base, size) kbusCheckFlaSupportedAndInit_DISPATCH(pGpu, pKernelBus, base, size) #define kbusCheckFlaSupportedAndInit_HAL(pGpu, pKernelBus, base, size) kbusCheckFlaSupportedAndInit_DISPATCH(pGpu, pKernelBus, base, size) #define kbusDetermineFlaRangeAndAllocate(pGpu, pKernelBus, base, size) kbusDetermineFlaRangeAndAllocate_DISPATCH(pGpu, pKernelBus, base, size) @@ -579,6 +581,10 @@ NV_STATUS __nvoc_objCreate_KernelBus(KernelBus**, Dynamic*, NvU32); #define kbusSetupUnbindFla_HAL(pGpu, pKernelBus) kbusSetupUnbindFla_DISPATCH(pGpu, pKernelBus) #define kbusSetupBindFla(pGpu, pKernelBus, gfid) kbusSetupBindFla_DISPATCH(pGpu, pKernelBus, gfid) #define kbusSetupBindFla_HAL(pGpu, pKernelBus, gfid) kbusSetupBindFla_DISPATCH(pGpu, pKernelBus, gfid) +#define kbusCacheBAR1ResizeSize_WAR_BUG_3249028(pGpu, pKernelBus) kbusCacheBAR1ResizeSize_WAR_BUG_3249028_DISPATCH(pGpu, pKernelBus) +#define kbusCacheBAR1ResizeSize_WAR_BUG_3249028_HAL(pGpu, pKernelBus) kbusCacheBAR1ResizeSize_WAR_BUG_3249028_DISPATCH(pGpu, pKernelBus) +#define kbusRestoreBAR1ResizeSize_WAR_BUG_3249028(pGpu, pKernelBus) kbusRestoreBAR1ResizeSize_WAR_BUG_3249028_DISPATCH(pGpu, pKernelBus) +#define kbusRestoreBAR1ResizeSize_WAR_BUG_3249028_HAL(pGpu, pKernelBus) kbusRestoreBAR1ResizeSize_WAR_BUG_3249028_DISPATCH(pGpu, pKernelBus) #define kbusIsDirectMappingAllowed(pGpu, pKernelBus, arg0, arg1, arg2) kbusIsDirectMappingAllowed_DISPATCH(pGpu, pKernelBus, arg0, arg1, arg2) #define kbusIsDirectMappingAllowed_HAL(pGpu, pKernelBus, arg0, arg1, arg2) kbusIsDirectMappingAllowed_DISPATCH(pGpu, pKernelBus, arg0, arg1, arg2) #define kbusUseDirectSysmemMap(pGpu, pKernelBus, arg0, arg1) kbusUseDirectSysmemMap_DISPATCH(pGpu, pKernelBus, arg0, arg1) @@ -607,16 +613,15 @@ NV_STATUS __nvoc_objCreate_KernelBus(KernelBus**, Dynamic*, NvU32); #define kbusUnmapCoherentCpuMapping_HAL(pGpu, pKernelBus, arg0) kbusUnmapCoherentCpuMapping_DISPATCH(pGpu, pKernelBus, arg0) #define kbusTeardownCoherentCpuMapping(pGpu, pKernelBus, arg0) kbusTeardownCoherentCpuMapping_DISPATCH(pGpu, pKernelBus, arg0) #define kbusTeardownCoherentCpuMapping_HAL(pGpu, pKernelBus, arg0) kbusTeardownCoherentCpuMapping_DISPATCH(pGpu, pKernelBus, arg0) -#define kbusStatePostUnload(pGpu, pEngstate, arg0) kbusStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) #define kbusStateInitUnlocked(pGpu, pEngstate) kbusStateInitUnlocked_DISPATCH(pGpu, pEngstate) #define kbusInitMissing(pGpu, pEngstate) kbusInitMissing_DISPATCH(pGpu, pEngstate) #define kbusStatePreInitUnlocked(pGpu, pEngstate) kbusStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) #define kbusIsPresent(pGpu, pEngstate) kbusIsPresent_DISPATCH(pGpu, pEngstate) -NV_STATUS kbusInitBarsSize_KERNEL(OBJGPU *pGpu, struct KernelBus *pKernelBus); +NV_STATUS kbusInitBarsSize_KERNEL(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusInitBarsSize(OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline NV_STATUS kbusInitBarsSize(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -626,11 +631,11 @@ static inline NV_STATUS kbusInitBarsSize(OBJGPU *pGpu, struct KernelBus *pKernel #define kbusInitBarsSize_HAL(pGpu, pKernelBus) kbusInitBarsSize(pGpu, pKernelBus) -NV_STATUS kbusConstructHal_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus); +NV_STATUS kbusConstructHal_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusConstructHal(OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline NV_STATUS kbusConstructHal(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -640,11 +645,11 @@ static inline NV_STATUS kbusConstructHal(OBJGPU *pGpu, struct KernelBus *pKernel #define kbusConstructHal_HAL(pGpu, pKernelBus) kbusConstructHal(pGpu, pKernelBus) -NV_STATUS kbusStateInitLockedKernel_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus); +NV_STATUS kbusStateInitLockedKernel_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusStateInitLockedKernel(OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline NV_STATUS kbusStateInitLockedKernel(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -654,15 +659,15 @@ static inline NV_STATUS kbusStateInitLockedKernel(OBJGPU *pGpu, struct KernelBus #define kbusStateInitLockedKernel_HAL(pGpu, pKernelBus) kbusStateInitLockedKernel(pGpu, pKernelBus) -static inline NV_STATUS kbusStateInitLockedPhysical_56cd7a(OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline NV_STATUS kbusStateInitLockedPhysical_56cd7a(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { return NV_OK; } -NV_STATUS kbusStateInitLockedPhysical_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus); +NV_STATUS kbusStateInitLockedPhysical_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusStateInitLockedPhysical(OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline NV_STATUS kbusStateInitLockedPhysical(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -672,13 +677,13 @@ static inline NV_STATUS kbusStateInitLockedPhysical(OBJGPU *pGpu, struct KernelB #define kbusStateInitLockedPhysical_HAL(pGpu, pKernelBus) kbusStateInitLockedPhysical(pGpu, pKernelBus) -NvU8 *kbusMapBar2Aperture_VBAR2_SRIOV(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU32 transfer_flags); +NvU8 *kbusMapBar2Aperture_VBAR2_SRIOV(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU32 transfer_flags); -NvU8 *kbusMapBar2Aperture_VBAR2(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU32 transfer_flags); +NvU8 *kbusMapBar2Aperture_VBAR2(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU32 transfer_flags); #ifdef __nvoc_kern_bus_h_disabled -static inline NvU8 *kbusMapBar2Aperture(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU32 transfer_flags) { +static inline NvU8 *kbusMapBar2Aperture(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU32 transfer_flags) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NULL; } @@ -688,13 +693,13 @@ static inline NvU8 *kbusMapBar2Aperture(OBJGPU *pGpu, struct KernelBus *pKernelB #define kbusMapBar2Aperture_HAL(pGpu, pKernelBus, pMemDesc, transfer_flags) kbusMapBar2Aperture(pGpu, pKernelBus, pMemDesc, transfer_flags) -NvU8 *kbusValidateBar2ApertureMapping_VBAR2_SRIOV(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU8 *p); +NvU8 *kbusValidateBar2ApertureMapping_VBAR2_SRIOV(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU8 *p); -NvU8 *kbusValidateBar2ApertureMapping_VBAR2(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU8 *p); +NvU8 *kbusValidateBar2ApertureMapping_VBAR2(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU8 *p); #ifdef __nvoc_kern_bus_h_disabled -static inline NvU8 *kbusValidateBar2ApertureMapping(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU8 *p) { +static inline NvU8 *kbusValidateBar2ApertureMapping(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU8 *p) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NULL; } @@ -704,13 +709,13 @@ static inline NvU8 *kbusValidateBar2ApertureMapping(OBJGPU *pGpu, struct KernelB #define kbusValidateBar2ApertureMapping_HAL(pGpu, pKernelBus, pMemDesc, p) kbusValidateBar2ApertureMapping(pGpu, pKernelBus, pMemDesc, p) -void kbusUnmapBar2ApertureWithFlags_VBAR2_SRIOV(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU8 **pCpuPtr, NvU32 flags); +void kbusUnmapBar2ApertureWithFlags_VBAR2_SRIOV(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU8 **pCpuPtr, NvU32 flags); -void kbusUnmapBar2ApertureWithFlags_VBAR2(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU8 **pCpuPtr, NvU32 flags); +void kbusUnmapBar2ApertureWithFlags_VBAR2(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU8 **pCpuPtr, NvU32 flags); #ifdef __nvoc_kern_bus_h_disabled -static inline void kbusUnmapBar2ApertureWithFlags(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU8 **pCpuPtr, NvU32 flags) { +static inline void kbusUnmapBar2ApertureWithFlags(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU8 **pCpuPtr, NvU32 flags) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); } #else //__nvoc_kern_bus_h_disabled @@ -719,11 +724,11 @@ static inline void kbusUnmapBar2ApertureWithFlags(OBJGPU *pGpu, struct KernelBus #define kbusUnmapBar2ApertureWithFlags_HAL(pGpu, pKernelBus, pMemDesc, pCpuPtr, flags) kbusUnmapBar2ApertureWithFlags(pGpu, pKernelBus, pMemDesc, pCpuPtr, flags) -NV_STATUS kbusUpdateRmAperture_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0, NvU64 arg1, NvU64 arg2, NvU32 arg3); +NV_STATUS kbusUpdateRmAperture_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0, NvU64 arg1, NvU64 arg2, NvU32 arg3); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusUpdateRmAperture(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0, NvU64 arg1, NvU64 arg2, NvU32 arg3) { +static inline NV_STATUS kbusUpdateRmAperture(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0, NvU64 arg1, NvU64 arg2, NvU32 arg3) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -733,11 +738,11 @@ static inline NV_STATUS kbusUpdateRmAperture(OBJGPU *pGpu, struct KernelBus *pKe #define kbusUpdateRmAperture_HAL(pGpu, pKernelBus, arg0, arg1, arg2, arg3) kbusUpdateRmAperture(pGpu, pKernelBus, arg0, arg1, arg2, arg3) -NV_STATUS kbusSetupBar2GpuVaSpace_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); +NV_STATUS kbusSetupBar2GpuVaSpace_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusSetupBar2GpuVaSpace(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { +static inline NV_STATUS kbusSetupBar2GpuVaSpace(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -747,11 +752,11 @@ static inline NV_STATUS kbusSetupBar2GpuVaSpace(OBJGPU *pGpu, struct KernelBus * #define kbusSetupBar2GpuVaSpace_HAL(pGpu, pKernelBus, gfid) kbusSetupBar2GpuVaSpace(pGpu, pKernelBus, gfid) -NV_STATUS kbusTeardownBar2GpuVaSpace_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); +NV_STATUS kbusTeardownBar2GpuVaSpace_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusTeardownBar2GpuVaSpace(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { +static inline NV_STATUS kbusTeardownBar2GpuVaSpace(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -761,11 +766,11 @@ static inline NV_STATUS kbusTeardownBar2GpuVaSpace(OBJGPU *pGpu, struct KernelBu #define kbusTeardownBar2GpuVaSpace_HAL(pGpu, pKernelBus, gfid) kbusTeardownBar2GpuVaSpace(pGpu, pKernelBus, gfid) -NvU32 kbusGetSizeOfBar2PageTables_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus); +NvU32 kbusGetSizeOfBar2PageTables_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); #ifdef __nvoc_kern_bus_h_disabled -static inline NvU32 kbusGetSizeOfBar2PageTables(OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline NvU32 kbusGetSizeOfBar2PageTables(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return 0; } @@ -775,11 +780,11 @@ static inline NvU32 kbusGetSizeOfBar2PageTables(OBJGPU *pGpu, struct KernelBus * #define kbusGetSizeOfBar2PageTables_HAL(pGpu, pKernelBus) kbusGetSizeOfBar2PageTables(pGpu, pKernelBus) -NvU32 kbusGetSizeOfBar2PageDirs_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus); +NvU32 kbusGetSizeOfBar2PageDirs_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); #ifdef __nvoc_kern_bus_h_disabled -static inline NvU32 kbusGetSizeOfBar2PageDirs(OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline NvU32 kbusGetSizeOfBar2PageDirs(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return 0; } @@ -789,13 +794,13 @@ static inline NvU32 kbusGetSizeOfBar2PageDirs(OBJGPU *pGpu, struct KernelBus *pK #define kbusGetSizeOfBar2PageDirs_HAL(pGpu, pKernelBus) kbusGetSizeOfBar2PageDirs(pGpu, pKernelBus) -NvU64 kbusGetVaLimitForBar2_KERNEL(OBJGPU *pGpu, struct KernelBus *pKernelBus); +NvU64 kbusGetVaLimitForBar2_KERNEL(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); -NvU64 kbusGetVaLimitForBar2_PHYSICAL(OBJGPU *pGpu, struct KernelBus *pKernelBus); +NvU64 kbusGetVaLimitForBar2_PHYSICAL(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); #ifdef __nvoc_kern_bus_h_disabled -static inline NvU64 kbusGetVaLimitForBar2(OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline NvU64 kbusGetVaLimitForBar2(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return 0; } @@ -805,11 +810,11 @@ static inline NvU64 kbusGetVaLimitForBar2(OBJGPU *pGpu, struct KernelBus *pKerne #define kbusGetVaLimitForBar2_HAL(pGpu, pKernelBus) kbusGetVaLimitForBar2(pGpu, pKernelBus) -NV_STATUS kbusCommitBar2_KERNEL(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 flags); +NV_STATUS kbusCommitBar2_KERNEL(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 flags); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusCommitBar2(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 flags) { +static inline NV_STATUS kbusCommitBar2(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 flags) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -847,11 +852,11 @@ static inline const struct GMMU_FMT *kbusGetBar2GmmuFmt(struct KernelBus *pKerne #define kbusGetBar2GmmuFmt_HAL(pKernelBus) kbusGetBar2GmmuFmt(pKernelBus) -NV_STATUS kbusPatchBar1Pdb_GSPCLIENT(OBJGPU *pGpu, struct KernelBus *pKernelBus); +NV_STATUS kbusPatchBar1Pdb_GSPCLIENT(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusPatchBar1Pdb(OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline NV_STATUS kbusPatchBar1Pdb(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -861,11 +866,11 @@ static inline NV_STATUS kbusPatchBar1Pdb(OBJGPU *pGpu, struct KernelBus *pKernel #define kbusPatchBar1Pdb_HAL(pGpu, pKernelBus) kbusPatchBar1Pdb(pGpu, pKernelBus) -NV_STATUS kbusPatchBar2Pdb_GSPCLIENT(OBJGPU *pGpu, struct KernelBus *pKernelBus); +NV_STATUS kbusPatchBar2Pdb_GSPCLIENT(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusPatchBar2Pdb(OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline NV_STATUS kbusPatchBar2Pdb(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -875,11 +880,11 @@ static inline NV_STATUS kbusPatchBar2Pdb(OBJGPU *pGpu, struct KernelBus *pKernel #define kbusPatchBar2Pdb_HAL(pGpu, pKernelBus) kbusPatchBar2Pdb(pGpu, pKernelBus) -NV_STATUS kbusSetBarsApertureSize_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); +NV_STATUS kbusSetBarsApertureSize_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusSetBarsApertureSize(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { +static inline NV_STATUS kbusSetBarsApertureSize(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -889,11 +894,11 @@ static inline NV_STATUS kbusSetBarsApertureSize(OBJGPU *pGpu, struct KernelBus * #define kbusSetBarsApertureSize_HAL(pGpu, pKernelBus, gfid) kbusSetBarsApertureSize(pGpu, pKernelBus, gfid) -NV_STATUS kbusConstructVirtualBar2_VBAR2(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); +NV_STATUS kbusConstructVirtualBar2_VBAR2(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusConstructVirtualBar2(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { +static inline NV_STATUS kbusConstructVirtualBar2(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -903,11 +908,11 @@ static inline NV_STATUS kbusConstructVirtualBar2(OBJGPU *pGpu, struct KernelBus #define kbusConstructVirtualBar2_HAL(pGpu, pKernelBus, gfid) kbusConstructVirtualBar2(pGpu, pKernelBus, gfid) -void kbusDestructVirtualBar2_VBAR2(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvBool shutdown, NvU32 gfid); +void kbusDestructVirtualBar2_VBAR2(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvBool shutdown, NvU32 gfid); #ifdef __nvoc_kern_bus_h_disabled -static inline void kbusDestructVirtualBar2(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvBool shutdown, NvU32 gfid) { +static inline void kbusDestructVirtualBar2(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvBool shutdown, NvU32 gfid) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); } #else //__nvoc_kern_bus_h_disabled @@ -916,11 +921,11 @@ static inline void kbusDestructVirtualBar2(OBJGPU *pGpu, struct KernelBus *pKern #define kbusDestructVirtualBar2_HAL(pGpu, pKernelBus, shutdown, gfid) kbusDestructVirtualBar2(pGpu, pKernelBus, shutdown, gfid) -void kbusFlushVirtualBar2_VBAR2(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvBool shutdown, NvU32 gfid); +void kbusFlushVirtualBar2_VBAR2(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvBool shutdown, NvU32 gfid); #ifdef __nvoc_kern_bus_h_disabled -static inline void kbusFlushVirtualBar2(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvBool shutdown, NvU32 gfid) { +static inline void kbusFlushVirtualBar2(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvBool shutdown, NvU32 gfid) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); } #else //__nvoc_kern_bus_h_disabled @@ -929,11 +934,11 @@ static inline void kbusFlushVirtualBar2(OBJGPU *pGpu, struct KernelBus *pKernelB #define kbusFlushVirtualBar2_HAL(pGpu, pKernelBus, shutdown, gfid) kbusFlushVirtualBar2(pGpu, pKernelBus, shutdown, gfid) -NV_STATUS kbusInitVirtualBar2_VBAR2(OBJGPU *pGpu, struct KernelBus *pKernelBus); +NV_STATUS kbusInitVirtualBar2_VBAR2(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusInitVirtualBar2(OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline NV_STATUS kbusInitVirtualBar2(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -943,11 +948,11 @@ static inline NV_STATUS kbusInitVirtualBar2(OBJGPU *pGpu, struct KernelBus *pKer #define kbusInitVirtualBar2_HAL(pGpu, pKernelBus) kbusInitVirtualBar2(pGpu, pKernelBus) -NV_STATUS kbusPreInitVirtualBar2_VBAR2(OBJGPU *pGpu, struct KernelBus *pKernelBus); +NV_STATUS kbusPreInitVirtualBar2_VBAR2(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusPreInitVirtualBar2(OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline NV_STATUS kbusPreInitVirtualBar2(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -989,15 +994,15 @@ static inline NV_STATUS kbusConstructVirtualBar2CpuInvisibleHeap(struct KernelBu #define kbusConstructVirtualBar2CpuInvisibleHeap_HAL(pKernelBus, gfid) kbusConstructVirtualBar2CpuInvisibleHeap(pKernelBus, gfid) -static inline NV_STATUS kbusMapCpuInvisibleBar2Aperture_46f6a7(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU64 *pVaddr, NvU64 allocSize, NvU32 allocFlags, NvU32 gfid) { +static inline NV_STATUS kbusMapCpuInvisibleBar2Aperture_46f6a7(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU64 *pVaddr, NvU64 allocSize, NvU32 allocFlags, NvU32 gfid) { return NV_ERR_NOT_SUPPORTED; } -NV_STATUS kbusMapCpuInvisibleBar2Aperture_VBAR2(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU64 *pVaddr, NvU64 allocSize, NvU32 allocFlags, NvU32 gfid); +NV_STATUS kbusMapCpuInvisibleBar2Aperture_VBAR2(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU64 *pVaddr, NvU64 allocSize, NvU32 allocFlags, NvU32 gfid); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusMapCpuInvisibleBar2Aperture(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU64 *pVaddr, NvU64 allocSize, NvU32 allocFlags, NvU32 gfid) { +static inline NV_STATUS kbusMapCpuInvisibleBar2Aperture(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU64 *pVaddr, NvU64 allocSize, NvU32 allocFlags, NvU32 gfid) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1007,15 +1012,15 @@ static inline NV_STATUS kbusMapCpuInvisibleBar2Aperture(OBJGPU *pGpu, struct Ker #define kbusMapCpuInvisibleBar2Aperture_HAL(pGpu, pKernelBus, pMemDesc, pVaddr, allocSize, allocFlags, gfid) kbusMapCpuInvisibleBar2Aperture(pGpu, pKernelBus, pMemDesc, pVaddr, allocSize, allocFlags, gfid) -static inline void kbusUnmapCpuInvisibleBar2Aperture_b3696a(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU64 vAddr, NvU32 gfid) { +static inline void kbusUnmapCpuInvisibleBar2Aperture_b3696a(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU64 vAddr, NvU32 gfid) { return; } -void kbusUnmapCpuInvisibleBar2Aperture_VBAR2(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU64 vAddr, NvU32 gfid); +void kbusUnmapCpuInvisibleBar2Aperture_VBAR2(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU64 vAddr, NvU32 gfid); #ifdef __nvoc_kern_bus_h_disabled -static inline void kbusUnmapCpuInvisibleBar2Aperture(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU64 vAddr, NvU32 gfid) { +static inline void kbusUnmapCpuInvisibleBar2Aperture(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU64 vAddr, NvU32 gfid) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); } #else //__nvoc_kern_bus_h_disabled @@ -1024,11 +1029,11 @@ static inline void kbusUnmapCpuInvisibleBar2Aperture(OBJGPU *pGpu, struct Kernel #define kbusUnmapCpuInvisibleBar2Aperture_HAL(pGpu, pKernelBus, pMemDesc, vAddr, gfid) kbusUnmapCpuInvisibleBar2Aperture(pGpu, pKernelBus, pMemDesc, vAddr, gfid) -NV_STATUS kbusSetupCpuPointerForBusFlush_GV100(OBJGPU *pGpu, struct KernelBus *pKernelBus); +NV_STATUS kbusSetupCpuPointerForBusFlush_GV100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusSetupCpuPointerForBusFlush(OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline NV_STATUS kbusSetupCpuPointerForBusFlush(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1038,11 +1043,11 @@ static inline NV_STATUS kbusSetupCpuPointerForBusFlush(OBJGPU *pGpu, struct Kern #define kbusSetupCpuPointerForBusFlush_HAL(pGpu, pKernelBus) kbusSetupCpuPointerForBusFlush(pGpu, pKernelBus) -void kbusDestroyCpuPointerForBusFlush_GV100(OBJGPU *pGpu, struct KernelBus *pKernelBus); +void kbusDestroyCpuPointerForBusFlush_GV100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); #ifdef __nvoc_kern_bus_h_disabled -static inline void kbusDestroyCpuPointerForBusFlush(OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline void kbusDestroyCpuPointerForBusFlush(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); } #else //__nvoc_kern_bus_h_disabled @@ -1051,11 +1056,11 @@ static inline void kbusDestroyCpuPointerForBusFlush(OBJGPU *pGpu, struct KernelB #define kbusDestroyCpuPointerForBusFlush_HAL(pGpu, pKernelBus) kbusDestroyCpuPointerForBusFlush(pGpu, pKernelBus) -NV_STATUS kbusSetupBar2CpuAperture_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); +NV_STATUS kbusSetupBar2CpuAperture_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusSetupBar2CpuAperture(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { +static inline NV_STATUS kbusSetupBar2CpuAperture(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1065,11 +1070,11 @@ static inline NV_STATUS kbusSetupBar2CpuAperture(OBJGPU *pGpu, struct KernelBus #define kbusSetupBar2CpuAperture_HAL(pGpu, pKernelBus, gfid) kbusSetupBar2CpuAperture(pGpu, pKernelBus, gfid) -NV_STATUS kbusSetP2PMailboxBar1Area_GM200(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 mailboxBar1Addr, NvU32 mailboxTotalSize); +NV_STATUS kbusSetP2PMailboxBar1Area_GM200(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 mailboxBar1Addr, NvU32 mailboxTotalSize); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusSetP2PMailboxBar1Area(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 mailboxBar1Addr, NvU32 mailboxTotalSize) { +static inline NV_STATUS kbusSetP2PMailboxBar1Area(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 mailboxBar1Addr, NvU32 mailboxTotalSize) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1079,11 +1084,11 @@ static inline NV_STATUS kbusSetP2PMailboxBar1Area(OBJGPU *pGpu, struct KernelBus #define kbusSetP2PMailboxBar1Area_HAL(pGpu, pKernelBus, mailboxBar1Addr, mailboxTotalSize) kbusSetP2PMailboxBar1Area(pGpu, pKernelBus, mailboxBar1Addr, mailboxTotalSize) -void kbusUnsetP2PMailboxBar1Area_GM200(OBJGPU *pGpu, struct KernelBus *pKernelBus); +void kbusUnsetP2PMailboxBar1Area_GM200(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); #ifdef __nvoc_kern_bus_h_disabled -static inline void kbusUnsetP2PMailboxBar1Area(OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline void kbusUnsetP2PMailboxBar1Area(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); } #else //__nvoc_kern_bus_h_disabled @@ -1092,11 +1097,11 @@ static inline void kbusUnsetP2PMailboxBar1Area(OBJGPU *pGpu, struct KernelBus *p #define kbusUnsetP2PMailboxBar1Area_HAL(pGpu, pKernelBus) kbusUnsetP2PMailboxBar1Area(pGpu, pKernelBus) -NV_STATUS kbusAllocP2PMailboxBar1_GM200(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid, NvU64 vaRangeMax); +NV_STATUS kbusAllocP2PMailboxBar1_GM200(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid, NvU64 vaRangeMax); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusAllocP2PMailboxBar1(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid, NvU64 vaRangeMax) { +static inline NV_STATUS kbusAllocP2PMailboxBar1(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid, NvU64 vaRangeMax) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1106,11 +1111,11 @@ static inline NV_STATUS kbusAllocP2PMailboxBar1(OBJGPU *pGpu, struct KernelBus * #define kbusAllocP2PMailboxBar1_HAL(pGpu, pKernelBus, gfid, vaRangeMax) kbusAllocP2PMailboxBar1(pGpu, pKernelBus, gfid, vaRangeMax) -RmPhysAddr kbusSetupMailboxAccess_GM200(OBJGPU *pGpu, struct KernelBus *pKernelBus, OBJGPU *pGpu1, NvU32 localPeerId, PMEMORY_DESCRIPTOR *ppWMBoxMemDesc); +RmPhysAddr kbusSetupMailboxAccess_GM200(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, struct OBJGPU *pGpu1, NvU32 localPeerId, PMEMORY_DESCRIPTOR *ppWMBoxMemDesc); #ifdef __nvoc_kern_bus_h_disabled -static inline RmPhysAddr kbusSetupMailboxAccess(OBJGPU *pGpu, struct KernelBus *pKernelBus, OBJGPU *pGpu1, NvU32 localPeerId, PMEMORY_DESCRIPTOR *ppWMBoxMemDesc) { +static inline RmPhysAddr kbusSetupMailboxAccess(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, struct OBJGPU *pGpu1, NvU32 localPeerId, PMEMORY_DESCRIPTOR *ppWMBoxMemDesc) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); RmPhysAddr ret; portMemSet(&ret, 0, sizeof(RmPhysAddr)); @@ -1122,11 +1127,11 @@ static inline RmPhysAddr kbusSetupMailboxAccess(OBJGPU *pGpu, struct KernelBus * #define kbusSetupMailboxAccess_HAL(pGpu, pKernelBus, pGpu1, localPeerId, ppWMBoxMemDesc) kbusSetupMailboxAccess(pGpu, pKernelBus, pGpu1, localPeerId, ppWMBoxMemDesc) -void kbusDestroyPeerAccess_GM200(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 peerNum); +void kbusDestroyPeerAccess_GM200(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 peerNum); #ifdef __nvoc_kern_bus_h_disabled -static inline void kbusDestroyPeerAccess(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 peerNum) { +static inline void kbusDestroyPeerAccess(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 peerNum) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); } #else //__nvoc_kern_bus_h_disabled @@ -1135,15 +1140,15 @@ static inline void kbusDestroyPeerAccess(OBJGPU *pGpu, struct KernelBus *pKernel #define kbusDestroyPeerAccess_HAL(pGpu, pKernelBus, peerNum) kbusDestroyPeerAccess(pGpu, pKernelBus, peerNum) -NvU32 kbusGetNvlinkPeerId_GA100(OBJGPU *pGpu, struct KernelBus *pKernelBus, OBJGPU *pPeerGpu); +NvU32 kbusGetNvlinkPeerId_GA100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, struct OBJGPU *pPeerGpu); -static inline NvU32 kbusGetNvlinkPeerId_c732fb(OBJGPU *pGpu, struct KernelBus *pKernelBus, OBJGPU *pPeerGpu) { +static inline NvU32 kbusGetNvlinkPeerId_c732fb(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, struct OBJGPU *pPeerGpu) { return 4294967295U; } #ifdef __nvoc_kern_bus_h_disabled -static inline NvU32 kbusGetNvlinkPeerId(OBJGPU *pGpu, struct KernelBus *pKernelBus, OBJGPU *pPeerGpu) { +static inline NvU32 kbusGetNvlinkPeerId(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, struct OBJGPU *pPeerGpu) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return 0; } @@ -1153,11 +1158,11 @@ static inline NvU32 kbusGetNvlinkPeerId(OBJGPU *pGpu, struct KernelBus *pKernelB #define kbusGetNvlinkPeerId_HAL(pGpu, pKernelBus, pPeerGpu) kbusGetNvlinkPeerId(pGpu, pKernelBus, pPeerGpu) -NvU32 kbusGetPeerIdFromTable_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 locPeerIdx, NvU32 remPeerIdx); +NvU32 kbusGetPeerIdFromTable_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 locPeerIdx, NvU32 remPeerIdx); #ifdef __nvoc_kern_bus_h_disabled -static inline NvU32 kbusGetPeerIdFromTable(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 locPeerIdx, NvU32 remPeerIdx) { +static inline NvU32 kbusGetPeerIdFromTable(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 locPeerIdx, NvU32 remPeerIdx) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return 0; } @@ -1167,11 +1172,11 @@ static inline NvU32 kbusGetPeerIdFromTable(OBJGPU *pGpu, struct KernelBus *pKern #define kbusGetPeerIdFromTable_HAL(pGpu, pKernelBus, locPeerIdx, remPeerIdx) kbusGetPeerIdFromTable(pGpu, pKernelBus, locPeerIdx, remPeerIdx) -NvU32 kbusGetUnusedPeerId_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus); +NvU32 kbusGetUnusedPeerId_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); #ifdef __nvoc_kern_bus_h_disabled -static inline NvU32 kbusGetUnusedPeerId(OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline NvU32 kbusGetUnusedPeerId(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return 0; } @@ -1181,11 +1186,11 @@ static inline NvU32 kbusGetUnusedPeerId(OBJGPU *pGpu, struct KernelBus *pKernelB #define kbusGetUnusedPeerId_HAL(pGpu, pKernelBus) kbusGetUnusedPeerId(pGpu, pKernelBus) -NV_STATUS kbusReserveP2PPeerIds_GM200(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 peerMask); +NV_STATUS kbusReserveP2PPeerIds_GM200(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 peerMask); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusReserveP2PPeerIds(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 peerMask) { +static inline NV_STATUS kbusReserveP2PPeerIds(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 peerMask) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1195,11 +1200,11 @@ static inline NV_STATUS kbusReserveP2PPeerIds(OBJGPU *pGpu, struct KernelBus *pK #define kbusReserveP2PPeerIds_HAL(pGpu, pKernelBus, peerMask) kbusReserveP2PPeerIds(pGpu, pKernelBus, peerMask) -NV_STATUS kbusCreateP2PMappingForMailbox_GM200(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *peer0, NvU32 *peer1, NvU32 attributes); +NV_STATUS kbusCreateP2PMappingForMailbox_GM200(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *peer0, NvU32 *peer1, NvU32 attributes); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusCreateP2PMappingForMailbox(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *peer0, NvU32 *peer1, NvU32 attributes) { +static inline NV_STATUS kbusCreateP2PMappingForMailbox(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *peer0, NvU32 *peer1, NvU32 attributes) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1209,11 +1214,11 @@ static inline NV_STATUS kbusCreateP2PMappingForMailbox(OBJGPU *pGpu0, struct Ker #define kbusCreateP2PMappingForMailbox_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) kbusCreateP2PMappingForMailbox(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) -NV_STATUS kbusRemoveP2PMappingForMailbox_GM200(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 peer0, NvU32 peer1, NvU32 attributes); +NV_STATUS kbusRemoveP2PMappingForMailbox_GM200(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 peer0, NvU32 peer1, NvU32 attributes); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusRemoveP2PMappingForMailbox(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 peer0, NvU32 peer1, NvU32 attributes) { +static inline NV_STATUS kbusRemoveP2PMappingForMailbox(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 peer0, NvU32 peer1, NvU32 attributes) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1223,11 +1228,11 @@ static inline NV_STATUS kbusRemoveP2PMappingForMailbox(OBJGPU *pGpu0, struct Ker #define kbusRemoveP2PMappingForMailbox_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) kbusRemoveP2PMappingForMailbox(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) -void kbusSetupMailboxes_GM200(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 arg0, NvU32 arg1); +void kbusSetupMailboxes_GM200(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 arg0, NvU32 arg1); #ifdef __nvoc_kern_bus_h_disabled -static inline void kbusSetupMailboxes(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 arg0, NvU32 arg1) { +static inline void kbusSetupMailboxes(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 arg0, NvU32 arg1) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); } #else //__nvoc_kern_bus_h_disabled @@ -1236,11 +1241,11 @@ static inline void kbusSetupMailboxes(OBJGPU *pGpu0, struct KernelBus *pKernelBu #define kbusSetupMailboxes_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, arg0, arg1) kbusSetupMailboxes(pGpu0, pKernelBus0, pGpu1, pKernelBus1, arg0, arg1) -NV_STATUS kbusCreateP2PMappingForNvlink_GP100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *peer0, NvU32 *peer1, NvU32 attributes); +NV_STATUS kbusCreateP2PMappingForNvlink_GP100(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *peer0, NvU32 *peer1, NvU32 attributes); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusCreateP2PMappingForNvlink(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *peer0, NvU32 *peer1, NvU32 attributes) { +static inline NV_STATUS kbusCreateP2PMappingForNvlink(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *peer0, NvU32 *peer1, NvU32 attributes) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1250,11 +1255,11 @@ static inline NV_STATUS kbusCreateP2PMappingForNvlink(OBJGPU *pGpu0, struct Kern #define kbusCreateP2PMappingForNvlink_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) kbusCreateP2PMappingForNvlink(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) -NV_STATUS kbusRemoveP2PMappingForNvlink_GP100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 peer0, NvU32 peer1, NvU32 attributes); +NV_STATUS kbusRemoveP2PMappingForNvlink_GP100(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 peer0, NvU32 peer1, NvU32 attributes); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusRemoveP2PMappingForNvlink(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 peer0, NvU32 peer1, NvU32 attributes) { +static inline NV_STATUS kbusRemoveP2PMappingForNvlink(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 peer0, NvU32 peer1, NvU32 attributes) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1264,11 +1269,11 @@ static inline NV_STATUS kbusRemoveP2PMappingForNvlink(OBJGPU *pGpu0, struct Kern #define kbusRemoveP2PMappingForNvlink_HAL(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) kbusRemoveP2PMappingForNvlink(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes) -NvU32 kbusGetNvlinkPeerNumberMask_GP100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 peerId); +NvU32 kbusGetNvlinkPeerNumberMask_GP100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 peerId); #ifdef __nvoc_kern_bus_h_disabled -static inline NvU32 kbusGetNvlinkPeerNumberMask(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 peerId) { +static inline NvU32 kbusGetNvlinkPeerNumberMask(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 peerId) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return 0; } @@ -1278,11 +1283,11 @@ static inline NvU32 kbusGetNvlinkPeerNumberMask(OBJGPU *pGpu, struct KernelBus * #define kbusGetNvlinkPeerNumberMask_HAL(pGpu, pKernelBus, peerId) kbusGetNvlinkPeerNumberMask(pGpu, pKernelBus, peerId) -void kbusUnlinkP2P_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBu); +void kbusUnlinkP2P_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBu); #ifdef __nvoc_kern_bus_h_disabled -static inline void kbusUnlinkP2P(OBJGPU *pGpu, struct KernelBus *pKernelBu) { +static inline void kbusUnlinkP2P(struct OBJGPU *pGpu, struct KernelBus *pKernelBu) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); } #else //__nvoc_kern_bus_h_disabled @@ -1291,25 +1296,25 @@ static inline void kbusUnlinkP2P(OBJGPU *pGpu, struct KernelBus *pKernelBu) { #define kbusUnlinkP2P_HAL(pGpu, pKernelBu) kbusUnlinkP2P(pGpu, pKernelBu) -NV_STATUS kbusFlushSingle_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 flags); +NV_STATUS kbusFlushSingle_GV100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 flags); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusFlushSingle(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 flags) { +static inline NV_STATUS kbusFlushSingle(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 flags) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kern_bus_h_disabled -#define kbusFlushSingle(pGpu, pKernelBus, flags) kbusFlushSingle_GM107(pGpu, pKernelBus, flags) +#define kbusFlushSingle(pGpu, pKernelBus, flags) kbusFlushSingle_GV100(pGpu, pKernelBus, flags) #endif //__nvoc_kern_bus_h_disabled #define kbusFlushSingle_HAL(pGpu, pKernelBus, flags) kbusFlushSingle(pGpu, pKernelBus, flags) -NV_STATUS kbusSendSysmembarSingle_KERNEL(OBJGPU *pGpu, struct KernelBus *pKernelBus); +NV_STATUS kbusSendSysmembarSingle_KERNEL(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusSendSysmembarSingle(OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline NV_STATUS kbusSendSysmembarSingle(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1346,11 +1351,11 @@ static inline NV_STATUS kbusInitBarsBaseInfo(struct KernelBus *pKernelBus) { #define kbusInitBarsBaseInfo_HAL(pKernelBus) kbusInitBarsBaseInfo(pKernelBus) -NV_STATUS kbusMemAccessBar0Window_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 physAddr, void *pData, NvU64 accessSize, NvBool bRead, NV_ADDRESS_SPACE addrSpace); +NV_STATUS kbusMemAccessBar0Window_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 physAddr, void *pData, NvU64 accessSize, NvBool bRead, NV_ADDRESS_SPACE addrSpace); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusMemAccessBar0Window(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 physAddr, void *pData, NvU64 accessSize, NvBool bRead, NV_ADDRESS_SPACE addrSpace) { +static inline NV_STATUS kbusMemAccessBar0Window(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 physAddr, void *pData, NvU64 accessSize, NvBool bRead, NV_ADDRESS_SPACE addrSpace) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1360,11 +1365,11 @@ static inline NV_STATUS kbusMemAccessBar0Window(OBJGPU *pGpu, struct KernelBus * #define kbusMemAccessBar0Window_HAL(pGpu, pKernelBus, physAddr, pData, accessSize, bRead, addrSpace) kbusMemAccessBar0Window(pGpu, pKernelBus, physAddr, pData, accessSize, bRead, addrSpace) -NV_STATUS kbusMemCopyBar0Window_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, RmPhysAddr physAddr, void *pData, NvLength copySize, NvBool bRead); +NV_STATUS kbusMemCopyBar0Window_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, RmPhysAddr physAddr, void *pData, NvLength copySize, NvBool bRead); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusMemCopyBar0Window(OBJGPU *pGpu, struct KernelBus *pKernelBus, RmPhysAddr physAddr, void *pData, NvLength copySize, NvBool bRead) { +static inline NV_STATUS kbusMemCopyBar0Window(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, RmPhysAddr physAddr, void *pData, NvLength copySize, NvBool bRead) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1388,11 +1393,11 @@ static inline NvU64 kbusGetBAR0WindowAddress(struct KernelBus *pKernelBus) { #define kbusGetBAR0WindowAddress_HAL(pKernelBus) kbusGetBAR0WindowAddress(pKernelBus) -NV_STATUS kbusSetupBar0WindowBeforeBar2Bootstrap_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 *arg0); +NV_STATUS kbusSetupBar0WindowBeforeBar2Bootstrap_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 *arg0); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusSetupBar0WindowBeforeBar2Bootstrap(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 *arg0) { +static inline NV_STATUS kbusSetupBar0WindowBeforeBar2Bootstrap(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 *arg0) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1402,11 +1407,11 @@ static inline NV_STATUS kbusSetupBar0WindowBeforeBar2Bootstrap(OBJGPU *pGpu, str #define kbusSetupBar0WindowBeforeBar2Bootstrap_HAL(pGpu, pKernelBus, arg0) kbusSetupBar0WindowBeforeBar2Bootstrap(pGpu, pKernelBus, arg0) -void kbusRestoreBar0WindowAfterBar2Bootstrap_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 arg0); +void kbusRestoreBar0WindowAfterBar2Bootstrap_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 arg0); #ifdef __nvoc_kern_bus_h_disabled -static inline void kbusRestoreBar0WindowAfterBar2Bootstrap(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 arg0) { +static inline void kbusRestoreBar0WindowAfterBar2Bootstrap(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 arg0) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); } #else //__nvoc_kern_bus_h_disabled @@ -1415,11 +1420,11 @@ static inline void kbusRestoreBar0WindowAfterBar2Bootstrap(OBJGPU *pGpu, struct #define kbusRestoreBar0WindowAfterBar2Bootstrap_HAL(pGpu, pKernelBus, arg0) kbusRestoreBar0WindowAfterBar2Bootstrap(pGpu, pKernelBus, arg0) -NV_STATUS kbusInitBar2_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); +NV_STATUS kbusInitBar2_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusInitBar2(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { +static inline NV_STATUS kbusInitBar2(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1429,11 +1434,25 @@ static inline NV_STATUS kbusInitBar2(OBJGPU *pGpu, struct KernelBus *pKernelBus, #define kbusInitBar2_HAL(pGpu, pKernelBus, gfid) kbusInitBar2(pGpu, pKernelBus, gfid) -NV_STATUS kbusDestroyBar2_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); +NV_STATUS kbusRestoreBar2_GM107(struct KernelBus *pKernelBus, NvU32 flags); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusDestroyBar2(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { +static inline NV_STATUS kbusRestoreBar2(struct KernelBus *pKernelBus, NvU32 flags) { + NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kern_bus_h_disabled +#define kbusRestoreBar2(pKernelBus, flags) kbusRestoreBar2_GM107(pKernelBus, flags) +#endif //__nvoc_kern_bus_h_disabled + +#define kbusRestoreBar2_HAL(pKernelBus, flags) kbusRestoreBar2(pKernelBus, flags) + +NV_STATUS kbusDestroyBar2_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); + + +#ifdef __nvoc_kern_bus_h_disabled +static inline NV_STATUS kbusDestroyBar2(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1443,11 +1462,11 @@ static inline NV_STATUS kbusDestroyBar2(OBJGPU *pGpu, struct KernelBus *pKernelB #define kbusDestroyBar2_HAL(pGpu, pKernelBus, gfid) kbusDestroyBar2(pGpu, pKernelBus, gfid) -NV_STATUS kbusInitBar1_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); +NV_STATUS kbusInitBar1_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusInitBar1(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { +static inline NV_STATUS kbusInitBar1(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1457,11 +1476,11 @@ static inline NV_STATUS kbusInitBar1(OBJGPU *pGpu, struct KernelBus *pKernelBus, #define kbusInitBar1_HAL(pGpu, pKernelBus, gfid) kbusInitBar1(pGpu, pKernelBus, gfid) -NV_STATUS kbusDestroyBar1_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); +NV_STATUS kbusDestroyBar1_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusDestroyBar1(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { +static inline NV_STATUS kbusDestroyBar1(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1471,11 +1490,11 @@ static inline NV_STATUS kbusDestroyBar1(OBJGPU *pGpu, struct KernelBus *pKernelB #define kbusDestroyBar1_HAL(pGpu, pKernelBus, gfid) kbusDestroyBar1(pGpu, pKernelBus, gfid) -NV_STATUS kbusMapFbAperture_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0, NvU64 offset, NvU64 *pAperOffset, NvU64 *pLength, NvU32 flags, struct Device *pDevice); +NV_STATUS kbusMapFbAperture_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0, NvU64 offset, NvU64 *pAperOffset, NvU64 *pLength, NvU32 flags, struct Device *pDevice); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusMapFbAperture(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0, NvU64 offset, NvU64 *pAperOffset, NvU64 *pLength, NvU32 flags, struct Device *pDevice) { +static inline NV_STATUS kbusMapFbAperture(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0, NvU64 offset, NvU64 *pAperOffset, NvU64 *pLength, NvU32 flags, struct Device *pDevice) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1485,11 +1504,11 @@ static inline NV_STATUS kbusMapFbAperture(OBJGPU *pGpu, struct KernelBus *pKerne #define kbusMapFbAperture_HAL(pGpu, pKernelBus, arg0, offset, pAperOffset, pLength, flags, pDevice) kbusMapFbAperture(pGpu, pKernelBus, arg0, offset, pAperOffset, pLength, flags, pDevice) -NV_STATUS kbusUnmapFbAperture_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0, NvU64 aperOffset, NvU64 length, NvU32 flags); +NV_STATUS kbusUnmapFbAperture_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0, NvU64 aperOffset, NvU64 length, NvU32 flags); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusUnmapFbAperture(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0, NvU64 aperOffset, NvU64 length, NvU32 flags) { +static inline NV_STATUS kbusUnmapFbAperture(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0, NvU64 aperOffset, NvU64 length, NvU32 flags) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1499,11 +1518,11 @@ static inline NV_STATUS kbusUnmapFbAperture(OBJGPU *pGpu, struct KernelBus *pKer #define kbusUnmapFbAperture_HAL(pGpu, pKernelBus, arg0, aperOffset, length, flags) kbusUnmapFbAperture(pGpu, pKernelBus, arg0, aperOffset, length, flags) -void kbusReleaseRmAperture_VBAR2(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0); +void kbusReleaseRmAperture_VBAR2(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0); #ifdef __nvoc_kern_bus_h_disabled -static inline void kbusReleaseRmAperture(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0) { +static inline void kbusReleaseRmAperture(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); } #else //__nvoc_kern_bus_h_disabled @@ -1512,11 +1531,11 @@ static inline void kbusReleaseRmAperture(OBJGPU *pGpu, struct KernelBus *pKernel #define kbusReleaseRmAperture_HAL(pGpu, pKernelBus, arg0) kbusReleaseRmAperture(pGpu, pKernelBus, arg0) -struct OBJVASPACE *kbusGetBar1VASpace_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus); +struct OBJVASPACE *kbusGetBar1VASpace_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); #ifdef __nvoc_kern_bus_h_disabled -static inline struct OBJVASPACE *kbusGetBar1VASpace(OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline struct OBJVASPACE *kbusGetBar1VASpace(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NULL; } @@ -1526,13 +1545,13 @@ static inline struct OBJVASPACE *kbusGetBar1VASpace(OBJGPU *pGpu, struct KernelB #define kbusGetBar1VASpace_HAL(pGpu, pKernelBus) kbusGetBar1VASpace(pGpu, pKernelBus) -static inline NV_STATUS kbusInitInstBlk_56cd7a(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR pInstBlkMemDesc, PMEMORY_DESCRIPTOR pPDB, NvU64 vaLimit, NvU64 bigPageSize, struct OBJVASPACE *pVAS) { +static inline NV_STATUS kbusInitInstBlk_56cd7a(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR pInstBlkMemDesc, PMEMORY_DESCRIPTOR pPDB, NvU64 vaLimit, NvU64 bigPageSize, struct OBJVASPACE *pVAS) { return NV_OK; } #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusInitInstBlk(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR pInstBlkMemDesc, PMEMORY_DESCRIPTOR pPDB, NvU64 vaLimit, NvU64 bigPageSize, struct OBJVASPACE *pVAS) { +static inline NV_STATUS kbusInitInstBlk(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR pInstBlkMemDesc, PMEMORY_DESCRIPTOR pPDB, NvU64 vaLimit, NvU64 bigPageSize, struct OBJVASPACE *pVAS) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1542,15 +1561,15 @@ static inline NV_STATUS kbusInitInstBlk(OBJGPU *pGpu, struct KernelBus *pKernelB #define kbusInitInstBlk_HAL(pGpu, pKernelBus, pInstBlkMemDesc, pPDB, vaLimit, bigPageSize, pVAS) kbusInitInstBlk(pGpu, pKernelBus, pInstBlkMemDesc, pPDB, vaLimit, bigPageSize, pVAS) -static inline NV_STATUS kbusBar1InstBlkVasUpdate_56cd7a(OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline NV_STATUS kbusBar1InstBlkVasUpdate_56cd7a(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { return NV_OK; } -NV_STATUS kbusBar1InstBlkVasUpdate_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus); +NV_STATUS kbusBar1InstBlkVasUpdate_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusBar1InstBlkVasUpdate(OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline NV_STATUS kbusBar1InstBlkVasUpdate(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1560,11 +1579,11 @@ static inline NV_STATUS kbusBar1InstBlkVasUpdate(OBJGPU *pGpu, struct KernelBus #define kbusBar1InstBlkVasUpdate_HAL(pGpu, pKernelBus) kbusBar1InstBlkVasUpdate(pGpu, pKernelBus) -NvBool kbusCheckEngine_KERNEL(OBJGPU *pGpu, struct KernelBus *pKernelBus, ENGDESCRIPTOR desc); +NvBool kbusCheckEngine_KERNEL(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, ENGDESCRIPTOR desc); #ifdef __nvoc_kern_bus_h_disabled -static inline NvBool kbusCheckEngine(OBJGPU *pGpu, struct KernelBus *pKernelBus, ENGDESCRIPTOR desc) { +static inline NvBool kbusCheckEngine(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, ENGDESCRIPTOR desc) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_FALSE; } @@ -1574,11 +1593,11 @@ static inline NvBool kbusCheckEngine(OBJGPU *pGpu, struct KernelBus *pKernelBus, #define kbusCheckEngine_HAL(pGpu, pKernelBus, desc) kbusCheckEngine(pGpu, pKernelBus, desc) -NV_STATUS kbusFlush_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 flags); +NV_STATUS kbusFlush_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 flags); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusFlush(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 flags) { +static inline NV_STATUS kbusFlush(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 flags) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1588,13 +1607,13 @@ static inline NV_STATUS kbusFlush(OBJGPU *pGpu, struct KernelBus *pKernelBus, Nv #define kbusFlush_HAL(pGpu, pKernelBus, flags) kbusFlush(pGpu, pKernelBus, flags) -static inline void kbusTeardownCoherentCpuMappingAcr_b3696a(OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline void kbusTeardownCoherentCpuMappingAcr_b3696a(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { return; } #ifdef __nvoc_kern_bus_h_disabled -static inline void kbusTeardownCoherentCpuMappingAcr(OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline void kbusTeardownCoherentCpuMappingAcr(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); } #else //__nvoc_kern_bus_h_disabled @@ -1603,622 +1622,636 @@ static inline void kbusTeardownCoherentCpuMappingAcr(OBJGPU *pGpu, struct Kernel #define kbusTeardownCoherentCpuMappingAcr_HAL(pGpu, pKernelBus) kbusTeardownCoherentCpuMappingAcr(pGpu, pKernelBus) -NV_STATUS kbusConstructEngine_IMPL(OBJGPU *pGpu, struct KernelBus *pKernelBus, ENGDESCRIPTOR arg0); +NV_STATUS kbusConstructEngine_IMPL(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, ENGDESCRIPTOR arg0); -static inline NV_STATUS kbusConstructEngine_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, ENGDESCRIPTOR arg0) { +static inline NV_STATUS kbusConstructEngine_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, ENGDESCRIPTOR arg0) { return pKernelBus->__kbusConstructEngine__(pGpu, pKernelBus, arg0); } -NV_STATUS kbusStatePreInitLocked_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus); +NV_STATUS kbusStatePreInitLocked_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); -static inline NV_STATUS kbusStatePreInitLocked_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline NV_STATUS kbusStatePreInitLocked_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { return pKernelBus->__kbusStatePreInitLocked__(pGpu, pKernelBus); } -NV_STATUS kbusStateInitLocked_IMPL(OBJGPU *pGpu, struct KernelBus *pKernelBus); +NV_STATUS kbusStateInitLocked_IMPL(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); -static inline NV_STATUS kbusStateInitLocked_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline NV_STATUS kbusStateInitLocked_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { return pKernelBus->__kbusStateInitLocked__(pGpu, pKernelBus); } -static inline NV_STATUS kbusStatePreLoad_56cd7a(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0) { - return NV_OK; -} +NV_STATUS kbusStatePreLoad_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0); -static inline NV_STATUS kbusStatePreLoad_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0) { +static inline NV_STATUS kbusStatePreLoad_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0) { return pKernelBus->__kbusStatePreLoad__(pGpu, pKernelBus, arg0); } -NV_STATUS kbusStateLoad_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0); +NV_STATUS kbusStateLoad_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0); -static inline NV_STATUS kbusStateLoad_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0) { +static inline NV_STATUS kbusStateLoad_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0) { return pKernelBus->__kbusStateLoad__(pGpu, pKernelBus, arg0); } -NV_STATUS kbusStatePostLoad_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0); +NV_STATUS kbusStatePostLoad_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0); -static inline NV_STATUS kbusStatePostLoad_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0) { +static inline NV_STATUS kbusStatePostLoad_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0) { return pKernelBus->__kbusStatePostLoad__(pGpu, pKernelBus, arg0); } -NV_STATUS kbusStatePreUnload_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0); +NV_STATUS kbusStatePreUnload_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0); -static inline NV_STATUS kbusStatePreUnload_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0) { +static inline NV_STATUS kbusStatePreUnload_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0) { return pKernelBus->__kbusStatePreUnload__(pGpu, pKernelBus, arg0); } -NV_STATUS kbusStateUnload_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 flags); +NV_STATUS kbusStateUnload_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 flags); -static inline NV_STATUS kbusStateUnload_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 flags) { +static inline NV_STATUS kbusStateUnload_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 flags) { return pKernelBus->__kbusStateUnload__(pGpu, pKernelBus, flags); } -void kbusStateDestroy_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus); +NV_STATUS kbusStatePostUnload_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 flags); + +static inline NV_STATUS kbusStatePostUnload_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 flags) { + return pKernelBus->__kbusStatePostUnload__(pGpu, pKernelBus, flags); +} + +void kbusStateDestroy_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); -static inline void kbusStateDestroy_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline void kbusStateDestroy_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { pKernelBus->__kbusStateDestroy__(pGpu, pKernelBus); } -NV_STATUS kbusTeardownBar2CpuAperture_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); +NV_STATUS kbusTeardownBar2CpuAperture_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); -NV_STATUS kbusTeardownBar2CpuAperture_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); +NV_STATUS kbusTeardownBar2CpuAperture_GH100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); -static inline NV_STATUS kbusTeardownBar2CpuAperture_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { +static inline NV_STATUS kbusTeardownBar2CpuAperture_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { return pKernelBus->__kbusTeardownBar2CpuAperture__(pGpu, pKernelBus, gfid); } -NvU32 kbusGetP2PWriteMailboxAddressSize_GH100(OBJGPU *pGpu); +NvU32 kbusGetP2PWriteMailboxAddressSize_GH100(struct OBJGPU *pGpu); -static inline NvU32 kbusGetP2PWriteMailboxAddressSize_474d46(OBJGPU *pGpu) { +static inline NvU32 kbusGetP2PWriteMailboxAddressSize_474d46(struct OBJGPU *pGpu) { NV_ASSERT_OR_RETURN_PRECOMP(0, 0); } -NvU32 kbusGetP2PWriteMailboxAddressSize_STATIC_DISPATCH(OBJGPU *pGpu); +NvU32 kbusGetP2PWriteMailboxAddressSize_STATIC_DISPATCH(struct OBJGPU *pGpu); -void kbusGetP2PMailboxAttributes_GM200(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 *pMailboxAreaSize, NvU32 *pMailboxAlignmentSize, NvU32 *pMailboxMaxOffset64KB); +void kbusGetP2PMailboxAttributes_GM200(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 *pMailboxAreaSize, NvU32 *pMailboxAlignmentSize, NvU32 *pMailboxMaxOffset64KB); -void kbusGetP2PMailboxAttributes_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 *pMailboxAreaSize, NvU32 *pMailboxAlignmentSize, NvU32 *pMailboxMaxOffset64KB); +void kbusGetP2PMailboxAttributes_GH100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 *pMailboxAreaSize, NvU32 *pMailboxAlignmentSize, NvU32 *pMailboxMaxOffset64KB); -static inline void kbusGetP2PMailboxAttributes_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 *pMailboxAreaSize, NvU32 *pMailboxAlignmentSize, NvU32 *pMailboxMaxOffset64KB) { +static inline void kbusGetP2PMailboxAttributes_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 *pMailboxAreaSize, NvU32 *pMailboxAlignmentSize, NvU32 *pMailboxMaxOffset64KB) { pKernelBus->__kbusGetP2PMailboxAttributes__(pGpu, pKernelBus, pMailboxAreaSize, pMailboxAlignmentSize, pMailboxMaxOffset64KB); } -NV_STATUS kbusCreateP2PMapping_GP100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *peer0, NvU32 *peer1, NvU32 attributes); +NV_STATUS kbusCreateP2PMapping_GP100(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *peer0, NvU32 *peer1, NvU32 attributes); -NV_STATUS kbusCreateP2PMapping_GH100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *peer0, NvU32 *peer1, NvU32 attributes); +NV_STATUS kbusCreateP2PMapping_GH100(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *peer0, NvU32 *peer1, NvU32 attributes); -static inline NV_STATUS kbusCreateP2PMapping_DISPATCH(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *peer0, NvU32 *peer1, NvU32 attributes) { +static inline NV_STATUS kbusCreateP2PMapping_DISPATCH(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *peer0, NvU32 *peer1, NvU32 attributes) { return pKernelBus0->__kbusCreateP2PMapping__(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes); } -NV_STATUS kbusRemoveP2PMapping_GP100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 peer0, NvU32 peer1, NvU32 attributes); +NV_STATUS kbusRemoveP2PMapping_GP100(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 peer0, NvU32 peer1, NvU32 attributes); -NV_STATUS kbusRemoveP2PMapping_GH100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 peer0, NvU32 peer1, NvU32 attributes); +NV_STATUS kbusRemoveP2PMapping_GH100(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 peer0, NvU32 peer1, NvU32 attributes); -static inline NV_STATUS kbusRemoveP2PMapping_DISPATCH(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 peer0, NvU32 peer1, NvU32 attributes) { +static inline NV_STATUS kbusRemoveP2PMapping_DISPATCH(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 peer0, NvU32 peer1, NvU32 attributes) { return pKernelBus0->__kbusRemoveP2PMapping__(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes); } -NvU32 kbusGetEgmPeerId_GH100(OBJGPU *pLocalGpu, struct KernelBus *pLocalKernelBus, OBJGPU *pRemoteGpu); +NvU32 kbusGetEgmPeerId_GH100(struct OBJGPU *pLocalGpu, struct KernelBus *pLocalKernelBus, struct OBJGPU *pRemoteGpu); -static inline NvU32 kbusGetEgmPeerId_56cd7a(OBJGPU *pLocalGpu, struct KernelBus *pLocalKernelBus, OBJGPU *pRemoteGpu) { +static inline NvU32 kbusGetEgmPeerId_56cd7a(struct OBJGPU *pLocalGpu, struct KernelBus *pLocalKernelBus, struct OBJGPU *pRemoteGpu) { return NV_OK; } -static inline NvU32 kbusGetEgmPeerId_DISPATCH(OBJGPU *pLocalGpu, struct KernelBus *pLocalKernelBus, OBJGPU *pRemoteGpu) { +static inline NvU32 kbusGetEgmPeerId_DISPATCH(struct OBJGPU *pLocalGpu, struct KernelBus *pLocalKernelBus, struct OBJGPU *pRemoteGpu) { return pLocalKernelBus->__kbusGetEgmPeerId__(pLocalGpu, pLocalKernelBus, pRemoteGpu); } -NvU32 kbusGetPeerId_GP100(OBJGPU *pGpu, struct KernelBus *pKernelBus, OBJGPU *pPeerGpu); +NvU32 kbusGetPeerId_GP100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, struct OBJGPU *pPeerGpu); -NvU32 kbusGetPeerId_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, OBJGPU *pPeerGpu); +NvU32 kbusGetPeerId_GH100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, struct OBJGPU *pPeerGpu); -static inline NvU32 kbusGetPeerId_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, OBJGPU *pPeerGpu) { +static inline NvU32 kbusGetPeerId_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, struct OBJGPU *pPeerGpu) { return pKernelBus->__kbusGetPeerId__(pGpu, pKernelBus, pPeerGpu); } -NvU32 kbusGetNvSwitchPeerId_GA100(OBJGPU *pGpu, struct KernelBus *pKernelBus); +NvU32 kbusGetNvSwitchPeerId_GA100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); -static inline NvU32 kbusGetNvSwitchPeerId_c732fb(OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline NvU32 kbusGetNvSwitchPeerId_c732fb(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { return 4294967295U; } -static inline NvU32 kbusGetNvSwitchPeerId_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline NvU32 kbusGetNvSwitchPeerId_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { return pKernelBus->__kbusGetNvSwitchPeerId__(pGpu, pKernelBus); } -NvU32 kbusGetUnusedPciePeerId_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus); +NvU32 kbusGetUnusedPciePeerId_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); -NvU32 kbusGetUnusedPciePeerId_TU102(OBJGPU *pGpu, struct KernelBus *pKernelBus); +NvU32 kbusGetUnusedPciePeerId_TU102(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); -static inline NvU32 kbusGetUnusedPciePeerId_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline NvU32 kbusGetUnusedPciePeerId_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { return pKernelBus->__kbusGetUnusedPciePeerId__(pGpu, pKernelBus); } -NV_STATUS kbusIsPeerIdValid_GP100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 peerId); +NV_STATUS kbusIsPeerIdValid_GP100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 peerId); -NV_STATUS kbusIsPeerIdValid_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 peerId); +NV_STATUS kbusIsPeerIdValid_GH100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 peerId); -static inline NV_STATUS kbusIsPeerIdValid_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 peerId) { +static inline NV_STATUS kbusIsPeerIdValid_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 peerId) { return pKernelBus->__kbusIsPeerIdValid__(pGpu, pKernelBus, peerId); } -NV_STATUS kbusGetNvlinkP2PPeerId_GP100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *nvlinkPeer, NvU32 attributes); +NV_STATUS kbusGetNvlinkP2PPeerId_GP100(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *nvlinkPeer, NvU32 attributes); -NV_STATUS kbusGetNvlinkP2PPeerId_GA100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *nvlinkPeer, NvU32 attributes); +NV_STATUS kbusGetNvlinkP2PPeerId_GA100(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *nvlinkPeer, NvU32 attributes); -static inline NV_STATUS kbusGetNvlinkP2PPeerId_56cd7a(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *nvlinkPeer, NvU32 attributes) { +static inline NV_STATUS kbusGetNvlinkP2PPeerId_56cd7a(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *nvlinkPeer, NvU32 attributes) { return NV_OK; } -static inline NV_STATUS kbusGetNvlinkP2PPeerId_DISPATCH(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *nvlinkPeer, NvU32 attributes) { +static inline NV_STATUS kbusGetNvlinkP2PPeerId_DISPATCH(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *nvlinkPeer, NvU32 attributes) { return pKernelBus0->__kbusGetNvlinkP2PPeerId__(pGpu0, pKernelBus0, pGpu1, pKernelBus1, nvlinkPeer, attributes); } -void kbusWriteP2PWmbTag_GM200(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 remote2Local, NvU64 p2pWmbTag); +void kbusWriteP2PWmbTag_GM200(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 remote2Local, NvU64 p2pWmbTag); -void kbusWriteP2PWmbTag_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 remote2Local, NvU64 p2pWmbTag); +void kbusWriteP2PWmbTag_GH100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 remote2Local, NvU64 p2pWmbTag); -static inline void kbusWriteP2PWmbTag_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 remote2Local, NvU64 p2pWmbTag) { +static inline void kbusWriteP2PWmbTag_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 remote2Local, NvU64 p2pWmbTag) { pKernelBus->__kbusWriteP2PWmbTag__(pGpu, pKernelBus, remote2Local, p2pWmbTag); } -RmPhysAddr kbusSetupP2PDomainAccess_GM200(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, PMEMORY_DESCRIPTOR *ppP2PDomMemDesc); +RmPhysAddr kbusSetupP2PDomainAccess_GM200(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, PMEMORY_DESCRIPTOR *ppP2PDomMemDesc); -RmPhysAddr kbusSetupP2PDomainAccess_GH100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, PMEMORY_DESCRIPTOR *ppP2PDomMemDesc); +RmPhysAddr kbusSetupP2PDomainAccess_GH100(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, PMEMORY_DESCRIPTOR *ppP2PDomMemDesc); -static inline RmPhysAddr kbusSetupP2PDomainAccess_DISPATCH(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, PMEMORY_DESCRIPTOR *ppP2PDomMemDesc) { +static inline RmPhysAddr kbusSetupP2PDomainAccess_DISPATCH(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, PMEMORY_DESCRIPTOR *ppP2PDomMemDesc) { return pKernelBus0->__kbusSetupP2PDomainAccess__(pGpu0, pKernelBus0, pGpu1, ppP2PDomMemDesc); } -NvBool kbusNeedWarForBug999673_GM200(OBJGPU *pGpu, struct KernelBus *pKernelBus, OBJGPU *pRemoteGpu); +NvBool kbusNeedWarForBug999673_GM200(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, struct OBJGPU *pRemoteGpu); -static inline NvBool kbusNeedWarForBug999673_491d52(OBJGPU *pGpu, struct KernelBus *pKernelBus, OBJGPU *pRemoteGpu) { +static inline NvBool kbusNeedWarForBug999673_491d52(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, struct OBJGPU *pRemoteGpu) { return ((NvBool)(0 != 0)); } -static inline NvBool kbusNeedWarForBug999673_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, OBJGPU *pRemoteGpu) { +static inline NvBool kbusNeedWarForBug999673_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, struct OBJGPU *pRemoteGpu) { return pKernelBus->__kbusNeedWarForBug999673__(pGpu, pKernelBus, pRemoteGpu); } -NV_STATUS kbusCreateP2PMappingForC2C_GH100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *peer0, NvU32 *peer1, NvU32 attributes); +NV_STATUS kbusCreateP2PMappingForC2C_GH100(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *peer0, NvU32 *peer1, NvU32 attributes); -static inline NV_STATUS kbusCreateP2PMappingForC2C_46f6a7(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *peer0, NvU32 *peer1, NvU32 attributes) { +static inline NV_STATUS kbusCreateP2PMappingForC2C_46f6a7(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *peer0, NvU32 *peer1, NvU32 attributes) { return NV_ERR_NOT_SUPPORTED; } -static inline NV_STATUS kbusCreateP2PMappingForC2C_DISPATCH(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *peer0, NvU32 *peer1, NvU32 attributes) { +static inline NV_STATUS kbusCreateP2PMappingForC2C_DISPATCH(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *peer0, NvU32 *peer1, NvU32 attributes) { return pKernelBus0->__kbusCreateP2PMappingForC2C__(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes); } -NV_STATUS kbusRemoveP2PMappingForC2C_GH100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 peer0, NvU32 peer1, NvU32 attributes); +NV_STATUS kbusRemoveP2PMappingForC2C_GH100(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 peer0, NvU32 peer1, NvU32 attributes); -static inline NV_STATUS kbusRemoveP2PMappingForC2C_46f6a7(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 peer0, NvU32 peer1, NvU32 attributes) { +static inline NV_STATUS kbusRemoveP2PMappingForC2C_46f6a7(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 peer0, NvU32 peer1, NvU32 attributes) { return NV_ERR_NOT_SUPPORTED; } -static inline NV_STATUS kbusRemoveP2PMappingForC2C_DISPATCH(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 peer0, NvU32 peer1, NvU32 attributes) { +static inline NV_STATUS kbusRemoveP2PMappingForC2C_DISPATCH(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 peer0, NvU32 peer1, NvU32 attributes) { return pKernelBus0->__kbusRemoveP2PMappingForC2C__(pGpu0, pKernelBus0, pGpu1, pKernelBus1, peer0, peer1, attributes); } -NV_STATUS kbusUnreserveP2PPeerIds_GP100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 peerMask); +NV_STATUS kbusUnreserveP2PPeerIds_GP100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 peerMask); -static inline NV_STATUS kbusUnreserveP2PPeerIds_46f6a7(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 peerMask) { +static inline NV_STATUS kbusUnreserveP2PPeerIds_46f6a7(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 peerMask) { return NV_ERR_NOT_SUPPORTED; } -static inline NV_STATUS kbusUnreserveP2PPeerIds_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 peerMask) { +static inline NV_STATUS kbusUnreserveP2PPeerIds_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 peerMask) { return pKernelBus->__kbusUnreserveP2PPeerIds__(pGpu, pKernelBus, peerMask); } -NvBool kbusNeedStaticBar1Mapping_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus); +NvBool kbusIsBar1P2PCapable_GH100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); -static inline NvBool kbusNeedStaticBar1Mapping_bf6dfa(OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline NvBool kbusIsBar1P2PCapable_bf6dfa(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { return ((NvBool)(0 != 0)); } -static inline NvBool kbusNeedStaticBar1Mapping_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus) { - return pKernelBus->__kbusNeedStaticBar1Mapping__(pGpu, pKernelBus); +static inline NvBool kbusIsBar1P2PCapable_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { + return pKernelBus->__kbusIsBar1P2PCapable__(pGpu, pKernelBus, gfid); } -NV_STATUS kbusEnableStaticBar1Mapping_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 reservedFbSize, NvU32 gfid); +NV_STATUS kbusEnableStaticBar1Mapping_GH100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); -static inline NV_STATUS kbusEnableStaticBar1Mapping_46f6a7(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 reservedFbSize, NvU32 gfid) { +static inline NV_STATUS kbusEnableStaticBar1Mapping_395e98(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { return NV_ERR_NOT_SUPPORTED; } -static inline NV_STATUS kbusEnableStaticBar1Mapping_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 reservedFbSize, NvU32 gfid) { - return pKernelBus->__kbusEnableStaticBar1Mapping__(pGpu, pKernelBus, reservedFbSize, gfid); +static inline NV_STATUS kbusEnableStaticBar1Mapping_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { + return pKernelBus->__kbusEnableStaticBar1Mapping__(pGpu, pKernelBus, gfid); } -NV_STATUS kbusDisableStaticBar1Mapping_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); - -static inline NV_STATUS kbusDisableStaticBar1Mapping_56cd7a(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { - return NV_OK; +static inline void kbusDisableStaticBar1Mapping_d44104(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { + return; } -static inline NV_STATUS kbusDisableStaticBar1Mapping_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { - return pKernelBus->__kbusDisableStaticBar1Mapping__(pGpu, pKernelBus, gfid); +void kbusDisableStaticBar1Mapping_GH100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); + +static inline void kbusDisableStaticBar1Mapping_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { + pKernelBus->__kbusDisableStaticBar1Mapping__(pGpu, pKernelBus, gfid); } -NV_STATUS kbusGetBar1P2PDmaInfo_GH100(OBJGPU *pSrcGpu, OBJGPU *pPeerGpu, struct KernelBus *pPeerKernelBus, NvU64 *dma_addr, NvU64 *dma_size); +NV_STATUS kbusGetBar1P2PDmaInfo_GH100(struct OBJGPU *pSrcGpu, struct OBJGPU *pPeerGpu, struct KernelBus *pPeerKernelBus, NvU64 *dma_addr, NvU64 *dma_size); -static inline NV_STATUS kbusGetBar1P2PDmaInfo_395e98(OBJGPU *pSrcGpu, OBJGPU *pPeerGpu, struct KernelBus *pPeerKernelBus, NvU64 *dma_addr, NvU64 *dma_size) { +static inline NV_STATUS kbusGetBar1P2PDmaInfo_395e98(struct OBJGPU *pSrcGpu, struct OBJGPU *pPeerGpu, struct KernelBus *pPeerKernelBus, NvU64 *dma_addr, NvU64 *dma_size) { return NV_ERR_NOT_SUPPORTED; } -static inline NV_STATUS kbusGetBar1P2PDmaInfo_DISPATCH(OBJGPU *pSrcGpu, OBJGPU *pPeerGpu, struct KernelBus *pPeerKernelBus, NvU64 *dma_addr, NvU64 *dma_size) { +static inline NV_STATUS kbusGetBar1P2PDmaInfo_DISPATCH(struct OBJGPU *pSrcGpu, struct OBJGPU *pPeerGpu, struct KernelBus *pPeerKernelBus, NvU64 *dma_addr, NvU64 *dma_size) { return pPeerKernelBus->__kbusGetBar1P2PDmaInfo__(pSrcGpu, pPeerGpu, pPeerKernelBus, dma_addr, dma_size); } -NV_STATUS kbusStaticMapFbAperture_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU64 offset, NvU64 *pAperOffset, NvU64 *pLength, NvU32 gfid); +NV_STATUS kbusUpdateStaticBar1VAMapping_GH100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU64 offset, NvU64 length, NvBool bRelease); -static inline NV_STATUS kbusStaticMapFbAperture_395e98(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU64 offset, NvU64 *pAperOffset, NvU64 *pLength, NvU32 gfid) { +static inline NV_STATUS kbusUpdateStaticBar1VAMapping_395e98(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU64 offset, NvU64 length, NvBool bRelease) { return NV_ERR_NOT_SUPPORTED; } -static inline NV_STATUS kbusStaticMapFbAperture_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU64 offset, NvU64 *pAperOffset, NvU64 *pLength, NvU32 gfid) { - return pKernelBus->__kbusStaticMapFbAperture__(pGpu, pKernelBus, pMemDesc, offset, pAperOffset, pLength, gfid); +static inline NV_STATUS kbusUpdateStaticBar1VAMapping_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU64 offset, NvU64 length, NvBool bRelease) { + return pKernelBus->__kbusUpdateStaticBar1VAMapping__(pGpu, pKernelBus, pMemDesc, offset, length, bRelease); } -NV_STATUS kbusStaticUnmapFbAperture_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU32 gfid); +NV_STATUS kbusGetStaticFbAperture_GH100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU64 offset, NvU64 *pAperOffset, NvU64 *pLength, NvU32 gfid); -static inline NV_STATUS kbusStaticUnmapFbAperture_395e98(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU32 gfid) { +static inline NV_STATUS kbusGetStaticFbAperture_395e98(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU64 offset, NvU64 *pAperOffset, NvU64 *pLength, NvU32 gfid) { return NV_ERR_NOT_SUPPORTED; } -static inline NV_STATUS kbusStaticUnmapFbAperture_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU32 gfid) { - return pKernelBus->__kbusStaticUnmapFbAperture__(pGpu, pKernelBus, pMemDesc, gfid); +static inline NV_STATUS kbusGetStaticFbAperture_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU64 offset, NvU64 *pAperOffset, NvU64 *pLength, NvU32 gfid) { + return pKernelBus->__kbusGetStaticFbAperture__(pGpu, pKernelBus, pMemDesc, offset, pAperOffset, pLength, gfid); } -NV_STATUS kbusCreateP2PMappingForBar1P2P_GH100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 attributes); +NV_STATUS kbusCreateP2PMappingForBar1P2P_GH100(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 attributes); -static inline NV_STATUS kbusCreateP2PMappingForBar1P2P_46f6a7(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 attributes) { +static inline NV_STATUS kbusCreateP2PMappingForBar1P2P_395e98(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 attributes) { return NV_ERR_NOT_SUPPORTED; } -static inline NV_STATUS kbusCreateP2PMappingForBar1P2P_DISPATCH(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 attributes) { +static inline NV_STATUS kbusCreateP2PMappingForBar1P2P_DISPATCH(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 attributes) { return pKernelBus0->__kbusCreateP2PMappingForBar1P2P__(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes); } -NV_STATUS kbusRemoveP2PMappingForBar1P2P_GH100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 attributes); +NV_STATUS kbusRemoveP2PMappingForBar1P2P_GH100(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 attributes); -static inline NV_STATUS kbusRemoveP2PMappingForBar1P2P_46f6a7(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 attributes) { +static inline NV_STATUS kbusRemoveP2PMappingForBar1P2P_395e98(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 attributes) { return NV_ERR_NOT_SUPPORTED; } -static inline NV_STATUS kbusRemoveP2PMappingForBar1P2P_DISPATCH(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 attributes) { +static inline NV_STATUS kbusRemoveP2PMappingForBar1P2P_DISPATCH(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 attributes) { return pKernelBus0->__kbusRemoveP2PMappingForBar1P2P__(pGpu0, pKernelBus0, pGpu1, pKernelBus1, attributes); } -NvBool kbusHasPcieBar1P2PMapping_GH100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1); +NvBool kbusHasPcieBar1P2PMapping_GH100(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, struct KernelBus *pKernelBus1); -static inline NvBool kbusHasPcieBar1P2PMapping_491d52(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1) { +static inline NvBool kbusHasPcieBar1P2PMapping_bf6dfa(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, struct KernelBus *pKernelBus1) { return ((NvBool)(0 != 0)); } -static inline NvBool kbusHasPcieBar1P2PMapping_DISPATCH(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1) { +static inline NvBool kbusHasPcieBar1P2PMapping_DISPATCH(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, struct KernelBus *pKernelBus1) { return pKernelBus0->__kbusHasPcieBar1P2PMapping__(pGpu0, pKernelBus0, pGpu1, pKernelBus1); } -NvBool kbusIsPcieBar1P2PMappingSupported_GH100(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1); +NvBool kbusIsPcieBar1P2PMappingSupported_GH100(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, struct KernelBus *pKernelBus1); -static inline NvBool kbusIsPcieBar1P2PMappingSupported_491d52(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1) { +static inline NvBool kbusIsPcieBar1P2PMappingSupported_bf6dfa(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, struct KernelBus *pKernelBus1) { return ((NvBool)(0 != 0)); } -static inline NvBool kbusIsPcieBar1P2PMappingSupported_DISPATCH(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, struct KernelBus *pKernelBus1) { +static inline NvBool kbusIsPcieBar1P2PMappingSupported_DISPATCH(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, struct KernelBus *pKernelBus1) { return pKernelBus0->__kbusIsPcieBar1P2PMappingSupported__(pGpu0, pKernelBus0, pGpu1, pKernelBus1); } -void kbusSetupBar1P2PCapability_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus); - -static inline void kbusSetupBar1P2PCapability_b3696a(OBJGPU *pGpu, struct KernelBus *pKernelBus) { - return; -} - -static inline void kbusSetupBar1P2PCapability_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus) { - pKernelBus->__kbusSetupBar1P2PCapability__(pGpu, pKernelBus); -} - -NV_STATUS kbusCheckFlaSupportedAndInit_GA100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 base, NvU64 size); +NV_STATUS kbusCheckFlaSupportedAndInit_GA100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 base, NvU64 size); -static inline NV_STATUS kbusCheckFlaSupportedAndInit_ac1694(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 base, NvU64 size) { +static inline NV_STATUS kbusCheckFlaSupportedAndInit_ac1694(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 base, NvU64 size) { return NV_OK; } -static inline NV_STATUS kbusCheckFlaSupportedAndInit_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 base, NvU64 size) { +static inline NV_STATUS kbusCheckFlaSupportedAndInit_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 base, NvU64 size) { return pKernelBus->__kbusCheckFlaSupportedAndInit__(pGpu, pKernelBus, base, size); } -NV_STATUS kbusDetermineFlaRangeAndAllocate_GA100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 base, NvU64 size); +NV_STATUS kbusDetermineFlaRangeAndAllocate_GA100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 base, NvU64 size); -NV_STATUS kbusDetermineFlaRangeAndAllocate_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 base, NvU64 size); +NV_STATUS kbusDetermineFlaRangeAndAllocate_GH100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 base, NvU64 size); -static inline NV_STATUS kbusDetermineFlaRangeAndAllocate_395e98(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 base, NvU64 size) { +static inline NV_STATUS kbusDetermineFlaRangeAndAllocate_395e98(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 base, NvU64 size) { return NV_ERR_NOT_SUPPORTED; } -static inline NV_STATUS kbusDetermineFlaRangeAndAllocate_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 base, NvU64 size) { +static inline NV_STATUS kbusDetermineFlaRangeAndAllocate_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 base, NvU64 size) { return pKernelBus->__kbusDetermineFlaRangeAndAllocate__(pGpu, pKernelBus, base, size); } -NV_STATUS kbusAllocateFlaVaspace_GA100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 arg0, NvU64 arg1); +NV_STATUS kbusAllocateFlaVaspace_GA100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 arg0, NvU64 arg1); -NV_STATUS kbusAllocateFlaVaspace_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 arg0, NvU64 arg1); +NV_STATUS kbusAllocateFlaVaspace_GH100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 arg0, NvU64 arg1); -static inline NV_STATUS kbusAllocateFlaVaspace_395e98(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 arg0, NvU64 arg1) { +static inline NV_STATUS kbusAllocateFlaVaspace_395e98(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 arg0, NvU64 arg1) { return NV_ERR_NOT_SUPPORTED; } -static inline NV_STATUS kbusAllocateFlaVaspace_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 arg0, NvU64 arg1) { +static inline NV_STATUS kbusAllocateFlaVaspace_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 arg0, NvU64 arg1) { return pKernelBus->__kbusAllocateFlaVaspace__(pGpu, pKernelBus, arg0, arg1); } -NV_STATUS kbusGetFlaRange_GA100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 *arg0, NvU64 *arg1, NvBool arg2); +NV_STATUS kbusGetFlaRange_GA100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 *arg0, NvU64 *arg1, NvBool arg2); -NV_STATUS kbusGetFlaRange_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 *arg0, NvU64 *arg1, NvBool arg2); +NV_STATUS kbusGetFlaRange_GH100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 *arg0, NvU64 *arg1, NvBool arg2); -static inline NV_STATUS kbusGetFlaRange_395e98(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 *arg0, NvU64 *arg1, NvBool arg2) { +static inline NV_STATUS kbusGetFlaRange_395e98(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 *arg0, NvU64 *arg1, NvBool arg2) { return NV_ERR_NOT_SUPPORTED; } -static inline NV_STATUS kbusGetFlaRange_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 *arg0, NvU64 *arg1, NvBool arg2) { +static inline NV_STATUS kbusGetFlaRange_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 *arg0, NvU64 *arg1, NvBool arg2) { return pKernelBus->__kbusGetFlaRange__(pGpu, pKernelBus, arg0, arg1, arg2); } -NV_STATUS kbusAllocateLegacyFlaVaspace_GA100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 arg0, NvU64 arg1); +NV_STATUS kbusAllocateLegacyFlaVaspace_GA100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 arg0, NvU64 arg1); -static inline NV_STATUS kbusAllocateLegacyFlaVaspace_395e98(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 arg0, NvU64 arg1) { +static inline NV_STATUS kbusAllocateLegacyFlaVaspace_395e98(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 arg0, NvU64 arg1) { return NV_ERR_NOT_SUPPORTED; } -static inline NV_STATUS kbusAllocateLegacyFlaVaspace_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 arg0, NvU64 arg1) { +static inline NV_STATUS kbusAllocateLegacyFlaVaspace_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 arg0, NvU64 arg1) { return pKernelBus->__kbusAllocateLegacyFlaVaspace__(pGpu, pKernelBus, arg0, arg1); } -NV_STATUS kbusAllocateHostManagedFlaVaspace_GA100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvHandle arg0, NvHandle arg1, NvHandle arg2, NvHandle arg3, NvU64 arg4, NvU64 arg5, NvU32 arg6); +NV_STATUS kbusAllocateHostManagedFlaVaspace_GA100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvHandle arg0, NvHandle arg1, NvHandle arg2, NvHandle arg3, NvU64 arg4, NvU64 arg5, NvU32 arg6); -static inline NV_STATUS kbusAllocateHostManagedFlaVaspace_395e98(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvHandle arg0, NvHandle arg1, NvHandle arg2, NvHandle arg3, NvU64 arg4, NvU64 arg5, NvU32 arg6) { +static inline NV_STATUS kbusAllocateHostManagedFlaVaspace_395e98(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvHandle arg0, NvHandle arg1, NvHandle arg2, NvHandle arg3, NvU64 arg4, NvU64 arg5, NvU32 arg6) { return NV_ERR_NOT_SUPPORTED; } -static inline NV_STATUS kbusAllocateHostManagedFlaVaspace_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvHandle arg0, NvHandle arg1, NvHandle arg2, NvHandle arg3, NvU64 arg4, NvU64 arg5, NvU32 arg6) { +static inline NV_STATUS kbusAllocateHostManagedFlaVaspace_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvHandle arg0, NvHandle arg1, NvHandle arg2, NvHandle arg3, NvU64 arg4, NvU64 arg5, NvU32 arg6) { return pKernelBus->__kbusAllocateHostManagedFlaVaspace__(pGpu, pKernelBus, arg0, arg1, arg2, arg3, arg4, arg5, arg6); } -void kbusDestroyFla_GA100(OBJGPU *pGpu, struct KernelBus *pKernelBus); +void kbusDestroyFla_GA100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); -void kbusDestroyFla_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus); +void kbusDestroyFla_GH100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); -static inline void kbusDestroyFla_d44104(OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline void kbusDestroyFla_d44104(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { return; } -static inline void kbusDestroyFla_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline void kbusDestroyFla_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { pKernelBus->__kbusDestroyFla__(pGpu, pKernelBus); } -NV_STATUS kbusGetFlaVaspace_GA100(OBJGPU *pGpu, struct KernelBus *pKernelBus, struct OBJVASPACE **arg0); +NV_STATUS kbusGetFlaVaspace_GA100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, struct OBJVASPACE **arg0); -static inline NV_STATUS kbusGetFlaVaspace_395e98(OBJGPU *pGpu, struct KernelBus *pKernelBus, struct OBJVASPACE **arg0) { +static inline NV_STATUS kbusGetFlaVaspace_395e98(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, struct OBJVASPACE **arg0) { return NV_ERR_NOT_SUPPORTED; } -static inline NV_STATUS kbusGetFlaVaspace_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, struct OBJVASPACE **arg0) { +static inline NV_STATUS kbusGetFlaVaspace_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, struct OBJVASPACE **arg0) { return pKernelBus->__kbusGetFlaVaspace__(pGpu, pKernelBus, arg0); } -void kbusDestroyHostManagedFlaVaspace_GA100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0); +void kbusDestroyHostManagedFlaVaspace_GA100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0); -static inline void kbusDestroyHostManagedFlaVaspace_d44104(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0) { +static inline void kbusDestroyHostManagedFlaVaspace_d44104(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0) { return; } -static inline void kbusDestroyHostManagedFlaVaspace_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0) { +static inline void kbusDestroyHostManagedFlaVaspace_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0) { pKernelBus->__kbusDestroyHostManagedFlaVaspace__(pGpu, pKernelBus, arg0); } -NvBool kbusVerifyFlaRange_GA100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 arg0, NvU64 arg1); +NvBool kbusVerifyFlaRange_GA100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 arg0, NvU64 arg1); -static inline NvBool kbusVerifyFlaRange_bf6dfa(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 arg0, NvU64 arg1) { +static inline NvBool kbusVerifyFlaRange_bf6dfa(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 arg0, NvU64 arg1) { return ((NvBool)(0 != 0)); } -static inline NvBool kbusVerifyFlaRange_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 arg0, NvU64 arg1) { +static inline NvBool kbusVerifyFlaRange_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 arg0, NvU64 arg1) { return pKernelBus->__kbusVerifyFlaRange__(pGpu, pKernelBus, arg0, arg1); } -NV_STATUS kbusConstructFlaInstBlk_GA100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0); +NV_STATUS kbusConstructFlaInstBlk_GA100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0); -static inline NV_STATUS kbusConstructFlaInstBlk_395e98(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0) { +static inline NV_STATUS kbusConstructFlaInstBlk_395e98(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0) { return NV_ERR_NOT_SUPPORTED; } -static inline NV_STATUS kbusConstructFlaInstBlk_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0) { +static inline NV_STATUS kbusConstructFlaInstBlk_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 arg0) { return pKernelBus->__kbusConstructFlaInstBlk__(pGpu, pKernelBus, arg0); } -void kbusDestructFlaInstBlk_GA100(OBJGPU *pGpu, struct KernelBus *pKernelBus); +void kbusDestructFlaInstBlk_GA100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); -static inline void kbusDestructFlaInstBlk_d44104(OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline void kbusDestructFlaInstBlk_d44104(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { return; } -static inline void kbusDestructFlaInstBlk_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline void kbusDestructFlaInstBlk_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { pKernelBus->__kbusDestructFlaInstBlk__(pGpu, pKernelBus); } -NV_STATUS kbusValidateFlaBaseAddress_GA100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 flaBaseAddr); +NV_STATUS kbusValidateFlaBaseAddress_GA100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 flaBaseAddr); -static inline NV_STATUS kbusValidateFlaBaseAddress_395e98(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 flaBaseAddr) { +static inline NV_STATUS kbusValidateFlaBaseAddress_395e98(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 flaBaseAddr) { return NV_ERR_NOT_SUPPORTED; } -static inline NV_STATUS kbusValidateFlaBaseAddress_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 flaBaseAddr) { +static inline NV_STATUS kbusValidateFlaBaseAddress_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 flaBaseAddr) { return pKernelBus->__kbusValidateFlaBaseAddress__(pGpu, pKernelBus, flaBaseAddr); } -NV_STATUS kbusSetupUnbindFla_GA100(OBJGPU *pGpu, struct KernelBus *pKernelBus); +NV_STATUS kbusSetupUnbindFla_GA100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); -NV_STATUS kbusSetupUnbindFla_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus); +NV_STATUS kbusSetupUnbindFla_GH100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); -static inline NV_STATUS kbusSetupUnbindFla_46f6a7(OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline NV_STATUS kbusSetupUnbindFla_46f6a7(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { return NV_ERR_NOT_SUPPORTED; } -static inline NV_STATUS kbusSetupUnbindFla_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline NV_STATUS kbusSetupUnbindFla_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { return pKernelBus->__kbusSetupUnbindFla__(pGpu, pKernelBus); } -NV_STATUS kbusSetupBindFla_GA100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); +NV_STATUS kbusSetupBindFla_GA100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); -NV_STATUS kbusSetupBindFla_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); +NV_STATUS kbusSetupBindFla_GH100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); -static inline NV_STATUS kbusSetupBindFla_46f6a7(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { +static inline NV_STATUS kbusSetupBindFla_46f6a7(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { return NV_ERR_NOT_SUPPORTED; } -static inline NV_STATUS kbusSetupBindFla_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { +static inline NV_STATUS kbusSetupBindFla_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { return pKernelBus->__kbusSetupBindFla__(pGpu, pKernelBus, gfid); } -NV_STATUS kbusIsDirectMappingAllowed_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0, NvU32 arg1, NvBool *arg2); +void kbusCacheBAR1ResizeSize_WAR_BUG_3249028_GA100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); + +void kbusCacheBAR1ResizeSize_WAR_BUG_3249028_GH100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); + +static inline void kbusCacheBAR1ResizeSize_WAR_BUG_3249028_d44104(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return; +} + +static inline void kbusCacheBAR1ResizeSize_WAR_BUG_3249028_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { + pKernelBus->__kbusCacheBAR1ResizeSize_WAR_BUG_3249028__(pGpu, pKernelBus); +} + +NV_STATUS kbusRestoreBAR1ResizeSize_WAR_BUG_3249028_GA100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); + +NV_STATUS kbusRestoreBAR1ResizeSize_WAR_BUG_3249028_GH100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); + +static inline NV_STATUS kbusRestoreBAR1ResizeSize_WAR_BUG_3249028_ac1694(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return NV_OK; +} + +static inline NV_STATUS kbusRestoreBAR1ResizeSize_WAR_BUG_3249028_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return pKernelBus->__kbusRestoreBAR1ResizeSize_WAR_BUG_3249028__(pGpu, pKernelBus); +} + +NV_STATUS kbusIsDirectMappingAllowed_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0, NvU32 arg1, NvBool *arg2); -NV_STATUS kbusIsDirectMappingAllowed_GA100(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0, NvU32 arg1, NvBool *arg2); +NV_STATUS kbusIsDirectMappingAllowed_GA100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0, NvU32 arg1, NvBool *arg2); -static inline NV_STATUS kbusIsDirectMappingAllowed_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0, NvU32 arg1, NvBool *arg2) { +static inline NV_STATUS kbusIsDirectMappingAllowed_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0, NvU32 arg1, NvBool *arg2) { return pKernelBus->__kbusIsDirectMappingAllowed__(pGpu, pKernelBus, arg0, arg1, arg2); } -NV_STATUS kbusUseDirectSysmemMap_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *arg0, NvBool *arg1); +NV_STATUS kbusUseDirectSysmemMap_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *arg0, NvBool *arg1); -NV_STATUS kbusUseDirectSysmemMap_GA100(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *arg0, NvBool *arg1); +NV_STATUS kbusUseDirectSysmemMap_GA100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *arg0, NvBool *arg1); -static inline NV_STATUS kbusUseDirectSysmemMap_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *arg0, NvBool *arg1) { +static inline NV_STATUS kbusUseDirectSysmemMap_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *arg0, NvBool *arg1) { return pKernelBus->__kbusUseDirectSysmemMap__(pGpu, pKernelBus, arg0, arg1); } -NV_STATUS kbusWriteBAR0WindowBase_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 base); +NV_STATUS kbusWriteBAR0WindowBase_GH100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 base); -static inline NV_STATUS kbusWriteBAR0WindowBase_395e98(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 base) { +static inline NV_STATUS kbusWriteBAR0WindowBase_395e98(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 base) { return NV_ERR_NOT_SUPPORTED; } -static inline NV_STATUS kbusWriteBAR0WindowBase_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 base) { +static inline NV_STATUS kbusWriteBAR0WindowBase_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 base) { return pKernelBus->__kbusWriteBAR0WindowBase__(pGpu, pKernelBus, base); } -NvU32 kbusReadBAR0WindowBase_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus); +NvU32 kbusReadBAR0WindowBase_GH100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); -static inline NvU32 kbusReadBAR0WindowBase_13cd8d(OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline NvU32 kbusReadBAR0WindowBase_13cd8d(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_PRECOMP(0); return 0; } -static inline NvU32 kbusReadBAR0WindowBase_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline NvU32 kbusReadBAR0WindowBase_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { return pKernelBus->__kbusReadBAR0WindowBase__(pGpu, pKernelBus); } -NvBool kbusValidateBAR0WindowBase_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 base); +NvBool kbusValidateBAR0WindowBase_GH100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 base); -static inline NvBool kbusValidateBAR0WindowBase_ceaee8(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 base) { +static inline NvBool kbusValidateBAR0WindowBase_ceaee8(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 base) { NV_ASSERT_PRECOMP(0); return ((NvBool)(0 != 0)); } -static inline NvBool kbusValidateBAR0WindowBase_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 base) { +static inline NvBool kbusValidateBAR0WindowBase_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 base) { return pKernelBus->__kbusValidateBAR0WindowBase__(pGpu, pKernelBus, base); } -NV_STATUS kbusSetBAR0WindowVidOffset_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 vidOffset); +NV_STATUS kbusSetBAR0WindowVidOffset_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 vidOffset); -NV_STATUS kbusSetBAR0WindowVidOffset_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 vidOffset); +NV_STATUS kbusSetBAR0WindowVidOffset_GH100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 vidOffset); -static inline NV_STATUS kbusSetBAR0WindowVidOffset_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 vidOffset) { +static inline NV_STATUS kbusSetBAR0WindowVidOffset_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 vidOffset) { return pKernelBus->__kbusSetBAR0WindowVidOffset__(pGpu, pKernelBus, vidOffset); } -NvU64 kbusGetBAR0WindowVidOffset_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus); +NvU64 kbusGetBAR0WindowVidOffset_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); -NvU64 kbusGetBAR0WindowVidOffset_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus); +NvU64 kbusGetBAR0WindowVidOffset_GH100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); -static inline NvU64 kbusGetBAR0WindowVidOffset_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline NvU64 kbusGetBAR0WindowVidOffset_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { return pKernelBus->__kbusGetBAR0WindowVidOffset__(pGpu, pKernelBus); } -NV_STATUS kbusVerifyBar2_GM107(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR memDescIn, NvU8 *pCpuPtrIn, NvU64 offset, NvU64 size); +NV_STATUS kbusVerifyBar2_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR memDescIn, NvU8 *pCpuPtrIn, NvU64 offset, NvU64 size); -NV_STATUS kbusVerifyBar2_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR memDescIn, NvU8 *pCpuPtrIn, NvU64 offset, NvU64 size); +NV_STATUS kbusVerifyBar2_GH100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR memDescIn, NvU8 *pCpuPtrIn, NvU64 offset, NvU64 size); -static inline NV_STATUS kbusVerifyBar2_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR memDescIn, NvU8 *pCpuPtrIn, NvU64 offset, NvU64 size) { +static inline NV_STATUS kbusVerifyBar2_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR memDescIn, NvU8 *pCpuPtrIn, NvU64 offset, NvU64 size) { return pKernelBus->__kbusVerifyBar2__(pGpu, pKernelBus, memDescIn, pCpuPtrIn, offset, size); } -static inline NV_STATUS kbusVerifyCoherentLink_56cd7a(OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline NV_STATUS kbusVerifyCoherentLink_56cd7a(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { return NV_OK; } -NV_STATUS kbusVerifyCoherentLink_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus); +NV_STATUS kbusVerifyCoherentLink_GH100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); -static inline NV_STATUS kbusVerifyCoherentLink_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline NV_STATUS kbusVerifyCoherentLink_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { return pKernelBus->__kbusVerifyCoherentLink__(pGpu, pKernelBus); } -NV_STATUS kbusFlushPcieForBar0Doorbell_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus); +NV_STATUS kbusFlushPcieForBar0Doorbell_GH100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); -static inline NV_STATUS kbusFlushPcieForBar0Doorbell_56cd7a(OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline NV_STATUS kbusFlushPcieForBar0Doorbell_56cd7a(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { return NV_OK; } -static inline NV_STATUS kbusFlushPcieForBar0Doorbell_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline NV_STATUS kbusFlushPcieForBar0Doorbell_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { return pKernelBus->__kbusFlushPcieForBar0Doorbell__(pGpu, pKernelBus); } -NV_STATUS kbusCreateCoherentCpuMapping_GH100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 numaOnlineMemorySize, NvBool bFlush); +NV_STATUS kbusCreateCoherentCpuMapping_GH100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 numaOnlineMemorySize, NvBool bFlush); -static inline NV_STATUS kbusCreateCoherentCpuMapping_46f6a7(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 numaOnlineMemorySize, NvBool bFlush) { +static inline NV_STATUS kbusCreateCoherentCpuMapping_46f6a7(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 numaOnlineMemorySize, NvBool bFlush) { return NV_ERR_NOT_SUPPORTED; } -static inline NV_STATUS kbusCreateCoherentCpuMapping_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 numaOnlineMemorySize, NvBool bFlush) { +static inline NV_STATUS kbusCreateCoherentCpuMapping_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 numaOnlineMemorySize, NvBool bFlush) { return pKernelBus->__kbusCreateCoherentCpuMapping__(pGpu, pKernelBus, numaOnlineMemorySize, bFlush); } -NvU8 *kbusMapCoherentCpuMapping_GV100(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0); +NvU8 *kbusMapCoherentCpuMapping_GV100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0); -static inline NvU8 *kbusMapCoherentCpuMapping_9e2234(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0) { +static inline NvU8 *kbusMapCoherentCpuMapping_9e2234(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0) { return ((void *)0); } -static inline NvU8 *kbusMapCoherentCpuMapping_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0) { +static inline NvU8 *kbusMapCoherentCpuMapping_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0) { return pKernelBus->__kbusMapCoherentCpuMapping__(pGpu, pKernelBus, arg0); } -void kbusUnmapCoherentCpuMapping_GV100(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0); +void kbusUnmapCoherentCpuMapping_GV100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0); -static inline void kbusUnmapCoherentCpuMapping_d44104(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0) { +static inline void kbusUnmapCoherentCpuMapping_d44104(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0) { return; } -static inline void kbusUnmapCoherentCpuMapping_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0) { +static inline void kbusUnmapCoherentCpuMapping_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0) { pKernelBus->__kbusUnmapCoherentCpuMapping__(pGpu, pKernelBus, arg0); } -void kbusTeardownCoherentCpuMapping_GV100(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvBool arg0); +void kbusTeardownCoherentCpuMapping_GV100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvBool arg0); -static inline void kbusTeardownCoherentCpuMapping_d44104(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvBool arg0) { +static inline void kbusTeardownCoherentCpuMapping_d44104(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvBool arg0) { return; } -static inline void kbusTeardownCoherentCpuMapping_DISPATCH(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvBool arg0) { +static inline void kbusTeardownCoherentCpuMapping_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvBool arg0) { pKernelBus->__kbusTeardownCoherentCpuMapping__(pGpu, pKernelBus, arg0); } -static inline NV_STATUS kbusStatePostUnload_DISPATCH(POBJGPU pGpu, struct KernelBus *pEngstate, NvU32 arg0) { - return pEngstate->__kbusStatePostUnload__(pGpu, pEngstate, arg0); -} - static inline NV_STATUS kbusStateInitUnlocked_DISPATCH(POBJGPU pGpu, struct KernelBus *pEngstate) { return pEngstate->__kbusStateInitUnlocked__(pGpu, pEngstate); } @@ -2299,14 +2332,6 @@ static inline NvBool kbusIsReadCpuPointerToFlushEnabled(struct KernelBus *pKerne return pKernelBus->bReadCpuPointerToFlush; } -static inline void kbusSetBar1P2pCapable(struct KernelBus *pKernelBus, NvBool val) { - pKernelBus->bBar1P2pCapable = val; -} - -static inline NvBool kbusIsBar1P2PCapable(struct KernelBus *pKernelBus) { - return pKernelBus->bBar1P2pCapable; -} - static inline NvBool kbusIsBarAccessBlocked(struct KernelBus *pKernelBus) { return pKernelBus->bBarAccessBlocked; } @@ -2314,33 +2339,44 @@ static inline NvBool kbusIsBarAccessBlocked(struct KernelBus *pKernelBus) { void kbusDestruct_IMPL(struct KernelBus *pKernelBus); #define __nvoc_kbusDestruct(pKernelBus) kbusDestruct_IMPL(pKernelBus) -void kbusGetDeviceCaps_IMPL(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU8 *pHostCaps, NvBool bCapsInitialized); +void kbusGetDeviceCaps_IMPL(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU8 *pHostCaps, NvBool bCapsInitialized); #ifdef __nvoc_kern_bus_h_disabled -static inline void kbusGetDeviceCaps(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU8 *pHostCaps, NvBool bCapsInitialized) { +static inline void kbusGetDeviceCaps(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU8 *pHostCaps, NvBool bCapsInitialized) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); } #else //__nvoc_kern_bus_h_disabled #define kbusGetDeviceCaps(pGpu, pKernelBus, pHostCaps, bCapsInitialized) kbusGetDeviceCaps_IMPL(pGpu, pKernelBus, pHostCaps, bCapsInitialized) #endif //__nvoc_kern_bus_h_disabled -void kbusDestroyMailbox_IMPL(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, NvU32 peerIdx); +void kbusDestroyMailbox_IMPL(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, NvU32 peerIdx); #ifdef __nvoc_kern_bus_h_disabled -static inline void kbusDestroyMailbox(OBJGPU *pGpu0, struct KernelBus *pKernelBus0, OBJGPU *pGpu1, NvU32 peerIdx) { +static inline void kbusDestroyMailbox(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, NvU32 peerIdx) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); } #else //__nvoc_kern_bus_h_disabled #define kbusDestroyMailbox(pGpu0, pKernelBus0, pGpu1, peerIdx) kbusDestroyMailbox_IMPL(pGpu0, pKernelBus0, pGpu1, peerIdx) #endif //__nvoc_kern_bus_h_disabled -RmPhysAddr kbusSetupPeerBarAccess_IMPL(OBJGPU *pGpu0, OBJGPU *pGpu1, RmPhysAddr arg0, NvU64 arg1, PMEMORY_DESCRIPTOR *arg2); +RmPhysAddr kbusSetupPeerBarAccess_IMPL(struct OBJGPU *pGpu0, struct OBJGPU *pGpu1, RmPhysAddr arg0, NvU64 arg1, PMEMORY_DESCRIPTOR *arg2); #define kbusSetupPeerBarAccess(pGpu0, pGpu1, arg0, arg1, arg2) kbusSetupPeerBarAccess_IMPL(pGpu0, pGpu1, arg0, arg1, arg2) -NV_STATUS kbusSendSysmembar_IMPL(OBJGPU *pGpu, struct KernelBus *pKernelBus); +NvBool kbusIsStaticBar1Enabled_IMPL(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); + +#ifdef __nvoc_kern_bus_h_disabled +static inline NvBool kbusIsStaticBar1Enabled(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { + NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); + return NV_FALSE; +} +#else //__nvoc_kern_bus_h_disabled +#define kbusIsStaticBar1Enabled(pGpu, pKernelBus) kbusIsStaticBar1Enabled_IMPL(pGpu, pKernelBus) +#endif //__nvoc_kern_bus_h_disabled + +NV_STATUS kbusSendSysmembar_IMPL(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusSendSysmembar(OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline NV_STATUS kbusSendSysmembar(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -2348,10 +2384,10 @@ static inline NV_STATUS kbusSendSysmembar(OBJGPU *pGpu, struct KernelBus *pKerne #define kbusSendSysmembar(pGpu, pKernelBus) kbusSendSysmembar_IMPL(pGpu, pKernelBus) #endif //__nvoc_kern_bus_h_disabled -NV_STATUS kbusSendBusInfo_IMPL(OBJGPU *pGpu, struct KernelBus *pKernelBus, NV2080_CTRL_BUS_INFO *pBusInfo); +NV_STATUS kbusSendBusInfo_IMPL(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NV2080_CTRL_BUS_INFO *pBusInfo); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusSendBusInfo(OBJGPU *pGpu, struct KernelBus *pKernelBus, NV2080_CTRL_BUS_INFO *pBusInfo) { +static inline NV_STATUS kbusSendBusInfo(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NV2080_CTRL_BUS_INFO *pBusInfo) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -2383,10 +2419,10 @@ static inline RmPhysAddr kbusGetPciBarOffset(struct KernelBus *pKernelBus, NvU32 #define kbusGetPciBarOffset(pKernelBus, index) kbusGetPciBarOffset_IMPL(pKernelBus, index) #endif //__nvoc_kern_bus_h_disabled -NV_STATUS kbusIsGpuP2pAlive_IMPL(OBJGPU *pGpu, struct KernelBus *pKernelBus); +NV_STATUS kbusIsGpuP2pAlive_IMPL(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusIsGpuP2pAlive(OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline NV_STATUS kbusIsGpuP2pAlive(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -2414,10 +2450,10 @@ static inline void kbusDetermineBar1ApertureLength(struct KernelBus *pKernelBus, #define kbusDetermineBar1ApertureLength(pKernelBus, gfid) kbusDetermineBar1ApertureLength_IMPL(pKernelBus, gfid) #endif //__nvoc_kern_bus_h_disabled -NV_STATUS kbusMapFbApertureByHandle_IMPL(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvHandle hClient, NvHandle hMemory, NvU64 offset, NvU64 size, NvU64 *pBar1Va, struct Device *pDevice); +NV_STATUS kbusMapFbApertureByHandle_IMPL(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvHandle hClient, NvHandle hMemory, NvU64 offset, NvU64 size, NvU64 *pBar1Va, struct Device *pDevice); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusMapFbApertureByHandle(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvHandle hClient, NvHandle hMemory, NvU64 offset, NvU64 size, NvU64 *pBar1Va, struct Device *pDevice) { +static inline NV_STATUS kbusMapFbApertureByHandle(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvHandle hClient, NvHandle hMemory, NvU64 offset, NvU64 size, NvU64 *pBar1Va, struct Device *pDevice) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -2425,10 +2461,10 @@ static inline NV_STATUS kbusMapFbApertureByHandle(OBJGPU *pGpu, struct KernelBus #define kbusMapFbApertureByHandle(pGpu, pKernelBus, hClient, hMemory, offset, size, pBar1Va, pDevice) kbusMapFbApertureByHandle_IMPL(pGpu, pKernelBus, hClient, hMemory, offset, size, pBar1Va, pDevice) #endif //__nvoc_kern_bus_h_disabled -NV_STATUS kbusUnmapFbApertureByHandle_IMPL(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvHandle hClient, NvHandle hMemory, NvU64 bar1Va); +NV_STATUS kbusUnmapFbApertureByHandle_IMPL(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvHandle hClient, NvHandle hMemory, NvU64 bar1Va); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusUnmapFbApertureByHandle(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvHandle hClient, NvHandle hMemory, NvU64 bar1Va) { +static inline NV_STATUS kbusUnmapFbApertureByHandle(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvHandle hClient, NvHandle hMemory, NvU64 bar1Va) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -2436,15 +2472,15 @@ static inline NV_STATUS kbusUnmapFbApertureByHandle(OBJGPU *pGpu, struct KernelB #define kbusUnmapFbApertureByHandle(pGpu, pKernelBus, hClient, hMemory, bar1Va) kbusUnmapFbApertureByHandle_IMPL(pGpu, pKernelBus, hClient, hMemory, bar1Va) #endif //__nvoc_kern_bus_h_disabled -NV_STATUS kbusGetBar1VARangeForClient_IMPL(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvHandle arg0, struct NV_RANGE *arg1); +NV_STATUS kbusGetBar1VARangeForDevice_IMPL(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, struct Device *pDevice, struct NV_RANGE *arg0); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusGetBar1VARangeForClient(OBJGPU *pGpu, struct KernelBus *pKernelBus, NvHandle arg0, struct NV_RANGE *arg1) { +static inline NV_STATUS kbusGetBar1VARangeForDevice(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, struct Device *pDevice, struct NV_RANGE *arg0) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kern_bus_h_disabled -#define kbusGetBar1VARangeForClient(pGpu, pKernelBus, arg0, arg1) kbusGetBar1VARangeForClient_IMPL(pGpu, pKernelBus, arg0, arg1) +#define kbusGetBar1VARangeForDevice(pGpu, pKernelBus, pDevice, arg0) kbusGetBar1VARangeForDevice_IMPL(pGpu, pKernelBus, pDevice, arg0) #endif //__nvoc_kern_bus_h_disabled NvU32 kbusGetFlushAperture_IMPL(struct KernelBus *pKernelBus, NV_ADDRESS_SPACE addrSpace); @@ -2458,10 +2494,10 @@ static inline NvU32 kbusGetFlushAperture(struct KernelBus *pKernelBus, NV_ADDRES #define kbusGetFlushAperture(pKernelBus, addrSpace) kbusGetFlushAperture_IMPL(pKernelBus, addrSpace) #endif //__nvoc_kern_bus_h_disabled -NvU8 *kbusCpuOffsetInBar2WindowGet_IMPL(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc); +NvU8 *kbusCpuOffsetInBar2WindowGet_IMPL(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc); #ifdef __nvoc_kern_bus_h_disabled -static inline NvU8 *kbusCpuOffsetInBar2WindowGet(OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc) { +static inline NvU8 *kbusCpuOffsetInBar2WindowGet(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NULL; } @@ -2472,8 +2508,6 @@ static inline NvU8 *kbusCpuOffsetInBar2WindowGet(OBJGPU *pGpu, struct KernelBus #undef PRIVATE_FIELD -#define KBUS_BAR2_ENABLED(pKernelBus) (!(pKernelBus)->bBar2Tunnelled || (pKernelBus)->bBar2InternalOnly) -#define KBUS_BAR2_TUNNELLED(pKernelBus) ((pKernelBus)->bBar2Tunnelled) #define kbusMapRmAperture_HAL(pGpu, pMemDesc) memdescMapInternal(pGpu, pMemDesc, 0) #define kbusUnmapRmApertureWithFlags_HAL(pGpu, pMemDesc, pCpuPtr, flags) (memdescUnmapInternal(pGpu, pMemDesc, flags), ((void) (*(pCpuPtr) = NULL))) @@ -2490,12 +2524,14 @@ static inline NvU8 *kbusCpuOffsetInBar2WindowGet(OBJGPU *pGpu, struct KernelBus ( pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING) && \ gpuIsSelfHosted(pGpu) ) #define KBUS_CPU_VISIBLE_BAR12_DISABLED(pGpu) \ - ( pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING) && \ - gpuIsSelfHosted(pGpu) ) + ( ( pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING) && \ + gpuIsSelfHosted(pGpu) ) || \ + pGpu->getProperty(pGpu, PDB_PROP_GPU_BAR1_BAR2_DISABLED) ) #endif // KERN_BUS_H #ifdef __cplusplus } // extern "C" #endif + #endif // _G_KERN_BUS_NVOC_H_ diff --git a/src/nvidia/generated/g_kern_disp_nvoc.c b/src/nvidia/generated/g_kern_disp_nvoc.c index 35afa01123..efd6798a82 100644 --- a/src/nvidia/generated/g_kern_disp_nvoc.c +++ b/src/nvidia/generated/g_kern_disp_nvoc.c @@ -99,7 +99,7 @@ static NV_STATUS __nvoc_thunk_KernelDisplay_engstateStateUnload(OBJGPU *pGpu, st return kdispStateUnload(pGpu, (struct KernelDisplay *)(((unsigned char *)pKernelDisplay) - __nvoc_rtti_KernelDisplay_OBJENGSTATE.offset), flags); } -static void __nvoc_thunk_KernelDisplay_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pKernelDisplay, IntrServiceRecord pRecords[167]) { +static void __nvoc_thunk_KernelDisplay_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pKernelDisplay, IntrServiceRecord pRecords[168]) { kdispRegisterIntrService(pGpu, (struct KernelDisplay *)(((unsigned char *)pKernelDisplay) - __nvoc_rtti_KernelDisplay_IntrService.offset), pRecords); } diff --git a/src/nvidia/generated/g_kern_disp_nvoc.h b/src/nvidia/generated/g_kern_disp_nvoc.h index 97269ed133..86db29748c 100644 --- a/src/nvidia/generated/g_kern_disp_nvoc.h +++ b/src/nvidia/generated/g_kern_disp_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -136,10 +136,10 @@ struct KernelDisplay { NvBool PDB_PROP_KDISP_BUG_2089053_SERIALIZE_AGGRESSIVE_VBLANKS_ONLY_ON_HMD_ACTIVE; NvBool PDB_PROP_KDISP_IN_AWAKEN_INTR; struct DisplayInstanceMemory *pInst; - struct KernelHead *pKernelHead[4]; + struct KernelHead *pKernelHead[8]; const KernelDisplayStaticInfo *pStaticInfo; NvBool bWarPurgeSatellitesOnCoreFree; - struct RgLineCallback *rgLineCallbackPerHead[4][2]; + struct RgLineCallback *rgLineCallbackPerHead[8][2]; NvU32 isrVblankHeads; NvBool bExtdevIntrSupported; NvU32 numHeads; @@ -233,6 +233,19 @@ NV_STATUS __nvoc_objCreate_KernelDisplay(KernelDisplay**, Dynamic*, NvU32); #define kdispClearInterrupt(pGpu, pIntrService, pParams) kdispClearInterrupt_DISPATCH(pGpu, pIntrService, pParams) #define kdispStatePostLoad(pGpu, pEngstate, arg0) kdispStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) #define kdispIsPresent(pGpu, pEngstate) kdispIsPresent_DISPATCH(pGpu, pEngstate) +void kdispServiceVblank_KERNEL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2); + + +#ifdef __nvoc_kern_disp_h_disabled +static inline void kdispServiceVblank(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2) { + NV_ASSERT_FAILED_PRECOMP("KernelDisplay was disabled!"); +} +#else //__nvoc_kern_disp_h_disabled +#define kdispServiceVblank(pGpu, pKernelDisplay, arg0, arg1, arg2) kdispServiceVblank_KERNEL(pGpu, pKernelDisplay, arg0, arg1, arg2) +#endif //__nvoc_kern_disp_h_disabled + +#define kdispServiceVblank_HAL(pGpu, pKernelDisplay, arg0, arg1, arg2) kdispServiceVblank(pGpu, pKernelDisplay, arg0, arg1, arg2) + NV_STATUS kdispConstructInstMem_IMPL(struct KernelDisplay *pKernelDisplay); @@ -408,19 +421,6 @@ static inline void kdispInvokeRgLineCallback(struct KernelDisplay *pKernelDispla #define kdispInvokeRgLineCallback_HAL(pKernelDisplay, head, rgIntrLine, bIsIrqlIsr) kdispInvokeRgLineCallback(pKernelDisplay, head, rgIntrLine, bIsIrqlIsr) -void kdispServiceVblank_KERNEL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2); - - -#ifdef __nvoc_kern_disp_h_disabled -static inline void kdispServiceVblank(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2) { - NV_ASSERT_FAILED_PRECOMP("KernelDisplay was disabled!"); -} -#else //__nvoc_kern_disp_h_disabled -#define kdispServiceVblank(pGpu, pKernelDisplay, arg0, arg1, arg2) kdispServiceVblank_KERNEL(pGpu, pKernelDisplay, arg0, arg1, arg2) -#endif //__nvoc_kern_disp_h_disabled - -#define kdispServiceVblank_HAL(pGpu, pKernelDisplay, arg0, arg1, arg2) kdispServiceVblank(pGpu, pKernelDisplay, arg0, arg1, arg2) - NvU32 kdispReadPendingVblank_IMPL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, struct THREAD_STATE_NODE *arg0); @@ -604,9 +604,9 @@ static inline NV_STATUS kdispStateUnload_DISPATCH(OBJGPU *pGpu, struct KernelDis return pKernelDisplay->__kdispStateUnload__(pGpu, pKernelDisplay, flags); } -void kdispRegisterIntrService_IMPL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, IntrServiceRecord pRecords[167]); +void kdispRegisterIntrService_IMPL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, IntrServiceRecord pRecords[168]); -static inline void kdispRegisterIntrService_DISPATCH(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, IntrServiceRecord pRecords[167]) { +static inline void kdispRegisterIntrService_DISPATCH(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, IntrServiceRecord pRecords[168]) { pKernelDisplay->__kdispRegisterIntrService__(pGpu, pKernelDisplay, pRecords); } @@ -921,4 +921,5 @@ kdispGetDispCommonHandle(struct KernelDisplay *pKernelDisplay) #ifdef __cplusplus } // extern "C" #endif + #endif // _G_KERN_DISP_NVOC_H_ diff --git a/src/nvidia/generated/g_kern_fsp_nvoc.h b/src/nvidia/generated/g_kern_fsp_nvoc.h index 3d7d371bf0..2c72b33cef 100644 --- a/src/nvidia/generated/g_kern_fsp_nvoc.h +++ b/src/nvidia/generated/g_kern_fsp_nvoc.h @@ -646,4 +646,5 @@ static inline NvBool kfspIsPresent_DISPATCH(POBJGPU pGpu, struct KernelFsp *pEng #ifdef __cplusplus } // extern "C" #endif + #endif // _G_KERN_FSP_NVOC_H_ diff --git a/src/nvidia/generated/g_kern_gmmu_nvoc.c b/src/nvidia/generated/g_kern_gmmu_nvoc.c index 6e905e2bb2..cb124cf357 100644 --- a/src/nvidia/generated/g_kern_gmmu_nvoc.c +++ b/src/nvidia/generated/g_kern_gmmu_nvoc.c @@ -95,7 +95,7 @@ static void __nvoc_thunk_KernelGmmu_engstateStateDestroy(OBJGPU *pGpu, struct OB kgmmuStateDestroy(pGpu, (struct KernelGmmu *)(((unsigned char *)pKernelGmmu) - __nvoc_rtti_KernelGmmu_OBJENGSTATE.offset)); } -static void __nvoc_thunk_KernelGmmu_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pKernelGmmu, IntrServiceRecord arg0[167]) { +static void __nvoc_thunk_KernelGmmu_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pKernelGmmu, IntrServiceRecord arg0[168]) { kgmmuRegisterIntrService(pGpu, (struct KernelGmmu *)(((unsigned char *)pKernelGmmu) - __nvoc_rtti_KernelGmmu_IntrService.offset), arg0); } diff --git a/src/nvidia/generated/g_kern_gmmu_nvoc.h b/src/nvidia/generated/g_kern_gmmu_nvoc.h index ecf9ea11d4..e5f92b7e09 100644 --- a/src/nvidia/generated/g_kern_gmmu_nvoc.h +++ b/src/nvidia/generated/g_kern_gmmu_nvoc.h @@ -396,6 +396,7 @@ struct KernelGmmu { NvBool PRIVATE_FIELD(bBug2720120WarEnabled); NvBool PRIVATE_FIELD(bVaspaceInteropSupported); }; + struct KernelGmmu_PRIVATE { const struct NVOC_RTTI *__nvoc_rtti; struct OBJENGSTATE __nvoc_base_OBJENGSTATE; @@ -1086,9 +1087,9 @@ static inline void kgmmuStateDestroy_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *p pKernelGmmu->__kgmmuStateDestroy__(pGpu, pKernelGmmu); } -void kgmmuRegisterIntrService_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, IntrServiceRecord arg0[167]); +void kgmmuRegisterIntrService_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, IntrServiceRecord arg0[168]); -static inline void kgmmuRegisterIntrService_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, IntrServiceRecord arg0[167]) { +static inline void kgmmuRegisterIntrService_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, IntrServiceRecord arg0[168]) { pKernelGmmu->__kgmmuRegisterIntrService__(pGpu, pKernelGmmu, arg0); } @@ -1843,4 +1844,5 @@ void gmmuMemDescCacheFree(GVAS_GPU_STATE *pGpuState); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_KERN_GMMU_NVOC_H_ diff --git a/src/nvidia/generated/g_kern_mem_sys_nvoc.c b/src/nvidia/generated/g_kern_mem_sys_nvoc.c index 97b700f450..40502648fd 100644 --- a/src/nvidia/generated/g_kern_mem_sys_nvoc.c +++ b/src/nvidia/generated/g_kern_mem_sys_nvoc.c @@ -425,6 +425,17 @@ static void __nvoc_init_funcTable_KernelMemorySystem_1(KernelMemorySystem *pThis pThis->__kmemsysRemoveAllAtsPeers__ = &kmemsysRemoveAllAtsPeers_GV100; } + // Hal function -- kmemsysAssertFbAckTimeoutPending + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kmemsysAssertFbAckTimeoutPending__ = &kmemsysAssertFbAckTimeoutPending_GH100; + } + // default + else + { + pThis->__kmemsysAssertFbAckTimeoutPending__ = &kmemsysAssertFbAckTimeoutPending_491d52; + } + // Hal function -- kmemsysCheckEccCounts if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { diff --git a/src/nvidia/generated/g_kern_mem_sys_nvoc.h b/src/nvidia/generated/g_kern_mem_sys_nvoc.h index f5cdb3d468..1ee2484bce 100644 --- a/src/nvidia/generated/g_kern_mem_sys_nvoc.h +++ b/src/nvidia/generated/g_kern_mem_sys_nvoc.h @@ -222,6 +222,7 @@ struct KernelMemorySystem { void (*__kmemsysNumaRemoveAllMemory__)(OBJGPU *, struct KernelMemorySystem *); NV_STATUS (*__kmemsysSetupAllAtsPeers__)(OBJGPU *, struct KernelMemorySystem *); void (*__kmemsysRemoveAllAtsPeers__)(OBJGPU *, struct KernelMemorySystem *); + NvBool (*__kmemsysAssertFbAckTimeoutPending__)(OBJGPU *, struct KernelMemorySystem *); void (*__kmemsysCheckEccCounts__)(OBJGPU *, struct KernelMemorySystem *); NV_STATUS (*__kmemsysClearEccCounts__)(OBJGPU *, struct KernelMemorySystem *); NV_STATUS (*__kmemsysStateLoad__)(POBJGPU, struct KernelMemorySystem *, NvU32); @@ -325,6 +326,8 @@ NV_STATUS __nvoc_objCreate_KernelMemorySystem(KernelMemorySystem**, Dynamic*, Nv #define kmemsysSetupAllAtsPeers_HAL(pGpu, pKernelMemorySystem) kmemsysSetupAllAtsPeers_DISPATCH(pGpu, pKernelMemorySystem) #define kmemsysRemoveAllAtsPeers(pGpu, pKernelMemorySystem) kmemsysRemoveAllAtsPeers_DISPATCH(pGpu, pKernelMemorySystem) #define kmemsysRemoveAllAtsPeers_HAL(pGpu, pKernelMemorySystem) kmemsysRemoveAllAtsPeers_DISPATCH(pGpu, pKernelMemorySystem) +#define kmemsysAssertFbAckTimeoutPending(pGpu, pKernelMemorySystem) kmemsysAssertFbAckTimeoutPending_DISPATCH(pGpu, pKernelMemorySystem) +#define kmemsysAssertFbAckTimeoutPending_HAL(pGpu, pKernelMemorySystem) kmemsysAssertFbAckTimeoutPending_DISPATCH(pGpu, pKernelMemorySystem) #define kmemsysCheckEccCounts(pGpu, pKernelMemorySystem) kmemsysCheckEccCounts_DISPATCH(pGpu, pKernelMemorySystem) #define kmemsysCheckEccCounts_HAL(pGpu, pKernelMemorySystem) kmemsysCheckEccCounts_DISPATCH(pGpu, pKernelMemorySystem) #define kmemsysClearEccCounts(pGpu, pKernelMemorySystem) kmemsysClearEccCounts_DISPATCH(pGpu, pKernelMemorySystem) @@ -739,6 +742,16 @@ static inline void kmemsysRemoveAllAtsPeers_DISPATCH(OBJGPU *pGpu, struct Kernel pKernelMemorySystem->__kmemsysRemoveAllAtsPeers__(pGpu, pKernelMemorySystem); } +NvBool kmemsysAssertFbAckTimeoutPending_GH100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); + +static inline NvBool kmemsysAssertFbAckTimeoutPending_491d52(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { + return ((NvBool)(0 != 0)); +} + +static inline NvBool kmemsysAssertFbAckTimeoutPending_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { + return pKernelMemorySystem->__kmemsysAssertFbAckTimeoutPending__(pGpu, pKernelMemorySystem); +} + void kmemsysCheckEccCounts_GH100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); static inline void kmemsysCheckEccCounts_b3696a(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { @@ -930,4 +943,5 @@ static inline NV_STATUS kmemsysInitMIGGPUInstanceMemConfigForSwizzId(OBJGPU *arg #ifdef __cplusplus } // extern "C" #endif + #endif // _G_KERN_MEM_SYS_NVOC_H_ diff --git a/src/nvidia/generated/g_kern_perf_nvoc.h b/src/nvidia/generated/g_kern_perf_nvoc.h index 9fc6eccf27..84ab453c5e 100644 --- a/src/nvidia/generated/g_kern_perf_nvoc.h +++ b/src/nvidia/generated/g_kern_perf_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -228,17 +228,6 @@ static inline NvBool kperfIsPresent_DISPATCH(POBJGPU pGpu, struct KernelPerf *pE return pEngstate->__kperfIsPresent__(pGpu, pEngstate); } -NV_STATUS kperfBoostStateInit_IMPL(struct OBJGPU *pGpu, struct KernelPerf *pKernelPerf); - -#ifdef __nvoc_kern_perf_h_disabled -static inline NV_STATUS kperfBoostStateInit(struct OBJGPU *pGpu, struct KernelPerf *pKernelPerf) { - NV_ASSERT_FAILED_PRECOMP("KernelPerf was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kern_perf_h_disabled -#define kperfBoostStateInit(pGpu, pKernelPerf) kperfBoostStateInit_IMPL(pGpu, pKernelPerf) -#endif //__nvoc_kern_perf_h_disabled - NV_STATUS kperfGpuBoostSyncActivate_IMPL(struct OBJGPU *pGpu, struct KernelPerf *pKernelPerf, NvBool bActivate); #ifdef __nvoc_kern_perf_h_disabled @@ -284,4 +273,5 @@ static inline NV_STATUS kperfReentrancy(struct OBJGPU *pGpu, struct KernelPerf * #ifdef __cplusplus } // extern "C" #endif + #endif // _G_KERN_PERF_NVOC_H_ diff --git a/src/nvidia/generated/g_kern_perfbuffer_nvoc.h b/src/nvidia/generated/g_kern_perfbuffer_nvoc.h index 61d17ac091..57cd134b73 100644 --- a/src/nvidia/generated/g_kern_perfbuffer_nvoc.h +++ b/src/nvidia/generated/g_kern_perfbuffer_nvoc.h @@ -279,4 +279,5 @@ static inline NV_STATUS perfbufferPrivilegeCheck(struct PerfBuffer *pPerfBuffer) #ifdef __cplusplus } // extern "C" #endif + #endif // _G_KERN_PERFBUFFER_NVOC_H_ diff --git a/src/nvidia/generated/g_kern_pmu_nvoc.c b/src/nvidia/generated/g_kern_pmu_nvoc.c index d992278c48..da2eacd063 100644 --- a/src/nvidia/generated/g_kern_pmu_nvoc.c +++ b/src/nvidia/generated/g_kern_pmu_nvoc.c @@ -70,6 +70,10 @@ static NV_STATUS __nvoc_thunk_KernelPmu_engstateConstructEngine(struct OBJGPU *p return kpmuConstructEngine(pGpu, (struct KernelPmu *)(((unsigned char *)pKernelPmu) - __nvoc_rtti_KernelPmu_OBJENGSTATE.offset), engDesc); } +static void __nvoc_thunk_KernelPmu_engstateStateDestroy(struct OBJGPU *pGpu, struct OBJENGSTATE *pKernelPmu) { + kpmuStateDestroy(pGpu, (struct KernelPmu *)(((unsigned char *)pKernelPmu) - __nvoc_rtti_KernelPmu_OBJENGSTATE.offset)); +} + static NV_STATUS __nvoc_thunk_KernelPmu_engstateStateInitLocked(struct OBJGPU *pGpu, struct OBJENGSTATE *pKernelPmu) { return kpmuStateInitLocked(pGpu, (struct KernelPmu *)(((unsigned char *)pKernelPmu) - __nvoc_rtti_KernelPmu_OBJENGSTATE.offset)); } @@ -90,10 +94,6 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_kpmuStatePostUnload(POBJGPU pGpu, stru return engstateStatePostUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPmu_OBJENGSTATE.offset), arg0); } -static void __nvoc_thunk_OBJENGSTATE_kpmuStateDestroy(POBJGPU pGpu, struct KernelPmu *pEngstate) { - engstateStateDestroy(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPmu_OBJENGSTATE.offset)); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kpmuStatePreUnload(POBJGPU pGpu, struct KernelPmu *pEngstate, NvU32 arg0) { return engstateStatePreUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelPmu_OBJENGSTATE.offset), arg0); } @@ -158,10 +158,14 @@ static void __nvoc_init_funcTable_KernelPmu_1(KernelPmu *pThis) { pThis->__kpmuConstructEngine__ = &kpmuConstructEngine_IMPL; + pThis->__kpmuStateDestroy__ = &kpmuStateDestroy_IMPL; + pThis->__kpmuStateInitLocked__ = &kpmuStateInitLocked_IMPL; pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelPmu_engstateConstructEngine; + pThis->__nvoc_base_OBJENGSTATE.__engstateStateDestroy__ = &__nvoc_thunk_KernelPmu_engstateStateDestroy; + pThis->__nvoc_base_OBJENGSTATE.__engstateStateInitLocked__ = &__nvoc_thunk_KernelPmu_engstateStateInitLocked; pThis->__kpmuStateLoad__ = &__nvoc_thunk_OBJENGSTATE_kpmuStateLoad; @@ -172,8 +176,6 @@ static void __nvoc_init_funcTable_KernelPmu_1(KernelPmu *pThis) { pThis->__kpmuStatePostUnload__ = &__nvoc_thunk_OBJENGSTATE_kpmuStatePostUnload; - pThis->__kpmuStateDestroy__ = &__nvoc_thunk_OBJENGSTATE_kpmuStateDestroy; - pThis->__kpmuStatePreUnload__ = &__nvoc_thunk_OBJENGSTATE_kpmuStatePreUnload; pThis->__kpmuStateInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kpmuStateInitUnlocked; diff --git a/src/nvidia/generated/g_kern_pmu_nvoc.h b/src/nvidia/generated/g_kern_pmu_nvoc.h index 706c74179e..d0de5c0e91 100644 --- a/src/nvidia/generated/g_kern_pmu_nvoc.h +++ b/src/nvidia/generated/g_kern_pmu_nvoc.h @@ -65,12 +65,12 @@ struct KernelPmu { struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; struct KernelPmu *__nvoc_pbase_KernelPmu; NV_STATUS (*__kpmuConstructEngine__)(struct OBJGPU *, struct KernelPmu *, ENGDESCRIPTOR); + void (*__kpmuStateDestroy__)(struct OBJGPU *, struct KernelPmu *); NV_STATUS (*__kpmuStateInitLocked__)(struct OBJGPU *, struct KernelPmu *); NV_STATUS (*__kpmuStateLoad__)(POBJGPU, struct KernelPmu *, NvU32); NV_STATUS (*__kpmuStateUnload__)(POBJGPU, struct KernelPmu *, NvU32); NV_STATUS (*__kpmuStatePreLoad__)(POBJGPU, struct KernelPmu *, NvU32); NV_STATUS (*__kpmuStatePostUnload__)(POBJGPU, struct KernelPmu *, NvU32); - void (*__kpmuStateDestroy__)(POBJGPU, struct KernelPmu *); NV_STATUS (*__kpmuStatePreUnload__)(POBJGPU, struct KernelPmu *, NvU32); NV_STATUS (*__kpmuStateInitUnlocked__)(POBJGPU, struct KernelPmu *); void (*__kpmuInitMissing__)(POBJGPU, struct KernelPmu *); @@ -78,6 +78,7 @@ struct KernelPmu { NV_STATUS (*__kpmuStatePreInitUnlocked__)(POBJGPU, struct KernelPmu *); NV_STATUS (*__kpmuStatePostLoad__)(POBJGPU, struct KernelPmu *, NvU32); NvBool (*__kpmuIsPresent__)(POBJGPU, struct KernelPmu *); + MEMORY_DESCRIPTOR *pPmuRsvdMemdesc; LIBOS_LOG_DECODE logDecode; NvU32 printBufSize; NvU8 *pPrintBuf; @@ -116,12 +117,12 @@ NV_STATUS __nvoc_objCreate_KernelPmu(KernelPmu**, Dynamic*, NvU32); __nvoc_objCreate_KernelPmu((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) #define kpmuConstructEngine(pGpu, pKernelPmu, engDesc) kpmuConstructEngine_DISPATCH(pGpu, pKernelPmu, engDesc) +#define kpmuStateDestroy(pGpu, pKernelPmu) kpmuStateDestroy_DISPATCH(pGpu, pKernelPmu) #define kpmuStateInitLocked(pGpu, pKernelPmu) kpmuStateInitLocked_DISPATCH(pGpu, pKernelPmu) #define kpmuStateLoad(pGpu, pEngstate, arg0) kpmuStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define kpmuStateUnload(pGpu, pEngstate, arg0) kpmuStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define kpmuStatePreLoad(pGpu, pEngstate, arg0) kpmuStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define kpmuStatePostUnload(pGpu, pEngstate, arg0) kpmuStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) -#define kpmuStateDestroy(pGpu, pEngstate) kpmuStateDestroy_DISPATCH(pGpu, pEngstate) #define kpmuStatePreUnload(pGpu, pEngstate, arg0) kpmuStatePreUnload_DISPATCH(pGpu, pEngstate, arg0) #define kpmuStateInitUnlocked(pGpu, pEngstate) kpmuStateInitUnlocked_DISPATCH(pGpu, pEngstate) #define kpmuInitMissing(pGpu, pEngstate) kpmuInitMissing_DISPATCH(pGpu, pEngstate) @@ -135,6 +136,12 @@ static inline NV_STATUS kpmuConstructEngine_DISPATCH(struct OBJGPU *pGpu, struct return pKernelPmu->__kpmuConstructEngine__(pGpu, pKernelPmu, engDesc); } +void kpmuStateDestroy_IMPL(struct OBJGPU *pGpu, struct KernelPmu *pKernelPmu); + +static inline void kpmuStateDestroy_DISPATCH(struct OBJGPU *pGpu, struct KernelPmu *pKernelPmu) { + pKernelPmu->__kpmuStateDestroy__(pGpu, pKernelPmu); +} + NV_STATUS kpmuStateInitLocked_IMPL(struct OBJGPU *pGpu, struct KernelPmu *pKernelPmu); static inline NV_STATUS kpmuStateInitLocked_DISPATCH(struct OBJGPU *pGpu, struct KernelPmu *pKernelPmu) { @@ -157,10 +164,6 @@ static inline NV_STATUS kpmuStatePostUnload_DISPATCH(POBJGPU pGpu, struct Kernel return pEngstate->__kpmuStatePostUnload__(pGpu, pEngstate, arg0); } -static inline void kpmuStateDestroy_DISPATCH(POBJGPU pGpu, struct KernelPmu *pEngstate) { - pEngstate->__kpmuStateDestroy__(pGpu, pEngstate); -} - static inline NV_STATUS kpmuStatePreUnload_DISPATCH(POBJGPU pGpu, struct KernelPmu *pEngstate, NvU32 arg0) { return pEngstate->__kpmuStatePreUnload__(pGpu, pEngstate, arg0); } @@ -192,6 +195,28 @@ static inline NvBool kpmuIsPresent_DISPATCH(POBJGPU pGpu, struct KernelPmu *pEng void kpmuDestruct_IMPL(struct KernelPmu *pKernelPmu); #define __nvoc_kpmuDestruct(pKernelPmu) kpmuDestruct_IMPL(pKernelPmu) +NvU32 kpmuReservedMemorySizeGet_IMPL(struct KernelPmu *pKernelPmu); + +#ifdef __nvoc_kern_pmu_h_disabled +static inline NvU32 kpmuReservedMemorySizeGet(struct KernelPmu *pKernelPmu) { + NV_ASSERT_FAILED_PRECOMP("KernelPmu was disabled!"); + return 0; +} +#else //__nvoc_kern_pmu_h_disabled +#define kpmuReservedMemorySizeGet(pKernelPmu) kpmuReservedMemorySizeGet_IMPL(pKernelPmu) +#endif //__nvoc_kern_pmu_h_disabled + +NvU64 kpmuReservedMemoryOffsetGet_IMPL(struct OBJGPU *pGpu, struct KernelPmu *pKernelPmu); + +#ifdef __nvoc_kern_pmu_h_disabled +static inline NvU64 kpmuReservedMemoryOffsetGet(struct OBJGPU *pGpu, struct KernelPmu *pKernelPmu) { + NV_ASSERT_FAILED_PRECOMP("KernelPmu was disabled!"); + return 0; +} +#else //__nvoc_kern_pmu_h_disabled +#define kpmuReservedMemoryOffsetGet(pGpu, pKernelPmu) kpmuReservedMemoryOffsetGet_IMPL(pGpu, pKernelPmu) +#endif //__nvoc_kern_pmu_h_disabled + NV_STATUS kpmuInitLibosLoggingStructures_IMPL(struct OBJGPU *pGpu, struct KernelPmu *pKernelPmu); #ifdef __nvoc_kern_pmu_h_disabled @@ -231,4 +256,5 @@ static inline void kpmuLogBuf(struct OBJGPU *pGpu, struct KernelPmu *pKernelPmu, #ifdef __cplusplus } // extern "C" #endif + #endif // _G_KERN_PMU_NVOC_H_ diff --git a/src/nvidia/generated/g_kernel_bif_nvoc.c b/src/nvidia/generated/g_kernel_bif_nvoc.c index d0aa00e1e3..b383be4a3a 100644 --- a/src/nvidia/generated/g_kernel_bif_nvoc.c +++ b/src/nvidia/generated/g_kernel_bif_nvoc.c @@ -130,6 +130,7 @@ const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelBif = void __nvoc_dtor_OBJENGSTATE(OBJENGSTATE*); void __nvoc_dtor_KernelBif(KernelBif *pThis) { + __nvoc_kbifDestruct(pThis); __nvoc_dtor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); PORT_UNREFERENCED_VARIABLE(pThis); } @@ -442,6 +443,26 @@ static void __nvoc_init_funcTable_KernelBif_1(KernelBif *pThis, RmHalspecOwner * pThis->__kbifEnablePcieAtomics__ = &kbifEnablePcieAtomics_b3696a; } + // Hal function -- kbifInitXveRegMap + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__kbifInitXveRegMap__ = &kbifInitXveRegMap_TU102; + } + else + { + pThis->__kbifInitXveRegMap__ = &kbifInitXveRegMap_GA102; + } + + // Hal function -- kbifGetMSIXTableVectorControlSize + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifGetMSIXTableVectorControlSize__ = &kbifGetMSIXTableVectorControlSize_GH100; + } + else + { + pThis->__kbifGetMSIXTableVectorControlSize__ = &kbifGetMSIXTableVectorControlSize_TU102; + } + // Hal function -- kbifGetPciConfigSpacePriMirror if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { @@ -473,6 +494,61 @@ static void __nvoc_init_funcTable_KernelBif_1(KernelBif *pThis, RmHalspecOwner * pThis->__kbifPreOsGlobalErotGrantRequest__ = &kbifPreOsGlobalErotGrantRequest_56cd7a; } + // Hal function -- kbifStopSysMemRequests + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifStopSysMemRequests__ = &kbifStopSysMemRequests_GH100; + } + else + { + pThis->__kbifStopSysMemRequests__ = &kbifStopSysMemRequests_GM107; + } + + // Hal function -- kbifWaitForTransactionsComplete + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifWaitForTransactionsComplete__ = &kbifWaitForTransactionsComplete_GH100; + } + else + { + pThis->__kbifWaitForTransactionsComplete__ = &kbifWaitForTransactionsComplete_TU102; + } + + // Hal function -- kbifTriggerFlr + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifTriggerFlr__ = &kbifTriggerFlr_GH100; + } + else + { + pThis->__kbifTriggerFlr__ = &kbifTriggerFlr_TU102; + } + + // Hal function -- kbifCacheFlrSupport + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifCacheFlrSupport__ = &kbifCacheFlrSupport_GH100; + } + else + { + pThis->__kbifCacheFlrSupport__ = &kbifCacheFlrSupport_TU102; + } + + // Hal function -- kbifCache64bBar0Support + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifCache64bBar0Support__ = &kbifCache64bBar0Support_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->__kbifCache64bBar0Support__ = &kbifCache64bBar0Support_GA100; + } + // default + else + { + pThis->__kbifCache64bBar0Support__ = &kbifCache64bBar0Support_b3696a; + } + // Hal function -- kbifCacheVFInfo if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { @@ -483,6 +559,61 @@ static void __nvoc_init_funcTable_KernelBif_1(KernelBif *pThis, RmHalspecOwner * pThis->__kbifCacheVFInfo__ = &kbifCacheVFInfo_TU102; } + // Hal function -- kbifRestoreBar0 + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__kbifRestoreBar0__ = &kbifRestoreBar0_GM107; + } + else + { + pThis->__kbifRestoreBar0__ = &kbifRestoreBar0_GA100; + } + + // Hal function -- kbifAnyBarsAreValid + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__kbifAnyBarsAreValid__ = &kbifAnyBarsAreValid_GM107; + } + else + { + pThis->__kbifAnyBarsAreValid__ = &kbifAnyBarsAreValid_GA100; + } + + // Hal function -- kbifRestoreBarsAndCommand + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifRestoreBarsAndCommand__ = &kbifRestoreBarsAndCommand_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__kbifRestoreBarsAndCommand__ = &kbifRestoreBarsAndCommand_GM107; + } + else + { + pThis->__kbifRestoreBarsAndCommand__ = &kbifRestoreBarsAndCommand_GA100; + } + + // Hal function -- kbifStoreBarRegOffsets + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->__kbifStoreBarRegOffsets__ = &kbifStoreBarRegOffsets_GA100; + } + // default + else + { + pThis->__kbifStoreBarRegOffsets__ = &kbifStoreBarRegOffsets_b3696a; + } + + // Hal function -- kbifInit + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifInit__ = &kbifInit_GH100; + } + else + { + pThis->__kbifInit__ = &kbifInit_GM107; + } + pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelBif_engstateConstructEngine; pThis->__nvoc_base_OBJENGSTATE.__engstateStateInitLocked__ = &__nvoc_thunk_KernelBif_engstateStateInitLocked; diff --git a/src/nvidia/generated/g_kernel_bif_nvoc.h b/src/nvidia/generated/g_kernel_bif_nvoc.h index fd6a9aa148..0a1d2697c4 100644 --- a/src/nvidia/generated/g_kernel_bif_nvoc.h +++ b/src/nvidia/generated/g_kernel_bif_nvoc.h @@ -64,6 +64,10 @@ extern "C" { #define kbifIsSnoopDmaCapable(pGpu, pKernelBif) ((REF_VAL(BIF_DMA_CAPS_SNOOP, \ kbifGetDmaCaps(pGpu, pKernelBif)))) +// Number of BAR entries: BAR0_LO, BAR0_HI, BAR1_LO, BAR1_HI, BAR2_LO, BAR2_HI and BAR3 +#define KBIF_NUM_BAR_OFFSET_ENTRIES 0x7 +// Indicates a non existent BAR offset +#define KBIF_INVALID_BAR_REG_OFFSET 0xFFFF // XVE bus options typedef enum BUS_OPTIONS @@ -74,6 +78,44 @@ typedef enum BUS_OPTIONS } BUS_OPTIONS; +// +// References to save/restore PCIe Config space using registry_map +// +typedef struct KBIF_XVE_REGMAP_REF +{ + // XVE Valid register map array + const NvU32 *xveRegMapValid; + + // XVE Writable register map array + const NvU32 *xveRegMapWrite; + + // XVE Valid register map array count + NvU16 numXveRegMapValid; + + // XVE Writable register map array count + NvU16 numXveRegMapWrite; + + // PCIe function number + NvU8 nFunc; + + // Buffer to store boot PCIe config space + NvU32 *bufBootConfigSpace; + + // Buffer to store boot PCIe MSIX table (GH100+) + NvU32 *bufMsixTable; + +} KBIF_XVE_REGMAP_REF, *PKBIF_XVE_REGMAP_REF; + +typedef struct +{ + // Used to save/restore config space after a hot reset + NvU32 gpuBootConfigSpace[PCIE_CONFIG_SPACE_SIZE/sizeof(NvU32)]; + NvU32 azaliaBootConfigSpace[PCIE_CONFIG_SPACE_SIZE/sizeof(NvU32)]; + + // Saved device control register value (Kepler+) + NvU32 xveDevCtrl; +} KBIF_CACHE_DATA; + typedef struct KERNEL_HOST_VGPU_DEVICE KERNEL_HOST_VGPU_DEVICE; #ifdef NVOC_KERNEL_BIF_H_PRIVATE_ACCESS_ALLOWED @@ -112,10 +154,22 @@ struct KernelBif { void (*__kbifApplyWARBug3208922__)(struct OBJGPU *, struct KernelBif *); void (*__kbifProbePcieReqAtomicCaps__)(struct OBJGPU *, struct KernelBif *); void (*__kbifEnablePcieAtomics__)(struct OBJGPU *, struct KernelBif *); + NV_STATUS (*__kbifInitXveRegMap__)(struct OBJGPU *, struct KernelBif *, NvU8); + NvU32 (*__kbifGetMSIXTableVectorControlSize__)(struct OBJGPU *, struct KernelBif *); NV_STATUS (*__kbifGetPciConfigSpacePriMirror__)(struct OBJGPU *, struct KernelBif *, NvU32 *, NvU32 *); NV_STATUS (*__kbifGetBusOptionsAddr__)(struct OBJGPU *, struct KernelBif *, BUS_OPTIONS, NvU32 *); NV_STATUS (*__kbifPreOsGlobalErotGrantRequest__)(struct OBJGPU *, struct KernelBif *); + NV_STATUS (*__kbifStopSysMemRequests__)(struct OBJGPU *, struct KernelBif *, NvBool); + NV_STATUS (*__kbifWaitForTransactionsComplete__)(struct OBJGPU *, struct KernelBif *); + NV_STATUS (*__kbifTriggerFlr__)(struct OBJGPU *, struct KernelBif *); + void (*__kbifCacheFlrSupport__)(struct OBJGPU *, struct KernelBif *); + void (*__kbifCache64bBar0Support__)(struct OBJGPU *, struct KernelBif *); void (*__kbifCacheVFInfo__)(struct OBJGPU *, struct KernelBif *); + void (*__kbifRestoreBar0__)(struct OBJGPU *, struct KernelBif *, void *, NvU32 *); + NvBool (*__kbifAnyBarsAreValid__)(struct OBJGPU *, struct KernelBif *); + NV_STATUS (*__kbifRestoreBarsAndCommand__)(struct OBJGPU *, struct KernelBif *); + void (*__kbifStoreBarRegOffsets__)(struct OBJGPU *, struct KernelBif *, NvU32); + NV_STATUS (*__kbifInit__)(struct OBJGPU *, struct KernelBif *); NV_STATUS (*__kbifStatePreLoad__)(POBJGPU, struct KernelBif *, NvU32); NV_STATUS (*__kbifStatePostUnload__)(POBJGPU, struct KernelBif *, NvU32); void (*__kbifStateDestroy__)(POBJGPU, struct KernelBif *); @@ -140,14 +194,21 @@ struct KernelBif { NvBool PDB_PROP_KBIF_PCIE_GEN4_CAPABLE; NvBool PDB_PROP_KBIF_PCIE_RELAXED_ORDERING_SET_IN_EMULATED_CONFIG_SPACE; NvBool PDB_PROP_KBIF_SYSTEM_ACCESS_DISABLED; + NvBool PDB_PROP_KBIF_FLR_SUPPORTED; + NvBool PDB_PROP_KBIF_64BIT_BAR0_SUPPORTED; + NvBool PDB_PROP_KBIF_DEVICE_IS_MULTIFUNCTION; + NvBool PDB_PROP_KBIF_GCX_PMU_CFG_SPACE_RESTORE; NvU32 dmaCaps; RmPhysAddr dmaWindowStartAddress; NvU32 p2pOverride; NvU32 forceP2PType; NvBool peerMappingOverride; NvBool EnteredRecoverySinceErrorsLastChecked; + KBIF_CACHE_DATA cacheData; NvU32 osPcieAtomicsOpMask; + KBIF_XVE_REGMAP_REF xveRegmapRef[2]; NvBool bMnocAvailable; + NvU32 barRegOffsets[7]; }; #ifndef __NVOC_CLASS_KernelBif_TYPEDEF__ @@ -179,6 +240,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelBif; #define PDB_PROP_KBIF_IS_MSIX_ENABLED_BASE_NAME PDB_PROP_KBIF_IS_MSIX_ENABLED #define PDB_PROP_KBIF_P2P_WRITES_DISABLED_BASE_CAST #define PDB_PROP_KBIF_P2P_WRITES_DISABLED_BASE_NAME PDB_PROP_KBIF_P2P_WRITES_DISABLED +#define PDB_PROP_KBIF_FLR_SUPPORTED_BASE_CAST +#define PDB_PROP_KBIF_FLR_SUPPORTED_BASE_NAME PDB_PROP_KBIF_FLR_SUPPORTED #define PDB_PROP_KBIF_USE_CONFIG_SPACE_TO_REARM_MSI_BASE_CAST #define PDB_PROP_KBIF_USE_CONFIG_SPACE_TO_REARM_MSI_BASE_NAME PDB_PROP_KBIF_USE_CONFIG_SPACE_TO_REARM_MSI #define PDB_PROP_KBIF_IS_MSI_ENABLED_BASE_CAST @@ -187,6 +250,10 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelBif; #define PDB_PROP_KBIF_PCIE_RELAXED_ORDERING_SET_IN_EMULATED_CONFIG_SPACE_BASE_NAME PDB_PROP_KBIF_PCIE_RELAXED_ORDERING_SET_IN_EMULATED_CONFIG_SPACE #define PDB_PROP_KBIF_SYSTEM_ACCESS_DISABLED_BASE_CAST #define PDB_PROP_KBIF_SYSTEM_ACCESS_DISABLED_BASE_NAME PDB_PROP_KBIF_SYSTEM_ACCESS_DISABLED +#define PDB_PROP_KBIF_GCX_PMU_CFG_SPACE_RESTORE_BASE_CAST +#define PDB_PROP_KBIF_GCX_PMU_CFG_SPACE_RESTORE_BASE_NAME PDB_PROP_KBIF_GCX_PMU_CFG_SPACE_RESTORE +#define PDB_PROP_KBIF_64BIT_BAR0_SUPPORTED_BASE_CAST +#define PDB_PROP_KBIF_64BIT_BAR0_SUPPORTED_BASE_NAME PDB_PROP_KBIF_64BIT_BAR0_SUPPORTED #define PDB_PROP_KBIF_UPSTREAM_LTR_SUPPORT_WAR_BUG_200634944_BASE_CAST #define PDB_PROP_KBIF_UPSTREAM_LTR_SUPPORT_WAR_BUG_200634944_BASE_NAME PDB_PROP_KBIF_UPSTREAM_LTR_SUPPORT_WAR_BUG_200634944 #define PDB_PROP_KBIF_IS_MSIX_CACHED_BASE_CAST @@ -201,6 +268,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelBif; #define PDB_PROP_KBIF_IS_FMODEL_MSI_BROKEN_BASE_NAME PDB_PROP_KBIF_IS_FMODEL_MSI_BROKEN #define PDB_PROP_KBIF_IS_MSI_CACHED_BASE_CAST #define PDB_PROP_KBIF_IS_MSI_CACHED_BASE_NAME PDB_PROP_KBIF_IS_MSI_CACHED +#define PDB_PROP_KBIF_DEVICE_IS_MULTIFUNCTION_BASE_CAST +#define PDB_PROP_KBIF_DEVICE_IS_MULTIFUNCTION_BASE_NAME PDB_PROP_KBIF_DEVICE_IS_MULTIFUNCTION #define PDB_PROP_KBIF_SUPPORT_NONCOHERENT_BASE_CAST #define PDB_PROP_KBIF_SUPPORT_NONCOHERENT_BASE_NAME PDB_PROP_KBIF_SUPPORT_NONCOHERENT @@ -258,14 +327,38 @@ NV_STATUS __nvoc_objCreate_KernelBif(KernelBif**, Dynamic*, NvU32); #define kbifProbePcieReqAtomicCaps_HAL(pGpu, pKernelBif) kbifProbePcieReqAtomicCaps_DISPATCH(pGpu, pKernelBif) #define kbifEnablePcieAtomics(pGpu, pKernelBif) kbifEnablePcieAtomics_DISPATCH(pGpu, pKernelBif) #define kbifEnablePcieAtomics_HAL(pGpu, pKernelBif) kbifEnablePcieAtomics_DISPATCH(pGpu, pKernelBif) +#define kbifInitXveRegMap(pGpu, pKernelBif, arg0) kbifInitXveRegMap_DISPATCH(pGpu, pKernelBif, arg0) +#define kbifInitXveRegMap_HAL(pGpu, pKernelBif, arg0) kbifInitXveRegMap_DISPATCH(pGpu, pKernelBif, arg0) +#define kbifGetMSIXTableVectorControlSize(pGpu, pKernelBif) kbifGetMSIXTableVectorControlSize_DISPATCH(pGpu, pKernelBif) +#define kbifGetMSIXTableVectorControlSize_HAL(pGpu, pKernelBif) kbifGetMSIXTableVectorControlSize_DISPATCH(pGpu, pKernelBif) #define kbifGetPciConfigSpacePriMirror(pGpu, pKernelBif, pMirrorBase, pMirrorSize) kbifGetPciConfigSpacePriMirror_DISPATCH(pGpu, pKernelBif, pMirrorBase, pMirrorSize) #define kbifGetPciConfigSpacePriMirror_HAL(pGpu, pKernelBif, pMirrorBase, pMirrorSize) kbifGetPciConfigSpacePriMirror_DISPATCH(pGpu, pKernelBif, pMirrorBase, pMirrorSize) #define kbifGetBusOptionsAddr(pGpu, pKernelBif, options, addrReg) kbifGetBusOptionsAddr_DISPATCH(pGpu, pKernelBif, options, addrReg) #define kbifGetBusOptionsAddr_HAL(pGpu, pKernelBif, options, addrReg) kbifGetBusOptionsAddr_DISPATCH(pGpu, pKernelBif, options, addrReg) #define kbifPreOsGlobalErotGrantRequest(pGpu, pKernelBif) kbifPreOsGlobalErotGrantRequest_DISPATCH(pGpu, pKernelBif) #define kbifPreOsGlobalErotGrantRequest_HAL(pGpu, pKernelBif) kbifPreOsGlobalErotGrantRequest_DISPATCH(pGpu, pKernelBif) +#define kbifStopSysMemRequests(pGpu, pKernelBif, bStop) kbifStopSysMemRequests_DISPATCH(pGpu, pKernelBif, bStop) +#define kbifStopSysMemRequests_HAL(pGpu, pKernelBif, bStop) kbifStopSysMemRequests_DISPATCH(pGpu, pKernelBif, bStop) +#define kbifWaitForTransactionsComplete(pGpu, pKernelBif) kbifWaitForTransactionsComplete_DISPATCH(pGpu, pKernelBif) +#define kbifWaitForTransactionsComplete_HAL(pGpu, pKernelBif) kbifWaitForTransactionsComplete_DISPATCH(pGpu, pKernelBif) +#define kbifTriggerFlr(pGpu, pKernelBif) kbifTriggerFlr_DISPATCH(pGpu, pKernelBif) +#define kbifTriggerFlr_HAL(pGpu, pKernelBif) kbifTriggerFlr_DISPATCH(pGpu, pKernelBif) +#define kbifCacheFlrSupport(pGpu, pKernelBif) kbifCacheFlrSupport_DISPATCH(pGpu, pKernelBif) +#define kbifCacheFlrSupport_HAL(pGpu, pKernelBif) kbifCacheFlrSupport_DISPATCH(pGpu, pKernelBif) +#define kbifCache64bBar0Support(pGpu, pKernelBif) kbifCache64bBar0Support_DISPATCH(pGpu, pKernelBif) +#define kbifCache64bBar0Support_HAL(pGpu, pKernelBif) kbifCache64bBar0Support_DISPATCH(pGpu, pKernelBif) #define kbifCacheVFInfo(pGpu, pKernelBif) kbifCacheVFInfo_DISPATCH(pGpu, pKernelBif) #define kbifCacheVFInfo_HAL(pGpu, pKernelBif) kbifCacheVFInfo_DISPATCH(pGpu, pKernelBif) +#define kbifRestoreBar0(pGpu, pKernelBif, arg0, arg1) kbifRestoreBar0_DISPATCH(pGpu, pKernelBif, arg0, arg1) +#define kbifRestoreBar0_HAL(pGpu, pKernelBif, arg0, arg1) kbifRestoreBar0_DISPATCH(pGpu, pKernelBif, arg0, arg1) +#define kbifAnyBarsAreValid(pGpu, pKernelBif) kbifAnyBarsAreValid_DISPATCH(pGpu, pKernelBif) +#define kbifAnyBarsAreValid_HAL(pGpu, pKernelBif) kbifAnyBarsAreValid_DISPATCH(pGpu, pKernelBif) +#define kbifRestoreBarsAndCommand(pGpu, pKernelBif) kbifRestoreBarsAndCommand_DISPATCH(pGpu, pKernelBif) +#define kbifRestoreBarsAndCommand_HAL(pGpu, pKernelBif) kbifRestoreBarsAndCommand_DISPATCH(pGpu, pKernelBif) +#define kbifStoreBarRegOffsets(pGpu, pKernelBif, arg0) kbifStoreBarRegOffsets_DISPATCH(pGpu, pKernelBif, arg0) +#define kbifStoreBarRegOffsets_HAL(pGpu, pKernelBif, arg0) kbifStoreBarRegOffsets_DISPATCH(pGpu, pKernelBif, arg0) +#define kbifInit(pGpu, pKernelBif) kbifInit_DISPATCH(pGpu, pKernelBif) +#define kbifInit_HAL(pGpu, pKernelBif) kbifInit_DISPATCH(pGpu, pKernelBif) #define kbifStatePreLoad(pGpu, pEngstate, arg0) kbifStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define kbifStatePostUnload(pGpu, pEngstate, arg0) kbifStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) #define kbifStateDestroy(pGpu, pEngstate) kbifStateDestroy_DISPATCH(pGpu, pEngstate) @@ -275,6 +368,10 @@ NV_STATUS __nvoc_objCreate_KernelBif(KernelBif**, Dynamic*, NvU32); #define kbifStatePreInitLocked(pGpu, pEngstate) kbifStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define kbifStatePreInitUnlocked(pGpu, pEngstate) kbifStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) #define kbifIsPresent(pGpu, pEngstate) kbifIsPresent_DISPATCH(pGpu, pEngstate) +void kbifDestruct_GM107(struct KernelBif *pKernelBif); + + +#define __nvoc_kbifDestruct(pKernelBif) kbifDestruct_GM107(pKernelBif) static inline NvU32 kbifGetBusIntfType_2f2c74(struct KernelBif *pKernelBif) { return (3); } @@ -358,20 +455,20 @@ static inline NV_STATUS kbifDisableSysmemAccess(struct OBJGPU *pGpu, struct Kern #define kbifDisableSysmemAccess_HAL(pGpu, pKernelBif, bDisable) kbifDisableSysmemAccess(pGpu, pKernelBif, bDisable) -static inline void kbifIsMnocSupported_b3696a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { +static inline void kbifCacheMnocSupport_b3696a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { return; } #ifdef __nvoc_kernel_bif_h_disabled -static inline void kbifIsMnocSupported(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { +static inline void kbifCacheMnocSupport(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); } #else //__nvoc_kernel_bif_h_disabled -#define kbifIsMnocSupported(pGpu, pKernelBif) kbifIsMnocSupported_b3696a(pGpu, pKernelBif) +#define kbifCacheMnocSupport(pGpu, pKernelBif) kbifCacheMnocSupport_b3696a(pGpu, pKernelBif) #endif //__nvoc_kernel_bif_h_disabled -#define kbifIsMnocSupported_HAL(pGpu, pKernelBif) kbifIsMnocSupported(pGpu, pKernelBif) +#define kbifCacheMnocSupport_HAL(pGpu, pKernelBif) kbifCacheMnocSupport(pGpu, pKernelBif) NV_STATUS kbifConstructEngine_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, ENGDESCRIPTOR arg0); @@ -583,6 +680,22 @@ static inline void kbifEnablePcieAtomics_DISPATCH(struct OBJGPU *pGpu, struct Ke pKernelBif->__kbifEnablePcieAtomics__(pGpu, pKernelBif); } +NV_STATUS kbifInitXveRegMap_TU102(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU8 arg0); + +NV_STATUS kbifInitXveRegMap_GA102(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU8 arg0); + +static inline NV_STATUS kbifInitXveRegMap_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU8 arg0) { + return pKernelBif->__kbifInitXveRegMap__(pGpu, pKernelBif, arg0); +} + +NvU32 kbifGetMSIXTableVectorControlSize_TU102(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +NvU32 kbifGetMSIXTableVectorControlSize_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +static inline NvU32 kbifGetMSIXTableVectorControlSize_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return pKernelBif->__kbifGetMSIXTableVectorControlSize__(pGpu, pKernelBif); +} + NV_STATUS kbifGetPciConfigSpacePriMirror_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pMirrorBase, NvU32 *pMirrorSize); NV_STATUS kbifGetPciConfigSpacePriMirror_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pMirrorBase, NvU32 *pMirrorSize); @@ -609,6 +722,50 @@ static inline NV_STATUS kbifPreOsGlobalErotGrantRequest_DISPATCH(struct OBJGPU * return pKernelBif->__kbifPreOsGlobalErotGrantRequest__(pGpu, pKernelBif); } +NV_STATUS kbifStopSysMemRequests_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvBool bStop); + +NV_STATUS kbifStopSysMemRequests_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvBool bStop); + +static inline NV_STATUS kbifStopSysMemRequests_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvBool bStop) { + return pKernelBif->__kbifStopSysMemRequests__(pGpu, pKernelBif, bStop); +} + +NV_STATUS kbifWaitForTransactionsComplete_TU102(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +NV_STATUS kbifWaitForTransactionsComplete_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +static inline NV_STATUS kbifWaitForTransactionsComplete_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return pKernelBif->__kbifWaitForTransactionsComplete__(pGpu, pKernelBif); +} + +NV_STATUS kbifTriggerFlr_TU102(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +NV_STATUS kbifTriggerFlr_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +static inline NV_STATUS kbifTriggerFlr_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return pKernelBif->__kbifTriggerFlr__(pGpu, pKernelBif); +} + +void kbifCacheFlrSupport_TU102(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +void kbifCacheFlrSupport_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +static inline void kbifCacheFlrSupport_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + pKernelBif->__kbifCacheFlrSupport__(pGpu, pKernelBif); +} + +static inline void kbifCache64bBar0Support_b3696a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return; +} + +void kbifCache64bBar0Support_GA100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +void kbifCache64bBar0Support_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +static inline void kbifCache64bBar0Support_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + pKernelBif->__kbifCache64bBar0Support__(pGpu, pKernelBif); +} + void kbifCacheVFInfo_TU102(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); void kbifCacheVFInfo_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); @@ -617,6 +774,50 @@ static inline void kbifCacheVFInfo_DISPATCH(struct OBJGPU *pGpu, struct KernelBi pKernelBif->__kbifCacheVFInfo__(pGpu, pKernelBif); } +void kbifRestoreBar0_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, void *arg0, NvU32 *arg1); + +void kbifRestoreBar0_GA100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, void *arg0, NvU32 *arg1); + +static inline void kbifRestoreBar0_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, void *arg0, NvU32 *arg1) { + pKernelBif->__kbifRestoreBar0__(pGpu, pKernelBif, arg0, arg1); +} + +NvBool kbifAnyBarsAreValid_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +NvBool kbifAnyBarsAreValid_GA100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +static inline NvBool kbifAnyBarsAreValid_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return pKernelBif->__kbifAnyBarsAreValid__(pGpu, pKernelBif); +} + +NV_STATUS kbifRestoreBarsAndCommand_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +NV_STATUS kbifRestoreBarsAndCommand_GA100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +NV_STATUS kbifRestoreBarsAndCommand_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +static inline NV_STATUS kbifRestoreBarsAndCommand_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return pKernelBif->__kbifRestoreBarsAndCommand__(pGpu, pKernelBif); +} + +void kbifStoreBarRegOffsets_GA100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 arg0); + +static inline void kbifStoreBarRegOffsets_b3696a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 arg0) { + return; +} + +static inline void kbifStoreBarRegOffsets_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 arg0) { + pKernelBif->__kbifStoreBarRegOffsets__(pGpu, pKernelBif, arg0); +} + +NV_STATUS kbifInit_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +NV_STATUS kbifInit_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +static inline NV_STATUS kbifInit_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return pKernelBif->__kbifInit__(pGpu, pKernelBif); +} + static inline NV_STATUS kbifStatePreLoad_DISPATCH(POBJGPU pGpu, struct KernelBif *pEngstate, NvU32 arg0) { return pEngstate->__kbifStatePreLoad__(pGpu, pEngstate, arg0); } @@ -780,4 +981,5 @@ static inline NvU32 kbifGetDmaCaps(struct OBJGPU *pGpu, struct KernelBif *pKerne #ifdef __cplusplus } // extern "C" #endif + #endif // _G_KERNEL_BIF_NVOC_H_ diff --git a/src/nvidia/generated/g_kernel_ccu_api_nvoc.h b/src/nvidia/generated/g_kernel_ccu_api_nvoc.h index e20c176896..9fbcbfbcac 100644 --- a/src/nvidia/generated/g_kernel_ccu_api_nvoc.h +++ b/src/nvidia/generated/g_kernel_ccu_api_nvoc.h @@ -291,4 +291,5 @@ void kccuapiDestruct_IMPL(struct KernelCcuApi *pKernelCcuApi); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_KERNEL_CCU_API_NVOC_H_ diff --git a/src/nvidia/generated/g_kernel_ccu_nvoc.h b/src/nvidia/generated/g_kernel_ccu_nvoc.h index 634ee2fe11..b918bf7ab8 100644 --- a/src/nvidia/generated/g_kernel_ccu_nvoc.h +++ b/src/nvidia/generated/g_kernel_ccu_nvoc.h @@ -363,4 +363,5 @@ static inline NV_STATUS kccuMemDescGetForComputeInst(OBJGPU *arg0, struct Kernel #ifdef __cplusplus } // extern "C" #endif + #endif // _G_KERNEL_CCU_NVOC_H_ diff --git a/src/nvidia/generated/g_kernel_ce_context_nvoc.c b/src/nvidia/generated/g_kernel_ce_context_nvoc.c index aa39ddc1b7..1e161dfcfd 100644 --- a/src/nvidia/generated/g_kernel_ce_context_nvoc.c +++ b/src/nvidia/generated/g_kernel_ce_context_nvoc.c @@ -136,7 +136,7 @@ static NV_STATUS __nvoc_thunk_RsResource_kcectxMapTo(struct KernelCeContext *pRe return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCeContext_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_GpuResource_kcectxGetMapAddrSpace(struct KernelCeContext *pGpuResource, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { +static NV_STATUS __nvoc_thunk_GpuResource_kcectxGetMapAddrSpace(struct KernelCeContext *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCeContext_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); } @@ -184,11 +184,11 @@ static NvHandle __nvoc_thunk_GpuResource_kcectxGetInternalObjectHandle(struct Ke return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCeContext_GpuResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_kcectxControl(struct KernelCeContext *pGpuResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { +static NV_STATUS __nvoc_thunk_GpuResource_kcectxControl(struct KernelCeContext *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCeContext_GpuResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_GpuResource_kcectxUnmap(struct KernelCeContext *pGpuResource, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { +static NV_STATUS __nvoc_thunk_GpuResource_kcectxUnmap(struct KernelCeContext *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCeContext_GpuResource.offset), pCallContext, pCpuMapping); } @@ -240,7 +240,7 @@ static struct NotifShare *__nvoc_thunk_Notifier_kcectxGetNotificationShare(struc return notifyGetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_KernelCeContext_Notifier.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_kcectxMap(struct KernelCeContext *pGpuResource, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { +static NV_STATUS __nvoc_thunk_GpuResource_kcectxMap(struct KernelCeContext *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { return gpuresMap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCeContext_GpuResource.offset), pCallContext, pParams, pCpuMapping); } diff --git a/src/nvidia/generated/g_kernel_ce_context_nvoc.h b/src/nvidia/generated/g_kernel_ce_context_nvoc.h index d418a73b5e..5b33c83b88 100644 --- a/src/nvidia/generated/g_kernel_ce_context_nvoc.h +++ b/src/nvidia/generated/g_kernel_ce_context_nvoc.h @@ -66,7 +66,7 @@ struct KernelCeContext { NvBool (*__kcectxShareCallback__)(struct KernelCeContext *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NvBool (*__kcectxAccessCallback__)(struct KernelCeContext *, struct RsClient *, void *, RsAccessRight); NV_STATUS (*__kcectxMapTo__)(struct KernelCeContext *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__kcectxGetMapAddrSpace__)(struct KernelCeContext *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NV_STATUS (*__kcectxGetMapAddrSpace__)(struct KernelCeContext *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); void (*__kcectxSetNotificationShare__)(struct KernelCeContext *, struct NotifShare *); NvU32 (*__kcectxGetRefCount__)(struct KernelCeContext *); void (*__kcectxAddAdditionalDependants__)(struct RsClient *, struct KernelCeContext *, RsResourceRef *); @@ -78,8 +78,8 @@ struct KernelCeContext { NV_STATUS (*__kcectxControlLookup__)(struct KernelCeContext *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__kcectxGetSwMethods__)(struct KernelCeContext *, const METHOD **, NvU32 *); NvHandle (*__kcectxGetInternalObjectHandle__)(struct KernelCeContext *); - NV_STATUS (*__kcectxControl__)(struct KernelCeContext *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__kcectxUnmap__)(struct KernelCeContext *, CALL_CONTEXT *, RsCpuMapping *); + NV_STATUS (*__kcectxControl__)(struct KernelCeContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__kcectxUnmap__)(struct KernelCeContext *, struct CALL_CONTEXT *, struct RsCpuMapping *); NV_STATUS (*__kcectxGetMemInterMapParams__)(struct KernelCeContext *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__kcectxGetMemoryMappingDescriptor__)(struct KernelCeContext *, struct MEMORY_DESCRIPTOR **); NvBool (*__kcectxIsSwMethodStalling__)(struct KernelCeContext *, NvU32); @@ -92,7 +92,7 @@ struct KernelCeContext { void (*__kcectxControlSerialization_Epilogue__)(struct KernelCeContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__kcectxGetNotificationListPtr__)(struct KernelCeContext *); struct NotifShare *(*__kcectxGetNotificationShare__)(struct KernelCeContext *); - NV_STATUS (*__kcectxMap__)(struct KernelCeContext *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); + NV_STATUS (*__kcectxMap__)(struct KernelCeContext *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NV_STATUS (*__kcectxGetOrAllocNotifShare__)(struct KernelCeContext *, NvHandle, NvHandle, struct NotifShare **); }; @@ -172,7 +172,7 @@ static inline NV_STATUS kcectxMapTo_DISPATCH(struct KernelCeContext *pResource, return pResource->__kcectxMapTo__(pResource, pParams); } -static inline NV_STATUS kcectxGetMapAddrSpace_DISPATCH(struct KernelCeContext *pGpuResource, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { +static inline NV_STATUS kcectxGetMapAddrSpace_DISPATCH(struct KernelCeContext *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { return pGpuResource->__kcectxGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); } @@ -220,11 +220,11 @@ static inline NvHandle kcectxGetInternalObjectHandle_DISPATCH(struct KernelCeCon return pGpuResource->__kcectxGetInternalObjectHandle__(pGpuResource); } -static inline NV_STATUS kcectxControl_DISPATCH(struct KernelCeContext *pGpuResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { +static inline NV_STATUS kcectxControl_DISPATCH(struct KernelCeContext *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pGpuResource->__kcectxControl__(pGpuResource, pCallContext, pParams); } -static inline NV_STATUS kcectxUnmap_DISPATCH(struct KernelCeContext *pGpuResource, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { +static inline NV_STATUS kcectxUnmap_DISPATCH(struct KernelCeContext *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { return pGpuResource->__kcectxUnmap__(pGpuResource, pCallContext, pCpuMapping); } @@ -276,7 +276,7 @@ static inline struct NotifShare *kcectxGetNotificationShare_DISPATCH(struct Kern return pNotifier->__kcectxGetNotificationShare__(pNotifier); } -static inline NV_STATUS kcectxMap_DISPATCH(struct KernelCeContext *pGpuResource, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { +static inline NV_STATUS kcectxMap_DISPATCH(struct KernelCeContext *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { return pGpuResource->__kcectxMap__(pGpuResource, pCallContext, pParams, pCpuMapping); } @@ -298,4 +298,5 @@ void kcectxDestruct_IMPL(struct KernelCeContext *pKCeContext); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_KERNEL_CE_CONTEXT_NVOC_H_ diff --git a/src/nvidia/generated/g_kernel_ce_nvoc.c b/src/nvidia/generated/g_kernel_ce_nvoc.c index b1f4d93f81..e42f5c642d 100644 --- a/src/nvidia/generated/g_kernel_ce_nvoc.c +++ b/src/nvidia/generated/g_kernel_ce_nvoc.c @@ -91,7 +91,7 @@ static NV_STATUS __nvoc_thunk_KernelCE_engstateStateUnload(OBJGPU *pGpu, struct return kceStateUnload(pGpu, (struct KernelCE *)(((unsigned char *)pKCe) - __nvoc_rtti_KernelCE_OBJENGSTATE.offset), flags); } -static void __nvoc_thunk_KernelCE_intrservRegisterIntrService(OBJGPU *arg0, struct IntrService *arg1, IntrServiceRecord arg2[167]) { +static void __nvoc_thunk_KernelCE_intrservRegisterIntrService(OBJGPU *arg0, struct IntrService *arg1, IntrServiceRecord arg2[168]) { kceRegisterIntrService(arg0, (struct KernelCE *)(((unsigned char *)arg1) - __nvoc_rtti_KernelCE_IntrService.offset), arg2); } @@ -221,16 +221,6 @@ static void __nvoc_init_funcTable_KernelCE_1(KernelCE *pThis, RmHalspecOwner *pR pThis->__kceServiceNotificationInterrupt__ = &kceServiceNotificationInterrupt_IMPL; - // Hal function -- kceGetP2PCes - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ - { - pThis->__kceGetP2PCes__ = &kceGetP2PCes_GH100; - } - else - { - pThis->__kceGetP2PCes__ = &kceGetP2PCes_GV100; - } - // Hal function -- kceGetNvlinkAutoConfigCeValues if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { diff --git a/src/nvidia/generated/g_kernel_ce_nvoc.h b/src/nvidia/generated/g_kernel_ce_nvoc.h index 90d04d2b72..d0d09f1879 100644 --- a/src/nvidia/generated/g_kernel_ce_nvoc.h +++ b/src/nvidia/generated/g_kernel_ce_nvoc.h @@ -113,7 +113,6 @@ struct KernelCE { NV_STATUS (*__kceStateUnload__)(OBJGPU *, struct KernelCE *, NvU32); void (*__kceRegisterIntrService__)(OBJGPU *, struct KernelCE *, IntrServiceRecord *); NV_STATUS (*__kceServiceNotificationInterrupt__)(OBJGPU *, struct KernelCE *, IntrServiceServiceNotificationInterruptArguments *); - NV_STATUS (*__kceGetP2PCes__)(struct KernelCE *, OBJGPU *, NvU32, NvU32 *); NV_STATUS (*__kceGetNvlinkAutoConfigCeValues__)(OBJGPU *, struct KernelCE *, NvU32 *, NvU32 *, NvU32 *); NvBool (*__kceGetNvlinkMaxTopoForTable__)(OBJGPU *, struct KernelCE *, struct NVLINK_TOPOLOGY_PARAMS *, void *, NvU32, NvU32 *); NvBool (*__kceIsCurrentMaxTopology__)(OBJGPU *, struct KernelCE *, struct NVLINK_TOPOLOGY_PARAMS *, NvU32 *, NvU32 *); @@ -191,8 +190,6 @@ NV_STATUS __nvoc_objCreate_KernelCE(KernelCE**, Dynamic*, NvU32); #define kceStateUnload_HAL(pGpu, pKCe, flags) kceStateUnload_DISPATCH(pGpu, pKCe, flags) #define kceRegisterIntrService(arg0, arg1, arg2) kceRegisterIntrService_DISPATCH(arg0, arg1, arg2) #define kceServiceNotificationInterrupt(arg0, arg1, arg2) kceServiceNotificationInterrupt_DISPATCH(arg0, arg1, arg2) -#define kceGetP2PCes(arg0, pGpu, gpuMask, nvlinkP2PCeMask) kceGetP2PCes_DISPATCH(arg0, pGpu, gpuMask, nvlinkP2PCeMask) -#define kceGetP2PCes_HAL(arg0, pGpu, gpuMask, nvlinkP2PCeMask) kceGetP2PCes_DISPATCH(arg0, pGpu, gpuMask, nvlinkP2PCeMask) #define kceGetNvlinkAutoConfigCeValues(pGpu, pKCe, arg0, arg1, arg2) kceGetNvlinkAutoConfigCeValues_DISPATCH(pGpu, pKCe, arg0, arg1, arg2) #define kceGetNvlinkAutoConfigCeValues_HAL(pGpu, pKCe, arg0, arg1, arg2) kceGetNvlinkAutoConfigCeValues_DISPATCH(pGpu, pKCe, arg0, arg1, arg2) #define kceGetNvlinkMaxTopoForTable(pGpu, pKCe, arg0, arg1, arg2, arg3) kceGetNvlinkMaxTopoForTable_DISPATCH(pGpu, pKCe, arg0, arg1, arg2, arg3) @@ -308,6 +305,20 @@ static inline NvBool kceIsCeNvlinkP2P(OBJGPU *pGpu, struct KernelCE *pKCe) { #define kceIsCeNvlinkP2P_HAL(pGpu, pKCe) kceIsCeNvlinkP2P(pGpu, pKCe) +NV_STATUS kceGetP2PCes_GV100(struct KernelCE *arg0, OBJGPU *pGpu, NvU32 gpuMask, NvU32 *nvlinkP2PCeMask); + + +#ifdef __nvoc_kernel_ce_h_disabled +static inline NV_STATUS kceGetP2PCes(struct KernelCE *arg0, OBJGPU *pGpu, NvU32 gpuMask, NvU32 *nvlinkP2PCeMask) { + NV_ASSERT_FAILED_PRECOMP("KernelCE was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_ce_h_disabled +#define kceGetP2PCes(arg0, pGpu, gpuMask, nvlinkP2PCeMask) kceGetP2PCes_GV100(arg0, pGpu, gpuMask, nvlinkP2PCeMask) +#endif //__nvoc_kernel_ce_h_disabled + +#define kceGetP2PCes_HAL(arg0, pGpu, gpuMask, nvlinkP2PCeMask) kceGetP2PCes(arg0, pGpu, gpuMask, nvlinkP2PCeMask) + void kceGetSysmemRWLCEs_GV100(struct KernelCE *arg0, NvU32 *rd, NvU32 *wr); @@ -374,9 +385,9 @@ static inline NV_STATUS kceStateUnload_DISPATCH(OBJGPU *pGpu, struct KernelCE *p return pKCe->__kceStateUnload__(pGpu, pKCe, flags); } -void kceRegisterIntrService_IMPL(OBJGPU *arg0, struct KernelCE *arg1, IntrServiceRecord arg2[167]); +void kceRegisterIntrService_IMPL(OBJGPU *arg0, struct KernelCE *arg1, IntrServiceRecord arg2[168]); -static inline void kceRegisterIntrService_DISPATCH(OBJGPU *arg0, struct KernelCE *arg1, IntrServiceRecord arg2[167]) { +static inline void kceRegisterIntrService_DISPATCH(OBJGPU *arg0, struct KernelCE *arg1, IntrServiceRecord arg2[168]) { arg1->__kceRegisterIntrService__(arg0, arg1, arg2); } @@ -386,14 +397,6 @@ static inline NV_STATUS kceServiceNotificationInterrupt_DISPATCH(OBJGPU *arg0, s return arg1->__kceServiceNotificationInterrupt__(arg0, arg1, arg2); } -NV_STATUS kceGetP2PCes_GV100(struct KernelCE *arg0, OBJGPU *pGpu, NvU32 gpuMask, NvU32 *nvlinkP2PCeMask); - -NV_STATUS kceGetP2PCes_GH100(struct KernelCE *arg0, OBJGPU *pGpu, NvU32 gpuMask, NvU32 *nvlinkP2PCeMask); - -static inline NV_STATUS kceGetP2PCes_DISPATCH(struct KernelCE *arg0, OBJGPU *pGpu, NvU32 gpuMask, NvU32 *nvlinkP2PCeMask) { - return arg0->__kceGetP2PCes__(arg0, pGpu, gpuMask, nvlinkP2PCeMask); -} - NV_STATUS kceGetNvlinkAutoConfigCeValues_TU102(OBJGPU *pGpu, struct KernelCE *pKCe, NvU32 *arg0, NvU32 *arg1, NvU32 *arg2); NV_STATUS kceGetNvlinkAutoConfigCeValues_GA100(OBJGPU *pGpu, struct KernelCE *pKCe, NvU32 *arg0, NvU32 *arg1, NvU32 *arg2); @@ -633,9 +636,9 @@ static inline NV_STATUS kceTopLevelPceLceMappingsUpdate(OBJGPU *pGpu, struct Ker NV_STATUS kceGetFaultMethodBufferSize_IMPL(OBJGPU *pGpu, NvU32 *size); #define kceGetFaultMethodBufferSize(pGpu, size) kceGetFaultMethodBufferSize_IMPL(pGpu, size) -NV_STATUS kceGetAvailableHubPceMask_IMPL(OBJGPU *pGpu, NVLINK_TOPOLOGY_PARAMS *pTopoParams); +NV_STATUS kceGetAvailableHubPceMask_IMPL(OBJGPU *pGpu, struct KernelCE *pKCe, NVLINK_TOPOLOGY_PARAMS *pTopoParams); -#define kceGetAvailableHubPceMask(pGpu, pTopoParams) kceGetAvailableHubPceMask_IMPL(pGpu, pTopoParams) +#define kceGetAvailableHubPceMask(pGpu, pKCe, pTopoParams) kceGetAvailableHubPceMask_IMPL(pGpu, pKCe, pTopoParams) void kceGetNvlinkCaps_IMPL(OBJGPU *pGpu, struct KernelCE *pKCe, NvU8 *pKCeCaps); #ifdef __nvoc_kernel_ce_h_disabled @@ -732,4 +735,5 @@ static inline NV_STATUS kceGetCeFromNvlinkConfig(OBJGPU *pGpu, struct KernelCE * #ifdef __cplusplus } // extern "C" #endif + #endif // _G_KERNEL_CE_NVOC_H_ diff --git a/src/nvidia/generated/g_kernel_channel_group_api_nvoc.h b/src/nvidia/generated/g_kernel_channel_group_api_nvoc.h index c9be207e2c..c78fa4f285 100644 --- a/src/nvidia/generated/g_kernel_channel_group_api_nvoc.h +++ b/src/nvidia/generated/g_kernel_channel_group_api_nvoc.h @@ -446,4 +446,5 @@ NV_STATUS CliGetChannelGroup(NvHandle, NvHandle, RsResourceRef**, NvHandle*); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_KERNEL_CHANNEL_GROUP_API_NVOC_H_ diff --git a/src/nvidia/generated/g_kernel_channel_group_nvoc.h b/src/nvidia/generated/g_kernel_channel_group_nvoc.h index 8abac989b4..4332b4040a 100644 --- a/src/nvidia/generated/g_kernel_channel_group_nvoc.h +++ b/src/nvidia/generated/g_kernel_channel_group_nvoc.h @@ -437,4 +437,5 @@ MAKE_INTRUSIVE_MAP(KernelChannelGroupMap, KernelChannelGroup, mapNode); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_KERNEL_CHANNEL_GROUP_NVOC_H_ diff --git a/src/nvidia/generated/g_kernel_channel_nvoc.h b/src/nvidia/generated/g_kernel_channel_nvoc.h index 2db3a7820f..93c38fd1a7 100644 --- a/src/nvidia/generated/g_kernel_channel_nvoc.h +++ b/src/nvidia/generated/g_kernel_channel_nvoc.h @@ -1509,7 +1509,7 @@ NV_STATUS CliGetKernelChannel(struct RsClient *pClient, * @brief Helper to get type and memdesc of a channel notifier (memory/ctxdma) */ NV_STATUS kchannelGetNotifierInfo(struct OBJGPU *pGpu, - struct RsClient *pRsClient, + Device *pDevice, NvHandle hErrorContext, MEMORY_DESCRIPTOR **ppMemDesc, ErrorNotifierType *pNotifierType, @@ -1549,4 +1549,5 @@ void kchannelSetRunlistSet(struct OBJGPU *pGpu, struct KernelChannel *pKernelCha #ifdef __cplusplus } // extern "C" #endif + #endif // _G_KERNEL_CHANNEL_NVOC_H_ diff --git a/src/nvidia/generated/g_kernel_crashcat_engine_nvoc.h b/src/nvidia/generated/g_kernel_crashcat_engine_nvoc.h index aff96ed20d..38d48b9059 100644 --- a/src/nvidia/generated/g_kernel_crashcat_engine_nvoc.h +++ b/src/nvidia/generated/g_kernel_crashcat_engine_nvoc.h @@ -271,4 +271,5 @@ static inline void kcrashcatEngineUnregisterCrashBuffer(struct KernelCrashCatEng #ifdef __cplusplus } // extern "C" #endif + #endif // _G_KERNEL_CRASHCAT_ENGINE_NVOC_H_ diff --git a/src/nvidia/generated/g_kernel_ctxshare_nvoc.h b/src/nvidia/generated/g_kernel_ctxshare_nvoc.h index 6bdffeb6d9..c2376a3b4c 100644 --- a/src/nvidia/generated/g_kernel_ctxshare_nvoc.h +++ b/src/nvidia/generated/g_kernel_ctxshare_nvoc.h @@ -434,4 +434,5 @@ void kctxshareapiDestruct_IMPL(struct KernelCtxShareApi *pKernelCtxShareApi); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_KERNEL_CTXSHARE_NVOC_H_ diff --git a/src/nvidia/generated/g_kernel_falcon_nvoc.c b/src/nvidia/generated/g_kernel_falcon_nvoc.c index 29a5e038e4..3632f028fe 100644 --- a/src/nvidia/generated/g_kernel_falcon_nvoc.c +++ b/src/nvidia/generated/g_kernel_falcon_nvoc.c @@ -413,7 +413,7 @@ static NV_STATUS __nvoc_thunk_GenericKernelFalcon_kflcnResetHw(struct OBJGPU *pG return gkflcnResetHw(pGpu, (struct GenericKernelFalcon *)(((unsigned char *)pGenKernFlcn) - __nvoc_rtti_GenericKernelFalcon_KernelFalcon.offset)); } -static void __nvoc_thunk_GenericKernelFalcon_intrservRegisterIntrService(struct OBJGPU *arg0, struct IntrService *arg1, IntrServiceRecord arg2[167]) { +static void __nvoc_thunk_GenericKernelFalcon_intrservRegisterIntrService(struct OBJGPU *arg0, struct IntrService *arg1, IntrServiceRecord arg2[168]) { gkflcnRegisterIntrService(arg0, (struct GenericKernelFalcon *)(((unsigned char *)arg1) - __nvoc_rtti_GenericKernelFalcon_IntrService.offset), arg2); } diff --git a/src/nvidia/generated/g_kernel_falcon_nvoc.h b/src/nvidia/generated/g_kernel_falcon_nvoc.h index 20b990cc1e..e167c6bc0d 100644 --- a/src/nvidia/generated/g_kernel_falcon_nvoc.h +++ b/src/nvidia/generated/g_kernel_falcon_nvoc.h @@ -580,9 +580,9 @@ static inline NV_STATUS gkflcnResetHw_DISPATCH(struct OBJGPU *pGpu, struct Gener return pGenKernFlcn->__gkflcnResetHw__(pGpu, pGenKernFlcn); } -void gkflcnRegisterIntrService_IMPL(struct OBJGPU *arg0, struct GenericKernelFalcon *arg1, IntrServiceRecord arg2[167]); +void gkflcnRegisterIntrService_IMPL(struct OBJGPU *arg0, struct GenericKernelFalcon *arg1, IntrServiceRecord arg2[168]); -static inline void gkflcnRegisterIntrService_DISPATCH(struct OBJGPU *arg0, struct GenericKernelFalcon *arg1, IntrServiceRecord arg2[167]) { +static inline void gkflcnRegisterIntrService_DISPATCH(struct OBJGPU *arg0, struct GenericKernelFalcon *arg1, IntrServiceRecord arg2[168]) { arg1->__gkflcnRegisterIntrService__(arg0, arg1, arg2); } @@ -671,4 +671,5 @@ NV_STATUS gkflcnConstruct_IMPL(struct GenericKernelFalcon *arg_pGenKernFlcn, str #ifdef __cplusplus } // extern "C" #endif + #endif // _G_KERNEL_FALCON_NVOC_H_ diff --git a/src/nvidia/generated/g_kernel_fifo_nvoc.c b/src/nvidia/generated/g_kernel_fifo_nvoc.c index 8d0278416c..4a8ae2bd56 100644 --- a/src/nvidia/generated/g_kernel_fifo_nvoc.c +++ b/src/nvidia/generated/g_kernel_fifo_nvoc.c @@ -208,6 +208,12 @@ void __nvoc_init_dataField_KernelFifo(KernelFifo *pThis, RmHalspecOwner *pRmhals pThis->bIsSchedSupported = ((NvBool)(0 == 0)); } + // Hal field -- bGuestGenenratesWorkSubmitToken + // default + { + pThis->bGuestGenenratesWorkSubmitToken = ((NvBool)(0 != 0)); + } + pThis->pBar1VF = ((void *)0); pThis->pBar1PrivVF = ((void *)0); diff --git a/src/nvidia/generated/g_kernel_fifo_nvoc.h b/src/nvidia/generated/g_kernel_fifo_nvoc.h index 0c3102aa2d..004b72ca42 100644 --- a/src/nvidia/generated/g_kernel_fifo_nvoc.h +++ b/src/nvidia/generated/g_kernel_fifo_nvoc.h @@ -43,6 +43,7 @@ extern "C" { #include "kernel/gpu/eng_state.h" #include "kernel/gpu/gpu_halspec.h" #include "kernel/gpu/fifo/channel_descendant.h" +#include "kernel/gpu/fifo/engine_info.h" #include "kernel/gpu/gpu_engine_type.h" #include "containers/eheap_old.h" @@ -168,7 +169,7 @@ typedef enum FIFO_CTX_INST_BLOCK = 1, } FIFO_CTX; -typedef struct +typedef struct _fifo_mmu_exception_data { NvU32 addrLo; NvU32 addrHi; @@ -206,7 +207,7 @@ typedef struct _fifo_hw_id DECLARE_INTRUSIVE_MAP(KernelChannelGroupMap); -typedef struct +typedef struct _chid_mgr { /*! * Runlist managed by this CHID_MGR. @@ -277,96 +278,6 @@ struct channel_iterator CHANNEL_NODE channelNode; }; -typedef enum -{ - /* ************************************************************************* - * Bug 3820969 - * THINK BEFORE CHANGING ENUM ORDER HERE. - * VGPU-guest uses this same ordering. Because this enum is not versioned, - * changing the order here WILL BREAK old-guest-on-newer-host compatibility. - * ************************************************************************/ - - // *ENG_XYZ, e.g.: ENG_GR, ENG_CE etc., - ENGINE_INFO_TYPE_ENG_DESC = 0, - - // HW engine ID - ENGINE_INFO_TYPE_FIFO_TAG, - - // RM_ENGINE_TYPE_* - ENGINE_INFO_TYPE_RM_ENGINE_TYPE, - - // - // runlist id (meaning varies by GPU) - // Valid only for Esched-driven engines - // - ENGINE_INFO_TYPE_RUNLIST, - - // NV_PFIFO_INTR_MMU_FAULT_ENG_ID_* - ENGINE_INFO_TYPE_MMU_FAULT_ID, - - // ROBUST_CHANNEL_* - ENGINE_INFO_TYPE_RC_MASK, - - // Reset Bit Position. On Ampere, only valid if not _INVALID - ENGINE_INFO_TYPE_RESET, - - // Interrupt Bit Position - ENGINE_INFO_TYPE_INTR, - - // log2(MC_ENGINE_*) - ENGINE_INFO_TYPE_MC, - - // The DEV_TYPE_ENUM for this engine - ENGINE_INFO_TYPE_DEV_TYPE_ENUM, - - // The particular instance of this engine type - ENGINE_INFO_TYPE_INSTANCE_ID, - - // - // The base address for this engine's NV_RUNLIST. Valid only on Ampere+ - // Valid only for Esched-driven engines - // - ENGINE_INFO_TYPE_RUNLIST_PRI_BASE, - - // - // If this entry is a host-driven engine. - // Update _isEngineInfoTypeValidForOnlyHostDriven when adding any new entry. - // - ENGINE_INFO_TYPE_IS_HOST_DRIVEN_ENGINE, - - // - // The index into the per-engine NV_RUNLIST registers. Valid only on Ampere+ - // Valid only for Esched-driven engines - // - ENGINE_INFO_TYPE_RUNLIST_ENGINE_ID, - - // - // The base address for this engine's NV_CHRAM registers. Valid only on - // Ampere+ - // - // Valid only for Esched-driven engines - // - ENGINE_INFO_TYPE_CHRAM_PRI_BASE, - - // This entry added to copy data at RMCTRL_EXPORT() call for Kernel RM - ENGINE_INFO_TYPE_KERNEL_RM_MAX, - // Used for iterating the engine info table by the index passed. - ENGINE_INFO_TYPE_INVALID = ENGINE_INFO_TYPE_KERNEL_RM_MAX, - - // Size of FIFO_ENGINE_LIST.engineData - ENGINE_INFO_TYPE_ENGINE_DATA_ARRAY_SIZE = ENGINE_INFO_TYPE_INVALID, - - // Input-only parameter for kfifoEngineInfoXlate. - ENGINE_INFO_TYPE_PBDMA_ID - - /* ************************************************************************* - * Bug 3820969 - * THINK BEFORE CHANGING ENUM ORDER HERE. - * VGPU-guest uses this same ordering. Because this enum is not versioned, - * changing the order here WILL BREAK old-guest-on-newer-host compatibility. - * ************************************************************************/ -} ENGINE_INFO_TYPE; - // Maximum number of pbdma IDs for a given engine #define FIFO_ENGINE_MAX_NUM_PBDMA 2 @@ -409,7 +320,7 @@ typedef struct _def_engine_info } ENGINE_INFO; // Fully qualified instance block address -typedef struct +typedef struct _inst_block_desc { NvU64 address; // Physical address or IOVA (unshifted) NvU32 aperture; // INST_BLOCK_APERTURE @@ -523,6 +434,7 @@ struct KernelFifo { NvBool bMixedInstmemApertureDefAllowed; NvBool bIsZombieSubctxWarEnabled; NvBool bIsSchedSupported; + NvBool bGuestGenenratesWorkSubmitToken; NvBool bWddmInterleavingPolicyEnabled; NvBool bUserdInSystemMemory; NvBool bUserdMapDmaSupported; @@ -536,7 +448,7 @@ struct KernelFifo { MEMORY_DESCRIPTOR *pBar1VF; MEMORY_DESCRIPTOR *pBar1PrivVF; MEMORY_DESCRIPTOR *pRegVF; - CTX_BUF_POOL_INFO *pRunlistBufPool[62]; + CTX_BUF_POOL_INFO *pRunlistBufPool[63]; MEMORY_DESCRIPTOR ***pppRunlistBufMemDesc; }; @@ -935,19 +847,19 @@ static inline NV_STATUS kfifoConstructEngineList(struct OBJGPU *pGpu, struct Ker #define kfifoConstructEngineList_HAL(pGpu, pKernelFifo) kfifoConstructEngineList(pGpu, pKernelFifo) -NV_STATUS kfifoGetHostDeviceInfoTable_KERNEL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, ENGINE_INFO *pEngineInfo, NvHandle hMigClient); +NV_STATUS kfifoGetHostDeviceInfoTable_KERNEL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, ENGINE_INFO *pEngineInfo, struct Device *pMigDevice); #ifdef __nvoc_kernel_fifo_h_disabled -static inline NV_STATUS kfifoGetHostDeviceInfoTable(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, ENGINE_INFO *pEngineInfo, NvHandle hMigClient) { +static inline NV_STATUS kfifoGetHostDeviceInfoTable(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, ENGINE_INFO *pEngineInfo, struct Device *pMigDevice) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_fifo_h_disabled -#define kfifoGetHostDeviceInfoTable(pGpu, pKernelFifo, pEngineInfo, hMigClient) kfifoGetHostDeviceInfoTable_KERNEL(pGpu, pKernelFifo, pEngineInfo, hMigClient) +#define kfifoGetHostDeviceInfoTable(pGpu, pKernelFifo, pEngineInfo, pMigDevice) kfifoGetHostDeviceInfoTable_KERNEL(pGpu, pKernelFifo, pEngineInfo, pMigDevice) #endif //__nvoc_kernel_fifo_h_disabled -#define kfifoGetHostDeviceInfoTable_HAL(pGpu, pKernelFifo, pEngineInfo, hMigClient) kfifoGetHostDeviceInfoTable(pGpu, pKernelFifo, pEngineInfo, hMigClient) +#define kfifoGetHostDeviceInfoTable_HAL(pGpu, pKernelFifo, pEngineInfo, pMigDevice) kfifoGetHostDeviceInfoTable(pGpu, pKernelFifo, pEngineInfo, pMigDevice) void kfifoGetSubctxType_GV100(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, struct KernelChannel *arg0, NvU32 *arg1); @@ -1279,21 +1191,21 @@ static inline NV_STATUS kfifoGetVChIdForSChId(struct OBJGPU *pGpu, struct Kernel #define kfifoGetVChIdForSChId_HAL(pGpu, pKernelFifo, chId, gfid, engineId, pVChid) kfifoGetVChIdForSChId(pGpu, pKernelFifo, chId, gfid, engineId, pVChid) -static inline NV_STATUS kfifoProgramChIdTable_56cd7a(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 offset, NvU32 numChannels, NvU32 gfid, NvHandle hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList) { +static inline NV_STATUS kfifoProgramChIdTable_56cd7a(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 offset, NvU32 numChannels, NvU32 gfid, struct Device *pMigDevice, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList) { return NV_OK; } #ifdef __nvoc_kernel_fifo_h_disabled -static inline NV_STATUS kfifoProgramChIdTable(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 offset, NvU32 numChannels, NvU32 gfid, NvHandle hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList) { +static inline NV_STATUS kfifoProgramChIdTable(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 offset, NvU32 numChannels, NvU32 gfid, struct Device *pMigDevice, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_fifo_h_disabled -#define kfifoProgramChIdTable(pGpu, pKernelFifo, pChidMgr, offset, numChannels, gfid, hMigClient, engineFifoListNumEntries, pEngineFifoList) kfifoProgramChIdTable_56cd7a(pGpu, pKernelFifo, pChidMgr, offset, numChannels, gfid, hMigClient, engineFifoListNumEntries, pEngineFifoList) +#define kfifoProgramChIdTable(pGpu, pKernelFifo, pChidMgr, offset, numChannels, gfid, pMigDevice, engineFifoListNumEntries, pEngineFifoList) kfifoProgramChIdTable_56cd7a(pGpu, pKernelFifo, pChidMgr, offset, numChannels, gfid, pMigDevice, engineFifoListNumEntries, pEngineFifoList) #endif //__nvoc_kernel_fifo_h_disabled -#define kfifoProgramChIdTable_HAL(pGpu, pKernelFifo, pChidMgr, offset, numChannels, gfid, hMigClient, engineFifoListNumEntries, pEngineFifoList) kfifoProgramChIdTable(pGpu, pKernelFifo, pChidMgr, offset, numChannels, gfid, hMigClient, engineFifoListNumEntries, pEngineFifoList) +#define kfifoProgramChIdTable_HAL(pGpu, pKernelFifo, pChidMgr, offset, numChannels, gfid, pMigDevice, engineFifoListNumEntries, pEngineFifoList) kfifoProgramChIdTable(pGpu, pKernelFifo, pChidMgr, offset, numChannels, gfid, pMigDevice, engineFifoListNumEntries, pEngineFifoList) static inline NV_STATUS kfifoRestoreSchedPolicy_56cd7a(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo) { return NV_OK; @@ -1644,37 +1556,37 @@ static inline NV_STATUS kfifoChidMgrFreeChid(struct OBJGPU *pGpu, struct KernelF #define kfifoChidMgrFreeChid(pGpu, pKernelFifo, pChidMgr, ChID) kfifoChidMgrFreeChid_IMPL(pGpu, pKernelFifo, pChidMgr, ChID) #endif //__nvoc_kernel_fifo_h_disabled -NV_STATUS kfifoChidMgrReserveSystemChids_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 numChannels, NvU32 flags, NvU32 gfid, NvU32 *pChidOffset, NvU32 *pChannelCount, NvHandle hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList); +NV_STATUS kfifoChidMgrReserveSystemChids_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 numChannels, NvU32 flags, NvU32 gfid, NvU32 *pChidOffset, NvU32 *pChannelCount, struct Device *pMigDevice, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList); #ifdef __nvoc_kernel_fifo_h_disabled -static inline NV_STATUS kfifoChidMgrReserveSystemChids(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 numChannels, NvU32 flags, NvU32 gfid, NvU32 *pChidOffset, NvU32 *pChannelCount, NvHandle hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList) { +static inline NV_STATUS kfifoChidMgrReserveSystemChids(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 numChannels, NvU32 flags, NvU32 gfid, NvU32 *pChidOffset, NvU32 *pChannelCount, struct Device *pMigDevice, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_fifo_h_disabled -#define kfifoChidMgrReserveSystemChids(pGpu, pKernelFifo, pChidMgr, numChannels, flags, gfid, pChidOffset, pChannelCount, hMigClient, engineFifoListNumEntries, pEngineFifoList) kfifoChidMgrReserveSystemChids_IMPL(pGpu, pKernelFifo, pChidMgr, numChannels, flags, gfid, pChidOffset, pChannelCount, hMigClient, engineFifoListNumEntries, pEngineFifoList) +#define kfifoChidMgrReserveSystemChids(pGpu, pKernelFifo, pChidMgr, numChannels, flags, gfid, pChidOffset, pChannelCount, pMigDevice, engineFifoListNumEntries, pEngineFifoList) kfifoChidMgrReserveSystemChids_IMPL(pGpu, pKernelFifo, pChidMgr, numChannels, flags, gfid, pChidOffset, pChannelCount, pMigDevice, engineFifoListNumEntries, pEngineFifoList) #endif //__nvoc_kernel_fifo_h_disabled -NV_STATUS kfifoChidMgrFreeSystemChids_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 gfid, NvU32 *pChidOffset, NvU32 *pChannelCount, NvHandle hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList); +NV_STATUS kfifoChidMgrFreeSystemChids_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 gfid, NvU32 *pChidOffset, NvU32 *pChannelCount, struct Device *pMigDevice, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList); #ifdef __nvoc_kernel_fifo_h_disabled -static inline NV_STATUS kfifoChidMgrFreeSystemChids(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 gfid, NvU32 *pChidOffset, NvU32 *pChannelCount, NvHandle hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList) { +static inline NV_STATUS kfifoChidMgrFreeSystemChids(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 gfid, NvU32 *pChidOffset, NvU32 *pChannelCount, struct Device *pMigDevice, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_fifo_h_disabled -#define kfifoChidMgrFreeSystemChids(pGpu, pKernelFifo, pChidMgr, gfid, pChidOffset, pChannelCount, hMigClient, engineFifoListNumEntries, pEngineFifoList) kfifoChidMgrFreeSystemChids_IMPL(pGpu, pKernelFifo, pChidMgr, gfid, pChidOffset, pChannelCount, hMigClient, engineFifoListNumEntries, pEngineFifoList) +#define kfifoChidMgrFreeSystemChids(pGpu, pKernelFifo, pChidMgr, gfid, pChidOffset, pChannelCount, pMigDevice, engineFifoListNumEntries, pEngineFifoList) kfifoChidMgrFreeSystemChids_IMPL(pGpu, pKernelFifo, pChidMgr, gfid, pChidOffset, pChannelCount, pMigDevice, engineFifoListNumEntries, pEngineFifoList) #endif //__nvoc_kernel_fifo_h_disabled -NV_STATUS kfifoSetChidOffset_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 offset, NvU32 numChannels, NvU32 gfid, NvU32 *pChidOffset, NvU32 *pChannelCount, NvHandle hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList); +NV_STATUS kfifoSetChidOffset_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 offset, NvU32 numChannels, NvU32 gfid, NvU32 *pChidOffset, NvU32 *pChannelCount, struct Device *pMigDevice, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList); #ifdef __nvoc_kernel_fifo_h_disabled -static inline NV_STATUS kfifoSetChidOffset(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 offset, NvU32 numChannels, NvU32 gfid, NvU32 *pChidOffset, NvU32 *pChannelCount, NvHandle hMigClient, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList) { +static inline NV_STATUS kfifoSetChidOffset(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 offset, NvU32 numChannels, NvU32 gfid, NvU32 *pChidOffset, NvU32 *pChannelCount, struct Device *pMigDevice, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_fifo_h_disabled -#define kfifoSetChidOffset(pGpu, pKernelFifo, pChidMgr, offset, numChannels, gfid, pChidOffset, pChannelCount, hMigClient, engineFifoListNumEntries, pEngineFifoList) kfifoSetChidOffset_IMPL(pGpu, pKernelFifo, pChidMgr, offset, numChannels, gfid, pChidOffset, pChannelCount, hMigClient, engineFifoListNumEntries, pEngineFifoList) +#define kfifoSetChidOffset(pGpu, pKernelFifo, pChidMgr, offset, numChannels, gfid, pChidOffset, pChannelCount, pMigDevice, engineFifoListNumEntries, pEngineFifoList) kfifoSetChidOffset_IMPL(pGpu, pKernelFifo, pChidMgr, offset, numChannels, gfid, pChidOffset, pChannelCount, pMigDevice, engineFifoListNumEntries, pEngineFifoList) #endif //__nvoc_kernel_fifo_h_disabled NvU32 kfifoChidMgrGetNumChannels_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr); @@ -2072,4 +1984,5 @@ NV_STATUS RmIdleChannels(NvHandle hClient, #ifdef __cplusplus } // extern "C" #endif + #endif // _G_KERNEL_FIFO_NVOC_H_ diff --git a/src/nvidia/generated/g_kernel_graphics_context_nvoc.h b/src/nvidia/generated/g_kernel_graphics_context_nvoc.h index ec32570ccd..bdc0136527 100644 --- a/src/nvidia/generated/g_kernel_graphics_context_nvoc.h +++ b/src/nvidia/generated/g_kernel_graphics_context_nvoc.h @@ -68,6 +68,19 @@ typedef struct KernelChannelGroupApi KernelChannelGroupApi; #endif /* __nvoc_class_id_KernelChannelGroupApi */ +struct KernelSMDebuggerSession; + +#ifndef __NVOC_CLASS_KernelSMDebuggerSession_TYPEDEF__ +#define __NVOC_CLASS_KernelSMDebuggerSession_TYPEDEF__ +typedef struct KernelSMDebuggerSession KernelSMDebuggerSession; +#endif /* __NVOC_CLASS_KernelSMDebuggerSession_TYPEDEF__ */ + +#ifndef __nvoc_class_id_KernelSMDebuggerSession +#define __nvoc_class_id_KernelSMDebuggerSession 0x4adc81 +#endif /* __nvoc_class_id_KernelSMDebuggerSession */ + + +MAKE_LIST(KernelSMDebuggerSessionList, KernelSMDebuggerSession *); typedef struct { @@ -587,6 +600,40 @@ static inline void kgrctxRecordMmuFault(struct OBJGPU *arg0, struct KernelGraphi #define kgrctxRecordMmuFault(arg0, arg1, mmuFaultInfo, mmuFaultAddress, mmuFaultType, mmuFaultAccessType) kgrctxRecordMmuFault_IMPL(arg0, arg1, mmuFaultInfo, mmuFaultAddress, mmuFaultType, mmuFaultAccessType) #endif //__nvoc_kernel_graphics_context_h_disabled +KernelSMDebuggerSessionListIter kgrctxGetDebuggerSessionIter_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1); + +#ifdef __nvoc_kernel_graphics_context_h_disabled +static inline KernelSMDebuggerSessionListIter kgrctxGetDebuggerSessionIter(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1) { + NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); + KernelSMDebuggerSessionListIter ret; + portMemSet(&ret, 0, sizeof(KernelSMDebuggerSessionListIter)); + return ret; +} +#else //__nvoc_kernel_graphics_context_h_disabled +#define kgrctxGetDebuggerSessionIter(arg0, arg1) kgrctxGetDebuggerSessionIter_IMPL(arg0, arg1) +#endif //__nvoc_kernel_graphics_context_h_disabled + +NvBool kgrctxRegisterKernelSMDebuggerSession_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelSMDebuggerSession *arg2); + +#ifdef __nvoc_kernel_graphics_context_h_disabled +static inline NvBool kgrctxRegisterKernelSMDebuggerSession(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelSMDebuggerSession *arg2) { + NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); + return NV_FALSE; +} +#else //__nvoc_kernel_graphics_context_h_disabled +#define kgrctxRegisterKernelSMDebuggerSession(arg0, arg1, arg2) kgrctxRegisterKernelSMDebuggerSession_IMPL(arg0, arg1, arg2) +#endif //__nvoc_kernel_graphics_context_h_disabled + +void kgrctxDeregisterKernelSMDebuggerSession_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelSMDebuggerSession *arg2); + +#ifdef __nvoc_kernel_graphics_context_h_disabled +static inline void kgrctxDeregisterKernelSMDebuggerSession(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelSMDebuggerSession *arg2) { + NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); +} +#else //__nvoc_kernel_graphics_context_h_disabled +#define kgrctxDeregisterKernelSMDebuggerSession(arg0, arg1, arg2) kgrctxDeregisterKernelSMDebuggerSession_IMPL(arg0, arg1, arg2) +#endif //__nvoc_kernel_graphics_context_h_disabled + NvBool kgrctxIsValid_IMPL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelChannel *arg2); #ifdef __nvoc_kernel_graphics_context_h_disabled @@ -971,6 +1018,7 @@ struct KernelGraphicsContextShared { struct RsShared *__nvoc_pbase_RsShared; struct KernelGraphicsContextShared *__nvoc_pbase_KernelGraphicsContextShared; struct KernelGraphicsContextUnicast PRIVATE_FIELD(kernelGraphicsContextUnicast); + KernelSMDebuggerSessionList PRIVATE_FIELD(activeDebuggers); }; #ifndef __NVOC_CLASS_KernelGraphicsContextShared_TYPEDEF__ @@ -1074,4 +1122,5 @@ NV_STATUS kgrctxCtrlHandle #ifdef __cplusplus } // extern "C" #endif + #endif // _G_KERNEL_GRAPHICS_CONTEXT_NVOC_H_ diff --git a/src/nvidia/generated/g_kernel_graphics_manager_nvoc.c b/src/nvidia/generated/g_kernel_graphics_manager_nvoc.c index b9155541e0..655bfe2eb9 100644 --- a/src/nvidia/generated/g_kernel_graphics_manager_nvoc.c +++ b/src/nvidia/generated/g_kernel_graphics_manager_nvoc.c @@ -17,10 +17,10 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJENGSTATE; -void __nvoc_init_KernelGraphicsManager(KernelGraphicsManager*); -void __nvoc_init_funcTable_KernelGraphicsManager(KernelGraphicsManager*); -NV_STATUS __nvoc_ctor_KernelGraphicsManager(KernelGraphicsManager*); -void __nvoc_init_dataField_KernelGraphicsManager(KernelGraphicsManager*); +void __nvoc_init_KernelGraphicsManager(KernelGraphicsManager*, RmHalspecOwner* ); +void __nvoc_init_funcTable_KernelGraphicsManager(KernelGraphicsManager*, RmHalspecOwner* ); +NV_STATUS __nvoc_ctor_KernelGraphicsManager(KernelGraphicsManager*, RmHalspecOwner* ); +void __nvoc_init_dataField_KernelGraphicsManager(KernelGraphicsManager*, RmHalspecOwner* ); void __nvoc_dtor_KernelGraphicsManager(KernelGraphicsManager*); extern const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelGraphicsManager; @@ -66,7 +66,7 @@ const struct NVOC_CLASS_DEF __nvoc_class_def_KernelGraphicsManager = /*pExportInfo=*/ &__nvoc_export_info_KernelGraphicsManager }; -static NV_STATUS __nvoc_thunk_KernelGraphicsManager_engstateConstructEngine(struct OBJGPU *arg0, struct OBJENGSTATE *arg1, ENGDESCRIPTOR arg2) { +static NV_STATUS __nvoc_thunk_KernelGraphicsManager_engstateConstructEngine(OBJGPU *arg0, struct OBJENGSTATE *arg1, ENGDESCRIPTOR arg2) { return kgrmgrConstructEngine(arg0, (struct KernelGraphicsManager *)(((unsigned char *)arg1) - __nvoc_rtti_KernelGraphicsManager_OBJENGSTATE.offset), arg2); } @@ -135,16 +135,21 @@ void __nvoc_dtor_KernelGraphicsManager(KernelGraphicsManager *pThis) { PORT_UNREFERENCED_VARIABLE(pThis); } -void __nvoc_init_dataField_KernelGraphicsManager(KernelGraphicsManager *pThis) { +void __nvoc_init_dataField_KernelGraphicsManager(KernelGraphicsManager *pThis, RmHalspecOwner *pRmhalspecowner) { + ChipHal *chipHal = &pRmhalspecowner->chipHal; + const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); + PORT_UNREFERENCED_VARIABLE(chipHal); + PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); } NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* ); -NV_STATUS __nvoc_ctor_KernelGraphicsManager(KernelGraphicsManager *pThis) { +NV_STATUS __nvoc_ctor_KernelGraphicsManager(KernelGraphicsManager *pThis, RmHalspecOwner *pRmhalspecowner) { NV_STATUS status = NV_OK; status = __nvoc_ctor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); if (status != NV_OK) goto __nvoc_ctor_KernelGraphicsManager_fail_OBJENGSTATE; - __nvoc_init_dataField_KernelGraphicsManager(pThis); + __nvoc_init_dataField_KernelGraphicsManager(pThis, pRmhalspecowner); goto __nvoc_ctor_KernelGraphicsManager_exit; // Success __nvoc_ctor_KernelGraphicsManager_fail_OBJENGSTATE: @@ -153,11 +158,27 @@ NV_STATUS __nvoc_ctor_KernelGraphicsManager(KernelGraphicsManager *pThis) { return status; } -static void __nvoc_init_funcTable_KernelGraphicsManager_1(KernelGraphicsManager *pThis) { +static void __nvoc_init_funcTable_KernelGraphicsManager_1(KernelGraphicsManager *pThis, RmHalspecOwner *pRmhalspecowner) { + ChipHal *chipHal = &pRmhalspecowner->chipHal; + const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); + PORT_UNREFERENCED_VARIABLE(chipHal); + PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); pThis->__kgrmgrConstructEngine__ = &kgrmgrConstructEngine_IMPL; + // Hal function -- kgrmgrGetVeidsFromGpcCount + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + { + pThis->__kgrmgrGetVeidsFromGpcCount__ = &kgrmgrGetVeidsFromGpcCount_GA100; + } + // default + else + { + pThis->__kgrmgrGetVeidsFromGpcCount__ = &kgrmgrGetVeidsFromGpcCount_46f6a7; + } + pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelGraphicsManager_engstateConstructEngine; pThis->__kgrmgrStateLoad__ = &__nvoc_thunk_OBJENGSTATE_kgrmgrStateLoad; @@ -187,23 +208,24 @@ static void __nvoc_init_funcTable_KernelGraphicsManager_1(KernelGraphicsManager pThis->__kgrmgrIsPresent__ = &__nvoc_thunk_OBJENGSTATE_kgrmgrIsPresent; } -void __nvoc_init_funcTable_KernelGraphicsManager(KernelGraphicsManager *pThis) { - __nvoc_init_funcTable_KernelGraphicsManager_1(pThis); +void __nvoc_init_funcTable_KernelGraphicsManager(KernelGraphicsManager *pThis, RmHalspecOwner *pRmhalspecowner) { + __nvoc_init_funcTable_KernelGraphicsManager_1(pThis, pRmhalspecowner); } void __nvoc_init_OBJENGSTATE(OBJENGSTATE*); -void __nvoc_init_KernelGraphicsManager(KernelGraphicsManager *pThis) { +void __nvoc_init_KernelGraphicsManager(KernelGraphicsManager *pThis, RmHalspecOwner *pRmhalspecowner) { pThis->__nvoc_pbase_KernelGraphicsManager = pThis; pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object; pThis->__nvoc_pbase_OBJENGSTATE = &pThis->__nvoc_base_OBJENGSTATE; __nvoc_init_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); - __nvoc_init_funcTable_KernelGraphicsManager(pThis); + __nvoc_init_funcTable_KernelGraphicsManager(pThis, pRmhalspecowner); } NV_STATUS __nvoc_objCreate_KernelGraphicsManager(KernelGraphicsManager **ppThis, Dynamic *pParent, NvU32 createFlags) { NV_STATUS status; Object *pParentObj; KernelGraphicsManager *pThis; + RmHalspecOwner *pRmhalspecowner; status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelGraphicsManager), (void**)&pThis, (void**)ppThis); if (status != NV_OK) @@ -225,8 +247,12 @@ NV_STATUS __nvoc_objCreate_KernelGraphicsManager(KernelGraphicsManager **ppThis, pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.pParent = NULL; } - __nvoc_init_KernelGraphicsManager(pThis); - status = __nvoc_ctor_KernelGraphicsManager(pThis); + if ((pRmhalspecowner = dynamicCast(pParent, RmHalspecOwner)) == NULL) + pRmhalspecowner = objFindAncestorOfType(RmHalspecOwner, pParent); + NV_ASSERT_OR_RETURN(pRmhalspecowner != NULL, NV_ERR_INVALID_ARGUMENT); + + __nvoc_init_KernelGraphicsManager(pThis, pRmhalspecowner); + status = __nvoc_ctor_KernelGraphicsManager(pThis, pRmhalspecowner); if (status != NV_OK) goto __nvoc_objCreate_KernelGraphicsManager_cleanup; *ppThis = pThis; diff --git a/src/nvidia/generated/g_kernel_graphics_manager_nvoc.h b/src/nvidia/generated/g_kernel_graphics_manager_nvoc.h index 28cb4def22..ecbd867018 100644 --- a/src/nvidia/generated/g_kernel_graphics_manager_nvoc.h +++ b/src/nvidia/generated/g_kernel_graphics_manager_nvoc.h @@ -46,6 +46,14 @@ extern "C" { #define KGRMGR_MAX_GPCGRP 4 typedef struct KERNEL_MIG_GPU_INSTANCE KERNEL_MIG_GPU_INSTANCE; +typedef struct GRMGR_LEGACY_KGRAPHICS_STATIC_INFO +{ + NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS floorsweepingMasks; + NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS *pPpcMasks; + NV2080_CTRL_INTERNAL_STATIC_GR_INFO *pGrInfo; + NvBool bInitialized; +} GRMGR_LEGACY_KGRAPHICS_STATIC_INFO; + /*! * KernelGraphicsManager provides means to access KernelGraphics engine with specified index. @@ -56,21 +64,14 @@ typedef struct KERNEL_MIG_GPU_INSTANCE KERNEL_MIG_GPU_INSTANCE; #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif -struct GRMGR_LEGACY_KGRAPHICS_STATIC_INFO { - NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS floorsweepingMasks; - NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS *pPpcMasks; - NV2080_CTRL_INTERNAL_STATIC_GR_INFO *pGrInfo; - NvBool bInitialized; -}; - - struct KernelGraphicsManager { const struct NVOC_RTTI *__nvoc_rtti; struct OBJENGSTATE __nvoc_base_OBJENGSTATE; struct Object *__nvoc_pbase_Object; struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; struct KernelGraphicsManager *__nvoc_pbase_KernelGraphicsManager; - NV_STATUS (*__kgrmgrConstructEngine__)(struct OBJGPU *, struct KernelGraphicsManager *, ENGDESCRIPTOR); + NV_STATUS (*__kgrmgrConstructEngine__)(OBJGPU *, struct KernelGraphicsManager *, ENGDESCRIPTOR); + NV_STATUS (*__kgrmgrGetVeidsFromGpcCount__)(OBJGPU *, struct KernelGraphicsManager *, NvU32, NvU32 *); NV_STATUS (*__kgrmgrStateLoad__)(POBJGPU, struct KernelGraphicsManager *, NvU32); NV_STATUS (*__kgrmgrStateUnload__)(POBJGPU, struct KernelGraphicsManager *, NvU32); NV_STATUS (*__kgrmgrStateInitLocked__)(POBJGPU, struct KernelGraphicsManager *); @@ -84,18 +85,21 @@ struct KernelGraphicsManager { NV_STATUS (*__kgrmgrStatePreInitUnlocked__)(POBJGPU, struct KernelGraphicsManager *); NV_STATUS (*__kgrmgrStatePostLoad__)(POBJGPU, struct KernelGraphicsManager *, NvU32); NvBool (*__kgrmgrIsPresent__)(POBJGPU, struct KernelGraphicsManager *); - struct GRMGR_LEGACY_KGRAPHICS_STATIC_INFO PRIVATE_FIELD(legacyKgraphicsStaticInfo); + GRMGR_LEGACY_KGRAPHICS_STATIC_INFO PRIVATE_FIELD(legacyKgraphicsStaticInfo); + NvU32 PRIVATE_FIELD(fecsCallbackScheduled); NvU64 PRIVATE_FIELD(veidInUseMask); NvU64 PRIVATE_FIELD(grIdxVeidMask)[8]; CTX_BUF_INFO PRIVATE_FIELD(globalCtxBufInfo)[10]; }; + struct KernelGraphicsManager_PRIVATE { const struct NVOC_RTTI *__nvoc_rtti; struct OBJENGSTATE __nvoc_base_OBJENGSTATE; struct Object *__nvoc_pbase_Object; struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; struct KernelGraphicsManager *__nvoc_pbase_KernelGraphicsManager; - NV_STATUS (*__kgrmgrConstructEngine__)(struct OBJGPU *, struct KernelGraphicsManager *, ENGDESCRIPTOR); + NV_STATUS (*__kgrmgrConstructEngine__)(OBJGPU *, struct KernelGraphicsManager *, ENGDESCRIPTOR); + NV_STATUS (*__kgrmgrGetVeidsFromGpcCount__)(OBJGPU *, struct KernelGraphicsManager *, NvU32, NvU32 *); NV_STATUS (*__kgrmgrStateLoad__)(POBJGPU, struct KernelGraphicsManager *, NvU32); NV_STATUS (*__kgrmgrStateUnload__)(POBJGPU, struct KernelGraphicsManager *, NvU32); NV_STATUS (*__kgrmgrStateInitLocked__)(POBJGPU, struct KernelGraphicsManager *); @@ -109,7 +113,8 @@ struct KernelGraphicsManager_PRIVATE { NV_STATUS (*__kgrmgrStatePreInitUnlocked__)(POBJGPU, struct KernelGraphicsManager *); NV_STATUS (*__kgrmgrStatePostLoad__)(POBJGPU, struct KernelGraphicsManager *, NvU32); NvBool (*__kgrmgrIsPresent__)(POBJGPU, struct KernelGraphicsManager *); - struct GRMGR_LEGACY_KGRAPHICS_STATIC_INFO legacyKgraphicsStaticInfo; + GRMGR_LEGACY_KGRAPHICS_STATIC_INFO legacyKgraphicsStaticInfo; + NvU32 fecsCallbackScheduled; NvU64 veidInUseMask; NvU64 grIdxVeidMask[8]; CTX_BUF_INFO globalCtxBufInfo[10]; @@ -146,6 +151,8 @@ NV_STATUS __nvoc_objCreate_KernelGraphicsManager(KernelGraphicsManager**, Dynami __nvoc_objCreate_KernelGraphicsManager((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) #define kgrmgrConstructEngine(arg0, arg1, arg2) kgrmgrConstructEngine_DISPATCH(arg0, arg1, arg2) +#define kgrmgrGetVeidsFromGpcCount(arg0, arg1, gpcCount, pVeidCount) kgrmgrGetVeidsFromGpcCount_DISPATCH(arg0, arg1, gpcCount, pVeidCount) +#define kgrmgrGetVeidsFromGpcCount_HAL(arg0, arg1, gpcCount, pVeidCount) kgrmgrGetVeidsFromGpcCount_DISPATCH(arg0, arg1, gpcCount, pVeidCount) #define kgrmgrStateLoad(pGpu, pEngstate, arg0) kgrmgrStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define kgrmgrStateUnload(pGpu, pEngstate, arg0) kgrmgrStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define kgrmgrStateInitLocked(pGpu, pEngstate) kgrmgrStateInitLocked_DISPATCH(pGpu, pEngstate) @@ -159,12 +166,22 @@ NV_STATUS __nvoc_objCreate_KernelGraphicsManager(KernelGraphicsManager**, Dynami #define kgrmgrStatePreInitUnlocked(pGpu, pEngstate) kgrmgrStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) #define kgrmgrStatePostLoad(pGpu, pEngstate, arg0) kgrmgrStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) #define kgrmgrIsPresent(pGpu, pEngstate) kgrmgrIsPresent_DISPATCH(pGpu, pEngstate) -NV_STATUS kgrmgrConstructEngine_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, ENGDESCRIPTOR arg2); +NV_STATUS kgrmgrConstructEngine_IMPL(OBJGPU *arg0, struct KernelGraphicsManager *arg1, ENGDESCRIPTOR arg2); -static inline NV_STATUS kgrmgrConstructEngine_DISPATCH(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, ENGDESCRIPTOR arg2) { +static inline NV_STATUS kgrmgrConstructEngine_DISPATCH(OBJGPU *arg0, struct KernelGraphicsManager *arg1, ENGDESCRIPTOR arg2) { return arg1->__kgrmgrConstructEngine__(arg0, arg1, arg2); } +NV_STATUS kgrmgrGetVeidsFromGpcCount_GA100(OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 gpcCount, NvU32 *pVeidCount); + +static inline NV_STATUS kgrmgrGetVeidsFromGpcCount_46f6a7(OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 gpcCount, NvU32 *pVeidCount) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kgrmgrGetVeidsFromGpcCount_DISPATCH(OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 gpcCount, NvU32 *pVeidCount) { + return arg1->__kgrmgrGetVeidsFromGpcCount__(arg0, arg1, gpcCount, pVeidCount); +} + static inline NV_STATUS kgrmgrStateLoad_DISPATCH(POBJGPU pGpu, struct KernelGraphicsManager *pEngstate, NvU32 arg0) { return pEngstate->__kgrmgrStateLoad__(pGpu, pEngstate, arg0); } @@ -217,11 +234,31 @@ static inline NvBool kgrmgrIsPresent_DISPATCH(POBJGPU pGpu, struct KernelGraphic return pEngstate->__kgrmgrIsPresent__(pGpu, pEngstate); } -static inline NvU64 kgrmgrGetGrIdxVeidMask(struct OBJGPU *pGpu, struct KernelGraphicsManager *pKernelGraphicsManager, NvU32 grIdx) { +static inline NvU64 kgrmgrGetGrIdxVeidMask(OBJGPU *pGpu, struct KernelGraphicsManager *pKernelGraphicsManager, NvU32 grIdx) { struct KernelGraphicsManager_PRIVATE *pKernelGraphicsManager_PRIVATE = (struct KernelGraphicsManager_PRIVATE *)pKernelGraphicsManager; return pKernelGraphicsManager_PRIVATE->grIdxVeidMask[grIdx]; } +static inline const GRMGR_LEGACY_KGRAPHICS_STATIC_INFO *kgrmgrGetLegacyKGraphicsStaticInfo(OBJGPU *pGpu, struct KernelGraphicsManager *pKernelGraphicsManager) { + struct KernelGraphicsManager_PRIVATE *pKernelGraphicsManager_PRIVATE = (struct KernelGraphicsManager_PRIVATE *)pKernelGraphicsManager; + return &pKernelGraphicsManager_PRIVATE->legacyKgraphicsStaticInfo; +} + +static inline void kgrmgrSetGrIdxVeidMask(OBJGPU *pGpu, struct KernelGraphicsManager *pKernelGraphicsManager, NvU32 grIdx, NvU64 mask) { + struct KernelGraphicsManager_PRIVATE *pKernelGraphicsManager_PRIVATE = (struct KernelGraphicsManager_PRIVATE *)pKernelGraphicsManager; + pKernelGraphicsManager_PRIVATE->grIdxVeidMask[grIdx] = mask; +} + +static inline NvU64 kgrmgrGetVeidInUseMask(OBJGPU *pGpu, struct KernelGraphicsManager *pKernelGraphicsManager) { + struct KernelGraphicsManager_PRIVATE *pKernelGraphicsManager_PRIVATE = (struct KernelGraphicsManager_PRIVATE *)pKernelGraphicsManager; + return pKernelGraphicsManager_PRIVATE->veidInUseMask; +} + +static inline void kgrmgrSetVeidInUseMask(OBJGPU *pGpu, struct KernelGraphicsManager *pKernelGraphicsManager, NvU64 mask) { + struct KernelGraphicsManager_PRIVATE *pKernelGraphicsManager_PRIVATE = (struct KernelGraphicsManager_PRIVATE *)pKernelGraphicsManager; + pKernelGraphicsManager_PRIVATE->veidInUseMask = mask; +} + void kgrmgrGetGrObjectType_IMPL(NvU32 classNum, NvU32 *pObjectType); #define kgrmgrGetGrObjectType(classNum, pObjectType) kgrmgrGetGrObjectType_IMPL(classNum, pObjectType) @@ -240,31 +277,20 @@ void kgrmgrCtrlSetChannelHandle_IMPL(NvHandle hChannel, NV2080_CTRL_GR_ROUTE_INF void kgrmgrDestruct_IMPL(struct KernelGraphicsManager *arg0); #define __nvoc_kgrmgrDestruct(arg0) kgrmgrDestruct_IMPL(arg0) -void kgrmgrSetLegacyKgraphicsStaticInfo_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, struct KernelGraphics *arg2); +void kgrmgrSetLegacyKgraphicsStaticInfo_IMPL(OBJGPU *arg0, struct KernelGraphicsManager *arg1, struct KernelGraphics *arg2); #ifdef __nvoc_kernel_graphics_manager_h_disabled -static inline void kgrmgrSetLegacyKgraphicsStaticInfo(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, struct KernelGraphics *arg2) { +static inline void kgrmgrSetLegacyKgraphicsStaticInfo(OBJGPU *arg0, struct KernelGraphicsManager *arg1, struct KernelGraphics *arg2) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsManager was disabled!"); } #else //__nvoc_kernel_graphics_manager_h_disabled #define kgrmgrSetLegacyKgraphicsStaticInfo(arg0, arg1, arg2) kgrmgrSetLegacyKgraphicsStaticInfo_IMPL(arg0, arg1, arg2) #endif //__nvoc_kernel_graphics_manager_h_disabled -NV_STATUS kgrmgrCtrlRouteKGR_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvHandle hClient, const NV2080_CTRL_GR_ROUTE_INFO *pGrRouteInfo, struct KernelGraphics **ppKernelGraphics); - -#ifdef __nvoc_kernel_graphics_manager_h_disabled -static inline NV_STATUS kgrmgrCtrlRouteKGR(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvHandle hClient, const NV2080_CTRL_GR_ROUTE_INFO *pGrRouteInfo, struct KernelGraphics **ppKernelGraphics) { - NV_ASSERT_FAILED_PRECOMP("KernelGraphicsManager was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kernel_graphics_manager_h_disabled -#define kgrmgrCtrlRouteKGR(arg0, arg1, hClient, pGrRouteInfo, ppKernelGraphics) kgrmgrCtrlRouteKGR_IMPL(arg0, arg1, hClient, pGrRouteInfo, ppKernelGraphics) -#endif //__nvoc_kernel_graphics_manager_h_disabled - -NV_STATUS kgrmgrCtrlRouteKGRWithDevice_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, struct Device *pDevice, const NV2080_CTRL_GR_ROUTE_INFO *pGrRouteInfo, struct KernelGraphics **ppKernelGraphics); +NV_STATUS kgrmgrCtrlRouteKGRWithDevice_IMPL(OBJGPU *arg0, struct KernelGraphicsManager *arg1, Device *pDevice, const NV2080_CTRL_GR_ROUTE_INFO *pGrRouteInfo, struct KernelGraphics **ppKernelGraphics); #ifdef __nvoc_kernel_graphics_manager_h_disabled -static inline NV_STATUS kgrmgrCtrlRouteKGRWithDevice(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, struct Device *pDevice, const NV2080_CTRL_GR_ROUTE_INFO *pGrRouteInfo, struct KernelGraphics **ppKernelGraphics) { +static inline NV_STATUS kgrmgrCtrlRouteKGRWithDevice(OBJGPU *arg0, struct KernelGraphicsManager *arg1, Device *pDevice, const NV2080_CTRL_GR_ROUTE_INFO *pGrRouteInfo, struct KernelGraphics **ppKernelGraphics) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsManager was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -272,10 +298,10 @@ static inline NV_STATUS kgrmgrCtrlRouteKGRWithDevice(struct OBJGPU *arg0, struct #define kgrmgrCtrlRouteKGRWithDevice(arg0, arg1, pDevice, pGrRouteInfo, ppKernelGraphics) kgrmgrCtrlRouteKGRWithDevice_IMPL(arg0, arg1, pDevice, pGrRouteInfo, ppKernelGraphics) #endif //__nvoc_kernel_graphics_manager_h_disabled -NvU32 kgrmgrGetLegacyGpcMask_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1); +NvU32 kgrmgrGetLegacyGpcMask_IMPL(OBJGPU *arg0, struct KernelGraphicsManager *arg1); #ifdef __nvoc_kernel_graphics_manager_h_disabled -static inline NvU32 kgrmgrGetLegacyGpcMask(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1) { +static inline NvU32 kgrmgrGetLegacyGpcMask(OBJGPU *arg0, struct KernelGraphicsManager *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsManager was disabled!"); return 0; } @@ -283,10 +309,10 @@ static inline NvU32 kgrmgrGetLegacyGpcMask(struct OBJGPU *arg0, struct KernelGra #define kgrmgrGetLegacyGpcMask(arg0, arg1) kgrmgrGetLegacyGpcMask_IMPL(arg0, arg1) #endif //__nvoc_kernel_graphics_manager_h_disabled -NvU32 kgrmgrGetLegacyPhysGfxGpcMask_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1); +NvU32 kgrmgrGetLegacyPhysGfxGpcMask_IMPL(OBJGPU *arg0, struct KernelGraphicsManager *arg1); #ifdef __nvoc_kernel_graphics_manager_h_disabled -static inline NvU32 kgrmgrGetLegacyPhysGfxGpcMask(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1) { +static inline NvU32 kgrmgrGetLegacyPhysGfxGpcMask(OBJGPU *arg0, struct KernelGraphicsManager *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsManager was disabled!"); return 0; } @@ -294,10 +320,10 @@ static inline NvU32 kgrmgrGetLegacyPhysGfxGpcMask(struct OBJGPU *arg0, struct Ke #define kgrmgrGetLegacyPhysGfxGpcMask(arg0, arg1) kgrmgrGetLegacyPhysGfxGpcMask_IMPL(arg0, arg1) #endif //__nvoc_kernel_graphics_manager_h_disabled -NvU32 kgrmgrGetLegacyTpcMask_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 gpcId); +NvU32 kgrmgrGetLegacyTpcMask_IMPL(OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 gpcId); #ifdef __nvoc_kernel_graphics_manager_h_disabled -static inline NvU32 kgrmgrGetLegacyTpcMask(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 gpcId) { +static inline NvU32 kgrmgrGetLegacyTpcMask(OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 gpcId) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsManager was disabled!"); return 0; } @@ -305,10 +331,10 @@ static inline NvU32 kgrmgrGetLegacyTpcMask(struct OBJGPU *arg0, struct KernelGra #define kgrmgrGetLegacyTpcMask(arg0, arg1, gpcId) kgrmgrGetLegacyTpcMask_IMPL(arg0, arg1, gpcId) #endif //__nvoc_kernel_graphics_manager_h_disabled -NV_STATUS kgrmgrGetLegacyPpcMask_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 physGpcId, NvU32 *pPpcMask); +NV_STATUS kgrmgrGetLegacyPpcMask_IMPL(OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 physGpcId, NvU32 *pPpcMask); #ifdef __nvoc_kernel_graphics_manager_h_disabled -static inline NV_STATUS kgrmgrGetLegacyPpcMask(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 physGpcId, NvU32 *pPpcMask) { +static inline NV_STATUS kgrmgrGetLegacyPpcMask(OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 physGpcId, NvU32 *pPpcMask) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsManager was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -316,10 +342,10 @@ static inline NV_STATUS kgrmgrGetLegacyPpcMask(struct OBJGPU *arg0, struct Kerne #define kgrmgrGetLegacyPpcMask(arg0, arg1, physGpcId, pPpcMask) kgrmgrGetLegacyPpcMask_IMPL(arg0, arg1, physGpcId, pPpcMask) #endif //__nvoc_kernel_graphics_manager_h_disabled -NvU32 kgrmgrGetLegacyZcullMask_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 physGpcId); +NvU32 kgrmgrGetLegacyZcullMask_IMPL(OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 physGpcId); #ifdef __nvoc_kernel_graphics_manager_h_disabled -static inline NvU32 kgrmgrGetLegacyZcullMask(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 physGpcId) { +static inline NvU32 kgrmgrGetLegacyZcullMask(OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 physGpcId) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsManager was disabled!"); return 0; } @@ -327,10 +353,10 @@ static inline NvU32 kgrmgrGetLegacyZcullMask(struct OBJGPU *arg0, struct KernelG #define kgrmgrGetLegacyZcullMask(arg0, arg1, physGpcId) kgrmgrGetLegacyZcullMask_IMPL(arg0, arg1, physGpcId) #endif //__nvoc_kernel_graphics_manager_h_disabled -NV_STATUS kgrmgrAllocVeidsForGrIdx_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 grIdx, NvU32 veidSpanOffset, NvU32 veidCount, KERNEL_MIG_GPU_INSTANCE *arg2); +NV_STATUS kgrmgrAllocVeidsForGrIdx_IMPL(OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 grIdx, NvU32 veidSpanOffset, NvU32 veidCount, KERNEL_MIG_GPU_INSTANCE *arg2); #ifdef __nvoc_kernel_graphics_manager_h_disabled -static inline NV_STATUS kgrmgrAllocVeidsForGrIdx(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 grIdx, NvU32 veidSpanOffset, NvU32 veidCount, KERNEL_MIG_GPU_INSTANCE *arg2) { +static inline NV_STATUS kgrmgrAllocVeidsForGrIdx(OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 grIdx, NvU32 veidSpanOffset, NvU32 veidCount, KERNEL_MIG_GPU_INSTANCE *arg2) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsManager was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -338,31 +364,31 @@ static inline NV_STATUS kgrmgrAllocVeidsForGrIdx(struct OBJGPU *arg0, struct Ker #define kgrmgrAllocVeidsForGrIdx(arg0, arg1, grIdx, veidSpanOffset, veidCount, arg2) kgrmgrAllocVeidsForGrIdx_IMPL(arg0, arg1, grIdx, veidSpanOffset, veidCount, arg2) #endif //__nvoc_kernel_graphics_manager_h_disabled -void kgrmgrClearVeidsForGrIdx_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 grIdx); +void kgrmgrClearVeidsForGrIdx_IMPL(OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 grIdx); #ifdef __nvoc_kernel_graphics_manager_h_disabled -static inline void kgrmgrClearVeidsForGrIdx(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 grIdx) { +static inline void kgrmgrClearVeidsForGrIdx(OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 grIdx) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsManager was disabled!"); } #else //__nvoc_kernel_graphics_manager_h_disabled #define kgrmgrClearVeidsForGrIdx(arg0, arg1, grIdx) kgrmgrClearVeidsForGrIdx_IMPL(arg0, arg1, grIdx) #endif //__nvoc_kernel_graphics_manager_h_disabled -NV_STATUS kgrmgrGetMaxVeidsPerGpc_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 *pMaxVeidsPerGpc); +NV_STATUS kgrmgrGetVeidStepSize_IMPL(OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 *pVeidStepSize); #ifdef __nvoc_kernel_graphics_manager_h_disabled -static inline NV_STATUS kgrmgrGetMaxVeidsPerGpc(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 *pMaxVeidsPerGpc) { +static inline NV_STATUS kgrmgrGetVeidStepSize(OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 *pVeidStepSize) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsManager was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_graphics_manager_h_disabled -#define kgrmgrGetMaxVeidsPerGpc(arg0, arg1, pMaxVeidsPerGpc) kgrmgrGetMaxVeidsPerGpc_IMPL(arg0, arg1, pMaxVeidsPerGpc) +#define kgrmgrGetVeidStepSize(arg0, arg1, pVeidStepSize) kgrmgrGetVeidStepSize_IMPL(arg0, arg1, pVeidStepSize) #endif //__nvoc_kernel_graphics_manager_h_disabled -NV_STATUS kgrmgrGetVeidBaseForGrIdx_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 grIdx, NvU32 *pVeidStart); +NV_STATUS kgrmgrGetVeidBaseForGrIdx_IMPL(OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 grIdx, NvU32 *pVeidStart); #ifdef __nvoc_kernel_graphics_manager_h_disabled -static inline NV_STATUS kgrmgrGetVeidBaseForGrIdx(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 grIdx, NvU32 *pVeidStart) { +static inline NV_STATUS kgrmgrGetVeidBaseForGrIdx(OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 grIdx, NvU32 *pVeidStart) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsManager was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -370,10 +396,10 @@ static inline NV_STATUS kgrmgrGetVeidBaseForGrIdx(struct OBJGPU *arg0, struct Ke #define kgrmgrGetVeidBaseForGrIdx(arg0, arg1, grIdx, pVeidStart) kgrmgrGetVeidBaseForGrIdx_IMPL(arg0, arg1, grIdx, pVeidStart) #endif //__nvoc_kernel_graphics_manager_h_disabled -NV_STATUS kgrmgrGetGrIdxForVeid_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 veid, NvU32 *pGrIdx); +NV_STATUS kgrmgrGetGrIdxForVeid_IMPL(OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 veid, NvU32 *pGrIdx); #ifdef __nvoc_kernel_graphics_manager_h_disabled -static inline NV_STATUS kgrmgrGetGrIdxForVeid(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 veid, NvU32 *pGrIdx) { +static inline NV_STATUS kgrmgrGetGrIdxForVeid(OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 veid, NvU32 *pGrIdx) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsManager was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -381,10 +407,10 @@ static inline NV_STATUS kgrmgrGetGrIdxForVeid(struct OBJGPU *arg0, struct Kernel #define kgrmgrGetGrIdxForVeid(arg0, arg1, veid, pGrIdx) kgrmgrGetGrIdxForVeid_IMPL(arg0, arg1, veid, pGrIdx) #endif //__nvoc_kernel_graphics_manager_h_disabled -NV_STATUS kgrmgrDiscoverMaxLocalCtxBufInfo_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, struct KernelGraphics *arg2, NvU32 swizzId); +NV_STATUS kgrmgrDiscoverMaxLocalCtxBufInfo_IMPL(OBJGPU *arg0, struct KernelGraphicsManager *arg1, struct KernelGraphics *arg2, NvU32 swizzId); #ifdef __nvoc_kernel_graphics_manager_h_disabled -static inline NV_STATUS kgrmgrDiscoverMaxLocalCtxBufInfo(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, struct KernelGraphics *arg2, NvU32 swizzId) { +static inline NV_STATUS kgrmgrDiscoverMaxLocalCtxBufInfo(OBJGPU *arg0, struct KernelGraphicsManager *arg1, struct KernelGraphics *arg2, NvU32 swizzId) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsManager was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -392,10 +418,10 @@ static inline NV_STATUS kgrmgrDiscoverMaxLocalCtxBufInfo(struct OBJGPU *arg0, st #define kgrmgrDiscoverMaxLocalCtxBufInfo(arg0, arg1, arg2, swizzId) kgrmgrDiscoverMaxLocalCtxBufInfo_IMPL(arg0, arg1, arg2, swizzId) #endif //__nvoc_kernel_graphics_manager_h_disabled -const CTX_BUF_INFO *kgrmgrGetGlobalCtxBufInfo_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, GR_GLOBALCTX_BUFFER arg2); +const CTX_BUF_INFO *kgrmgrGetGlobalCtxBufInfo_IMPL(OBJGPU *arg0, struct KernelGraphicsManager *arg1, GR_GLOBALCTX_BUFFER arg2); #ifdef __nvoc_kernel_graphics_manager_h_disabled -static inline const CTX_BUF_INFO *kgrmgrGetGlobalCtxBufInfo(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, GR_GLOBALCTX_BUFFER arg2) { +static inline const CTX_BUF_INFO *kgrmgrGetGlobalCtxBufInfo(OBJGPU *arg0, struct KernelGraphicsManager *arg1, GR_GLOBALCTX_BUFFER arg2) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsManager was disabled!"); return NULL; } @@ -403,20 +429,20 @@ static inline const CTX_BUF_INFO *kgrmgrGetGlobalCtxBufInfo(struct OBJGPU *arg0, #define kgrmgrGetGlobalCtxBufInfo(arg0, arg1, arg2) kgrmgrGetGlobalCtxBufInfo_IMPL(arg0, arg1, arg2) #endif //__nvoc_kernel_graphics_manager_h_disabled -void kgrmgrSetGlobalCtxBufInfo_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, GR_GLOBALCTX_BUFFER arg2, NvU64 size, NvU64 align, RM_ATTR_PAGE_SIZE attr, NvBool bContiguous); +void kgrmgrSetGlobalCtxBufInfo_IMPL(OBJGPU *arg0, struct KernelGraphicsManager *arg1, GR_GLOBALCTX_BUFFER arg2, NvU64 size, NvU64 align, RM_ATTR_PAGE_SIZE attr, NvBool bContiguous); #ifdef __nvoc_kernel_graphics_manager_h_disabled -static inline void kgrmgrSetGlobalCtxBufInfo(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, GR_GLOBALCTX_BUFFER arg2, NvU64 size, NvU64 align, RM_ATTR_PAGE_SIZE attr, NvBool bContiguous) { +static inline void kgrmgrSetGlobalCtxBufInfo(OBJGPU *arg0, struct KernelGraphicsManager *arg1, GR_GLOBALCTX_BUFFER arg2, NvU64 size, NvU64 align, RM_ATTR_PAGE_SIZE attr, NvBool bContiguous) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsManager was disabled!"); } #else //__nvoc_kernel_graphics_manager_h_disabled #define kgrmgrSetGlobalCtxBufInfo(arg0, arg1, arg2, size, align, attr, bContiguous) kgrmgrSetGlobalCtxBufInfo_IMPL(arg0, arg1, arg2, size, align, attr, bContiguous) #endif //__nvoc_kernel_graphics_manager_h_disabled -NV_STATUS kgrmgrDiscoverMaxGlobalCtxBufSizes_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, struct KernelGraphics *arg2, NvBool bMemoryPartitioningNeeded); +NV_STATUS kgrmgrDiscoverMaxGlobalCtxBufSizes_IMPL(OBJGPU *arg0, struct KernelGraphicsManager *arg1, struct KernelGraphics *arg2, NvBool bMemoryPartitioningNeeded); #ifdef __nvoc_kernel_graphics_manager_h_disabled -static inline NV_STATUS kgrmgrDiscoverMaxGlobalCtxBufSizes(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, struct KernelGraphics *arg2, NvBool bMemoryPartitioningNeeded) { +static inline NV_STATUS kgrmgrDiscoverMaxGlobalCtxBufSizes(OBJGPU *arg0, struct KernelGraphicsManager *arg1, struct KernelGraphics *arg2, NvBool bMemoryPartitioningNeeded) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsManager was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -424,10 +450,10 @@ static inline NV_STATUS kgrmgrDiscoverMaxGlobalCtxBufSizes(struct OBJGPU *arg0, #define kgrmgrDiscoverMaxGlobalCtxBufSizes(arg0, arg1, arg2, bMemoryPartitioningNeeded) kgrmgrDiscoverMaxGlobalCtxBufSizes_IMPL(arg0, arg1, arg2, bMemoryPartitioningNeeded) #endif //__nvoc_kernel_graphics_manager_h_disabled -NvU32 kgrmgrGetLegacyGpcTpcCount_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 gpcId); +NvU32 kgrmgrGetLegacyGpcTpcCount_IMPL(OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 gpcId); #ifdef __nvoc_kernel_graphics_manager_h_disabled -static inline NvU32 kgrmgrGetLegacyGpcTpcCount(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 gpcId) { +static inline NvU32 kgrmgrGetLegacyGpcTpcCount(OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU32 gpcId) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsManager was disabled!"); return 0; } @@ -435,10 +461,10 @@ static inline NvU32 kgrmgrGetLegacyGpcTpcCount(struct OBJGPU *arg0, struct Kerne #define kgrmgrGetLegacyGpcTpcCount(arg0, arg1, gpcId) kgrmgrGetLegacyGpcTpcCount_IMPL(arg0, arg1, gpcId) #endif //__nvoc_kernel_graphics_manager_h_disabled -NV_STATUS kgrmgrCheckVeidsRequest_IMPL(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU64 *pInUseMask, NvU32 veidCount, NvU32 *pSpanStart, KERNEL_MIG_GPU_INSTANCE *arg2); +NV_STATUS kgrmgrCheckVeidsRequest_IMPL(OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU64 *pInUseMask, NvU32 veidCount, NvU32 *pSpanStart, KERNEL_MIG_GPU_INSTANCE *arg2); #ifdef __nvoc_kernel_graphics_manager_h_disabled -static inline NV_STATUS kgrmgrCheckVeidsRequest(struct OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU64 *pInUseMask, NvU32 veidCount, NvU32 *pSpanStart, KERNEL_MIG_GPU_INSTANCE *arg2) { +static inline NV_STATUS kgrmgrCheckVeidsRequest(OBJGPU *arg0, struct KernelGraphicsManager *arg1, NvU64 *pInUseMask, NvU32 veidCount, NvU32 *pSpanStart, KERNEL_MIG_GPU_INSTANCE *arg2) { NV_ASSERT_FAILED_PRECOMP("KernelGraphicsManager was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -446,6 +472,27 @@ static inline NV_STATUS kgrmgrCheckVeidsRequest(struct OBJGPU *arg0, struct Kern #define kgrmgrCheckVeidsRequest(arg0, arg1, pInUseMask, veidCount, pSpanStart, arg2) kgrmgrCheckVeidsRequest_IMPL(arg0, arg1, pInUseMask, veidCount, pSpanStart, arg2) #endif //__nvoc_kernel_graphics_manager_h_disabled +NvBool kgrmgrSignalFecsCallbackScheduled_IMPL(OBJGPU *pGpu, struct KernelGraphicsManager *pKernelGraphicsManager); + +#ifdef __nvoc_kernel_graphics_manager_h_disabled +static inline NvBool kgrmgrSignalFecsCallbackScheduled(OBJGPU *pGpu, struct KernelGraphicsManager *pKernelGraphicsManager) { + NV_ASSERT_FAILED_PRECOMP("KernelGraphicsManager was disabled!"); + return NV_FALSE; +} +#else //__nvoc_kernel_graphics_manager_h_disabled +#define kgrmgrSignalFecsCallbackScheduled(pGpu, pKernelGraphicsManager) kgrmgrSignalFecsCallbackScheduled_IMPL(pGpu, pKernelGraphicsManager) +#endif //__nvoc_kernel_graphics_manager_h_disabled + +void kgrmgrClearFecsCallbackScheduled_IMPL(OBJGPU *pGpu, struct KernelGraphicsManager *pKernelGraphicsManager); + +#ifdef __nvoc_kernel_graphics_manager_h_disabled +static inline void kgrmgrClearFecsCallbackScheduled(OBJGPU *pGpu, struct KernelGraphicsManager *pKernelGraphicsManager) { + NV_ASSERT_FAILED_PRECOMP("KernelGraphicsManager was disabled!"); +} +#else //__nvoc_kernel_graphics_manager_h_disabled +#define kgrmgrClearFecsCallbackScheduled(pGpu, pKernelGraphicsManager) kgrmgrClearFecsCallbackScheduled_IMPL(pGpu, pKernelGraphicsManager) +#endif //__nvoc_kernel_graphics_manager_h_disabled + #undef PRIVATE_FIELD @@ -455,4 +502,5 @@ static inline NV_STATUS kgrmgrCheckVeidsRequest(struct OBJGPU *arg0, struct Kern #ifdef __cplusplus } // extern "C" #endif + #endif // _G_KERNEL_GRAPHICS_MANAGER_NVOC_H_ diff --git a/src/nvidia/generated/g_kernel_graphics_nvoc.c b/src/nvidia/generated/g_kernel_graphics_nvoc.c index 820a450efb..09e399826c 100644 --- a/src/nvidia/generated/g_kernel_graphics_nvoc.c +++ b/src/nvidia/generated/g_kernel_graphics_nvoc.c @@ -107,7 +107,7 @@ static NV_STATUS __nvoc_thunk_KernelGraphics_engstateStatePostLoad(OBJGPU *arg0, return kgraphicsStatePostLoad(arg0, (struct KernelGraphics *)(((unsigned char *)arg1) - __nvoc_rtti_KernelGraphics_OBJENGSTATE.offset), flags); } -static void __nvoc_thunk_KernelGraphics_intrservRegisterIntrService(OBJGPU *arg0, struct IntrService *arg1, IntrServiceRecord arg2[167]) { +static void __nvoc_thunk_KernelGraphics_intrservRegisterIntrService(OBJGPU *arg0, struct IntrService *arg1, IntrServiceRecord arg2[168]) { kgraphicsRegisterIntrService(arg0, (struct KernelGraphics *)(((unsigned char *)arg1) - __nvoc_rtti_KernelGraphics_IntrService.offset), arg2); } diff --git a/src/nvidia/generated/g_kernel_graphics_nvoc.h b/src/nvidia/generated/g_kernel_graphics_nvoc.h index d1f12b6215..43f32d5853 100644 --- a/src/nvidia/generated/g_kernel_graphics_nvoc.h +++ b/src/nvidia/generated/g_kernel_graphics_nvoc.h @@ -188,12 +188,14 @@ struct KernelGraphics { NvU32 PRIVATE_FIELD(instance); KGRAPHICS_PRIVATE_DATA *PRIVATE_FIELD(pPrivate); NvBool PRIVATE_FIELD(bCollectingDeferredStaticData); + NvBool PRIVATE_FIELD(bBug4162646War); KGRAPHICS_FECS_TRACE_INFO *PRIVATE_FIELD(pFecsTraceInfo); struct KGRAPHICS_GLOBAL_CTX_BUFFERS_INFO PRIVATE_FIELD(globalCtxBuffersInfo); struct CTX_BUF_POOL_INFO *PRIVATE_FIELD(pCtxBufPool); CTX_BUF_INFO PRIVATE_FIELD(maxCtxBufSize)[9]; GR_BUFFER_ATTR PRIVATE_FIELD(ctxAttr)[9]; }; + struct KernelGraphics_PRIVATE { const struct NVOC_RTTI *__nvoc_rtti; struct OBJENGSTATE __nvoc_base_OBJENGSTATE; @@ -232,6 +234,7 @@ struct KernelGraphics_PRIVATE { NvU32 instance; KGRAPHICS_PRIVATE_DATA *pPrivate; NvBool bCollectingDeferredStaticData; + NvBool bBug4162646War; KGRAPHICS_FECS_TRACE_INFO *pFecsTraceInfo; struct KGRAPHICS_GLOBAL_CTX_BUFFERS_INFO globalCtxBuffersInfo; struct CTX_BUF_POOL_INFO *pCtxBufPool; @@ -451,9 +454,9 @@ static inline NV_STATUS kgraphicsStatePostLoad_DISPATCH(OBJGPU *arg0, struct Ker return arg1->__kgraphicsStatePostLoad__(arg0, arg1, flags); } -void kgraphicsRegisterIntrService_IMPL(OBJGPU *arg0, struct KernelGraphics *arg1, IntrServiceRecord arg2[167]); +void kgraphicsRegisterIntrService_IMPL(OBJGPU *arg0, struct KernelGraphics *arg1, IntrServiceRecord arg2[168]); -static inline void kgraphicsRegisterIntrService_DISPATCH(OBJGPU *arg0, struct KernelGraphics *arg1, IntrServiceRecord arg2[167]) { +static inline void kgraphicsRegisterIntrService_DISPATCH(OBJGPU *arg0, struct KernelGraphics *arg1, IntrServiceRecord arg2[168]) { arg1->__kgraphicsRegisterIntrService__(arg0, arg1, arg2); } @@ -821,4 +824,5 @@ static inline NV_STATUS kgraphicsGetCaps(OBJGPU *arg0, struct KernelGraphics *ar #ifdef __cplusplus } // extern "C" #endif + #endif // _G_KERNEL_GRAPHICS_NVOC_H_ diff --git a/src/nvidia/generated/g_kernel_graphics_object_nvoc.h b/src/nvidia/generated/g_kernel_graphics_object_nvoc.h index 714e80d530..0a4cba287f 100644 --- a/src/nvidia/generated/g_kernel_graphics_object_nvoc.h +++ b/src/nvidia/generated/g_kernel_graphics_object_nvoc.h @@ -41,20 +41,6 @@ extern "C" { #include "utils/nv_enum.h" #include "kernel/gpu/gr/kernel_graphics_context.h" -struct KernelSMDebuggerSession; - -#ifndef __NVOC_CLASS_KernelSMDebuggerSession_TYPEDEF__ -#define __NVOC_CLASS_KernelSMDebuggerSession_TYPEDEF__ -typedef struct KernelSMDebuggerSession KernelSMDebuggerSession; -#endif /* __NVOC_CLASS_KernelSMDebuggerSession_TYPEDEF__ */ - -#ifndef __nvoc_class_id_KernelSMDebuggerSession -#define __nvoc_class_id_KernelSMDebuggerSession 0x4adc81 -#endif /* __nvoc_class_id_KernelSMDebuggerSession */ - - -MAKE_LIST(KernelSMDebuggerSessionList, KernelSMDebuggerSession *); - /*! * RM internal class representing 3D and compute graphics classes, e.g.: _A, * _COMPUTE_A, etc @@ -109,7 +95,54 @@ struct KernelGraphicsObject { NV_STATUS (*__kgrobjMap__)(struct KernelGraphicsObject *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NV_STATUS (*__kgrobjGetOrAllocNotifShare__)(struct KernelGraphicsObject *, NvHandle, NvHandle, struct NotifShare **); MEMORY_DESCRIPTOR *PRIVATE_FIELD(pMmioMemDesc); - KernelSMDebuggerSessionList activeDebuggers; + struct KernelGraphicsContext *PRIVATE_FIELD(pKernelGraphicsContext); +}; + +struct KernelGraphicsObject_PRIVATE { + const struct NVOC_RTTI *__nvoc_rtti; + struct ChannelDescendant __nvoc_base_ChannelDescendant; + struct Object *__nvoc_pbase_Object; + struct RsResource *__nvoc_pbase_RsResource; + struct RmResourceCommon *__nvoc_pbase_RmResourceCommon; + struct RmResource *__nvoc_pbase_RmResource; + struct GpuResource *__nvoc_pbase_GpuResource; + struct INotifier *__nvoc_pbase_INotifier; + struct Notifier *__nvoc_pbase_Notifier; + struct ChannelDescendant *__nvoc_pbase_ChannelDescendant; + struct KernelGraphicsObject *__nvoc_pbase_KernelGraphicsObject; + NV_STATUS (*__kgrobjGetMemInterMapParams__)(struct KernelGraphicsObject *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__kgrobjCheckMemInterUnmap__)(struct KernelGraphicsObject *, NvBool); + NvBool (*__kgrobjShareCallback__)(struct KernelGraphicsObject *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NvBool (*__kgrobjAccessCallback__)(struct KernelGraphicsObject *, struct RsClient *, void *, RsAccessRight); + NV_STATUS (*__kgrobjMapTo__)(struct KernelGraphicsObject *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__kgrobjGetMapAddrSpace__)(struct KernelGraphicsObject *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + void (*__kgrobjSetNotificationShare__)(struct KernelGraphicsObject *, struct NotifShare *); + NvU32 (*__kgrobjGetRefCount__)(struct KernelGraphicsObject *); + void (*__kgrobjAddAdditionalDependants__)(struct RsClient *, struct KernelGraphicsObject *, RsResourceRef *); + NV_STATUS (*__kgrobjControl_Prologue__)(struct KernelGraphicsObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__kgrobjGetRegBaseOffsetAndSize__)(struct KernelGraphicsObject *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__kgrobjInternalControlForward__)(struct KernelGraphicsObject *, NvU32, void *, NvU32); + NV_STATUS (*__kgrobjUnmapFrom__)(struct KernelGraphicsObject *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__kgrobjControl_Epilogue__)(struct KernelGraphicsObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__kgrobjControlLookup__)(struct KernelGraphicsObject *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NV_STATUS (*__kgrobjGetSwMethods__)(struct KernelGraphicsObject *, const METHOD **, NvU32 *); + NvHandle (*__kgrobjGetInternalObjectHandle__)(struct KernelGraphicsObject *); + NV_STATUS (*__kgrobjControl__)(struct KernelGraphicsObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__kgrobjUnmap__)(struct KernelGraphicsObject *, struct CALL_CONTEXT *, struct RsCpuMapping *); + NV_STATUS (*__kgrobjGetMemoryMappingDescriptor__)(struct KernelGraphicsObject *, struct MEMORY_DESCRIPTOR **); + NvBool (*__kgrobjIsSwMethodStalling__)(struct KernelGraphicsObject *, NvU32); + NV_STATUS (*__kgrobjControlFilter__)(struct KernelGraphicsObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__kgrobjUnregisterEvent__)(struct KernelGraphicsObject *, NvHandle, NvHandle, NvHandle, NvHandle); + NV_STATUS (*__kgrobjControlSerialization_Prologue__)(struct KernelGraphicsObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__kgrobjCanCopy__)(struct KernelGraphicsObject *); + void (*__kgrobjPreDestruct__)(struct KernelGraphicsObject *); + NV_STATUS (*__kgrobjIsDuplicate__)(struct KernelGraphicsObject *, NvHandle, NvBool *); + void (*__kgrobjControlSerialization_Epilogue__)(struct KernelGraphicsObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + PEVENTNOTIFICATION *(*__kgrobjGetNotificationListPtr__)(struct KernelGraphicsObject *); + struct NotifShare *(*__kgrobjGetNotificationShare__)(struct KernelGraphicsObject *); + NV_STATUS (*__kgrobjMap__)(struct KernelGraphicsObject *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); + NV_STATUS (*__kgrobjGetOrAllocNotifShare__)(struct KernelGraphicsObject *, NvHandle, NvHandle, struct NotifShare **); + MEMORY_DESCRIPTOR *pMmioMemDesc; struct KernelGraphicsContext *pKernelGraphicsContext; }; @@ -357,6 +390,11 @@ static inline NV_STATUS kgrobjGetOrAllocNotifShare_DISPATCH(struct KernelGraphic return pNotifier->__kgrobjGetOrAllocNotifShare__(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare); } +static inline struct KernelGraphicsContext *kgrobjGetKernelGraphicsContext(struct OBJGPU *pGpu, struct KernelGraphicsObject *pKernelGraphicsObject) { + struct KernelGraphicsObject_PRIVATE *pKernelGraphicsObject_PRIVATE = (struct KernelGraphicsObject_PRIVATE *)pKernelGraphicsObject; + return pKernelGraphicsObject_PRIVATE->pKernelGraphicsContext; +} + NV_STATUS kgrobjConstruct_IMPL(struct KernelGraphicsObject *arg_pKernelGraphicsObject, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); #define __nvoc_kgrobjConstruct(arg_pKernelGraphicsObject, arg_pCallContext, arg_pParams) kgrobjConstruct_IMPL(arg_pKernelGraphicsObject, arg_pCallContext, arg_pParams) @@ -382,4 +420,5 @@ static inline NV_STATUS kgrobjPromoteContext(struct OBJGPU *arg0, struct KernelG #ifdef __cplusplus } // extern "C" #endif + #endif // _G_KERNEL_GRAPHICS_OBJECT_NVOC_H_ diff --git a/src/nvidia/generated/g_kernel_gsp_nvoc.c b/src/nvidia/generated/g_kernel_gsp_nvoc.c index b8573c5000..b5721a4048 100644 --- a/src/nvidia/generated/g_kernel_gsp_nvoc.c +++ b/src/nvidia/generated/g_kernel_gsp_nvoc.c @@ -106,7 +106,7 @@ static NV_STATUS __nvoc_thunk_KernelGsp_engstateConstructEngine(struct OBJGPU *p return kgspConstructEngine(pGpu, (struct KernelGsp *)(((unsigned char *)pKernelGsp) - __nvoc_rtti_KernelGsp_OBJENGSTATE.offset), arg0); } -static void __nvoc_thunk_KernelGsp_intrservRegisterIntrService(struct OBJGPU *pGpu, struct IntrService *pKernelGsp, IntrServiceRecord pRecords[167]) { +static void __nvoc_thunk_KernelGsp_intrservRegisterIntrService(struct OBJGPU *pGpu, struct IntrService *pKernelGsp, IntrServiceRecord pRecords[168]) { kgspRegisterIntrService(pGpu, (struct KernelGsp *)(((unsigned char *)pKernelGsp) - __nvoc_rtti_KernelGsp_IntrService.offset), pRecords); } @@ -302,17 +302,15 @@ void __nvoc_init_dataField_KernelGsp(KernelGsp *pThis, RmHalspecOwner *pRmhalspe pThis->fwHeapParamBaseSize = (14 << 20); } - // Hal field -- fwHeapParamOsCarveoutSize - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + // Hal field -- bBootGspRmWithBoostClocks + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ - { - pThis->fwHeapParamOsCarveoutSize = (0 << 20); - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ - { - pThis->fwHeapParamOsCarveoutSize = (20 << 20); - } + pThis->bBootGspRmWithBoostClocks = ((NvBool)(0 == 0)); + } + // default + else + { + pThis->bBootGspRmWithBoostClocks = ((NvBool)(0 != 0)); } } @@ -724,7 +722,7 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * } else { - pThis->__kgspGetMinWprHeapSizeMB__ = &kgspGetMinWprHeapSizeMB_907c84; + pThis->__kgspGetMinWprHeapSizeMB__ = &kgspGetMinWprHeapSizeMB_cc88c3; } // Hal function -- kgspGetMaxWprHeapSizeMB @@ -734,7 +732,17 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * } else { - pThis->__kgspGetMaxWprHeapSizeMB__ = &kgspGetMaxWprHeapSizeMB_5839e2; + pThis->__kgspGetMaxWprHeapSizeMB__ = &kgspGetMaxWprHeapSizeMB_55728f; + } + + // Hal function -- kgspGetFwHeapParamOsCarveoutSize + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + { + pThis->__kgspGetFwHeapParamOsCarveoutSize__ = &kgspGetFwHeapParamOsCarveoutSize_397f70; + } + else + { + pThis->__kgspGetFwHeapParamOsCarveoutSize__ = &kgspGetFwHeapParamOsCarveoutSize_4b5307; } // Hal function -- kgspInitVgpuPartitionLogging diff --git a/src/nvidia/generated/g_kernel_gsp_nvoc.h b/src/nvidia/generated/g_kernel_gsp_nvoc.h index 9f487bb004..a7e37cbbcd 100644 --- a/src/nvidia/generated/g_kernel_gsp_nvoc.h +++ b/src/nvidia/generated/g_kernel_gsp_nvoc.h @@ -292,6 +292,7 @@ struct KernelGsp { const BINDATA_ARCHIVE *(*__kgspGetBinArchiveBooterUnloadUcode__)(struct KernelGsp *); NvU64 (*__kgspGetMinWprHeapSizeMB__)(struct OBJGPU *, struct KernelGsp *); NvU64 (*__kgspGetMaxWprHeapSizeMB__)(struct OBJGPU *, struct KernelGsp *); + NvU32 (*__kgspGetFwHeapParamOsCarveoutSize__)(struct OBJGPU *, struct KernelGsp *); NV_STATUS (*__kgspInitVgpuPartitionLogging__)(struct OBJGPU *, struct KernelGsp *, NvU32, NvU64, NvU64, NvU64, NvU64); NV_STATUS (*__kgspFreeVgpuPartitionLogging__)(struct OBJGPU *, struct KernelGsp *, NvU32); const char *(*__kgspGetSignatureSectionNamePrefix__)(struct OBJGPU *, struct KernelGsp *); @@ -380,7 +381,7 @@ struct KernelGsp { NvBool bPartitionedFmc; NvBool bScrubberUcodeSupported; NvU32 fwHeapParamBaseSize; - NvU32 fwHeapParamOsCarveoutSize; + NvBool bBootGspRmWithBoostClocks; }; #ifndef __NVOC_CLASS_KernelGsp_TYPEDEF__ @@ -480,6 +481,8 @@ NV_STATUS __nvoc_objCreate_KernelGsp(KernelGsp**, Dynamic*, NvU32); #define kgspGetMinWprHeapSizeMB_HAL(pGpu, pKernelGsp) kgspGetMinWprHeapSizeMB_DISPATCH(pGpu, pKernelGsp) #define kgspGetMaxWprHeapSizeMB(pGpu, pKernelGsp) kgspGetMaxWprHeapSizeMB_DISPATCH(pGpu, pKernelGsp) #define kgspGetMaxWprHeapSizeMB_HAL(pGpu, pKernelGsp) kgspGetMaxWprHeapSizeMB_DISPATCH(pGpu, pKernelGsp) +#define kgspGetFwHeapParamOsCarveoutSize(pGpu, pKernelGsp) kgspGetFwHeapParamOsCarveoutSize_DISPATCH(pGpu, pKernelGsp) +#define kgspGetFwHeapParamOsCarveoutSize_HAL(pGpu, pKernelGsp) kgspGetFwHeapParamOsCarveoutSize_DISPATCH(pGpu, pKernelGsp) #define kgspInitVgpuPartitionLogging(pGpu, pKernelGsp, gfid, initTaskLogBUffOffset, initTaskLogBUffSize, vgpuTaskLogBUffOffset, vgpuTaskLogBuffSize) kgspInitVgpuPartitionLogging_DISPATCH(pGpu, pKernelGsp, gfid, initTaskLogBUffOffset, initTaskLogBUffSize, vgpuTaskLogBUffOffset, vgpuTaskLogBuffSize) #define kgspInitVgpuPartitionLogging_HAL(pGpu, pKernelGsp, gfid, initTaskLogBUffOffset, initTaskLogBUffSize, vgpuTaskLogBUffOffset, vgpuTaskLogBuffSize) kgspInitVgpuPartitionLogging_DISPATCH(pGpu, pKernelGsp, gfid, initTaskLogBUffOffset, initTaskLogBUffSize, vgpuTaskLogBUffOffset, vgpuTaskLogBuffSize) #define kgspFreeVgpuPartitionLogging(pGpu, pKernelGsp, gfid) kgspFreeVgpuPartitionLogging_DISPATCH(pGpu, pKernelGsp, gfid) @@ -634,9 +637,9 @@ static inline NV_STATUS kgspConstructEngine_DISPATCH(struct OBJGPU *pGpu, struct return pKernelGsp->__kgspConstructEngine__(pGpu, pKernelGsp, arg0); } -void kgspRegisterIntrService_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, IntrServiceRecord pRecords[167]); +void kgspRegisterIntrService_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, IntrServiceRecord pRecords[168]); -static inline void kgspRegisterIntrService_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, IntrServiceRecord pRecords[167]) { +static inline void kgspRegisterIntrService_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, IntrServiceRecord pRecords[168]) { pKernelGsp->__kgspRegisterIntrService__(pGpu, pKernelGsp, pRecords); } @@ -958,8 +961,8 @@ static inline NvU64 kgspGetMinWprHeapSizeMB_7185bf(struct OBJGPU *pGpu, struct K return (64U); } -static inline NvU64 kgspGetMinWprHeapSizeMB_907c84(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - return pGpu->bVgpuGspPluginOffloadEnabled ? (549U) : (84U); +static inline NvU64 kgspGetMinWprHeapSizeMB_cc88c3(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return pGpu->bVgpuGspPluginOffloadEnabled ? (565U) : (86U); } static inline NvU64 kgspGetMinWprHeapSizeMB_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { @@ -970,14 +973,26 @@ static inline NvU64 kgspGetMaxWprHeapSizeMB_ad4e6a(struct OBJGPU *pGpu, struct K return (256U); } -static inline NvU64 kgspGetMaxWprHeapSizeMB_5839e2(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - return pGpu->bVgpuGspPluginOffloadEnabled ? (1024U) : (276U); +static inline NvU64 kgspGetMaxWprHeapSizeMB_55728f(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return pGpu->bVgpuGspPluginOffloadEnabled ? (1040U) : (278U); } static inline NvU64 kgspGetMaxWprHeapSizeMB_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { return pKernelGsp->__kgspGetMaxWprHeapSizeMB__(pGpu, pKernelGsp); } +static inline NvU32 kgspGetFwHeapParamOsCarveoutSize_397f70(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return (0 << 20); +} + +static inline NvU32 kgspGetFwHeapParamOsCarveoutSize_4b5307(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return pGpu->bVgpuGspPluginOffloadEnabled ? (36 << 20) : (22 << 20); +} + +static inline NvU32 kgspGetFwHeapParamOsCarveoutSize_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return pKernelGsp->__kgspGetFwHeapParamOsCarveoutSize__(pGpu, pKernelGsp); +} + static inline NV_STATUS kgspInitVgpuPartitionLogging_395e98(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 gfid, NvU64 initTaskLogBUffOffset, NvU64 initTaskLogBUffSize, NvU64 vgpuTaskLogBUffOffset, NvU64 vgpuTaskLogBuffSize) { return NV_ERR_NOT_SUPPORTED; } @@ -1344,4 +1359,5 @@ void kgspFreeFlcnUcode(KernelGspFlcnUcode *pFlcnUcode); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_KERNEL_GSP_NVOC_H_ diff --git a/src/nvidia/generated/g_kernel_head_nvoc.c b/src/nvidia/generated/g_kernel_head_nvoc.c index dbb37ed281..873e0791b7 100644 --- a/src/nvidia/generated/g_kernel_head_nvoc.c +++ b/src/nvidia/generated/g_kernel_head_nvoc.c @@ -198,6 +198,16 @@ static void __nvoc_init_funcTable_KernelHead_1(KernelHead *pThis, RmHalspecOwner { pThis->__kheadReadPendingVblank__ = &kheadReadPendingVblank_108313; } + + // Hal function -- kheadGetLoadVCounter + if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00020000UL) )) /* DispIpHal: DISPv0000 */ + { + pThis->__kheadGetLoadVCounter__ = &kheadGetLoadVCounter_4a4dee; + } + else + { + pThis->__kheadGetLoadVCounter__ = &kheadGetLoadVCounter_v03_00; + } } void __nvoc_init_funcTable_KernelHead(KernelHead *pThis, RmHalspecOwner *pRmhalspecowner) { diff --git a/src/nvidia/generated/g_kernel_head_nvoc.h b/src/nvidia/generated/g_kernel_head_nvoc.h index ebb1e67350..793157a1cd 100644 --- a/src/nvidia/generated/g_kernel_head_nvoc.h +++ b/src/nvidia/generated/g_kernel_head_nvoc.h @@ -77,6 +77,7 @@ struct KernelHead { void (*__kheadProcessVblankCallbacks__)(struct OBJGPU *, struct KernelHead *, NvU32); void (*__kheadResetPendingVblank__)(struct OBJGPU *, struct KernelHead *, THREAD_STATE_NODE *); NvBool (*__kheadReadPendingVblank__)(struct OBJGPU *, struct KernelHead *, NvU32 *, THREAD_STATE_NODE *); + NvU32 (*__kheadGetLoadVCounter__)(struct OBJGPU *, struct KernelHead *); struct __nvoc_inner_struc_KernelHead_1__ Vblank; NvU32 PublicId; }; @@ -121,6 +122,8 @@ NV_STATUS __nvoc_objCreate_KernelHead(KernelHead**, Dynamic*, NvU32); #define kheadResetPendingVblank_HAL(pGpu, pKernelHead, arg0) kheadResetPendingVblank_DISPATCH(pGpu, pKernelHead, arg0) #define kheadReadPendingVblank(pGpu, pKernelHead, pCachedIntr, pThreadState) kheadReadPendingVblank_DISPATCH(pGpu, pKernelHead, pCachedIntr, pThreadState) #define kheadReadPendingVblank_HAL(pGpu, pKernelHead, pCachedIntr, pThreadState) kheadReadPendingVblank_DISPATCH(pGpu, pKernelHead, pCachedIntr, pThreadState) +#define kheadGetLoadVCounter(pGpu, pKernelHead) kheadGetLoadVCounter_DISPATCH(pGpu, pKernelHead) +#define kheadGetLoadVCounter_HAL(pGpu, pKernelHead) kheadGetLoadVCounter_DISPATCH(pGpu, pKernelHead) NvU32 kheadGetVblankTotalCounter_IMPL(struct KernelHead *pKernelHead); @@ -293,6 +296,16 @@ static inline NvBool kheadReadPendingVblank_DISPATCH(struct OBJGPU *pGpu, struct return pKernelHead->__kheadReadPendingVblank__(pGpu, pKernelHead, pCachedIntr, pThreadState); } +NvU32 kheadGetLoadVCounter_v03_00(struct OBJGPU *pGpu, struct KernelHead *pKernelHead); + +static inline NvU32 kheadGetLoadVCounter_4a4dee(struct OBJGPU *pGpu, struct KernelHead *pKernelHead) { + return 0; +} + +static inline NvU32 kheadGetLoadVCounter_DISPATCH(struct OBJGPU *pGpu, struct KernelHead *pKernelHead) { + return pKernelHead->__kheadGetLoadVCounter__(pGpu, pKernelHead); +} + NV_STATUS kheadConstruct_IMPL(struct KernelHead *arg_pKernelHead); #define __nvoc_kheadConstruct(arg_pKernelHead) kheadConstruct_IMPL(arg_pKernelHead) @@ -356,4 +369,5 @@ static inline void kheadWriteVblankIntrState(struct OBJGPU *pGpu, struct KernelH #ifdef __cplusplus } // extern "C" #endif + #endif // _G_KERNEL_HEAD_NVOC_H_ diff --git a/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.c b/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.c index f8d230b209..0f9481e31e 100644 --- a/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.c +++ b/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.c @@ -295,7 +295,7 @@ static NV_STATUS __nvoc_thunk_RsResource_kernelhostvgpudeviceapiMapTo(struct Ker return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_GpuResource_kernelhostvgpudeviceapiGetMapAddrSpace(struct KernelHostVgpuDeviceApi *pGpuResource, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { +static NV_STATUS __nvoc_thunk_GpuResource_kernelhostvgpudeviceapiGetMapAddrSpace(struct KernelHostVgpuDeviceApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); } @@ -339,11 +339,11 @@ static NvHandle __nvoc_thunk_GpuResource_kernelhostvgpudeviceapiGetInternalObjec return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_GpuResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_kernelhostvgpudeviceapiControl(struct KernelHostVgpuDeviceApi *pGpuResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { +static NV_STATUS __nvoc_thunk_GpuResource_kernelhostvgpudeviceapiControl(struct KernelHostVgpuDeviceApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_GpuResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_GpuResource_kernelhostvgpudeviceapiUnmap(struct KernelHostVgpuDeviceApi *pGpuResource, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { +static NV_STATUS __nvoc_thunk_GpuResource_kernelhostvgpudeviceapiUnmap(struct KernelHostVgpuDeviceApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_GpuResource.offset), pCallContext, pCpuMapping); } @@ -387,7 +387,7 @@ static struct NotifShare *__nvoc_thunk_Notifier_kernelhostvgpudeviceapiGetNotifi return notifyGetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_KernelHostVgpuDeviceApi_Notifier.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_kernelhostvgpudeviceapiMap(struct KernelHostVgpuDeviceApi *pGpuResource, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { +static NV_STATUS __nvoc_thunk_GpuResource_kernelhostvgpudeviceapiMap(struct KernelHostVgpuDeviceApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { return gpuresMap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_GpuResource.offset), pCallContext, pParams, pCpuMapping); } diff --git a/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.h b/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.h index 7ca99754c9..d7870212d5 100644 --- a/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.h +++ b/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.h @@ -125,7 +125,7 @@ struct KernelHostVgpuDeviceApi { NV_STATUS (*__kernelhostvgpudeviceapiCheckMemInterUnmap__)(struct KernelHostVgpuDeviceApi *, NvBool); NV_STATUS (*__kernelhostvgpudeviceapiGetOrAllocNotifShare__)(struct KernelHostVgpuDeviceApi *, NvHandle, NvHandle, struct NotifShare **); NV_STATUS (*__kernelhostvgpudeviceapiMapTo__)(struct KernelHostVgpuDeviceApi *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__kernelhostvgpudeviceapiGetMapAddrSpace__)(struct KernelHostVgpuDeviceApi *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NV_STATUS (*__kernelhostvgpudeviceapiGetMapAddrSpace__)(struct KernelHostVgpuDeviceApi *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); void (*__kernelhostvgpudeviceapiSetNotificationShare__)(struct KernelHostVgpuDeviceApi *, struct NotifShare *); NvU32 (*__kernelhostvgpudeviceapiGetRefCount__)(struct KernelHostVgpuDeviceApi *); void (*__kernelhostvgpudeviceapiAddAdditionalDependants__)(struct RsClient *, struct KernelHostVgpuDeviceApi *, RsResourceRef *); @@ -136,8 +136,8 @@ struct KernelHostVgpuDeviceApi { void (*__kernelhostvgpudeviceapiControl_Epilogue__)(struct KernelHostVgpuDeviceApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kernelhostvgpudeviceapiControlLookup__)(struct KernelHostVgpuDeviceApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__kernelhostvgpudeviceapiGetInternalObjectHandle__)(struct KernelHostVgpuDeviceApi *); - NV_STATUS (*__kernelhostvgpudeviceapiControl__)(struct KernelHostVgpuDeviceApi *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__kernelhostvgpudeviceapiUnmap__)(struct KernelHostVgpuDeviceApi *, CALL_CONTEXT *, RsCpuMapping *); + NV_STATUS (*__kernelhostvgpudeviceapiControl__)(struct KernelHostVgpuDeviceApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__kernelhostvgpudeviceapiUnmap__)(struct KernelHostVgpuDeviceApi *, struct CALL_CONTEXT *, struct RsCpuMapping *); NV_STATUS (*__kernelhostvgpudeviceapiGetMemInterMapParams__)(struct KernelHostVgpuDeviceApi *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__kernelhostvgpudeviceapiGetMemoryMappingDescriptor__)(struct KernelHostVgpuDeviceApi *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__kernelhostvgpudeviceapiControlFilter__)(struct KernelHostVgpuDeviceApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -148,7 +148,7 @@ struct KernelHostVgpuDeviceApi { void (*__kernelhostvgpudeviceapiControlSerialization_Epilogue__)(struct KernelHostVgpuDeviceApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__kernelhostvgpudeviceapiGetNotificationListPtr__)(struct KernelHostVgpuDeviceApi *); struct NotifShare *(*__kernelhostvgpudeviceapiGetNotificationShare__)(struct KernelHostVgpuDeviceApi *); - NV_STATUS (*__kernelhostvgpudeviceapiMap__)(struct KernelHostVgpuDeviceApi *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); + NV_STATUS (*__kernelhostvgpudeviceapiMap__)(struct KernelHostVgpuDeviceApi *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__kernelhostvgpudeviceapiAccessCallback__)(struct KernelHostVgpuDeviceApi *, struct RsClient *, void *, RsAccessRight); struct KernelHostVgpuDeviceShr *pShared; NvU32 notifyActions[7]; @@ -297,7 +297,7 @@ static inline NV_STATUS kernelhostvgpudeviceapiMapTo_DISPATCH(struct KernelHostV return pResource->__kernelhostvgpudeviceapiMapTo__(pResource, pParams); } -static inline NV_STATUS kernelhostvgpudeviceapiGetMapAddrSpace_DISPATCH(struct KernelHostVgpuDeviceApi *pGpuResource, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { +static inline NV_STATUS kernelhostvgpudeviceapiGetMapAddrSpace_DISPATCH(struct KernelHostVgpuDeviceApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { return pGpuResource->__kernelhostvgpudeviceapiGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); } @@ -341,11 +341,11 @@ static inline NvHandle kernelhostvgpudeviceapiGetInternalObjectHandle_DISPATCH(s return pGpuResource->__kernelhostvgpudeviceapiGetInternalObjectHandle__(pGpuResource); } -static inline NV_STATUS kernelhostvgpudeviceapiControl_DISPATCH(struct KernelHostVgpuDeviceApi *pGpuResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { +static inline NV_STATUS kernelhostvgpudeviceapiControl_DISPATCH(struct KernelHostVgpuDeviceApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pGpuResource->__kernelhostvgpudeviceapiControl__(pGpuResource, pCallContext, pParams); } -static inline NV_STATUS kernelhostvgpudeviceapiUnmap_DISPATCH(struct KernelHostVgpuDeviceApi *pGpuResource, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { +static inline NV_STATUS kernelhostvgpudeviceapiUnmap_DISPATCH(struct KernelHostVgpuDeviceApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { return pGpuResource->__kernelhostvgpudeviceapiUnmap__(pGpuResource, pCallContext, pCpuMapping); } @@ -389,7 +389,7 @@ static inline struct NotifShare *kernelhostvgpudeviceapiGetNotificationShare_DIS return pNotifier->__kernelhostvgpudeviceapiGetNotificationShare__(pNotifier); } -static inline NV_STATUS kernelhostvgpudeviceapiMap_DISPATCH(struct KernelHostVgpuDeviceApi *pGpuResource, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { +static inline NV_STATUS kernelhostvgpudeviceapiMap_DISPATCH(struct KernelHostVgpuDeviceApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { return pGpuResource->__kernelhostvgpudeviceapiMap__(pGpuResource, pCallContext, pParams, pCpuMapping); } @@ -431,4 +431,5 @@ kernelhostvgpudeviceSetGuestFbInfo(struct OBJGPU *pGpu, KERNEL_HOST_VGPU_DEVICE #ifdef __cplusplus } // extern "C" #endif + #endif // _G_KERNEL_HOSTVGPUDEVICEAPI_NVOC_H_ diff --git a/src/nvidia/generated/g_kernel_ioctrl_nvoc.h b/src/nvidia/generated/g_kernel_ioctrl_nvoc.h index a7bb372a38..c929e1ae41 100644 --- a/src/nvidia/generated/g_kernel_ioctrl_nvoc.h +++ b/src/nvidia/generated/g_kernel_ioctrl_nvoc.h @@ -243,4 +243,5 @@ static inline void kioctrlDestructEngine(struct KernelIoctrl *arg0) { #ifdef __cplusplus } // extern "C" #endif + #endif // _G_KERNEL_IOCTRL_NVOC_H_ diff --git a/src/nvidia/generated/g_kernel_mc_nvoc.h b/src/nvidia/generated/g_kernel_mc_nvoc.h index c3232bcaeb..65e041526a 100644 --- a/src/nvidia/generated/g_kernel_mc_nvoc.h +++ b/src/nvidia/generated/g_kernel_mc_nvoc.h @@ -241,4 +241,5 @@ static inline NvBool kmcIsPresent_DISPATCH(POBJGPU pGpu, struct KernelMc *pEngst #ifdef __cplusplus } // extern "C" #endif + #endif // _G_KERNEL_MC_NVOC_H_ diff --git a/src/nvidia/generated/g_kernel_mig_manager_nvoc.h b/src/nvidia/generated/g_kernel_mig_manager_nvoc.h index 560c2ceef6..a0be1efc3f 100644 --- a/src/nvidia/generated/g_kernel_mig_manager_nvoc.h +++ b/src/nvidia/generated/g_kernel_mig_manager_nvoc.h @@ -499,7 +499,10 @@ struct KernelMIGManager { union ENGTYPE_BIT_VECTOR PRIVATE_FIELD(partitionableEnginesInUse); NvBool PRIVATE_FIELD(bDeviceProfilingInUse); NvBool PRIVATE_FIELD(bMIGAutoOnlineEnabled); + NvBool PRIVATE_FIELD(bBootConfigSupported); + NvBool PRIVATE_FIELD(bAutoUpdateBootConfig); }; + struct KernelMIGManager_PRIVATE { const struct NVOC_RTTI *__nvoc_rtti; struct OBJENGSTATE __nvoc_base_OBJENGSTATE; @@ -537,6 +540,8 @@ struct KernelMIGManager_PRIVATE { union ENGTYPE_BIT_VECTOR partitionableEnginesInUse; NvBool bDeviceProfilingInUse; NvBool bMIGAutoOnlineEnabled; + NvBool bBootConfigSupported; + NvBool bAutoUpdateBootConfig; }; #ifndef __NVOC_CLASS_KernelMIGManager_TYPEDEF__ @@ -757,6 +762,20 @@ static inline NV_STATUS kmigmgrSetMIGState(OBJGPU *arg0, struct KernelMIGManager #define kmigmgrSetMIGState_HAL(arg0, arg1, bMemoryPartitioningNeeded, bEnable, bUnload) kmigmgrSetMIGState(arg0, arg1, bMemoryPartitioningNeeded, bEnable, bUnload) +NV_STATUS kmigmgrGetComputeProfileFromGpcCount_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 gpcCount, NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE *pProfile); + + +#ifdef __nvoc_kernel_mig_manager_h_disabled +static inline NV_STATUS kmigmgrGetComputeProfileFromGpcCount(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 gpcCount, NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE *pProfile) { + NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_mig_manager_h_disabled +#define kmigmgrGetComputeProfileFromGpcCount(arg0, arg1, gpcCount, pProfile) kmigmgrGetComputeProfileFromGpcCount_IMPL(arg0, arg1, gpcCount, pProfile) +#endif //__nvoc_kernel_mig_manager_h_disabled + +#define kmigmgrGetComputeProfileFromGpcCount_HAL(arg0, arg1, gpcCount, pProfile) kmigmgrGetComputeProfileFromGpcCount(arg0, arg1, gpcCount, pProfile) + NvBool kmigmgrIsCTSAlignmentRequired_PF(OBJGPU *arg0, struct KernelMIGManager *arg1); @@ -771,6 +790,20 @@ static inline NvBool kmigmgrIsCTSAlignmentRequired(OBJGPU *arg0, struct KernelMI #define kmigmgrIsCTSAlignmentRequired_HAL(arg0, arg1) kmigmgrIsCTSAlignmentRequired(arg0, arg1) +NV_STATUS kmigmgrRestoreFromBootConfig_PF(OBJGPU *pGpu, struct KernelMIGManager *pKernelMIGManager); + + +#ifdef __nvoc_kernel_mig_manager_h_disabled +static inline NV_STATUS kmigmgrRestoreFromBootConfig(OBJGPU *pGpu, struct KernelMIGManager *pKernelMIGManager) { + NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_mig_manager_h_disabled +#define kmigmgrRestoreFromBootConfig(pGpu, pKernelMIGManager) kmigmgrRestoreFromBootConfig_PF(pGpu, pKernelMIGManager) +#endif //__nvoc_kernel_mig_manager_h_disabled + +#define kmigmgrRestoreFromBootConfig_HAL(pGpu, pKernelMIGManager) kmigmgrRestoreFromBootConfig(pGpu, pKernelMIGManager) + NV_STATUS kmigmgrConstructEngine_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, ENGDESCRIPTOR arg2); static inline NV_STATUS kmigmgrConstructEngine_DISPATCH(OBJGPU *arg0, struct KernelMIGManager *arg1, ENGDESCRIPTOR arg2) { @@ -915,6 +948,11 @@ static inline NvBool kmigmgrIsMIGNvlinkP2PSupportOverridden(OBJGPU *pGpu, struct return ((NvBool)(0 != 0)); } +static inline void kmigmgrSetMIGEnabled(OBJGPU *pGpu, struct KernelMIGManager *pKernelMIGManager, NvBool bEnabled) { + struct KernelMIGManager_PRIVATE *pKernelMIGManager_PRIVATE = (struct KernelMIGManager_PRIVATE *)pKernelMIGManager; + pKernelMIGManager_PRIVATE->bMIGEnabled = bEnabled; +} + static inline const union ENGTYPE_BIT_VECTOR *kmigmgrGetPartitionableEnginesInUse(OBJGPU *pGpu, struct KernelMIGManager *pKernelMIGManager) { struct KernelMIGManager_PRIVATE *pKernelMIGManager_PRIVATE = (struct KernelMIGManager_PRIVATE *)pKernelMIGManager; return &pKernelMIGManager_PRIVATE->partitionableEnginesInUse; @@ -925,6 +963,11 @@ static inline NvBool kmigmgrIsA100ReducedConfig(OBJGPU *pGpu, struct KernelMIGMa return pKernelMIGManager_PRIVATE->bIsA100ReducedConfig; } +static inline void kmigmgrSetIsA100ReducedConfig(OBJGPU *pGpu, struct KernelMIGManager *pKernelMIGManager, NvBool bA100ReducedConfig) { + struct KernelMIGManager_PRIVATE *pKernelMIGManager_PRIVATE = (struct KernelMIGManager_PRIVATE *)pKernelMIGManager; + pKernelMIGManager_PRIVATE->bIsA100ReducedConfig = bA100ReducedConfig; +} + NV_STATUS kmigmgrIncRefCount_IMPL(struct RsShared *arg0); #define kmigmgrIncRefCount(arg0) kmigmgrIncRefCount_IMPL(arg0) @@ -1385,21 +1428,10 @@ static inline NvBool kmigmgrIsDeviceProfilingInUse(OBJGPU *arg0, struct KernelMI #define kmigmgrIsDeviceProfilingInUse(arg0, arg1) kmigmgrIsDeviceProfilingInUse_IMPL(arg0, arg1) #endif //__nvoc_kernel_mig_manager_h_disabled -NvBool kmigmgrIsClientUsingDeviceProfiling_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvHandle hClient); +NvBool kmigmgrIsDeviceUsingDeviceProfiling_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, Device *pDevice); #ifdef __nvoc_kernel_mig_manager_h_disabled -static inline NvBool kmigmgrIsClientUsingDeviceProfiling(OBJGPU *arg0, struct KernelMIGManager *arg1, NvHandle hClient) { - NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); - return NV_FALSE; -} -#else //__nvoc_kernel_mig_manager_h_disabled -#define kmigmgrIsClientUsingDeviceProfiling(arg0, arg1, hClient) kmigmgrIsClientUsingDeviceProfiling_IMPL(arg0, arg1, hClient) -#endif //__nvoc_kernel_mig_manager_h_disabled - -NvBool kmigmgrIsDeviceUsingDeviceProfiling_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, struct Device *pDevice); - -#ifdef __nvoc_kernel_mig_manager_h_disabled -static inline NvBool kmigmgrIsDeviceUsingDeviceProfiling(OBJGPU *arg0, struct KernelMIGManager *arg1, struct Device *pDevice) { +static inline NvBool kmigmgrIsDeviceUsingDeviceProfiling(OBJGPU *arg0, struct KernelMIGManager *arg1, Device *pDevice) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); return NV_FALSE; } @@ -1418,10 +1450,10 @@ static inline NV_STATUS kmigmgrEnableAllLCEs(OBJGPU *arg0, struct KernelMIGManag #define kmigmgrEnableAllLCEs(arg0, arg1, bEnableAllLCEs) kmigmgrEnableAllLCEs_IMPL(arg0, arg1, bEnableAllLCEs) #endif //__nvoc_kernel_mig_manager_h_disabled -NV_STATUS kmigmgrGetInstanceRefFromDevice_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, struct Device *arg2, struct MIG_INSTANCE_REF *arg3); +NV_STATUS kmigmgrGetInstanceRefFromDevice_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, Device *arg2, struct MIG_INSTANCE_REF *arg3); #ifdef __nvoc_kernel_mig_manager_h_disabled -static inline NV_STATUS kmigmgrGetInstanceRefFromDevice(OBJGPU *arg0, struct KernelMIGManager *arg1, struct Device *arg2, struct MIG_INSTANCE_REF *arg3) { +static inline NV_STATUS kmigmgrGetInstanceRefFromDevice(OBJGPU *arg0, struct KernelMIGManager *arg1, Device *arg2, struct MIG_INSTANCE_REF *arg3) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1429,21 +1461,10 @@ static inline NV_STATUS kmigmgrGetInstanceRefFromDevice(OBJGPU *arg0, struct Ker #define kmigmgrGetInstanceRefFromDevice(arg0, arg1, arg2, arg3) kmigmgrGetInstanceRefFromDevice_IMPL(arg0, arg1, arg2, arg3) #endif //__nvoc_kernel_mig_manager_h_disabled -NV_STATUS kmigmgrGetInstanceRefFromClient_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvHandle hClient, struct MIG_INSTANCE_REF *arg2); +NV_STATUS kmigmgrGetMemoryPartitionHeapFromDevice_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, Device *arg2, struct Heap **arg3); #ifdef __nvoc_kernel_mig_manager_h_disabled -static inline NV_STATUS kmigmgrGetInstanceRefFromClient(OBJGPU *arg0, struct KernelMIGManager *arg1, NvHandle hClient, struct MIG_INSTANCE_REF *arg2) { - NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kernel_mig_manager_h_disabled -#define kmigmgrGetInstanceRefFromClient(arg0, arg1, hClient, arg2) kmigmgrGetInstanceRefFromClient_IMPL(arg0, arg1, hClient, arg2) -#endif //__nvoc_kernel_mig_manager_h_disabled - -NV_STATUS kmigmgrGetMemoryPartitionHeapFromDevice_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, struct Device *arg2, struct Heap **arg3); - -#ifdef __nvoc_kernel_mig_manager_h_disabled -static inline NV_STATUS kmigmgrGetMemoryPartitionHeapFromDevice(OBJGPU *arg0, struct KernelMIGManager *arg1, struct Device *arg2, struct Heap **arg3) { +static inline NV_STATUS kmigmgrGetMemoryPartitionHeapFromDevice(OBJGPU *arg0, struct KernelMIGManager *arg1, Device *arg2, struct Heap **arg3) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1451,10 +1472,10 @@ static inline NV_STATUS kmigmgrGetMemoryPartitionHeapFromDevice(OBJGPU *arg0, st #define kmigmgrGetMemoryPartitionHeapFromDevice(arg0, arg1, arg2, arg3) kmigmgrGetMemoryPartitionHeapFromDevice_IMPL(arg0, arg1, arg2, arg3) #endif //__nvoc_kernel_mig_manager_h_disabled -NV_STATUS kmigmgrGetSwizzIdFromDevice_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, struct Device *pDevice, NvU32 *pSwizzId); +NV_STATUS kmigmgrGetSwizzIdFromDevice_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, Device *pDevice, NvU32 *pSwizzId); #ifdef __nvoc_kernel_mig_manager_h_disabled -static inline NV_STATUS kmigmgrGetSwizzIdFromDevice(OBJGPU *arg0, struct KernelMIGManager *arg1, struct Device *pDevice, NvU32 *pSwizzId) { +static inline NV_STATUS kmigmgrGetSwizzIdFromDevice(OBJGPU *arg0, struct KernelMIGManager *arg1, Device *pDevice, NvU32 *pSwizzId) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1582,10 +1603,10 @@ static inline NV_STATUS kmigmgrGetMIGReferenceFromEngineType(OBJGPU *arg0, struc #define kmigmgrGetMIGReferenceFromEngineType(arg0, arg1, rmEngineType, arg2) kmigmgrGetMIGReferenceFromEngineType_IMPL(arg0, arg1, rmEngineType, arg2) #endif //__nvoc_kernel_mig_manager_h_disabled -NV_STATUS kmigmgrGetGPUInstanceScrubberCe_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, struct Device *pDevice, NvU32 *ceInst); +NV_STATUS kmigmgrGetGPUInstanceScrubberCe_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, Device *pDevice, NvU32 *ceInst); #ifdef __nvoc_kernel_mig_manager_h_disabled -static inline NV_STATUS kmigmgrGetGPUInstanceScrubberCe(OBJGPU *arg0, struct KernelMIGManager *arg1, struct Device *pDevice, NvU32 *ceInst) { +static inline NV_STATUS kmigmgrGetGPUInstanceScrubberCe(OBJGPU *arg0, struct KernelMIGManager *arg1, Device *pDevice, NvU32 *ceInst) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1726,17 +1747,6 @@ static inline NV_STATUS kmigmgrGetComputeProfileFromSmCount(OBJGPU *arg0, struct #define kmigmgrGetComputeProfileFromSmCount(arg0, arg1, smCount, pProfile) kmigmgrGetComputeProfileFromSmCount_IMPL(arg0, arg1, smCount, pProfile) #endif //__nvoc_kernel_mig_manager_h_disabled -NV_STATUS kmigmgrGetComputeProfileFromGpcCount_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 gpcCount, NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE *pProfile); - -#ifdef __nvoc_kernel_mig_manager_h_disabled -static inline NV_STATUS kmigmgrGetComputeProfileFromGpcCount(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 gpcCount, NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE *pProfile) { - NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kernel_mig_manager_h_disabled -#define kmigmgrGetComputeProfileFromGpcCount(arg0, arg1, gpcCount, pProfile) kmigmgrGetComputeProfileFromGpcCount_IMPL(arg0, arg1, gpcCount, pProfile) -#endif //__nvoc_kernel_mig_manager_h_disabled - NV_STATUS kmigmgrGetComputeProfileFromCTSId_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 ctsId, NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE *pProfile); #ifdef __nvoc_kernel_mig_manager_h_disabled @@ -1762,15 +1772,15 @@ static inline NV_STATUS kmigmgrGetInvalidCTSIdMask(OBJGPU *arg0, struct KernelMI struct NV_RANGE kmigmgrComputeProfileSizeToCTSIdRange_IMPL(NvU32 computeSize); #define kmigmgrComputeProfileSizeToCTSIdRange(computeSize) kmigmgrComputeProfileSizeToCTSIdRange_IMPL(computeSize) -NV_STATUS kmigmgrGetFreeCTSId_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 *pCtsId, NvU64 globalValidCtsMask, NvU64 ctsIdInUseMask, NvU32 profileSize); +NV_STATUS kmigmgrGetFreeCTSId_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 *pCtsId, NvU64 globalValidCtsMask, NvU64 globalValidGfxCtsMask, NvU64 ctsIdsInUseMask, NvU32 profileSize, NvBool bRestrictWithGfx, NvBool bGfxRequested); #ifdef __nvoc_kernel_mig_manager_h_disabled -static inline NV_STATUS kmigmgrGetFreeCTSId(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 *pCtsId, NvU64 globalValidCtsMask, NvU64 ctsIdInUseMask, NvU32 profileSize) { +static inline NV_STATUS kmigmgrGetFreeCTSId(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 *pCtsId, NvU64 globalValidCtsMask, NvU64 globalValidGfxCtsMask, NvU64 ctsIdsInUseMask, NvU32 profileSize, NvBool bRestrictWithGfx, NvBool bGfxRequested) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_mig_manager_h_disabled -#define kmigmgrGetFreeCTSId(arg0, arg1, pCtsId, globalValidCtsMask, ctsIdInUseMask, profileSize) kmigmgrGetFreeCTSId_IMPL(arg0, arg1, pCtsId, globalValidCtsMask, ctsIdInUseMask, profileSize) +#define kmigmgrGetFreeCTSId(arg0, arg1, pCtsId, globalValidCtsMask, globalValidGfxCtsMask, ctsIdsInUseMask, profileSize, bRestrictWithGfx, bGfxRequested) kmigmgrGetFreeCTSId_IMPL(arg0, arg1, pCtsId, globalValidCtsMask, globalValidGfxCtsMask, ctsIdsInUseMask, profileSize, bRestrictWithGfx, bGfxRequested) #endif //__nvoc_kernel_mig_manager_h_disabled NvU32 kmigmgrGetComputeSizeFromCTSId_IMPL(NvU32 ctsId); @@ -1854,4 +1864,5 @@ static inline NV_STATUS kmigmgrUpdateCiConfigForVgpu(OBJGPU *pGpu, struct Kernel #ifdef __cplusplus } // extern "C" #endif + #endif // _G_KERNEL_MIG_MANAGER_NVOC_H_ diff --git a/src/nvidia/generated/g_kernel_nvdec_ctx_nvoc.h b/src/nvidia/generated/g_kernel_nvdec_ctx_nvoc.h index 10b56a252e..88b1b07585 100644 --- a/src/nvidia/generated/g_kernel_nvdec_ctx_nvoc.h +++ b/src/nvidia/generated/g_kernel_nvdec_ctx_nvoc.h @@ -323,4 +323,5 @@ static inline void __nvoc_nvdecctxDestruct(struct NvdecContext *pNvdecContext) { #ifdef __cplusplus } // extern "C" #endif + #endif // _G_KERNEL_NVDEC_CTX_NVOC_H_ diff --git a/src/nvidia/generated/g_kernel_nvenc_ctx_nvoc.h b/src/nvidia/generated/g_kernel_nvenc_ctx_nvoc.h index 5a52810954..1a6aaaf64c 100644 --- a/src/nvidia/generated/g_kernel_nvenc_ctx_nvoc.h +++ b/src/nvidia/generated/g_kernel_nvenc_ctx_nvoc.h @@ -323,4 +323,5 @@ static inline void __nvoc_msencctxDestruct(struct MsencContext *pMsencContext) { #ifdef __cplusplus } // extern "C" #endif + #endif // _G_KERNEL_NVENC_CTX_NVOC_H_ diff --git a/src/nvidia/generated/g_kernel_nvjpg_ctx_nvoc.h b/src/nvidia/generated/g_kernel_nvjpg_ctx_nvoc.h index 26c42965c1..a7580f04bf 100644 --- a/src/nvidia/generated/g_kernel_nvjpg_ctx_nvoc.h +++ b/src/nvidia/generated/g_kernel_nvjpg_ctx_nvoc.h @@ -323,4 +323,5 @@ static inline void __nvoc_nvjpgctxDestruct(struct NvjpgContext *pNvjpgContext) { #ifdef __cplusplus } // extern "C" #endif + #endif // _G_KERNEL_NVJPG_CTX_NVOC_H_ diff --git a/src/nvidia/generated/g_kernel_nvlink_nvoc.c b/src/nvidia/generated/g_kernel_nvlink_nvoc.c index db6ddeb170..11f4c03c67 100644 --- a/src/nvidia/generated/g_kernel_nvlink_nvoc.c +++ b/src/nvidia/generated/g_kernel_nvlink_nvoc.c @@ -66,31 +66,31 @@ const struct NVOC_CLASS_DEF __nvoc_class_def_KernelNvlink = /*pExportInfo=*/ &__nvoc_export_info_KernelNvlink }; -static NV_STATUS __nvoc_thunk_KernelNvlink_engstateConstructEngine(OBJGPU *arg0, struct OBJENGSTATE *arg1, ENGDESCRIPTOR arg2) { +static NV_STATUS __nvoc_thunk_KernelNvlink_engstateConstructEngine(struct OBJGPU *arg0, struct OBJENGSTATE *arg1, ENGDESCRIPTOR arg2) { return knvlinkConstructEngine(arg0, (struct KernelNvlink *)(((unsigned char *)arg1) - __nvoc_rtti_KernelNvlink_OBJENGSTATE.offset), arg2); } -static NV_STATUS __nvoc_thunk_KernelNvlink_engstateStatePreInitLocked(OBJGPU *arg0, struct OBJENGSTATE *arg1) { +static NV_STATUS __nvoc_thunk_KernelNvlink_engstateStatePreInitLocked(struct OBJGPU *arg0, struct OBJENGSTATE *arg1) { return knvlinkStatePreInitLocked(arg0, (struct KernelNvlink *)(((unsigned char *)arg1) - __nvoc_rtti_KernelNvlink_OBJENGSTATE.offset)); } -static NV_STATUS __nvoc_thunk_KernelNvlink_engstateStateLoad(OBJGPU *arg0, struct OBJENGSTATE *arg1, NvU32 arg2) { +static NV_STATUS __nvoc_thunk_KernelNvlink_engstateStateLoad(struct OBJGPU *arg0, struct OBJENGSTATE *arg1, NvU32 arg2) { return knvlinkStateLoad(arg0, (struct KernelNvlink *)(((unsigned char *)arg1) - __nvoc_rtti_KernelNvlink_OBJENGSTATE.offset), arg2); } -static NV_STATUS __nvoc_thunk_KernelNvlink_engstateStatePostLoad(OBJGPU *arg0, struct OBJENGSTATE *arg1, NvU32 arg2) { +static NV_STATUS __nvoc_thunk_KernelNvlink_engstateStatePostLoad(struct OBJGPU *arg0, struct OBJENGSTATE *arg1, NvU32 arg2) { return knvlinkStatePostLoad(arg0, (struct KernelNvlink *)(((unsigned char *)arg1) - __nvoc_rtti_KernelNvlink_OBJENGSTATE.offset), arg2); } -static NV_STATUS __nvoc_thunk_KernelNvlink_engstateStateUnload(OBJGPU *arg0, struct OBJENGSTATE *arg1, NvU32 arg2) { +static NV_STATUS __nvoc_thunk_KernelNvlink_engstateStateUnload(struct OBJGPU *arg0, struct OBJENGSTATE *arg1, NvU32 arg2) { return knvlinkStateUnload(arg0, (struct KernelNvlink *)(((unsigned char *)arg1) - __nvoc_rtti_KernelNvlink_OBJENGSTATE.offset), arg2); } -static NV_STATUS __nvoc_thunk_KernelNvlink_engstateStatePostUnload(OBJGPU *arg0, struct OBJENGSTATE *arg1, NvU32 arg2) { +static NV_STATUS __nvoc_thunk_KernelNvlink_engstateStatePostUnload(struct OBJGPU *arg0, struct OBJENGSTATE *arg1, NvU32 arg2) { return knvlinkStatePostUnload(arg0, (struct KernelNvlink *)(((unsigned char *)arg1) - __nvoc_rtti_KernelNvlink_OBJENGSTATE.offset), arg2); } -static NvBool __nvoc_thunk_KernelNvlink_engstateIsPresent(OBJGPU *arg0, struct OBJENGSTATE *arg1) { +static NvBool __nvoc_thunk_KernelNvlink_engstateIsPresent(struct OBJGPU *arg0, struct OBJENGSTATE *arg1) { return knvlinkIsPresent(arg0, (struct KernelNvlink *)(((unsigned char *)arg1) - __nvoc_rtti_KernelNvlink_OBJENGSTATE.offset)); } diff --git a/src/nvidia/generated/g_kernel_nvlink_nvoc.h b/src/nvidia/generated/g_kernel_nvlink_nvoc.h index 4b181b5b5f..95d6e6df65 100644 --- a/src/nvidia/generated/g_kernel_nvlink_nvoc.h +++ b/src/nvidia/generated/g_kernel_nvlink_nvoc.h @@ -45,6 +45,7 @@ extern "C" { #if defined(INCLUDE_NVLINK_LIB) #include "nvlink.h" #include "nvlink_export.h" +#include "nvlink_lib_ctrl.h" #endif #include "kernel/gpu/nvlink/kernel_ioctrl.h" @@ -167,7 +168,7 @@ typedef struct _def_knvlink_link #endif - OBJGPU *pGpu; + struct OBJGPU *pGpu; NvU8 linkId; NvBool bValid; @@ -220,39 +221,39 @@ struct KernelNvlink { struct Object *__nvoc_pbase_Object; struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; struct KernelNvlink *__nvoc_pbase_KernelNvlink; - NV_STATUS (*__knvlinkConstructEngine__)(OBJGPU *, struct KernelNvlink *, ENGDESCRIPTOR); - NV_STATUS (*__knvlinkStatePreInitLocked__)(OBJGPU *, struct KernelNvlink *); - NV_STATUS (*__knvlinkStateLoad__)(OBJGPU *, struct KernelNvlink *, NvU32); - NV_STATUS (*__knvlinkStatePostLoad__)(OBJGPU *, struct KernelNvlink *, NvU32); - NV_STATUS (*__knvlinkStateUnload__)(OBJGPU *, struct KernelNvlink *, NvU32); - NV_STATUS (*__knvlinkStatePostUnload__)(OBJGPU *, struct KernelNvlink *, NvU32); - NvBool (*__knvlinkIsPresent__)(OBJGPU *, struct KernelNvlink *); - NV_STATUS (*__knvlinkSetUniqueFabricBaseAddress__)(OBJGPU *, struct KernelNvlink *, NvU64); - void (*__knvlinkClearUniqueFabricBaseAddress__)(OBJGPU *, struct KernelNvlink *); - NV_STATUS (*__knvlinkHandleFaultUpInterrupt__)(OBJGPU *, struct KernelNvlink *, NvU32); - NV_STATUS (*__knvlinkValidateFabricBaseAddress__)(OBJGPU *, struct KernelNvlink *, NvU64); - NvU32 (*__knvlinkGetConnectedLinksMask__)(OBJGPU *, struct KernelNvlink *); - NV_STATUS (*__knvlinkEnableLinksPostTopology__)(OBJGPU *, struct KernelNvlink *, NvU32); - NV_STATUS (*__knvlinkOverrideConfig__)(OBJGPU *, struct KernelNvlink *, NvU32); - NV_STATUS (*__knvlinkFilterBridgeLinks__)(OBJGPU *, struct KernelNvlink *); - NvU32 (*__knvlinkGetUniquePeerIdMask__)(OBJGPU *, struct KernelNvlink *); - NvU32 (*__knvlinkGetUniquePeerId__)(OBJGPU *, struct KernelNvlink *, OBJGPU *); - NV_STATUS (*__knvlinkRemoveMapping__)(OBJGPU *, struct KernelNvlink *, NvBool, NvU32, NvBool); - NV_STATUS (*__knvlinkGetP2POptimalCEs__)(OBJGPU *, struct KernelNvlink *, NvU32, NvU32 *, NvU32 *, NvU32 *, NvU32 *); - NV_STATUS (*__knvlinkConstructHal__)(OBJGPU *, struct KernelNvlink *); - void (*__knvlinkSetupPeerMapping__)(OBJGPU *, struct KernelNvlink *, OBJGPU *, NvU32); - NV_STATUS (*__knvlinkProgramLinkSpeed__)(OBJGPU *, struct KernelNvlink *); - NvBool (*__knvlinkPoweredUpForD3__)(OBJGPU *, struct KernelNvlink *); - NV_STATUS (*__knvlinkIsAliSupported__)(OBJGPU *, struct KernelNvlink *); - NV_STATUS (*__knvlinkPostSetupNvlinkPeer__)(OBJGPU *, struct KernelNvlink *); - NV_STATUS (*__knvlinkDiscoverPostRxDetLinks__)(OBJGPU *, struct KernelNvlink *, OBJGPU *); - NV_STATUS (*__knvlinkLogAliDebugMessages__)(OBJGPU *, struct KernelNvlink *); - void (*__knvlinkGetEffectivePeerLinkMask__)(OBJGPU *, struct KernelNvlink *, OBJGPU *, NvU32 *); - NvU32 (*__knvlinkGetNumLinksToBeReducedPerIoctrl__)(struct KernelNvlink *); + NV_STATUS (*__knvlinkConstructEngine__)(struct OBJGPU *, struct KernelNvlink *, ENGDESCRIPTOR); + NV_STATUS (*__knvlinkStatePreInitLocked__)(struct OBJGPU *, struct KernelNvlink *); + NV_STATUS (*__knvlinkStateLoad__)(struct OBJGPU *, struct KernelNvlink *, NvU32); + NV_STATUS (*__knvlinkStatePostLoad__)(struct OBJGPU *, struct KernelNvlink *, NvU32); + NV_STATUS (*__knvlinkStateUnload__)(struct OBJGPU *, struct KernelNvlink *, NvU32); + NV_STATUS (*__knvlinkStatePostUnload__)(struct OBJGPU *, struct KernelNvlink *, NvU32); + NvBool (*__knvlinkIsPresent__)(struct OBJGPU *, struct KernelNvlink *); + NV_STATUS (*__knvlinkSetUniqueFabricBaseAddress__)(struct OBJGPU *, struct KernelNvlink *, NvU64); + void (*__knvlinkClearUniqueFabricBaseAddress__)(struct OBJGPU *, struct KernelNvlink *); + NV_STATUS (*__knvlinkHandleFaultUpInterrupt__)(struct OBJGPU *, struct KernelNvlink *, NvU32); + NV_STATUS (*__knvlinkValidateFabricBaseAddress__)(struct OBJGPU *, struct KernelNvlink *, NvU64); + NvU32 (*__knvlinkGetConnectedLinksMask__)(struct OBJGPU *, struct KernelNvlink *); + NV_STATUS (*__knvlinkEnableLinksPostTopology__)(struct OBJGPU *, struct KernelNvlink *, NvU32); + NV_STATUS (*__knvlinkOverrideConfig__)(struct OBJGPU *, struct KernelNvlink *, NvU32); + NV_STATUS (*__knvlinkFilterBridgeLinks__)(struct OBJGPU *, struct KernelNvlink *); + NvU32 (*__knvlinkGetUniquePeerIdMask__)(struct OBJGPU *, struct KernelNvlink *); + NvU32 (*__knvlinkGetUniquePeerId__)(struct OBJGPU *, struct KernelNvlink *, struct OBJGPU *); + NV_STATUS (*__knvlinkRemoveMapping__)(struct OBJGPU *, struct KernelNvlink *, NvBool, NvU32, NvBool); + NV_STATUS (*__knvlinkGetP2POptimalCEs__)(struct OBJGPU *, struct KernelNvlink *, NvU32, NvU32 *, NvU32 *, NvU32 *, NvU32 *); + NV_STATUS (*__knvlinkConstructHal__)(struct OBJGPU *, struct KernelNvlink *); + void (*__knvlinkSetupPeerMapping__)(struct OBJGPU *, struct KernelNvlink *, struct OBJGPU *, NvU32); + NV_STATUS (*__knvlinkProgramLinkSpeed__)(struct OBJGPU *, struct KernelNvlink *); + NvBool (*__knvlinkPoweredUpForD3__)(struct OBJGPU *, struct KernelNvlink *); + NV_STATUS (*__knvlinkIsAliSupported__)(struct OBJGPU *, struct KernelNvlink *); + NV_STATUS (*__knvlinkPostSetupNvlinkPeer__)(struct OBJGPU *, struct KernelNvlink *); + NV_STATUS (*__knvlinkDiscoverPostRxDetLinks__)(struct OBJGPU *, struct KernelNvlink *, struct OBJGPU *); + NV_STATUS (*__knvlinkLogAliDebugMessages__)(struct OBJGPU *, struct KernelNvlink *); + void (*__knvlinkGetEffectivePeerLinkMask__)(struct OBJGPU *, struct KernelNvlink *, struct OBJGPU *, NvU32 *); + NvU32 (*__knvlinkGetNumLinksToBeReducedPerIoctrl__)(struct OBJGPU *, struct KernelNvlink *); NvBool (*__knvlinkIsBandwidthModeOff__)(struct KernelNvlink *); - void (*__knvlinkDirectConnectCheck__)(OBJGPU *, struct KernelNvlink *); - NvBool (*__knvlinkIsGpuReducedNvlinkConfig__)(OBJGPU *, struct KernelNvlink *); - NvBool (*__knvlinkIsFloorSweepingNeeded__)(OBJGPU *, struct KernelNvlink *, NvU32, NvU32); + void (*__knvlinkDirectConnectCheck__)(struct OBJGPU *, struct KernelNvlink *); + NvBool (*__knvlinkIsGpuReducedNvlinkConfig__)(struct OBJGPU *, struct KernelNvlink *); + NvBool (*__knvlinkIsFloorSweepingNeeded__)(struct OBJGPU *, struct KernelNvlink *, NvU32, NvU32); NV_STATUS (*__knvlinkStateInitLocked__)(POBJGPU, struct KernelNvlink *); NV_STATUS (*__knvlinkStatePreLoad__)(POBJGPU, struct KernelNvlink *, NvU32); void (*__knvlinkStateDestroy__)(POBJGPU, struct KernelNvlink *); @@ -274,6 +275,7 @@ struct KernelNvlink { NvBool PDB_PROP_KNVLINK_MINION_FORCE_NON_ALI_TRAINING; NvBool PDB_PROP_KNVLINK_MINION_GFW_BOOT; NvBool PDB_PROP_KNVLINK_SYSMEM_SUPPORT_ENABLED; + NvBool PDB_PROP_KNVLINK_FORCED_LOOPBACK_ON_SWITCH_MODE_ENABLED; struct KernelIoctrl *PRIVATE_FIELD(pKernelIoctrl)[3]; NvU32 PRIVATE_FIELD(ioctrlMask); NvU32 PRIVATE_FIELD(ipVerNvlink); @@ -304,9 +306,11 @@ struct KernelNvlink { NvU32 PRIVATE_FIELD(sysmemLinkMask); NvU32 PRIVATE_FIELD(peerLinkMasks)[32]; NvU32 PRIVATE_FIELD(forcedSysmemDeviceType); - NVLINK_INBAND_MSG_CALLBACK PRIVATE_FIELD(inbandCallback)[5]; + NVLINK_INBAND_MSG_CALLBACK PRIVATE_FIELD(inbandCallback)[6]; nvlink_device *PRIVATE_FIELD(pNvlinkDev); NvU32 PRIVATE_FIELD(deviceLockRefcount); + char *PRIVATE_FIELD(driverName); + char *PRIVATE_FIELD(deviceName); NvBool PRIVATE_FIELD(bVerifTrainingEnable); NvBool PRIVATE_FIELD(bL2Entry); NvBool PRIVATE_FIELD(bSkipLinkTraining); @@ -321,6 +325,119 @@ struct KernelNvlink { NvU32 PRIVATE_FIELD(nvlinkLinkSpeed); NvU32 PRIVATE_FIELD(errorRecoveries)[18]; NvBool PRIVATE_FIELD(bNvswitchProxy); + NvU64 PRIVATE_FIELD(fabricBaseAddr); +}; + +struct KernelNvlink_PRIVATE { + const struct NVOC_RTTI *__nvoc_rtti; + struct OBJENGSTATE __nvoc_base_OBJENGSTATE; + struct Object *__nvoc_pbase_Object; + struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; + struct KernelNvlink *__nvoc_pbase_KernelNvlink; + NV_STATUS (*__knvlinkConstructEngine__)(struct OBJGPU *, struct KernelNvlink *, ENGDESCRIPTOR); + NV_STATUS (*__knvlinkStatePreInitLocked__)(struct OBJGPU *, struct KernelNvlink *); + NV_STATUS (*__knvlinkStateLoad__)(struct OBJGPU *, struct KernelNvlink *, NvU32); + NV_STATUS (*__knvlinkStatePostLoad__)(struct OBJGPU *, struct KernelNvlink *, NvU32); + NV_STATUS (*__knvlinkStateUnload__)(struct OBJGPU *, struct KernelNvlink *, NvU32); + NV_STATUS (*__knvlinkStatePostUnload__)(struct OBJGPU *, struct KernelNvlink *, NvU32); + NvBool (*__knvlinkIsPresent__)(struct OBJGPU *, struct KernelNvlink *); + NV_STATUS (*__knvlinkSetUniqueFabricBaseAddress__)(struct OBJGPU *, struct KernelNvlink *, NvU64); + void (*__knvlinkClearUniqueFabricBaseAddress__)(struct OBJGPU *, struct KernelNvlink *); + NV_STATUS (*__knvlinkHandleFaultUpInterrupt__)(struct OBJGPU *, struct KernelNvlink *, NvU32); + NV_STATUS (*__knvlinkValidateFabricBaseAddress__)(struct OBJGPU *, struct KernelNvlink *, NvU64); + NvU32 (*__knvlinkGetConnectedLinksMask__)(struct OBJGPU *, struct KernelNvlink *); + NV_STATUS (*__knvlinkEnableLinksPostTopology__)(struct OBJGPU *, struct KernelNvlink *, NvU32); + NV_STATUS (*__knvlinkOverrideConfig__)(struct OBJGPU *, struct KernelNvlink *, NvU32); + NV_STATUS (*__knvlinkFilterBridgeLinks__)(struct OBJGPU *, struct KernelNvlink *); + NvU32 (*__knvlinkGetUniquePeerIdMask__)(struct OBJGPU *, struct KernelNvlink *); + NvU32 (*__knvlinkGetUniquePeerId__)(struct OBJGPU *, struct KernelNvlink *, struct OBJGPU *); + NV_STATUS (*__knvlinkRemoveMapping__)(struct OBJGPU *, struct KernelNvlink *, NvBool, NvU32, NvBool); + NV_STATUS (*__knvlinkGetP2POptimalCEs__)(struct OBJGPU *, struct KernelNvlink *, NvU32, NvU32 *, NvU32 *, NvU32 *, NvU32 *); + NV_STATUS (*__knvlinkConstructHal__)(struct OBJGPU *, struct KernelNvlink *); + void (*__knvlinkSetupPeerMapping__)(struct OBJGPU *, struct KernelNvlink *, struct OBJGPU *, NvU32); + NV_STATUS (*__knvlinkProgramLinkSpeed__)(struct OBJGPU *, struct KernelNvlink *); + NvBool (*__knvlinkPoweredUpForD3__)(struct OBJGPU *, struct KernelNvlink *); + NV_STATUS (*__knvlinkIsAliSupported__)(struct OBJGPU *, struct KernelNvlink *); + NV_STATUS (*__knvlinkPostSetupNvlinkPeer__)(struct OBJGPU *, struct KernelNvlink *); + NV_STATUS (*__knvlinkDiscoverPostRxDetLinks__)(struct OBJGPU *, struct KernelNvlink *, struct OBJGPU *); + NV_STATUS (*__knvlinkLogAliDebugMessages__)(struct OBJGPU *, struct KernelNvlink *); + void (*__knvlinkGetEffectivePeerLinkMask__)(struct OBJGPU *, struct KernelNvlink *, struct OBJGPU *, NvU32 *); + NvU32 (*__knvlinkGetNumLinksToBeReducedPerIoctrl__)(struct OBJGPU *, struct KernelNvlink *); + NvBool (*__knvlinkIsBandwidthModeOff__)(struct KernelNvlink *); + void (*__knvlinkDirectConnectCheck__)(struct OBJGPU *, struct KernelNvlink *); + NvBool (*__knvlinkIsGpuReducedNvlinkConfig__)(struct OBJGPU *, struct KernelNvlink *); + NvBool (*__knvlinkIsFloorSweepingNeeded__)(struct OBJGPU *, struct KernelNvlink *, NvU32, NvU32); + NV_STATUS (*__knvlinkStateInitLocked__)(POBJGPU, struct KernelNvlink *); + NV_STATUS (*__knvlinkStatePreLoad__)(POBJGPU, struct KernelNvlink *, NvU32); + void (*__knvlinkStateDestroy__)(POBJGPU, struct KernelNvlink *); + NV_STATUS (*__knvlinkStatePreUnload__)(POBJGPU, struct KernelNvlink *, NvU32); + NV_STATUS (*__knvlinkStateInitUnlocked__)(POBJGPU, struct KernelNvlink *); + void (*__knvlinkInitMissing__)(POBJGPU, struct KernelNvlink *); + NV_STATUS (*__knvlinkStatePreInitUnlocked__)(POBJGPU, struct KernelNvlink *); + NvBool PDB_PROP_KNVLINK_ENABLED; + NvBool PDB_PROP_KNVLINK_L2_POWER_STATE_ENABLED; + NvBool PDB_PROP_KNVLINK_UNSET_NVLINK_PEER_SUPPORTED; + NvBool PDB_PROP_KNVLINK_CONFIG_REQUIRE_INITIALIZED_LINKS_CHECK; + NvBool PDB_PROP_KNVLINK_LANE_SHUTDOWN_ENABLED; + NvBool PDB_PROP_KNVLINK_LANE_SHUTDOWN_ON_UNLOAD; + NvBool PDB_PROP_KNVLINK_LINKRESET_AFTER_SHUTDOWN; + NvBool PDB_PROP_KNVLINK_BUG2274645_RESET_FOR_RTD3_FGC6; + NvBool PDB_PROP_KNVLINK_L2_POWER_STATE_FOR_LONG_IDLE; + NvBool PDB_PROP_KNVLINK_WAR_BUG_3471679_PEERID_FILTERING; + NvBool PDB_PROP_KNVLINK_MINION_FORCE_ALI_TRAINING; + NvBool PDB_PROP_KNVLINK_MINION_FORCE_NON_ALI_TRAINING; + NvBool PDB_PROP_KNVLINK_MINION_GFW_BOOT; + NvBool PDB_PROP_KNVLINK_SYSMEM_SUPPORT_ENABLED; + NvBool PDB_PROP_KNVLINK_FORCED_LOOPBACK_ON_SWITCH_MODE_ENABLED; + struct KernelIoctrl *pKernelIoctrl[3]; + NvU32 ioctrlMask; + NvU32 ipVerNvlink; + NvU8 ioctrlNumEntries; + NvU32 ioctrlSize; + NvU32 registryControl; + NvU32 minionControl; + NvU32 verboseMask; + NvU32 *pLinkConnection; + NvBool bChiplibConfig; + NvBool bRegistryLinkOverride; + NvU32 registryLinkMask; + NvBool bOverrideComputePeerMode; + NvU32 discoveredLinks; + NvU32 vbiosDisabledLinkMask; + NvU32 regkeyDisabledLinksMask; + NvU32 initDisabledLinksMask; + NvU32 connectedLinksMask; + NvU32 bridgeSensableLinks; + NvU32 bridgedLinks; + NvU32 enabledLinks; + FaultUpList faultUpLinks; + NvU32 initializedLinks; + KNVLINK_RM_LINK nvlinkLinks[18]; + NvBool bIsGpuDegraded; + NvU32 postRxDetLinkMask; + NvU32 disconnectedLinkMask; + NvU32 sysmemLinkMask; + NvU32 peerLinkMasks[32]; + NvU32 forcedSysmemDeviceType; + NVLINK_INBAND_MSG_CALLBACK inbandCallback[6]; + nvlink_device *pNvlinkDev; + NvU32 deviceLockRefcount; + char *driverName; + char *deviceName; + NvBool bVerifTrainingEnable; + NvBool bL2Entry; + NvBool bSkipLinkTraining; + NvBool bForceAutoconfig; + NvBool bForceEnableCoreLibRtlsims; + NvBool bEnableTrainingAtLoad; + NvBool bEnableSafeModeAtLoad; + NvBool bEnableAli; + NvBool bFloorSwept; + NvBool bLinkTrainingDebugSpew; + NvBool bDisableL2Mode; + NvU32 nvlinkLinkSpeed; + NvU32 errorRecoveries[18]; + NvBool bNvswitchProxy; NvU64 fabricBaseAddr; }; @@ -371,6 +488,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelNvlink; #define PDB_PROP_KNVLINK_BUG2274645_RESET_FOR_RTD3_FGC6_BASE_NAME PDB_PROP_KNVLINK_BUG2274645_RESET_FOR_RTD3_FGC6 #define PDB_PROP_KNVLINK_LANE_SHUTDOWN_ON_UNLOAD_BASE_CAST #define PDB_PROP_KNVLINK_LANE_SHUTDOWN_ON_UNLOAD_BASE_NAME PDB_PROP_KNVLINK_LANE_SHUTDOWN_ON_UNLOAD +#define PDB_PROP_KNVLINK_FORCED_LOOPBACK_ON_SWITCH_MODE_ENABLED_BASE_CAST +#define PDB_PROP_KNVLINK_FORCED_LOOPBACK_ON_SWITCH_MODE_ENABLED_BASE_NAME PDB_PROP_KNVLINK_FORCED_LOOPBACK_ON_SWITCH_MODE_ENABLED #define PDB_PROP_KNVLINK_L2_POWER_STATE_FOR_LONG_IDLE_BASE_CAST #define PDB_PROP_KNVLINK_L2_POWER_STATE_FOR_LONG_IDLE_BASE_NAME PDB_PROP_KNVLINK_L2_POWER_STATE_FOR_LONG_IDLE #define PDB_PROP_KNVLINK_LINKRESET_AFTER_SHUTDOWN_BASE_CAST @@ -431,8 +550,8 @@ NV_STATUS __nvoc_objCreate_KernelNvlink(KernelNvlink**, Dynamic*, NvU32); #define knvlinkLogAliDebugMessages_HAL(pGpu, pKernelNvlink) knvlinkLogAliDebugMessages_DISPATCH(pGpu, pKernelNvlink) #define knvlinkGetEffectivePeerLinkMask(pGpu, pKernelNvlink, pRemoteGpu, pPeerLinkMask) knvlinkGetEffectivePeerLinkMask_DISPATCH(pGpu, pKernelNvlink, pRemoteGpu, pPeerLinkMask) #define knvlinkGetEffectivePeerLinkMask_HAL(pGpu, pKernelNvlink, pRemoteGpu, pPeerLinkMask) knvlinkGetEffectivePeerLinkMask_DISPATCH(pGpu, pKernelNvlink, pRemoteGpu, pPeerLinkMask) -#define knvlinkGetNumLinksToBeReducedPerIoctrl(pKernelNvlink) knvlinkGetNumLinksToBeReducedPerIoctrl_DISPATCH(pKernelNvlink) -#define knvlinkGetNumLinksToBeReducedPerIoctrl_HAL(pKernelNvlink) knvlinkGetNumLinksToBeReducedPerIoctrl_DISPATCH(pKernelNvlink) +#define knvlinkGetNumLinksToBeReducedPerIoctrl(pGpu, pKernelNvlink) knvlinkGetNumLinksToBeReducedPerIoctrl_DISPATCH(pGpu, pKernelNvlink) +#define knvlinkGetNumLinksToBeReducedPerIoctrl_HAL(pGpu, pKernelNvlink) knvlinkGetNumLinksToBeReducedPerIoctrl_DISPATCH(pGpu, pKernelNvlink) #define knvlinkIsBandwidthModeOff(pKernelNvlink) knvlinkIsBandwidthModeOff_DISPATCH(pKernelNvlink) #define knvlinkIsBandwidthModeOff_HAL(pKernelNvlink) knvlinkIsBandwidthModeOff_DISPATCH(pKernelNvlink) #define knvlinkDirectConnectCheck(pGpu, pKernelNvlink) knvlinkDirectConnectCheck_DISPATCH(pGpu, pKernelNvlink) @@ -448,11 +567,11 @@ NV_STATUS __nvoc_objCreate_KernelNvlink(KernelNvlink**, Dynamic*, NvU32); #define knvlinkStateInitUnlocked(pGpu, pEngstate) knvlinkStateInitUnlocked_DISPATCH(pGpu, pEngstate) #define knvlinkInitMissing(pGpu, pEngstate) knvlinkInitMissing_DISPATCH(pGpu, pEngstate) #define knvlinkStatePreInitUnlocked(pGpu, pEngstate) knvlinkStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -NvBool knvlinkIsForcedConfig_IMPL(OBJGPU *arg0, struct KernelNvlink *arg1); +NvBool knvlinkIsForcedConfig_IMPL(struct OBJGPU *arg0, struct KernelNvlink *arg1); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NvBool knvlinkIsForcedConfig(OBJGPU *arg0, struct KernelNvlink *arg1) { +static inline NvBool knvlinkIsForcedConfig(struct OBJGPU *arg0, struct KernelNvlink *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_FALSE; } @@ -462,11 +581,11 @@ static inline NvBool knvlinkIsForcedConfig(OBJGPU *arg0, struct KernelNvlink *ar #define knvlinkIsForcedConfig_HAL(arg0, arg1) knvlinkIsForcedConfig(arg0, arg1) -NV_STATUS knvlinkApplyRegkeyOverrides_IMPL(OBJGPU *pGpu, struct KernelNvlink *arg0); +NV_STATUS knvlinkApplyRegkeyOverrides_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *arg0); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkApplyRegkeyOverrides(OBJGPU *pGpu, struct KernelNvlink *arg0) { +static inline NV_STATUS knvlinkApplyRegkeyOverrides(struct OBJGPU *pGpu, struct KernelNvlink *arg0) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -476,11 +595,11 @@ static inline NV_STATUS knvlinkApplyRegkeyOverrides(OBJGPU *pGpu, struct KernelN #define knvlinkApplyRegkeyOverrides_HAL(pGpu, arg0) knvlinkApplyRegkeyOverrides(pGpu, arg0) -NvBool knvlinkIsNvlinkDefaultEnabled_IMPL(OBJGPU *pGpu, struct KernelNvlink *arg0); +NvBool knvlinkIsNvlinkDefaultEnabled_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *arg0); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NvBool knvlinkIsNvlinkDefaultEnabled(OBJGPU *pGpu, struct KernelNvlink *arg0) { +static inline NvBool knvlinkIsNvlinkDefaultEnabled(struct OBJGPU *pGpu, struct KernelNvlink *arg0) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_FALSE; } @@ -490,11 +609,11 @@ static inline NvBool knvlinkIsNvlinkDefaultEnabled(OBJGPU *pGpu, struct KernelNv #define knvlinkIsNvlinkDefaultEnabled_HAL(pGpu, arg0) knvlinkIsNvlinkDefaultEnabled(pGpu, arg0) -NvBool knvlinkIsP2pLoopbackSupported_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); +NvBool knvlinkIsP2pLoopbackSupported_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NvBool knvlinkIsP2pLoopbackSupported(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NvBool knvlinkIsP2pLoopbackSupported(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_FALSE; } @@ -504,11 +623,11 @@ static inline NvBool knvlinkIsP2pLoopbackSupported(OBJGPU *pGpu, struct KernelNv #define knvlinkIsP2pLoopbackSupported_HAL(pGpu, pKernelNvlink) knvlinkIsP2pLoopbackSupported(pGpu, pKernelNvlink) -NvBool knvlinkIsP2pLoopbackSupportedPerLink_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0); +NvBool knvlinkIsP2pLoopbackSupportedPerLink_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NvBool knvlinkIsP2pLoopbackSupportedPerLink(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0) { +static inline NvBool knvlinkIsP2pLoopbackSupportedPerLink(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_FALSE; } @@ -518,11 +637,11 @@ static inline NvBool knvlinkIsP2pLoopbackSupportedPerLink(OBJGPU *pGpu, struct K #define knvlinkIsP2pLoopbackSupportedPerLink_HAL(pGpu, pKernelNvlink, arg0) knvlinkIsP2pLoopbackSupportedPerLink(pGpu, pKernelNvlink, arg0) -NvBool knvlinkIsNvlinkP2pSupported_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, OBJGPU *pPeerGpu); +NvBool knvlinkIsNvlinkP2pSupported_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, struct OBJGPU *pPeerGpu); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NvBool knvlinkIsNvlinkP2pSupported(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, OBJGPU *pPeerGpu) { +static inline NvBool knvlinkIsNvlinkP2pSupported(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, struct OBJGPU *pPeerGpu) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_FALSE; } @@ -532,11 +651,11 @@ static inline NvBool knvlinkIsNvlinkP2pSupported(OBJGPU *pGpu, struct KernelNvli #define knvlinkIsNvlinkP2pSupported_HAL(pGpu, pKernelNvlink, pPeerGpu) knvlinkIsNvlinkP2pSupported(pGpu, pKernelNvlink, pPeerGpu) -NvBool knvlinkCheckNvswitchP2pConfig_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, OBJGPU *pPeerGpu); +NvBool knvlinkCheckNvswitchP2pConfig_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, struct OBJGPU *pPeerGpu); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NvBool knvlinkCheckNvswitchP2pConfig(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, OBJGPU *pPeerGpu) { +static inline NvBool knvlinkCheckNvswitchP2pConfig(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, struct OBJGPU *pPeerGpu) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_FALSE; } @@ -546,11 +665,11 @@ static inline NvBool knvlinkCheckNvswitchP2pConfig(OBJGPU *pGpu, struct KernelNv #define knvlinkCheckNvswitchP2pConfig_HAL(pGpu, pKernelNvlink, pPeerGpu) knvlinkCheckNvswitchP2pConfig(pGpu, pKernelNvlink, pPeerGpu) -NV_STATUS knvlinkGetP2pConnectionStatus_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, OBJGPU *pPeerGpu); +NV_STATUS knvlinkGetP2pConnectionStatus_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, struct OBJGPU *pPeerGpu); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkGetP2pConnectionStatus(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, OBJGPU *pPeerGpu) { +static inline NV_STATUS knvlinkGetP2pConnectionStatus(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, struct OBJGPU *pPeerGpu) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -560,11 +679,11 @@ static inline NV_STATUS knvlinkGetP2pConnectionStatus(OBJGPU *pGpu, struct Kerne #define knvlinkGetP2pConnectionStatus_HAL(pGpu, pKernelNvlink, pPeerGpu) knvlinkGetP2pConnectionStatus(pGpu, pKernelNvlink, pPeerGpu) -NV_STATUS knvlinkUpdateCurrentConfig_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); +NV_STATUS knvlinkUpdateCurrentConfig_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkUpdateCurrentConfig(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NV_STATUS knvlinkUpdateCurrentConfig(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -574,11 +693,11 @@ static inline NV_STATUS knvlinkUpdateCurrentConfig(OBJGPU *pGpu, struct KernelNv #define knvlinkUpdateCurrentConfig_HAL(pGpu, pKernelNvlink) knvlinkUpdateCurrentConfig(pGpu, pKernelNvlink) -void knvlinkCoreDriverLoadWar_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); +void knvlinkCoreDriverLoadWar_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline void knvlinkCoreDriverLoadWar(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline void knvlinkCoreDriverLoadWar(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); } #else //__nvoc_kernel_nvlink_h_disabled @@ -587,11 +706,11 @@ static inline void knvlinkCoreDriverLoadWar(OBJGPU *pGpu, struct KernelNvlink *p #define knvlinkCoreDriverLoadWar_HAL(pGpu, pKernelNvlink) knvlinkCoreDriverLoadWar(pGpu, pKernelNvlink) -void knvlinkCoreDriverUnloadWar_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); +void knvlinkCoreDriverUnloadWar_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline void knvlinkCoreDriverUnloadWar(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline void knvlinkCoreDriverUnloadWar(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); } #else //__nvoc_kernel_nvlink_h_disabled @@ -600,11 +719,11 @@ static inline void knvlinkCoreDriverUnloadWar(OBJGPU *pGpu, struct KernelNvlink #define knvlinkCoreDriverUnloadWar_HAL(pGpu, pKernelNvlink) knvlinkCoreDriverUnloadWar(pGpu, pKernelNvlink) -NV_STATUS knvlinkCoreIsDriverSupported_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); +NV_STATUS knvlinkCoreIsDriverSupported_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkCoreIsDriverSupported(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NV_STATUS knvlinkCoreIsDriverSupported(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -614,11 +733,11 @@ static inline NV_STATUS knvlinkCoreIsDriverSupported(OBJGPU *pGpu, struct Kernel #define knvlinkCoreIsDriverSupported_HAL(pGpu, pKernelNvlink) knvlinkCoreIsDriverSupported(pGpu, pKernelNvlink) -NV_STATUS knvlinkCoreAddDevice_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); +NV_STATUS knvlinkCoreAddDevice_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkCoreAddDevice(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NV_STATUS knvlinkCoreAddDevice(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -628,11 +747,11 @@ static inline NV_STATUS knvlinkCoreAddDevice(OBJGPU *pGpu, struct KernelNvlink * #define knvlinkCoreAddDevice_HAL(pGpu, pKernelNvlink) knvlinkCoreAddDevice(pGpu, pKernelNvlink) -NV_STATUS knvlinkCoreAddLink_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0); +NV_STATUS knvlinkCoreAddLink_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkCoreAddLink(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0) { +static inline NV_STATUS knvlinkCoreAddLink(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -642,11 +761,11 @@ static inline NV_STATUS knvlinkCoreAddLink(OBJGPU *pGpu, struct KernelNvlink *pK #define knvlinkCoreAddLink_HAL(pGpu, pKernelNvlink, arg0) knvlinkCoreAddLink(pGpu, pKernelNvlink, arg0) -NV_STATUS knvlinkCoreRemoveDevice_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); +NV_STATUS knvlinkCoreRemoveDevice_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkCoreRemoveDevice(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NV_STATUS knvlinkCoreRemoveDevice(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -656,11 +775,11 @@ static inline NV_STATUS knvlinkCoreRemoveDevice(OBJGPU *pGpu, struct KernelNvlin #define knvlinkCoreRemoveDevice_HAL(pGpu, pKernelNvlink) knvlinkCoreRemoveDevice(pGpu, pKernelNvlink) -void knvlinkSetDegradedMode_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0); +void knvlinkSetDegradedMode_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline void knvlinkSetDegradedMode(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0) { +static inline void knvlinkSetDegradedMode(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); } #else //__nvoc_kernel_nvlink_h_disabled @@ -669,11 +788,11 @@ static inline void knvlinkSetDegradedMode(OBJGPU *pGpu, struct KernelNvlink *pKe #define knvlinkSetDegradedMode_HAL(pGpu, pKernelNvlink, arg0) knvlinkSetDegradedMode(pGpu, pKernelNvlink, arg0) -NV_STATUS knvlinkCoreRemoveLink_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0); +NV_STATUS knvlinkCoreRemoveLink_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkCoreRemoveLink(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0) { +static inline NV_STATUS knvlinkCoreRemoveLink(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -683,11 +802,11 @@ static inline NV_STATUS knvlinkCoreRemoveLink(OBJGPU *pGpu, struct KernelNvlink #define knvlinkCoreRemoveLink_HAL(pGpu, pKernelNvlink, arg0) knvlinkCoreRemoveLink(pGpu, pKernelNvlink, arg0) -NV_STATUS knvlinkCoreShutdownDeviceLinks_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvBool bForcePowerDown); +NV_STATUS knvlinkCoreShutdownDeviceLinks_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvBool bForcePowerDown); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkCoreShutdownDeviceLinks(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvBool bForcePowerDown) { +static inline NV_STATUS knvlinkCoreShutdownDeviceLinks(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvBool bForcePowerDown) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -697,11 +816,11 @@ static inline NV_STATUS knvlinkCoreShutdownDeviceLinks(OBJGPU *pGpu, struct Kern #define knvlinkCoreShutdownDeviceLinks_HAL(pGpu, pKernelNvlink, bForcePowerDown) knvlinkCoreShutdownDeviceLinks(pGpu, pKernelNvlink, bForcePowerDown) -NV_STATUS knvlinkCoreResetDeviceLinks_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); +NV_STATUS knvlinkCoreResetDeviceLinks_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkCoreResetDeviceLinks(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NV_STATUS knvlinkCoreResetDeviceLinks(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -711,11 +830,11 @@ static inline NV_STATUS knvlinkCoreResetDeviceLinks(OBJGPU *pGpu, struct KernelN #define knvlinkCoreResetDeviceLinks_HAL(pGpu, pKernelNvlink) knvlinkCoreResetDeviceLinks(pGpu, pKernelNvlink) -NV_STATUS knvlinkCoreUpdateDeviceUUID_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); +NV_STATUS knvlinkCoreUpdateDeviceUUID_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkCoreUpdateDeviceUUID(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NV_STATUS knvlinkCoreUpdateDeviceUUID(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -725,11 +844,11 @@ static inline NV_STATUS knvlinkCoreUpdateDeviceUUID(OBJGPU *pGpu, struct KernelN #define knvlinkCoreUpdateDeviceUUID_HAL(pGpu, pKernelNvlink) knvlinkCoreUpdateDeviceUUID(pGpu, pKernelNvlink) -NV_STATUS knvlinkRegisterInbandCallback_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NVLINK_INBAND_MSG_CALLBACK *params); +NV_STATUS knvlinkRegisterInbandCallback_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NVLINK_INBAND_MSG_CALLBACK *params); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkRegisterInbandCallback(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NVLINK_INBAND_MSG_CALLBACK *params) { +static inline NV_STATUS knvlinkRegisterInbandCallback(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NVLINK_INBAND_MSG_CALLBACK *params) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -739,11 +858,11 @@ static inline NV_STATUS knvlinkRegisterInbandCallback(OBJGPU *pGpu, struct Kerne #define knvlinkRegisterInbandCallback_HAL(pGpu, pKernelNvlink, params) knvlinkRegisterInbandCallback(pGpu, pKernelNvlink, params) -NV_STATUS knvlinkUnregisterInbandCallback_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU16 msgType); +NV_STATUS knvlinkUnregisterInbandCallback_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU16 msgType); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkUnregisterInbandCallback(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU16 msgType) { +static inline NV_STATUS knvlinkUnregisterInbandCallback(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU16 msgType) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -753,11 +872,11 @@ static inline NV_STATUS knvlinkUnregisterInbandCallback(OBJGPU *pGpu, struct Ker #define knvlinkUnregisterInbandCallback_HAL(pGpu, pKernelNvlink, msgType) knvlinkUnregisterInbandCallback(pGpu, pKernelNvlink, msgType) -NV_STATUS knvlinkCoreGetRemoteDeviceInfo_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); +NV_STATUS knvlinkCoreGetRemoteDeviceInfo_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkCoreGetRemoteDeviceInfo(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NV_STATUS knvlinkCoreGetRemoteDeviceInfo(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -767,11 +886,11 @@ static inline NV_STATUS knvlinkCoreGetRemoteDeviceInfo(OBJGPU *pGpu, struct Kern #define knvlinkCoreGetRemoteDeviceInfo_HAL(pGpu, pKernelNvlink) knvlinkCoreGetRemoteDeviceInfo(pGpu, pKernelNvlink) -NvBool knvlinkIsGpuConnectedToNvswitch_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); +NvBool knvlinkIsGpuConnectedToNvswitch_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NvBool knvlinkIsGpuConnectedToNvswitch(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NvBool knvlinkIsGpuConnectedToNvswitch(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_FALSE; } @@ -781,11 +900,11 @@ static inline NvBool knvlinkIsGpuConnectedToNvswitch(OBJGPU *pGpu, struct Kernel #define knvlinkIsGpuConnectedToNvswitch_HAL(pGpu, pKernelNvlink) knvlinkIsGpuConnectedToNvswitch(pGpu, pKernelNvlink) -NvBool knvlinkIsLinkConnected_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0); +NvBool knvlinkIsLinkConnected_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NvBool knvlinkIsLinkConnected(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0) { +static inline NvBool knvlinkIsLinkConnected(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_FALSE; } @@ -795,11 +914,11 @@ static inline NvBool knvlinkIsLinkConnected(OBJGPU *pGpu, struct KernelNvlink *p #define knvlinkIsLinkConnected_HAL(pGpu, pKernelNvlink, arg0) knvlinkIsLinkConnected(pGpu, pKernelNvlink, arg0) -NV_STATUS knvlinkTrainSysmemLinksToActive_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); +NV_STATUS knvlinkTrainSysmemLinksToActive_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkTrainSysmemLinksToActive(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NV_STATUS knvlinkTrainSysmemLinksToActive(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -809,11 +928,11 @@ static inline NV_STATUS knvlinkTrainSysmemLinksToActive(OBJGPU *pGpu, struct Ker #define knvlinkTrainSysmemLinksToActive_HAL(pGpu, pKernelNvlink) knvlinkTrainSysmemLinksToActive(pGpu, pKernelNvlink) -NV_STATUS knvlinkTrainP2pLinksToActive_IMPL(OBJGPU *pGpu0, OBJGPU *pGpu1, struct KernelNvlink *pKernelNvlink); +NV_STATUS knvlinkTrainP2pLinksToActive_IMPL(struct OBJGPU *pGpu0, struct OBJGPU *pGpu1, struct KernelNvlink *pKernelNvlink); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkTrainP2pLinksToActive(OBJGPU *pGpu0, OBJGPU *pGpu1, struct KernelNvlink *pKernelNvlink) { +static inline NV_STATUS knvlinkTrainP2pLinksToActive(struct OBJGPU *pGpu0, struct OBJGPU *pGpu1, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -823,11 +942,11 @@ static inline NV_STATUS knvlinkTrainP2pLinksToActive(OBJGPU *pGpu0, OBJGPU *pGpu #define knvlinkTrainP2pLinksToActive_HAL(pGpu0, pGpu1, pKernelNvlink) knvlinkTrainP2pLinksToActive(pGpu0, pGpu1, pKernelNvlink) -NV_STATUS knvlinkCheckTrainingIsComplete_IMPL(OBJGPU *pGpu0, OBJGPU *pGpu1, struct KernelNvlink *pKernelNvlink); +NV_STATUS knvlinkCheckTrainingIsComplete_IMPL(struct OBJGPU *pGpu0, struct OBJGPU *pGpu1, struct KernelNvlink *pKernelNvlink); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkCheckTrainingIsComplete(OBJGPU *pGpu0, OBJGPU *pGpu1, struct KernelNvlink *pKernelNvlink) { +static inline NV_STATUS knvlinkCheckTrainingIsComplete(struct OBJGPU *pGpu0, struct OBJGPU *pGpu1, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -837,11 +956,11 @@ static inline NV_STATUS knvlinkCheckTrainingIsComplete(OBJGPU *pGpu0, OBJGPU *pG #define knvlinkCheckTrainingIsComplete_HAL(pGpu0, pGpu1, pKernelNvlink) knvlinkCheckTrainingIsComplete(pGpu0, pGpu1, pKernelNvlink) -NV_STATUS knvlinkTrainFabricLinksToActive_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); +NV_STATUS knvlinkTrainFabricLinksToActive_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkTrainFabricLinksToActive(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NV_STATUS knvlinkTrainFabricLinksToActive(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -851,11 +970,11 @@ static inline NV_STATUS knvlinkTrainFabricLinksToActive(OBJGPU *pGpu, struct Ker #define knvlinkTrainFabricLinksToActive_HAL(pGpu, pKernelNvlink) knvlinkTrainFabricLinksToActive(pGpu, pKernelNvlink) -NV_STATUS knvlinkRetrainLink_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 linkId, NvBool bFromOff); +NV_STATUS knvlinkRetrainLink_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 linkId, NvBool bFromOff); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkRetrainLink(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 linkId, NvBool bFromOff) { +static inline NV_STATUS knvlinkRetrainLink(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 linkId, NvBool bFromOff) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -865,11 +984,11 @@ static inline NV_STATUS knvlinkRetrainLink(OBJGPU *pGpu, struct KernelNvlink *pK #define knvlinkRetrainLink_HAL(pGpu, pKernelNvlink, linkId, bFromOff) knvlinkRetrainLink(pGpu, pKernelNvlink, linkId, bFromOff) -NvU32 knvlinkGetEnabledLinkMask_IMPL(OBJGPU *pGpu, struct KernelNvlink *arg0); +NvU32 knvlinkGetEnabledLinkMask_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *arg0); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NvU32 knvlinkGetEnabledLinkMask(OBJGPU *pGpu, struct KernelNvlink *arg0) { +static inline NvU32 knvlinkGetEnabledLinkMask(struct OBJGPU *pGpu, struct KernelNvlink *arg0) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return 0; } @@ -879,11 +998,11 @@ static inline NvU32 knvlinkGetEnabledLinkMask(OBJGPU *pGpu, struct KernelNvlink #define knvlinkGetEnabledLinkMask_HAL(pGpu, arg0) knvlinkGetEnabledLinkMask(pGpu, arg0) -NvU32 knvlinkGetDiscoveredLinkMask_IMPL(OBJGPU *pGpu, struct KernelNvlink *arg0); +NvU32 knvlinkGetDiscoveredLinkMask_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *arg0); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NvU32 knvlinkGetDiscoveredLinkMask(OBJGPU *pGpu, struct KernelNvlink *arg0) { +static inline NvU32 knvlinkGetDiscoveredLinkMask(struct OBJGPU *pGpu, struct KernelNvlink *arg0) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return 0; } @@ -893,11 +1012,11 @@ static inline NvU32 knvlinkGetDiscoveredLinkMask(OBJGPU *pGpu, struct KernelNvli #define knvlinkGetDiscoveredLinkMask_HAL(pGpu, arg0) knvlinkGetDiscoveredLinkMask(pGpu, arg0) -NV_STATUS knvlinkProcessInitDisabledLinks_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); +NV_STATUS knvlinkProcessInitDisabledLinks_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkProcessInitDisabledLinks(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NV_STATUS knvlinkProcessInitDisabledLinks(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -907,11 +1026,11 @@ static inline NV_STATUS knvlinkProcessInitDisabledLinks(OBJGPU *pGpu, struct Ker #define knvlinkProcessInitDisabledLinks_HAL(pGpu, pKernelNvlink) knvlinkProcessInitDisabledLinks(pGpu, pKernelNvlink) -NvU32 knvlinkGetNumLinksToSystem_IMPL(OBJGPU *arg0, struct KernelNvlink *arg1); +NvU32 knvlinkGetNumLinksToSystem_IMPL(struct OBJGPU *arg0, struct KernelNvlink *arg1); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NvU32 knvlinkGetNumLinksToSystem(OBJGPU *arg0, struct KernelNvlink *arg1) { +static inline NvU32 knvlinkGetNumLinksToSystem(struct OBJGPU *arg0, struct KernelNvlink *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return 0; } @@ -921,11 +1040,11 @@ static inline NvU32 knvlinkGetNumLinksToSystem(OBJGPU *arg0, struct KernelNvlink #define knvlinkGetNumLinksToSystem_HAL(arg0, arg1) knvlinkGetNumLinksToSystem(arg0, arg1) -NvU32 knvlinkGetNumLinksToPeer_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, OBJGPU *pRemoteGpu); +NvU32 knvlinkGetNumLinksToPeer_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, struct OBJGPU *pRemoteGpu); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NvU32 knvlinkGetNumLinksToPeer(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, OBJGPU *pRemoteGpu) { +static inline NvU32 knvlinkGetNumLinksToPeer(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, struct OBJGPU *pRemoteGpu) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return 0; } @@ -935,11 +1054,11 @@ static inline NvU32 knvlinkGetNumLinksToPeer(OBJGPU *pGpu, struct KernelNvlink * #define knvlinkGetNumLinksToPeer_HAL(pGpu, pKernelNvlink, pRemoteGpu) knvlinkGetNumLinksToPeer(pGpu, pKernelNvlink, pRemoteGpu) -NvU32 knvlinkGetLinkMaskToPeer_IMPL(OBJGPU *pGpu0, struct KernelNvlink *pKernelNvlink0, OBJGPU *pGpu1); +NvU32 knvlinkGetLinkMaskToPeer_IMPL(struct OBJGPU *pGpu0, struct KernelNvlink *pKernelNvlink0, struct OBJGPU *pGpu1); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NvU32 knvlinkGetLinkMaskToPeer(OBJGPU *pGpu0, struct KernelNvlink *pKernelNvlink0, OBJGPU *pGpu1) { +static inline NvU32 knvlinkGetLinkMaskToPeer(struct OBJGPU *pGpu0, struct KernelNvlink *pKernelNvlink0, struct OBJGPU *pGpu1) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return 0; } @@ -949,11 +1068,11 @@ static inline NvU32 knvlinkGetLinkMaskToPeer(OBJGPU *pGpu0, struct KernelNvlink #define knvlinkGetLinkMaskToPeer_HAL(pGpu0, pKernelNvlink0, pGpu1) knvlinkGetLinkMaskToPeer(pGpu0, pKernelNvlink0, pGpu1) -NV_STATUS knvlinkSetLinkMaskToPeer_IMPL(OBJGPU *pGpu0, struct KernelNvlink *pKernelNvlink0, OBJGPU *pGpu1, NvU32 peerLinkMask); +NV_STATUS knvlinkSetLinkMaskToPeer_IMPL(struct OBJGPU *pGpu0, struct KernelNvlink *pKernelNvlink0, struct OBJGPU *pGpu1, NvU32 peerLinkMask); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkSetLinkMaskToPeer(OBJGPU *pGpu0, struct KernelNvlink *pKernelNvlink0, OBJGPU *pGpu1, NvU32 peerLinkMask) { +static inline NV_STATUS knvlinkSetLinkMaskToPeer(struct OBJGPU *pGpu0, struct KernelNvlink *pKernelNvlink0, struct OBJGPU *pGpu1, NvU32 peerLinkMask) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -963,11 +1082,11 @@ static inline NV_STATUS knvlinkSetLinkMaskToPeer(OBJGPU *pGpu0, struct KernelNvl #define knvlinkSetLinkMaskToPeer_HAL(pGpu0, pKernelNvlink0, pGpu1, peerLinkMask) knvlinkSetLinkMaskToPeer(pGpu0, pKernelNvlink0, pGpu1, peerLinkMask) -NvU32 knvlinkGetPeersNvlinkMaskFromHshub_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); +NvU32 knvlinkGetPeersNvlinkMaskFromHshub_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NvU32 knvlinkGetPeersNvlinkMaskFromHshub(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NvU32 knvlinkGetPeersNvlinkMaskFromHshub(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return 0; } @@ -977,11 +1096,11 @@ static inline NvU32 knvlinkGetPeersNvlinkMaskFromHshub(OBJGPU *pGpu, struct Kern #define knvlinkGetPeersNvlinkMaskFromHshub_HAL(pGpu, pKernelNvlink) knvlinkGetPeersNvlinkMaskFromHshub(pGpu, pKernelNvlink) -NV_STATUS knvlinkPrepareForXVEReset_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvBool bForcePowerDown); +NV_STATUS knvlinkPrepareForXVEReset_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvBool bForcePowerDown); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkPrepareForXVEReset(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvBool bForcePowerDown) { +static inline NV_STATUS knvlinkPrepareForXVEReset(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvBool bForcePowerDown) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -991,11 +1110,11 @@ static inline NV_STATUS knvlinkPrepareForXVEReset(OBJGPU *pGpu, struct KernelNvl #define knvlinkPrepareForXVEReset_HAL(pGpu, pKernelNvlink, bForcePowerDown) knvlinkPrepareForXVEReset(pGpu, pKernelNvlink, bForcePowerDown) -NV_STATUS knvlinkEnterExitSleep_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0, NvBool arg1); +NV_STATUS knvlinkEnterExitSleep_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0, NvBool arg1); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkEnterExitSleep(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0, NvBool arg1) { +static inline NV_STATUS knvlinkEnterExitSleep(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0, NvBool arg1) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1005,11 +1124,11 @@ static inline NV_STATUS knvlinkEnterExitSleep(OBJGPU *pGpu, struct KernelNvlink #define knvlinkEnterExitSleep_HAL(pGpu, pKernelNvlink, arg0, arg1) knvlinkEnterExitSleep(pGpu, pKernelNvlink, arg0, arg1) -NV_STATUS knvlinkSyncLinkMasksAndVbiosInfo_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); +NV_STATUS knvlinkSyncLinkMasksAndVbiosInfo_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkSyncLinkMasksAndVbiosInfo(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NV_STATUS knvlinkSyncLinkMasksAndVbiosInfo(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1019,11 +1138,11 @@ static inline NV_STATUS knvlinkSyncLinkMasksAndVbiosInfo(OBJGPU *pGpu, struct Ke #define knvlinkSyncLinkMasksAndVbiosInfo_HAL(pGpu, pKernelNvlink) knvlinkSyncLinkMasksAndVbiosInfo(pGpu, pKernelNvlink) -NV_STATUS knvlinkInbandMsgCallbackDispatcher_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvLink, NvU32 dataSize, NvU8 *pMessage); +NV_STATUS knvlinkInbandMsgCallbackDispatcher_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvLink, NvU32 dataSize, NvU8 *pMessage); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkInbandMsgCallbackDispatcher(OBJGPU *pGpu, struct KernelNvlink *pKernelNvLink, NvU32 dataSize, NvU8 *pMessage) { +static inline NV_STATUS knvlinkInbandMsgCallbackDispatcher(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvLink, NvU32 dataSize, NvU8 *pMessage) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1033,11 +1152,11 @@ static inline NV_STATUS knvlinkInbandMsgCallbackDispatcher(OBJGPU *pGpu, struct #define knvlinkInbandMsgCallbackDispatcher_HAL(pGpu, pKernelNvLink, dataSize, pMessage) knvlinkInbandMsgCallbackDispatcher(pGpu, pKernelNvLink, dataSize, pMessage) -NV_STATUS knvlinkSendInbandData_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS *pParams); +NV_STATUS knvlinkSendInbandData_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS *pParams); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkSendInbandData(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS *pParams) { +static inline NV_STATUS knvlinkSendInbandData(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS *pParams) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1047,11 +1166,11 @@ static inline NV_STATUS knvlinkSendInbandData(OBJGPU *pGpu, struct KernelNvlink #define knvlinkSendInbandData_HAL(pGpu, pKernelNvlink, pParams) knvlinkSendInbandData(pGpu, pKernelNvlink, pParams) -NV_STATUS knvlinkUpdateLinkConnectionStatus_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0); +NV_STATUS knvlinkUpdateLinkConnectionStatus_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkUpdateLinkConnectionStatus(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0) { +static inline NV_STATUS knvlinkUpdateLinkConnectionStatus(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1061,11 +1180,11 @@ static inline NV_STATUS knvlinkUpdateLinkConnectionStatus(OBJGPU *pGpu, struct K #define knvlinkUpdateLinkConnectionStatus_HAL(pGpu, pKernelNvlink, arg0) knvlinkUpdateLinkConnectionStatus(pGpu, pKernelNvlink, arg0) -NV_STATUS knvlinkPreTrainLinksToActiveAli_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0, NvBool arg1); +NV_STATUS knvlinkPreTrainLinksToActiveAli_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0, NvBool arg1); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkPreTrainLinksToActiveAli(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0, NvBool arg1) { +static inline NV_STATUS knvlinkPreTrainLinksToActiveAli(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0, NvBool arg1) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1075,11 +1194,11 @@ static inline NV_STATUS knvlinkPreTrainLinksToActiveAli(OBJGPU *pGpu, struct Ker #define knvlinkPreTrainLinksToActiveAli_HAL(pGpu, pKernelNvlink, arg0, arg1) knvlinkPreTrainLinksToActiveAli(pGpu, pKernelNvlink, arg0, arg1) -NV_STATUS knvlinkTrainLinksToActiveAli_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0, NvBool arg1); +NV_STATUS knvlinkTrainLinksToActiveAli_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0, NvBool arg1); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkTrainLinksToActiveAli(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0, NvBool arg1) { +static inline NV_STATUS knvlinkTrainLinksToActiveAli(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0, NvBool arg1) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1089,11 +1208,11 @@ static inline NV_STATUS knvlinkTrainLinksToActiveAli(OBJGPU *pGpu, struct Kernel #define knvlinkTrainLinksToActiveAli_HAL(pGpu, pKernelNvlink, arg0, arg1) knvlinkTrainLinksToActiveAli(pGpu, pKernelNvlink, arg0, arg1) -NV_STATUS knvlinkUpdatePostRxDetectLinkMask_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); +NV_STATUS knvlinkUpdatePostRxDetectLinkMask_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkUpdatePostRxDetectLinkMask(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NV_STATUS knvlinkUpdatePostRxDetectLinkMask(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1103,11 +1222,11 @@ static inline NV_STATUS knvlinkUpdatePostRxDetectLinkMask(OBJGPU *pGpu, struct K #define knvlinkUpdatePostRxDetectLinkMask_HAL(pGpu, pKernelNvlink) knvlinkUpdatePostRxDetectLinkMask(pGpu, pKernelNvlink) -NV_STATUS knvlinkCopyNvlinkDeviceInfo_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); +NV_STATUS knvlinkCopyNvlinkDeviceInfo_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkCopyNvlinkDeviceInfo(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NV_STATUS knvlinkCopyNvlinkDeviceInfo(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1117,11 +1236,11 @@ static inline NV_STATUS knvlinkCopyNvlinkDeviceInfo(OBJGPU *pGpu, struct KernelN #define knvlinkCopyNvlinkDeviceInfo_HAL(pGpu, pKernelNvlink) knvlinkCopyNvlinkDeviceInfo(pGpu, pKernelNvlink) -NV_STATUS knvlinkCopyIoctrlDeviceInfo_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); +NV_STATUS knvlinkCopyIoctrlDeviceInfo_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkCopyIoctrlDeviceInfo(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NV_STATUS knvlinkCopyIoctrlDeviceInfo(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1131,11 +1250,11 @@ static inline NV_STATUS knvlinkCopyIoctrlDeviceInfo(OBJGPU *pGpu, struct KernelN #define knvlinkCopyIoctrlDeviceInfo_HAL(pGpu, pKernelNvlink) knvlinkCopyIoctrlDeviceInfo(pGpu, pKernelNvlink) -NV_STATUS knvlinkSetupTopologyForForcedConfig_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); +NV_STATUS knvlinkSetupTopologyForForcedConfig_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkSetupTopologyForForcedConfig(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NV_STATUS knvlinkSetupTopologyForForcedConfig(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1145,11 +1264,11 @@ static inline NV_STATUS knvlinkSetupTopologyForForcedConfig(OBJGPU *pGpu, struct #define knvlinkSetupTopologyForForcedConfig_HAL(pGpu, pKernelNvlink) knvlinkSetupTopologyForForcedConfig(pGpu, pKernelNvlink) -NV_STATUS knvlinkSyncLaneShutdownProps_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); +NV_STATUS knvlinkSyncLaneShutdownProps_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkSyncLaneShutdownProps(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NV_STATUS knvlinkSyncLaneShutdownProps(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1159,11 +1278,11 @@ static inline NV_STATUS knvlinkSyncLaneShutdownProps(OBJGPU *pGpu, struct Kernel #define knvlinkSyncLaneShutdownProps_HAL(pGpu, pKernelNvlink) knvlinkSyncLaneShutdownProps(pGpu, pKernelNvlink) -void knvlinkSetPowerFeatures_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); +void knvlinkSetPowerFeatures_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline void knvlinkSetPowerFeatures(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline void knvlinkSetPowerFeatures(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); } #else //__nvoc_kernel_nvlink_h_disabled @@ -1172,11 +1291,11 @@ static inline void knvlinkSetPowerFeatures(OBJGPU *pGpu, struct KernelNvlink *pK #define knvlinkSetPowerFeatures_HAL(pGpu, pKernelNvlink) knvlinkSetPowerFeatures(pGpu, pKernelNvlink) -NV_STATUS knvlinkExecGspRmRpc_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0, void *arg1, NvU32 arg2); +NV_STATUS knvlinkExecGspRmRpc_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0, void *arg1, NvU32 arg2); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkExecGspRmRpc(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0, void *arg1, NvU32 arg2) { +static inline NV_STATUS knvlinkExecGspRmRpc(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0, void *arg1, NvU32 arg2) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1186,11 +1305,11 @@ static inline NV_STATUS knvlinkExecGspRmRpc(OBJGPU *pGpu, struct KernelNvlink *p #define knvlinkExecGspRmRpc_HAL(pGpu, pKernelNvlink, arg0, arg1, arg2) knvlinkExecGspRmRpc(pGpu, pKernelNvlink, arg0, arg1, arg2) -NvBool knvlinkIsNvswitchProxyPresent_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); +NvBool knvlinkIsNvswitchProxyPresent_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NvBool knvlinkIsNvswitchProxyPresent(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NvBool knvlinkIsNvswitchProxyPresent(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_FALSE; } @@ -1200,11 +1319,11 @@ static inline NvBool knvlinkIsNvswitchProxyPresent(OBJGPU *pGpu, struct KernelNv #define knvlinkIsNvswitchProxyPresent_HAL(pGpu, pKernelNvlink) knvlinkIsNvswitchProxyPresent(pGpu, pKernelNvlink) -void knvlinkDetectNvswitchProxy_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); +void knvlinkDetectNvswitchProxy_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline void knvlinkDetectNvswitchProxy(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline void knvlinkDetectNvswitchProxy(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); } #else //__nvoc_kernel_nvlink_h_disabled @@ -1213,11 +1332,11 @@ static inline void knvlinkDetectNvswitchProxy(OBJGPU *pGpu, struct KernelNvlink #define knvlinkDetectNvswitchProxy_HAL(pGpu, pKernelNvlink) knvlinkDetectNvswitchProxy(pGpu, pKernelNvlink) -NV_STATUS knvlinkSetUniqueFlaBaseAddress_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU64 arg0); +NV_STATUS knvlinkSetUniqueFlaBaseAddress_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU64 arg0); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkSetUniqueFlaBaseAddress(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU64 arg0) { +static inline NV_STATUS knvlinkSetUniqueFlaBaseAddress(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU64 arg0) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1227,11 +1346,11 @@ static inline NV_STATUS knvlinkSetUniqueFlaBaseAddress(OBJGPU *pGpu, struct Kern #define knvlinkSetUniqueFlaBaseAddress_HAL(pGpu, pKernelNvlink, arg0) knvlinkSetUniqueFlaBaseAddress(pGpu, pKernelNvlink, arg0) -NV_STATUS knvlinkFloorSweep_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 numLinksPerIp, NvU32 *pNumActiveLinks); +NV_STATUS knvlinkFloorSweep_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 numLinksPerIp, NvU32 *pNumActiveLinks); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkFloorSweep(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 numLinksPerIp, NvU32 *pNumActiveLinks) { +static inline NV_STATUS knvlinkFloorSweep(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 numLinksPerIp, NvU32 *pNumActiveLinks) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1241,27 +1360,28 @@ static inline NV_STATUS knvlinkFloorSweep(OBJGPU *pGpu, struct KernelNvlink *pKe #define knvlinkFloorSweep_HAL(pGpu, pKernelNvlink, numLinksPerIp, pNumActiveLinks) knvlinkFloorSweep(pGpu, pKernelNvlink, numLinksPerIp, pNumActiveLinks) -static inline NvU64 knvlinkGetUniqueFabricBaseAddress_72249a(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { - return pKernelNvlink->fabricBaseAddr; +static inline NvU64 knvlinkGetUniqueFabricBaseAddress_e203db(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { + struct KernelNvlink_PRIVATE *pKernelNvlink_PRIVATE = (struct KernelNvlink_PRIVATE *)pKernelNvlink; + return pKernelNvlink_PRIVATE->fabricBaseAddr; } #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NvU64 knvlinkGetUniqueFabricBaseAddress(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NvU64 knvlinkGetUniqueFabricBaseAddress(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return 0; } #else //__nvoc_kernel_nvlink_h_disabled -#define knvlinkGetUniqueFabricBaseAddress(pGpu, pKernelNvlink) knvlinkGetUniqueFabricBaseAddress_72249a(pGpu, pKernelNvlink) +#define knvlinkGetUniqueFabricBaseAddress(pGpu, pKernelNvlink) knvlinkGetUniqueFabricBaseAddress_e203db(pGpu, pKernelNvlink) #endif //__nvoc_kernel_nvlink_h_disabled #define knvlinkGetUniqueFabricBaseAddress_HAL(pGpu, pKernelNvlink) knvlinkGetUniqueFabricBaseAddress(pGpu, pKernelNvlink) -NV_STATUS knvlinkStatePostLoadHal_GV100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); +NV_STATUS knvlinkStatePostLoadHal_GV100(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkStatePostLoadHal(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NV_STATUS knvlinkStatePostLoadHal(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1271,11 +1391,11 @@ static inline NV_STATUS knvlinkStatePostLoadHal(OBJGPU *pGpu, struct KernelNvlin #define knvlinkStatePostLoadHal_HAL(pGpu, pKernelNvlink) knvlinkStatePostLoadHal(pGpu, pKernelNvlink) -NV_STATUS knvlinkApplyNvswitchDegradedModeSettings_GV100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 *switchLinkMasks); +NV_STATUS knvlinkApplyNvswitchDegradedModeSettings_GV100(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 *switchLinkMasks); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkApplyNvswitchDegradedModeSettings(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 *switchLinkMasks) { +static inline NV_STATUS knvlinkApplyNvswitchDegradedModeSettings(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 *switchLinkMasks) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1285,11 +1405,11 @@ static inline NV_STATUS knvlinkApplyNvswitchDegradedModeSettings(OBJGPU *pGpu, s #define knvlinkApplyNvswitchDegradedModeSettings_HAL(pGpu, pKernelNvlink, switchLinkMasks) knvlinkApplyNvswitchDegradedModeSettings(pGpu, pKernelNvlink, switchLinkMasks) -NvU32 knvlinkGetNumActiveLinksPerIoctrl_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); +NvU32 knvlinkGetNumActiveLinksPerIoctrl_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NvU32 knvlinkGetNumActiveLinksPerIoctrl(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NvU32 knvlinkGetNumActiveLinksPerIoctrl(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return 0; } @@ -1299,11 +1419,11 @@ static inline NvU32 knvlinkGetNumActiveLinksPerIoctrl(OBJGPU *pGpu, struct Kerne #define knvlinkGetNumActiveLinksPerIoctrl_HAL(pGpu, pKernelNvlink) knvlinkGetNumActiveLinksPerIoctrl(pGpu, pKernelNvlink) -NvU32 knvlinkGetTotalNumLinksPerIoctrl_IMPL(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); +NvU32 knvlinkGetTotalNumLinksPerIoctrl_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NvU32 knvlinkGetTotalNumLinksPerIoctrl(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NvU32 knvlinkGetTotalNumLinksPerIoctrl(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return 0; } @@ -1313,274 +1433,287 @@ static inline NvU32 knvlinkGetTotalNumLinksPerIoctrl(OBJGPU *pGpu, struct Kernel #define knvlinkGetTotalNumLinksPerIoctrl_HAL(pGpu, pKernelNvlink) knvlinkGetTotalNumLinksPerIoctrl(pGpu, pKernelNvlink) -NV_STATUS knvlinkConstructEngine_IMPL(OBJGPU *arg0, struct KernelNvlink *arg1, ENGDESCRIPTOR arg2); +void knvlinkCoreGetDevicePciInfo_GP100(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, nvlink_device_info *devInfo); -static inline NV_STATUS knvlinkConstructEngine_DISPATCH(OBJGPU *arg0, struct KernelNvlink *arg1, ENGDESCRIPTOR arg2) { + +#ifdef __nvoc_kernel_nvlink_h_disabled +static inline void knvlinkCoreGetDevicePciInfo(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, nvlink_device_info *devInfo) { + NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); +} +#else //__nvoc_kernel_nvlink_h_disabled +#define knvlinkCoreGetDevicePciInfo(pGpu, pKernelNvlink, devInfo) knvlinkCoreGetDevicePciInfo_GP100(pGpu, pKernelNvlink, devInfo) +#endif //__nvoc_kernel_nvlink_h_disabled + +#define knvlinkCoreGetDevicePciInfo_HAL(pGpu, pKernelNvlink, devInfo) knvlinkCoreGetDevicePciInfo(pGpu, pKernelNvlink, devInfo) + +NV_STATUS knvlinkConstructEngine_IMPL(struct OBJGPU *arg0, struct KernelNvlink *arg1, ENGDESCRIPTOR arg2); + +static inline NV_STATUS knvlinkConstructEngine_DISPATCH(struct OBJGPU *arg0, struct KernelNvlink *arg1, ENGDESCRIPTOR arg2) { return arg1->__knvlinkConstructEngine__(arg0, arg1, arg2); } -NV_STATUS knvlinkStatePreInitLocked_IMPL(OBJGPU *arg0, struct KernelNvlink *arg1); +NV_STATUS knvlinkStatePreInitLocked_IMPL(struct OBJGPU *arg0, struct KernelNvlink *arg1); -static inline NV_STATUS knvlinkStatePreInitLocked_DISPATCH(OBJGPU *arg0, struct KernelNvlink *arg1) { +static inline NV_STATUS knvlinkStatePreInitLocked_DISPATCH(struct OBJGPU *arg0, struct KernelNvlink *arg1) { return arg1->__knvlinkStatePreInitLocked__(arg0, arg1); } -NV_STATUS knvlinkStateLoad_IMPL(OBJGPU *arg0, struct KernelNvlink *arg1, NvU32 arg2); +NV_STATUS knvlinkStateLoad_IMPL(struct OBJGPU *arg0, struct KernelNvlink *arg1, NvU32 arg2); -static inline NV_STATUS knvlinkStateLoad_DISPATCH(OBJGPU *arg0, struct KernelNvlink *arg1, NvU32 arg2) { +static inline NV_STATUS knvlinkStateLoad_DISPATCH(struct OBJGPU *arg0, struct KernelNvlink *arg1, NvU32 arg2) { return arg1->__knvlinkStateLoad__(arg0, arg1, arg2); } -NV_STATUS knvlinkStatePostLoad_IMPL(OBJGPU *arg0, struct KernelNvlink *arg1, NvU32 arg2); +NV_STATUS knvlinkStatePostLoad_IMPL(struct OBJGPU *arg0, struct KernelNvlink *arg1, NvU32 arg2); -static inline NV_STATUS knvlinkStatePostLoad_DISPATCH(OBJGPU *arg0, struct KernelNvlink *arg1, NvU32 arg2) { +static inline NV_STATUS knvlinkStatePostLoad_DISPATCH(struct OBJGPU *arg0, struct KernelNvlink *arg1, NvU32 arg2) { return arg1->__knvlinkStatePostLoad__(arg0, arg1, arg2); } -NV_STATUS knvlinkStateUnload_IMPL(OBJGPU *arg0, struct KernelNvlink *arg1, NvU32 arg2); +NV_STATUS knvlinkStateUnload_IMPL(struct OBJGPU *arg0, struct KernelNvlink *arg1, NvU32 arg2); -static inline NV_STATUS knvlinkStateUnload_DISPATCH(OBJGPU *arg0, struct KernelNvlink *arg1, NvU32 arg2) { +static inline NV_STATUS knvlinkStateUnload_DISPATCH(struct OBJGPU *arg0, struct KernelNvlink *arg1, NvU32 arg2) { return arg1->__knvlinkStateUnload__(arg0, arg1, arg2); } -NV_STATUS knvlinkStatePostUnload_IMPL(OBJGPU *arg0, struct KernelNvlink *arg1, NvU32 arg2); +NV_STATUS knvlinkStatePostUnload_IMPL(struct OBJGPU *arg0, struct KernelNvlink *arg1, NvU32 arg2); -static inline NV_STATUS knvlinkStatePostUnload_DISPATCH(OBJGPU *arg0, struct KernelNvlink *arg1, NvU32 arg2) { +static inline NV_STATUS knvlinkStatePostUnload_DISPATCH(struct OBJGPU *arg0, struct KernelNvlink *arg1, NvU32 arg2) { return arg1->__knvlinkStatePostUnload__(arg0, arg1, arg2); } -NvBool knvlinkIsPresent_IMPL(OBJGPU *arg0, struct KernelNvlink *arg1); +NvBool knvlinkIsPresent_IMPL(struct OBJGPU *arg0, struct KernelNvlink *arg1); -static inline NvBool knvlinkIsPresent_DISPATCH(OBJGPU *arg0, struct KernelNvlink *arg1) { +static inline NvBool knvlinkIsPresent_DISPATCH(struct OBJGPU *arg0, struct KernelNvlink *arg1) { return arg1->__knvlinkIsPresent__(arg0, arg1); } -NV_STATUS knvlinkSetUniqueFabricBaseAddress_GV100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU64 arg0); +NV_STATUS knvlinkSetUniqueFabricBaseAddress_GV100(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU64 arg0); -NV_STATUS knvlinkSetUniqueFabricBaseAddress_GH100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU64 arg0); +NV_STATUS knvlinkSetUniqueFabricBaseAddress_GH100(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU64 arg0); -static inline NV_STATUS knvlinkSetUniqueFabricBaseAddress_46f6a7(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU64 arg0) { +static inline NV_STATUS knvlinkSetUniqueFabricBaseAddress_46f6a7(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU64 arg0) { return NV_ERR_NOT_SUPPORTED; } -static inline NV_STATUS knvlinkSetUniqueFabricBaseAddress_DISPATCH(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU64 arg0) { +static inline NV_STATUS knvlinkSetUniqueFabricBaseAddress_DISPATCH(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU64 arg0) { return pKernelNvlink->__knvlinkSetUniqueFabricBaseAddress__(pGpu, pKernelNvlink, arg0); } -static inline void knvlinkClearUniqueFabricBaseAddress_b3696a(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline void knvlinkClearUniqueFabricBaseAddress_b3696a(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { return; } -void knvlinkClearUniqueFabricBaseAddress_GH100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); +void knvlinkClearUniqueFabricBaseAddress_GH100(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); -static inline void knvlinkClearUniqueFabricBaseAddress_DISPATCH(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline void knvlinkClearUniqueFabricBaseAddress_DISPATCH(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { pKernelNvlink->__knvlinkClearUniqueFabricBaseAddress__(pGpu, pKernelNvlink); } -NV_STATUS knvlinkHandleFaultUpInterrupt_GH100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0); +NV_STATUS knvlinkHandleFaultUpInterrupt_GH100(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0); -static inline NV_STATUS knvlinkHandleFaultUpInterrupt_46f6a7(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0) { +static inline NV_STATUS knvlinkHandleFaultUpInterrupt_46f6a7(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0) { return NV_ERR_NOT_SUPPORTED; } -static inline NV_STATUS knvlinkHandleFaultUpInterrupt_DISPATCH(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0) { +static inline NV_STATUS knvlinkHandleFaultUpInterrupt_DISPATCH(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0) { return pKernelNvlink->__knvlinkHandleFaultUpInterrupt__(pGpu, pKernelNvlink, arg0); } -NV_STATUS knvlinkValidateFabricBaseAddress_GA100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU64 arg0); +NV_STATUS knvlinkValidateFabricBaseAddress_GA100(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU64 arg0); -NV_STATUS knvlinkValidateFabricBaseAddress_GH100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU64 arg0); +NV_STATUS knvlinkValidateFabricBaseAddress_GH100(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU64 arg0); -static inline NV_STATUS knvlinkValidateFabricBaseAddress_46f6a7(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU64 arg0) { +static inline NV_STATUS knvlinkValidateFabricBaseAddress_46f6a7(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU64 arg0) { return NV_ERR_NOT_SUPPORTED; } -static inline NV_STATUS knvlinkValidateFabricBaseAddress_DISPATCH(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU64 arg0) { +static inline NV_STATUS knvlinkValidateFabricBaseAddress_DISPATCH(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU64 arg0) { return pKernelNvlink->__knvlinkValidateFabricBaseAddress__(pGpu, pKernelNvlink, arg0); } -static inline NvU32 knvlinkGetConnectedLinksMask_15a734(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NvU32 knvlinkGetConnectedLinksMask_15a734(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { return 0U; } -NvU32 knvlinkGetConnectedLinksMask_TU102(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); +NvU32 knvlinkGetConnectedLinksMask_TU102(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); -static inline NvU32 knvlinkGetConnectedLinksMask_DISPATCH(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NvU32 knvlinkGetConnectedLinksMask_DISPATCH(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { return pKernelNvlink->__knvlinkGetConnectedLinksMask__(pGpu, pKernelNvlink); } -static inline NV_STATUS knvlinkEnableLinksPostTopology_56cd7a(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0) { +static inline NV_STATUS knvlinkEnableLinksPostTopology_56cd7a(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0) { return NV_OK; } -NV_STATUS knvlinkEnableLinksPostTopology_GV100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0); +NV_STATUS knvlinkEnableLinksPostTopology_GV100(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0); -static inline NV_STATUS knvlinkEnableLinksPostTopology_DISPATCH(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0) { +static inline NV_STATUS knvlinkEnableLinksPostTopology_DISPATCH(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0) { return pKernelNvlink->__knvlinkEnableLinksPostTopology__(pGpu, pKernelNvlink, arg0); } -static inline NV_STATUS knvlinkOverrideConfig_56cd7a(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0) { +static inline NV_STATUS knvlinkOverrideConfig_56cd7a(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0) { return NV_OK; } -NV_STATUS knvlinkOverrideConfig_GV100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0); +NV_STATUS knvlinkOverrideConfig_GV100(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0); -NV_STATUS knvlinkOverrideConfig_GA100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0); +NV_STATUS knvlinkOverrideConfig_GA100(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0); -static inline NV_STATUS knvlinkOverrideConfig_DISPATCH(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0) { +static inline NV_STATUS knvlinkOverrideConfig_DISPATCH(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0) { return pKernelNvlink->__knvlinkOverrideConfig__(pGpu, pKernelNvlink, arg0); } -NV_STATUS knvlinkFilterBridgeLinks_TU102(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); +NV_STATUS knvlinkFilterBridgeLinks_TU102(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); -static inline NV_STATUS knvlinkFilterBridgeLinks_46f6a7(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NV_STATUS knvlinkFilterBridgeLinks_46f6a7(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { return NV_ERR_NOT_SUPPORTED; } -static inline NV_STATUS knvlinkFilterBridgeLinks_DISPATCH(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NV_STATUS knvlinkFilterBridgeLinks_DISPATCH(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { return pKernelNvlink->__knvlinkFilterBridgeLinks__(pGpu, pKernelNvlink); } -NvU32 knvlinkGetUniquePeerIdMask_GP100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); +NvU32 knvlinkGetUniquePeerIdMask_GP100(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); -static inline NvU32 knvlinkGetUniquePeerIdMask_15a734(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NvU32 knvlinkGetUniquePeerIdMask_15a734(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { return 0U; } -static inline NvU32 knvlinkGetUniquePeerIdMask_DISPATCH(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NvU32 knvlinkGetUniquePeerIdMask_DISPATCH(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { return pKernelNvlink->__knvlinkGetUniquePeerIdMask__(pGpu, pKernelNvlink); } -static inline NvU32 knvlinkGetUniquePeerId_c732fb(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, OBJGPU *pRemoteGpu) { +static inline NvU32 knvlinkGetUniquePeerId_c732fb(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, struct OBJGPU *pRemoteGpu) { return 4294967295U; } -NvU32 knvlinkGetUniquePeerId_GP100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, OBJGPU *pRemoteGpu); +NvU32 knvlinkGetUniquePeerId_GP100(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, struct OBJGPU *pRemoteGpu); -static inline NvU32 knvlinkGetUniquePeerId_DISPATCH(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, OBJGPU *pRemoteGpu) { +static inline NvU32 knvlinkGetUniquePeerId_DISPATCH(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, struct OBJGPU *pRemoteGpu) { return pKernelNvlink->__knvlinkGetUniquePeerId__(pGpu, pKernelNvlink, pRemoteGpu); } -static inline NV_STATUS knvlinkRemoveMapping_56cd7a(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvBool bAllMapping, NvU32 peerMask, NvBool bL2Entry) { +static inline NV_STATUS knvlinkRemoveMapping_56cd7a(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvBool bAllMapping, NvU32 peerMask, NvBool bL2Entry) { return NV_OK; } -NV_STATUS knvlinkRemoveMapping_GP100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvBool bAllMapping, NvU32 peerMask, NvBool bL2Entry); +NV_STATUS knvlinkRemoveMapping_GP100(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvBool bAllMapping, NvU32 peerMask, NvBool bL2Entry); -NV_STATUS knvlinkRemoveMapping_GA100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvBool bAllMapping, NvU32 peerMask, NvBool bL2Entry); +NV_STATUS knvlinkRemoveMapping_GA100(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvBool bAllMapping, NvU32 peerMask, NvBool bL2Entry); -static inline NV_STATUS knvlinkRemoveMapping_DISPATCH(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvBool bAllMapping, NvU32 peerMask, NvBool bL2Entry) { +static inline NV_STATUS knvlinkRemoveMapping_DISPATCH(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvBool bAllMapping, NvU32 peerMask, NvBool bL2Entry) { return pKernelNvlink->__knvlinkRemoveMapping__(pGpu, pKernelNvlink, bAllMapping, peerMask, bL2Entry); } -static inline NV_STATUS knvlinkGetP2POptimalCEs_56cd7a(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0, NvU32 *arg1, NvU32 *arg2, NvU32 *arg3, NvU32 *arg4) { +static inline NV_STATUS knvlinkGetP2POptimalCEs_56cd7a(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0, NvU32 *arg1, NvU32 *arg2, NvU32 *arg3, NvU32 *arg4) { return NV_OK; } -NV_STATUS knvlinkGetP2POptimalCEs_GP100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0, NvU32 *arg1, NvU32 *arg2, NvU32 *arg3, NvU32 *arg4); +NV_STATUS knvlinkGetP2POptimalCEs_GP100(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0, NvU32 *arg1, NvU32 *arg2, NvU32 *arg3, NvU32 *arg4); -static inline NV_STATUS knvlinkGetP2POptimalCEs_DISPATCH(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0, NvU32 *arg1, NvU32 *arg2, NvU32 *arg3, NvU32 *arg4) { +static inline NV_STATUS knvlinkGetP2POptimalCEs_DISPATCH(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0, NvU32 *arg1, NvU32 *arg2, NvU32 *arg3, NvU32 *arg4) { return pKernelNvlink->__knvlinkGetP2POptimalCEs__(pGpu, pKernelNvlink, arg0, arg1, arg2, arg3, arg4); } -static inline NV_STATUS knvlinkConstructHal_56cd7a(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NV_STATUS knvlinkConstructHal_56cd7a(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { return NV_OK; } -NV_STATUS knvlinkConstructHal_GV100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); +NV_STATUS knvlinkConstructHal_GV100(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); -static inline NV_STATUS knvlinkConstructHal_DISPATCH(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NV_STATUS knvlinkConstructHal_DISPATCH(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { return pKernelNvlink->__knvlinkConstructHal__(pGpu, pKernelNvlink); } -static inline void knvlinkSetupPeerMapping_b3696a(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, OBJGPU *pRemoteGpu, NvU32 peerId) { +static inline void knvlinkSetupPeerMapping_b3696a(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, struct OBJGPU *pRemoteGpu, NvU32 peerId) { return; } -void knvlinkSetupPeerMapping_GP100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, OBJGPU *pRemoteGpu, NvU32 peerId); +void knvlinkSetupPeerMapping_GP100(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, struct OBJGPU *pRemoteGpu, NvU32 peerId); -static inline void knvlinkSetupPeerMapping_DISPATCH(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, OBJGPU *pRemoteGpu, NvU32 peerId) { +static inline void knvlinkSetupPeerMapping_DISPATCH(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, struct OBJGPU *pRemoteGpu, NvU32 peerId) { pKernelNvlink->__knvlinkSetupPeerMapping__(pGpu, pKernelNvlink, pRemoteGpu, peerId); } -static inline NV_STATUS knvlinkProgramLinkSpeed_56cd7a(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NV_STATUS knvlinkProgramLinkSpeed_56cd7a(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { return NV_OK; } -NV_STATUS knvlinkProgramLinkSpeed_GV100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); +NV_STATUS knvlinkProgramLinkSpeed_GV100(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); -static inline NV_STATUS knvlinkProgramLinkSpeed_DISPATCH(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NV_STATUS knvlinkProgramLinkSpeed_DISPATCH(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { return pKernelNvlink->__knvlinkProgramLinkSpeed__(pGpu, pKernelNvlink); } -static inline NvBool knvlinkPoweredUpForD3_491d52(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NvBool knvlinkPoweredUpForD3_491d52(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { return ((NvBool)(0 != 0)); } -NvBool knvlinkPoweredUpForD3_TU102(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); +NvBool knvlinkPoweredUpForD3_TU102(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); -static inline NvBool knvlinkPoweredUpForD3_DISPATCH(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NvBool knvlinkPoweredUpForD3_DISPATCH(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { return pKernelNvlink->__knvlinkPoweredUpForD3__(pGpu, pKernelNvlink); } -static inline NV_STATUS knvlinkIsAliSupported_56cd7a(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NV_STATUS knvlinkIsAliSupported_56cd7a(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { return NV_OK; } -NV_STATUS knvlinkIsAliSupported_GH100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); +NV_STATUS knvlinkIsAliSupported_GH100(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); -static inline NV_STATUS knvlinkIsAliSupported_DISPATCH(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NV_STATUS knvlinkIsAliSupported_DISPATCH(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { return pKernelNvlink->__knvlinkIsAliSupported__(pGpu, pKernelNvlink); } -static inline NV_STATUS knvlinkPostSetupNvlinkPeer_56cd7a(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NV_STATUS knvlinkPostSetupNvlinkPeer_56cd7a(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { return NV_OK; } -NV_STATUS knvlinkPostSetupNvlinkPeer_GH100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); +NV_STATUS knvlinkPostSetupNvlinkPeer_GH100(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); -static inline NV_STATUS knvlinkPostSetupNvlinkPeer_DISPATCH(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NV_STATUS knvlinkPostSetupNvlinkPeer_DISPATCH(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { return pKernelNvlink->__knvlinkPostSetupNvlinkPeer__(pGpu, pKernelNvlink); } -NV_STATUS knvlinkDiscoverPostRxDetLinks_GH100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, OBJGPU *pPeerGpu); +NV_STATUS knvlinkDiscoverPostRxDetLinks_GH100(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, struct OBJGPU *pPeerGpu); -static inline NV_STATUS knvlinkDiscoverPostRxDetLinks_46f6a7(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, OBJGPU *pPeerGpu) { +static inline NV_STATUS knvlinkDiscoverPostRxDetLinks_46f6a7(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, struct OBJGPU *pPeerGpu) { return NV_ERR_NOT_SUPPORTED; } -static inline NV_STATUS knvlinkDiscoverPostRxDetLinks_DISPATCH(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, OBJGPU *pPeerGpu) { +static inline NV_STATUS knvlinkDiscoverPostRxDetLinks_DISPATCH(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, struct OBJGPU *pPeerGpu) { return pKernelNvlink->__knvlinkDiscoverPostRxDetLinks__(pGpu, pKernelNvlink, pPeerGpu); } -NV_STATUS knvlinkLogAliDebugMessages_GH100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); +NV_STATUS knvlinkLogAliDebugMessages_GH100(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); -static inline NV_STATUS knvlinkLogAliDebugMessages_46f6a7(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NV_STATUS knvlinkLogAliDebugMessages_46f6a7(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { return NV_ERR_NOT_SUPPORTED; } -static inline NV_STATUS knvlinkLogAliDebugMessages_DISPATCH(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NV_STATUS knvlinkLogAliDebugMessages_DISPATCH(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { return pKernelNvlink->__knvlinkLogAliDebugMessages__(pGpu, pKernelNvlink); } -static inline void knvlinkGetEffectivePeerLinkMask_b3696a(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, OBJGPU *pRemoteGpu, NvU32 *pPeerLinkMask) { +static inline void knvlinkGetEffectivePeerLinkMask_b3696a(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, struct OBJGPU *pRemoteGpu, NvU32 *pPeerLinkMask) { return; } -void knvlinkGetEffectivePeerLinkMask_GH100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, OBJGPU *pRemoteGpu, NvU32 *pPeerLinkMask); +void knvlinkGetEffectivePeerLinkMask_GH100(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, struct OBJGPU *pRemoteGpu, NvU32 *pPeerLinkMask); -static inline void knvlinkGetEffectivePeerLinkMask_DISPATCH(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, OBJGPU *pRemoteGpu, NvU32 *pPeerLinkMask) { +static inline void knvlinkGetEffectivePeerLinkMask_DISPATCH(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, struct OBJGPU *pRemoteGpu, NvU32 *pPeerLinkMask) { pKernelNvlink->__knvlinkGetEffectivePeerLinkMask__(pGpu, pKernelNvlink, pRemoteGpu, pPeerLinkMask); } -static inline NvU32 knvlinkGetNumLinksToBeReducedPerIoctrl_4a4dee(struct KernelNvlink *pKernelNvlink) { +static inline NvU32 knvlinkGetNumLinksToBeReducedPerIoctrl_4a4dee(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { return 0; } -NvU32 knvlinkGetNumLinksToBeReducedPerIoctrl_GH100(struct KernelNvlink *pKernelNvlink); +NvU32 knvlinkGetNumLinksToBeReducedPerIoctrl_GH100(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); -static inline NvU32 knvlinkGetNumLinksToBeReducedPerIoctrl_DISPATCH(struct KernelNvlink *pKernelNvlink) { - return pKernelNvlink->__knvlinkGetNumLinksToBeReducedPerIoctrl__(pKernelNvlink); +static inline NvU32 knvlinkGetNumLinksToBeReducedPerIoctrl_DISPATCH(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { + return pKernelNvlink->__knvlinkGetNumLinksToBeReducedPerIoctrl__(pGpu, pKernelNvlink); } static inline NvBool knvlinkIsBandwidthModeOff_491d52(struct KernelNvlink *pKernelNvlink) { @@ -1593,33 +1726,33 @@ static inline NvBool knvlinkIsBandwidthModeOff_DISPATCH(struct KernelNvlink *pKe return pKernelNvlink->__knvlinkIsBandwidthModeOff__(pKernelNvlink); } -static inline void knvlinkDirectConnectCheck_b3696a(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline void knvlinkDirectConnectCheck_b3696a(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { return; } -void knvlinkDirectConnectCheck_GH100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); +void knvlinkDirectConnectCheck_GH100(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); -static inline void knvlinkDirectConnectCheck_DISPATCH(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline void knvlinkDirectConnectCheck_DISPATCH(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { pKernelNvlink->__knvlinkDirectConnectCheck__(pGpu, pKernelNvlink); } -static inline NvBool knvlinkIsGpuReducedNvlinkConfig_491d52(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NvBool knvlinkIsGpuReducedNvlinkConfig_491d52(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { return ((NvBool)(0 != 0)); } -NvBool knvlinkIsGpuReducedNvlinkConfig_GA100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); +NvBool knvlinkIsGpuReducedNvlinkConfig_GA100(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); -static inline NvBool knvlinkIsGpuReducedNvlinkConfig_DISPATCH(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { +static inline NvBool knvlinkIsGpuReducedNvlinkConfig_DISPATCH(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { return pKernelNvlink->__knvlinkIsGpuReducedNvlinkConfig__(pGpu, pKernelNvlink); } -static inline NvBool knvlinkIsFloorSweepingNeeded_491d52(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 numActiveLinksPerIoctrl, NvU32 numLinksPerIoctrl) { +static inline NvBool knvlinkIsFloorSweepingNeeded_491d52(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 numActiveLinksPerIoctrl, NvU32 numLinksPerIoctrl) { return ((NvBool)(0 != 0)); } -NvBool knvlinkIsFloorSweepingNeeded_GH100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 numActiveLinksPerIoctrl, NvU32 numLinksPerIoctrl); +NvBool knvlinkIsFloorSweepingNeeded_GH100(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 numActiveLinksPerIoctrl, NvU32 numLinksPerIoctrl); -static inline NvBool knvlinkIsFloorSweepingNeeded_DISPATCH(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 numActiveLinksPerIoctrl, NvU32 numLinksPerIoctrl) { +static inline NvBool knvlinkIsFloorSweepingNeeded_DISPATCH(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 numActiveLinksPerIoctrl, NvU32 numLinksPerIoctrl) { return pKernelNvlink->__knvlinkIsFloorSweepingNeeded__(pGpu, pKernelNvlink, numActiveLinksPerIoctrl, numLinksPerIoctrl); } @@ -1651,13 +1784,38 @@ static inline NV_STATUS knvlinkStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struc return pEngstate->__knvlinkStatePreInitUnlocked__(pGpu, pEngstate); } +static inline NvU32 knvlinkGetInitializedLinkMask(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { + struct KernelNvlink_PRIVATE *pKernelNvlink_PRIVATE = (struct KernelNvlink_PRIVATE *)pKernelNvlink; + return pKernelNvlink_PRIVATE->initializedLinks; +} + +static inline NvBool knvlinkAreLinksRegistryOverriden(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { + struct KernelNvlink_PRIVATE *pKernelNvlink_PRIVATE = (struct KernelNvlink_PRIVATE *)pKernelNvlink; + return pKernelNvlink_PRIVATE->bRegistryLinkOverride; +} + +static inline NvU32 knvlinkGetPeerLinkMask(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 peerId) { + struct KernelNvlink_PRIVATE *pKernelNvlink_PRIVATE = (struct KernelNvlink_PRIVATE *)pKernelNvlink; + return (peerId < ((sizeof (pKernelNvlink_PRIVATE->peerLinkMasks) / sizeof ((pKernelNvlink_PRIVATE->peerLinkMasks)[0])))) ? pKernelNvlink_PRIVATE->peerLinkMasks[peerId] : 0; +} + +static inline KNVLINK_RM_LINK *knvlinkGetLinkData(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 linkId) { + struct KernelNvlink_PRIVATE *pKernelNvlink_PRIVATE = (struct KernelNvlink_PRIVATE *)pKernelNvlink; + return (linkId < ((sizeof (pKernelNvlink_PRIVATE->nvlinkLinks) / sizeof ((pKernelNvlink_PRIVATE->nvlinkLinks)[0])))) ? &pKernelNvlink_PRIVATE->nvlinkLinks[linkId] : ((void *)0); +} + +static inline NvU32 knvlinkGetIPVersion(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { + struct KernelNvlink_PRIVATE *pKernelNvlink_PRIVATE = (struct KernelNvlink_PRIVATE *)pKernelNvlink; + return pKernelNvlink_PRIVATE->ipVerNvlink; +} + void knvlinkDestruct_IMPL(struct KernelNvlink *arg0); #define __nvoc_knvlinkDestruct(arg0) knvlinkDestruct_IMPL(arg0) -NV_STATUS knvlinkRemoveMissingIoctrlObjects_IMPL(OBJGPU *arg0, struct KernelNvlink *arg1); +NV_STATUS knvlinkRemoveMissingIoctrlObjects_IMPL(struct OBJGPU *arg0, struct KernelNvlink *arg1); #ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkRemoveMissingIoctrlObjects(OBJGPU *arg0, struct KernelNvlink *arg1) { +static inline NV_STATUS knvlinkRemoveMissingIoctrlObjects(struct OBJGPU *arg0, struct KernelNvlink *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -1685,8 +1843,8 @@ static inline NV_STATUS knvlinkRemoveMissingIoctrlObjects(OBJGPU *arg0, struct K // // NVLINK internal functions // -NV_STATUS knvlinkRetrainLinkFromOff (OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 linkId); -NV_STATUS knvlinkRetrainLinkFromSafe(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 linkId); +NV_STATUS knvlinkRetrainLinkFromOff (struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 linkId); +NV_STATUS knvlinkRetrainLinkFromSafe(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 linkId); // // NVLINK Callback functions from core library @@ -1694,12 +1852,12 @@ NV_STATUS knvlinkRetrainLinkFromSafe(OBJGPU *pGpu, struct KernelNvlink *pKernelN #if defined(INCLUDE_NVLINK_LIB) // Device callback functions - + NvlStatus knvlinkCoreAddDeviceCallback (nvlink_device *dev); NvlStatus knvlinkCoreRemoveDeviceCallback(nvlink_device *dev); - + // Link callback functions - + NvlStatus knvlinkCoreAddLinkCallback (nvlink_link *link); NvlStatus knvlinkCoreRemoveLinkCallback (nvlink_link *link); NvlStatus knvlinkCoreLockLinkCallback (nvlink_link *link); @@ -1720,17 +1878,18 @@ NvlStatus knvlinkCoreGetRxSublinkDetectCallback (nvlink_link *link); void knvlinkCoreTrainingCompleteCallback (nvlink_link *link); void knvlinkCoreGetUphyLoadCallback (nvlink_link *link, NvBool *bUnlocked); NvlStatus knvlinkCoreAliTrainingCallback (nvlink_link *link); - + #endif // NVLINK Utility Functions void knvlinkUtoa(NvU8 *, NvU64, NvU64); -NV_STATUS ioctrlFaultUpTmrHandler(OBJGPU *, struct OBJTMR *,TMR_EVENT *); +NV_STATUS ioctrlFaultUpTmrHandler(struct OBJGPU *, struct OBJTMR *,TMR_EVENT *); #endif // _KERNEL_NVLINK_H_ #ifdef __cplusplus } // extern "C" #endif + #endif // _G_KERNEL_NVLINK_NVOC_H_ diff --git a/src/nvidia/generated/g_kernel_ofa_ctx_nvoc.c b/src/nvidia/generated/g_kernel_ofa_ctx_nvoc.c index 1e84364b33..43658fe221 100644 --- a/src/nvidia/generated/g_kernel_ofa_ctx_nvoc.c +++ b/src/nvidia/generated/g_kernel_ofa_ctx_nvoc.c @@ -270,10 +270,10 @@ void __nvoc_init_dataField_OfaContext(OfaContext *pThis, RmHalspecOwner *pRmhals PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); } -NV_STATUS __nvoc_ctor_ChannelDescendant(ChannelDescendant* , RmHalspecOwner* , struct CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *, PARAM_TO_ENGDESC_FUNCTION *); +NV_STATUS __nvoc_ctor_ChannelDescendant(ChannelDescendant* , RmHalspecOwner* , struct CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *, ENGDESCRIPTOR (*)(struct OBJGPU *, NvU32, void *)); NV_STATUS __nvoc_ctor_OfaContext(OfaContext *pThis, RmHalspecOwner *pRmhalspecowner, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { NV_STATUS status = NV_OK; - status = __nvoc_ctor_ChannelDescendant(&pThis->__nvoc_base_ChannelDescendant, pRmhalspecowner, arg_pCallContext, arg_pParams, ((void *)0)); + status = __nvoc_ctor_ChannelDescendant(&pThis->__nvoc_base_ChannelDescendant, pRmhalspecowner, arg_pCallContext, arg_pParams, ofaGetEngineDescFromAllocParams); if (status != NV_OK) goto __nvoc_ctor_OfaContext_fail_ChannelDescendant; __nvoc_init_dataField_OfaContext(pThis, pRmhalspecowner); diff --git a/src/nvidia/generated/g_kernel_ofa_ctx_nvoc.h b/src/nvidia/generated/g_kernel_ofa_ctx_nvoc.h index 105c9eb7db..0a8bec05dc 100644 --- a/src/nvidia/generated/g_kernel_ofa_ctx_nvoc.h +++ b/src/nvidia/generated/g_kernel_ofa_ctx_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -36,6 +36,8 @@ extern "C" { #include "kernel/gpu/fifo/channel_descendant.h" +ENGDESCRIPTOR ofaGetEngineDescFromAllocParams(OBJGPU *pGpu, NvU32 externalClassId, void *pAllocParams); + /*! * RM internal class representing NVXXXX_VIDEO_OFA */ @@ -321,4 +323,5 @@ static inline void __nvoc_ofactxDestruct(struct OfaContext *pOfaContext) { #ifdef __cplusplus } // extern "C" #endif + #endif // _G_KERNEL_OFA_CTX_NVOC_H_ diff --git a/src/nvidia/generated/g_kernel_rc_nvoc.h b/src/nvidia/generated/g_kernel_rc_nvoc.h index c7bdf1b68e..8b639f6890 100644 --- a/src/nvidia/generated/g_kernel_rc_nvoc.h +++ b/src/nvidia/generated/g_kernel_rc_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -42,9 +42,23 @@ extern "C" { #include "kernel/gpu/rc/kernel_rc_watchdog.h" #include "kernel/gpu/rc/kernel_rc_watchdog_private.h" #include "kernel/gpu/gpu_engine_type.h" -#include "kernel/gpu/subdevice/subdevice.h" #include "kernel/rmapi/client_resource.h" +#include "ctrl/ctrl2080/ctrl2080rc.h" + +struct Subdevice; + +#ifndef __NVOC_CLASS_Subdevice_TYPEDEF__ +#define __NVOC_CLASS_Subdevice_TYPEDEF__ +typedef struct Subdevice Subdevice; +#endif /* __NVOC_CLASS_Subdevice_TYPEDEF__ */ + +#ifndef __nvoc_class_id_Subdevice +#define __nvoc_class_id_Subdevice 0x4b01b3 +#endif /* __nvoc_class_id_Subdevice */ + + + typedef enum { RC_NOTIFIER_SCOPE_CHANNEL = 0, RC_NOTIFIER_SCOPE_TSG, @@ -82,6 +96,7 @@ struct KernelRc { NvBool bBreakOnRc; NvBool bLogEvents; struct KernelChannel *pPreviousChannelInError; + NvBool bRcOnBar2Fault; NvBool bGpuUuidLoggedOnce; KernelWatchdog watchdog; KernelWatchdogPersistent watchdogPersistent; @@ -379,10 +394,10 @@ static inline void krcInitRegistryOverridesDelayed(struct OBJGPU *pGpu, struct K #define krcInitRegistryOverridesDelayed(pGpu, pKernelRc) krcInitRegistryOverridesDelayed_IMPL(pGpu, pKernelRc) #endif //__nvoc_kernel_rc_h_disabled -NV_STATUS krcErrorSetNotifier_IMPL(struct OBJGPU *pGpu, struct KernelRc *pKernelRc, struct KernelChannel *pKernelChannel, NvU32 exceptType, NvU32 nv2080EngineType, RC_NOTIFIER_SCOPE scope); +NV_STATUS krcErrorSetNotifier_IMPL(struct OBJGPU *pGpu, struct KernelRc *pKernelRc, struct KernelChannel *pKernelChannel, NvU32 exceptType, RM_ENGINE_TYPE nv2080EngineType, RC_NOTIFIER_SCOPE scope); #ifdef __nvoc_kernel_rc_h_disabled -static inline NV_STATUS krcErrorSetNotifier(struct OBJGPU *pGpu, struct KernelRc *pKernelRc, struct KernelChannel *pKernelChannel, NvU32 exceptType, NvU32 nv2080EngineType, RC_NOTIFIER_SCOPE scope) { +static inline NV_STATUS krcErrorSetNotifier(struct OBJGPU *pGpu, struct KernelRc *pKernelRc, struct KernelChannel *pKernelChannel, NvU32 exceptType, RM_ENGINE_TYPE nv2080EngineType, RC_NOTIFIER_SCOPE scope) { NV_ASSERT_FAILED_PRECOMP("KernelRc was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -557,4 +572,5 @@ void krcWatchdogTimerProc(struct OBJGPU *pGpu, void *); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_KERNEL_RC_NVOC_H_ diff --git a/src/nvidia/generated/g_kernel_sched_mgr_nvoc.h b/src/nvidia/generated/g_kernel_sched_mgr_nvoc.h index 3bb156abd5..5a540007b2 100644 --- a/src/nvidia/generated/g_kernel_sched_mgr_nvoc.h +++ b/src/nvidia/generated/g_kernel_sched_mgr_nvoc.h @@ -140,4 +140,5 @@ static inline void kschedmgrSetConfigPolicyFromUser(struct KernelSchedMgr *pKern #ifdef __cplusplus } // extern "C" #endif + #endif // _G_KERNEL_SCHED_MGR_NVOC_H_ diff --git a/src/nvidia/generated/g_kernel_sec2_nvoc.c b/src/nvidia/generated/g_kernel_sec2_nvoc.c index 16d626012b..de33cd529e 100644 --- a/src/nvidia/generated/g_kernel_sec2_nvoc.c +++ b/src/nvidia/generated/g_kernel_sec2_nvoc.c @@ -106,7 +106,7 @@ static NV_STATUS __nvoc_thunk_KernelSec2_engstateConstructEngine(struct OBJGPU * return ksec2ConstructEngine(pGpu, (struct KernelSec2 *)(((unsigned char *)pKernelSec2) - __nvoc_rtti_KernelSec2_OBJENGSTATE.offset), arg0); } -static void __nvoc_thunk_KernelSec2_intrservRegisterIntrService(struct OBJGPU *pGpu, struct IntrService *pKernelSec2, IntrServiceRecord pRecords[167]) { +static void __nvoc_thunk_KernelSec2_intrservRegisterIntrService(struct OBJGPU *pGpu, struct IntrService *pKernelSec2, IntrServiceRecord pRecords[168]) { ksec2RegisterIntrService(pGpu, (struct KernelSec2 *)(((unsigned char *)pKernelSec2) - __nvoc_rtti_KernelSec2_IntrService.offset), pRecords); } diff --git a/src/nvidia/generated/g_kernel_sec2_nvoc.h b/src/nvidia/generated/g_kernel_sec2_nvoc.h index a492e18e60..49917cc068 100644 --- a/src/nvidia/generated/g_kernel_sec2_nvoc.h +++ b/src/nvidia/generated/g_kernel_sec2_nvoc.h @@ -189,9 +189,9 @@ static inline NV_STATUS ksec2ConstructEngine_DISPATCH(struct OBJGPU *pGpu, struc return pKernelSec2->__ksec2ConstructEngine__(pGpu, pKernelSec2, arg0); } -void ksec2RegisterIntrService_IMPL(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, IntrServiceRecord pRecords[167]); +void ksec2RegisterIntrService_IMPL(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, IntrServiceRecord pRecords[168]); -static inline void ksec2RegisterIntrService_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, IntrServiceRecord pRecords[167]) { +static inline void ksec2RegisterIntrService_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, IntrServiceRecord pRecords[168]) { pKernelSec2->__ksec2RegisterIntrService__(pGpu, pKernelSec2, pRecords); } @@ -394,4 +394,5 @@ void ksec2Destruct_IMPL(struct KernelSec2 *pKernelSec2); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_KERNEL_SEC2_NVOC_H_ diff --git a/src/nvidia/generated/g_kernel_sm_debugger_session_nvoc.h b/src/nvidia/generated/g_kernel_sm_debugger_session_nvoc.h index 42547d0bce..945f5f29e4 100644 --- a/src/nvidia/generated/g_kernel_sm_debugger_session_nvoc.h +++ b/src/nvidia/generated/g_kernel_sm_debugger_session_nvoc.h @@ -674,4 +674,5 @@ static inline void ksmdbgssnFreeCallback(struct KernelSMDebuggerSession *arg0) { #ifdef __cplusplus } // extern "C" #endif + #endif // _G_KERNEL_SM_DEBUGGER_SESSION_NVOC_H_ diff --git a/src/nvidia/generated/g_kernel_vgpu_mgr_nvoc.h b/src/nvidia/generated/g_kernel_vgpu_mgr_nvoc.h index 70beba1f70..2e45ea3c13 100644 --- a/src/nvidia/generated/g_kernel_vgpu_mgr_nvoc.h +++ b/src/nvidia/generated/g_kernel_vgpu_mgr_nvoc.h @@ -103,12 +103,19 @@ typedef struct VGPU_DEVICE_GUEST_FB_INFO NvBool bValid; } VGPU_DEVICE_GUEST_FB_INFO; +typedef struct +{ + NvU64 hbmBaseAddr; + NvU64 size; +} HBM_REGION_INFO; + /* This structure represents guest vgpu device's (assigned to VM) information. For VGPU-GSP, only KERNEL_HOST_VGPU_DEVICE is avaliable on kernel. */ typedef struct KERNEL_HOST_VGPU_DEVICE { NvU32 vgpuType; - NvHandle hClient; /*Internal RM client to dup smcPartition*/ + NvHandle hMigClient; /*Internal RM client to dup smcPartition*/ + NvHandle hMigDevice; /*Internal RM device to dup smcPartition*/ struct KERNEL_VGPU_GUEST *vgpuGuest; NvU32 gfid; NvU32 swizzId; @@ -120,6 +127,8 @@ typedef struct KERNEL_HOST_VGPU_DEVICE struct REQUEST_VGPU_INFO_NODE *pRequestVgpuInfoNode; struct PhysMemSubAlloc *pPhysMemSubAlloc; struct HOST_VGPU_DEVICE *pHostVgpuDevice; + HBM_REGION_INFO *hbmRegionList; + NvU32 numValidHbmRegions; // Legacy fields NvHandle hPluginFBAllocationClient; VGPU_DEVICE_GUEST_FB_INFO vgpuDeviceGuestFbInfo; @@ -385,4 +394,5 @@ kvgpuMgrRestoreSmcExecPart(struct OBJGPU *pGpu,KERNEL_HOST_VGPU_DEVICE *pKernelH #ifdef __cplusplus } // extern "C" #endif + #endif // _G_KERNEL_VGPU_MGR_NVOC_H_ diff --git a/src/nvidia/generated/g_kernel_video_engine_nvoc.c b/src/nvidia/generated/g_kernel_video_engine_nvoc.c new file mode 100644 index 0000000000..c2fb9debc3 --- /dev/null +++ b/src/nvidia/generated/g_kernel_video_engine_nvoc.c @@ -0,0 +1,164 @@ +#define NVOC_KERNEL_VIDEO_ENGINE_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_kernel_video_engine_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0x9e2f3e = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelVideoEngine; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +void __nvoc_init_KernelVideoEngine(KernelVideoEngine*); +void __nvoc_init_funcTable_KernelVideoEngine(KernelVideoEngine*); +NV_STATUS __nvoc_ctor_KernelVideoEngine(KernelVideoEngine*, struct OBJGPU * arg_pGpu, ENGDESCRIPTOR arg_physEngDesc); +void __nvoc_init_dataField_KernelVideoEngine(KernelVideoEngine*); +void __nvoc_dtor_KernelVideoEngine(KernelVideoEngine*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelVideoEngine; + +static const struct NVOC_RTTI __nvoc_rtti_KernelVideoEngine_KernelVideoEngine = { + /*pClassDef=*/ &__nvoc_class_def_KernelVideoEngine, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_KernelVideoEngine, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_KernelVideoEngine_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(KernelVideoEngine, __nvoc_base_Object), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_KernelVideoEngine = { + /*numRelatives=*/ 2, + /*relatives=*/ { + &__nvoc_rtti_KernelVideoEngine_KernelVideoEngine, + &__nvoc_rtti_KernelVideoEngine_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_KernelVideoEngine = +{ + /*classInfo=*/ { + /*size=*/ sizeof(KernelVideoEngine), + /*classId=*/ classId(KernelVideoEngine), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "KernelVideoEngine", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_KernelVideoEngine, + /*pCastInfo=*/ &__nvoc_castinfo_KernelVideoEngine, + /*pExportInfo=*/ &__nvoc_export_info_KernelVideoEngine +}; + +const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelVideoEngine = +{ + /*numEntries=*/ 0, + /*pExportEntries=*/ 0 +}; + +void __nvoc_dtor_Object(Object*); +void __nvoc_dtor_KernelVideoEngine(KernelVideoEngine *pThis) { + __nvoc_dtor_Object(&pThis->__nvoc_base_Object); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_KernelVideoEngine(KernelVideoEngine *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +NV_STATUS __nvoc_ctor_Object(Object* ); +NV_STATUS __nvoc_ctor_KernelVideoEngine(KernelVideoEngine *pThis, struct OBJGPU * arg_pGpu, ENGDESCRIPTOR arg_physEngDesc) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_Object(&pThis->__nvoc_base_Object); + if (status != NV_OK) goto __nvoc_ctor_KernelVideoEngine_fail_Object; + __nvoc_init_dataField_KernelVideoEngine(pThis); + + status = __nvoc_kvidengConstruct(pThis, arg_pGpu, arg_physEngDesc); + if (status != NV_OK) goto __nvoc_ctor_KernelVideoEngine_fail__init; + goto __nvoc_ctor_KernelVideoEngine_exit; // Success + +__nvoc_ctor_KernelVideoEngine_fail__init: + __nvoc_dtor_Object(&pThis->__nvoc_base_Object); +__nvoc_ctor_KernelVideoEngine_fail_Object: +__nvoc_ctor_KernelVideoEngine_exit: + + return status; +} + +static void __nvoc_init_funcTable_KernelVideoEngine_1(KernelVideoEngine *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_funcTable_KernelVideoEngine(KernelVideoEngine *pThis) { + __nvoc_init_funcTable_KernelVideoEngine_1(pThis); +} + +void __nvoc_init_Object(Object*); +void __nvoc_init_KernelVideoEngine(KernelVideoEngine *pThis) { + pThis->__nvoc_pbase_KernelVideoEngine = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_Object; + __nvoc_init_Object(&pThis->__nvoc_base_Object); + __nvoc_init_funcTable_KernelVideoEngine(pThis); +} + +NV_STATUS __nvoc_objCreate_KernelVideoEngine(KernelVideoEngine **ppThis, Dynamic *pParent, NvU32 createFlags, struct OBJGPU * arg_pGpu, ENGDESCRIPTOR arg_physEngDesc) { + NV_STATUS status; + Object *pParentObj; + KernelVideoEngine *pThis; + + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelVideoEngine), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; + + portMemSet(pThis, 0, sizeof(KernelVideoEngine)); + + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelVideoEngine); + + pThis->__nvoc_base_Object.createFlags = createFlags; + + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_Object.pParent = NULL; + } + + __nvoc_init_KernelVideoEngine(pThis); + status = __nvoc_ctor_KernelVideoEngine(pThis, arg_pGpu, arg_physEngDesc); + if (status != NV_OK) goto __nvoc_objCreate_KernelVideoEngine_cleanup; + + *ppThis = pThis; + + return NV_OK; + +__nvoc_objCreate_KernelVideoEngine_cleanup: + // do not call destructors here since the constructor already called them + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelVideoEngine)); + else + portMemFree(pThis); + + // coverity[leaked_storage:FALSE] + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_KernelVideoEngine(KernelVideoEngine **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + struct OBJGPU * arg_pGpu = va_arg(args, struct OBJGPU *); + ENGDESCRIPTOR arg_physEngDesc = va_arg(args, ENGDESCRIPTOR); + + status = __nvoc_objCreate_KernelVideoEngine(ppThis, pParent, createFlags, arg_pGpu, arg_physEngDesc); + + return status; +} + diff --git a/src/nvidia/generated/g_kernel_video_engine_nvoc.h b/src/nvidia/generated/g_kernel_video_engine_nvoc.h new file mode 100644 index 0000000000..8187e496e7 --- /dev/null +++ b/src/nvidia/generated/g_kernel_video_engine_nvoc.h @@ -0,0 +1,151 @@ +#ifndef _G_KERNEL_VIDEO_ENGINE_NVOC_H_ +#define _G_KERNEL_VIDEO_ENGINE_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_kernel_video_engine_nvoc.h" + +#ifndef KERNEL_VIDEO_ENGINE_H +#define KERNEL_VIDEO_ENGINE_H + +#include "kernel/core/core.h" +#include "kernel/gpu/eng_desc.h" +#include "kernel/mem_mgr/mem.h" +#include "kernel/gpuvideo/video_event.h" + +#define IS_VIDEO_ENGINE(engDesc) (IS_NVDEC(engDesc) || IS_OFA(engDesc) || IS_NVJPEG(engDesc) || IS_MSENC(engDesc)) + +typedef struct +{ + /*! + * Trace buffer for Kernel events. + */ + MEMORY_DESCRIPTOR *pTraceBufferEngineMemDesc; + + /*! + * Mapped memdesc pointer for kernel events + */ + VIDEO_TRACE_RING_BUFFER *pTraceBufferEngine; + + /*! + * Local scratch system memory for variable data. + */ + NvU8 *pTraceBufferVariableData; + + /*! + * Timestamp for Engine start event used for generate noisy timestamp + */ + NvU64 noisyTimestampStart; + +#if PORT_IS_MODULE_SUPPORTED(crypto) + /*! + * Random number generator used for generate noisy timestamp + */ + PORT_CRYPTO_PRNG *pVideoLogPrng; +#endif +} VIDEO_TRACE_INFO; + +// Basic implementation of KernelVideoEngine that can be instantiated. +#ifdef NVOC_KERNEL_VIDEO_ENGINE_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif +struct KernelVideoEngine { + const struct NVOC_RTTI *__nvoc_rtti; + struct Object __nvoc_base_Object; + struct Object *__nvoc_pbase_Object; + struct KernelVideoEngine *__nvoc_pbase_KernelVideoEngine; + ENGDESCRIPTOR physEngDesc; + VIDEO_TRACE_INFO videoTraceInfo; + NvBool bVideoTraceEnabled; +}; + +#ifndef __NVOC_CLASS_KernelVideoEngine_TYPEDEF__ +#define __NVOC_CLASS_KernelVideoEngine_TYPEDEF__ +typedef struct KernelVideoEngine KernelVideoEngine; +#endif /* __NVOC_CLASS_KernelVideoEngine_TYPEDEF__ */ + +#ifndef __nvoc_class_id_KernelVideoEngine +#define __nvoc_class_id_KernelVideoEngine 0x9e2f3e +#endif /* __nvoc_class_id_KernelVideoEngine */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelVideoEngine; + +#define __staticCast_KernelVideoEngine(pThis) \ + ((pThis)->__nvoc_pbase_KernelVideoEngine) + +#ifdef __nvoc_kernel_video_engine_h_disabled +#define __dynamicCast_KernelVideoEngine(pThis) ((KernelVideoEngine*)NULL) +#else //__nvoc_kernel_video_engine_h_disabled +#define __dynamicCast_KernelVideoEngine(pThis) \ + ((KernelVideoEngine*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(KernelVideoEngine))) +#endif //__nvoc_kernel_video_engine_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_KernelVideoEngine(KernelVideoEngine**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_KernelVideoEngine(KernelVideoEngine**, Dynamic*, NvU32, struct OBJGPU * arg_pGpu, ENGDESCRIPTOR arg_physEngDesc); +#define __objCreate_KernelVideoEngine(ppNewObj, pParent, createFlags, arg_pGpu, arg_physEngDesc) \ + __nvoc_objCreate_KernelVideoEngine((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pGpu, arg_physEngDesc) + +NV_STATUS kvidengConstruct_IMPL(struct KernelVideoEngine *arg_pKernelVideoEngine, struct OBJGPU *arg_pGpu, ENGDESCRIPTOR arg_physEngDesc); + +#define __nvoc_kvidengConstruct(arg_pKernelVideoEngine, arg_pGpu, arg_physEngDesc) kvidengConstruct_IMPL(arg_pKernelVideoEngine, arg_pGpu, arg_physEngDesc) +NV_STATUS kvidengInitLogging_IMPL(struct OBJGPU *pGpu, struct KernelVideoEngine *pKernelVideoEngine); + +#ifdef __nvoc_kernel_video_engine_h_disabled +static inline NV_STATUS kvidengInitLogging(struct OBJGPU *pGpu, struct KernelVideoEngine *pKernelVideoEngine) { + NV_ASSERT_FAILED_PRECOMP("KernelVideoEngine was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_video_engine_h_disabled +#define kvidengInitLogging(pGpu, pKernelVideoEngine) kvidengInitLogging_IMPL(pGpu, pKernelVideoEngine) +#endif //__nvoc_kernel_video_engine_h_disabled + +void kvidengFreeLogging_IMPL(struct OBJGPU *pGpu, struct KernelVideoEngine *pKernelVideoEngine); + +#ifdef __nvoc_kernel_video_engine_h_disabled +static inline void kvidengFreeLogging(struct OBJGPU *pGpu, struct KernelVideoEngine *pKernelVideoEngine) { + NV_ASSERT_FAILED_PRECOMP("KernelVideoEngine was disabled!"); +} +#else //__nvoc_kernel_video_engine_h_disabled +#define kvidengFreeLogging(pGpu, pKernelVideoEngine) kvidengFreeLogging_IMPL(pGpu, pKernelVideoEngine) +#endif //__nvoc_kernel_video_engine_h_disabled + +#undef PRIVATE_FIELD + + +#endif // KERNEL_VIDEO_ENGINE_H + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif // _G_KERNEL_VIDEO_ENGINE_NVOC_H_ diff --git a/src/nvidia/generated/g_mem_desc_nvoc.h b/src/nvidia/generated/g_mem_desc_nvoc.h index a21ea9144c..1259d2adb4 100644 --- a/src/nvidia/generated/g_mem_desc_nvoc.h +++ b/src/nvidia/generated/g_mem_desc_nvoc.h @@ -175,6 +175,227 @@ typedef struct ADDRESS_TRANSLATION_ *ADDRESS_TRANSLATION; #define NV_RM_SURF_NAME_VAB "rm_vab_surface" #define NV_RM_SURF_NAME_GR_CIRCULAR_BUFFER "rm_gr_ctx_circular_buffer_surface" +// +// Tagging wrapper macro for memdescAlloc +// +#define memdescTagAlloc(stat, tag, pMemdesc) {(pMemdesc)->allocTag = tag; stat = memdescAlloc(pMemdesc);} +#define memdescTagAllocList(stat, tag, pMemdesc, pList) {(pMemdesc)->allocTag = tag; stat = memdescAllocList(pMemdesc, pList);} + +// +// RM internal allocations owner tags +// Total 200 tags are introduced, out of which some are already +// replaced with known verbose strings +// +typedef enum +{ + NV_FB_ALLOC_RM_INTERNAL_OWNER__MIN = 10U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_COMPBIT_STORE = 11U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_CONTEXT_BUFFER = 12U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_ATTR_BUFFER = 13U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_PMU_SURFACE = 14U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_CIRCULAR_BUFFER = 15U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_PAGE_POOL = 16U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_ACCESS_MAP = 17U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_WPR_METADATA = 18U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_LIBOS_ARGS = 19U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_BOOTLOADER_ARGS = 20U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_SR_METADATA = 21U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_ACR_SETUP = 22U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_ACR_SHADOW = 23U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_ACR_BACKUP = 24U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_ACR_BINARY = 25U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_VBIOS_FRTS = 26U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_USERD_BUFFER = 27U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_RUNLIST_ENTRIES = 28U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_PAGE_PTE = 29U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_MMU_FAULT_BUFFER = 30U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_FAULT_METHOD = 31U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_WAR_PT = 32U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_WAR_PD = 33U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_1 = 34U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_2 = 35U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_3 = 36U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_4 = 37U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_5 = 38U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_6 = 39U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_7 = 40U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_8 = 41U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_9 = 42U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_10 = 43U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_11 = 44U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_12 = 45U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_13 = 46U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_14 = 47U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_15 = 48U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_16 = 49U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_17 = 50U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_18 = 51U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_19 = 52U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_20 = 53U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_21 = 54U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_22 = 55U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_23 = 56U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_24 = 57U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_25 = 58U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_26 = 59U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_27 = 60U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_28 = 61U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_29 = 62U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_30 = 63U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_31 = 64U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_32 = 65U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_33 = 66U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_34 = 67U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_35 = 68U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_36 = 69U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_37 = 70U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_38 = 71U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_39 = 72U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_40 = 73U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_41 = 74U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_42 = 75U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_43 = 76U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_44 = 77U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_45 = 78U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_46 = 79U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_47 = 80U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_48 = 81U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_49 = 82U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_50 = 83U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_51 = 84U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_52 = 85U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_53 = 86U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_54 = 87U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_55 = 88U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_56 = 89U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_57 = 90U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_58 = 91U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_59 = 92U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_60 = 93U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_61 = 94U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_62 = 95U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_63 = 96U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_64 = 97U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_65 = 98U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_66 = 99U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_67 = 100U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_68 = 101U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_69 = 102U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_70 = 103U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_71 = 104U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_72 = 105U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_73 = 106U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_74 = 107U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_75 = 108U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_76 = 109U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_77 = 110U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_78 = 111U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_79 = 112U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_80 = 113U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_81 = 114U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_82 = 115U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_83 = 116U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_84 = 117U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_85 = 118U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_86 = 119U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_87 = 120U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_88 = 121U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_89 = 122U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_90 = 123U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_91 = 124U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_92 = 125U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_93 = 126U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_94 = 127U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_95 = 128U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_96 = 129U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_97 = 130U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_98 = 131U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_99 = 132U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_100 = 133U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_101 = 134U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_102 = 135U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_103 = 136U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_104 = 137U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_105 = 138U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_106 = 139U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_107 = 140U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_108 = 141U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_109 = 142U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_110 = 143U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_111 = 144U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_112 = 145U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_113 = 146U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_114 = 147U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_115 = 148U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_116 = 149U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_117 = 150U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_118 = 151U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_119 = 152U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_120 = 153U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_121 = 154U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_122 = 155U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_123 = 156U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_124 = 157U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_125 = 158U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_126 = 159U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_127 = 160U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_128 = 161U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_129 = 162U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_130 = 163U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_131 = 164U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_132 = 165U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_133 = 166U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_134 = 167U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_135 = 168U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_136 = 169U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_137 = 170U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_138 = 171U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_139 = 172U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_140 = 173U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_141 = 174U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_142 = 175U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_143 = 176U, + + // + // Unused tags from here, for any new use-case it's required + // to replace the below tags with known verbose strings + // + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_144 = 177U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_145 = 178U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_146 = 179U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_147 = 180U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_148 = 181U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_149 = 182U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_150 = 183U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_151 = 184U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_152 = 185U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_153 = 186U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_154 = 187U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_155 = 188U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_156 = 189U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_157 = 190U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_158 = 191U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_159 = 192U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_160 = 193U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_161 = 194U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_162 = 195U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_163 = 196U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_164 = 197U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_165 = 198U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_166 = 199U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_167 = 200U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_168 = 201U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_169 = 202U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_170 = 203U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_171 = 204U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_172 = 205U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_173 = 206U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_174 = 207U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_175 = 208U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_176 = 209U, + NV_FB_ALLOC_RM_INTERNAL_OWNER__MAX = 210U, +} NV_FB_ALLOC_RM_INTERNAL_OWNER; + // // Overrides address translation in SR-IOV enabled usecases // @@ -307,6 +528,11 @@ typedef struct MEMORY_DESCRIPTOR // NvU32 _hwResId; + // + // alloc tag for tracking internal allocations @ref NV_FB_ALLOC_RM_INTERNAL_OWNER + // + NV_FB_ALLOC_RM_INTERNAL_OWNER allocTag; + // // Keep track which heap is actually used for this allocation // @@ -390,6 +616,12 @@ typedef struct MEMORY_DESCRIPTOR // Indicates granularity of mapping. Will be used to implement dynamic page sizes. NvU32 pageArrayGranularity; + // NUMA node ID from which memory should be allocated + NvS32 numaNode; + + // Array to hold EGM addresses when EGM is enabled + RmPhysAddr *pPteEgmMappings; + // // If PhysicallyContiguous is NV_TRUE, this array consists of one element. // If PhysicallyContiguous is NV_FALSE, this array is actually larger and has @@ -654,9 +886,12 @@ PMEMORY_DESCRIPTOR memdescGetRootMemDesc(PMEMORY_DESCRIPTOR pMemDesc, NvU64 *pRo void memdescSetCustomHeap(PMEMORY_DESCRIPTOR); NvBool memdescGetCustomHeap(PMEMORY_DESCRIPTOR); NV_STATUS memdescSetPageArrayGranularity(MEMORY_DESCRIPTOR *pMemDesc, NvU64 pageArrayGranularity); - NvBool memdescAcquireRmExclusiveUse(MEMORY_DESCRIPTOR *pMemDesc); +NV_STATUS memdescFillMemdescForPhysAttr(MEMORY_DESCRIPTOR *pMemDesc, ADDRESS_TRANSLATION addressTranslation, + NvU64 *pOffset,NvU32 *pMemAperture, NvU32 *pMemKind, NvU32 *pZCullId, + NvU32 *pGpuCacheAttr, NvU32 *pGpuP2PCacheAttr, NvU64 *contigSegmentSize); +NvBool memdescIsEgm(MEMORY_DESCRIPTOR *pMemDesc); /*! * @brief Get PTE kind * @@ -845,6 +1080,31 @@ memdescGetSize(PMEMORY_DESCRIPTOR pMemDesc) return pMemDesc->Size; } +/*! + * @brief Set CPU NUMA node to allocate memory from + * + * @param[in] pMemDesc Memory Descriptor to use + * @param[in] numaNode NUMA node to allocate memory from + */ +static NV_INLINE void +memdescSetNumaNode(MEMORY_DESCRIPTOR *pMemDesc, NvS32 numaNode) +{ + pMemDesc->numaNode = numaNode; +} + +/*! + * @brief Get CPU NUMA node to allocate memory from + * + * @param[in] pMemDesc Memory Descriptor to use + * + * @returns NUMA node to allocate memory from + */ +static NV_INLINE NvS32 +memdescGetNumaNode(MEMORY_DESCRIPTOR *pMemDesc) +{ + return pMemDesc->numaNode; +} + /*! * @brief Checks if subdevice memory descriptors are present * @@ -1151,9 +1411,16 @@ void memdescSetName(OBJGPU*, MEMORY_DESCRIPTOR *pMemDesc, const char *name, cons // #define MEMDESC_FLAGS_FORCE_ALLOC_FROM_SUBHEAP NVBIT64(48) +// +// Indicate if memdesc needs to restore pte kind in the static bar1 mode +// when it is freed. +// +#define MEMDESC_FLAGS_RESTORE_PTE_KIND_ON_FREE NVBIT64(49) + #endif // _MEMDESC_H_ #ifdef __cplusplus } // extern "C" #endif + #endif // _G_MEM_DESC_NVOC_H_ diff --git a/src/nvidia/generated/g_mem_fabric_nvoc.c b/src/nvidia/generated/g_mem_fabric_nvoc.c index 602892b985..c00913898c 100644 --- a/src/nvidia/generated/g_mem_fabric_nvoc.c +++ b/src/nvidia/generated/g_mem_fabric_nvoc.c @@ -117,6 +117,10 @@ static NV_STATUS __nvoc_thunk_Memory_memoryfabricGetMapAddrSpace(struct MemoryFa return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryFabric_Memory.offset), pCallContext, mapFlags, pAddrSpace); } +static NvBool __nvoc_thunk_Memory_memoryfabricIsExportAllowed(struct MemoryFabric *pMemory) { + return memIsExportAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryFabric_Memory.offset)); +} + static NvU32 __nvoc_thunk_RsResource_memoryfabricGetRefCount(struct MemoryFabric *pResource) { return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabric_RsResource.offset)); } @@ -215,12 +219,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_MemoryFa #endif }, { /* [1] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2844u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) memoryfabricCtrlCmdDescribe_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2844u) - /*flags=*/ 0x2844u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2850u) + /*flags=*/ 0x2850u, /*accessRight=*/0x0u, /*methodId=*/ 0xf80102u, /*paramSize=*/ sizeof(NV00F8_CTRL_DESCRIBE_PARAMS), @@ -356,7 +360,7 @@ static void __nvoc_init_funcTable_MemoryFabric_1(MemoryFabric *pThis) { pThis->__memoryfabricCtrlGetInfo__ = &memoryfabricCtrlGetInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2844u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2850u) pThis->__memoryfabricCtrlCmdDescribe__ = &memoryfabricCtrlCmdDescribe_IMPL; #endif @@ -392,6 +396,8 @@ static void __nvoc_init_funcTable_MemoryFabric_1(MemoryFabric *pThis) { pThis->__memoryfabricGetMapAddrSpace__ = &__nvoc_thunk_Memory_memoryfabricGetMapAddrSpace; + pThis->__memoryfabricIsExportAllowed__ = &__nvoc_thunk_Memory_memoryfabricIsExportAllowed; + pThis->__memoryfabricGetRefCount__ = &__nvoc_thunk_RsResource_memoryfabricGetRefCount; pThis->__memoryfabricAddAdditionalDependants__ = &__nvoc_thunk_RsResource_memoryfabricAddAdditionalDependants; diff --git a/src/nvidia/generated/g_mem_fabric_nvoc.h b/src/nvidia/generated/g_mem_fabric_nvoc.h index 9e798ea5ec..52a5e4a895 100644 --- a/src/nvidia/generated/g_mem_fabric_nvoc.h +++ b/src/nvidia/generated/g_mem_fabric_nvoc.h @@ -80,6 +80,7 @@ struct MemoryFabric { NvBool (*__memoryfabricShareCallback__)(struct MemoryFabric *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__memoryfabricMapTo__)(struct MemoryFabric *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__memoryfabricGetMapAddrSpace__)(struct MemoryFabric *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvBool (*__memoryfabricIsExportAllowed__)(struct MemoryFabric *); NvU32 (*__memoryfabricGetRefCount__)(struct MemoryFabric *); void (*__memoryfabricAddAdditionalDependants__)(struct RsClient *, struct MemoryFabric *, RsResourceRef *); NV_STATUS (*__memoryfabricControl_Prologue__)(struct MemoryFabric *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -143,6 +144,7 @@ NV_STATUS __nvoc_objCreate_MemoryFabric(MemoryFabric**, Dynamic*, NvU32, CALL_CO #define memoryfabricShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) memoryfabricShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define memoryfabricMapTo(pResource, pParams) memoryfabricMapTo_DISPATCH(pResource, pParams) #define memoryfabricGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) memoryfabricGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define memoryfabricIsExportAllowed(pMemory) memoryfabricIsExportAllowed_DISPATCH(pMemory) #define memoryfabricGetRefCount(pResource) memoryfabricGetRefCount_DISPATCH(pResource) #define memoryfabricAddAdditionalDependants(pClient, pResource, pReference) memoryfabricAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define memoryfabricControl_Prologue(pResource, pCallContext, pParams) memoryfabricControl_Prologue_DISPATCH(pResource, pCallContext, pParams) @@ -238,6 +240,10 @@ static inline NV_STATUS memoryfabricGetMapAddrSpace_DISPATCH(struct MemoryFabric return pMemory->__memoryfabricGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); } +static inline NvBool memoryfabricIsExportAllowed_DISPATCH(struct MemoryFabric *pMemory) { + return pMemory->__memoryfabricIsExportAllowed__(pMemory); +} + static inline NvU32 memoryfabricGetRefCount_DISPATCH(struct MemoryFabric *pResource) { return pResource->__memoryfabricGetRefCount__(pResource); } @@ -349,4 +355,5 @@ typedef struct #ifdef __cplusplus } // extern "C" #endif + #endif // _G_MEM_FABRIC_NVOC_H_ diff --git a/src/nvidia/generated/g_mem_list_nvoc.c b/src/nvidia/generated/g_mem_list_nvoc.c index 33e8764983..5f0f55766d 100644 --- a/src/nvidia/generated/g_mem_list_nvoc.c +++ b/src/nvidia/generated/g_mem_list_nvoc.c @@ -113,6 +113,10 @@ static NV_STATUS __nvoc_thunk_Memory_memlistGetMapAddrSpace(struct MemoryList *p return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryList_Memory.offset), pCallContext, mapFlags, pAddrSpace); } +static NvBool __nvoc_thunk_Memory_memlistIsExportAllowed(struct MemoryList *pMemory) { + return memIsExportAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryList_Memory.offset)); +} + static NvU32 __nvoc_thunk_RsResource_memlistGetRefCount(struct MemoryList *pResource) { return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RsResource.offset)); } @@ -243,6 +247,8 @@ static void __nvoc_init_funcTable_MemoryList_1(MemoryList *pThis) { pThis->__memlistGetMapAddrSpace__ = &__nvoc_thunk_Memory_memlistGetMapAddrSpace; + pThis->__memlistIsExportAllowed__ = &__nvoc_thunk_Memory_memlistIsExportAllowed; + pThis->__memlistGetRefCount__ = &__nvoc_thunk_RsResource_memlistGetRefCount; pThis->__memlistAddAdditionalDependants__ = &__nvoc_thunk_RsResource_memlistAddAdditionalDependants; diff --git a/src/nvidia/generated/g_mem_list_nvoc.h b/src/nvidia/generated/g_mem_list_nvoc.h index e63e6fe8d6..551ed16cfc 100644 --- a/src/nvidia/generated/g_mem_list_nvoc.h +++ b/src/nvidia/generated/g_mem_list_nvoc.h @@ -59,6 +59,7 @@ struct MemoryList { NvBool (*__memlistShareCallback__)(struct MemoryList *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__memlistMapTo__)(struct MemoryList *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__memlistGetMapAddrSpace__)(struct MemoryList *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvBool (*__memlistIsExportAllowed__)(struct MemoryList *); NvU32 (*__memlistGetRefCount__)(struct MemoryList *); void (*__memlistAddAdditionalDependants__)(struct RsClient *, struct MemoryList *, RsResourceRef *); NV_STATUS (*__memlistControl_Prologue__)(struct MemoryList *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -114,6 +115,7 @@ NV_STATUS __nvoc_objCreate_MemoryList(MemoryList**, Dynamic*, NvU32, CALL_CONTEX #define memlistShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) memlistShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define memlistMapTo(pResource, pParams) memlistMapTo_DISPATCH(pResource, pParams) #define memlistGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) memlistGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define memlistIsExportAllowed(pMemory) memlistIsExportAllowed_DISPATCH(pMemory) #define memlistGetRefCount(pResource) memlistGetRefCount_DISPATCH(pResource) #define memlistAddAdditionalDependants(pClient, pResource, pReference) memlistAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define memlistControl_Prologue(pResource, pCallContext, pParams) memlistControl_Prologue_DISPATCH(pResource, pCallContext, pParams) @@ -156,6 +158,10 @@ static inline NV_STATUS memlistGetMapAddrSpace_DISPATCH(struct MemoryList *pMemo return pMemory->__memlistGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); } +static inline NvBool memlistIsExportAllowed_DISPATCH(struct MemoryList *pMemory) { + return pMemory->__memlistIsExportAllowed__(pMemory); +} + static inline NvU32 memlistGetRefCount_DISPATCH(struct MemoryList *pResource) { return pResource->__memlistGetRefCount__(pResource); } @@ -247,4 +253,5 @@ NV_STATUS memlistConstruct_IMPL(struct MemoryList *arg_pMemoryList, CALL_CONTEXT #ifdef __cplusplus } // extern "C" #endif + #endif // _G_MEM_LIST_NVOC_H_ diff --git a/src/nvidia/generated/g_mem_mapper_nvoc.h b/src/nvidia/generated/g_mem_mapper_nvoc.h index 69483eb85a..fb685ab021 100644 --- a/src/nvidia/generated/g_mem_mapper_nvoc.h +++ b/src/nvidia/generated/g_mem_mapper_nvoc.h @@ -285,4 +285,5 @@ NV_STATUS memmapperConstruct_IMPL(struct MemoryMapper *arg_pMemoryMapper, struct #ifdef __cplusplus } // extern "C" #endif + #endif // _G_MEM_MAPPER_NVOC_H_ diff --git a/src/nvidia/generated/g_mem_mgr_nvoc.c b/src/nvidia/generated/g_mem_mgr_nvoc.c index a2e5dadecb..d106e2cef3 100644 --- a/src/nvidia/generated/g_mem_mgr_nvoc.c +++ b/src/nvidia/generated/g_mem_mgr_nvoc.c @@ -215,6 +215,17 @@ void __nvoc_init_dataField_MemoryManager(MemoryManager *pThis, RmHalspecOwner *p pThis->bScrubChannelSetupInProgress = ((NvBool)(0 != 0)); + // Hal field -- bBug3922001DisableCtxBufOnSim + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->bBug3922001DisableCtxBufOnSim = ((NvBool)(0 == 0)); + } + // default + else + { + pThis->bBug3922001DisableCtxBufOnSim = ((NvBool)(0 != 0)); + } + pThis->bEnableDynamicGranularityPageArrays = ((NvBool)(0 != 0)); // Hal field -- bAllowNoncontiguousAllocation @@ -272,6 +283,12 @@ void __nvoc_init_dataField_MemoryManager(MemoryManager *pThis, RmHalspecOwner *p { pThis->bGenericKindSupport = ((NvBool)(0 == 0)); } + + // Hal field -- bLocalizedMemPoolEnabled + // default + { + pThis->bLocalizedMemPoolEnabled = ((NvBool)(0 != 0)); + } } NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* ); diff --git a/src/nvidia/generated/g_mem_mgr_nvoc.h b/src/nvidia/generated/g_mem_mgr_nvoc.h index f9e580f6b7..9a44e84f6e 100644 --- a/src/nvidia/generated/g_mem_mgr_nvoc.h +++ b/src/nvidia/generated/g_mem_mgr_nvoc.h @@ -79,7 +79,9 @@ typedef enum { TRANSFER_TYPE_PROCESSOR = 0, // CPU/GSP/DPU depending on execution context TRANSFER_TYPE_GSP_DMA, // Dma engine internal to GSP - TRANSFER_TYPE_CE, // Copy Engine HW + TRANSFER_TYPE_CE, // Copy Engine using CeUtils channel + TRANSFER_TYPE_CE_PRI, // Copy Engine using PRIs + TRANSFER_TYPE_BAR0, // Copy using BAR0 PRAMIN } TRANSFER_TYPE; #define TRANSFER_FLAGS_NONE 0 @@ -89,10 +91,12 @@ typedef enum #define TRANSFER_FLAGS_PERSISTENT_CPU_MAPPING NVBIT32(3) // Require long lived PROCESSOR mapping #define TRANSFER_FLAGS_DESTROY_MAPPING NVBIT32(4) // Destroy any cached mappings when complete #define TRANSFER_FLAGS_USE_BAR1 NVBIT32(5) // Use only BAR1 for PROCESSOR transfers +#define TRANSFER_FLAGS_PREFER_CE NVBIT32(6) // Use CE if possible (BAR0 on simulation for perf) +#define TRANSFER_FLAGS_CE_PRI_DEFER_FLUSH NVBIT32(7) // Defer CE flush; only affects PRI CE operations // Protection flags: at most 1 may be set, none means READ_WRITE by default -#define TRANSFER_FLAGS_MAP_PROTECT_READABLE NVBIT32(6) // Transfer is only reading data -#define TRANSFER_FLAGS_MAP_PROTECT_WRITEABLE NVBIT32(7) // Transfer is only writing data +#define TRANSFER_FLAGS_MAP_PROTECT_READABLE NVBIT32(8) // Transfer is only reading data +#define TRANSFER_FLAGS_MAP_PROTECT_WRITEABLE NVBIT32(9) // Transfer is only writing data typedef struct { @@ -146,6 +150,64 @@ typedef struct COMPR_INFO NvU32 compTagLineMultiplier; } COMPR_INFO; +// +// Individual entry for logging Fb reserved use-cases +// +typedef struct NV_FB_RSVD_BLOCK_LOG_ENTRY +{ + // Owner tag associated with reservation block + NvU32 ownerId; + + // Size of the memory reserved + NvU64 rsvdSize; +} NV_FB_RSVD_BLOCK_LOG_ENTRY; + +// Total number of FB internal reservation enries +#define NV_FB_RSVD_BLOCK_LOG_ENTRY_MAX 10U + +// +// Structure for logging Fb reserved use-cases +// +typedef struct NV_FB_RSVD_BLOCK_LOG_INFO +{ + // Counter for logging entries + NvU32 counter; + + // List of all reserved entries + NV_FB_RSVD_BLOCK_LOG_ENTRY rsvdBlockList[NV_FB_RSVD_BLOCK_LOG_ENTRY_MAX]; +} NV_FB_RSVD_BLOCK_LOG_INFO; + +// +// Macro for initializing reserved block log data +// +#define NV_FB_RSVD_BLOCK_LOG_INIT(pMem) \ + { \ + ((pMem)->rsvdBlockInfo).counter = 0; \ + for (NvU32 i = 0; i < NV_FB_RSVD_BLOCK_LOG_ENTRY_MAX; i++) \ + { \ + ((pMem)->rsvdBlockInfo).rsvdBlockList[i].ownerId = 0; \ + ((pMem)->rsvdBlockInfo).rsvdBlockList[i].rsvdSize = 0; \ + } \ + } + +// +// Macro for adding new reserved block entry to the list +// If unable to log, marks the status as NV_ERR_NO_MEMORY otherwise keeps it unchanged +// +#define NV_FB_RSVD_BLOCK_LOG_ENTRY_ADD(status, pMem, tag, size) \ + { \ + if(((pMem)->rsvdBlockInfo).counter < NV_FB_RSVD_BLOCK_LOG_ENTRY_MAX) \ + { \ + ((pMem)->rsvdBlockInfo).rsvdBlockList[((pMem)->rsvdBlockInfo).counter].ownerId = (tag); \ + ((pMem)->rsvdBlockInfo).rsvdBlockList[((pMem)->rsvdBlockInfo).counter].rsvdSize = (size); \ + (((pMem)->rsvdBlockInfo).counter)++; \ + } \ + else \ + { \ + status = NV_ERR_NO_MEMORY; \ + } \ + } + // // Fixed Channel Properties for Memutils Object // @@ -230,7 +292,6 @@ typedef struct OBJCHANNEL NvU32 *pBlockDoneState; NvU32 blockCount; NvHandle hClient; - NvHandle hLiteClient; // Used only for fifo lite channels NvBool bClientAllocated; NvU64 pbGpuVA; NvU64 pbGpuBitMapVA; @@ -269,15 +330,6 @@ typedef struct OBJCHANNEL NvHandle hUserD; NvBool bClientUserd; - - // - // Used only by suspend resume channel. - // This denotes whether the channel manages the BAR2 VASpace. - // Suspend resume happens way before the regular BAR2 init. - // Channel instmem has to be stored in vidmem due to 40 bit restriction in host on Pascal+ chips. - // So the suspend resume channel has to setup BAR2 for accessing vidmem. - // - NvBool bManageBAR2; OBJGPU *pGpu; NvU32 ceId; @@ -412,7 +464,6 @@ struct MIG_MEMORY_PARTITIONING_INFO { NvHandle hClient; NvHandle hDevice; NvHandle hSubdevice; - NvBool bNonMIGTopLevelScrubber; }; @@ -469,7 +520,6 @@ struct MemoryManager { NvBool bEnableFbsrPagedDma; NvBool bDisallowSplitLowerMemory; NvBool bIgnoreUpperMemory; - NvBool bLddmReservedMemoryCalculated; NvBool bSmallPageCompression; NvBool bSysmemCompressionSupportDef; NvBool bBug1698088IncreaseRmReserveMemoryWar; @@ -478,6 +528,7 @@ struct MemoryManager { NvBool bEnableDynamicPageOfflining; NvBool bVgpuPmaSupport; NvBool bScrubChannelSetupInProgress; + NvBool bBug3922001DisableCtxBufOnSim; NvBool bEnableDynamicGranularityPageArrays; NvBool bAllowNoncontiguousAllocation; NvBool bLocalEgmSupported; @@ -502,6 +553,8 @@ struct MemoryManager { NvU64 rsvdMemoryBase; NvU32 rsvdMemorySize; struct CeUtils *pCeUtils; + struct CeUtils *pCeUtilsSuspended; + NvBool bDisableGlobalCeUtils; OBJSCRUB eccScrubberState; struct __nvoc_inner_struc_MemoryManager_1__ Ram; NvU32 PteKindOverride; @@ -519,6 +572,7 @@ struct MemoryManager { PFB_MEM_NODE pMemTailNode; struct RM_POOL_ALLOC_MEM_RESERVE_INFO *pPageLevelReserve; struct MIG_MEMORY_PARTITIONING_INFO MIGMemoryPartitioningInfo; + NV_FB_RSVD_BLOCK_LOG_INFO rsvdBlockInfo; NvHandle hClient; NvHandle hDevice; NvHandle hSubdevice; @@ -526,6 +580,7 @@ struct MemoryManager { NvBool bMonitoredFenceSupported; NvBool b64BitSemaphoresSupported; NvBool bGenericKindSupport; + NvBool bLocalizedMemPoolEnabled; }; #ifndef __NVOC_CLASS_MemoryManager_TYPEDEF__ @@ -694,7 +749,9 @@ static inline NV_STATUS memmgrGetKindComprForGpu(struct MemoryManager *pMemoryMa #define memmgrGetKindComprForGpu_HAL(pMemoryManager, arg0, pGpu, offset, kind, pComprInfo) memmgrGetKindComprForGpu(pMemoryManager, arg0, pGpu, offset, kind, pComprInfo) -NV_STATUS memmgrScrubInit_GP100(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); +static inline NV_STATUS memmgrScrubInit_56cd7a(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { + return NV_OK; +} #ifdef __nvoc_mem_mgr_h_disabled @@ -703,7 +760,7 @@ static inline NV_STATUS memmgrScrubInit(OBJGPU *pGpu, struct MemoryManager *pMem return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_mem_mgr_h_disabled -#define memmgrScrubInit(pGpu, pMemoryManager) memmgrScrubInit_GP100(pGpu, pMemoryManager) +#define memmgrScrubInit(pGpu, pMemoryManager) memmgrScrubInit_56cd7a(pGpu, pMemoryManager) #endif //__nvoc_mem_mgr_h_disabled #define memmgrScrubInit_HAL(pGpu, pMemoryManager) memmgrScrubInit(pGpu, pMemoryManager) @@ -799,7 +856,9 @@ static inline NV_STATUS memmgrScrubHandlePreSchedulingDisable(OBJGPU *pGpu, stru #define memmgrScrubHandlePreSchedulingDisable_HAL(pGpu, pMemoryManager) memmgrScrubHandlePreSchedulingDisable(pGpu, pMemoryManager) -void memmgrScrubDestroy_GP100(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); +static inline void memmgrScrubDestroy_b3696a(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { + return; +} #ifdef __nvoc_mem_mgr_h_disabled @@ -807,7 +866,7 @@ static inline void memmgrScrubDestroy(OBJGPU *pGpu, struct MemoryManager *pMemor NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); } #else //__nvoc_mem_mgr_h_disabled -#define memmgrScrubDestroy(pGpu, pMemoryManager) memmgrScrubDestroy_GP100(pGpu, pMemoryManager) +#define memmgrScrubDestroy(pGpu, pMemoryManager) memmgrScrubDestroy_b3696a(pGpu, pMemoryManager) #endif //__nvoc_mem_mgr_h_disabled #define memmgrScrubDestroy_HAL(pGpu, pMemoryManager) memmgrScrubDestroy(pGpu, pMemoryManager) @@ -857,34 +916,6 @@ static inline NV_STATUS memmgrMemUtilsMemSet(OBJGPU *pGpu, struct MemoryManager #define memmgrMemUtilsMemSet_HAL(pGpu, pMemoryManager, arg0, arg1, arg2, arg3, arg4) memmgrMemUtilsMemSet(pGpu, pMemoryManager, arg0, arg1, arg2, arg3, arg4) -NV_STATUS memmgrMemUtilsMemSetBatched_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, OBJCHANNEL *arg0, RmPhysAddr arg1, NvU64 arg2); - - -#ifdef __nvoc_mem_mgr_h_disabled -static inline NV_STATUS memmgrMemUtilsMemSetBatched(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, OBJCHANNEL *arg0, RmPhysAddr arg1, NvU64 arg2) { - NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_mem_mgr_h_disabled -#define memmgrMemUtilsMemSetBatched(pGpu, pMemoryManager, arg0, arg1, arg2) memmgrMemUtilsMemSetBatched_GM107(pGpu, pMemoryManager, arg0, arg1, arg2) -#endif //__nvoc_mem_mgr_h_disabled - -#define memmgrMemUtilsMemSetBatched_HAL(pGpu, pMemoryManager, arg0, arg1, arg2) memmgrMemUtilsMemSetBatched(pGpu, pMemoryManager, arg0, arg1, arg2) - -NV_STATUS memmgrMemUtilsMemCopyBatched_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, OBJCHANNEL *arg0, RmPhysAddr arg1, NV_ADDRESS_SPACE arg2, NvU32 arg3, RmPhysAddr arg4, NV_ADDRESS_SPACE arg5, NvU32 arg6, NvU64 arg7); - - -#ifdef __nvoc_mem_mgr_h_disabled -static inline NV_STATUS memmgrMemUtilsMemCopyBatched(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, OBJCHANNEL *arg0, RmPhysAddr arg1, NV_ADDRESS_SPACE arg2, NvU32 arg3, RmPhysAddr arg4, NV_ADDRESS_SPACE arg5, NvU32 arg6, NvU64 arg7) { - NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_mem_mgr_h_disabled -#define memmgrMemUtilsMemCopyBatched(pGpu, pMemoryManager, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7) memmgrMemUtilsMemCopyBatched_GM107(pGpu, pMemoryManager, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7) -#endif //__nvoc_mem_mgr_h_disabled - -#define memmgrMemUtilsMemCopyBatched_HAL(pGpu, pMemoryManager, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7) memmgrMemUtilsMemCopyBatched(pGpu, pMemoryManager, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7) - NV_STATUS memmgrMemUtilsAllocateEccScrubber_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, OBJCHANNEL *arg0); @@ -1775,6 +1806,50 @@ static inline NV_STATUS memmgrDiscoverMIGPartitionableMemoryRange(OBJGPU *pGpu, #define memmgrDiscoverMIGPartitionableMemoryRange_HAL(pGpu, pMemoryManager, pMemoryRange) memmgrDiscoverMIGPartitionableMemoryRange(pGpu, pMemoryManager, pMemoryRange) +NvU32 memmgrGetFBEndReserveSizeEstimate_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + + +#ifdef __nvoc_mem_mgr_h_disabled +static inline NvU32 memmgrGetFBEndReserveSizeEstimate(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { + NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); + return 0; +} +#else //__nvoc_mem_mgr_h_disabled +#define memmgrGetFBEndReserveSizeEstimate(pGpu, pMemoryManager) memmgrGetFBEndReserveSizeEstimate_GM107(pGpu, pMemoryManager) +#endif //__nvoc_mem_mgr_h_disabled + +#define memmgrGetFBEndReserveSizeEstimate_HAL(pGpu, pMemoryManager) memmgrGetFBEndReserveSizeEstimate(pGpu, pMemoryManager) + +NV_STATUS memmgrValidateFBEndReservation_PF(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + + +#ifdef __nvoc_mem_mgr_h_disabled +static inline NV_STATUS memmgrValidateFBEndReservation(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { + NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_mem_mgr_h_disabled +#define memmgrValidateFBEndReservation(pGpu, pMemoryManager) memmgrValidateFBEndReservation_PF(pGpu, pMemoryManager) +#endif //__nvoc_mem_mgr_h_disabled + +#define memmgrValidateFBEndReservation_HAL(pGpu, pMemoryManager) memmgrValidateFBEndReservation(pGpu, pMemoryManager) + +static inline NV_STATUS memmgrReserveMemoryForPmu_56cd7a(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { + return NV_OK; +} + + +#ifdef __nvoc_mem_mgr_h_disabled +static inline NV_STATUS memmgrReserveMemoryForPmu(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { + NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_mem_mgr_h_disabled +#define memmgrReserveMemoryForPmu(pGpu, pMemoryManager) memmgrReserveMemoryForPmu_56cd7a(pGpu, pMemoryManager) +#endif //__nvoc_mem_mgr_h_disabled + +#define memmgrReserveMemoryForPmu_HAL(pGpu, pMemoryManager) memmgrReserveMemoryForPmu(pGpu, pMemoryManager) + void memmgrFreeFbsrMemory_KERNEL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); @@ -2094,6 +2169,10 @@ static inline NvBool memmgrIsLocalEgmEnabled(struct MemoryManager *pMemoryManage return pMemoryManager->bLocalEgmEnabled; } +static inline NvU32 memmgrLocalEgmPeerId(struct MemoryManager *pMemoryManager) { + return pMemoryManager->localEgmPeerId; +} + static inline NvBool memmgrIsScrubOnFreeEnabled(struct MemoryManager *pMemoryManager) { return pMemoryManager->bScrubOnFreeEnabled; } @@ -2162,6 +2241,10 @@ static inline NvU32 memmgrGetRsvdMemorySize(struct MemoryManager *pMemoryManager return pMemoryManager->rsvdMemorySize; } +static inline NvBool memmgrBug3922001DisableCtxBufOnSim(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { + return pMemoryManager->bBug3922001DisableCtxBufOnSim; +} + void memmgrDestruct_IMPL(struct MemoryManager *pMemoryManager); #define __nvoc_memmgrDestruct(pMemoryManager) memmgrDestruct_IMPL(pMemoryManager) @@ -2648,6 +2731,28 @@ static inline NV_STATUS memmgrPmaRegisterRegions(OBJGPU *pGpu, struct MemoryMana #define memmgrPmaRegisterRegions(pGpu, pMemoryManager, pHeap, pPma) memmgrPmaRegisterRegions_IMPL(pGpu, pMemoryManager, pHeap, pPma) #endif //__nvoc_mem_mgr_h_disabled +NV_STATUS memmgrInitInternalChannels_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + +#ifdef __nvoc_mem_mgr_h_disabled +static inline NV_STATUS memmgrInitInternalChannels(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { + NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_mem_mgr_h_disabled +#define memmgrInitInternalChannels(pGpu, pMemoryManager) memmgrInitInternalChannels_IMPL(pGpu, pMemoryManager) +#endif //__nvoc_mem_mgr_h_disabled + +NV_STATUS memmgrDestroyInternalChannels_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + +#ifdef __nvoc_mem_mgr_h_disabled +static inline NV_STATUS memmgrDestroyInternalChannels(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { + NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_mem_mgr_h_disabled +#define memmgrDestroyInternalChannels(pGpu, pMemoryManager) memmgrDestroyInternalChannels_IMPL(pGpu, pMemoryManager) +#endif //__nvoc_mem_mgr_h_disabled + NV_STATUS memmgrInitCeUtils_IMPL(struct MemoryManager *pMemoryManager, NvBool bFifoLite); #ifdef __nvoc_mem_mgr_h_disabled @@ -2659,14 +2764,14 @@ static inline NV_STATUS memmgrInitCeUtils(struct MemoryManager *pMemoryManager, #define memmgrInitCeUtils(pMemoryManager, bFifoLite) memmgrInitCeUtils_IMPL(pMemoryManager, bFifoLite) #endif //__nvoc_mem_mgr_h_disabled -void memmgrDestroyCeUtils_IMPL(struct MemoryManager *pMemoryManager); +void memmgrDestroyCeUtils_IMPL(struct MemoryManager *pMemoryManager, NvBool bSuspendCeUtils); #ifdef __nvoc_mem_mgr_h_disabled -static inline void memmgrDestroyCeUtils(struct MemoryManager *pMemoryManager) { +static inline void memmgrDestroyCeUtils(struct MemoryManager *pMemoryManager, NvBool bSuspendCeUtils) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); } #else //__nvoc_mem_mgr_h_disabled -#define memmgrDestroyCeUtils(pMemoryManager) memmgrDestroyCeUtils_IMPL(pMemoryManager) +#define memmgrDestroyCeUtils(pMemoryManager, bSuspendCeUtils) memmgrDestroyCeUtils_IMPL(pMemoryManager, bSuspendCeUtils) #endif //__nvoc_mem_mgr_h_disabled NV_STATUS memmgrSetMIGPartitionableBAR1Range_IMPL(OBJGPU *arg0, struct MemoryManager *arg1); @@ -2748,15 +2853,15 @@ static inline void memmgrPageLevelPoolsDestroy(OBJGPU *pGpu, struct MemoryManage #define memmgrPageLevelPoolsDestroy(pGpu, pMemoryManager) memmgrPageLevelPoolsDestroy_IMPL(pGpu, pMemoryManager) #endif //__nvoc_mem_mgr_h_disabled -NV_STATUS memmgrPageLevelPoolsGetInfo_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvHandle arg0, struct RM_POOL_ALLOC_MEM_RESERVE_INFO **arg1); +NV_STATUS memmgrPageLevelPoolsGetInfo_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, struct Device *pDevice, struct RM_POOL_ALLOC_MEM_RESERVE_INFO **arg0); #ifdef __nvoc_mem_mgr_h_disabled -static inline NV_STATUS memmgrPageLevelPoolsGetInfo(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvHandle arg0, struct RM_POOL_ALLOC_MEM_RESERVE_INFO **arg1) { +static inline NV_STATUS memmgrPageLevelPoolsGetInfo(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, struct Device *pDevice, struct RM_POOL_ALLOC_MEM_RESERVE_INFO **arg0) { NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_mem_mgr_h_disabled -#define memmgrPageLevelPoolsGetInfo(pGpu, pMemoryManager, arg0, arg1) memmgrPageLevelPoolsGetInfo_IMPL(pGpu, pMemoryManager, arg0, arg1) +#define memmgrPageLevelPoolsGetInfo(pGpu, pMemoryManager, pDevice, arg0) memmgrPageLevelPoolsGetInfo_IMPL(pGpu, pMemoryManager, pDevice, arg0) #endif //__nvoc_mem_mgr_h_disabled NV_STATUS memmgrAllocMIGMemoryAllocationInternalHandles_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); @@ -2810,28 +2915,6 @@ static inline void memmgrGetTopLevelScrubberStatus(OBJGPU *arg0, struct MemoryMa #define memmgrGetTopLevelScrubberStatus(arg0, arg1, pbTopLevelScrubberEnabled, pbTopLevelScrubberConstructed) memmgrGetTopLevelScrubberStatus_IMPL(arg0, arg1, pbTopLevelScrubberEnabled, pbTopLevelScrubberConstructed) #endif //__nvoc_mem_mgr_h_disabled -NV_STATUS memmgrSaveAndDestroyTopLevelScrubber_IMPL(OBJGPU *arg0, struct MemoryManager *arg1); - -#ifdef __nvoc_mem_mgr_h_disabled -static inline NV_STATUS memmgrSaveAndDestroyTopLevelScrubber(OBJGPU *arg0, struct MemoryManager *arg1) { - NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_mem_mgr_h_disabled -#define memmgrSaveAndDestroyTopLevelScrubber(arg0, arg1) memmgrSaveAndDestroyTopLevelScrubber_IMPL(arg0, arg1) -#endif //__nvoc_mem_mgr_h_disabled - -NV_STATUS memmgrInitSavedTopLevelScrubber_IMPL(OBJGPU *arg0, struct MemoryManager *arg1); - -#ifdef __nvoc_mem_mgr_h_disabled -static inline NV_STATUS memmgrInitSavedTopLevelScrubber(OBJGPU *arg0, struct MemoryManager *arg1) { - NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_mem_mgr_h_disabled -#define memmgrInitSavedTopLevelScrubber(arg0, arg1) memmgrInitSavedTopLevelScrubber_IMPL(arg0, arg1) -#endif //__nvoc_mem_mgr_h_disabled - MEMORY_DESCRIPTOR *memmgrMemUtilsGetMemDescFromHandle_IMPL(struct MemoryManager *pMemoryManager, NvHandle hClient, NvHandle hMemory); #ifdef __nvoc_mem_mgr_h_disabled @@ -2873,4 +2956,5 @@ static inline NV_STATUS memmgrReserveMemoryForFsp(OBJGPU *pGpu, struct MemoryMan #ifdef __cplusplus } // extern "C" #endif + #endif // _G_MEM_MGR_NVOC_H_ diff --git a/src/nvidia/generated/g_mem_multicast_fabric_nvoc.c b/src/nvidia/generated/g_mem_multicast_fabric_nvoc.c index 272f987293..fbe6a12320 100644 --- a/src/nvidia/generated/g_mem_multicast_fabric_nvoc.c +++ b/src/nvidia/generated/g_mem_multicast_fabric_nvoc.c @@ -109,6 +109,10 @@ static NvBool __nvoc_thunk_MemoryMulticastFabric_memIsGpuMapAllowed(struct Memor return memorymulticastfabricIsGpuMapAllowed((struct MemoryMulticastFabric *)(((unsigned char *)pMemoryMulticastFabric) - __nvoc_rtti_MemoryMulticastFabric_Memory.offset), pGpu); } +static NvBool __nvoc_thunk_MemoryMulticastFabric_memIsExportAllowed(struct Memory *pMemoryMulticastFabric) { + return memorymulticastfabricIsExportAllowed((struct MemoryMulticastFabric *)(((unsigned char *)pMemoryMulticastFabric) - __nvoc_rtti_MemoryMulticastFabric_Memory.offset)); +} + static NV_STATUS __nvoc_thunk_MemoryMulticastFabric_memGetMapAddrSpace(struct Memory *pMemoryMulticastFabric, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { return memorymulticastfabricGetMapAddrSpace((struct MemoryMulticastFabric *)(((unsigned char *)pMemoryMulticastFabric) - __nvoc_rtti_MemoryMulticastFabric_Memory.offset), pCallContext, mapFlags, pAddrSpace); } @@ -326,6 +330,8 @@ static void __nvoc_init_funcTable_MemoryMulticastFabric_1(MemoryMulticastFabric pThis->__memorymulticastfabricIsGpuMapAllowed__ = &memorymulticastfabricIsGpuMapAllowed_IMPL; + pThis->__memorymulticastfabricIsExportAllowed__ = &memorymulticastfabricIsExportAllowed_IMPL; + pThis->__memorymulticastfabricGetMapAddrSpace__ = &memorymulticastfabricGetMapAddrSpace_IMPL; #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) @@ -356,6 +362,8 @@ static void __nvoc_init_funcTable_MemoryMulticastFabric_1(MemoryMulticastFabric pThis->__nvoc_base_Memory.__memIsGpuMapAllowed__ = &__nvoc_thunk_MemoryMulticastFabric_memIsGpuMapAllowed; + pThis->__nvoc_base_Memory.__memIsExportAllowed__ = &__nvoc_thunk_MemoryMulticastFabric_memIsExportAllowed; + pThis->__nvoc_base_Memory.__memGetMapAddrSpace__ = &__nvoc_thunk_MemoryMulticastFabric_memGetMapAddrSpace; pThis->__memorymulticastfabricCheckMemInterUnmap__ = &__nvoc_thunk_Memory_memorymulticastfabricCheckMemInterUnmap; diff --git a/src/nvidia/generated/g_mem_multicast_fabric_nvoc.h b/src/nvidia/generated/g_mem_multicast_fabric_nvoc.h index e266ff0928..3b7c7c3aef 100644 --- a/src/nvidia/generated/g_mem_multicast_fabric_nvoc.h +++ b/src/nvidia/generated/g_mem_multicast_fabric_nvoc.h @@ -54,91 +54,7 @@ extern "C" { // Type Definitions // **************************************************************************** -typedef struct mem_multicast_fabric_attach_mem_info_node -{ - MEMORY_DESCRIPTOR *pPhysMemDesc; - NvHandle hDupedPhysMem; - NvU64 physMapLength; - NODE node; -} MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO_NODE; - -typedef struct mem_multicast_fabric_client_info -{ - void *pOsEvent; - struct Memory *pMemory; -} MEM_MULTICAST_FABRIC_CLIENT_INFO; - -typedef struct mem_multicast_fabric_gpu_info -{ - void *pGpuOsInfo; - OBJGPU *pGpu; - NvU64 gpuProbeHandle; - NvBool bMcflaAlloc; - - // Tracks memory attached using NV00FD_CTRL_CMD_ATTACH_MEM - PNODE pAttachMemInfoTree; -} MEM_MULTICAST_FABRIC_GPU_INFO; - -MAKE_LIST(MemMulticastFabricClientInfoList, MEM_MULTICAST_FABRIC_CLIENT_INFO); - -MAKE_LIST(MemMulticastFabricGpuInfoList, MEM_MULTICAST_FABRIC_GPU_INFO); - -typedef enum -{ - MEM_MULTICAST_FABRIC_TEAM_SETUP_REQUEST = 0, - MEM_MULTICAST_FABRIC_TEAM_RELEASE_REQUEST, -} MEM_MULTICAST_FABRIC_REQUEST_TYPE; - -typedef struct mem_multicast_fabric_descriptor -{ - // Refcount to keep this descriptor alive - NvU64 refCount; - - // List of clients waiting on this object to be ready - MemMulticastFabricClientInfoList waitingClientsList; - - // Mask representing the list of attached GPUs - NvU32 attachedGpusMask; - - // List of attached GPU info - MemMulticastFabricGpuInfoList gpuInfoList; - - // Boolean to be set when pMemDesc is installed - NvBool bMemdescInstalled; - - // Memory descriptor associated with the multicast object - MEMORY_DESCRIPTOR *pMemDesc; - - // Unique handle assigned for the multicast team by FM - NvU64 mcTeamHandle; - - // Status of the multicast team - NV_STATUS mcTeamStatus; - - // Boolean to be set when an Inband request has been sent to FM and is currently in progress - NvBool bInbandReqInProgress; - - // Request Id associated with the Inband request in progress when bInbandReqSent is set to true - NvU64 inbandReqId; - - // Alignment for the multicast FLA allocation - NvU64 alignment; - - // Multicast FLA allocation size - NvU64 allocSize; - - // Page size for the multicast FLA - NvU64 pageSize; - - // Multicast FLA allocation flags - NvU32 allocFlags; - - // Max. number of unique GPUs associated with the multicast object - NvU32 numMaxGpus; - - // No. of unique GPUs currently attached to the multicast object - NvU32 numAttachedGpus; -} MEM_MULTICAST_FABRIC_DESCRIPTOR; +typedef struct mem_multicast_fabric_descriptor MEM_MULTICAST_FABRIC_DESCRIPTOR; #ifdef NVOC_MEM_MULTICAST_FABRIC_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x @@ -159,6 +75,7 @@ struct MemoryMulticastFabric { NV_STATUS (*__memorymulticastfabricIsReady__)(struct MemoryMulticastFabric *, NvBool); NV_STATUS (*__memorymulticastfabricControl__)(struct MemoryMulticastFabric *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__memorymulticastfabricIsGpuMapAllowed__)(struct MemoryMulticastFabric *, struct OBJGPU *); + NvBool (*__memorymulticastfabricIsExportAllowed__)(struct MemoryMulticastFabric *); NV_STATUS (*__memorymulticastfabricGetMapAddrSpace__)(struct MemoryMulticastFabric *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); NV_STATUS (*__memorymulticastfabricCtrlGetInfo__)(struct MemoryMulticastFabric *, NV00FD_CTRL_GET_INFO_PARAMS *); NV_STATUS (*__memorymulticastfabricCtrlAttachMem__)(struct MemoryMulticastFabric *, NV00FD_CTRL_ATTACH_MEM_PARAMS *); @@ -185,7 +102,7 @@ struct MemoryMulticastFabric { void (*__memorymulticastfabricControlSerialization_Epilogue__)(struct MemoryMulticastFabric *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__memorymulticastfabricMap__)(struct MemoryMulticastFabric *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__memorymulticastfabricAccessCallback__)(struct MemoryMulticastFabric *, struct RsClient *, void *, RsAccessRight); - MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc; + MEM_MULTICAST_FABRIC_DESCRIPTOR *PRIVATE_FIELD(pMulticastFabricDesc); }; #ifndef __NVOC_CLASS_MemoryMulticastFabric_TYPEDEF__ @@ -221,6 +138,7 @@ NV_STATUS __nvoc_objCreate_MemoryMulticastFabric(MemoryMulticastFabric**, Dynami #define memorymulticastfabricIsReady(pMemoryMulticastFabric, bCopyConstructorContext) memorymulticastfabricIsReady_DISPATCH(pMemoryMulticastFabric, bCopyConstructorContext) #define memorymulticastfabricControl(pMemoryMulticastFabric, pCallContext, pParams) memorymulticastfabricControl_DISPATCH(pMemoryMulticastFabric, pCallContext, pParams) #define memorymulticastfabricIsGpuMapAllowed(pMemoryMulticastFabric, pGpu) memorymulticastfabricIsGpuMapAllowed_DISPATCH(pMemoryMulticastFabric, pGpu) +#define memorymulticastfabricIsExportAllowed(pMemoryMulticastFabric) memorymulticastfabricIsExportAllowed_DISPATCH(pMemoryMulticastFabric) #define memorymulticastfabricGetMapAddrSpace(pMemoryMulticastFabric, pCallContext, mapFlags, pAddrSpace) memorymulticastfabricGetMapAddrSpace_DISPATCH(pMemoryMulticastFabric, pCallContext, mapFlags, pAddrSpace) #define memorymulticastfabricCtrlGetInfo(pMemoryMulticastFabric, pParams) memorymulticastfabricCtrlGetInfo_DISPATCH(pMemoryMulticastFabric, pParams) #define memorymulticastfabricCtrlAttachMem(pMemoryMulticastFabric, pParams) memorymulticastfabricCtrlAttachMem_DISPATCH(pMemoryMulticastFabric, pParams) @@ -277,6 +195,12 @@ static inline NvBool memorymulticastfabricIsGpuMapAllowed_DISPATCH(struct Memory return pMemoryMulticastFabric->__memorymulticastfabricIsGpuMapAllowed__(pMemoryMulticastFabric, pGpu); } +NvBool memorymulticastfabricIsExportAllowed_IMPL(struct MemoryMulticastFabric *pMemoryMulticastFabric); + +static inline NvBool memorymulticastfabricIsExportAllowed_DISPATCH(struct MemoryMulticastFabric *pMemoryMulticastFabric) { + return pMemoryMulticastFabric->__memorymulticastfabricIsExportAllowed__(pMemoryMulticastFabric); +} + NV_STATUS memorymulticastfabricGetMapAddrSpace_IMPL(struct MemoryMulticastFabric *pMemoryMulticastFabric, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace); static inline NV_STATUS memorymulticastfabricGetMapAddrSpace_DISPATCH(struct MemoryMulticastFabric *pMemoryMulticastFabric, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { @@ -403,11 +327,12 @@ void memorymulticastfabricDestruct_IMPL(struct MemoryMulticastFabric *pMemoryMul NV_STATUS memorymulticastfabricTeamSetupResponseCallback(NvU32 gpuInstance, - NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pMessage); + NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pMessage); #endif // _MEMORYMULTICASTFABRIC_H_ #ifdef __cplusplus } // extern "C" #endif + #endif // _G_MEM_MULTICAST_FABRIC_NVOC_H_ diff --git a/src/nvidia/generated/g_mem_nvoc.c b/src/nvidia/generated/g_mem_nvoc.c index 1c9ea88dc3..08ed1d4c42 100644 --- a/src/nvidia/generated/g_mem_nvoc.c +++ b/src/nvidia/generated/g_mem_nvoc.c @@ -175,6 +175,21 @@ static NvBool __nvoc_thunk_RmResource_memAccessCallback(struct Memory *pResource static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Memory[] = { { /* [0] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) memCtrlCmdGetSurfacePhysAttrLvm_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) + /*flags=*/ 0x0u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x410103u, + /*paramSize=*/ sizeof(NV0041_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Memory.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "memCtrlCmdGetSurfacePhysAttrLvm" +#endif + }, + { /* [1] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -189,7 +204,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Memory[] /*func=*/ "memCtrlCmdGetSurfaceInfoLvm" #endif }, - { /* [1] */ + { /* [2] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -204,7 +219,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Memory[] /*func=*/ "memCtrlCmdGetSurfaceCompressionCoverageLvm" #endif }, - { /* [2] */ + { /* [3] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -219,7 +234,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Memory[] /*func=*/ "memCtrlCmdSurfaceFlushGpuCache" #endif }, - { /* [3] */ + { /* [4] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -234,7 +249,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Memory[] /*func=*/ "memCtrlCmdGetMemPageSize" #endif }, - { /* [4] */ + { /* [5] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -249,7 +264,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Memory[] /*func=*/ "memCtrlCmdSetTag" #endif }, - { /* [5] */ + { /* [6] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -269,7 +284,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Memory[] const struct NVOC_EXPORT_INFO __nvoc_export_info_Memory = { - /*numEntries=*/ 6, + /*numEntries=*/ 7, /*pExportEntries=*/ __nvoc_exported_method_def_Memory }; @@ -328,6 +343,8 @@ static void __nvoc_init_funcTable_Memory_1(Memory *pThis) { pThis->__memIsGpuMapAllowed__ = &memIsGpuMapAllowed_0c883b; + pThis->__memIsExportAllowed__ = &memIsExportAllowed_0c883b; + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__memCtrlCmdGetSurfaceCompressionCoverageLvm__ = &memCtrlCmdGetSurfaceCompressionCoverageLvm_IMPL; #endif @@ -352,6 +369,10 @@ static void __nvoc_init_funcTable_Memory_1(Memory *pThis) { pThis->__memCtrlCmdGetTag__ = &memCtrlCmdGetTag_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) + pThis->__memCtrlCmdGetSurfacePhysAttrLvm__ = &memCtrlCmdGetSurfacePhysAttrLvm_IMPL; +#endif + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__resIsDuplicate__ = &__nvoc_thunk_Memory_resIsDuplicate; pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__resControl__ = &__nvoc_thunk_Memory_resControl; diff --git a/src/nvidia/generated/g_mem_nvoc.h b/src/nvidia/generated/g_mem_nvoc.h index e4c2cc3258..b06237c474 100644 --- a/src/nvidia/generated/g_mem_nvoc.h +++ b/src/nvidia/generated/g_mem_nvoc.h @@ -159,12 +159,14 @@ struct Memory { NV_STATUS (*__memCheckCopyPermissions__)(struct Memory *, struct OBJGPU *, struct Device *); NV_STATUS (*__memIsReady__)(struct Memory *, NvBool); NvBool (*__memIsGpuMapAllowed__)(struct Memory *, struct OBJGPU *); + NvBool (*__memIsExportAllowed__)(struct Memory *); NV_STATUS (*__memCtrlCmdGetSurfaceCompressionCoverageLvm__)(struct Memory *, NV0041_CTRL_GET_SURFACE_COMPRESSION_COVERAGE_PARAMS *); NV_STATUS (*__memCtrlCmdGetSurfaceInfoLvm__)(struct Memory *, NV0041_CTRL_GET_SURFACE_INFO_PARAMS *); NV_STATUS (*__memCtrlCmdSurfaceFlushGpuCache__)(struct Memory *, NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_PARAMS *); NV_STATUS (*__memCtrlCmdGetMemPageSize__)(struct Memory *, NV0041_CTRL_GET_MEM_PAGE_SIZE_PARAMS *); NV_STATUS (*__memCtrlCmdSetTag__)(struct Memory *, NV0041_CTRL_CMD_SET_TAG_PARAMS *); NV_STATUS (*__memCtrlCmdGetTag__)(struct Memory *, NV0041_CTRL_CMD_GET_TAG_PARAMS *); + NV_STATUS (*__memCtrlCmdGetSurfacePhysAttrLvm__)(struct Memory *, NV0041_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS *); NvBool (*__memShareCallback__)(struct Memory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NvU32 (*__memGetRefCount__)(struct Memory *); NV_STATUS (*__memControlFilter__)(struct Memory *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -247,12 +249,14 @@ NV_STATUS __nvoc_objCreate_Memory(Memory**, Dynamic*, NvU32, CALL_CONTEXT * arg_ #define memCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) memCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define memIsReady(pMemory, bCopyConstructorContext) memIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define memIsGpuMapAllowed(pMemory, pGpu) memIsGpuMapAllowed_DISPATCH(pMemory, pGpu) +#define memIsExportAllowed(pMemory) memIsExportAllowed_DISPATCH(pMemory) #define memCtrlCmdGetSurfaceCompressionCoverageLvm(pMemory, pParams) memCtrlCmdGetSurfaceCompressionCoverageLvm_DISPATCH(pMemory, pParams) #define memCtrlCmdGetSurfaceInfoLvm(pMemory, pSurfaceInfoParams) memCtrlCmdGetSurfaceInfoLvm_DISPATCH(pMemory, pSurfaceInfoParams) #define memCtrlCmdSurfaceFlushGpuCache(pMemory, pCacheFlushParams) memCtrlCmdSurfaceFlushGpuCache_DISPATCH(pMemory, pCacheFlushParams) #define memCtrlCmdGetMemPageSize(pMemory, pPageSizeParams) memCtrlCmdGetMemPageSize_DISPATCH(pMemory, pPageSizeParams) #define memCtrlCmdSetTag(pMemory, pParams) memCtrlCmdSetTag_DISPATCH(pMemory, pParams) #define memCtrlCmdGetTag(pMemory, pParams) memCtrlCmdGetTag_DISPATCH(pMemory, pParams) +#define memCtrlCmdGetSurfacePhysAttrLvm(pMemory, pGPAP) memCtrlCmdGetSurfacePhysAttrLvm_DISPATCH(pMemory, pGPAP) #define memShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) memShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define memGetRefCount(pResource) memGetRefCount_DISPATCH(pResource) #define memControlFilter(pResource, pCallContext, pParams) memControlFilter_DISPATCH(pResource, pCallContext, pParams) @@ -339,6 +343,14 @@ static inline NvBool memIsGpuMapAllowed_DISPATCH(struct Memory *pMemory, struct return pMemory->__memIsGpuMapAllowed__(pMemory, pGpu); } +static inline NvBool memIsExportAllowed_0c883b(struct Memory *pMemory) { + return ((NvBool)(0 == 0)); +} + +static inline NvBool memIsExportAllowed_DISPATCH(struct Memory *pMemory) { + return pMemory->__memIsExportAllowed__(pMemory); +} + NV_STATUS memCtrlCmdGetSurfaceCompressionCoverageLvm_IMPL(struct Memory *pMemory, NV0041_CTRL_GET_SURFACE_COMPRESSION_COVERAGE_PARAMS *pParams); static inline NV_STATUS memCtrlCmdGetSurfaceCompressionCoverageLvm_DISPATCH(struct Memory *pMemory, NV0041_CTRL_GET_SURFACE_COMPRESSION_COVERAGE_PARAMS *pParams) { @@ -375,6 +387,12 @@ static inline NV_STATUS memCtrlCmdGetTag_DISPATCH(struct Memory *pMemory, NV0041 return pMemory->__memCtrlCmdGetTag__(pMemory, pParams); } +NV_STATUS memCtrlCmdGetSurfacePhysAttrLvm_IMPL(struct Memory *pMemory, NV0041_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS *pGPAP); + +static inline NV_STATUS memCtrlCmdGetSurfacePhysAttrLvm_DISPATCH(struct Memory *pMemory, NV0041_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS *pGPAP) { + return pMemory->__memCtrlCmdGetSurfacePhysAttrLvm__(pMemory, pGPAP); +} + static inline NvBool memShareCallback_DISPATCH(struct Memory *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { return pResource->__memShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); } @@ -501,4 +519,5 @@ NV_STATUS memGetByHandleAndGroupedGpu_IMPL(struct RsClient *pClient, NvHandle hM #ifdef __cplusplus } // extern "C" #endif + #endif // _G_MEM_NVOC_H_ diff --git a/src/nvidia/generated/g_mig_config_session_nvoc.h b/src/nvidia/generated/g_mig_config_session_nvoc.h index 37ccabe9b0..6bf2b9eaad 100644 --- a/src/nvidia/generated/g_mig_config_session_nvoc.h +++ b/src/nvidia/generated/g_mig_config_session_nvoc.h @@ -236,4 +236,5 @@ void migconfigsessionDestruct_IMPL(struct MIGConfigSession *pMIGConfigSession); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_MIG_CONFIG_SESSION_NVOC_H_ diff --git a/src/nvidia/generated/g_mig_monitor_session_nvoc.h b/src/nvidia/generated/g_mig_monitor_session_nvoc.h index 6792bef246..c0d72295fc 100644 --- a/src/nvidia/generated/g_mig_monitor_session_nvoc.h +++ b/src/nvidia/generated/g_mig_monitor_session_nvoc.h @@ -237,4 +237,5 @@ void migmonitorsessionDestruct_IMPL(struct MIGMonitorSession *pMIGMonitorSession #ifdef __cplusplus } // extern "C" #endif + #endif // _G_MIG_MONITOR_SESSION_NVOC_H_ diff --git a/src/nvidia/generated/g_mmu_fault_buffer_nvoc.h b/src/nvidia/generated/g_mmu_fault_buffer_nvoc.h index 0bef7787f9..55b5f6cccd 100644 --- a/src/nvidia/generated/g_mmu_fault_buffer_nvoc.h +++ b/src/nvidia/generated/g_mmu_fault_buffer_nvoc.h @@ -338,4 +338,5 @@ void faultbufDestruct_IMPL(struct MmuFaultBuffer *pMmuFaultBuffer); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_MMU_FAULT_BUFFER_NVOC_H_ diff --git a/src/nvidia/generated/g_mps_api_nvoc.h b/src/nvidia/generated/g_mps_api_nvoc.h index 2701466b93..5e7199eecd 100644 --- a/src/nvidia/generated/g_mps_api_nvoc.h +++ b/src/nvidia/generated/g_mps_api_nvoc.h @@ -240,4 +240,5 @@ void mpsApiDestruct_IMPL(struct MpsApi *pMpsApi); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_MPS_API_NVOC_H_ diff --git a/src/nvidia/generated/g_no_device_mem_nvoc.c b/src/nvidia/generated/g_no_device_mem_nvoc.c index 0f235883f3..bd66952fbc 100644 --- a/src/nvidia/generated/g_no_device_mem_nvoc.c +++ b/src/nvidia/generated/g_no_device_mem_nvoc.c @@ -109,6 +109,10 @@ static NV_STATUS __nvoc_thunk_RsResource_nodevicememMapTo(struct NoDeviceMemory return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RsResource.offset), pParams); } +static NvBool __nvoc_thunk_Memory_nodevicememIsExportAllowed(struct NoDeviceMemory *pMemory) { + return memIsExportAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_NoDeviceMemory_Memory.offset)); +} + static NvU32 __nvoc_thunk_RsResource_nodevicememGetRefCount(struct NoDeviceMemory *pResource) { return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RsResource.offset)); } @@ -242,6 +246,8 @@ static void __nvoc_init_funcTable_NoDeviceMemory_1(NoDeviceMemory *pThis) { pThis->__nodevicememMapTo__ = &__nvoc_thunk_RsResource_nodevicememMapTo; + pThis->__nodevicememIsExportAllowed__ = &__nvoc_thunk_Memory_nodevicememIsExportAllowed; + pThis->__nodevicememGetRefCount__ = &__nvoc_thunk_RsResource_nodevicememGetRefCount; pThis->__nodevicememAddAdditionalDependants__ = &__nvoc_thunk_RsResource_nodevicememAddAdditionalDependants; diff --git a/src/nvidia/generated/g_no_device_mem_nvoc.h b/src/nvidia/generated/g_no_device_mem_nvoc.h index 928ac7c0aa..25d3465693 100644 --- a/src/nvidia/generated/g_no_device_mem_nvoc.h +++ b/src/nvidia/generated/g_no_device_mem_nvoc.h @@ -59,6 +59,7 @@ struct NoDeviceMemory { NV_STATUS (*__nodevicememCheckMemInterUnmap__)(struct NoDeviceMemory *, NvBool); NvBool (*__nodevicememShareCallback__)(struct NoDeviceMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__nodevicememMapTo__)(struct NoDeviceMemory *, RS_RES_MAP_TO_PARAMS *); + NvBool (*__nodevicememIsExportAllowed__)(struct NoDeviceMemory *); NvU32 (*__nodevicememGetRefCount__)(struct NoDeviceMemory *); void (*__nodevicememAddAdditionalDependants__)(struct RsClient *, struct NoDeviceMemory *, RsResourceRef *); NV_STATUS (*__nodevicememControl_Prologue__)(struct NoDeviceMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -114,6 +115,7 @@ NV_STATUS __nvoc_objCreate_NoDeviceMemory(NoDeviceMemory**, Dynamic*, NvU32, CAL #define nodevicememCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) nodevicememCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) #define nodevicememShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) nodevicememShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define nodevicememMapTo(pResource, pParams) nodevicememMapTo_DISPATCH(pResource, pParams) +#define nodevicememIsExportAllowed(pMemory) nodevicememIsExportAllowed_DISPATCH(pMemory) #define nodevicememGetRefCount(pResource) nodevicememGetRefCount_DISPATCH(pResource) #define nodevicememAddAdditionalDependants(pClient, pResource, pReference) nodevicememAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define nodevicememControl_Prologue(pResource, pCallContext, pParams) nodevicememControl_Prologue_DISPATCH(pResource, pCallContext, pParams) @@ -153,6 +155,10 @@ static inline NV_STATUS nodevicememMapTo_DISPATCH(struct NoDeviceMemory *pResour return pResource->__nodevicememMapTo__(pResource, pParams); } +static inline NvBool nodevicememIsExportAllowed_DISPATCH(struct NoDeviceMemory *pMemory) { + return pMemory->__nodevicememIsExportAllowed__(pMemory); +} + static inline NvU32 nodevicememGetRefCount_DISPATCH(struct NoDeviceMemory *pResource) { return pResource->__nodevicememGetRefCount__(pResource); } @@ -251,4 +257,5 @@ void nodevicememDestruct_IMPL(struct NoDeviceMemory *pNoDeviceMemory); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_NO_DEVICE_MEM_NVOC_H_ diff --git a/src/nvidia/generated/g_nv_debug_dump_nvoc.h b/src/nvidia/generated/g_nv_debug_dump_nvoc.h index 8fbf1d99a8..29fcc5a790 100644 --- a/src/nvidia/generated/g_nv_debug_dump_nvoc.h +++ b/src/nvidia/generated/g_nv_debug_dump_nvoc.h @@ -395,4 +395,5 @@ static inline NV_STATUS nvdFindEngine(struct OBJGPU *pGpu, struct NvDebugDump *p #ifdef __cplusplus } // extern "C" #endif + #endif // _G_NV_DEBUG_DUMP_NVOC_H_ diff --git a/src/nvidia/generated/g_nv_name_released.h b/src/nvidia/generated/g_nv_name_released.h index 26f9bd0a3d..c4a72b2711 100644 --- a/src/nvidia/generated/g_nv_name_released.h +++ b/src/nvidia/generated/g_nv_name_released.h @@ -1509,6 +1509,17 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x20B7, 0x1590, 0x10DE, "NVIDIA A30-24C" }, { 0x20B7, 0x1610, 0x10DE, "NVIDIA A30-1-6CME" }, { 0x20B7, 0x183c, 0x10DE, "NVIDIA A30-2-12CME" }, + { 0x20BF, 0x4450, 0x10DE, "GRID A100B-4C" }, + { 0x20BF, 0x4451, 0x10DE, "GRID A100B-5C" }, + { 0x20BF, 0x4452, 0x10DE, "GRID A100B-8C" }, + { 0x20BF, 0x4453, 0x10DE, "GRID A100B-10C" }, + { 0x20BF, 0x4454, 0x10DE, "GRID A100B-20C" }, + { 0x20BF, 0x4455, 0x10DE, "GRID A100B-40C" }, + { 0x20BF, 0x5560, 0x10DE, "GRID A100B-1-5C" }, + { 0x20BF, 0x5561, 0x10DE, "GRID A100B-2-10C" }, + { 0x20BF, 0x5562, 0x10DE, "GRID A100B-3-20C" }, + { 0x20BF, 0x5563, 0x10DE, "GRID A100B-4-20C" }, + { 0x20BF, 0x5564, 0x10DE, "GRID A100B-7-40C" }, { 0x20F1, 0x1493, 0x10DE, "GRID A100-1-5C" }, { 0x20F1, 0x1494, 0x10DE, "GRID A100-2-10C" }, { 0x20F1, 0x1495, 0x10DE, "GRID A100-3-20C" }, @@ -1550,19 +1561,6 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x20F5, 0x17ca, 0x10DE, "GRID A800D-40C" }, { 0x20F5, 0x17cb, 0x10DE, "GRID A800D-80C" }, { 0x20F5, 0x183f, 0x10DE, "GRID A800D-1-20C" }, - { 0x20F6, 0x17cc, 0x10DE, "GRID A800-1-5CME" }, - { 0x20F6, 0x17cd, 0x10DE, "GRID A800-1-5C" }, - { 0x20F6, 0x17ce, 0x10DE, "GRID A800-2-10C" }, - { 0x20F6, 0x17cf, 0x10DE, "GRID A800-3-20C" }, - { 0x20F6, 0x17d0, 0x10DE, "GRID A800-4-20C" }, - { 0x20F6, 0x17d1, 0x10DE, "GRID A800-7-40C" }, - { 0x20F6, 0x17d2, 0x10DE, "GRID A800-4C" }, - { 0x20F6, 0x17d3, 0x10DE, "GRID A800-5C" }, - { 0x20F6, 0x17d4, 0x10DE, "GRID A800-8C" }, - { 0x20F6, 0x17d5, 0x10DE, "GRID A800-10C" }, - { 0x20F6, 0x17d6, 0x10DE, "GRID A800-20C" }, - { 0x20F6, 0x17d7, 0x10DE, "GRID A800-40C" }, - { 0x20F6, 0x1843, 0x10DE, "GRID A800-1-10C" }, { 0x2230, 0x14fa, 0x10DE, "NVIDIA RTXA6000-1B" }, { 0x2230, 0x14fb, 0x10DE, "NVIDIA RTXA6000-2B" }, { 0x2230, 0x14fc, 0x10DE, "NVIDIA RTXA6000-1Q" }, @@ -1801,6 +1799,21 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x2322, 0x17ee, 0x10DE, "NVIDIA H800-40C" }, { 0x2322, 0x17ef, 0x10DE, "NVIDIA H800-80C" }, { 0x2322, 0x1845, 0x10DE, "NVIDIA H800-1-20C" }, + { 0x2330, 0x187a, 0x10DE, "NVIDIA H100XM-1-10CME" }, + { 0x2330, 0x187b, 0x10DE, "NVIDIA H100XM-1-10C" }, + { 0x2330, 0x187c, 0x10DE, "NVIDIA H100XM-1-20C" }, + { 0x2330, 0x187d, 0x10DE, "NVIDIA H100XM-2-20C" }, + { 0x2330, 0x187e, 0x10DE, "NVIDIA H100XM-3-40C" }, + { 0x2330, 0x187f, 0x10DE, "NVIDIA H100XM-4-40C" }, + { 0x2330, 0x1880, 0x10DE, "NVIDIA H100XM-7-80C" }, + { 0x2330, 0x1881, 0x10DE, "NVIDIA H100XM-4C" }, + { 0x2330, 0x1882, 0x10DE, "NVIDIA H100XM-5C" }, + { 0x2330, 0x1883, 0x10DE, "NVIDIA H100XM-8C" }, + { 0x2330, 0x1884, 0x10DE, "NVIDIA H100XM-10C" }, + { 0x2330, 0x1885, 0x10DE, "NVIDIA H100XM-16C" }, + { 0x2330, 0x1886, 0x10DE, "NVIDIA H100XM-20C" }, + { 0x2330, 0x1887, 0x10DE, "NVIDIA H100XM-40C" }, + { 0x2330, 0x1888, 0x10DE, "NVIDIA H100XM-80C" }, { 0x2331, 0x16d3, 0x10DE, "NVIDIA H100-1-10C" }, { 0x2331, 0x16d4, 0x10DE, "NVIDIA H100-2-20C" }, { 0x2331, 0x16d5, 0x10DE, "NVIDIA H100-3-40C" }, diff --git a/src/nvidia/generated/g_object_nvoc.h b/src/nvidia/generated/g_object_nvoc.h index c4b4fb49d8..8da263c56e 100644 --- a/src/nvidia/generated/g_object_nvoc.h +++ b/src/nvidia/generated/g_object_nvoc.h @@ -188,4 +188,5 @@ static inline struct Object *objGetDirectParent(struct Object *pObj) { #ifdef __cplusplus } // extern "C" #endif + #endif // _G_OBJECT_NVOC_H_ diff --git a/src/nvidia/generated/g_objgpumon_nvoc.h b/src/nvidia/generated/g_objgpumon_nvoc.h index c6c7e246b2..3c1e1b2f5c 100644 --- a/src/nvidia/generated/g_objgpumon_nvoc.h +++ b/src/nvidia/generated/g_objgpumon_nvoc.h @@ -207,4 +207,5 @@ static inline NV_STATUS gpumonGetPerfmonUtilSamples(struct OBJGPU *pGpu, struct #ifdef __cplusplus } // extern "C" #endif + #endif // _G_OBJGPUMON_NVOC_H_ diff --git a/src/nvidia/generated/g_objsweng_nvoc.h b/src/nvidia/generated/g_objsweng_nvoc.h index 587bba7891..b4d62d1707 100644 --- a/src/nvidia/generated/g_objsweng_nvoc.h +++ b/src/nvidia/generated/g_objsweng_nvoc.h @@ -184,4 +184,5 @@ static inline NvBool swengIsPresent_DISPATCH(POBJGPU pGpu, struct OBJSWENG *pEng #ifdef __cplusplus } // extern "C" #endif + #endif // _G_OBJSWENG_NVOC_H_ diff --git a/src/nvidia/generated/g_objtmr_nvoc.c b/src/nvidia/generated/g_objtmr_nvoc.c index 0a40a369d8..b34b186efb 100644 --- a/src/nvidia/generated/g_objtmr_nvoc.c +++ b/src/nvidia/generated/g_objtmr_nvoc.c @@ -75,7 +75,7 @@ const struct NVOC_CLASS_DEF __nvoc_class_def_OBJTMR = /*pExportInfo=*/ &__nvoc_export_info_OBJTMR }; -static void __nvoc_thunk_OBJTMR_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pTmr, IntrServiceRecord pRecords[167]) { +static void __nvoc_thunk_OBJTMR_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pTmr, IntrServiceRecord pRecords[168]) { tmrRegisterIntrService(pGpu, (struct OBJTMR *)(((unsigned char *)pTmr) - __nvoc_rtti_OBJTMR_IntrService.offset), pRecords); } diff --git a/src/nvidia/generated/g_objtmr_nvoc.h b/src/nvidia/generated/g_objtmr_nvoc.h index 6cd1dcef98..2d572db9b9 100644 --- a/src/nvidia/generated/g_objtmr_nvoc.h +++ b/src/nvidia/generated/g_objtmr_nvoc.h @@ -743,9 +743,9 @@ static inline NV_STATUS tmrEventDestroyOSTimer(struct OBJTMR *pTmr, PTMR_EVENT p #define tmrEventDestroyOSTimer_HAL(pTmr, pEvent) tmrEventDestroyOSTimer(pTmr, pEvent) -void tmrRegisterIntrService_IMPL(OBJGPU *pGpu, struct OBJTMR *pTmr, IntrServiceRecord pRecords[167]); +void tmrRegisterIntrService_IMPL(OBJGPU *pGpu, struct OBJTMR *pTmr, IntrServiceRecord pRecords[168]); -static inline void tmrRegisterIntrService_DISPATCH(OBJGPU *pGpu, struct OBJTMR *pTmr, IntrServiceRecord pRecords[167]) { +static inline void tmrRegisterIntrService_DISPATCH(OBJGPU *pGpu, struct OBJTMR *pTmr, IntrServiceRecord pRecords[168]) { pTmr->__tmrRegisterIntrService__(pGpu, pTmr, pRecords); } @@ -1179,4 +1179,5 @@ NV_STATUS tmrCtrlCmdEventDestroy(OBJGPU *pGpu, TMR_EVENT_GENERAL_PARAMS *pParams #ifdef __cplusplus } // extern "C" #endif + #endif // _G_OBJTMR_NVOC_H_ diff --git a/src/nvidia/generated/g_os_desc_mem_nvoc.c b/src/nvidia/generated/g_os_desc_mem_nvoc.c index fc4d7eee0b..b160419bb1 100644 --- a/src/nvidia/generated/g_os_desc_mem_nvoc.c +++ b/src/nvidia/generated/g_os_desc_mem_nvoc.c @@ -113,6 +113,10 @@ static NV_STATUS __nvoc_thunk_Memory_osdescGetMapAddrSpace(struct OsDescMemory * return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_OsDescMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); } +static NvBool __nvoc_thunk_Memory_osdescIsExportAllowed(struct OsDescMemory *pMemory) { + return memIsExportAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_OsDescMemory_Memory.offset)); +} + static NvU32 __nvoc_thunk_RsResource_osdescGetRefCount(struct OsDescMemory *pResource) { return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RsResource.offset)); } @@ -243,6 +247,8 @@ static void __nvoc_init_funcTable_OsDescMemory_1(OsDescMemory *pThis) { pThis->__osdescGetMapAddrSpace__ = &__nvoc_thunk_Memory_osdescGetMapAddrSpace; + pThis->__osdescIsExportAllowed__ = &__nvoc_thunk_Memory_osdescIsExportAllowed; + pThis->__osdescGetRefCount__ = &__nvoc_thunk_RsResource_osdescGetRefCount; pThis->__osdescAddAdditionalDependants__ = &__nvoc_thunk_RsResource_osdescAddAdditionalDependants; diff --git a/src/nvidia/generated/g_os_desc_mem_nvoc.h b/src/nvidia/generated/g_os_desc_mem_nvoc.h index 2aee14bf66..4f31ee5aad 100644 --- a/src/nvidia/generated/g_os_desc_mem_nvoc.h +++ b/src/nvidia/generated/g_os_desc_mem_nvoc.h @@ -58,6 +58,7 @@ struct OsDescMemory { NvBool (*__osdescShareCallback__)(struct OsDescMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__osdescMapTo__)(struct OsDescMemory *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__osdescGetMapAddrSpace__)(struct OsDescMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvBool (*__osdescIsExportAllowed__)(struct OsDescMemory *); NvU32 (*__osdescGetRefCount__)(struct OsDescMemory *); void (*__osdescAddAdditionalDependants__)(struct RsClient *, struct OsDescMemory *, RsResourceRef *); NV_STATUS (*__osdescControl_Prologue__)(struct OsDescMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -113,6 +114,7 @@ NV_STATUS __nvoc_objCreate_OsDescMemory(OsDescMemory**, Dynamic*, NvU32, CALL_CO #define osdescShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) osdescShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define osdescMapTo(pResource, pParams) osdescMapTo_DISPATCH(pResource, pParams) #define osdescGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) osdescGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define osdescIsExportAllowed(pMemory) osdescIsExportAllowed_DISPATCH(pMemory) #define osdescGetRefCount(pResource) osdescGetRefCount_DISPATCH(pResource) #define osdescAddAdditionalDependants(pClient, pResource, pReference) osdescAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define osdescControl_Prologue(pResource, pCallContext, pParams) osdescControl_Prologue_DISPATCH(pResource, pCallContext, pParams) @@ -155,6 +157,10 @@ static inline NV_STATUS osdescGetMapAddrSpace_DISPATCH(struct OsDescMemory *pMem return pMemory->__osdescGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); } +static inline NvBool osdescIsExportAllowed_DISPATCH(struct OsDescMemory *pMemory) { + return pMemory->__osdescIsExportAllowed__(pMemory); +} + static inline NvU32 osdescGetRefCount_DISPATCH(struct OsDescMemory *pResource) { return pResource->__osdescGetRefCount__(pResource); } @@ -246,4 +252,5 @@ NV_STATUS osdescConstruct_IMPL(struct OsDescMemory *arg_pOsDescMemory, CALL_CONT #ifdef __cplusplus } // extern "C" #endif + #endif // _G_OS_DESC_MEM_NVOC_H_ diff --git a/src/nvidia/generated/g_os_nvoc.h b/src/nvidia/generated/g_os_nvoc.h index 60cc7fb8b2..c0edaa2818 100644 --- a/src/nvidia/generated/g_os_nvoc.h +++ b/src/nvidia/generated/g_os_nvoc.h @@ -43,6 +43,7 @@ extern "C" { /* ------------------------ Core & Library Includes ------------------------- */ #include "core/core.h" #include "containers/btree.h" +#include "ctrl/ctrl0073/ctrl0073dfp.h" /* ------------------------ SDK & Interface Includes ------------------------ */ #include "nvsecurityinfo.h" @@ -53,7 +54,6 @@ extern "C" { /* ------------------------ OS Includes ------------------------------------- */ #include "os/nv_memory_type.h" #include "os/capability.h" -#include "os/os_fixed_mode_timings_props.h" /* ------------------------ Forward Declarations ---------------------------- */ struct OBJOS; @@ -236,6 +236,7 @@ typedef struct PACKED_REGISTRY_TABLE PACKED_REGISTRY_ENTRY entries[0]; } PACKED_REGISTRY_TABLE; +// TODO: Merge with NV_REGISTRY_ENTRY_TYPE // // Values for PACKED_REGISTRY_ENTRY::type // @@ -244,6 +245,40 @@ typedef struct PACKED_REGISTRY_TABLE #define REGISTRY_TABLE_ENTRY_TYPE_BINARY 2 #define REGISTRY_TABLE_ENTRY_TYPE_STRING 3 +typedef enum +{ + NV_REGISTRY_ENTRY_TYPE_UNKNOWN = 0, + NV_REGISTRY_ENTRY_TYPE_DWORD, + NV_REGISTRY_ENTRY_TYPE_BINARY, + NV_REGISTRY_ENTRY_TYPE_STRING +} nv_reg_type_t; + +/* + * nv_reg_entry_t + * + * regParmStr/regName + * Name of key + * type + * One of nv_reg_type_t enum + * data + * Integer data of key. Only used with DWORD type + * pdata + * Pointer to data of key. Only used with BINARY or STRING type + * len + * Length of pdata buffer. Only used with BINARY or STRING type + * next + * Next entry in linked list + */ +typedef struct nv_reg_entry_s +{ + char *regParmStr; + NvU32 type; + NvU32 data; + NvU8 *pdata; + NvU32 len; + struct nv_reg_entry_s *next; +} nv_reg_entry_t; + /* * OS_DRIVER_BLOCK * @@ -340,7 +375,7 @@ typedef NV_STATUS NV_FORCERESULTCHECK OSMapSystemMemory(MEMORY_DESCRIPTOR *, Nv typedef void OSUnmapSystemMemory(MEMORY_DESCRIPTOR *, NvBool, NvU32, NvP64, NvP64); typedef NvBool OSLockShouldToggleInterrupts(OBJGPU *); typedef NV_STATUS OSGetPerformanceCounter(NvU64 *); -typedef NvBool OSDbgBreakpointEnabled(void); +NvBool osDbgBreakpointEnabled(void); typedef NV_STATUS OSAttachGpu(OBJGPU *, void *); typedef NV_STATUS OSDpcAttachGpu(OBJGPU *, void *); typedef void OSDpcDetachGpu(OBJGPU *); @@ -385,9 +420,14 @@ typedef NvBool OSIsEqualGUID(void *, void *); #define OS_QUEUE_WORKITEM_FLAGS_FOR_PM_RESUME NVBIT(18) typedef void OSWorkItemFunction(NvU32 gpuInstance, void *); typedef void OSSystemWorkItemFunction(void *); -typedef NV_STATUS OSQueueWorkItem(OBJGPU *, OSWorkItemFunction, void *); -typedef NV_STATUS OSQueueWorkItemWithFlags(OBJGPU *, OSWorkItemFunction, void *, NvU32); -typedef NV_STATUS OSQueueSystemWorkItem(OSSystemWorkItemFunction, void *); +NV_STATUS osQueueWorkItemWithFlags(OBJGPU *, OSWorkItemFunction, void *, NvU32); + +static NV_INLINE NV_STATUS osQueueWorkItem(OBJGPU *pGpu, OSWorkItemFunction pFunction, void *pParams) +{ + return osQueueWorkItemWithFlags(pGpu, pFunction, pParams, OS_QUEUE_WORKITEM_FLAGS_NONE); +} + +NV_STATUS osQueueSystemWorkItem(OSSystemWorkItemFunction, void *); // MXM ACPI calls NV_STATUS osCallACPI_MXMX(OBJGPU *, NvU32, NvU8 *); @@ -403,12 +443,12 @@ NV_STATUS osCallACPI_LRST(OBJGPU *, NvU32, NvU32 *); // Hybrid GPU ACPI calls NV_STATUS osCallACPI_NVHG_GPUON(OBJGPU *, NvU32 *); NV_STATUS osCallACPI_NVHG_GPUOFF(OBJGPU *, NvU32 *); -typedef NV_STATUS OSCallACPI_NVHG_GPUSTA(OBJGPU *, NvU32 *); -typedef NV_STATUS OSCallACPI_NVHG_MXDS(OBJGPU *, NvU32, NvU32 *); -typedef NV_STATUS OSCallACPI_NVHG_MXMX(OBJGPU *, NvU32, NvU32 *); -typedef NV_STATUS OSCallACPI_NVHG_DOS(OBJGPU *, NvU32, NvU32 *); +NV_STATUS osCallACPI_NVHG_GPUSTA(OBJGPU *, NvU32 *); +NV_STATUS osCallACPI_NVHG_MXDS(OBJGPU *, NvU32, NvU32 *); +NV_STATUS osCallACPI_NVHG_MXMX(OBJGPU *, NvU32, NvU32 *); +NV_STATUS osCallACPI_NVHG_DOS(OBJGPU *, NvU32, NvU32 *); NV_STATUS osCallACPI_NVHG_ROM(OBJGPU *, NvU32 *, NvU32 *); -typedef NV_STATUS OSCallACPI_NVHG_DCS(OBJGPU *, NvU32, NvU32 *); +NV_STATUS osCallACPI_NVHG_DCS(OBJGPU *, NvU32, NvU32 *); NV_STATUS osCallACPI_DOD(OBJGPU *, NvU32 *, NvU32 *); // Tegra ACPI calls @@ -423,10 +463,10 @@ NV_STATUS osCallACPI_DSM(OBJGPU *pGpu, ACPI_DSM_FUNCTION acpiDSMFunction, NvU32 NVHGDSMSubfunction, NvU32 *pInOut, NvU16 *size); // UEFI variable calls -typedef NV_STATUS OSGetUefiVariable(OBJGPU *, char *, LPGUID, NvU8 *, NvU32 *, NvU32 *); +NV_STATUS osGetUefiVariable(const char *, LPGUID, NvU8 *, NvU32 *); // The following functions are also implemented in WinNT -typedef void OSQADbgRegistryInit(struct OBJOS *); +void osQADbgRegistryInit(void); typedef NV_STATUS OSGetVersionDump(void *); // End of WinNT @@ -442,14 +482,12 @@ typedef NvU32 OSnv_rdmsr(struct OBJOS *, NvU32, NvU32 *, NvU32 *); typedef NvU32 OSnv_wrmsr(struct OBJOS *, NvU32, NvU32, NvU32); // end functions shared by MacOS and UNIX -typedef NvU32 OSRobustChannelsDefaultState(struct OBJOS *); - // NOTE: The following functions are also implemented in MODS -typedef NV_STATUS OSSimEscapeWrite(OBJGPU *, const char *path, NvU32 Index, NvU32 Size, NvU32 Value); -typedef NV_STATUS OSSimEscapeWriteBuffer(OBJGPU *, const char *path, NvU32 Index, NvU32 Size, void* pBuffer); -typedef NV_STATUS OSSimEscapeRead(OBJGPU *, const char *path, NvU32 Index, NvU32 Size, NvU32 *Value); -typedef NV_STATUS OSSimEscapeReadBuffer(OBJGPU *, const char *path, NvU32 Index, NvU32 Size, void* pBuffer); -typedef NvU32 OSGetSimulationMode(void); +NV_STATUS osSimEscapeWrite(OBJGPU *, const char *path, NvU32 Index, NvU32 Size, NvU32 Value); +NV_STATUS osSimEscapeWriteBuffer(OBJGPU *, const char *path, NvU32 Index, NvU32 Size, void* pBuffer); +NV_STATUS osSimEscapeRead(OBJGPU *, const char *path, NvU32 Index, NvU32 Size, NvU32 *Value); +NV_STATUS osSimEscapeReadBuffer(OBJGPU *, const char *path, NvU32 Index, NvU32 Size, void* pBuffer); +NvU32 osGetSimulationMode(void); typedef void OSLogString(const char*, ...); typedef void OSFlushLog(void); typedef void OSSetSurfaceName(void *pDescriptor, char *name); @@ -458,8 +496,8 @@ typedef void OSSetSurfaceName(void *pDescriptor, char *name); //Vista Specific Functions -typedef NV_STATUS OSSetupVBlank(OBJGPU *pGpu, void * pProc, - void * pParm1, void * pParm2, NvU32 Head, void * pParm3); +NV_STATUS osSetupVBlank(OBJGPU *pGpu, void * pProc, + void * pParm1, void * pParm2, NvU32 Head, void * pParm3); // Heap reserve tracking functions typedef void OSInternalReserveAllocCallback(NvU64 offset, NvU64 size, NvU32 gpuId); @@ -580,8 +618,10 @@ typedef enum RC_CALLBACK_ISOLATE, RC_CALLBACK_ISOLATE_NO_RESET, } RC_CALLBACK_STATUS; -typedef RC_CALLBACK_STATUS OSRCCallback(OBJGPU *, NvHandle, NvHandle, NvHandle, NvHandle, NvU32, NvU32, NvU32 *, void *); -typedef NvBool OSCheckCallback(OBJGPU *); +RC_CALLBACK_STATUS osRCCallback(OBJGPU *, NvHandle, NvHandle, NvHandle, NvHandle, NvU32, NvU32, NvU32 *, void *); +NvBool osCheckCallback(OBJGPU *); +RC_CALLBACK_STATUS osRCCallback_v2(OBJGPU *, NvHandle, NvHandle, NvHandle, NvHandle, NvU32, NvU32, NvBool, NvU32 *, void *); +NvBool osCheckCallback_v2(OBJGPU *); typedef NV_STATUS OSReadPFPciConfigInVF(NvU32, NvU32*); // Actual definition of the OBJOS structure @@ -608,33 +648,12 @@ struct OBJOS { NvBool PDB_PROP_OS_SUPPORTS_DISPLAY_REMAPPER; NvBool PDB_PROP_OS_DOES_NOT_ALLOW_DIRECT_PCIE_MAPPINGS; NvBool PDB_PROP_OS_NO_PAGED_SEGMENT_ACCESS; - OSDbgBreakpointEnabled *osDbgBreakpointEnabled; - OSQADbgRegistryInit *osQADbgRegistryInit; - OSQueueWorkItem *osQueueWorkItem; - OSQueueWorkItemWithFlags *osQueueWorkItemWithFlags; - OSQueueSystemWorkItem *osQueueSystemWorkItem; - void *(*osGetStereoDongleInterface)(void); OSnv_rdcr4 *osNv_rdcr4; OSnv_rdxcr0 *osNv_rdxcr0; OSnv_cpuid *osNv_cpuid; OSnv_rdmsr *osNv_rdmsr; OSnv_wrmsr *osNv_wrmsr; - OSRobustChannelsDefaultState *osRobustChannelsDefaultState; - OSSimEscapeWrite *osSimEscapeWrite; - OSSimEscapeWriteBuffer *osSimEscapeWriteBuffer; - OSSimEscapeRead *osSimEscapeRead; - OSSimEscapeReadBuffer *osSimEscapeReadBuffer; OSRmInitRm *osRmInitRm; - OSGetSimulationMode *osGetSimulationMode; - OSCallACPI_NVHG_GPUSTA *osCallACPI_NVHG_GPUSTA; - OSCallACPI_NVHG_MXDS *osCallACPI_NVHG_MXDS; - OSCallACPI_NVHG_MXMX *osCallACPI_NVHG_MXMX; - OSCallACPI_NVHG_DOS *osCallACPI_NVHG_DOS; - OSCallACPI_NVHG_DCS *osCallACPI_NVHG_DCS; - OSGetUefiVariable *osGetUefiVariable; - OSCheckCallback *osCheckCallback; - OSRCCallback *osRCCallback; - OSSetupVBlank *osSetupVBlank; OSPexRecoveryCallback *osPexRecoveryCallback; OSInternalReserveAllocCallback *osInternalReserveAllocCallback; OSInternalReserveFreeCallback *osInternalReserveFreeCallback; @@ -918,7 +937,8 @@ NV_STATUS osGetSyncpointAperture(OS_GPU_INFO *pOsGpuInfo, NV_STATUS osTegraI2CGetBusState(OS_GPU_INFO *pOsGpuInfo, NvU32 port, NvS32 *scl, NvS32 *sda); NV_STATUS osTegraSocParseFixedModeTimings(OS_GPU_INFO *pOsGpuInfo, NvU32 dcbIndex, - OS_FIXED_MODE_TIMINGS *pFixedModeTimings); + NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS *pTimingsPerStream, + NvU8 *pNumTimings); NV_STATUS osGetVersion(NvU32 *pMajorVer, NvU32 *pMinorVer, @@ -1351,6 +1371,8 @@ OSReadRegistryStringBase osReadRegistryStringBase; OSPackageRegistry osPackageRegistry; OSUnpackageRegistry osUnpackageRegistry; NV_STATUS osDestroyRegistry(void); +nv_reg_entry_t* osGetRegistryList(void); +NV_STATUS osSetRegistryList(nv_reg_entry_t *pRegList); OSMapPciMemoryUser osMapPciMemoryUser; OSUnmapPciMemoryUser osUnmapPciMemoryUser; OSMapPciMemoryKernelOld osMapPciMemoryKernelOld; @@ -1448,7 +1470,6 @@ extern NV_STATUS constructObjOS(struct OBJOS *); extern void osInitObjOS(struct OBJOS *); extern OSGetTimeoutParams osGetTimeoutParams; -extern OSGetSimulationMode osGetSimulationMode; // // NV OS simulation mode defines @@ -1509,4 +1530,5 @@ extern OSGetSimulationMode osGetSimulationMode; #ifdef __cplusplus } // extern "C" #endif + #endif // _G_OS_NVOC_H_ diff --git a/src/nvidia/generated/g_p2p_api_nvoc.h b/src/nvidia/generated/g_p2p_api_nvoc.h index c33a4bd35b..ede81ca2bd 100644 --- a/src/nvidia/generated/g_p2p_api_nvoc.h +++ b/src/nvidia/generated/g_p2p_api_nvoc.h @@ -248,4 +248,5 @@ void p2papiDestruct_IMPL(struct P2PApi *pResource); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_P2P_API_NVOC_H_ diff --git a/src/nvidia/generated/g_phys_mem_nvoc.c b/src/nvidia/generated/g_phys_mem_nvoc.c index 139e5a4048..78880540f0 100644 --- a/src/nvidia/generated/g_phys_mem_nvoc.c +++ b/src/nvidia/generated/g_phys_mem_nvoc.c @@ -113,6 +113,10 @@ static NV_STATUS __nvoc_thunk_Memory_physmemGetMapAddrSpace(struct PhysicalMemor return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_PhysicalMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); } +static NvBool __nvoc_thunk_Memory_physmemIsExportAllowed(struct PhysicalMemory *pMemory) { + return memIsExportAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_PhysicalMemory_Memory.offset)); +} + static NvU32 __nvoc_thunk_RsResource_physmemGetRefCount(struct PhysicalMemory *pResource) { return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RsResource.offset)); } @@ -243,6 +247,8 @@ static void __nvoc_init_funcTable_PhysicalMemory_1(PhysicalMemory *pThis) { pThis->__physmemGetMapAddrSpace__ = &__nvoc_thunk_Memory_physmemGetMapAddrSpace; + pThis->__physmemIsExportAllowed__ = &__nvoc_thunk_Memory_physmemIsExportAllowed; + pThis->__physmemGetRefCount__ = &__nvoc_thunk_RsResource_physmemGetRefCount; pThis->__physmemAddAdditionalDependants__ = &__nvoc_thunk_RsResource_physmemAddAdditionalDependants; diff --git a/src/nvidia/generated/g_phys_mem_nvoc.h b/src/nvidia/generated/g_phys_mem_nvoc.h index 77c9ce4881..b1d2f903cc 100644 --- a/src/nvidia/generated/g_phys_mem_nvoc.h +++ b/src/nvidia/generated/g_phys_mem_nvoc.h @@ -60,6 +60,7 @@ struct PhysicalMemory { NvBool (*__physmemShareCallback__)(struct PhysicalMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__physmemMapTo__)(struct PhysicalMemory *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__physmemGetMapAddrSpace__)(struct PhysicalMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvBool (*__physmemIsExportAllowed__)(struct PhysicalMemory *); NvU32 (*__physmemGetRefCount__)(struct PhysicalMemory *); void (*__physmemAddAdditionalDependants__)(struct RsClient *, struct PhysicalMemory *, RsResourceRef *); NV_STATUS (*__physmemControl_Prologue__)(struct PhysicalMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -115,6 +116,7 @@ NV_STATUS __nvoc_objCreate_PhysicalMemory(PhysicalMemory**, Dynamic*, NvU32, CAL #define physmemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) physmemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define physmemMapTo(pResource, pParams) physmemMapTo_DISPATCH(pResource, pParams) #define physmemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) physmemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define physmemIsExportAllowed(pMemory) physmemIsExportAllowed_DISPATCH(pMemory) #define physmemGetRefCount(pResource) physmemGetRefCount_DISPATCH(pResource) #define physmemAddAdditionalDependants(pClient, pResource, pReference) physmemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define physmemControl_Prologue(pResource, pCallContext, pParams) physmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) @@ -157,6 +159,10 @@ static inline NV_STATUS physmemGetMapAddrSpace_DISPATCH(struct PhysicalMemory *p return pMemory->__physmemGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); } +static inline NvBool physmemIsExportAllowed_DISPATCH(struct PhysicalMemory *pMemory) { + return pMemory->__physmemIsExportAllowed__(pMemory); +} + static inline NvU32 physmemGetRefCount_DISPATCH(struct PhysicalMemory *pResource) { return pResource->__physmemGetRefCount__(pResource); } @@ -248,4 +254,5 @@ NV_STATUS physmemConstruct_IMPL(struct PhysicalMemory *arg_pPhysicalMemory, CALL #ifdef __cplusplus } // extern "C" #endif + #endif // _G_PHYS_MEM_NVOC_H_ diff --git a/src/nvidia/generated/g_platform_nvoc.h b/src/nvidia/generated/g_platform_nvoc.h index a2f7b62df4..2e8560ce2c 100644 --- a/src/nvidia/generated/g_platform_nvoc.h +++ b/src/nvidia/generated/g_platform_nvoc.h @@ -226,4 +226,5 @@ static inline void pfmUpdateDeviceAcpiId(struct OBJPFM *arg0, OBJGPU *arg1, NvU3 #ifdef __cplusplus } // extern "C" #endif + #endif // _G_PLATFORM_NVOC_H_ diff --git a/src/nvidia/generated/g_platform_request_handler_nvoc.h b/src/nvidia/generated/g_platform_request_handler_nvoc.h index 74f817530a..778740a443 100644 --- a/src/nvidia/generated/g_platform_request_handler_nvoc.h +++ b/src/nvidia/generated/g_platform_request_handler_nvoc.h @@ -525,4 +525,5 @@ NV_STATUS pfmreqhndlrGetPerfSensorCounters (NV0000_CTRL_SYSTEM_PFM_ #ifdef __cplusplus } // extern "C" #endif + #endif // _G_PLATFORM_REQUEST_HANDLER_NVOC_H_ diff --git a/src/nvidia/generated/g_prereq_tracker_nvoc.h b/src/nvidia/generated/g_prereq_tracker_nvoc.h index 7e15edb23a..f7a410072e 100644 --- a/src/nvidia/generated/g_prereq_tracker_nvoc.h +++ b/src/nvidia/generated/g_prereq_tracker_nvoc.h @@ -257,4 +257,5 @@ static inline NV_STATUS prereqComposeEntry(struct PrereqTracker *pTracker, GpuPr #ifdef __cplusplus } // extern "C" #endif + #endif // _G_PREREQ_TRACKER_NVOC_H_ diff --git a/src/nvidia/generated/g_profiler_v1_nvoc.h b/src/nvidia/generated/g_profiler_v1_nvoc.h index b2220bd374..730b990e7c 100644 --- a/src/nvidia/generated/g_profiler_v1_nvoc.h +++ b/src/nvidia/generated/g_profiler_v1_nvoc.h @@ -341,4 +341,5 @@ NV_STATUS profilerConstruct_IMPL(struct Profiler *arg_pProfiler, struct CALL_CON #ifdef __cplusplus } // extern "C" #endif + #endif // _G_PROFILER_V1_NVOC_H_ diff --git a/src/nvidia/generated/g_profiler_v2_nvoc.c b/src/nvidia/generated/g_profiler_v2_nvoc.c index 15948201dc..703b7ae3a0 100644 --- a/src/nvidia/generated/g_profiler_v2_nvoc.c +++ b/src/nvidia/generated/g_profiler_v2_nvoc.c @@ -455,6 +455,36 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler #endif }, { /* [17] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdDisableDynamicMMABoost_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xb0cc0117u, + /*paramSize=*/ sizeof(NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_ProfilerBase.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "profilerBaseCtrlCmdDisableDynamicMMABoost" +#endif + }, + { /* [18] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdGetDynamicMMABoostStatus_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xb0cc0118u, + /*paramSize=*/ sizeof(NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_ProfilerBase.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "profilerBaseCtrlCmdGetDynamicMMABoostStatus" +#endif + }, + { /* [19] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -469,7 +499,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler /*func=*/ "profilerBaseCtrlCmdInternalPermissionsInit" #endif }, - { /* [18] */ + { /* [20] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -484,7 +514,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler /*func=*/ "profilerBaseCtrlCmdInternalAllocPmaStream" #endif }, - { /* [19] */ + { /* [21] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -499,7 +529,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler /*func=*/ "profilerBaseCtrlCmdInternalFreePmaStream" #endif }, - { /* [20] */ + { /* [22] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -514,7 +544,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler /*func=*/ "profilerBaseCtrlCmdInternalGetMaxPmas" #endif }, - { /* [21] */ + { /* [23] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -529,7 +559,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler /*func=*/ "profilerBaseCtrlCmdInternalBindPmResources" #endif }, - { /* [22] */ + { /* [24] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -544,7 +574,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler /*func=*/ "profilerBaseCtrlCmdInternalUnbindPmResources" #endif }, - { /* [23] */ + { /* [25] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -559,7 +589,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler /*func=*/ "profilerBaseCtrlCmdInternalReserveHwpmLegacy" #endif }, - { /* [24] */ + { /* [26] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -574,7 +604,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler /*func=*/ "profilerBaseCtrlCmdRequestCgControls" #endif }, - { /* [25] */ + { /* [27] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -594,7 +624,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler const struct NVOC_EXPORT_INFO __nvoc_export_info_ProfilerBase = { - /*numEntries=*/ 26, + /*numEntries=*/ 28, /*pExportEntries=*/ __nvoc_exported_method_def_ProfilerBase }; @@ -745,6 +775,14 @@ static void __nvoc_init_funcTable_ProfilerBase_1(ProfilerBase *pThis, RmHalspecO pThis->__profilerBaseCtrlCmdReleaseCgControls__ = &profilerBaseCtrlCmdReleaseCgControls_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + pThis->__profilerBaseCtrlCmdDisableDynamicMMABoost__ = &profilerBaseCtrlCmdDisableDynamicMMABoost_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + pThis->__profilerBaseCtrlCmdGetDynamicMMABoostStatus__ = &profilerBaseCtrlCmdGetDynamicMMABoostStatus_IMPL; +#endif + pThis->__profilerBaseShareCallback__ = &__nvoc_thunk_GpuResource_profilerBaseShareCallback; pThis->__profilerBaseCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_profilerBaseCheckMemInterUnmap; diff --git a/src/nvidia/generated/g_profiler_v2_nvoc.h b/src/nvidia/generated/g_profiler_v2_nvoc.h index d84a9a4918..d40973c23c 100644 --- a/src/nvidia/generated/g_profiler_v2_nvoc.h +++ b/src/nvidia/generated/g_profiler_v2_nvoc.h @@ -92,6 +92,8 @@ struct ProfilerBase { NV_STATUS (*__profilerBaseCtrlCmdReleaseHes__)(struct ProfilerBase *, NVB0CC_CTRL_RELEASE_HES_PARAMS *); NV_STATUS (*__profilerBaseCtrlCmdRequestCgControls__)(struct ProfilerBase *, NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS *); NV_STATUS (*__profilerBaseCtrlCmdReleaseCgControls__)(struct ProfilerBase *, NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS *); + NV_STATUS (*__profilerBaseCtrlCmdDisableDynamicMMABoost__)(struct ProfilerBase *, NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS *); + NV_STATUS (*__profilerBaseCtrlCmdGetDynamicMMABoostStatus__)(struct ProfilerBase *, NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS *); NvBool (*__profilerBaseShareCallback__)(struct ProfilerBase *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__profilerBaseCheckMemInterUnmap__)(struct ProfilerBase *, NvBool); NV_STATUS (*__profilerBaseMapTo__)(struct ProfilerBase *, RS_RES_MAP_TO_PARAMS *); @@ -180,6 +182,8 @@ NV_STATUS __nvoc_objCreate_ProfilerBase(ProfilerBase**, Dynamic*, NvU32, struct #define profilerBaseCtrlCmdReleaseHes(pProfiler, pParams) profilerBaseCtrlCmdReleaseHes_DISPATCH(pProfiler, pParams) #define profilerBaseCtrlCmdRequestCgControls(pProfiler, pParams) profilerBaseCtrlCmdRequestCgControls_DISPATCH(pProfiler, pParams) #define profilerBaseCtrlCmdReleaseCgControls(pProfiler, pParams) profilerBaseCtrlCmdReleaseCgControls_DISPATCH(pProfiler, pParams) +#define profilerBaseCtrlCmdDisableDynamicMMABoost(pProfiler, pParams) profilerBaseCtrlCmdDisableDynamicMMABoost_DISPATCH(pProfiler, pParams) +#define profilerBaseCtrlCmdGetDynamicMMABoostStatus(pProfiler, pParams) profilerBaseCtrlCmdGetDynamicMMABoostStatus_DISPATCH(pProfiler, pParams) #define profilerBaseShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) profilerBaseShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) #define profilerBaseCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) profilerBaseCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define profilerBaseMapTo(pResource, pParams) profilerBaseMapTo_DISPATCH(pResource, pParams) @@ -392,6 +396,18 @@ static inline NV_STATUS profilerBaseCtrlCmdReleaseCgControls_DISPATCH(struct Pro return pProfiler->__profilerBaseCtrlCmdReleaseCgControls__(pProfiler, pParams); } +NV_STATUS profilerBaseCtrlCmdDisableDynamicMMABoost_IMPL(struct ProfilerBase *pProfiler, NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS *pParams); + +static inline NV_STATUS profilerBaseCtrlCmdDisableDynamicMMABoost_DISPATCH(struct ProfilerBase *pProfiler, NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS *pParams) { + return pProfiler->__profilerBaseCtrlCmdDisableDynamicMMABoost__(pProfiler, pParams); +} + +NV_STATUS profilerBaseCtrlCmdGetDynamicMMABoostStatus_IMPL(struct ProfilerBase *pProfiler, NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS *pParams); + +static inline NV_STATUS profilerBaseCtrlCmdGetDynamicMMABoostStatus_DISPATCH(struct ProfilerBase *pProfiler, NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS *pParams) { + return pProfiler->__profilerBaseCtrlCmdGetDynamicMMABoostStatus__(pProfiler, pParams); +} + static inline NvBool profilerBaseShareCallback_DISPATCH(struct ProfilerBase *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { return pGpuResource->__profilerBaseShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } @@ -794,4 +810,5 @@ void profilerDevDestruct_IMPL(struct ProfilerDev *pResource); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_PROFILER_V2_NVOC_H_ diff --git a/src/nvidia/generated/g_ref_count_nvoc.h b/src/nvidia/generated/g_ref_count_nvoc.h index dfdb5ed346..ea72aec267 100644 --- a/src/nvidia/generated/g_ref_count_nvoc.h +++ b/src/nvidia/generated/g_ref_count_nvoc.h @@ -185,4 +185,5 @@ static inline NV_STATUS refcntReset(POBJREFCNT pRefcnt, NvBool arg0) { #ifdef __cplusplus } // extern "C" #endif + #endif // _G_REF_COUNT_NVOC_H_ diff --git a/src/nvidia/generated/g_reg_mem_nvoc.c b/src/nvidia/generated/g_reg_mem_nvoc.c index 03b247d8b7..5e04684376 100644 --- a/src/nvidia/generated/g_reg_mem_nvoc.c +++ b/src/nvidia/generated/g_reg_mem_nvoc.c @@ -113,6 +113,10 @@ static NV_STATUS __nvoc_thunk_Memory_regmemGetMapAddrSpace(struct RegisterMemory return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_RegisterMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); } +static NvBool __nvoc_thunk_Memory_regmemIsExportAllowed(struct RegisterMemory *pMemory) { + return memIsExportAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_RegisterMemory_Memory.offset)); +} + static NvU32 __nvoc_thunk_RsResource_regmemGetRefCount(struct RegisterMemory *pResource) { return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RsResource.offset)); } @@ -243,6 +247,8 @@ static void __nvoc_init_funcTable_RegisterMemory_1(RegisterMemory *pThis) { pThis->__regmemGetMapAddrSpace__ = &__nvoc_thunk_Memory_regmemGetMapAddrSpace; + pThis->__regmemIsExportAllowed__ = &__nvoc_thunk_Memory_regmemIsExportAllowed; + pThis->__regmemGetRefCount__ = &__nvoc_thunk_RsResource_regmemGetRefCount; pThis->__regmemAddAdditionalDependants__ = &__nvoc_thunk_RsResource_regmemAddAdditionalDependants; diff --git a/src/nvidia/generated/g_reg_mem_nvoc.h b/src/nvidia/generated/g_reg_mem_nvoc.h index 6156a0fda1..80c8c65221 100644 --- a/src/nvidia/generated/g_reg_mem_nvoc.h +++ b/src/nvidia/generated/g_reg_mem_nvoc.h @@ -60,6 +60,7 @@ struct RegisterMemory { NvBool (*__regmemShareCallback__)(struct RegisterMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__regmemMapTo__)(struct RegisterMemory *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__regmemGetMapAddrSpace__)(struct RegisterMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvBool (*__regmemIsExportAllowed__)(struct RegisterMemory *); NvU32 (*__regmemGetRefCount__)(struct RegisterMemory *); void (*__regmemAddAdditionalDependants__)(struct RsClient *, struct RegisterMemory *, RsResourceRef *); NV_STATUS (*__regmemControl_Prologue__)(struct RegisterMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -115,6 +116,7 @@ NV_STATUS __nvoc_objCreate_RegisterMemory(RegisterMemory**, Dynamic*, NvU32, CAL #define regmemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) regmemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define regmemMapTo(pResource, pParams) regmemMapTo_DISPATCH(pResource, pParams) #define regmemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) regmemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define regmemIsExportAllowed(pMemory) regmemIsExportAllowed_DISPATCH(pMemory) #define regmemGetRefCount(pResource) regmemGetRefCount_DISPATCH(pResource) #define regmemAddAdditionalDependants(pClient, pResource, pReference) regmemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define regmemControl_Prologue(pResource, pCallContext, pParams) regmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) @@ -157,6 +159,10 @@ static inline NV_STATUS regmemGetMapAddrSpace_DISPATCH(struct RegisterMemory *pM return pMemory->__regmemGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); } +static inline NvBool regmemIsExportAllowed_DISPATCH(struct RegisterMemory *pMemory) { + return pMemory->__regmemIsExportAllowed__(pMemory); +} + static inline NvU32 regmemGetRefCount_DISPATCH(struct RegisterMemory *pResource) { return pResource->__regmemGetRefCount__(pResource); } @@ -248,4 +254,5 @@ NV_STATUS regmemConstruct_IMPL(struct RegisterMemory *arg_pRegisterMemory, CALL_ #ifdef __cplusplus } // extern "C" #endif + #endif // _G_REG_MEM_NVOC_H_ diff --git a/src/nvidia/generated/g_resource_fwd_decls_nvoc.h b/src/nvidia/generated/g_resource_fwd_decls_nvoc.h index 37ce899a95..a9a0a1ee80 100644 --- a/src/nvidia/generated/g_resource_fwd_decls_nvoc.h +++ b/src/nvidia/generated/g_resource_fwd_decls_nvoc.h @@ -1184,6 +1184,7 @@ struct NVOCFwdDeclHack { struct KernelHostVgpuDeviceApi *PRIVATE_FIELD(KernelHostVgpuDeviceApi_NVA084_KERNEL_HOST_VGPU_DEVICE); struct ThirdPartyP2P *PRIVATE_FIELD(ThirdPartyP2P_NV50_THIRD_PARTY_P2P); struct GenericEngineApi *PRIVATE_FIELD(GenericEngineApi_GF100_SUBDEVICE_MASTER); + struct GenericEngineApi *PRIVATE_FIELD(GenericEngineApi_GF100_SUBDEVICE_INFOROM); struct TimerApi *PRIVATE_FIELD(TimerApi_NV01_TIMER); struct I2cApi *PRIVATE_FIELD(I2cApi_NV40_I2C); struct DiagApi *PRIVATE_FIELD(DiagApi_NV20_SUBDEVICE_DIAG); @@ -1310,4 +1311,5 @@ NV_STATUS __nvoc_objCreate_NVOCFwdDeclHack(NVOCFwdDeclHack**, Dynamic*, NvU32); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_RESOURCE_FWD_DECLS_NVOC_H_ diff --git a/src/nvidia/generated/g_resource_nvoc.h b/src/nvidia/generated/g_resource_nvoc.h index 5e26bb272f..afb12d1fe4 100644 --- a/src/nvidia/generated/g_resource_nvoc.h +++ b/src/nvidia/generated/g_resource_nvoc.h @@ -376,4 +376,5 @@ NV_STATUS rmresConstruct_IMPL(struct RmResource *arg_pResource, struct CALL_CONT #ifdef __cplusplus } // extern "C" #endif + #endif // _G_RESOURCE_NVOC_H_ diff --git a/src/nvidia/generated/g_resserv_nvoc.h b/src/nvidia/generated/g_resserv_nvoc.h index a68bb80139..80c4810e05 100644 --- a/src/nvidia/generated/g_resserv_nvoc.h +++ b/src/nvidia/generated/g_resserv_nvoc.h @@ -423,4 +423,5 @@ struct ACCESS_CONTROL #ifdef __cplusplus } // extern "C" #endif + #endif // _G_RESSERV_NVOC_H_ diff --git a/src/nvidia/generated/g_rg_line_callback_nvoc.h b/src/nvidia/generated/g_rg_line_callback_nvoc.h index 2161d83eb6..9166b6dac7 100644 --- a/src/nvidia/generated/g_rg_line_callback_nvoc.h +++ b/src/nvidia/generated/g_rg_line_callback_nvoc.h @@ -278,4 +278,5 @@ static inline void rglcbInvoke(struct RgLineCallback *pRgLineCallback, NvBool bI #ifdef __cplusplus } // extern "C" #endif + #endif // _G_RG_LINE_CALLBACK_NVOC_H_ diff --git a/src/nvidia/generated/g_rmconfig_private.h b/src/nvidia/generated/g_rmconfig_private.h index 11ce2aad99..df0c13401b 100644 --- a/src/nvidia/generated/g_rmconfig_private.h +++ b/src/nvidia/generated/g_rmconfig_private.h @@ -288,6 +288,15 @@ #define IsGH10XorBetter(pGpu) rmcfg_IsGH10XorBetter(pGpu) +// GH20X +#define IsGH202(pGpu) ((0) && (pGpu)) +#define IsGH202orBetter(pGpu) ((0) && (pGpu)) + +// Any GH20X chip? +#define IsGH20X(pGpu) (0 && (pGpu)) +#define IsGH20XorBetter(pGpu) (0 && (pGpu)) + + // T12X #define IsT001_FERMI_NOT_EXIST(pGpu) ((0) && (pGpu)) #define IsT001_FERMI_NOT_EXISTorBetter(pGpu) ((0) && (pGpu)) @@ -343,11 +352,11 @@ #define IsT234(pGpu) ((0) && (pGpu)) #define IsT234orBetter(pGpu) ((0) && (pGpu)) -#define IsT003_HOPPER_NOT_EXIST(pGpu) ((0) && (pGpu)) -#define IsT003_HOPPER_NOT_EXISTorBetter(pGpu) ((0) && (pGpu)) +#define IsT003_ADA_NOT_EXIST(pGpu) ((0) && (pGpu)) +#define IsT003_ADA_NOT_EXISTorBetter(pGpu) ((0) && (pGpu)) -#define IsT004_ADA_NOT_EXIST(pGpu) ((0) && (pGpu)) -#define IsT004_ADA_NOT_EXISTorBetter(pGpu) ((0) && (pGpu)) +#define IsT004_HOPPER_NOT_EXIST(pGpu) ((0) && (pGpu)) +#define IsT004_HOPPER_NOT_EXISTorBetter(pGpu) ((0) && (pGpu)) // Any T23XG chip? #define IsT23XG(pGpu) (0 && (pGpu)) @@ -528,6 +537,11 @@ #define IsHOPPER_CLASSIC_GPUSorBetter(pGpu) rmcfg_IsHOPPER_CLASSIC_GPUSorBetter(pGpu) +// Any TEGRA_DISP chip? +#define IsTEGRA_DISP(pGpu) (IsTEGRA_DISP_CLASSIC_GPUS(pGpu) || IsTEGRA_DISP_TEGRA_BIG_GPUS(pGpu) || IsTEGRA_DISP_TEGRA_NVDISP_GPUS(pGpu)) +#define IsTEGRA_DISPorBetter(pGpu) (IsTEGRA_DISP_CLASSIC_GPUSorBetter(pGpu) || IsTEGRA_DISP_TEGRA_BIG_GPUSorBetter(pGpu) || IsTEGRA_DISP_TEGRA_NVDISP_GPUSorBetter(pGpu)) + + // Any TEGRA_BIG_GPUS chip? #define IsTEGRA_BIG_GPUS(pGpu) (0 && (pGpu)) #define IsTEGRA_BIG_GPUSorBetter(pGpu) (0 && (pGpu)) @@ -588,6 +602,11 @@ #define IsVOLTA_TEGRA_BIG_GPUSorBetter(pGpu) (0 && (pGpu)) +// Any TEGRA_DISP_TEGRA_BIG_GPUS chip? +#define IsTEGRA_DISP_TEGRA_BIG_GPUS(pGpu) (0 && (pGpu)) +#define IsTEGRA_DISP_TEGRA_BIG_GPUSorBetter(pGpu) (0 && (pGpu)) + + // Any TURING_TEGRA_BIG_GPUS chip? #define IsTURING_TEGRA_BIG_GPUS(pGpu) (0 && (pGpu)) #define IsTURING_TEGRA_BIG_GPUSorBetter(pGpu) (0 && (pGpu)) @@ -613,16 +632,16 @@ #define IsAMPERE_TEGRA_BIG_GPUSorBetter(pGpu) (0 && (pGpu)) -// Any HOPPER_TEGRA_BIG_GPUS chip? -#define IsHOPPER_TEGRA_BIG_GPUS(pGpu) (0 && (pGpu)) -#define IsHOPPER_TEGRA_BIG_GPUSorBetter(pGpu) (0 && (pGpu)) - - // Any ADA_TEGRA_BIG_GPUS chip? #define IsADA_TEGRA_BIG_GPUS(pGpu) (0 && (pGpu)) #define IsADA_TEGRA_BIG_GPUSorBetter(pGpu) (0 && (pGpu)) +// Any HOPPER_TEGRA_BIG_GPUS chip? +#define IsHOPPER_TEGRA_BIG_GPUS(pGpu) (0 && (pGpu)) +#define IsHOPPER_TEGRA_BIG_GPUSorBetter(pGpu) (0 && (pGpu)) + + // Any TEGRA_NVDISP_GPUS chip? #define IsTEGRA_NVDISP_GPUS(pGpu) (0 && (pGpu)) #define IsTEGRA_NVDISP_GPUSorBetter(pGpu) (0 && (pGpu)) @@ -638,6 +657,11 @@ #define IsTEGRA_TEGRA_NVDISP_GPUSorBetter(pGpu) (0 && (pGpu)) +// Any TEGRA_DISP_TEGRA_NVDISP_GPUS chip? +#define IsTEGRA_DISP_TEGRA_NVDISP_GPUS(pGpu) (0 && (pGpu)) +#define IsTEGRA_DISP_TEGRA_NVDISP_GPUSorBetter(pGpu) (0 && (pGpu)) + + // Any SIMULATION_GPUS chip? #define IsSIMULATION_GPUS(pGpu) (0 && (pGpu)) #define IsSIMULATION_GPUSorBetter(pGpu) (0 && (pGpu)) diff --git a/src/nvidia/generated/g_rpc-message-header.h b/src/nvidia/generated/g_rpc-message-header.h index 4117e65201..db5bd9d620 100644 --- a/src/nvidia/generated/g_rpc-message-header.h +++ b/src/nvidia/generated/g_rpc-message-header.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2008-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2008-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/nvidia/generated/g_rpc-structures.h b/src/nvidia/generated/g_rpc-structures.h index ef18eabd6b..0c26e51a3e 100644 --- a/src/nvidia/generated/g_rpc-structures.h +++ b/src/nvidia/generated/g_rpc-structures.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2008-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2008-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -414,6 +414,7 @@ typedef struct rpc_timed_semaphore_release_v01_00 NvU32 releaseValue; NvU32 completionStatus; NvHandle hClient; + NvHandle hDevice; } rpc_timed_semaphore_release_v01_00; typedef rpc_timed_semaphore_release_v01_00 rpc_timed_semaphore_release_v; @@ -481,13 +482,6 @@ typedef struct rpc_nvlink_is_gpu_degraded_v17_00 typedef rpc_nvlink_is_gpu_degraded_v17_00 rpc_nvlink_is_gpu_degraded_v; -typedef struct rpc_gsp_send_user_shared_data_v17_00 -{ - NvU32 data; -} rpc_gsp_send_user_shared_data_v17_00; - -typedef rpc_gsp_send_user_shared_data_v17_00 rpc_gsp_send_user_shared_data_v; - typedef struct rpc_set_sysmem_dirty_page_tracking_buffer_v20_00 { NvU32 sysmemPfnBitmapRing; @@ -2289,6 +2283,13 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_timed_semaphore_release_v01_00[] = { .name = "hClient" #endif }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_timed_semaphore_release_v01_00, hDevice), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hDevice" + #endif + }, { .vtype = vt_end } @@ -2510,29 +2511,6 @@ static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_is_gpu_degraded_v17_00 = { }; #endif -#ifndef SKIP_PRINT_rpc_gsp_send_user_shared_data_v17_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gsp_send_user_shared_data_v17_00[] = { - { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_gsp_send_user_shared_data_v17_00, data), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "data" - #endif - }, - { - .vtype = vt_end - } -}; - -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_gsp_send_user_shared_data_v17_00 = { - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_gsp_send_user_shared_data", - #endif - .header_length = sizeof(rpc_gsp_send_user_shared_data_v17_00), - .fdesc = vmiopd_fdesc_t_rpc_gsp_send_user_shared_data_v17_00 -}; -#endif - #ifndef SKIP_PRINT_rpc_set_sysmem_dirty_page_tracking_buffer_v20_00 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_set_sysmem_dirty_page_tracking_buffer_v20_00[] = { { @@ -3104,13 +3082,6 @@ vmiopd_mdesc_t *rpcdebugNvlinkIsGpuDegraded_v17_00(void) } #endif -#ifndef SKIP_PRINT_rpc_gsp_send_user_shared_data_v17_00 -vmiopd_mdesc_t *rpcdebugGspSendUserSharedData_v17_00(void) -{ - return &vmiopd_mdesc_t_rpc_gsp_send_user_shared_data_v17_00; -} -#endif - #ifndef SKIP_PRINT_rpc_set_sysmem_dirty_page_tracking_buffer_v20_00 vmiopd_mdesc_t *rpcdebugSetSysmemDirtyPageTrackingBuffer_v20_00(void) { @@ -3250,8 +3221,6 @@ typedef union rpc_generic_union { rpc_nvlink_inband_received_data_4096_v nvlink_inband_received_data_4096_v; rpc_nvlink_is_gpu_degraded_v17_00 nvlink_is_gpu_degraded_v17_00; rpc_nvlink_is_gpu_degraded_v nvlink_is_gpu_degraded_v; - rpc_gsp_send_user_shared_data_v17_00 gsp_send_user_shared_data_v17_00; - rpc_gsp_send_user_shared_data_v gsp_send_user_shared_data_v; rpc_set_sysmem_dirty_page_tracking_buffer_v20_00 set_sysmem_dirty_page_tracking_buffer_v20_00; rpc_set_sysmem_dirty_page_tracking_buffer_v set_sysmem_dirty_page_tracking_buffer_v; rpc_extdev_intr_service_v17_00 extdev_intr_service_v17_00; diff --git a/src/nvidia/generated/g_rpc_private.h b/src/nvidia/generated/g_rpc_private.h index 0bedcec3de..9e48b38161 100644 --- a/src/nvidia/generated/g_rpc_private.h +++ b/src/nvidia/generated/g_rpc_private.h @@ -2440,6 +2440,91 @@ static void rpc_iGrp_ipVersions_Install_v23_05(IGRP_IP_VERSIONS_TABLE_INFO *pInf #endif // } +// No enabled chips use this variant provider +static void rpc_iGrp_ipVersions_Install_v24_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; + RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpc_iGrp_ipVersions_Install_v24_01(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; + RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpc_iGrp_ipVersions_Install_v24_05(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; + RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpc_iGrp_ipVersions_Install_v24_06(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; + RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpc_iGrp_ipVersions_Install_v24_0A(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; + RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcHal += 0; + + +#endif // +} + @@ -2967,6 +3052,21 @@ static NV_STATUS rpc_iGrp_ipVersions_getInfo(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v23_05[] = { { 0x23050000, 0xFFFFFFFF, }, // }; + static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v24_00[] = { + { 0x24000000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v24_01[] = { + { 0x24010000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v24_05[] = { + { 0x24050000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v24_06[] = { + { 0x24060000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v24_0A[] = { + { 0x240A0000, 0xFFFFFFFF, }, // + }; #define _RPC_HAL_IGRP_ENTRY_INIT(v) \ { RPC_IGRP_IP_VERSIONS_RANGES_##v, NV_ARRAY_ELEMENTS(RPC_IGRP_IP_VERSIONS_RANGES_##v), rpc_iGrp_ipVersions_Install_##v, } @@ -3108,6 +3208,11 @@ static NV_STATUS rpc_iGrp_ipVersions_getInfo(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) _RPC_HAL_IGRP_ENTRY_INIT(v23_03), // _RPC_HAL_IGRP_ENTRY_INIT(v23_04), // _RPC_HAL_IGRP_ENTRY_INIT(v23_05), // + _RPC_HAL_IGRP_ENTRY_INIT(v24_00), // + _RPC_HAL_IGRP_ENTRY_INIT(v24_01), // + _RPC_HAL_IGRP_ENTRY_INIT(v24_05), // + _RPC_HAL_IGRP_ENTRY_INIT(v24_06), // + _RPC_HAL_IGRP_ENTRY_INIT(v24_0A), // }; #undef _RPC_HAL_IGRP_ENTRY_INIT diff --git a/src/nvidia/generated/g_rs_client_nvoc.h b/src/nvidia/generated/g_rs_client_nvoc.h index 4eeda2d3c8..03743bd467 100644 --- a/src/nvidia/generated/g_rs_client_nvoc.h +++ b/src/nvidia/generated/g_rs_client_nvoc.h @@ -665,4 +665,5 @@ NvBool indexRefIterNext(RsIndexIter *pIt); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_RS_CLIENT_NVOC_H_ diff --git a/src/nvidia/generated/g_rs_resource_nvoc.h b/src/nvidia/generated/g_rs_resource_nvoc.h index ff1abe6e02..c6d1be018d 100644 --- a/src/nvidia/generated/g_rs_resource_nvoc.h +++ b/src/nvidia/generated/g_rs_resource_nvoc.h @@ -888,4 +888,5 @@ NvBool refPendingFree(RsResourceRef *pResourceRef, struct RsClient *pClient); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_RS_RESOURCE_NVOC_H_ diff --git a/src/nvidia/generated/g_rs_server_nvoc.h b/src/nvidia/generated/g_rs_server_nvoc.h index b5cb3cf3ae..d39ef2f343 100644 --- a/src/nvidia/generated/g_rs_server_nvoc.h +++ b/src/nvidia/generated/g_rs_server_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -661,10 +661,12 @@ extern NV_STATUS serverAllocApiCopyOut(RsServer *pServer, NV_STATUS status, API_ /** * Obtain a second client handle to lock if required for the allocation. - * @param[in] pParams Resource allocation parameters - * @param[in] phClient Client to lock, if any + * @param[in] externalClassId External class ID of resource + * @param[in] pAllocParams Class-specific allocation parameters + * + * @return Second client to lock, if any */ -extern NV_STATUS serverLookupSecondClient(RS_RES_ALLOC_PARAMS_INTERNAL *pParams, NvHandle *phClient); +extern NvHandle serverAllocLookupSecondClient(NvU32 externalClassId, void *pAllocParams); /** * Acquires a top-level lock. User-implemented. @@ -1213,4 +1215,5 @@ RsResourceRef *resservGetContextRefByType(NvU32 internalClassId, NvBool bSearchA #ifdef __cplusplus } // extern "C" #endif + #endif // _G_RS_SERVER_NVOC_H_ diff --git a/src/nvidia/generated/g_sdk-structures.h b/src/nvidia/generated/g_sdk-structures.h index b4883d0783..7bf71603af 100644 --- a/src/nvidia/generated/g_sdk-structures.h +++ b/src/nvidia/generated/g_sdk-structures.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2008-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2008-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/nvidia/generated/g_sec2_context_nvoc.h b/src/nvidia/generated/g_sec2_context_nvoc.h index 315d3fd463..61f74b0949 100644 --- a/src/nvidia/generated/g_sec2_context_nvoc.h +++ b/src/nvidia/generated/g_sec2_context_nvoc.h @@ -324,4 +324,5 @@ static inline void __nvoc_sec2ctxDestruct(struct Sec2Context *pSec2Context) { #ifdef __cplusplus } // extern "C" #endif + #endif // _G_SEC2_CONTEXT_NVOC_H_ diff --git a/src/nvidia/generated/g_sec2_utils_nvoc.h b/src/nvidia/generated/g_sec2_utils_nvoc.h index baf1466a84..be2b2f4d6b 100644 --- a/src/nvidia/generated/g_sec2_utils_nvoc.h +++ b/src/nvidia/generated/g_sec2_utils_nvoc.h @@ -160,4 +160,5 @@ static inline void sec2utilsServiceInterrupts(struct Sec2Utils *psec2utils) { #ifdef __cplusplus } // extern "C" #endif + #endif // _G_SEC2_UTILS_NVOC_H_ diff --git a/src/nvidia/generated/g_sem_surf_nvoc.h b/src/nvidia/generated/g_sem_surf_nvoc.h index f39f9edec7..2976801316 100644 --- a/src/nvidia/generated/g_sem_surf_nvoc.h +++ b/src/nvidia/generated/g_sem_surf_nvoc.h @@ -360,4 +360,5 @@ void semsurfDestruct_IMPL(struct SemaphoreSurface *pSemSurf); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_SEM_SURF_NVOC_H_ diff --git a/src/nvidia/generated/g_spdm_nvoc.h b/src/nvidia/generated/g_spdm_nvoc.h index b1bf26197a..6cf4cb3807 100644 --- a/src/nvidia/generated/g_spdm_nvoc.h +++ b/src/nvidia/generated/g_spdm_nvoc.h @@ -288,4 +288,5 @@ static inline NV_STATUS spdmGetCertificates_DISPATCH(struct OBJGPU *pGpu, struct #ifdef __cplusplus } // extern "C" #endif + #endif // _G_SPDM_NVOC_H_ diff --git a/src/nvidia/generated/g_standard_mem_nvoc.c b/src/nvidia/generated/g_standard_mem_nvoc.c index c97b29ce32..4deebbd565 100644 --- a/src/nvidia/generated/g_standard_mem_nvoc.c +++ b/src/nvidia/generated/g_standard_mem_nvoc.c @@ -113,6 +113,10 @@ static NV_STATUS __nvoc_thunk_Memory_stdmemGetMapAddrSpace(struct StandardMemory return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_StandardMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); } +static NvBool __nvoc_thunk_Memory_stdmemIsExportAllowed(struct StandardMemory *pMemory) { + return memIsExportAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_StandardMemory_Memory.offset)); +} + static NvU32 __nvoc_thunk_RsResource_stdmemGetRefCount(struct StandardMemory *pResource) { return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RsResource.offset)); } @@ -243,6 +247,8 @@ static void __nvoc_init_funcTable_StandardMemory_1(StandardMemory *pThis) { pThis->__stdmemGetMapAddrSpace__ = &__nvoc_thunk_Memory_stdmemGetMapAddrSpace; + pThis->__stdmemIsExportAllowed__ = &__nvoc_thunk_Memory_stdmemIsExportAllowed; + pThis->__stdmemGetRefCount__ = &__nvoc_thunk_RsResource_stdmemGetRefCount; pThis->__stdmemAddAdditionalDependants__ = &__nvoc_thunk_RsResource_stdmemAddAdditionalDependants; diff --git a/src/nvidia/generated/g_standard_mem_nvoc.h b/src/nvidia/generated/g_standard_mem_nvoc.h index 2984c5d46b..eae441bc61 100644 --- a/src/nvidia/generated/g_standard_mem_nvoc.h +++ b/src/nvidia/generated/g_standard_mem_nvoc.h @@ -74,6 +74,7 @@ struct StandardMemory { NvBool (*__stdmemShareCallback__)(struct StandardMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__stdmemMapTo__)(struct StandardMemory *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__stdmemGetMapAddrSpace__)(struct StandardMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvBool (*__stdmemIsExportAllowed__)(struct StandardMemory *); NvU32 (*__stdmemGetRefCount__)(struct StandardMemory *); void (*__stdmemAddAdditionalDependants__)(struct RsClient *, struct StandardMemory *, RsResourceRef *); NV_STATUS (*__stdmemControl_Prologue__)(struct StandardMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -129,6 +130,7 @@ NV_STATUS __nvoc_objCreate_StandardMemory(StandardMemory**, Dynamic*, NvU32, CAL #define stdmemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) stdmemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define stdmemMapTo(pResource, pParams) stdmemMapTo_DISPATCH(pResource, pParams) #define stdmemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) stdmemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define stdmemIsExportAllowed(pMemory) stdmemIsExportAllowed_DISPATCH(pMemory) #define stdmemGetRefCount(pResource) stdmemGetRefCount_DISPATCH(pResource) #define stdmemAddAdditionalDependants(pClient, pResource, pReference) stdmemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define stdmemControl_Prologue(pResource, pCallContext, pParams) stdmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) @@ -185,6 +187,10 @@ static inline NV_STATUS stdmemGetMapAddrSpace_DISPATCH(struct StandardMemory *pM return pMemory->__stdmemGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); } +static inline NvBool stdmemIsExportAllowed_DISPATCH(struct StandardMemory *pMemory) { + return pMemory->__stdmemIsExportAllowed__(pMemory); +} + static inline NvU32 stdmemGetRefCount_DISPATCH(struct StandardMemory *pResource) { return pResource->__stdmemGetRefCount__(pResource); } @@ -288,4 +294,5 @@ NvU64 stdmemQueryPageSize_IMPL(struct MemoryManager *pMemoryManager, NvHandle hC #ifdef __cplusplus } // extern "C" #endif + #endif // _G_STANDARD_MEM_NVOC_H_ diff --git a/src/nvidia/generated/g_subdevice_diag_nvoc.h b/src/nvidia/generated/g_subdevice_diag_nvoc.h index 2b11179a72..f9742b9c3a 100644 --- a/src/nvidia/generated/g_subdevice_diag_nvoc.h +++ b/src/nvidia/generated/g_subdevice_diag_nvoc.h @@ -391,4 +391,5 @@ NV_STATUS diagapiConstruct_IMPL(struct DiagApi *arg_pDiagApi, struct CALL_CONTEX #ifdef __cplusplus } // extern "C" #endif + #endif // _G_SUBDEVICE_DIAG_NVOC_H_ diff --git a/src/nvidia/generated/g_subdevice_nvoc.c b/src/nvidia/generated/g_subdevice_nvoc.c index 68b6d74968..fb21407c81 100644 --- a/src/nvidia/generated/g_subdevice_nvoc.c +++ b/src/nvidia/generated/g_subdevice_nvoc.c @@ -1033,12 +1033,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [53] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuGetPartitions_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + /*flags=*/ 0x850u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800175u, /*paramSize=*/ sizeof(NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS), @@ -1213,12 +1213,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [65] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuGetActivePartitionIds_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + /*flags=*/ 0x850u, /*accessRight=*/0x0u, /*methodId=*/ 0x2080018bu, /*paramSize=*/ sizeof(NV2080_CTRL_GPU_GET_ACTIVE_PARTITION_IDS_PARAMS), @@ -1513,12 +1513,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [85] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdEventSetNotification_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + /*flags=*/ 0x850u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800301u, /*paramSize=*/ sizeof(NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS), @@ -1633,12 +1633,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [93] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdTimerGetTime_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + /*flags=*/ 0x850u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800403u, /*paramSize=*/ sizeof(NV2080_CTRL_TIMER_GET_TIME_PARAMS), @@ -1663,12 +1663,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [95] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdTimerGetGpuCpuTimeCorrelationInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + /*flags=*/ 0x810u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800406u, /*paramSize=*/ sizeof(NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS), @@ -1903,6 +1903,21 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [111] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalFlcnSetVideoEventBufferFlags_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800a21u, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalFlcnSetVideoEventBufferFlags" +#endif + }, + { /* [112] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1917,7 +1932,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetGlobalSmOrder" #endif }, - { /* [112] */ + { /* [113] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1932,7 +1947,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMsencGetCaps" #endif }, - { /* [113] */ + { /* [114] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1947,7 +1962,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetFloorsweepingMasks" #endif }, - { /* [114] */ + { /* [115] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x80000u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1962,7 +1977,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCtxBufferPtes" #endif }, - { /* [115] */ + { /* [116] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1977,7 +1992,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetInfo" #endif }, - { /* [116] */ + { /* [117] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1992,7 +2007,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetZcullInfo" #endif }, - { /* [117] */ + { /* [118] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2007,7 +2022,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetRopInfo" #endif }, - { /* [118] */ + { /* [119] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2022,13 +2037,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetPpcMasks" #endif }, - { /* [119] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) + { /* [120] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2e00u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdKGrInternalStaticGetContextBuffersInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) - /*flags=*/ 0x1c2600u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2e00u) + /*flags=*/ 0x1c2e00u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800a32u, /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS), @@ -2037,7 +2052,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetContextBuffersInfo" #endif }, - { /* [120] */ + { /* [121] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2052,7 +2067,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetSmIssueRateModifier" #endif }, - { /* [121] */ + { /* [122] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2067,7 +2082,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGetChipInfo" #endif }, - { /* [122] */ + { /* [123] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2082,7 +2097,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetFecsRecordSize" #endif }, - { /* [123] */ + { /* [124] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2097,7 +2112,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetFecsTraceDefines" #endif }, - { /* [124] */ + { /* [125] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2112,7 +2127,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGetDeviceInfoTable" #endif }, - { /* [125] */ + { /* [126] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2127,7 +2142,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGetUserRegisterAccessMap" #endif }, - { /* [126] */ + { /* [127] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2140,21 +2155,6 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), #if NV_PRINTF_STRINGS_ALLOWED /*func=*/ "subdeviceCtrlCmdInternalGetConstructedFalconInfo" -#endif - }, - { /* [127] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) - /*pFunc=*/ (void (*)(void)) NULL, -#else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalKMIGmgrPromoteGpuInstanceMemRange_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) - /*flags=*/ 0x2600u, - /*accessRight=*/0x0u, - /*methodId=*/ 0x20800a44u, - /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS), - /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), -#if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "subdeviceCtrlCmdInternalKMIGmgrPromoteGpuInstanceMemRange" #endif }, { /* [128] */ @@ -3898,6 +3898,36 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [244] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalInitUserSharedData_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800afeu, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalInitUserSharedData" +#endif + }, + { /* [245] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalUserSharedDataSetDataPoll_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800affu, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalUserSharedDataSetDataPoll" +#endif + }, + { /* [246] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3912,7 +3942,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdSetGpfifo" #endif }, - { /* [245] */ + { /* [247] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3927,7 +3957,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoBindEngines" #endif }, - { /* [246] */ + { /* [248] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3942,7 +3972,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdSetOperationalProperties" #endif }, - { /* [247] */ + { /* [249] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3957,7 +3987,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGetPhysicalChannelCount" #endif }, - { /* [248] */ + { /* [250] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200010u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3972,7 +4002,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoGetInfo" #endif }, - { /* [249] */ + { /* [251] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3987,7 +4017,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoDisableChannels" #endif }, - { /* [250] */ + { /* [252] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4002,7 +4032,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoGetChannelMemInfo" #endif }, - { /* [251] */ + { /* [253] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4017,7 +4047,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoGetUserdLocation" #endif }, - { /* [252] */ + { /* [254] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4032,7 +4062,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoGetDeviceInfoTable" #endif }, - { /* [253] */ + { /* [255] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4047,7 +4077,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoClearFaultedBit" #endif }, - { /* [254] */ + { /* [256] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2310u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4062,7 +4092,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoRunlistSetSchedPolicy" #endif }, - { /* [255] */ + { /* [257] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4077,7 +4107,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoUpdateChannelInfo" #endif }, - { /* [256] */ + { /* [258] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4092,7 +4122,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoDisableUsermodeChannels" #endif }, - { /* [257] */ + { /* [259] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4107,7 +4137,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoSetupVfZombieSubctxPdb" #endif }, - { /* [258] */ + { /* [260] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4122,13 +4152,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoGetAllocatedChannels" #endif }, - { /* [259] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) + { /* [261] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdKGrGetInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) - /*flags=*/ 0x50u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + /*flags=*/ 0x850u, /*accessRight=*/0x0u, /*methodId=*/ 0x20801201u, /*paramSize=*/ sizeof(NV2080_CTRL_GR_GET_INFO_PARAMS), @@ -4137,7 +4167,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetInfo" #endif }, - { /* [260] */ + { /* [262] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4152,13 +4182,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrCtxswZcullMode" #endif }, - { /* [261] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) + { /* [263] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdKGrGetZcullInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) - /*flags=*/ 0x11u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0x20801206u, /*paramSize=*/ sizeof(NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS), @@ -4167,13 +4197,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetZcullInfo" #endif }, - { /* [262] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2010u) + { /* [264] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdKGrCtxswPmMode_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2010u) - /*flags=*/ 0x2010u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2850u) + /*flags=*/ 0x2850u, /*accessRight=*/0x0u, /*methodId=*/ 0x20801207u, /*paramSize=*/ sizeof(NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS), @@ -4182,7 +4212,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrCtxswPmMode" #endif }, - { /* [263] */ + { /* [265] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4197,7 +4227,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrCtxswZcullBind" #endif }, - { /* [264] */ + { /* [266] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4212,7 +4242,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrCtxswPmBind" #endif }, - { /* [265] */ + { /* [267] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4227,7 +4257,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrSetGpcTileMap" #endif }, - { /* [266] */ + { /* [268] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4242,13 +4272,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrCtxswSmpcMode" #endif }, - { /* [267] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [269] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdKGrGetSmToGpcTpcMappings_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + /*flags=*/ 0x850u, /*accessRight=*/0x0u, /*methodId=*/ 0x2080120fu, /*paramSize=*/ sizeof(NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS), @@ -4257,13 +4287,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetSmToGpcTpcMappings" #endif }, - { /* [268] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) + { /* [270] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2a10u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdKGrSetCtxswPreemptionMode_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) - /*flags=*/ 0x2210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2a10u) + /*flags=*/ 0x2a10u, /*accessRight=*/0x0u, /*methodId=*/ 0x20801210u, /*paramSize=*/ sizeof(NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS), @@ -4272,7 +4302,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrSetCtxswPreemptionMode" #endif }, - { /* [269] */ + { /* [271] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4287,7 +4317,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrCtxswPreemptionBind" #endif }, - { /* [270] */ + { /* [272] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4302,7 +4332,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrPcSamplingMode" #endif }, - { /* [271] */ + { /* [273] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4317,7 +4347,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetROPInfo" #endif }, - { /* [272] */ + { /* [274] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4332,7 +4362,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCtxswStats" #endif }, - { /* [273] */ + { /* [275] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4347,7 +4377,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCtxBufferSize" #endif }, - { /* [274] */ + { /* [276] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x80000u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4362,7 +4392,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCtxBufferInfo" #endif }, - { /* [275] */ + { /* [277] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4377,7 +4407,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetGlobalSmOrder" #endif }, - { /* [276] */ + { /* [278] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4392,7 +4422,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCurrentResidentChannel" #endif }, - { /* [277] */ + { /* [279] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4407,7 +4437,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetVatAlarmData" #endif }, - { /* [278] */ + { /* [280] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4422,7 +4452,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetAttributeBufferSize" #endif }, - { /* [279] */ + { /* [281] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4437,7 +4467,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGfxPoolQuerySize" #endif }, - { /* [280] */ + { /* [282] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4452,7 +4482,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGfxPoolInitialize" #endif }, - { /* [281] */ + { /* [283] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4467,7 +4497,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGfxPoolAddSlots" #endif }, - { /* [282] */ + { /* [284] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4482,7 +4512,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGfxPoolRemoveSlots" #endif }, - { /* [283] */ + { /* [285] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x812u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4497,13 +4527,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCapsV2" #endif }, - { /* [284] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) + { /* [286] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdKGrGetInfoV2_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) - /*flags=*/ 0x50u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + /*flags=*/ 0x850u, /*accessRight=*/0x0u, /*methodId=*/ 0x20801228u, /*paramSize=*/ sizeof(NV2080_CTRL_GR_GET_INFO_V2_PARAMS), @@ -4512,13 +4542,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetInfoV2" #endif }, - { /* [285] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) + { /* [287] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdKGrGetGpcMask_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) - /*flags=*/ 0x50u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + /*flags=*/ 0x850u, /*accessRight=*/0x0u, /*methodId=*/ 0x2080122au, /*paramSize=*/ sizeof(NV2080_CTRL_GR_GET_GPC_MASK_PARAMS), @@ -4527,13 +4557,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetGpcMask" #endif }, - { /* [286] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [288] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdKGrGetTpcMask_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + /*flags=*/ 0x850u, /*accessRight=*/0x0u, /*methodId=*/ 0x2080122bu, /*paramSize=*/ sizeof(NV2080_CTRL_GR_GET_TPC_MASK_PARAMS), @@ -4542,7 +4572,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetTpcMask" #endif }, - { /* [287] */ + { /* [289] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4557,7 +4587,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrSetTpcPartitionMode" #endif }, - { /* [288] */ + { /* [290] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4572,7 +4602,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetEngineContextProperties" #endif }, - { /* [289] */ + { /* [291] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4587,13 +4617,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetSmIssueRateModifier" #endif }, - { /* [290] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [292] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdKGrFecsBindEvtbufForUid_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + /*flags=*/ 0x850u, /*accessRight=*/0x0u, /*methodId=*/ 0x20801231u, /*paramSize=*/ sizeof(NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_PARAMS), @@ -4602,7 +4632,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrFecsBindEvtbufForUid" #endif }, - { /* [291] */ + { /* [293] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4617,7 +4647,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetPhysGpcMask" #endif }, - { /* [292] */ + { /* [294] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4632,7 +4662,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetPpcMask" #endif }, - { /* [293] */ + { /* [295] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4647,7 +4677,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetNumTpcsForGpc" #endif }, - { /* [294] */ + { /* [296] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4662,7 +4692,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCtxswModes" #endif }, - { /* [295] */ + { /* [297] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4677,7 +4707,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetGpcTileMap" #endif }, - { /* [296] */ + { /* [298] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4692,13 +4722,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetZcullMask" #endif }, - { /* [297] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8010u) + { /* [299] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdKGrFecsBindEvtbufForUidV2_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8010u) - /*flags=*/ 0x8010u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8850u) + /*flags=*/ 0x8850u, /*accessRight=*/0x0u, /*methodId=*/ 0x20801238u, /*paramSize=*/ sizeof(NV2080_CTRL_GR_FECS_BIND_EVTBUF_FOR_UID_V2_PARAMS), @@ -4707,7 +4737,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrFecsBindEvtbufForUidV2" #endif }, - { /* [298] */ + { /* [300] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4722,7 +4752,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetGfxGpcAndTpcInfo" #endif }, - { /* [299] */ + { /* [301] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4737,7 +4767,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetInfo" #endif }, - { /* [300] */ + { /* [302] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4752,7 +4782,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetInfoV2" #endif }, - { /* [301] */ + { /* [303] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4767,7 +4797,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetCarveoutAddressInfo" #endif }, - { /* [302] */ + { /* [304] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4782,13 +4812,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetCalibrationLockFailed" #endif }, - { /* [303] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [305] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdFbFlushGpuCache_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + /*flags=*/ 0x850u, /*accessRight=*/0x0u, /*methodId=*/ 0x2080130eu, /*paramSize=*/ sizeof(NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS), @@ -4797,7 +4827,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbFlushGpuCache" #endif }, - { /* [304] */ + { /* [306] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4812,7 +4842,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetGpuCacheAllocPolicy" #endif }, - { /* [305] */ + { /* [307] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4827,7 +4857,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetBar1Offset" #endif }, - { /* [306] */ + { /* [308] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4842,7 +4872,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetGpuCacheAllocPolicy" #endif }, - { /* [307] */ + { /* [309] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4857,13 +4887,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbIsKind" #endif }, - { /* [308] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [310] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa10u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdFbGetGpuCacheInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa10u) + /*flags=*/ 0xa10u, /*accessRight=*/0x0u, /*methodId=*/ 0x20801315u, /*paramSize=*/ sizeof(NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS), @@ -4872,7 +4902,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetGpuCacheInfo" #endif }, - { /* [309] */ + { /* [311] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4887,7 +4917,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetGpuCacheAllocPolicyV2" #endif }, - { /* [310] */ + { /* [312] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4902,13 +4932,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetGpuCacheAllocPolicyV2" #endif }, - { /* [311] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [313] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdFbGetFBRegionInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + /*flags=*/ 0x810u, /*accessRight=*/0x0u, /*methodId=*/ 0x20801320u, /*paramSize=*/ sizeof(NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS), @@ -4917,7 +4947,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetFBRegionInfo" #endif }, - { /* [312] */ + { /* [314] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4932,7 +4962,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetOfflinedPages" #endif }, - { /* [313] */ + { /* [315] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4947,7 +4977,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetLTCInfoForFBP" #endif }, - { /* [314] */ + { /* [316] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4962,7 +4992,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbCBCOp" #endif }, - { /* [315] */ + { /* [317] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4977,7 +5007,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetCtagsForCbcEviction" #endif }, - { /* [316] */ + { /* [318] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4992,7 +5022,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetupVprRegion" #endif }, - { /* [317] */ + { /* [319] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5007,7 +5037,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetCliManagedOfflinedPages" #endif }, - { /* [318] */ + { /* [320] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5022,7 +5052,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetCompBitCopyConstructInfo" #endif }, - { /* [319] */ + { /* [321] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5037,7 +5067,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetRrd" #endif }, - { /* [320] */ + { /* [322] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5052,7 +5082,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetReadLimit" #endif }, - { /* [321] */ + { /* [323] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5067,7 +5097,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetWriteLimit" #endif }, - { /* [322] */ + { /* [324] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5082,7 +5112,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbPatchPbrForMining" #endif }, - { /* [323] */ + { /* [325] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5097,7 +5127,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetMemAlignment" #endif }, - { /* [324] */ + { /* [326] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5112,7 +5142,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetRemappedRows" #endif }, - { /* [325] */ + { /* [327] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5127,7 +5157,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetFsInfo" #endif }, - { /* [326] */ + { /* [328] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5142,7 +5172,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetRowRemapperHistogram" #endif }, - { /* [327] */ + { /* [329] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5157,7 +5187,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetDynamicOfflinedPages" #endif }, - { /* [328] */ + { /* [330] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5172,7 +5202,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbUpdateNumaStatus" #endif }, - { /* [329] */ + { /* [331] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5187,13 +5217,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetNumaInfo" #endif }, - { /* [330] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + { /* [332] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGbGetSemaphoreSurfaceLayout_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4811u) + /*flags=*/ 0x4811u, /*accessRight=*/0x0u, /*methodId=*/ 0x20801352u, /*paramSize=*/ sizeof(NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS), @@ -5202,7 +5232,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGbGetSemaphoreSurfaceLayout" #endif }, - { /* [331] */ + { /* [333] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4813u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5217,7 +5247,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMcGetArchInfo" #endif }, - { /* [332] */ + { /* [334] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5232,7 +5262,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMcServiceInterrupts" #endif }, - { /* [333] */ + { /* [335] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5247,7 +5277,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMcGetManufacturer" #endif }, - { /* [334] */ + { /* [336] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5262,7 +5292,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMcQueryHostclkSlowdownStatus" #endif }, - { /* [335] */ + { /* [337] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5277,7 +5307,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMcSetHostclkSlowdownStatus" #endif }, - { /* [336] */ + { /* [338] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5292,7 +5322,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMcChangeReplayableFaultOwnership" #endif }, - { /* [337] */ + { /* [339] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5307,7 +5337,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPciInfo" #endif }, - { /* [338] */ + { /* [340] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5322,7 +5352,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetInfo" #endif }, - { /* [339] */ + { /* [341] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5337,7 +5367,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPciBarInfo" #endif }, - { /* [340] */ + { /* [342] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5352,7 +5382,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSetPcieLinkWidth" #endif }, - { /* [341] */ + { /* [343] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5367,7 +5397,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSetPcieSpeed" #endif }, - { /* [342] */ + { /* [344] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5382,7 +5412,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSetHwbcUpstreamPcieSpeed" #endif }, - { /* [343] */ + { /* [345] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5397,7 +5427,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetHwbcUpstreamPcieSpeed" #endif }, - { /* [344] */ + { /* [346] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5412,7 +5442,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusHWBCGetUpstreamBAR0" #endif }, - { /* [345] */ + { /* [347] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5427,7 +5457,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusServiceGpuMultifunctionState" #endif }, - { /* [346] */ + { /* [348] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5442,7 +5472,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPexCounters" #endif }, - { /* [347] */ + { /* [349] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5457,7 +5487,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusClearPexCounters" #endif }, - { /* [348] */ + { /* [350] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5472,7 +5502,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusFreezePexCounters" #endif }, - { /* [349] */ + { /* [351] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5487,7 +5517,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPexLaneCounters" #endif }, - { /* [350] */ + { /* [352] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5502,7 +5532,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPcieLtrLatency" #endif }, - { /* [351] */ + { /* [353] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5517,7 +5547,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSetPcieLtrLatency" #endif }, - { /* [352] */ + { /* [354] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5532,7 +5562,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPexUtilCounters" #endif }, - { /* [353] */ + { /* [355] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5547,7 +5577,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusClearPexUtilCounters" #endif }, - { /* [354] */ + { /* [356] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5562,7 +5592,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetBFD" #endif }, - { /* [355] */ + { /* [357] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5577,7 +5607,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetAspmDisableFlags" #endif }, - { /* [356] */ + { /* [358] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5592,7 +5622,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetInfoV2" #endif }, - { /* [357] */ + { /* [359] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5607,7 +5637,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusControlPublicAspmBits" #endif }, - { /* [358] */ + { /* [360] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5622,7 +5652,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetNvlinkPeerIdMask" #endif }, - { /* [359] */ + { /* [361] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5637,7 +5667,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSetEomParameters" #endif }, - { /* [360] */ + { /* [362] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5652,7 +5682,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetUphyDlnCfgSpace" #endif }, - { /* [361] */ + { /* [363] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5667,7 +5697,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetEomStatus" #endif }, - { /* [362] */ + { /* [364] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x6210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5682,7 +5712,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPcieReqAtomicsCaps" #endif }, - { /* [363] */ + { /* [365] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x6210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5697,7 +5727,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPcieSupportedGpuAtomics" #endif }, - { /* [364] */ + { /* [366] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5712,7 +5742,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetC2CInfo" #endif }, - { /* [365] */ + { /* [367] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10000u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5727,22 +5757,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSysmemAccess" #endif }, - { /* [366] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*pFunc=*/ (void (*)(void)) NULL, -#else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBusGetC2CErrorInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, - /*accessRight=*/0x0u, - /*methodId=*/ 0x2080182du, - /*paramSize=*/ sizeof(NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS), - /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), -#if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "subdeviceCtrlCmdBusGetC2CErrorInfo" -#endif - }, - { /* [367] */ + { /* [368] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5757,7 +5772,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSetP2pMapping" #endif }, - { /* [368] */ + { /* [369] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5772,7 +5787,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusUnsetP2pMapping" #endif }, - { /* [369] */ + { /* [370] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5787,7 +5802,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKPerfBoost" #endif }, - { /* [370] */ + { /* [371] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5802,7 +5817,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdPerfSetPowerstate" #endif }, - { /* [371] */ + { /* [372] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5817,7 +5832,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdPerfRatedTdpGetControl" #endif }, - { /* [372] */ + { /* [373] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5832,7 +5847,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdPerfRatedTdpSetControl" #endif }, - { /* [373] */ + { /* [374] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5847,7 +5862,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdPerfSetAuxPowerState" #endif }, - { /* [374] */ + { /* [375] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5862,7 +5877,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdPerfReservePerfmonHw" #endif }, - { /* [375] */ + { /* [376] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5877,7 +5892,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamplesV2" #endif }, - { /* [376] */ + { /* [377] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5892,7 +5907,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcReadVirtualMem" #endif }, - { /* [377] */ + { /* [378] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5907,7 +5922,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcGetErrorCount" #endif }, - { /* [378] */ + { /* [379] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5922,7 +5937,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcSetCleanErrorHistory" #endif }, - { /* [379] */ + { /* [380] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5937,7 +5952,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcGetWatchdogInfo" #endif }, - { /* [380] */ + { /* [381] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5952,7 +5967,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcDisableWatchdog" #endif }, - { /* [381] */ + { /* [382] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5967,7 +5982,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcEnableWatchdog" #endif }, - { /* [382] */ + { /* [383] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5982,7 +5997,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcReleaseWatchdogRequests" #endif }, - { /* [383] */ + { /* [384] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5997,7 +6012,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdSetRcRecovery" #endif }, - { /* [384] */ + { /* [385] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6012,7 +6027,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGetRcRecovery" #endif }, - { /* [385] */ + { /* [386] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6027,7 +6042,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcSoftDisableWatchdog" #endif }, - { /* [386] */ + { /* [387] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6042,7 +6057,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdSetRcInfo" #endif }, - { /* [387] */ + { /* [388] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6057,7 +6072,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGetRcInfo" #endif }, - { /* [388] */ + { /* [389] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6072,7 +6087,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcGetErrorV2" #endif }, - { /* [389] */ + { /* [390] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6087,7 +6102,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGpioProgramDirection" #endif }, - { /* [390] */ + { /* [391] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6102,7 +6117,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGpioProgramOutput" #endif }, - { /* [391] */ + { /* [392] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6117,7 +6132,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGpioReadInput" #endif }, - { /* [392] */ + { /* [393] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6132,7 +6147,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGpioActivateHwFunction" #endif }, - { /* [393] */ + { /* [394] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6147,7 +6162,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvdGetDumpSize" #endif }, - { /* [394] */ + { /* [395] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6162,7 +6177,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvdGetDump" #endif }, - { /* [395] */ + { /* [396] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6177,7 +6192,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvdGetNocatJournalRpt" #endif }, - { /* [396] */ + { /* [397] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6192,7 +6207,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvdSetNocatJournalData" #endif }, - { /* [397] */ + { /* [398] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6207,7 +6222,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDmaInvalidateTLB" #endif }, - { /* [398] */ + { /* [399] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6222,7 +6237,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDmaGetInfo" #endif }, - { /* [399] */ + { /* [400] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6237,7 +6252,52 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdPmgrGetModuleInfo" #endif }, - { /* [400] */ + { /* [401] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuProcessPostGc6ExitTasks_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x2080270cu, + /*paramSize=*/ 0, + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdGpuProcessPostGc6ExitTasks" +#endif + }, + { /* [402] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGc6Entry_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2u) + /*flags=*/ 0x2u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x2080270du, + /*paramSize=*/ sizeof(NV2080_CTRL_GC6_ENTRY_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdGc6Entry" +#endif + }, + { /* [403] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGc6Exit_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2u) + /*flags=*/ 0x2u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x2080270eu, + /*paramSize=*/ sizeof(NV2080_CTRL_GC6_EXIT_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdGc6Exit" +#endif + }, + { /* [404] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6252,7 +6312,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdLpwrDifrCtrl" #endif }, - { /* [401] */ + { /* [405] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6267,7 +6327,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdLpwrDifrPrefetchResponse" #endif }, - { /* [402] */ + { /* [406] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6282,13 +6342,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetCaps" #endif }, - { /* [403] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2211u) + { /* [407] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2a11u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdCeGetCePceMask_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2211u) - /*flags=*/ 0x2211u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2a11u) + /*flags=*/ 0x2a11u, /*accessRight=*/0x0u, /*methodId=*/ 0x20802a02u, /*paramSize=*/ sizeof(NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS), @@ -6297,7 +6357,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetCePceMask" #endif }, - { /* [404] */ + { /* [408] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6312,7 +6372,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetCapsV2" #endif }, - { /* [405] */ + { /* [409] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6327,7 +6387,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeUpdatePceLceMappings" #endif }, - { /* [406] */ + { /* [410] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6342,7 +6402,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeUpdateClassDB" #endif }, - { /* [407] */ + { /* [411] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100e40u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6357,7 +6417,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetPhysicalCaps" #endif }, - { /* [408] */ + { /* [412] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c0200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6372,7 +6432,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetFaultMethodBufferSize" #endif }, - { /* [409] */ + { /* [413] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6387,7 +6447,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetHubPceMask" #endif }, - { /* [410] */ + { /* [414] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6402,7 +6462,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetAllCaps" #endif }, - { /* [411] */ + { /* [415] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe40u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6417,7 +6477,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetAllPhysicalCaps" #endif }, - { /* [412] */ + { /* [416] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6432,7 +6492,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetNvlinkCaps" #endif }, - { /* [413] */ + { /* [417] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6447,7 +6507,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetNvlinkStatus" #endif }, - { /* [414] */ + { /* [418] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6462,7 +6522,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetNvlinkErrInfo" #endif }, - { /* [415] */ + { /* [419] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6477,7 +6537,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGetNvlinkCounters" #endif }, - { /* [416] */ + { /* [420] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6492,7 +6552,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdClearNvlinkCounters" #endif }, - { /* [417] */ + { /* [421] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6507,7 +6567,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetLinkFatalErrorCounts" #endif }, - { /* [418] */ + { /* [422] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6522,7 +6582,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSetupEom" #endif }, - { /* [419] */ + { /* [423] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6537,7 +6597,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetPowerState" #endif }, - { /* [420] */ + { /* [424] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6552,7 +6612,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinGetLinkFomValues" #endif }, - { /* [421] */ + { /* [425] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6567,7 +6627,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetNvlinkEccErrors" #endif }, - { /* [422] */ + { /* [426] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6582,7 +6642,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkReadTpCounters" #endif }, - { /* [423] */ + { /* [427] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6597,7 +6657,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkEnableNvlinkPeer" #endif }, - { /* [424] */ + { /* [428] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6612,7 +6672,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetLpCounters" #endif }, - { /* [425] */ + { /* [429] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6627,7 +6687,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkCoreCallback" #endif }, - { /* [426] */ + { /* [430] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6642,7 +6702,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetAliEnabled" #endif }, - { /* [427] */ + { /* [431] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6657,7 +6717,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkUpdateRemoteLocalSid" #endif }, - { /* [428] */ + { /* [432] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6672,7 +6732,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkUpdateHshubMux" #endif }, - { /* [429] */ + { /* [433] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6687,7 +6747,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkPreSetupNvlinkPeer" #endif }, - { /* [430] */ + { /* [434] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6702,7 +6762,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkPostSetupNvlinkPeer" #endif }, - { /* [431] */ + { /* [435] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6717,7 +6777,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkRemoveNvlinkMapping" #endif }, - { /* [432] */ + { /* [436] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6732,7 +6792,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSaveRestoreHshubState" #endif }, - { /* [433] */ + { /* [437] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6747,7 +6807,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkProgramBufferready" #endif }, - { /* [434] */ + { /* [438] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6762,7 +6822,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkUpdateCurrentConfig" #endif }, - { /* [435] */ + { /* [439] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6777,7 +6837,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSetLoopbackMode" #endif }, - { /* [436] */ + { /* [440] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6792,7 +6852,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkUpdatePeerLinkMask" #endif }, - { /* [437] */ + { /* [441] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6807,7 +6867,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkUpdateLinkConnection" #endif }, - { /* [438] */ + { /* [442] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6822,7 +6882,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkEnableLinksPostTopology" #endif }, - { /* [439] */ + { /* [443] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6837,7 +6897,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkPreLinkTrainAli" #endif }, - { /* [440] */ + { /* [444] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6852,7 +6912,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetRefreshCounters" #endif }, - { /* [441] */ + { /* [445] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6867,7 +6927,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkClearRefreshCounters" #endif }, - { /* [442] */ + { /* [446] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6882,7 +6942,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetLinkMaskPostRxDet" #endif }, - { /* [443] */ + { /* [447] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6897,7 +6957,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkLinkTrainAli" #endif }, - { /* [444] */ + { /* [448] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6912,7 +6972,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetNvlinkDeviceInfo" #endif }, - { /* [445] */ + { /* [449] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6927,7 +6987,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetIoctrlDeviceInfo" #endif }, - { /* [446] */ + { /* [450] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6942,7 +7002,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkProgramLinkSpeed" #endif }, - { /* [447] */ + { /* [451] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6957,7 +7017,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkAreLinksTrained" #endif }, - { /* [448] */ + { /* [452] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6972,7 +7032,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkResetLinks" #endif }, - { /* [449] */ + { /* [453] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6987,7 +7047,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkDisableDlInterrupts" #endif }, - { /* [450] */ + { /* [454] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7002,7 +7062,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetLinkAndClockInfo" #endif }, - { /* [451] */ + { /* [455] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7017,7 +7077,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSetupNvlinkSysmem" #endif }, - { /* [452] */ + { /* [456] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7032,7 +7092,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkProcessForcedConfigs" #endif }, - { /* [453] */ + { /* [457] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7047,7 +7107,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSyncLaneShutdownProps" #endif }, - { /* [454] */ + { /* [458] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7062,7 +7122,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkEnableSysmemNvlinkAts" #endif }, - { /* [455] */ + { /* [459] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7077,7 +7137,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkHshubGetSysmemNvlinkMask" #endif }, - { /* [456] */ + { /* [460] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7092,7 +7152,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetSetNvswitchFlaAddr" #endif }, - { /* [457] */ + { /* [461] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7107,7 +7167,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSyncLinkMasksAndVbiosInfo" #endif }, - { /* [458] */ + { /* [462] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7122,7 +7182,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkEnableLinks" #endif }, - { /* [459] */ + { /* [463] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7137,7 +7197,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkProcessInitDisabledLinks" #endif }, - { /* [460] */ + { /* [464] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7152,7 +7212,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkEomControl" #endif }, - { /* [461] */ + { /* [465] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7167,7 +7227,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSetL1Threshold" #endif }, - { /* [462] */ + { /* [466] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7182,7 +7242,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetL1Threshold" #endif }, - { /* [463] */ + { /* [467] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1240u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7197,7 +7257,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkInbandSendData" #endif }, - { /* [464] */ + { /* [468] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7212,7 +7272,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkDirectConnectCheck" #endif }, - { /* [465] */ + { /* [469] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7227,7 +7287,37 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkPostFaultUp" #endif }, - { /* [466] */ + { /* [470] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdNvlinkGetPortEvents_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20803044u, + /*paramSize=*/ sizeof(NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdNvlinkGetPortEvents" +#endif + }, + { /* [471] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdNvlinkCycleLink_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20803045u, + /*paramSize=*/ sizeof(NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdNvlinkCycleLink" +#endif + }, + { /* [472] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7235,14 +7325,14 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*flags=*/ 0x200u, /*accessRight=*/0x0u, - /*methodId=*/ 0x20803044u, + /*methodId=*/ 0x20803046u, /*paramSize=*/ sizeof(NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS), /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), #if NV_PRINTF_STRINGS_ALLOWED /*func=*/ "subdeviceCtrlCmdIsNvlinkReducedConfig" #endif }, - { /* [467] */ + { /* [473] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7257,7 +7347,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnGetDmemUsage" #endif }, - { /* [468] */ + { /* [474] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7272,7 +7362,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnGetEngineArch" #endif }, - { /* [469] */ + { /* [475] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7287,7 +7377,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnUstreamerQueueInfo" #endif }, - { /* [470] */ + { /* [476] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7302,7 +7392,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnUstreamerControlGet" #endif }, - { /* [471] */ + { /* [477] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7317,7 +7407,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnUstreamerControlSet" #endif }, - { /* [472] */ + { /* [478] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7332,7 +7422,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnGetCtxBufferInfo" #endif }, - { /* [473] */ + { /* [479] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7347,7 +7437,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnGetCtxBufferSize" #endif }, - { /* [474] */ + { /* [480] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7362,13 +7452,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdEccGetClientExposedCounters" #endif }, - { /* [475] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + { /* [481] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdFlaRange_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) - /*flags=*/ 0x810u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, /*accessRight=*/0x0u, /*methodId=*/ 0x20803501u, /*paramSize=*/ sizeof(NV2080_CTRL_FLA_RANGE_PARAMS), @@ -7377,7 +7467,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlaRange" #endif }, - { /* [476] */ + { /* [482] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7392,7 +7482,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlaSetupInstanceMemBlock" #endif }, - { /* [477] */ + { /* [483] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100004u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7407,7 +7497,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlaGetRange" #endif }, - { /* [478] */ + { /* [484] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7422,13 +7512,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlaGetFabricMemStats" #endif }, - { /* [479] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4211u) + { /* [485] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4a11u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGspGetFeatures_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4211u) - /*flags=*/ 0x4211u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4a11u) + /*flags=*/ 0x4a11u, /*accessRight=*/0x0u, /*methodId=*/ 0x20803601u, /*paramSize=*/ sizeof(NV2080_CTRL_GSP_GET_FEATURES_PARAMS), @@ -7437,7 +7527,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGspGetFeatures" #endif }, - { /* [480] */ + { /* [486] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7452,7 +7542,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGspGetRmHeapStats" #endif }, - { /* [481] */ + { /* [487] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7467,7 +7557,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGrmgrGetGrFsInfo" #endif }, - { /* [482] */ + { /* [488] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x3u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7482,7 +7572,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixGc6BlockerRefCnt" #endif }, - { /* [483] */ + { /* [489] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7497,7 +7587,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixAllowDisallowGcoff" #endif }, - { /* [484] */ + { /* [490] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7512,7 +7602,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixAudioDynamicPower" #endif }, - { /* [485] */ + { /* [491] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7527,7 +7617,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixVidmemPersistenceStatus" #endif }, - { /* [486] */ + { /* [492] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7542,7 +7632,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixUpdateTgpStatus" #endif }, - { /* [487] */ + { /* [493] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7557,7 +7647,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask" #endif }, - { /* [488] */ + { /* [494] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7572,7 +7662,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalShutdownGspVgpuPluginTask" #endif }, - { /* [489] */ + { /* [495] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7587,7 +7677,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalPgpuAddVgpuType" #endif }, - { /* [490] */ + { /* [496] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7602,7 +7692,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalEnumerateVgpuPerPgpu" #endif }, - { /* [491] */ + { /* [497] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7617,7 +7707,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalClearGuestVmInfo" #endif }, - { /* [492] */ + { /* [498] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7632,7 +7722,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalGetVgpuFbUsage" #endif }, - { /* [493] */ + { /* [499] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7647,7 +7737,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalSetVgpuEncoderCapacity" #endif }, - { /* [494] */ + { /* [500] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7662,7 +7752,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalCleanupGspVgpuPluginResources" #endif }, - { /* [495] */ + { /* [501] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7677,7 +7767,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalGetPgpuFsEncoding" #endif }, - { /* [496] */ + { /* [502] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7692,7 +7782,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalGetPgpuMigrationSupport" #endif }, - { /* [497] */ + { /* [503] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7707,7 +7797,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalSetVgpuMgrConfig" #endif }, - { /* [498] */ + { /* [504] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7722,7 +7812,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGetAvailableHshubMask" #endif }, - { /* [499] */ + { /* [505] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlSetEcThrottleMode_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) + /*flags=*/ 0xa50u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20804102u, + /*paramSize=*/ sizeof(NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlSetEcThrottleMode" +#endif + }, + { /* [506] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7737,19 +7842,19 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamples" #endif }, - { /* [500] */ + { /* [507] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalGc6EntryPrerequisite_IMPL, + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalGcxEntryPrerequisite_IMPL, #endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*flags=*/ 0x600u, /*accessRight=*/0x0u, /*methodId=*/ 0x2080a7d7u, - /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS), + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS), /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), #if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "subdeviceCtrlCmdInternalGc6EntryPrerequisite" + /*func=*/ "subdeviceCtrlCmdInternalGcxEntryPrerequisite" #endif }, @@ -7757,7 +7862,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic const struct NVOC_EXPORT_INFO __nvoc_export_info_Subdevice = { - /*numEntries=*/ 501, + /*numEntries=*/ 508, /*pExportEntries=*/ __nvoc_exported_method_def_Subdevice }; @@ -7981,10 +8086,6 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdBusGetC2CInfo__ = &subdeviceCtrlCmdBusGetC2CInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - pThis->__subdeviceCtrlCmdBusGetC2CErrorInfo__ = &subdeviceCtrlCmdBusGetC2CErrorInfo_IMPL; -#endif - #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10000u) pThis->__subdeviceCtrlCmdBusSysmemAccess__ = &subdeviceCtrlCmdBusSysmemAccess_IMPL; #endif @@ -8217,6 +8318,14 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdIsNvlinkReducedConfig__ = &subdeviceCtrlCmdIsNvlinkReducedConfig_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + pThis->__subdeviceCtrlCmdNvlinkGetPortEvents__ = &subdeviceCtrlCmdNvlinkGetPortEvents_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + pThis->__subdeviceCtrlCmdNvlinkCycleLink__ = &subdeviceCtrlCmdNvlinkCycleLink_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) pThis->__subdeviceCtrlCmdI2cReadBuffer__ = &subdeviceCtrlCmdI2cReadBuffer_IMPL; #endif @@ -8261,7 +8370,7 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdKPerfBoost__ = &subdeviceCtrlCmdKPerfBoost_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) pThis->__subdeviceCtrlCmdFbGetFBRegionInfo__ = &subdeviceCtrlCmdFbGetFBRegionInfo_IMPL; #endif @@ -8285,7 +8394,7 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdInternalMemmgrGetVgpuHostRmReservedFb__ = &subdeviceCtrlCmdInternalMemmgrGetVgpuHostRmReservedFb_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4811u) pThis->__subdeviceCtrlCmdGbGetSemaphoreSurfaceLayout__ = &subdeviceCtrlCmdGbGetSemaphoreSurfaceLayout_IMPL; #endif @@ -8308,7 +8417,7 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdFbGetCalibrationLockFailed__ = &subdeviceCtrlCmdFbGetCalibrationLockFailed_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) pThis->__subdeviceCtrlCmdFbFlushGpuCache__ = &subdeviceCtrlCmdFbFlushGpuCache_IMPL; #endif @@ -8328,7 +8437,7 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdFbGetGpuCacheAllocPolicyV2__ = &subdeviceCtrlCmdFbGetGpuCacheAllocPolicyV2_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa10u) pThis->__subdeviceCtrlCmdFbGetGpuCacheInfo__ = &subdeviceCtrlCmdFbGetGpuCacheInfo_IMPL; #endif @@ -8508,11 +8617,11 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdInternalFifoGetNumSecureChannels__ = &subdeviceCtrlCmdInternalFifoGetNumSecureChannels_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) pThis->__subdeviceCtrlCmdKGrGetInfo__ = &subdeviceCtrlCmdKGrGetInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) pThis->__subdeviceCtrlCmdKGrGetInfoV2__ = &subdeviceCtrlCmdKGrGetInfoV2_IMPL; #endif @@ -8532,11 +8641,11 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdKGrCtxswZcullBind__ = &subdeviceCtrlCmdKGrCtxswZcullBind_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__subdeviceCtrlCmdKGrGetZcullInfo__ = &subdeviceCtrlCmdKGrGetZcullInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2010u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2850u) pThis->__subdeviceCtrlCmdKGrCtxswPmMode__ = &subdeviceCtrlCmdKGrCtxswPmMode_IMPL; #endif @@ -8556,7 +8665,7 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdKGrPcSamplingMode__ = &subdeviceCtrlCmdKGrPcSamplingMode_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) pThis->__subdeviceCtrlCmdKGrGetSmToGpcTpcMappings__ = &subdeviceCtrlCmdKGrGetSmToGpcTpcMappings_IMPL; #endif @@ -8564,7 +8673,7 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdKGrGetGlobalSmOrder__ = &subdeviceCtrlCmdKGrGetGlobalSmOrder_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2a10u) pThis->__subdeviceCtrlCmdKGrSetCtxswPreemptionMode__ = &subdeviceCtrlCmdKGrSetCtxswPreemptionMode_IMPL; #endif @@ -8632,11 +8741,11 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdKGrGetSmIssueRateModifier__ = &subdeviceCtrlCmdKGrGetSmIssueRateModifier_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) pThis->__subdeviceCtrlCmdKGrFecsBindEvtbufForUid__ = &subdeviceCtrlCmdKGrFecsBindEvtbufForUid_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8010u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8850u) pThis->__subdeviceCtrlCmdKGrFecsBindEvtbufForUidV2__ = &subdeviceCtrlCmdKGrFecsBindEvtbufForUidV2_IMPL; #endif @@ -8644,11 +8753,11 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdKGrGetPhysGpcMask__ = &subdeviceCtrlCmdKGrGetPhysGpcMask_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) pThis->__subdeviceCtrlCmdKGrGetGpcMask__ = &subdeviceCtrlCmdKGrGetGpcMask_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) pThis->__subdeviceCtrlCmdKGrGetTpcMask__ = &subdeviceCtrlCmdKGrGetTpcMask_IMPL; #endif @@ -8700,7 +8809,7 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdKGrInternalStaticGetRopInfo__ = &subdeviceCtrlCmdKGrInternalStaticGetRopInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2e00u) pThis->__subdeviceCtrlCmdKGrInternalStaticGetContextBuffersInfo__ = &subdeviceCtrlCmdKGrInternalStaticGetContextBuffersInfo_IMPL; #endif @@ -8851,10 +8960,6 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) pThis->__subdeviceCtrlCmdGpuGetInforomObjectVersion__ = &subdeviceCtrlCmdGpuGetInforomObjectVersion_IMPL; #endif - -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - pThis->__subdeviceCtrlCmdGpuQueryInforomEccSupport__ = &subdeviceCtrlCmdGpuQueryInforomEccSupport_IMPL; -#endif } static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner) { @@ -8865,6 +8970,10 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * PORT_UNREFERENCED_VARIABLE(rmVariantHal); PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + pThis->__subdeviceCtrlCmdGpuQueryInforomEccSupport__ = &subdeviceCtrlCmdGpuQueryInforomEccSupport_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) pThis->__subdeviceCtrlCmdGpuQueryEccStatus__ = &subdeviceCtrlCmdGpuQueryEccStatus_IMPL; #endif @@ -9033,7 +9142,7 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdEventSetTriggerFifo__ = &subdeviceCtrlCmdEventSetTriggerFifo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) pThis->__subdeviceCtrlCmdEventSetNotification__ = &subdeviceCtrlCmdEventSetNotification_IMPL; #endif @@ -9057,7 +9166,7 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdTimerSchedule__ = &subdeviceCtrlCmdTimerSchedule_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) pThis->__subdeviceCtrlCmdTimerGetTime__ = &subdeviceCtrlCmdTimerGetTime_IMPL; #endif @@ -9065,7 +9174,7 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdTimerGetRegisterOffset__ = &subdeviceCtrlCmdTimerGetRegisterOffset_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) pThis->__subdeviceCtrlCmdTimerGetGpuCpuTimeCorrelationInfo__ = &subdeviceCtrlCmdTimerGetGpuCpuTimeCorrelationInfo_IMPL; #endif @@ -9149,6 +9258,18 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdPmgrGetModuleInfo__ = &subdeviceCtrlCmdPmgrGetModuleInfo_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + pThis->__subdeviceCtrlCmdGpuProcessPostGc6ExitTasks__ = &subdeviceCtrlCmdGpuProcessPostGc6ExitTasks_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2u) + pThis->__subdeviceCtrlCmdGc6Entry__ = &subdeviceCtrlCmdGc6Entry_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2u) + pThis->__subdeviceCtrlCmdGc6Exit__ = &subdeviceCtrlCmdGc6Exit_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) pThis->__subdeviceCtrlCmdLpwrDifrPrefetchResponse__ = &subdeviceCtrlCmdLpwrDifrPrefetchResponse_IMPL; #endif @@ -9161,7 +9282,7 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdCeGetCaps__ = &subdeviceCtrlCmdCeGetCaps_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2211u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2a11u) pThis->__subdeviceCtrlCmdCeGetCePceMask__ = &subdeviceCtrlCmdCeGetCePceMask_IMPL; #endif @@ -9205,6 +9326,10 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdFlcnGetCtxBufferSize__ = &subdeviceCtrlCmdFlcnGetCtxBufferSize_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalFlcnSetVideoEventBufferFlags__ = &subdeviceCtrlCmdInternalFlcnSetVideoEventBufferFlags_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) pThis->__subdeviceCtrlCmdEccGetClientExposedCounters__ = &subdeviceCtrlCmdEccGetClientExposedCounters_IMPL; #endif @@ -9221,7 +9346,7 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdGpuResetEccErrorStatus__ = &subdeviceCtrlCmdGpuResetEccErrorStatus_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__subdeviceCtrlCmdFlaRange__ = &subdeviceCtrlCmdFlaRange_IMPL; #endif @@ -9237,7 +9362,7 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdFlaGetFabricMemStats__ = &subdeviceCtrlCmdFlaGetFabricMemStats_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4211u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4a11u) pThis->__subdeviceCtrlCmdGspGetFeatures__ = &subdeviceCtrlCmdGspGetFeatures_IMPL; #endif @@ -9245,7 +9370,7 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdGspGetRmHeapStats__ = &subdeviceCtrlCmdGspGetRmHeapStats_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) pThis->__subdeviceCtrlCmdGpuGetActivePartitionIds__ = &subdeviceCtrlCmdGpuGetActivePartitionIds_IMPL; #endif @@ -9269,7 +9394,7 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdGpuSetPartitions__ = &subdeviceCtrlCmdGpuSetPartitions_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) pThis->__subdeviceCtrlCmdGpuGetPartitions__ = &subdeviceCtrlCmdGpuGetPartitions_IMPL; #endif @@ -9301,10 +9426,6 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdInternalKMIGmgrImportGPUInstance__ = &subdeviceCtrlCmdInternalKMIGmgrImportGPUInstance_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) - pThis->__subdeviceCtrlCmdInternalKMIGmgrPromoteGpuInstanceMemRange__ = &subdeviceCtrlCmdInternalKMIGmgrPromoteGpuInstanceMemRange_IMPL; -#endif - #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x3u) pThis->__subdeviceCtrlCmdOsUnixGc6BlockerRefCnt__ = &subdeviceCtrlCmdOsUnixGc6BlockerRefCnt_IMPL; #endif @@ -9558,7 +9679,7 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - pThis->__subdeviceCtrlCmdInternalGc6EntryPrerequisite__ = &subdeviceCtrlCmdInternalGc6EntryPrerequisite_IMPL; + pThis->__subdeviceCtrlCmdInternalGcxEntryPrerequisite__ = &subdeviceCtrlCmdInternalGcxEntryPrerequisite_IMPL; #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) @@ -9761,6 +9882,14 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdInternalConfComputeDeriveLceKeys__ = &subdeviceCtrlCmdInternalConfComputeDeriveLceKeys_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalInitUserSharedData__ = &subdeviceCtrlCmdInternalInitUserSharedData_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdInternalUserSharedDataSetDataPoll__ = &subdeviceCtrlCmdInternalUserSharedDataSetDataPoll_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) pThis->__subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask__ = &subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask_IMPL; #endif @@ -9809,6 +9938,10 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdGetAvailableHshubMask__ = &subdeviceCtrlCmdGetAvailableHshubMask_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) + pThis->__subdeviceCtrlSetEcThrottleMode__ = &subdeviceCtrlSetEcThrottleMode_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) pThis->__subdeviceCtrlCmdCcuMap__ = &subdeviceCtrlCmdCcuMap_IMPL; #endif @@ -9858,6 +9991,15 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceControlLookup__ = &__nvoc_thunk_RsResource_subdeviceControlLookup; pThis->__subdeviceGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_subdeviceGetInternalObjectHandle; +} + +static void __nvoc_init_funcTable_Subdevice_3(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner) { + RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; + const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; + PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); + PORT_UNREFERENCED_VARIABLE(rmVariantHal); + PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); pThis->__subdeviceControl__ = &__nvoc_thunk_GpuResource_subdeviceControl; @@ -9872,15 +10014,6 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_subdeviceControlSerialization_Prologue; pThis->__subdeviceCanCopy__ = &__nvoc_thunk_RsResource_subdeviceCanCopy; -} - -static void __nvoc_init_funcTable_Subdevice_3(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner) { - RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; - const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; - PORT_UNREFERENCED_VARIABLE(pThis); - PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); - PORT_UNREFERENCED_VARIABLE(rmVariantHal); - PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); pThis->__subdeviceIsDuplicate__ = &__nvoc_thunk_RsResource_subdeviceIsDuplicate; diff --git a/src/nvidia/generated/g_subdevice_nvoc.h b/src/nvidia/generated/g_subdevice_nvoc.h index 1ae58323f1..03123808d0 100644 --- a/src/nvidia/generated/g_subdevice_nvoc.h +++ b/src/nvidia/generated/g_subdevice_nvoc.h @@ -160,7 +160,6 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdBusGetPcieReqAtomicsCaps__)(struct Subdevice *, NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdBusGetPcieSupportedGpuAtomics__)(struct Subdevice *, NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdBusGetC2CInfo__)(struct Subdevice *, NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS *); - NV_STATUS (*__subdeviceCtrlCmdBusGetC2CErrorInfo__)(struct Subdevice *, NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdBusSysmemAccess__)(struct Subdevice *, NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdBusSetP2pMapping__)(struct Subdevice *, NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdBusUnsetP2pMapping__)(struct Subdevice *, NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS *); @@ -219,6 +218,8 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdNvlinkDirectConnectCheck__)(struct Subdevice *, NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdNvlinkGetL1Threshold__)(struct Subdevice *, NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdIsNvlinkReducedConfig__)(struct Subdevice *, NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdNvlinkGetPortEvents__)(struct Subdevice *, NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdNvlinkCycleLink__)(struct Subdevice *, NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdI2cReadBuffer__)(struct Subdevice *, NV2080_CTRL_I2C_READ_BUFFER_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdI2cWriteBuffer__)(struct Subdevice *, NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdI2cReadReg__)(struct Subdevice *, NV2080_CTRL_I2C_RW_REG_PARAMS *); @@ -451,6 +452,9 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdNvdGetNocatJournalRpt__)(struct Subdevice *, NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdNvdSetNocatJournalData__)(struct Subdevice *, NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdPmgrGetModuleInfo__)(struct Subdevice *, NV2080_CTRL_PMGR_MODULE_INFO_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdGpuProcessPostGc6ExitTasks__)(struct Subdevice *); + NV_STATUS (*__subdeviceCtrlCmdGc6Entry__)(struct Subdevice *, NV2080_CTRL_GC6_ENTRY_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdGc6Exit__)(struct Subdevice *, NV2080_CTRL_GC6_EXIT_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdLpwrDifrPrefetchResponse__)(struct Subdevice *, NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdLpwrDifrCtrl__)(struct Subdevice *, NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdCeGetCaps__)(struct Subdevice *, NV2080_CTRL_CE_GET_CAPS_PARAMS *); @@ -465,6 +469,7 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdFlcnUstreamerControlSet__)(struct Subdevice *, NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFlcnGetCtxBufferInfo__)(struct Subdevice *, NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFlcnGetCtxBufferSize__)(struct Subdevice *, NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalFlcnSetVideoEventBufferFlags__)(struct Subdevice *, NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdEccGetClientExposedCounters__)(struct Subdevice *, NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuQueryEccConfiguration__)(struct Subdevice *, NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuSetEccConfiguration__)(struct Subdevice *, NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS *); @@ -489,7 +494,6 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdInternalStaticKMIGmgrGetComputeInstanceProfiles__)(struct Subdevice *, NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalKMIGmgrExportGPUInstance__)(struct Subdevice *, NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalKMIGmgrImportGPUInstance__)(struct Subdevice *, NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS *); - NV_STATUS (*__subdeviceCtrlCmdInternalKMIGmgrPromoteGpuInstanceMemRange__)(struct Subdevice *, NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdOsUnixGc6BlockerRefCnt__)(struct Subdevice *, NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdOsUnixAllowDisallowGcoff__)(struct Subdevice *, NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdOsUnixAudioDynamicPower__)(struct Subdevice *, NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS *); @@ -553,7 +557,7 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdInternalPerfPerfmonClientReservationSet__)(struct Subdevice *, NV2080_CTRL_INTERNAL_PERF_PERFMON_CLIENT_RESERVATION_SET_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalPerfCfControllerSetMaxVGpuVMCount__)(struct Subdevice *, NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalPerfGetAuxPowerState__)(struct Subdevice *, NV2080_CTRL_INTERNAL_PERF_GET_AUX_POWER_STATE_PARAMS *); - NV_STATUS (*__subdeviceCtrlCmdInternalGc6EntryPrerequisite__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalGcxEntryPrerequisite__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdBifGetStaticInfo__)(struct Subdevice *, NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdBifGetAspmL1Flags__)(struct Subdevice *, NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdBifSetPcieRo__)(struct Subdevice *, NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS *); @@ -604,6 +608,8 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdInternalConfComputeEncryptionControl__)(struct Subdevice *, NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalConfComputeDeriveSwlKeys__)(struct Subdevice *, NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalConfComputeDeriveLceKeys__)(struct Subdevice *, NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalInitUserSharedData__)(struct Subdevice *, NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalUserSharedDataSetDataPoll__)(struct Subdevice *, NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask__)(struct Subdevice *, NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdVgpuMgrInternalShutdownGspVgpuPluginTask__)(struct Subdevice *, NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdVgpuMgrInternalPgpuAddVgpuType__)(struct Subdevice *, NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS *); @@ -616,6 +622,7 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdVgpuMgrInternalGetPgpuMigrationSupport__)(struct Subdevice *, NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdVgpuMgrInternalSetVgpuMgrConfig__)(struct Subdevice *, NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGetAvailableHshubMask__)(struct Subdevice *, NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS *); + NV_STATUS (*__subdeviceCtrlSetEcThrottleMode__)(struct Subdevice *, NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdCcuMap__)(struct Subdevice *, NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdCcuUnmap__)(struct Subdevice *, NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdCcuSetStreamState__)(struct Subdevice *, NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS *); @@ -652,7 +659,7 @@ struct Subdevice { struct Device *pDevice; NvBool bMaxGrTickFreqRequested; NvU64 P2PfbMappedBytes; - NvU32 notifyActions[181]; + NvU32 notifyActions[183]; NvHandle hNotifierMemory; struct Memory *pNotifierMemory; NvHandle hSemMemory; @@ -749,7 +756,6 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdBusGetPcieReqAtomicsCaps(pSubdevice, pParams) subdeviceCtrlCmdBusGetPcieReqAtomicsCaps_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBusGetPcieSupportedGpuAtomics(pSubdevice, pParams) subdeviceCtrlCmdBusGetPcieSupportedGpuAtomics_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBusGetC2CInfo(pSubdevice, pParams) subdeviceCtrlCmdBusGetC2CInfo_DISPATCH(pSubdevice, pParams) -#define subdeviceCtrlCmdBusGetC2CErrorInfo(pSubdevice, pParams) subdeviceCtrlCmdBusGetC2CErrorInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBusSysmemAccess(pSubdevice, pParams) subdeviceCtrlCmdBusSysmemAccess_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBusSetP2pMapping(pSubdevice, pParams) subdeviceCtrlCmdBusSetP2pMapping_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBusUnsetP2pMapping(pSubdevice, pParams) subdeviceCtrlCmdBusUnsetP2pMapping_DISPATCH(pSubdevice, pParams) @@ -808,6 +814,8 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdNvlinkDirectConnectCheck(pSubdevice, pParams) subdeviceCtrlCmdNvlinkDirectConnectCheck_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdNvlinkGetL1Threshold(pSubdevice, pParams) subdeviceCtrlCmdNvlinkGetL1Threshold_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdIsNvlinkReducedConfig(pSubdevice, pParams) subdeviceCtrlCmdIsNvlinkReducedConfig_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdNvlinkGetPortEvents(pSubdevice, pParams) subdeviceCtrlCmdNvlinkGetPortEvents_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdNvlinkCycleLink(pSubdevice, pParams) subdeviceCtrlCmdNvlinkCycleLink_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdI2cReadBuffer(pSubdevice, pI2cParams) subdeviceCtrlCmdI2cReadBuffer_DISPATCH(pSubdevice, pI2cParams) #define subdeviceCtrlCmdI2cWriteBuffer(pSubdevice, pI2cParams) subdeviceCtrlCmdI2cWriteBuffer_DISPATCH(pSubdevice, pI2cParams) #define subdeviceCtrlCmdI2cReadReg(pSubdevice, pI2cParams) subdeviceCtrlCmdI2cReadReg_DISPATCH(pSubdevice, pI2cParams) @@ -1045,6 +1053,9 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdNvdGetNocatJournalRpt(pSubdevice, pReportParams) subdeviceCtrlCmdNvdGetNocatJournalRpt_DISPATCH(pSubdevice, pReportParams) #define subdeviceCtrlCmdNvdSetNocatJournalData(pSubdevice, pReportParams) subdeviceCtrlCmdNvdSetNocatJournalData_DISPATCH(pSubdevice, pReportParams) #define subdeviceCtrlCmdPmgrGetModuleInfo(pSubdevice, pModuleInfoParams) subdeviceCtrlCmdPmgrGetModuleInfo_DISPATCH(pSubdevice, pModuleInfoParams) +#define subdeviceCtrlCmdGpuProcessPostGc6ExitTasks(pSubdevice) subdeviceCtrlCmdGpuProcessPostGc6ExitTasks_DISPATCH(pSubdevice) +#define subdeviceCtrlCmdGc6Entry(pSubdevice, pParams) subdeviceCtrlCmdGc6Entry_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdGc6Exit(pSubdevice, pParams) subdeviceCtrlCmdGc6Exit_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdLpwrDifrPrefetchResponse(pSubdevice, pParams) subdeviceCtrlCmdLpwrDifrPrefetchResponse_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdLpwrDifrCtrl(pSubdevice, pParams) subdeviceCtrlCmdLpwrDifrCtrl_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdCeGetCaps(pSubdevice, pCeCapsParams) subdeviceCtrlCmdCeGetCaps_DISPATCH(pSubdevice, pCeCapsParams) @@ -1059,6 +1070,7 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdFlcnUstreamerControlSet(pSubdevice, pParams) subdeviceCtrlCmdFlcnUstreamerControlSet_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdFlcnGetCtxBufferInfo(pSubdevice, pParams) subdeviceCtrlCmdFlcnGetCtxBufferInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdFlcnGetCtxBufferSize(pSubdevice, pParams) subdeviceCtrlCmdFlcnGetCtxBufferSize_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalFlcnSetVideoEventBufferFlags(pSubdevice, pParams) subdeviceCtrlCmdInternalFlcnSetVideoEventBufferFlags_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdEccGetClientExposedCounters(pSubdevice, pParams) subdeviceCtrlCmdEccGetClientExposedCounters_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGpuQueryEccConfiguration(pSubdevice, pConfig) subdeviceCtrlCmdGpuQueryEccConfiguration_DISPATCH(pSubdevice, pConfig) #define subdeviceCtrlCmdGpuSetEccConfiguration(pSubdevice, pConfig) subdeviceCtrlCmdGpuSetEccConfiguration_DISPATCH(pSubdevice, pConfig) @@ -1083,7 +1095,6 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdInternalStaticKMIGmgrGetComputeInstanceProfiles(pSubdevice, pParams) subdeviceCtrlCmdInternalStaticKMIGmgrGetComputeInstanceProfiles_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalKMIGmgrExportGPUInstance(pSubdevice, pParams) subdeviceCtrlCmdInternalKMIGmgrExportGPUInstance_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalKMIGmgrImportGPUInstance(pSubdevice, pParams) subdeviceCtrlCmdInternalKMIGmgrImportGPUInstance_DISPATCH(pSubdevice, pParams) -#define subdeviceCtrlCmdInternalKMIGmgrPromoteGpuInstanceMemRange(pSubdevice, pParams) subdeviceCtrlCmdInternalKMIGmgrPromoteGpuInstanceMemRange_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdOsUnixGc6BlockerRefCnt(pSubdevice, pParams) subdeviceCtrlCmdOsUnixGc6BlockerRefCnt_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdOsUnixAllowDisallowGcoff(pSubdevice, pParams) subdeviceCtrlCmdOsUnixAllowDisallowGcoff_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdOsUnixAudioDynamicPower(pSubdevice, pParams) subdeviceCtrlCmdOsUnixAudioDynamicPower_DISPATCH(pSubdevice, pParams) @@ -1147,7 +1158,7 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdInternalPerfPerfmonClientReservationSet(pSubdevice, pParams) subdeviceCtrlCmdInternalPerfPerfmonClientReservationSet_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalPerfCfControllerSetMaxVGpuVMCount(pSubdevice, pParams) subdeviceCtrlCmdInternalPerfCfControllerSetMaxVGpuVMCount_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalPerfGetAuxPowerState(pSubdevice, pParams) subdeviceCtrlCmdInternalPerfGetAuxPowerState_DISPATCH(pSubdevice, pParams) -#define subdeviceCtrlCmdInternalGc6EntryPrerequisite(pSubdevice, pG6EntryPrerequisite) subdeviceCtrlCmdInternalGc6EntryPrerequisite_DISPATCH(pSubdevice, pG6EntryPrerequisite) +#define subdeviceCtrlCmdInternalGcxEntryPrerequisite(pSubdevice, pGcxEntryPrerequisite) subdeviceCtrlCmdInternalGcxEntryPrerequisite_DISPATCH(pSubdevice, pGcxEntryPrerequisite) #define subdeviceCtrlCmdBifGetStaticInfo(pSubdevice, pParams) subdeviceCtrlCmdBifGetStaticInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBifGetAspmL1Flags(pSubdevice, pParams) subdeviceCtrlCmdBifGetAspmL1Flags_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBifSetPcieRo(pSubdevice, pParams) subdeviceCtrlCmdBifSetPcieRo_DISPATCH(pSubdevice, pParams) @@ -1198,6 +1209,8 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdInternalConfComputeEncryptionControl(pSubdevice, pParams) subdeviceCtrlCmdInternalConfComputeEncryptionControl_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalConfComputeDeriveSwlKeys(pSubdevice, pParams) subdeviceCtrlCmdInternalConfComputeDeriveSwlKeys_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalConfComputeDeriveLceKeys(pSubdevice, pParams) subdeviceCtrlCmdInternalConfComputeDeriveLceKeys_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalInitUserSharedData(pSubdevice, pParams) subdeviceCtrlCmdInternalInitUserSharedData_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalUserSharedDataSetDataPoll(pSubdevice, pParams) subdeviceCtrlCmdInternalUserSharedDataSetDataPoll_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask(pSubdevice, pParams) subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdVgpuMgrInternalShutdownGspVgpuPluginTask(pSubdevice, pParams) subdeviceCtrlCmdVgpuMgrInternalShutdownGspVgpuPluginTask_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdVgpuMgrInternalPgpuAddVgpuType(pSubdevice, pParams) subdeviceCtrlCmdVgpuMgrInternalPgpuAddVgpuType_DISPATCH(pSubdevice, pParams) @@ -1210,6 +1223,7 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdVgpuMgrInternalGetPgpuMigrationSupport(pSubdevice, pParams) subdeviceCtrlCmdVgpuMgrInternalGetPgpuMigrationSupport_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdVgpuMgrInternalSetVgpuMgrConfig(pSubdevice, pParams) subdeviceCtrlCmdVgpuMgrInternalSetVgpuMgrConfig_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGetAvailableHshubMask(pSubdevice, pParams) subdeviceCtrlCmdGetAvailableHshubMask_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlSetEcThrottleMode(pSubdevice, pParams) subdeviceCtrlSetEcThrottleMode_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdCcuMap(pSubdevice, pParams) subdeviceCtrlCmdCcuMap_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdCcuUnmap(pSubdevice, pParams) subdeviceCtrlCmdCcuUnmap_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdCcuSetStreamState(pSubdevice, pParams) subdeviceCtrlCmdCcuSetStreamState_DISPATCH(pSubdevice, pParams) @@ -1505,12 +1519,6 @@ static inline NV_STATUS subdeviceCtrlCmdBusGetC2CInfo_DISPATCH(struct Subdevice return pSubdevice->__subdeviceCtrlCmdBusGetC2CInfo__(pSubdevice, pParams); } -NV_STATUS subdeviceCtrlCmdBusGetC2CErrorInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS *pParams); - -static inline NV_STATUS subdeviceCtrlCmdBusGetC2CErrorInfo_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS *pParams) { - return pSubdevice->__subdeviceCtrlCmdBusGetC2CErrorInfo__(pSubdevice, pParams); -} - NV_STATUS subdeviceCtrlCmdBusSysmemAccess_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdBusSysmemAccess_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS *pParams) { @@ -1859,6 +1867,18 @@ static inline NV_STATUS subdeviceCtrlCmdIsNvlinkReducedConfig_DISPATCH(struct Su return pSubdevice->__subdeviceCtrlCmdIsNvlinkReducedConfig__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdNvlinkGetPortEvents_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdNvlinkGetPortEvents_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdNvlinkGetPortEvents__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdNvlinkCycleLink_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdNvlinkCycleLink_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdNvlinkCycleLink__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdI2cReadBuffer_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_I2C_READ_BUFFER_PARAMS *pI2cParams); static inline NV_STATUS subdeviceCtrlCmdI2cReadBuffer_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_I2C_READ_BUFFER_PARAMS *pI2cParams) { @@ -3255,6 +3275,24 @@ static inline NV_STATUS subdeviceCtrlCmdPmgrGetModuleInfo_DISPATCH(struct Subdev return pSubdevice->__subdeviceCtrlCmdPmgrGetModuleInfo__(pSubdevice, pModuleInfoParams); } +NV_STATUS subdeviceCtrlCmdGpuProcessPostGc6ExitTasks_IMPL(struct Subdevice *pSubdevice); + +static inline NV_STATUS subdeviceCtrlCmdGpuProcessPostGc6ExitTasks_DISPATCH(struct Subdevice *pSubdevice) { + return pSubdevice->__subdeviceCtrlCmdGpuProcessPostGc6ExitTasks__(pSubdevice); +} + +NV_STATUS subdeviceCtrlCmdGc6Entry_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GC6_ENTRY_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdGc6Entry_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GC6_ENTRY_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdGc6Entry__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdGc6Exit_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GC6_EXIT_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdGc6Exit_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GC6_EXIT_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdGc6Exit__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdLpwrDifrPrefetchResponse_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdLpwrDifrPrefetchResponse_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS *pParams) { @@ -3339,6 +3377,12 @@ static inline NV_STATUS subdeviceCtrlCmdFlcnGetCtxBufferSize_DISPATCH(struct Sub return pSubdevice->__subdeviceCtrlCmdFlcnGetCtxBufferSize__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdInternalFlcnSetVideoEventBufferFlags_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalFlcnSetVideoEventBufferFlags_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalFlcnSetVideoEventBufferFlags__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdEccGetClientExposedCounters_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdEccGetClientExposedCounters_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS *pParams) { @@ -3483,12 +3527,6 @@ static inline NV_STATUS subdeviceCtrlCmdInternalKMIGmgrImportGPUInstance_DISPATC return pSubdevice->__subdeviceCtrlCmdInternalKMIGmgrImportGPUInstance__(pSubdevice, pParams); } -NV_STATUS subdeviceCtrlCmdInternalKMIGmgrPromoteGpuInstanceMemRange_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS *pParams); - -static inline NV_STATUS subdeviceCtrlCmdInternalKMIGmgrPromoteGpuInstanceMemRange_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS *pParams) { - return pSubdevice->__subdeviceCtrlCmdInternalKMIGmgrPromoteGpuInstanceMemRange__(pSubdevice, pParams); -} - NV_STATUS subdeviceCtrlCmdOsUnixGc6BlockerRefCnt_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdOsUnixGc6BlockerRefCnt_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS *pParams) { @@ -3867,10 +3905,10 @@ static inline NV_STATUS subdeviceCtrlCmdInternalPerfGetAuxPowerState_DISPATCH(st return pSubdevice->__subdeviceCtrlCmdInternalPerfGetAuxPowerState__(pSubdevice, pParams); } -NV_STATUS subdeviceCtrlCmdInternalGc6EntryPrerequisite_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS *pG6EntryPrerequisite); +NV_STATUS subdeviceCtrlCmdInternalGcxEntryPrerequisite_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS *pGcxEntryPrerequisite); -static inline NV_STATUS subdeviceCtrlCmdInternalGc6EntryPrerequisite_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS *pG6EntryPrerequisite) { - return pSubdevice->__subdeviceCtrlCmdInternalGc6EntryPrerequisite__(pSubdevice, pG6EntryPrerequisite); +static inline NV_STATUS subdeviceCtrlCmdInternalGcxEntryPrerequisite_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS *pGcxEntryPrerequisite) { + return pSubdevice->__subdeviceCtrlCmdInternalGcxEntryPrerequisite__(pSubdevice, pGcxEntryPrerequisite); } NV_STATUS subdeviceCtrlCmdBifGetStaticInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS *pParams); @@ -4173,6 +4211,18 @@ static inline NV_STATUS subdeviceCtrlCmdInternalConfComputeDeriveLceKeys_DISPATC return pSubdevice->__subdeviceCtrlCmdInternalConfComputeDeriveLceKeys__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdInternalInitUserSharedData_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalInitUserSharedData_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalInitUserSharedData__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdInternalUserSharedDataSetDataPoll_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalUserSharedDataSetDataPoll_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalUserSharedDataSetDataPoll__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS *pParams) { @@ -4245,6 +4295,12 @@ static inline NV_STATUS subdeviceCtrlCmdGetAvailableHshubMask_DISPATCH(struct Su return pSubdevice->__subdeviceCtrlCmdGetAvailableHshubMask__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlSetEcThrottleMode_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlSetEcThrottleMode_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlSetEcThrottleMode__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdCcuMap_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdCcuMap_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS *pParams) { @@ -4449,30 +4505,19 @@ NV_STATUS subdeviceGetByHandle_IMPL(struct RsClient *pClient, NvHandle hSubdevic NV_STATUS subdeviceGetByGpu_IMPL(struct RsClient *pClient, struct OBJGPU *pGpu, struct Subdevice **ppSubdevice); #define subdeviceGetByGpu(pClient, pGpu, ppSubdevice) subdeviceGetByGpu_IMPL(pClient, pGpu, ppSubdevice) +NV_STATUS subdeviceGetByDeviceAndGpu_IMPL(struct RsClient *pClient, struct Device *pDevice, struct OBJGPU *pGpu, struct Subdevice **ppSubdevice); + +#define subdeviceGetByDeviceAndGpu(pClient, pDevice, pGpu, ppSubdevice) subdeviceGetByDeviceAndGpu_IMPL(pClient, pDevice, pGpu, ppSubdevice) NV_STATUS subdeviceGetByInstance_IMPL(struct RsClient *pClient, NvHandle hDevice, NvU32 subDeviceInst, struct Subdevice **ppSubdevice); #define subdeviceGetByInstance(pClient, hDevice, subDeviceInst, ppSubdevice) subdeviceGetByInstance_IMPL(pClient, hDevice, subDeviceInst, ppSubdevice) #undef PRIVATE_FIELD -// **************************************************************************** -// Deprecated Definitions -// **************************************************************************** - -/** - * WARNING: This function is deprecated! Please use subdeviceGetByGpu and - * GPU_RES_SET_THREAD_BC_STATE (if needed to set thread UC state for SLI) - */ -struct Subdevice *CliGetSubDeviceInfoFromGpu(NvHandle, struct OBJGPU*); - -/** - * WARNING: This function is deprecated! Please use subdeviceGetByGpu and - * RES_GET_HANDLE - */ -NV_STATUS CliGetSubDeviceHandleFromGpu(NvHandle, struct OBJGPU*, NvHandle *); #endif #ifdef __cplusplus } // extern "C" #endif + #endif // _G_SUBDEVICE_NVOC_H_ diff --git a/src/nvidia/generated/g_sw_test_nvoc.h b/src/nvidia/generated/g_sw_test_nvoc.h index 82a71acb3e..2aafc6a715 100644 --- a/src/nvidia/generated/g_sw_test_nvoc.h +++ b/src/nvidia/generated/g_sw_test_nvoc.h @@ -295,4 +295,5 @@ void swtestDestruct_IMPL(struct SoftwareMethodTest *pSwTest); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_SW_TEST_NVOC_H_ diff --git a/src/nvidia/generated/g_swintr_nvoc.c b/src/nvidia/generated/g_swintr_nvoc.c index b23c9cd131..e837fc36b5 100644 --- a/src/nvidia/generated/g_swintr_nvoc.c +++ b/src/nvidia/generated/g_swintr_nvoc.c @@ -75,7 +75,7 @@ const struct NVOC_CLASS_DEF __nvoc_class_def_SwIntr = /*pExportInfo=*/ &__nvoc_export_info_SwIntr }; -static void __nvoc_thunk_SwIntr_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pSwIntr, IntrServiceRecord pRecords[167]) { +static void __nvoc_thunk_SwIntr_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pSwIntr, IntrServiceRecord pRecords[168]) { swintrRegisterIntrService(pGpu, (struct SwIntr *)(((unsigned char *)pSwIntr) - __nvoc_rtti_SwIntr_IntrService.offset), pRecords); } diff --git a/src/nvidia/generated/g_swintr_nvoc.h b/src/nvidia/generated/g_swintr_nvoc.h index d7e87f28e4..0ddf289eb6 100644 --- a/src/nvidia/generated/g_swintr_nvoc.h +++ b/src/nvidia/generated/g_swintr_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -125,9 +125,9 @@ NV_STATUS __nvoc_objCreate_SwIntr(SwIntr**, Dynamic*, NvU32); #define swintrStatePostLoad(pGpu, pEngstate, arg0) swintrStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) #define swintrConstructEngine(pGpu, pEngstate, arg0) swintrConstructEngine_DISPATCH(pGpu, pEngstate, arg0) #define swintrIsPresent(pGpu, pEngstate) swintrIsPresent_DISPATCH(pGpu, pEngstate) -void swintrRegisterIntrService_IMPL(OBJGPU *pGpu, struct SwIntr *pSwIntr, IntrServiceRecord pRecords[167]); +void swintrRegisterIntrService_IMPL(OBJGPU *pGpu, struct SwIntr *pSwIntr, IntrServiceRecord pRecords[168]); -static inline void swintrRegisterIntrService_DISPATCH(OBJGPU *pGpu, struct SwIntr *pSwIntr, IntrServiceRecord pRecords[167]) { +static inline void swintrRegisterIntrService_DISPATCH(OBJGPU *pGpu, struct SwIntr *pSwIntr, IntrServiceRecord pRecords[168]) { pSwIntr->__swintrRegisterIntrService__(pGpu, pSwIntr, pRecords); } @@ -209,4 +209,5 @@ static inline NvBool swintrIsPresent_DISPATCH(POBJGPU pGpu, struct SwIntr *pEngs #ifdef __cplusplus } // extern "C" #endif + #endif // _G_SWINTR_NVOC_H_ diff --git a/src/nvidia/generated/g_syncgpuboost_nvoc.h b/src/nvidia/generated/g_syncgpuboost_nvoc.h index ec656370e4..5d91bb07bc 100644 --- a/src/nvidia/generated/g_syncgpuboost_nvoc.h +++ b/src/nvidia/generated/g_syncgpuboost_nvoc.h @@ -223,4 +223,5 @@ void syncgpuboostDestruct_IMPL(struct SyncGpuBoost *pResource); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_SYNCGPUBOOST_NVOC_H_ diff --git a/src/nvidia/generated/g_system_mem_nvoc.c b/src/nvidia/generated/g_system_mem_nvoc.c index f27e958af0..31fbc7115b 100644 --- a/src/nvidia/generated/g_system_mem_nvoc.c +++ b/src/nvidia/generated/g_system_mem_nvoc.c @@ -118,6 +118,10 @@ static NV_STATUS __nvoc_thunk_Memory_sysmemGetMapAddrSpace(struct SystemMemory * return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_SystemMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); } +static NvBool __nvoc_thunk_Memory_sysmemIsExportAllowed(struct SystemMemory *pMemory) { + return memIsExportAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_SystemMemory_Memory.offset)); +} + static NvU32 __nvoc_thunk_RsResource_sysmemGetRefCount(struct SystemMemory *pResource) { return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RsResource.offset)); } @@ -295,6 +299,8 @@ static void __nvoc_init_funcTable_SystemMemory_1(SystemMemory *pThis) { pThis->__sysmemGetMapAddrSpace__ = &__nvoc_thunk_Memory_sysmemGetMapAddrSpace; + pThis->__sysmemIsExportAllowed__ = &__nvoc_thunk_Memory_sysmemIsExportAllowed; + pThis->__sysmemGetRefCount__ = &__nvoc_thunk_RsResource_sysmemGetRefCount; pThis->__sysmemAddAdditionalDependants__ = &__nvoc_thunk_RsResource_sysmemAddAdditionalDependants; diff --git a/src/nvidia/generated/g_system_mem_nvoc.h b/src/nvidia/generated/g_system_mem_nvoc.h index ddf1747372..6f6951d1cc 100644 --- a/src/nvidia/generated/g_system_mem_nvoc.h +++ b/src/nvidia/generated/g_system_mem_nvoc.h @@ -58,6 +58,7 @@ struct SystemMemory { NvBool (*__sysmemShareCallback__)(struct SystemMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__sysmemMapTo__)(struct SystemMemory *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__sysmemGetMapAddrSpace__)(struct SystemMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvBool (*__sysmemIsExportAllowed__)(struct SystemMemory *); NvU32 (*__sysmemGetRefCount__)(struct SystemMemory *); void (*__sysmemAddAdditionalDependants__)(struct RsClient *, struct SystemMemory *, RsResourceRef *); NV_STATUS (*__sysmemControl_Prologue__)(struct SystemMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -115,6 +116,7 @@ NV_STATUS __nvoc_objCreate_SystemMemory(SystemMemory**, Dynamic*, NvU32, CALL_CO #define sysmemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) sysmemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define sysmemMapTo(pResource, pParams) sysmemMapTo_DISPATCH(pResource, pParams) #define sysmemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) sysmemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define sysmemIsExportAllowed(pMemory) sysmemIsExportAllowed_DISPATCH(pMemory) #define sysmemGetRefCount(pResource) sysmemGetRefCount_DISPATCH(pResource) #define sysmemAddAdditionalDependants(pClient, pResource, pReference) sysmemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define sysmemControl_Prologue(pResource, pCallContext, pParams) sysmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) @@ -178,6 +180,10 @@ static inline NV_STATUS sysmemGetMapAddrSpace_DISPATCH(struct SystemMemory *pMem return pMemory->__sysmemGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); } +static inline NvBool sysmemIsExportAllowed_DISPATCH(struct SystemMemory *pMemory) { + return pMemory->__sysmemIsExportAllowed__(pMemory); +} + static inline NvU32 sysmemGetRefCount_DISPATCH(struct SystemMemory *pResource) { return pResource->__sysmemGetRefCount__(pResource); } @@ -277,4 +283,5 @@ NV_STATUS sysmemAllocResources(OBJGPU *pGpu, struct MemoryManager *pMemoryManage #ifdef __cplusplus } // extern "C" #endif + #endif // _G_SYSTEM_MEM_NVOC_H_ diff --git a/src/nvidia/generated/g_system_nvoc.c b/src/nvidia/generated/g_system_nvoc.c index 85bd55a3c7..7660371458 100644 --- a/src/nvidia/generated/g_system_nvoc.c +++ b/src/nvidia/generated/g_system_nvoc.c @@ -91,6 +91,7 @@ void __nvoc_init_dataField_OBJSYS(OBJSYS *pThis) { pThis->setProperty(pThis, PDB_PROP_SYS_PRIORITY_BOOST, (0)); pThis->setProperty(pThis, PDB_PROP_SYS_PRIORITY_THROTTLE_DELAY_US, 16 * 1000); pThis->setProperty(pThis, PDB_PROP_SYS_CLIENT_HANDLE_LOOKUP, ((NvBool)(0 == 0))); + pThis->setProperty(pThis, PDB_PROP_SYS_RM_LOCK_TIME_COLLECT, ((NvBool)(0 != 0))); pThis->setProperty(pThis, PDB_PROP_SYS_ROUTE_TO_PHYSICAL_LOCK_BYPASS, ((NvBool)(0 == 0))); pThis->bUseDeferredClientListFree = ((NvBool)(0 != 0)); diff --git a/src/nvidia/generated/g_system_nvoc.h b/src/nvidia/generated/g_system_nvoc.h index c86633ca10..15301c988a 100644 --- a/src/nvidia/generated/g_system_nvoc.h +++ b/src/nvidia/generated/g_system_nvoc.h @@ -200,18 +200,6 @@ typedef struct GpuDb GpuDb; #endif /* __nvoc_class_id_GpuDb */ -struct OBJSWINSTR; - -#ifndef __NVOC_CLASS_OBJSWINSTR_TYPEDEF__ -#define __NVOC_CLASS_OBJSWINSTR_TYPEDEF__ -typedef struct OBJSWINSTR OBJSWINSTR; -#endif /* __NVOC_CLASS_OBJSWINSTR_TYPEDEF__ */ - -#ifndef __nvoc_class_id_OBJSWINSTR -#define __nvoc_class_id_OBJSWINSTR 0xd586f3 -#endif /* __nvoc_class_id_OBJSWINSTR */ - - struct OBJCL; #ifndef __NVOC_CLASS_OBJCL_TYPEDEF__ @@ -322,16 +310,6 @@ typedef struct SYS_STATIC_CONFIG NvBool bOsCCTdxEnabled; } SYS_STATIC_CONFIG; -typedef enum -{ - CPU_VENDOR_UNKNOWN = 0, - CPU_VENDOR_INTEL, - CPU_VENDOR_AMD, - CPU_VENDOR_WINCHIP, - CPU_VENDOR_CYRIX, - CPU_VENDOR_TRANSM -} CPU_VENDOR; - typedef struct { NvBool bInitialized; // Set to true once we id the CPU @@ -350,7 +328,6 @@ typedef struct // filled in if CPU has embedded name NvU32 family; // Vendor defined Family/extended Family NvU32 model; // Vendor defined Model/extended Model - NvU8 vendor; // Vendor CPU_VENDOR NvU32 coresOnDie; // # of cores on the die (0 if unknown) NvU32 platformID; // Chip package type NvU8 stepping; // Silicon stepping @@ -365,7 +342,6 @@ typedef struct NvU32 genRegsMiscIoAdr; } SYS_VGA_POST_STATE; - #ifdef NVOC_SYSTEM_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else @@ -407,6 +383,7 @@ struct OBJSYS { NvU32 PDB_PROP_SYS_PRIORITY_THROTTLE_DELAY_US; NvBool PDB_PROP_SYS_BUGCHECK_ON_TIMEOUT; NvBool PDB_PROP_SYS_CLIENT_HANDLE_LOOKUP; + NvBool PDB_PROP_SYS_RM_LOCK_TIME_COLLECT; NvU32 apiLockMask; NvU32 apiLockModuleMask; NvU32 gpuLockModuleMask; @@ -435,7 +412,6 @@ struct OBJSYS { struct OBJOS *pOS; struct OBJCL *pCl; struct OBJPFM *pPfm; - struct OBJSWINSTR *pSwInstr; struct GpuAccounting *pGpuAcct; struct PlatformRequestHandler *pPlatformRequestHandler; Journal *pRcDB; @@ -526,6 +502,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJSYS; #define PDB_PROP_SYS_IS_AGGRESSIVE_GC6_ENABLED_BASE_NAME PDB_PROP_SYS_IS_AGGRESSIVE_GC6_ENABLED #define PDB_PROP_SYS_HASWELL_CPU_C0_STEPPING_BASE_CAST #define PDB_PROP_SYS_HASWELL_CPU_C0_STEPPING_BASE_NAME PDB_PROP_SYS_HASWELL_CPU_C0_STEPPING +#define PDB_PROP_SYS_RM_LOCK_TIME_COLLECT_BASE_CAST +#define PDB_PROP_SYS_RM_LOCK_TIME_COLLECT_BASE_NAME PDB_PROP_SYS_RM_LOCK_TIME_COLLECT #define PDB_PROP_SYS_DEBUGGER_DISABLED_BASE_CAST #define PDB_PROP_SYS_DEBUGGER_DISABLED_BASE_NAME PDB_PROP_SYS_DEBUGGER_DISABLED #define PDB_PROP_SYS_MXM_THERMAL_CONTROL_PRESENT_BASE_CAST @@ -630,4 +608,5 @@ extern struct OBJSYS *g_pSys; #ifdef __cplusplus } // extern "C" #endif + #endif // _G_SYSTEM_NVOC_H_ diff --git a/src/nvidia/generated/g_third_party_p2p_nvoc.h b/src/nvidia/generated/g_third_party_p2p_nvoc.h index b4237f7f17..e5f2e5d83f 100644 --- a/src/nvidia/generated/g_third_party_p2p_nvoc.h +++ b/src/nvidia/generated/g_third_party_p2p_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2009-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2009-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -36,28 +36,34 @@ extern "C" { #include "rmapi/client.h" #include "gpu/mem_mgr/mem_desc.h" -#include "gpu/subdevice/subdevice.h" #include "gpu/gpu_resource.h" #include -// -// The third-party P2P token is a 64bit integer. -// -// The value may be passed by the RM client enabling the third-party P2P access. -// Otherwise the P2P token format is: -// -// fn [ *GPU ID* ] [ *UNUSED* ] [ *PEER INDEX* ] -// bit 63 32 31 8 7 0 -// -// The third-party P2P token is a globally unique identifier for one -// of an attached GPU's several P2P slots. It is passed, as an -// opaque handle, to third-party driver stacks to allow the setup -// of a P2P mapping between a given GPU and a third-party device with -// NVIDIA P2P capabilities. -// +struct Subdevice; + +#ifndef __NVOC_CLASS_Subdevice_TYPEDEF__ +#define __NVOC_CLASS_Subdevice_TYPEDEF__ +typedef struct Subdevice Subdevice; +#endif /* __NVOC_CLASS_Subdevice_TYPEDEF__ */ + +#ifndef __nvoc_class_id_Subdevice +#define __nvoc_class_id_Subdevice 0x4b01b3 +#endif /* __nvoc_class_id_Subdevice */ + + +struct Memory; + +#ifndef __NVOC_CLASS_Memory_TYPEDEF__ +#define __NVOC_CLASS_Memory_TYPEDEF__ +typedef struct Memory Memory; +#endif /* __NVOC_CLASS_Memory_TYPEDEF__ */ + +#ifndef __nvoc_class_id_Memory +#define __nvoc_class_id_Memory 0x4789f2 +#endif /* __nvoc_class_id_Memory */ + -#define CLI_ENCODEP2PTOKEN(gpuId, peerIndex) (((NvU64)gpuId << 32) | peerIndex) #define CLI_THIRD_PARTY_P2P_FLAGS_INITIALIZED NVBIT(0) @@ -617,4 +623,5 @@ void CliUnregisterMemoryFromThirdPartyP2P(struct Memory *pMemory) #ifdef __cplusplus } // extern "C" #endif + #endif // _G_THIRD_PARTY_P2P_NVOC_H_ diff --git a/src/nvidia/generated/g_timed_sema_nvoc.h b/src/nvidia/generated/g_timed_sema_nvoc.h index a97cb9ed21..8a346c2630 100644 --- a/src/nvidia/generated/g_timed_sema_nvoc.h +++ b/src/nvidia/generated/g_timed_sema_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2016-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -182,11 +182,11 @@ NV_STATUS __nvoc_objCreate_TimedSemaSwObject(TimedSemaSwObject**, Dynamic*, NvU3 #define tsemaGetNotificationShare(pNotifier) tsemaGetNotificationShare_DISPATCH(pNotifier) #define tsemaMap(pGpuResource, pCallContext, pParams, pCpuMapping) tsemaMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define tsemaGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) tsemaGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) -NV_STATUS tsemaRelease_KERNEL(struct OBJGPU *pGpu, NvU64 semaphoreVA, NvU64 notifierVA, NvU32 hVASpace, NvU32 releasevalue, NvU32 completionStatus, struct RsClient *pClient); +NV_STATUS tsemaRelease_KERNEL(struct OBJGPU *pGpu, NvU64 semaphoreVA, NvU64 notifierVA, NvU32 hVASpace, NvU32 releasevalue, NvU32 completionStatus, struct Device *pDevice); -#define tsemaRelease(pGpu, semaphoreVA, notifierVA, hVASpace, releasevalue, completionStatus, pClient) tsemaRelease_KERNEL(pGpu, semaphoreVA, notifierVA, hVASpace, releasevalue, completionStatus, pClient) -#define tsemaRelease_HAL(pGpu, semaphoreVA, notifierVA, hVASpace, releasevalue, completionStatus, pClient) tsemaRelease(pGpu, semaphoreVA, notifierVA, hVASpace, releasevalue, completionStatus, pClient) +#define tsemaRelease(pGpu, semaphoreVA, notifierVA, hVASpace, releasevalue, completionStatus, pDevice) tsemaRelease_KERNEL(pGpu, semaphoreVA, notifierVA, hVASpace, releasevalue, completionStatus, pDevice) +#define tsemaRelease_HAL(pGpu, semaphoreVA, notifierVA, hVASpace, releasevalue, completionStatus, pDevice) tsemaRelease(pGpu, semaphoreVA, notifierVA, hVASpace, releasevalue, completionStatus, pDevice) NV_STATUS tsemaGetSwMethods_IMPL(struct TimedSemaSwObject *pTimedSemSw, const METHOD **ppMethods, NvU32 *pNumMethods); @@ -353,4 +353,5 @@ typedef struct TimedSemaSwObject *PGF100_TIMED_SEM_SW_OBJECT; #ifdef __cplusplus } // extern "C" #endif + #endif // _G_TIMED_SEMA_NVOC_H_ diff --git a/src/nvidia/generated/g_tmr_nvoc.h b/src/nvidia/generated/g_tmr_nvoc.h index a75b6cc585..bcf25d9de0 100644 --- a/src/nvidia/generated/g_tmr_nvoc.h +++ b/src/nvidia/generated/g_tmr_nvoc.h @@ -350,4 +350,5 @@ static inline void tmrapiDeregisterEvents(struct TimerApi *pTimerApi) { #ifdef __cplusplus } // extern "C" #endif + #endif // _G_TMR_NVOC_H_ diff --git a/src/nvidia/generated/g_traceable_nvoc.h b/src/nvidia/generated/g_traceable_nvoc.h index 0e59e39e18..039ead032c 100644 --- a/src/nvidia/generated/g_traceable_nvoc.h +++ b/src/nvidia/generated/g_traceable_nvoc.h @@ -84,4 +84,5 @@ void objTraverseCaptureState_IMPL(struct Object *pObj); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_TRACEABLE_NVOC_H_ diff --git a/src/nvidia/generated/g_usermode_api_nvoc.c b/src/nvidia/generated/g_usermode_api_nvoc.c index 6006392faa..4beb464cbe 100644 --- a/src/nvidia/generated/g_usermode_api_nvoc.c +++ b/src/nvidia/generated/g_usermode_api_nvoc.c @@ -97,6 +97,10 @@ static NvBool __nvoc_thunk_UserModeApi_resCanCopy(struct RsResource *pUserModeAp return usrmodeCanCopy((struct UserModeApi *)(((unsigned char *)pUserModeApi) - __nvoc_rtti_UserModeApi_RsResource.offset)); } +static NV_STATUS __nvoc_thunk_UserModeApi_memGetMemInterMapParams(struct Memory *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return usrmodeGetMemInterMapParams((struct UserModeApi *)(((unsigned char *)pMemory) - __nvoc_rtti_UserModeApi_Memory.offset), pParams); +} + static NV_STATUS __nvoc_thunk_Memory_usrmodeCheckMemInterUnmap(struct UserModeApi *pMemory, NvBool bSubdeviceHandleProvided) { return memCheckMemInterUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_UserModeApi_Memory.offset), bSubdeviceHandleProvided); } @@ -113,6 +117,10 @@ static NV_STATUS __nvoc_thunk_Memory_usrmodeGetMapAddrSpace(struct UserModeApi * return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_UserModeApi_Memory.offset), pCallContext, mapFlags, pAddrSpace); } +static NvBool __nvoc_thunk_Memory_usrmodeIsExportAllowed(struct UserModeApi *pMemory) { + return memIsExportAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_UserModeApi_Memory.offset)); +} + static NvU32 __nvoc_thunk_RsResource_usrmodeGetRefCount(struct UserModeApi *pResource) { return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RsResource.offset)); } @@ -149,10 +157,6 @@ static NV_STATUS __nvoc_thunk_Memory_usrmodeUnmap(struct UserModeApi *pMemory, C return memUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_UserModeApi_Memory.offset), pCallContext, pCpuMapping); } -static NV_STATUS __nvoc_thunk_Memory_usrmodeGetMemInterMapParams(struct UserModeApi *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return memGetMemInterMapParams((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_UserModeApi_Memory.offset), pParams); -} - static NV_STATUS __nvoc_thunk_Memory_usrmodeGetMemoryMappingDescriptor(struct UserModeApi *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_UserModeApi_Memory.offset), ppMemDesc); } @@ -233,8 +237,12 @@ static void __nvoc_init_funcTable_UserModeApi_1(UserModeApi *pThis) { pThis->__usrmodeCanCopy__ = &usrmodeCanCopy_IMPL; + pThis->__usrmodeGetMemInterMapParams__ = &usrmodeGetMemInterMapParams_IMPL; + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__resCanCopy__ = &__nvoc_thunk_UserModeApi_resCanCopy; + pThis->__nvoc_base_Memory.__memGetMemInterMapParams__ = &__nvoc_thunk_UserModeApi_memGetMemInterMapParams; + pThis->__usrmodeCheckMemInterUnmap__ = &__nvoc_thunk_Memory_usrmodeCheckMemInterUnmap; pThis->__usrmodeShareCallback__ = &__nvoc_thunk_RmResource_usrmodeShareCallback; @@ -243,6 +251,8 @@ static void __nvoc_init_funcTable_UserModeApi_1(UserModeApi *pThis) { pThis->__usrmodeGetMapAddrSpace__ = &__nvoc_thunk_Memory_usrmodeGetMapAddrSpace; + pThis->__usrmodeIsExportAllowed__ = &__nvoc_thunk_Memory_usrmodeIsExportAllowed; + pThis->__usrmodeGetRefCount__ = &__nvoc_thunk_RsResource_usrmodeGetRefCount; pThis->__usrmodeAddAdditionalDependants__ = &__nvoc_thunk_RsResource_usrmodeAddAdditionalDependants; @@ -261,8 +271,6 @@ static void __nvoc_init_funcTable_UserModeApi_1(UserModeApi *pThis) { pThis->__usrmodeUnmap__ = &__nvoc_thunk_Memory_usrmodeUnmap; - pThis->__usrmodeGetMemInterMapParams__ = &__nvoc_thunk_Memory_usrmodeGetMemInterMapParams; - pThis->__usrmodeGetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_usrmodeGetMemoryMappingDescriptor; pThis->__usrmodeControlFilter__ = &__nvoc_thunk_RsResource_usrmodeControlFilter; diff --git a/src/nvidia/generated/g_usermode_api_nvoc.h b/src/nvidia/generated/g_usermode_api_nvoc.h index f031dacd82..ddda4e4f55 100644 --- a/src/nvidia/generated/g_usermode_api_nvoc.h +++ b/src/nvidia/generated/g_usermode_api_nvoc.h @@ -59,10 +59,12 @@ struct UserModeApi { struct Memory *__nvoc_pbase_Memory; struct UserModeApi *__nvoc_pbase_UserModeApi; NvBool (*__usrmodeCanCopy__)(struct UserModeApi *); + NV_STATUS (*__usrmodeGetMemInterMapParams__)(struct UserModeApi *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__usrmodeCheckMemInterUnmap__)(struct UserModeApi *, NvBool); NvBool (*__usrmodeShareCallback__)(struct UserModeApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__usrmodeMapTo__)(struct UserModeApi *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__usrmodeGetMapAddrSpace__)(struct UserModeApi *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvBool (*__usrmodeIsExportAllowed__)(struct UserModeApi *); NvU32 (*__usrmodeGetRefCount__)(struct UserModeApi *); void (*__usrmodeAddAdditionalDependants__)(struct RsClient *, struct UserModeApi *, RsResourceRef *); NV_STATUS (*__usrmodeControl_Prologue__)(struct UserModeApi *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -72,7 +74,6 @@ struct UserModeApi { NV_STATUS (*__usrmodeControlLookup__)(struct UserModeApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__usrmodeControl__)(struct UserModeApi *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__usrmodeUnmap__)(struct UserModeApi *, CALL_CONTEXT *, RsCpuMapping *); - NV_STATUS (*__usrmodeGetMemInterMapParams__)(struct UserModeApi *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__usrmodeGetMemoryMappingDescriptor__)(struct UserModeApi *, MEMORY_DESCRIPTOR **); NV_STATUS (*__usrmodeControlFilter__)(struct UserModeApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__usrmodeControlSerialization_Prologue__)(struct UserModeApi *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -83,6 +84,8 @@ struct UserModeApi { void (*__usrmodeControlSerialization_Epilogue__)(struct UserModeApi *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__usrmodeMap__)(struct UserModeApi *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__usrmodeAccessCallback__)(struct UserModeApi *, struct RsClient *, void *, RsAccessRight); + NvBool bPrivMapping; + NvBool bInternalMmio; }; #ifndef __NVOC_CLASS_UserModeApi_TYPEDEF__ @@ -114,10 +117,12 @@ NV_STATUS __nvoc_objCreate_UserModeApi(UserModeApi**, Dynamic*, NvU32, CALL_CONT __nvoc_objCreate_UserModeApi((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) #define usrmodeCanCopy(pUserModeApi) usrmodeCanCopy_DISPATCH(pUserModeApi) +#define usrmodeGetMemInterMapParams(pMemory, pParams) usrmodeGetMemInterMapParams_DISPATCH(pMemory, pParams) #define usrmodeCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) usrmodeCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) #define usrmodeShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) usrmodeShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define usrmodeMapTo(pResource, pParams) usrmodeMapTo_DISPATCH(pResource, pParams) #define usrmodeGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) usrmodeGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define usrmodeIsExportAllowed(pMemory) usrmodeIsExportAllowed_DISPATCH(pMemory) #define usrmodeGetRefCount(pResource) usrmodeGetRefCount_DISPATCH(pResource) #define usrmodeAddAdditionalDependants(pClient, pResource, pReference) usrmodeAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define usrmodeControl_Prologue(pResource, pCallContext, pParams) usrmodeControl_Prologue_DISPATCH(pResource, pCallContext, pParams) @@ -127,7 +132,6 @@ NV_STATUS __nvoc_objCreate_UserModeApi(UserModeApi**, Dynamic*, NvU32, CALL_CONT #define usrmodeControlLookup(pResource, pParams, ppEntry) usrmodeControlLookup_DISPATCH(pResource, pParams, ppEntry) #define usrmodeControl(pMemory, pCallContext, pParams) usrmodeControl_DISPATCH(pMemory, pCallContext, pParams) #define usrmodeUnmap(pMemory, pCallContext, pCpuMapping) usrmodeUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) -#define usrmodeGetMemInterMapParams(pMemory, pParams) usrmodeGetMemInterMapParams_DISPATCH(pMemory, pParams) #define usrmodeGetMemoryMappingDescriptor(pMemory, ppMemDesc) usrmodeGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) #define usrmodeControlFilter(pResource, pCallContext, pParams) usrmodeControlFilter_DISPATCH(pResource, pCallContext, pParams) #define usrmodeControlSerialization_Prologue(pResource, pCallContext, pParams) usrmodeControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) @@ -144,6 +148,12 @@ static inline NvBool usrmodeCanCopy_DISPATCH(struct UserModeApi *pUserModeApi) { return pUserModeApi->__usrmodeCanCopy__(pUserModeApi); } +NV_STATUS usrmodeGetMemInterMapParams_IMPL(struct UserModeApi *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams); + +static inline NV_STATUS usrmodeGetMemInterMapParams_DISPATCH(struct UserModeApi *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pMemory->__usrmodeGetMemInterMapParams__(pMemory, pParams); +} + static inline NV_STATUS usrmodeCheckMemInterUnmap_DISPATCH(struct UserModeApi *pMemory, NvBool bSubdeviceHandleProvided) { return pMemory->__usrmodeCheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); } @@ -160,6 +170,10 @@ static inline NV_STATUS usrmodeGetMapAddrSpace_DISPATCH(struct UserModeApi *pMem return pMemory->__usrmodeGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); } +static inline NvBool usrmodeIsExportAllowed_DISPATCH(struct UserModeApi *pMemory) { + return pMemory->__usrmodeIsExportAllowed__(pMemory); +} + static inline NvU32 usrmodeGetRefCount_DISPATCH(struct UserModeApi *pResource) { return pResource->__usrmodeGetRefCount__(pResource); } @@ -196,10 +210,6 @@ static inline NV_STATUS usrmodeUnmap_DISPATCH(struct UserModeApi *pMemory, CALL_ return pMemory->__usrmodeUnmap__(pMemory, pCallContext, pCpuMapping); } -static inline NV_STATUS usrmodeGetMemInterMapParams_DISPATCH(struct UserModeApi *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { - return pMemory->__usrmodeGetMemInterMapParams__(pMemory, pParams); -} - static inline NV_STATUS usrmodeGetMemoryMappingDescriptor_DISPATCH(struct UserModeApi *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { return pMemory->__usrmodeGetMemoryMappingDescriptor__(pMemory, ppMemDesc); } @@ -251,4 +261,5 @@ NV_STATUS usrmodeConstruct_IMPL(struct UserModeApi *arg_pUserModeApi, CALL_CONTE #ifdef __cplusplus } // extern "C" #endif + #endif // _G_USERMODE_API_NVOC_H_ diff --git a/src/nvidia/generated/g_uvm_channel_retainer_nvoc.h b/src/nvidia/generated/g_uvm_channel_retainer_nvoc.h index 7d1bb23e70..e9d173d22d 100644 --- a/src/nvidia/generated/g_uvm_channel_retainer_nvoc.h +++ b/src/nvidia/generated/g_uvm_channel_retainer_nvoc.h @@ -279,4 +279,5 @@ void uvmchanrtnrDestruct_IMPL(struct UvmChannelRetainer *pUvmChannelRetainer); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_UVM_CHANNEL_RETAINER_NVOC_H_ diff --git a/src/nvidia/generated/g_uvm_nvoc.c b/src/nvidia/generated/g_uvm_nvoc.c index 1b98e06338..8b63ff2b09 100644 --- a/src/nvidia/generated/g_uvm_nvoc.c +++ b/src/nvidia/generated/g_uvm_nvoc.c @@ -83,7 +83,7 @@ static NV_STATUS __nvoc_thunk_OBJUVM_engstateStateInitUnlocked(OBJGPU *pGpu, str return uvmStateInitUnlocked(pGpu, (struct OBJUVM *)(((unsigned char *)pUvm) - __nvoc_rtti_OBJUVM_OBJENGSTATE.offset)); } -static void __nvoc_thunk_OBJUVM_intrservRegisterIntrService(OBJGPU *arg0, struct IntrService *pUvm, IntrServiceRecord arg1[167]) { +static void __nvoc_thunk_OBJUVM_intrservRegisterIntrService(OBJGPU *arg0, struct IntrService *pUvm, IntrServiceRecord arg1[168]) { uvmRegisterIntrService(arg0, (struct OBJUVM *)(((unsigned char *)pUvm) - __nvoc_rtti_OBJUVM_IntrService.offset), arg1); } diff --git a/src/nvidia/generated/g_uvm_nvoc.h b/src/nvidia/generated/g_uvm_nvoc.h index c2fa870658..ca702a102c 100644 --- a/src/nvidia/generated/g_uvm_nvoc.h +++ b/src/nvidia/generated/g_uvm_nvoc.h @@ -674,9 +674,9 @@ static inline NV_STATUS uvmStateInitUnlocked_DISPATCH(OBJGPU *pGpu, struct OBJUV return pUvm->__uvmStateInitUnlocked__(pGpu, pUvm); } -void uvmRegisterIntrService_IMPL(OBJGPU *arg0, struct OBJUVM *pUvm, IntrServiceRecord arg1[167]); +void uvmRegisterIntrService_IMPL(OBJGPU *arg0, struct OBJUVM *pUvm, IntrServiceRecord arg1[168]); -static inline void uvmRegisterIntrService_DISPATCH(OBJGPU *arg0, struct OBJUVM *pUvm, IntrServiceRecord arg1[167]) { +static inline void uvmRegisterIntrService_DISPATCH(OBJGPU *arg0, struct OBJUVM *pUvm, IntrServiceRecord arg1[168]) { pUvm->__uvmRegisterIntrService__(arg0, pUvm, arg1); } @@ -750,4 +750,5 @@ static inline NvBool uvmIsPresent_DISPATCH(POBJGPU pGpu, struct OBJUVM *pEngstat #ifdef __cplusplus } // extern "C" #endif + #endif // _G_UVM_NVOC_H_ diff --git a/src/nvidia/generated/g_uvm_sw_nvoc.h b/src/nvidia/generated/g_uvm_sw_nvoc.h index 21791d7528..b3d8ce58a6 100644 --- a/src/nvidia/generated/g_uvm_sw_nvoc.h +++ b/src/nvidia/generated/g_uvm_sw_nvoc.h @@ -313,4 +313,5 @@ static inline void uvmswInitSwMethodState(struct UvmSwObject *pUvmSw) { #ifdef __cplusplus } // extern "C" #endif + #endif // _G_UVM_SW_NVOC_H_ diff --git a/src/nvidia/generated/g_vaspace_api_nvoc.c b/src/nvidia/generated/g_vaspace_api_nvoc.c index 7b4211c951..1c37028df5 100644 --- a/src/nvidia/generated/g_vaspace_api_nvoc.c +++ b/src/nvidia/generated/g_vaspace_api_nvoc.c @@ -272,6 +272,21 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_VaSpaceA /*pClassInfo=*/ &(__nvoc_class_def_VaSpaceApi.classInfo), #if NV_PRINTF_STRINGS_ALLOWED /*func=*/ "vaspaceapiCtrlCmdVaspaceCopyServerReservedPdes" +#endif + }, + { /* [5] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) vaspaceapiCtrlCmdVaspaceGetHostRmManagedSize_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) + /*flags=*/ 0x0u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x90f10107u, + /*paramSize=*/ sizeof(NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_VaSpaceApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "vaspaceapiCtrlCmdVaspaceGetHostRmManagedSize" #endif }, @@ -279,7 +294,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_VaSpaceA const struct NVOC_EXPORT_INFO __nvoc_export_info_VaSpaceApi = { - /*numEntries=*/ 5, + /*numEntries=*/ 6, /*pExportEntries=*/ __nvoc_exported_method_def_VaSpaceApi }; @@ -338,6 +353,10 @@ static void __nvoc_init_funcTable_VaSpaceApi_1(VaSpaceApi *pThis) { pThis->__vaspaceapiCtrlCmdVaspaceCopyServerReservedPdes__ = &vaspaceapiCtrlCmdVaspaceCopyServerReservedPdes_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) + pThis->__vaspaceapiCtrlCmdVaspaceGetHostRmManagedSize__ = &vaspaceapiCtrlCmdVaspaceGetHostRmManagedSize_IMPL; +#endif + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__resCanCopy__ = &__nvoc_thunk_VaSpaceApi_resCanCopy; pThis->__vaspaceapiShareCallback__ = &__nvoc_thunk_GpuResource_vaspaceapiShareCallback; diff --git a/src/nvidia/generated/g_vaspace_api_nvoc.h b/src/nvidia/generated/g_vaspace_api_nvoc.h index 45c2946b2c..2282100057 100644 --- a/src/nvidia/generated/g_vaspace_api_nvoc.h +++ b/src/nvidia/generated/g_vaspace_api_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -73,6 +73,7 @@ struct VaSpaceApi { NV_STATUS (*__vaspaceapiCtrlCmdVaspaceReserveEntries__)(struct VaSpaceApi *, NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS *); NV_STATUS (*__vaspaceapiCtrlCmdVaspaceReleaseEntries__)(struct VaSpaceApi *, NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS *); NV_STATUS (*__vaspaceapiCtrlCmdVaspaceCopyServerReservedPdes__)(struct VaSpaceApi *, NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS *); + NV_STATUS (*__vaspaceapiCtrlCmdVaspaceGetHostRmManagedSize__)(struct VaSpaceApi *, NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS *); NvBool (*__vaspaceapiShareCallback__)(struct VaSpaceApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__vaspaceapiCheckMemInterUnmap__)(struct VaSpaceApi *, NvBool); NV_STATUS (*__vaspaceapiMapTo__)(struct VaSpaceApi *, RS_RES_MAP_TO_PARAMS *); @@ -135,6 +136,7 @@ NV_STATUS __nvoc_objCreate_VaSpaceApi(VaSpaceApi**, Dynamic*, NvU32, struct CALL #define vaspaceapiCtrlCmdVaspaceReserveEntries(pVaspaceApi, pReserveEntriesParams) vaspaceapiCtrlCmdVaspaceReserveEntries_DISPATCH(pVaspaceApi, pReserveEntriesParams) #define vaspaceapiCtrlCmdVaspaceReleaseEntries(pVaspaceApi, pReleaseEntriesParams) vaspaceapiCtrlCmdVaspaceReleaseEntries_DISPATCH(pVaspaceApi, pReleaseEntriesParams) #define vaspaceapiCtrlCmdVaspaceCopyServerReservedPdes(pVaspaceApi, pCopyServerReservedPdesParams) vaspaceapiCtrlCmdVaspaceCopyServerReservedPdes_DISPATCH(pVaspaceApi, pCopyServerReservedPdesParams) +#define vaspaceapiCtrlCmdVaspaceGetHostRmManagedSize(pVaspaceApi, pVaspaceGetHostRmManagedSizeParams) vaspaceapiCtrlCmdVaspaceGetHostRmManagedSize_DISPATCH(pVaspaceApi, pVaspaceGetHostRmManagedSizeParams) #define vaspaceapiShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) vaspaceapiShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) #define vaspaceapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) vaspaceapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define vaspaceapiMapTo(pResource, pParams) vaspaceapiMapTo_DISPATCH(pResource, pParams) @@ -195,6 +197,12 @@ static inline NV_STATUS vaspaceapiCtrlCmdVaspaceCopyServerReservedPdes_DISPATCH( return pVaspaceApi->__vaspaceapiCtrlCmdVaspaceCopyServerReservedPdes__(pVaspaceApi, pCopyServerReservedPdesParams); } +NV_STATUS vaspaceapiCtrlCmdVaspaceGetHostRmManagedSize_IMPL(struct VaSpaceApi *pVaspaceApi, NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS *pVaspaceGetHostRmManagedSizeParams); + +static inline NV_STATUS vaspaceapiCtrlCmdVaspaceGetHostRmManagedSize_DISPATCH(struct VaSpaceApi *pVaspaceApi, NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS *pVaspaceGetHostRmManagedSizeParams) { + return pVaspaceApi->__vaspaceapiCtrlCmdVaspaceGetHostRmManagedSize__(pVaspaceApi, pVaspaceGetHostRmManagedSizeParams); +} + static inline NvBool vaspaceapiShareCallback_DISPATCH(struct VaSpaceApi *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { return pGpuResource->__vaspaceapiShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } @@ -316,4 +324,5 @@ void vaspaceapiDestruct_IMPL(struct VaSpaceApi *pResource); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_VASPACE_API_NVOC_H_ diff --git a/src/nvidia/generated/g_vaspace_nvoc.c b/src/nvidia/generated/g_vaspace_nvoc.c index ad775654ed..71a3c87782 100644 --- a/src/nvidia/generated/g_vaspace_nvoc.c +++ b/src/nvidia/generated/g_vaspace_nvoc.c @@ -114,8 +114,6 @@ static void __nvoc_init_funcTable_OBJVASPACE_1(OBJVASPACE *pThis) { pThis->__vaspaceGetFlags__ = &vaspaceGetFlags_edd98b; - pThis->__vaspaceIsInternalVaRestricted__ = &vaspaceIsInternalVaRestricted_IMPL; - pThis->__vaspaceMap__ = &vaspaceMap_b7902c; pThis->__vaspaceUnmap__ = &vaspaceUnmap_8b86a5; diff --git a/src/nvidia/generated/g_vaspace_nvoc.h b/src/nvidia/generated/g_vaspace_nvoc.h index a7e651183d..2613cc0cb0 100644 --- a/src/nvidia/generated/g_vaspace_nvoc.h +++ b/src/nvidia/generated/g_vaspace_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -64,6 +64,18 @@ typedef struct VirtMemAllocator VirtMemAllocator; typedef struct MMU_MAP_TARGET MMU_MAP_TARGET; typedef struct NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS; +struct Device; + +#ifndef __NVOC_CLASS_Device_TYPEDEF__ +#define __NVOC_CLASS_Device_TYPEDEF__ +typedef struct Device Device; +#endif /* __NVOC_CLASS_Device_TYPEDEF__ */ + +#ifndef __nvoc_class_id_Device +#define __nvoc_class_id_Device 0xe0ac20 +#endif /* __nvoc_class_id_Device */ + + typedef struct { @@ -114,7 +126,6 @@ typedef enum // BAR_IFB Used for IFB // PERFMON Used for Perfmon // PMU Used for PMU -// DEFAULT_SIZE Ignore varange parameters and use default // SET_MIRRORED // This flag will create a privileged PDB as part of this vaspace // This new PDB will mirror all of the allocations made in the @@ -175,8 +186,6 @@ typedef enum #define VASPACE_FLAGS_BAR_IFB NVBIT(9) #define VASPACE_FLAGS_PERFMON NVBIT(10) #define VASPACE_FLAGS_PMU NVBIT(11) -#define VASPACE_FLAGS_DEFAULT_SIZE NVBIT(12) -#define VASPACE_FLAGS_DEFAULT_PARAMS NVBIT(13) #define VASPACE_FLAGS_PTETABLE_PMA_MANAGED NVBIT(14) #define VASPACE_FLAGS_INVALIDATE_SCOPE_NVLINK_TLB NVBIT(15) #define VASPACE_FLAGS_DISABLE_SPLIT_VAS NVBIT(16) @@ -250,10 +259,9 @@ struct OBJVASPACE { NvU64 (*__vaspaceGetVaLimit__)(struct OBJVASPACE *); NV_STATUS (*__vaspaceGetVasInfo__)(struct OBJVASPACE *, NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS *); NvU32 (*__vaspaceGetFlags__)(struct OBJVASPACE *); - NvBool (*__vaspaceIsInternalVaRestricted__)(struct OBJVASPACE *); NV_STATUS (*__vaspaceMap__)(struct OBJVASPACE *, struct OBJGPU *, const NvU64, const NvU64, const MMU_MAP_TARGET *, const VAS_MAP_FLAGS); void (*__vaspaceUnmap__)(struct OBJVASPACE *, struct OBJGPU *, const NvU64, const NvU64); - NV_STATUS (*__vaspaceReserveMempool__)(struct OBJVASPACE *, struct OBJGPU *, NvHandle, NvU64, NvU64, NvU32); + NV_STATUS (*__vaspaceReserveMempool__)(struct OBJVASPACE *, struct OBJGPU *, struct Device *, NvU64, NvU64, NvU32); struct OBJEHEAP *(*__vaspaceGetHeap__)(struct OBJVASPACE *); NvU64 (*__vaspaceGetMapPageSize__)(struct OBJVASPACE *, struct OBJGPU *, EMEMBLOCK *); NvU64 (*__vaspaceGetBigPageSize__)(struct OBJVASPACE *); @@ -316,10 +324,9 @@ NV_STATUS __nvoc_objCreate_OBJVASPACE(OBJVASPACE**, Dynamic*, NvU32); #define vaspaceGetVaLimit(pVAS) vaspaceGetVaLimit_DISPATCH(pVAS) #define vaspaceGetVasInfo(pVAS, pParams) vaspaceGetVasInfo_DISPATCH(pVAS, pParams) #define vaspaceGetFlags(pVAS) vaspaceGetFlags_DISPATCH(pVAS) -#define vaspaceIsInternalVaRestricted(pVAS) vaspaceIsInternalVaRestricted_DISPATCH(pVAS) #define vaspaceMap(pVAS, pGpu, vaLo, vaHi, pTarget, flags) vaspaceMap_DISPATCH(pVAS, pGpu, vaLo, vaHi, pTarget, flags) #define vaspaceUnmap(pVAS, pGpu, vaLo, vaHi) vaspaceUnmap_DISPATCH(pVAS, pGpu, vaLo, vaHi) -#define vaspaceReserveMempool(pVAS, pGpu, hClient, size, pageSizeLockMask, flags) vaspaceReserveMempool_DISPATCH(pVAS, pGpu, hClient, size, pageSizeLockMask, flags) +#define vaspaceReserveMempool(pVAS, pGpu, pDevice, size, pageSizeLockMask, flags) vaspaceReserveMempool_DISPATCH(pVAS, pGpu, pDevice, size, pageSizeLockMask, flags) #define vaspaceGetHeap(pVAS) vaspaceGetHeap_DISPATCH(pVAS) #define vaspaceGetMapPageSize(pVAS, pGpu, pMemBlock) vaspaceGetMapPageSize_DISPATCH(pVAS, pGpu, pMemBlock) #define vaspaceGetBigPageSize(pVAS) vaspaceGetBigPageSize_DISPATCH(pVAS) @@ -386,12 +393,6 @@ static inline NvU32 vaspaceGetFlags_DISPATCH(struct OBJVASPACE *pVAS) { return pVAS->__vaspaceGetFlags__(pVAS); } -NvBool vaspaceIsInternalVaRestricted_IMPL(struct OBJVASPACE *pVAS); - -static inline NvBool vaspaceIsInternalVaRestricted_DISPATCH(struct OBJVASPACE *pVAS) { - return pVAS->__vaspaceIsInternalVaRestricted__(pVAS); -} - static inline NV_STATUS vaspaceMap_b7902c(struct OBJVASPACE *pVAS, struct OBJGPU *pGpu, const NvU64 vaLo, const NvU64 vaHi, const MMU_MAP_TARGET *pTarget, const VAS_MAP_FLAGS flags) { NV_ASSERT_PRECOMP(((NvBool)(0 != 0))); return NV_ERR_NOT_SUPPORTED; @@ -409,12 +410,12 @@ static inline void vaspaceUnmap_DISPATCH(struct OBJVASPACE *pVAS, struct OBJGPU pVAS->__vaspaceUnmap__(pVAS, pGpu, vaLo, vaHi); } -static inline NV_STATUS vaspaceReserveMempool_ac1694(struct OBJVASPACE *pVAS, struct OBJGPU *pGpu, NvHandle hClient, NvU64 size, NvU64 pageSizeLockMask, NvU32 flags) { +static inline NV_STATUS vaspaceReserveMempool_ac1694(struct OBJVASPACE *pVAS, struct OBJGPU *pGpu, struct Device *pDevice, NvU64 size, NvU64 pageSizeLockMask, NvU32 flags) { return NV_OK; } -static inline NV_STATUS vaspaceReserveMempool_DISPATCH(struct OBJVASPACE *pVAS, struct OBJGPU *pGpu, NvHandle hClient, NvU64 size, NvU64 pageSizeLockMask, NvU32 flags) { - return pVAS->__vaspaceReserveMempool__(pVAS, pGpu, hClient, size, pageSizeLockMask, flags); +static inline NV_STATUS vaspaceReserveMempool_DISPATCH(struct OBJVASPACE *pVAS, struct OBJGPU *pGpu, struct Device *pDevice, NvU64 size, NvU64 pageSizeLockMask, NvU32 flags) { + return pVAS->__vaspaceReserveMempool__(pVAS, pGpu, pDevice, size, pageSizeLockMask, flags); } static inline struct OBJEHEAP *vaspaceGetHeap_128d6d(struct OBJVASPACE *pVAS) { @@ -614,4 +615,5 @@ NvU64 vaspaceGetVaStart_IMPL(struct OBJVASPACE *pVAS); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_VASPACE_NVOC_H_ diff --git a/src/nvidia/generated/g_vblank_callback_nvoc.c b/src/nvidia/generated/g_vblank_callback_nvoc.c index 7c7333ba1e..302c1b9b38 100644 --- a/src/nvidia/generated/g_vblank_callback_nvoc.c +++ b/src/nvidia/generated/g_vblank_callback_nvoc.c @@ -105,7 +105,7 @@ static NV_STATUS __nvoc_thunk_RsResource_vblcbMapTo(struct VblankCallback *pReso return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_GpuResource_vblcbGetMapAddrSpace(struct VblankCallback *pGpuResource, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { +static NV_STATUS __nvoc_thunk_GpuResource_vblcbGetMapAddrSpace(struct VblankCallback *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VblankCallback_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); } @@ -145,11 +145,11 @@ static NvHandle __nvoc_thunk_GpuResource_vblcbGetInternalObjectHandle(struct Vbl return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VblankCallback_GpuResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_vblcbControl(struct VblankCallback *pGpuResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { +static NV_STATUS __nvoc_thunk_GpuResource_vblcbControl(struct VblankCallback *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VblankCallback_GpuResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_GpuResource_vblcbUnmap(struct VblankCallback *pGpuResource, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { +static NV_STATUS __nvoc_thunk_GpuResource_vblcbUnmap(struct VblankCallback *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VblankCallback_GpuResource.offset), pCallContext, pCpuMapping); } @@ -185,7 +185,7 @@ static void __nvoc_thunk_RmResource_vblcbControlSerialization_Epilogue(struct Vb rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_GpuResource_vblcbMap(struct VblankCallback *pGpuResource, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { +static NV_STATUS __nvoc_thunk_GpuResource_vblcbMap(struct VblankCallback *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { return gpuresMap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VblankCallback_GpuResource.offset), pCallContext, pParams, pCpuMapping); } diff --git a/src/nvidia/generated/g_vblank_callback_nvoc.h b/src/nvidia/generated/g_vblank_callback_nvoc.h index 1ed6806e88..76c3b9aa3a 100644 --- a/src/nvidia/generated/g_vblank_callback_nvoc.h +++ b/src/nvidia/generated/g_vblank_callback_nvoc.h @@ -66,7 +66,7 @@ struct VblankCallback { NvBool (*__vblcbShareCallback__)(struct VblankCallback *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__vblcbCheckMemInterUnmap__)(struct VblankCallback *, NvBool); NV_STATUS (*__vblcbMapTo__)(struct VblankCallback *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__vblcbGetMapAddrSpace__)(struct VblankCallback *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NV_STATUS (*__vblcbGetMapAddrSpace__)(struct VblankCallback *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); NvU32 (*__vblcbGetRefCount__)(struct VblankCallback *); void (*__vblcbAddAdditionalDependants__)(struct RsClient *, struct VblankCallback *, RsResourceRef *); NV_STATUS (*__vblcbControl_Prologue__)(struct VblankCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -76,8 +76,8 @@ struct VblankCallback { void (*__vblcbControl_Epilogue__)(struct VblankCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__vblcbControlLookup__)(struct VblankCallback *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__vblcbGetInternalObjectHandle__)(struct VblankCallback *); - NV_STATUS (*__vblcbControl__)(struct VblankCallback *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__vblcbUnmap__)(struct VblankCallback *, CALL_CONTEXT *, RsCpuMapping *); + NV_STATUS (*__vblcbControl__)(struct VblankCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__vblcbUnmap__)(struct VblankCallback *, struct CALL_CONTEXT *, struct RsCpuMapping *); NV_STATUS (*__vblcbGetMemInterMapParams__)(struct VblankCallback *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__vblcbGetMemoryMappingDescriptor__)(struct VblankCallback *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__vblcbControlFilter__)(struct VblankCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -86,7 +86,7 @@ struct VblankCallback { void (*__vblcbPreDestruct__)(struct VblankCallback *); NV_STATUS (*__vblcbIsDuplicate__)(struct VblankCallback *, NvHandle, NvBool *); void (*__vblcbControlSerialization_Epilogue__)(struct VblankCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__vblcbMap__)(struct VblankCallback *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); + NV_STATUS (*__vblcbMap__)(struct VblankCallback *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__vblcbAccessCallback__)(struct VblankCallback *, struct RsClient *, void *, RsAccessRight); VBLANKCALLBACK CallBack; OSVBLANKCALLBACKPROC pProc; @@ -167,7 +167,7 @@ static inline NV_STATUS vblcbMapTo_DISPATCH(struct VblankCallback *pResource, RS return pResource->__vblcbMapTo__(pResource, pParams); } -static inline NV_STATUS vblcbGetMapAddrSpace_DISPATCH(struct VblankCallback *pGpuResource, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { +static inline NV_STATUS vblcbGetMapAddrSpace_DISPATCH(struct VblankCallback *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { return pGpuResource->__vblcbGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); } @@ -207,11 +207,11 @@ static inline NvHandle vblcbGetInternalObjectHandle_DISPATCH(struct VblankCallba return pGpuResource->__vblcbGetInternalObjectHandle__(pGpuResource); } -static inline NV_STATUS vblcbControl_DISPATCH(struct VblankCallback *pGpuResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { +static inline NV_STATUS vblcbControl_DISPATCH(struct VblankCallback *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pGpuResource->__vblcbControl__(pGpuResource, pCallContext, pParams); } -static inline NV_STATUS vblcbUnmap_DISPATCH(struct VblankCallback *pGpuResource, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { +static inline NV_STATUS vblcbUnmap_DISPATCH(struct VblankCallback *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { return pGpuResource->__vblcbUnmap__(pGpuResource, pCallContext, pCpuMapping); } @@ -247,7 +247,7 @@ static inline void vblcbControlSerialization_Epilogue_DISPATCH(struct VblankCall pResource->__vblcbControlSerialization_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS vblcbMap_DISPATCH(struct VblankCallback *pGpuResource, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { +static inline NV_STATUS vblcbMap_DISPATCH(struct VblankCallback *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { return pGpuResource->__vblcbMap__(pGpuResource, pCallContext, pParams, pCpuMapping); } @@ -269,4 +269,5 @@ void vblcbDestruct_IMPL(struct VblankCallback *pVblankCallback); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_VBLANK_CALLBACK_NVOC_H_ diff --git a/src/nvidia/generated/g_vgpuconfigapi_nvoc.h b/src/nvidia/generated/g_vgpuconfigapi_nvoc.h index 95f9f08ab6..ba828374ab 100644 --- a/src/nvidia/generated/g_vgpuconfigapi_nvoc.h +++ b/src/nvidia/generated/g_vgpuconfigapi_nvoc.h @@ -441,4 +441,5 @@ void CliNotifyVgpuConfigEvent (OBJGPU *, NvU32); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_VGPUCONFIGAPI_NVOC_H_ diff --git a/src/nvidia/generated/g_video_mem_nvoc.c b/src/nvidia/generated/g_video_mem_nvoc.c index 89f301eedf..0461224aa1 100644 --- a/src/nvidia/generated/g_video_mem_nvoc.c +++ b/src/nvidia/generated/g_video_mem_nvoc.c @@ -122,6 +122,10 @@ static NV_STATUS __nvoc_thunk_Memory_vidmemGetMapAddrSpace(struct VideoMemory *p return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VideoMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); } +static NvBool __nvoc_thunk_Memory_vidmemIsExportAllowed(struct VideoMemory *pMemory) { + return memIsExportAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VideoMemory_Memory.offset)); +} + static NvU32 __nvoc_thunk_RsResource_vidmemGetRefCount(struct VideoMemory *pResource) { return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RsResource.offset)); } @@ -253,6 +257,8 @@ static void __nvoc_init_funcTable_VideoMemory_1(VideoMemory *pThis) { pThis->__vidmemGetMapAddrSpace__ = &__nvoc_thunk_Memory_vidmemGetMapAddrSpace; + pThis->__vidmemIsExportAllowed__ = &__nvoc_thunk_Memory_vidmemIsExportAllowed; + pThis->__vidmemGetRefCount__ = &__nvoc_thunk_RsResource_vidmemGetRefCount; pThis->__vidmemAddAdditionalDependants__ = &__nvoc_thunk_RsResource_vidmemAddAdditionalDependants; diff --git a/src/nvidia/generated/g_video_mem_nvoc.h b/src/nvidia/generated/g_video_mem_nvoc.h index a47926ae01..100eaefb69 100644 --- a/src/nvidia/generated/g_video_mem_nvoc.h +++ b/src/nvidia/generated/g_video_mem_nvoc.h @@ -71,6 +71,7 @@ struct VideoMemory { NvBool (*__vidmemShareCallback__)(struct VideoMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__vidmemMapTo__)(struct VideoMemory *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__vidmemGetMapAddrSpace__)(struct VideoMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvBool (*__vidmemIsExportAllowed__)(struct VideoMemory *); NvU32 (*__vidmemGetRefCount__)(struct VideoMemory *); void (*__vidmemAddAdditionalDependants__)(struct RsClient *, struct VideoMemory *, RsResourceRef *); NV_STATUS (*__vidmemControl_Prologue__)(struct VideoMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -126,6 +127,7 @@ NV_STATUS __nvoc_objCreate_VideoMemory(VideoMemory**, Dynamic*, NvU32, CALL_CONT #define vidmemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) vidmemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define vidmemMapTo(pResource, pParams) vidmemMapTo_DISPATCH(pResource, pParams) #define vidmemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) vidmemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define vidmemIsExportAllowed(pMemory) vidmemIsExportAllowed_DISPATCH(pMemory) #define vidmemGetRefCount(pResource) vidmemGetRefCount_DISPATCH(pResource) #define vidmemAddAdditionalDependants(pClient, pResource, pReference) vidmemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define vidmemControl_Prologue(pResource, pCallContext, pParams) vidmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) @@ -168,6 +170,10 @@ static inline NV_STATUS vidmemGetMapAddrSpace_DISPATCH(struct VideoMemory *pMemo return pMemory->__vidmemGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); } +static inline NvBool vidmemIsExportAllowed_DISPATCH(struct VideoMemory *pMemory) { + return pMemory->__vidmemIsExportAllowed__(pMemory); +} + static inline NvU32 vidmemGetRefCount_DISPATCH(struct VideoMemory *pResource) { return pResource->__vidmemGetRefCount__(pResource); } @@ -254,9 +260,9 @@ NV_STATUS vidmemConstruct_IMPL(struct VideoMemory *arg_pVideoMemory, CALL_CONTEX void vidmemDestruct_IMPL(struct VideoMemory *pVideoMemory); #define __nvoc_vidmemDestruct(pVideoMemory) vidmemDestruct_IMPL(pVideoMemory) -struct Heap *vidmemGetHeap_IMPL(struct OBJGPU *pGpu, struct Device *pDevice, NvBool bSubheap); +struct Heap *vidmemGetHeap_IMPL(struct OBJGPU *pGpu, struct Device *pDevice, NvBool bSubheap, NvBool bForceGlobalHeap); -#define vidmemGetHeap(pGpu, pDevice, bSubheap) vidmemGetHeap_IMPL(pGpu, pDevice, bSubheap) +#define vidmemGetHeap(pGpu, pDevice, bSubheap, bForceGlobalHeap) vidmemGetHeap_IMPL(pGpu, pDevice, bSubheap, bForceGlobalHeap) #undef PRIVATE_FIELD @@ -271,4 +277,5 @@ NV_STATUS vidmemAllocResources(OBJGPU *pGpu, struct MemoryManager *pMemoryManage #ifdef __cplusplus } // extern "C" #endif + #endif // _G_VIDEO_MEM_NVOC_H_ diff --git a/src/nvidia/generated/g_vidmem_access_bit_buffer_nvoc.c b/src/nvidia/generated/g_vidmem_access_bit_buffer_nvoc.c index b3eeb6e375..2ef2f11abc 100644 --- a/src/nvidia/generated/g_vidmem_access_bit_buffer_nvoc.c +++ b/src/nvidia/generated/g_vidmem_access_bit_buffer_nvoc.c @@ -127,7 +127,7 @@ static NV_STATUS __nvoc_thunk_RsResource_vidmemAccessBitBufMapTo(struct VidmemAc return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VidmemAccessBitBuffer_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_GpuResource_vidmemAccessBitBufGetMapAddrSpace(struct VidmemAccessBitBuffer *pGpuResource, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { +static NV_STATUS __nvoc_thunk_GpuResource_vidmemAccessBitBufGetMapAddrSpace(struct VidmemAccessBitBuffer *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VidmemAccessBitBuffer_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); } @@ -171,11 +171,11 @@ static NvHandle __nvoc_thunk_GpuResource_vidmemAccessBitBufGetInternalObjectHand return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VidmemAccessBitBuffer_GpuResource.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_vidmemAccessBitBufControl(struct VidmemAccessBitBuffer *pGpuResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { +static NV_STATUS __nvoc_thunk_GpuResource_vidmemAccessBitBufControl(struct VidmemAccessBitBuffer *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VidmemAccessBitBuffer_GpuResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_GpuResource_vidmemAccessBitBufUnmap(struct VidmemAccessBitBuffer *pGpuResource, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { +static NV_STATUS __nvoc_thunk_GpuResource_vidmemAccessBitBufUnmap(struct VidmemAccessBitBuffer *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VidmemAccessBitBuffer_GpuResource.offset), pCallContext, pCpuMapping); } @@ -223,7 +223,7 @@ static struct NotifShare *__nvoc_thunk_Notifier_vidmemAccessBitBufGetNotificatio return notifyGetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_VidmemAccessBitBuffer_Notifier.offset)); } -static NV_STATUS __nvoc_thunk_GpuResource_vidmemAccessBitBufMap(struct VidmemAccessBitBuffer *pGpuResource, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { +static NV_STATUS __nvoc_thunk_GpuResource_vidmemAccessBitBufMap(struct VidmemAccessBitBuffer *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { return gpuresMap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VidmemAccessBitBuffer_GpuResource.offset), pCallContext, pParams, pCpuMapping); } diff --git a/src/nvidia/generated/g_vidmem_access_bit_buffer_nvoc.h b/src/nvidia/generated/g_vidmem_access_bit_buffer_nvoc.h index ef99913982..988d1eefb0 100644 --- a/src/nvidia/generated/g_vidmem_access_bit_buffer_nvoc.h +++ b/src/nvidia/generated/g_vidmem_access_bit_buffer_nvoc.h @@ -98,7 +98,7 @@ struct VidmemAccessBitBuffer { NV_STATUS (*__vidmemAccessBitBufCheckMemInterUnmap__)(struct VidmemAccessBitBuffer *, NvBool); NV_STATUS (*__vidmemAccessBitBufGetOrAllocNotifShare__)(struct VidmemAccessBitBuffer *, NvHandle, NvHandle, struct NotifShare **); NV_STATUS (*__vidmemAccessBitBufMapTo__)(struct VidmemAccessBitBuffer *, RS_RES_MAP_TO_PARAMS *); - NV_STATUS (*__vidmemAccessBitBufGetMapAddrSpace__)(struct VidmemAccessBitBuffer *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NV_STATUS (*__vidmemAccessBitBufGetMapAddrSpace__)(struct VidmemAccessBitBuffer *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); void (*__vidmemAccessBitBufSetNotificationShare__)(struct VidmemAccessBitBuffer *, struct NotifShare *); NvU32 (*__vidmemAccessBitBufGetRefCount__)(struct VidmemAccessBitBuffer *); void (*__vidmemAccessBitBufAddAdditionalDependants__)(struct RsClient *, struct VidmemAccessBitBuffer *, RsResourceRef *); @@ -109,8 +109,8 @@ struct VidmemAccessBitBuffer { void (*__vidmemAccessBitBufControl_Epilogue__)(struct VidmemAccessBitBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__vidmemAccessBitBufControlLookup__)(struct VidmemAccessBitBuffer *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__vidmemAccessBitBufGetInternalObjectHandle__)(struct VidmemAccessBitBuffer *); - NV_STATUS (*__vidmemAccessBitBufControl__)(struct VidmemAccessBitBuffer *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__vidmemAccessBitBufUnmap__)(struct VidmemAccessBitBuffer *, CALL_CONTEXT *, RsCpuMapping *); + NV_STATUS (*__vidmemAccessBitBufControl__)(struct VidmemAccessBitBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__vidmemAccessBitBufUnmap__)(struct VidmemAccessBitBuffer *, struct CALL_CONTEXT *, struct RsCpuMapping *); NV_STATUS (*__vidmemAccessBitBufGetMemInterMapParams__)(struct VidmemAccessBitBuffer *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__vidmemAccessBitBufGetMemoryMappingDescriptor__)(struct VidmemAccessBitBuffer *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__vidmemAccessBitBufControlFilter__)(struct VidmemAccessBitBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -122,7 +122,7 @@ struct VidmemAccessBitBuffer { void (*__vidmemAccessBitBufControlSerialization_Epilogue__)(struct VidmemAccessBitBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__vidmemAccessBitBufGetNotificationListPtr__)(struct VidmemAccessBitBuffer *); struct NotifShare *(*__vidmemAccessBitBufGetNotificationShare__)(struct VidmemAccessBitBuffer *); - NV_STATUS (*__vidmemAccessBitBufMap__)(struct VidmemAccessBitBuffer *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); + NV_STATUS (*__vidmemAccessBitBufMap__)(struct VidmemAccessBitBuffer *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__vidmemAccessBitBufAccessCallback__)(struct VidmemAccessBitBuffer *, struct RsClient *, void *, RsAccessRight); }; @@ -227,7 +227,7 @@ static inline NV_STATUS vidmemAccessBitBufMapTo_DISPATCH(struct VidmemAccessBitB return pResource->__vidmemAccessBitBufMapTo__(pResource, pParams); } -static inline NV_STATUS vidmemAccessBitBufGetMapAddrSpace_DISPATCH(struct VidmemAccessBitBuffer *pGpuResource, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { +static inline NV_STATUS vidmemAccessBitBufGetMapAddrSpace_DISPATCH(struct VidmemAccessBitBuffer *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { return pGpuResource->__vidmemAccessBitBufGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); } @@ -271,11 +271,11 @@ static inline NvHandle vidmemAccessBitBufGetInternalObjectHandle_DISPATCH(struct return pGpuResource->__vidmemAccessBitBufGetInternalObjectHandle__(pGpuResource); } -static inline NV_STATUS vidmemAccessBitBufControl_DISPATCH(struct VidmemAccessBitBuffer *pGpuResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { +static inline NV_STATUS vidmemAccessBitBufControl_DISPATCH(struct VidmemAccessBitBuffer *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pGpuResource->__vidmemAccessBitBufControl__(pGpuResource, pCallContext, pParams); } -static inline NV_STATUS vidmemAccessBitBufUnmap_DISPATCH(struct VidmemAccessBitBuffer *pGpuResource, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { +static inline NV_STATUS vidmemAccessBitBufUnmap_DISPATCH(struct VidmemAccessBitBuffer *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { return pGpuResource->__vidmemAccessBitBufUnmap__(pGpuResource, pCallContext, pCpuMapping); } @@ -323,7 +323,7 @@ static inline struct NotifShare *vidmemAccessBitBufGetNotificationShare_DISPATCH return pNotifier->__vidmemAccessBitBufGetNotificationShare__(pNotifier); } -static inline NV_STATUS vidmemAccessBitBufMap_DISPATCH(struct VidmemAccessBitBuffer *pGpuResource, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { +static inline NV_STATUS vidmemAccessBitBufMap_DISPATCH(struct VidmemAccessBitBuffer *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { return pGpuResource->__vidmemAccessBitBufMap__(pGpuResource, pCallContext, pParams, pCpuMapping); } @@ -343,4 +343,5 @@ static inline NV_STATUS __nvoc_vidmemAccessBitBufConstruct(struct VidmemAccessBi #ifdef __cplusplus } // extern "C" #endif + #endif // _G_VIDMEM_ACCESS_BIT_BUFFER_NVOC_H_ diff --git a/src/nvidia/generated/g_virt_mem_allocator_nvoc.h b/src/nvidia/generated/g_virt_mem_allocator_nvoc.h index 26ad67f51f..51872b6159 100644 --- a/src/nvidia/generated/g_virt_mem_allocator_nvoc.h +++ b/src/nvidia/generated/g_virt_mem_allocator_nvoc.h @@ -341,20 +341,6 @@ static inline void dmaUnmapBuffer(struct OBJGPU *pGpu, struct VirtMemAllocator * #define dmaUnmapBuffer_HAL(pGpu, pDma, pVAS, vaddr) dmaUnmapBuffer(pGpu, pDma, pVAS, vaddr) -NvU64 dmaGetPfnFromPte_GP100(struct VirtMemAllocator *pDma, NvBool bSysMem, NvU64 pPteMem); - - -#ifdef __nvoc_virt_mem_allocator_h_disabled -static inline NvU64 dmaGetPfnFromPte(struct VirtMemAllocator *pDma, NvBool bSysMem, NvU64 pPteMem) { - NV_ASSERT_FAILED_PRECOMP("VirtMemAllocator was disabled!"); - return 0; -} -#else //__nvoc_virt_mem_allocator_h_disabled -#define dmaGetPfnFromPte(pDma, bSysMem, pPteMem) dmaGetPfnFromPte_GP100(pDma, bSysMem, pPteMem) -#endif //__nvoc_virt_mem_allocator_h_disabled - -#define dmaGetPfnFromPte_HAL(pDma, bSysMem, pPteMem) dmaGetPfnFromPte(pDma, bSysMem, pPteMem) - static inline struct OBJVASPACE *dmaGetPrivateVAS_fa6e19(struct VirtMemAllocator *pDma) { return ((void *)0); } @@ -598,4 +584,5 @@ RmPhysAddr dmaPageArrayGetPhysAddr(DMA_PAGE_ARRAY *pPageArray, NvU32 pageIndex); #ifdef __cplusplus } // extern "C" #endif + #endif // _G_VIRT_MEM_ALLOCATOR_NVOC_H_ diff --git a/src/nvidia/generated/g_virt_mem_mgr_nvoc.h b/src/nvidia/generated/g_virt_mem_mgr_nvoc.h index c7fa042620..6b721b98cb 100644 --- a/src/nvidia/generated/g_virt_mem_mgr_nvoc.h +++ b/src/nvidia/generated/g_virt_mem_mgr_nvoc.h @@ -133,4 +133,5 @@ static inline NV_STATUS vmmGetVaspaceFromId(struct OBJVMM *pVmm, NvU32 vaspaceId #ifdef __cplusplus } // extern "C" #endif + #endif // _G_VIRT_MEM_MGR_NVOC_H_ diff --git a/src/nvidia/generated/g_virt_mem_range_nvoc.c b/src/nvidia/generated/g_virt_mem_range_nvoc.c index d77ed8a79a..a29bd470ea 100644 --- a/src/nvidia/generated/g_virt_mem_range_nvoc.c +++ b/src/nvidia/generated/g_virt_mem_range_nvoc.c @@ -127,6 +127,10 @@ static NV_STATUS __nvoc_thunk_Memory_vmrangeGetMapAddrSpace(struct VirtualMemory return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), pCallContext, mapFlags, pAddrSpace); } +static NvBool __nvoc_thunk_Memory_vmrangeIsExportAllowed(struct VirtualMemoryRange *pMemory) { + return memIsExportAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset)); +} + static NvU32 __nvoc_thunk_RsResource_vmrangeGetRefCount(struct VirtualMemoryRange *pResource) { return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemoryRange_RsResource.offset)); } @@ -257,6 +261,8 @@ static void __nvoc_init_funcTable_VirtualMemoryRange_1(VirtualMemoryRange *pThis pThis->__vmrangeGetMapAddrSpace__ = &__nvoc_thunk_Memory_vmrangeGetMapAddrSpace; + pThis->__vmrangeIsExportAllowed__ = &__nvoc_thunk_Memory_vmrangeIsExportAllowed; + pThis->__vmrangeGetRefCount__ = &__nvoc_thunk_RsResource_vmrangeGetRefCount; pThis->__vmrangeAddAdditionalDependants__ = &__nvoc_thunk_RsResource_vmrangeAddAdditionalDependants; diff --git a/src/nvidia/generated/g_virt_mem_range_nvoc.h b/src/nvidia/generated/g_virt_mem_range_nvoc.h index 7263e8f6b1..2ab6b0ed05 100644 --- a/src/nvidia/generated/g_virt_mem_range_nvoc.h +++ b/src/nvidia/generated/g_virt_mem_range_nvoc.h @@ -62,6 +62,7 @@ struct VirtualMemoryRange { NV_STATUS (*__vmrangeMapTo__)(struct VirtualMemoryRange *, struct RS_RES_MAP_TO_PARAMS *); NvBool (*__vmrangeShareCallback__)(struct VirtualMemoryRange *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__vmrangeGetMapAddrSpace__)(struct VirtualMemoryRange *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvBool (*__vmrangeIsExportAllowed__)(struct VirtualMemoryRange *); NvU32 (*__vmrangeGetRefCount__)(struct VirtualMemoryRange *); void (*__vmrangeAddAdditionalDependants__)(struct RsClient *, struct VirtualMemoryRange *, RsResourceRef *); NV_STATUS (*__vmrangeControl_Prologue__)(struct VirtualMemoryRange *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -117,6 +118,7 @@ NV_STATUS __nvoc_objCreate_VirtualMemoryRange(VirtualMemoryRange**, Dynamic*, Nv #define vmrangeMapTo(pVirtualMemory, pParams) vmrangeMapTo_DISPATCH(pVirtualMemory, pParams) #define vmrangeShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) vmrangeShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define vmrangeGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) vmrangeGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define vmrangeIsExportAllowed(pMemory) vmrangeIsExportAllowed_DISPATCH(pMemory) #define vmrangeGetRefCount(pResource) vmrangeGetRefCount_DISPATCH(pResource) #define vmrangeAddAdditionalDependants(pClient, pResource, pReference) vmrangeAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define vmrangeControl_Prologue(pResource, pCallContext, pParams) vmrangeControl_Prologue_DISPATCH(pResource, pCallContext, pParams) @@ -154,6 +156,10 @@ static inline NV_STATUS vmrangeGetMapAddrSpace_DISPATCH(struct VirtualMemoryRang return pMemory->__vmrangeGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); } +static inline NvBool vmrangeIsExportAllowed_DISPATCH(struct VirtualMemoryRange *pMemory) { + return pMemory->__vmrangeIsExportAllowed__(pMemory); +} + static inline NvU32 vmrangeGetRefCount_DISPATCH(struct VirtualMemoryRange *pResource) { return pResource->__vmrangeGetRefCount__(pResource); } @@ -249,4 +255,5 @@ NV_STATUS vmrangeConstruct_IMPL(struct VirtualMemoryRange *arg_pVmRange, CALL_CO #ifdef __cplusplus } // extern "C" #endif + #endif // _G_VIRT_MEM_RANGE_NVOC_H_ diff --git a/src/nvidia/generated/g_virtual_mem_nvoc.c b/src/nvidia/generated/g_virtual_mem_nvoc.c index 5773015bcb..8f68959439 100644 --- a/src/nvidia/generated/g_virtual_mem_nvoc.c +++ b/src/nvidia/generated/g_virtual_mem_nvoc.c @@ -122,6 +122,10 @@ static NV_STATUS __nvoc_thunk_Memory_virtmemGetMapAddrSpace(struct VirtualMemory return memGetMapAddrSpace((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemory_Memory.offset), pCallContext, mapFlags, pAddrSpace); } +static NvBool __nvoc_thunk_Memory_virtmemIsExportAllowed(struct VirtualMemory *pMemory) { + return memIsExportAllowed((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemory_Memory.offset)); +} + static NvU32 __nvoc_thunk_RsResource_virtmemGetRefCount(struct VirtualMemory *pResource) { return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemory_RsResource.offset)); } @@ -255,6 +259,8 @@ static void __nvoc_init_funcTable_VirtualMemory_1(VirtualMemory *pThis) { pThis->__virtmemGetMapAddrSpace__ = &__nvoc_thunk_Memory_virtmemGetMapAddrSpace; + pThis->__virtmemIsExportAllowed__ = &__nvoc_thunk_Memory_virtmemIsExportAllowed; + pThis->__virtmemGetRefCount__ = &__nvoc_thunk_RsResource_virtmemGetRefCount; pThis->__virtmemAddAdditionalDependants__ = &__nvoc_thunk_RsResource_virtmemAddAdditionalDependants; diff --git a/src/nvidia/generated/g_virtual_mem_nvoc.h b/src/nvidia/generated/g_virtual_mem_nvoc.h index e582e57981..3b209ea6a7 100644 --- a/src/nvidia/generated/g_virtual_mem_nvoc.h +++ b/src/nvidia/generated/g_virtual_mem_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -65,6 +65,7 @@ struct VirtualMemory { NV_STATUS (*__virtmemCheckMemInterUnmap__)(struct VirtualMemory *, NvBool); NvBool (*__virtmemShareCallback__)(struct VirtualMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__virtmemGetMapAddrSpace__)(struct VirtualMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvBool (*__virtmemIsExportAllowed__)(struct VirtualMemory *); NvU32 (*__virtmemGetRefCount__)(struct VirtualMemory *); void (*__virtmemAddAdditionalDependants__)(struct RsClient *, struct VirtualMemory *, RsResourceRef *); NV_STATUS (*__virtmemControl_Prologue__)(struct VirtualMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -127,6 +128,7 @@ NV_STATUS __nvoc_objCreate_VirtualMemory(VirtualMemory**, Dynamic*, NvU32, CALL_ #define virtmemCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) virtmemCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) #define virtmemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) virtmemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define virtmemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) virtmemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) +#define virtmemIsExportAllowed(pMemory) virtmemIsExportAllowed_DISPATCH(pMemory) #define virtmemGetRefCount(pResource) virtmemGetRefCount_DISPATCH(pResource) #define virtmemAddAdditionalDependants(pClient, pResource, pReference) virtmemAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define virtmemControl_Prologue(pResource, pCallContext, pParams) virtmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) @@ -171,6 +173,10 @@ static inline NV_STATUS virtmemGetMapAddrSpace_DISPATCH(struct VirtualMemory *pM return pMemory->__virtmemGetMapAddrSpace__(pMemory, pCallContext, mapFlags, pAddrSpace); } +static inline NvBool virtmemIsExportAllowed_DISPATCH(struct VirtualMemory *pMemory) { + return pMemory->__virtmemIsExportAllowed__(pMemory); +} + static inline NvU32 virtmemGetRefCount_DISPATCH(struct VirtualMemory *pResource) { return pResource->__virtmemGetRefCount__(pResource); } @@ -257,15 +263,15 @@ NV_STATUS virtmemConstruct_IMPL(struct VirtualMemory *arg_pVirtualMemory, CALL_C void virtmemDestruct_IMPL(struct VirtualMemory *pVirtualMemory); #define __nvoc_virtmemDestruct(pVirtualMemory) virtmemDestruct_IMPL(pVirtualMemory) -NV_STATUS virtmemReserveMempool_IMPL(struct VirtualMemory *pVirtualMemory, struct OBJGPU *arg0, NvHandle hDevice, NvU64 size, NvU64 pageSizeMask); +NV_STATUS virtmemReserveMempool_IMPL(struct VirtualMemory *pVirtualMemory, struct OBJGPU *arg0, struct Device *pDevice, NvU64 size, NvU64 pageSizeMask); #ifdef __nvoc_virtual_mem_h_disabled -static inline NV_STATUS virtmemReserveMempool(struct VirtualMemory *pVirtualMemory, struct OBJGPU *arg0, NvHandle hDevice, NvU64 size, NvU64 pageSizeMask) { +static inline NV_STATUS virtmemReserveMempool(struct VirtualMemory *pVirtualMemory, struct OBJGPU *arg0, struct Device *pDevice, NvU64 size, NvU64 pageSizeMask) { NV_ASSERT_FAILED_PRECOMP("VirtualMemory was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_virtual_mem_h_disabled -#define virtmemReserveMempool(pVirtualMemory, arg0, hDevice, size, pageSizeMask) virtmemReserveMempool_IMPL(pVirtualMemory, arg0, hDevice, size, pageSizeMask) +#define virtmemReserveMempool(pVirtualMemory, arg0, pDevice, size, pageSizeMask) virtmemReserveMempool_IMPL(pVirtualMemory, arg0, pDevice, size, pageSizeMask) #endif //__nvoc_virtual_mem_h_disabled NvBool virtmemMatchesVASpace_IMPL(struct VirtualMemory *pVirtualMemory, NvHandle hClient, NvHandle hVASpace); @@ -296,4 +302,5 @@ NV_STATUS virtmemAllocResources(OBJGPU *pGpu, struct MemoryManager *pMemoryManag #ifdef __cplusplus } // extern "C" #endif + #endif // _G_VIRTUAL_MEM_NVOC_H_ diff --git a/src/nvidia/generated/g_zbc_api_nvoc.h b/src/nvidia/generated/g_zbc_api_nvoc.h index 9100ba5614..858728ce53 100644 --- a/src/nvidia/generated/g_zbc_api_nvoc.h +++ b/src/nvidia/generated/g_zbc_api_nvoc.h @@ -327,4 +327,5 @@ static inline NV_STATUS __nvoc_zbcapiConstruct(struct ZbcApi *arg_pZbcApi, struc #ifdef __cplusplus } // extern "C" #endif + #endif // _G_ZBC_API_NVOC_H_ diff --git a/src/nvidia/generated/rmconfig.h b/src/nvidia/generated/rmconfig.h index 08f2679443..b9a9887041 100644 --- a/src/nvidia/generated/rmconfig.h +++ b/src/nvidia/generated/rmconfig.h @@ -31,6 +31,7 @@ #define RMCFG_CHIP_GA10XF 0 #define RMCFG_CHIP_AD10X 1 #define RMCFG_CHIP_GH10X 1 +#define RMCFG_CHIP_GH20X 0 #define RMCFG_CHIP_T12X 0 #define RMCFG_CHIP_T13X 0 #define RMCFG_CHIP_T21X 0 @@ -121,14 +122,15 @@ #define RMCFG_CHIP_GK110C 0 #define RMCFG_CHIP_GK208 0 #define RMCFG_CHIP_GK208S 0 +#define RMCFG_CHIP_GH202 0 #define RMCFG_CHIP_T001_FERMI_NOT_EXIST 0 #define RMCFG_CHIP_T124 0 #define RMCFG_CHIP_T132 0 #define RMCFG_CHIP_T210 0 #define RMCFG_CHIP_T186 0 #define RMCFG_CHIP_T002_TURING_NOT_EXIST 0 -#define RMCFG_CHIP_T003_HOPPER_NOT_EXIST 0 -#define RMCFG_CHIP_T004_ADA_NOT_EXIST 0 +#define RMCFG_CHIP_T003_ADA_NOT_EXIST 0 +#define RMCFG_CHIP_T004_HOPPER_NOT_EXIST 0 // @@ -179,6 +181,7 @@ #define RMCFG_CHIP_DHOPPER 1 #define RMCFG_CHIP_HOPPER 1 #define RMCFG_CHIP_HOPPER_CLASSIC_GPUS 1 +#define RMCFG_CHIP_TEGRA_DISP 0 #define RMCFG_CHIP_TEGRA_BIG_GPUS 0 #define RMCFG_CHIP_FERMI_TEGRA_BIG_GPUS 0 #define RMCFG_CHIP_TEGRA 0 @@ -197,17 +200,19 @@ #define RMCFG_CHIP_tVOLTA 0 #define RMCFG_CHIP_TVOLTA 0 #define RMCFG_CHIP_VOLTA_TEGRA_BIG_GPUS 0 +#define RMCFG_CHIP_TEGRA_DISP_TEGRA_BIG_GPUS 0 #define RMCFG_CHIP_TURING_TEGRA_BIG_GPUS 0 #define RMCFG_CHIP_T23X 0 #define RMCFG_CHIP_T23X_TEGRA_BIG_GPUS 0 #define RMCFG_CHIP_tAMPERE 0 #define RMCFG_CHIP_TAMPERE 0 #define RMCFG_CHIP_AMPERE_TEGRA_BIG_GPUS 0 -#define RMCFG_CHIP_HOPPER_TEGRA_BIG_GPUS 0 #define RMCFG_CHIP_ADA_TEGRA_BIG_GPUS 0 +#define RMCFG_CHIP_HOPPER_TEGRA_BIG_GPUS 0 #define RMCFG_CHIP_TEGRA_NVDISP_GPUS 0 #define RMCFG_CHIP_T23X_TEGRA_NVDISP_GPUS 0 #define RMCFG_CHIP_TEGRA_TEGRA_NVDISP_GPUS 0 +#define RMCFG_CHIP_TEGRA_DISP_TEGRA_NVDISP_GPUS 0 #define RMCFG_CHIP_ALL_TEGRA_NVDISP_GPUS 0 #define RMCFG_CHIP_ALL_CHIPS_TEGRA_NVDISP_GPUS 0 #define RMCFG_CHIP_SIMULATION_GPUS 0 @@ -244,7 +249,6 @@ #define RMCFG_FEATURE_KERNEL_RM 1 // Kernel layer of RM #define RMCFG_FEATURE_ORIN_PHYSICAL_RM 1 // Physical layer of RM, disabled only on Orin #define RMCFG_FEATURE_VGPU_GSP_PLUGIN_OFFLOAD 1 // vGPU GSP plugin offload -#define RMCFG_FEATURE_LIBOS_3_X 1 // Enable Libos-3.x feature #define RMCFG_FEATURE_SLINEXT 1 #define RMCFG_FEATURE_NOTEBOOK 1 // Notebook support #define RMCFG_FEATURE_EXTDEV 1 // Daughter boards connected to Quadro GPUs @@ -342,6 +346,7 @@ #define RMCFG_CLASS_NV01_MEMORY_LIST_OBJECT 1 #define RMCFG_CLASS_NV_IMEX_SESSION 0 #define RMCFG_CLASS_NV01_MEMORY_FLA 1 +#define RMCFG_CLASS_NV_MEMORY_EXPORT 0 #define RMCFG_CLASS_NV_MEMORY_FABRIC_EXPORT_V2 0 #define RMCFG_CLASS_NV_CE_UTILS 1 #define RMCFG_CLASS_NV_MEMORY_FABRIC 1 @@ -350,6 +355,7 @@ #define RMCFG_CLASS_NV_MEMORY_FABRIC_IMPORTED_REF 0 #define RMCFG_CLASS_FABRIC_VASPACE_A 1 #define RMCFG_CLASS_NV_MEMORY_MULTICAST_FABRIC 1 +#define RMCFG_CLASS_NV_FB_SEGMENT 0 #define RMCFG_CLASS_IO_VASPACE_A 1 #define RMCFG_CLASS_NV01_NULL 1 #define RMCFG_CLASS_NV1_NULL 1 // aka NV01_NULL @@ -370,7 +376,9 @@ #define RMCFG_CLASS_GF100_CHANNEL_GPFIFO 1 #define RMCFG_CLASS_KEPLER_CHANNEL_GPFIFO_A 1 #define RMCFG_CLASS_UVM_CHANNEL_RETAINER 1 +#define RMCFG_CLASS_PHYSICAL_CHANNEL_GPFIFO 0 #define RMCFG_CLASS_KEPLER_CHANNEL_GPFIFO_B 1 +#define RMCFG_CLASS_KEPLER_CHANNEL_GPFIFO_C 0 #define RMCFG_CLASS_MAXWELL_CHANNEL_GPFIFO_A 1 #define RMCFG_CLASS_PASCAL_CHANNEL_GPFIFO_A 1 #define RMCFG_CLASS_VOLTA_CHANNEL_GPFIFO_A 1 @@ -380,18 +388,39 @@ #define RMCFG_CLASS_NV04_SOFTWARE_TEST 1 #define RMCFG_CLASS_NV4_SOFTWARE_TEST 1 // aka NV04_SOFTWARE_TEST #define RMCFG_CLASS_NV30_GSYNC 1 +#define RMCFG_CLASS_NV50_DISPLAY 0 +#define RMCFG_CLASS_NV9470_DISPLAY 0 +#define RMCFG_CLASS_NV9471_DISP_SF_USER 0 +#define RMCFG_CLASS_NV9570_DISPLAY 0 +#define RMCFG_CLASS_NV9571_DISP_SF_USER 0 +#define RMCFG_CLASS_NV9770_DISPLAY 0 +#define RMCFG_CLASS_NV9870_DISPLAY 0 #define RMCFG_CLASS_VOLTA_USERMODE_A 1 #define RMCFG_CLASS_TURING_USERMODE_A 1 #define RMCFG_CLASS_AMPERE_USERMODE_A 1 #define RMCFG_CLASS_HOPPER_USERMODE_A 1 +#define RMCFG_CLASS_NVC370_DISPLAY 0 #define RMCFG_CLASS_NVC371_DISP_SF_USER 1 #define RMCFG_CLASS_NVC372_DISPLAY_SW 1 +#define RMCFG_CLASS_NVC373_DISP_CAPABILITIES 0 #define RMCFG_CLASS_NVC573_DISP_CAPABILITIES 1 #define RMCFG_CLASS_NVC673_DISP_CAPABILITIES 1 #define RMCFG_CLASS_NVC773_DISP_CAPABILITIES 1 #define RMCFG_CLASS_NV04_DISPLAY_COMMON 1 #define RMCFG_CLASS_NV50_DEFERRED_API_CLASS 1 #define RMCFG_CLASS_MPS_COMPUTE 1 +#define RMCFG_CLASS_NV917A_CURSOR_CHANNEL_PIO 0 +#define RMCFG_CLASS_NV917B_OVERLAY_IMM_CHANNEL_PIO 0 +#define RMCFG_CLASS_NV917E_OVERLAY_CHANNEL_DMA 0 +#define RMCFG_CLASS_NV927C_BASE_CHANNEL_DMA 0 +#define RMCFG_CLASS_NV947D_CORE_CHANNEL_DMA 0 +#define RMCFG_CLASS_NV957D_CORE_CHANNEL_DMA 0 +#define RMCFG_CLASS_NV977D_CORE_CHANNEL_DMA 0 +#define RMCFG_CLASS_NV987D_CORE_CHANNEL_DMA 0 +#define RMCFG_CLASS_NVC37A_CURSOR_IMM_CHANNEL_PIO 0 +#define RMCFG_CLASS_NVC37B_WINDOW_IMM_CHANNEL_DMA 0 +#define RMCFG_CLASS_NVC37D_CORE_CHANNEL_DMA 0 +#define RMCFG_CLASS_NVC37E_WINDOW_CHANNEL_DMA 0 #define RMCFG_CLASS_NVC570_DISPLAY 1 #define RMCFG_CLASS_NVC57A_CURSOR_IMM_CHANNEL_PIO 1 #define RMCFG_CLASS_NVC57B_WINDOW_IMM_CHANNEL_DMA 1 @@ -412,6 +441,8 @@ #define RMCFG_CLASS_MAXWELL_PROFILER 1 // Base Profiler Class #define RMCFG_CLASS_MAXWELL_PROFILER_DEVICE 1 // Device level Profiler Client Support #define RMCFG_CLASS_GF100_SUBDEVICE_MASTER 1 +#define RMCFG_CLASS_GF100_SUBDEVICE_INFOROM 1 // Inforom interface +#define RMCFG_CLASS_TURING_VMMU_A 0 #define RMCFG_CLASS_GF100_ZBC_CLEAR 1 #define RMCFG_CLASS_GF100_DISP_SW 1 #define RMCFG_CLASS_GF100_TIMED_SEMAPHORE_SW 1 @@ -423,11 +454,22 @@ #define RMCFG_CLASS_FERMI_VASPACE_A 1 // FERMI virtual address space #define RMCFG_CLASS_HOPPER_SEC2_WORK_LAUNCH_A 1 // Confidential Computing Work Launch #define RMCFG_CLASS_GF100_HDACODEC 1 +#define RMCFG_CLASS_NVA0B0_VIDEO_DECODER 0 // Combined MSVLD, MSPPP, MSPDEC (Maxwell) +#define RMCFG_CLASS_NVB0B0_VIDEO_DECODER 0 // Decoder Class for GM20X +#define RMCFG_CLASS_NVB6B0_VIDEO_DECODER 0 // Decoder Class for GM206 #define RMCFG_CLASS_NVB8B0_VIDEO_DECODER 1 // Decoder Class for Hopper +#define RMCFG_CLASS_NVC1B0_VIDEO_DECODER 0 // Decoder Class for Pascal +#define RMCFG_CLASS_NVC2B0_VIDEO_DECODER 0 // Decoder Class for Pascal +#define RMCFG_CLASS_NVC3B0_VIDEO_DECODER 0 // Decoder Class for Volta #define RMCFG_CLASS_NVC4B0_VIDEO_DECODER 1 // Decoder Class for Turing #define RMCFG_CLASS_NVC6B0_VIDEO_DECODER 1 // Decoder Class for Ampere #define RMCFG_CLASS_NVC7B0_VIDEO_DECODER 1 // Decoder Class for Ampere #define RMCFG_CLASS_NVC9B0_VIDEO_DECODER 1 // Decoder Class for Ada +#define RMCFG_CLASS_NVC0B7_VIDEO_ENCODER 0 +#define RMCFG_CLASS_NVD0B7_VIDEO_ENCODER 0 +#define RMCFG_CLASS_NVC1B7_VIDEO_ENCODER 0 +#define RMCFG_CLASS_NVC2B7_VIDEO_ENCODER 0 +#define RMCFG_CLASS_NVC3B7_VIDEO_ENCODER 0 #define RMCFG_CLASS_NVC4B7_VIDEO_ENCODER 1 #define RMCFG_CLASS_NVB4B7_VIDEO_ENCODER 1 #define RMCFG_CLASS_NVC7B7_VIDEO_ENCODER 1 @@ -442,15 +484,28 @@ #define RMCFG_CLASS_KEPLER_INLINE_TO_MEMORY_B 1 // Kepler inline to memory #define RMCFG_CLASS_FERMI_CONTEXT_SHARE_A 1 // Context Share class #define RMCFG_CLASS_KEPLER_CHANNEL_GROUP_A 1 // Channel Group Class +#define RMCFG_CLASS_MAXWELL_A 0 // Maxwell Graphics +#define RMCFG_CLASS_MAXWELL_COMPUTE_A 0 // Maxwell Graphics Compute +#define RMCFG_CLASS_MAXWELL_B 0 // Maxwell Graphics second generation +#define RMCFG_CLASS_MAXWELL_COMPUTE_B 0 // Maxwell Graphics Compute +#define RMCFG_CLASS_PASCAL_A 0 // Pascal Graphics +#define RMCFG_CLASS_PASCAL_COMPUTE_A 0 // Pascal Graphics Compute #define RMCFG_CLASS_PASCAL_DMA_COPY_A 1 +#define RMCFG_CLASS_PASCAL_DMA_COPY_B 0 +#define RMCFG_CLASS_VOLTA_DMA_COPY_A 0 #define RMCFG_CLASS_TURING_DMA_COPY_A 1 #define RMCFG_CLASS_AMPERE_DMA_COPY_A 1 #define RMCFG_CLASS_AMPERE_DMA_COPY_B 1 #define RMCFG_CLASS_HOPPER_DMA_COPY_A 1 #define RMCFG_CLASS_MAXWELL_DMA_COPY_A 1 +#define RMCFG_CLASS_MAXWELL_FAULT_BUFFER_A 0 // Maxwell Fault Buffer for Gr #define RMCFG_CLASS_ACCESS_COUNTER_NOTIFY_BUFFER 1 // Access Cntr Buffer for Gr #define RMCFG_CLASS_MMU_FAULT_BUFFER 1 // Volta Fault Buffer for Gr #define RMCFG_CLASS_MMU_VIDMEM_ACCESS_BIT_BUFFER 1 // Ampere Vidmem Access Bit Buffer +#define RMCFG_CLASS_PASCAL_B 0 // Pascal Graphics 2nd Gen +#define RMCFG_CLASS_PASCAL_COMPUTE_B 0 // Pascal Graphics Compute 2nd Gen +#define RMCFG_CLASS_VOLTA_A 0 // Volta Graphics +#define RMCFG_CLASS_VOLTA_COMPUTE_A 0 // Volta Graphics Compute #define RMCFG_CLASS_TURING_A 1 // Turing Graphics #define RMCFG_CLASS_TURING_COMPUTE_A 1 // Turing Graphics Compute #define RMCFG_CLASS_AMPERE_A 1 // AmpereA (Graphics) @@ -520,6 +575,7 @@ #define RMCFG_MODULE_SCHED 0 // Scheduler for runlist #define RMCFG_MODULE_FLCN 0 // Falcon-derived engines #define RMCFG_MODULE_KERNEL_FALCON 1 // Falcon on Kernel(CPU) RM. Used for booting Falcon cores. +#define RMCFG_MODULE_KERNEL_VIDEO_ENGINE 1 // Kernel Video Engine. Object to manage video engines (NVJPG, encoders, decoders, etc.) on Kernel RM #define RMCFG_MODULE_GR 0 // Graphic #define RMCFG_MODULE_GR0 0 // aka GR #define RMCFG_MODULE_KERNEL_GRAPHICS 1 // Graphic on Kernel(CPU) RM @@ -611,7 +667,6 @@ #define RMCFG_MODULE_TMDS 0 // Display component: Transition Minimized Differential Signaling #define RMCFG_MODULE_CL 1 // Core Logic #define RMCFG_MODULE_RCDB 1 // RC Journal log DB -#define RMCFG_MODULE_SWINSTR 0 // Software Instrumentation #define RMCFG_MODULE_GPUACCT 1 // GPU Accounting #define RMCFG_MODULE_GRDBG 0 // Debugger Engine Object #define RMCFG_MODULE_PSR 0 // Panel Self Refresh diff --git a/src/nvidia/inc/kernel/core/locks.h b/src/nvidia/inc/kernel/core/locks.h index 7e6948f409..e39dedda7a 100644 --- a/src/nvidia/inc/kernel/core/locks.h +++ b/src/nvidia/inc/kernel/core/locks.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -28,6 +28,7 @@ // Forward declarations typedef struct OBJSYS OBJSYS; +typedef struct NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS; typedef enum { @@ -161,6 +162,7 @@ NvBool rmGpuLockIsOwner(void); NvU32 rmGpuLocksGetOwnedMask(void); NvBool rmGpuLockIsHidden(OBJGPU *); NV_STATUS rmGpuLockSetOwner(OS_THREAD_HANDLE); +void rmGpuLockGetTimes(NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS *); NV_STATUS rmGpuGroupLockAcquire(NvU32, GPU_LOCK_GRP_ID, NvU32, NvU32, GPU_MASK *); NV_STATUS rmGpuGroupLockRelease(GPU_MASK, NvU32); NvBool rmGpuGroupLockIsOwner(NvU32, GPU_LOCK_GRP_ID, GPU_MASK*); diff --git a/src/nvidia/inc/kernel/core/printf.h b/src/nvidia/inc/kernel/core/printf.h index 96846c77a4..36168ae378 100644 --- a/src/nvidia/inc/kernel/core/printf.h +++ b/src/nvidia/inc/kernel/core/printf.h @@ -56,7 +56,7 @@ extern "C" { // NV_DBG_BREAKPOINT_ALLOWED can be overridden through CFLAGS #if !defined(NV_DBG_BREAKPOINT_ALLOWED) -#if defined(DEBUG) || defined(ASSERT_BUILD) || defined(NV_MODS) || defined(QA_BUILD) || (defined(NVRM) && NVCPU_IS_RISCV64) +#if defined(DEBUG) || defined(ASSERT_BUILD) || defined(NV_MODS) || defined(QA_BUILD) || (defined(NVRM) && NVOS_IS_LIBOS) #define NV_DBG_BREAKPOINT_ALLOWED 1 #else #define NV_DBG_BREAKPOINT_ALLOWED 0 @@ -116,7 +116,7 @@ void osFlushLog(void); #if NV_DBG_BREAKPOINT_ALLOWED -#if !NVCPU_IS_RISCV64 +#if !NVOS_IS_LIBOS #define DBG_BREAKPOINT_EX(PGPU, LEVEL) \ do \ @@ -126,7 +126,7 @@ void osFlushLog(void); DBG_ROUTINE(); \ } while (0) -#else // !NVCPU_IS_RISCV64 +#else // !NVOS_IS_LIBOS #define DBG_BREAKPOINT_EX(PGPU, LEVEL) \ do \ @@ -134,7 +134,7 @@ void osFlushLog(void); NV_ASSERT_FAILED("DBG_BREAKPOINT"); \ } while (0) -#endif // !NVCPU_IS_RISCV64 +#endif // !NVOS_IS_LIBOS #define DBG_BREAKPOINT() DBG_BREAKPOINT_EX(NULL, 0) diff --git a/src/nvidia/inc/kernel/core/thread_state.h b/src/nvidia/inc/kernel/core/thread_state.h index 27d0880a95..f5dc1c3452 100644 --- a/src/nvidia/inc/kernel/core/thread_state.h +++ b/src/nvidia/inc/kernel/core/thread_state.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -132,6 +132,10 @@ typedef struct THREAD_STATE_DB * sequencer id via @ref threadStateInitXYZ(). */ NvU32 threadSeqCntr; + /*! + * Thread state sequencer id counter for only GSP task_interrupt. + */ + NvU32 gspIsrThreadSeqCntr; PORT_SPINLOCK *spinlock; ThreadStateNodeMap dbRoot; ThreadStateNodeMap dbRootPreempted; diff --git a/src/nvidia/inc/kernel/gpu/ce/kernel_ce_shared.h b/src/nvidia/inc/kernel/gpu/ce/kernel_ce_shared.h index fdabac4afe..355c2ae71b 100644 --- a/src/nvidia/inc/kernel/gpu/ce/kernel_ce_shared.h +++ b/src/nvidia/inc/kernel/gpu/ce/kernel_ce_shared.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -30,7 +30,7 @@ * Routines shared between CE and KCE. */ -NvBool ceIsCeGrce(OBJGPU *pGpu, NvU32 ceEngineType); +NvBool ceIsCeGrce(OBJGPU *pGpu, RM_ENGINE_TYPE ceEngineType); NvU32 ceCountGrCe(OBJGPU *pGpu); #endif diff --git a/src/nvidia/inc/kernel/gpu/disp/kern_disp_max.h b/src/nvidia/inc/kernel/gpu/disp/kern_disp_max.h index 649c97976a..65eedadbbc 100644 --- a/src/nvidia/inc/kernel/gpu/disp/kern_disp_max.h +++ b/src/nvidia/inc/kernel/gpu/disp/kern_disp_max.h @@ -28,8 +28,7 @@ * @brief Defines max values used for the KernelDisplay Engine Object, * including values shared by OBJDISP code. */ - -#define OBJ_MAX_HEADS 4 +#define OBJ_MAX_HEADS 8 #define MAX_RG_LINE_CALLBACKS_PER_HEAD 2 #define OBJ_MAX_DFPS 31 diff --git a/src/nvidia/inc/kernel/gpu/fifo/engine_info.h b/src/nvidia/inc/kernel/gpu/fifo/engine_info.h new file mode 100644 index 0000000000..ef086a8e05 --- /dev/null +++ b/src/nvidia/inc/kernel/gpu/fifo/engine_info.h @@ -0,0 +1,117 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _ENGINE_INFO_H_ +#define _ENGINE_INFO_H_ + +typedef enum +{ + /* ************************************************************************* + * Bug 3820969 + * THINK BEFORE CHANGING ENUM ORDER HERE. + * VGPU-guest uses this same ordering. Because this enum is not versioned, + * changing the order here WILL BREAK old-guest-on-newer-host compatibility. + * ************************************************************************/ + + // *ENG_XYZ, e.g.: ENG_GR, ENG_CE etc., + ENGINE_INFO_TYPE_ENG_DESC = 0, + + // HW engine ID + ENGINE_INFO_TYPE_FIFO_TAG, + + // RM_ENGINE_TYPE_* + ENGINE_INFO_TYPE_RM_ENGINE_TYPE, + + // + // runlist id (meaning varies by GPU) + // Valid only for Esched-driven engines + // + ENGINE_INFO_TYPE_RUNLIST, + + // NV_PFIFO_INTR_MMU_FAULT_ENG_ID_* + ENGINE_INFO_TYPE_MMU_FAULT_ID, + + // ROBUST_CHANNEL_* + ENGINE_INFO_TYPE_RC_MASK, + + // Reset Bit Position. On Ampere, only valid if not _INVALID + ENGINE_INFO_TYPE_RESET, + + // Interrupt Bit Position + ENGINE_INFO_TYPE_INTR, + + // log2(MC_ENGINE_*) + ENGINE_INFO_TYPE_MC, + + // The DEV_TYPE_ENUM for this engine + ENGINE_INFO_TYPE_DEV_TYPE_ENUM, + + // The particular instance of this engine type + ENGINE_INFO_TYPE_INSTANCE_ID, + + // + // The base address for this engine's NV_RUNLIST. Valid only on Ampere+ + // Valid only for Esched-driven engines + // + ENGINE_INFO_TYPE_RUNLIST_PRI_BASE, + + // + // If this entry is a host-driven engine. + // Update _isEngineInfoTypeValidForOnlyHostDriven when adding any new entry. + // + ENGINE_INFO_TYPE_IS_HOST_DRIVEN_ENGINE, + + // + // The index into the per-engine NV_RUNLIST registers. Valid only on Ampere+ + // Valid only for Esched-driven engines + // + ENGINE_INFO_TYPE_RUNLIST_ENGINE_ID, + + // + // The base address for this engine's NV_CHRAM registers. Valid only on + // Ampere+ + // + // Valid only for Esched-driven engines + // + ENGINE_INFO_TYPE_CHRAM_PRI_BASE, + + // This entry added to copy data at RMCTRL_EXPORT() call for Kernel RM + ENGINE_INFO_TYPE_KERNEL_RM_MAX, + // Used for iterating the engine info table by the index passed. + ENGINE_INFO_TYPE_INVALID = ENGINE_INFO_TYPE_KERNEL_RM_MAX, + + // Size of FIFO_ENGINE_LIST.engineData + ENGINE_INFO_TYPE_ENGINE_DATA_ARRAY_SIZE = ENGINE_INFO_TYPE_INVALID, + + // Input-only parameter for kfifoEngineInfoXlate. + ENGINE_INFO_TYPE_PBDMA_ID + + /* ************************************************************************* + * Bug 3820969 + * THINK BEFORE CHANGING ENUM ORDER HERE. + * VGPU-guest uses this same ordering. Because this enum is not versioned, + * changing the order here WILL BREAK old-guest-on-newer-host compatibility. + * ************************************************************************/ +} ENGINE_INFO_TYPE; + +#endif // _ENGINE_INFO_H_ diff --git a/src/nvidia/inc/kernel/gpu/gpu_child_list.h b/src/nvidia/inc/kernel/gpu/gpu_child_list.h index 13ac242d72..1eed847071 100644 --- a/src/nvidia/inc/kernel/gpu/gpu_child_list.h +++ b/src/nvidia/inc/kernel/gpu/gpu_child_list.h @@ -295,7 +295,7 @@ GPU_CHILD_SINGLE_INST( KernelFsp, GPU_GET_KERNEL_FSP, 1, NV_FALSE, pKernelFsp ) #endif #if GPU_CHILD_MODULE(OFA) - GPU_CHILD_SINGLE_INST( OBJOFA, GPU_GET_OFA, 1, NV_FALSE, pOfa ) + GPU_CHILD_MULTI_INST( OBJOFA, GPU_GET_OFA, GPU_MAX_OFAS, NV_FALSE, pOfa ) #endif #if RMCFG_MODULE_CONF_COMPUTE && GPU_CHILD_MODULE(CONF_COMPUTE) GPU_CHILD_SINGLE_INST( ConfidentialCompute, GPU_GET_CONF_COMPUTE, 1, NV_TRUE, pConfCompute ) diff --git a/src/nvidia/inc/kernel/gpu/gpu_engine_type.h b/src/nvidia/inc/kernel/gpu/gpu_engine_type.h index 39030a8280..441f8fef96 100644 --- a/src/nvidia/inc/kernel/gpu/gpu_engine_type.h +++ b/src/nvidia/inc/kernel/gpu/gpu_engine_type.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -27,6 +27,7 @@ #include "class/cl2080.h" #include "nvrangetypes.h" #include "utils/nvbitvector.h" +#include "rmconfig.h" typedef enum { @@ -49,6 +50,16 @@ typedef enum RM_ENGINE_TYPE_COPY7 = (0x00000010), RM_ENGINE_TYPE_COPY8 = (0x00000011), RM_ENGINE_TYPE_COPY9 = (0x00000012), + RM_ENGINE_TYPE_RESERVED13 = (0x00000013), + RM_ENGINE_TYPE_RESERVED14 = (0x00000014), + RM_ENGINE_TYPE_RESERVED15 = (0x00000015), + RM_ENGINE_TYPE_RESERVED16 = (0x00000016), + RM_ENGINE_TYPE_RESERVED17 = (0x00000017), + RM_ENGINE_TYPE_RESERVED18 = (0x00000018), + RM_ENGINE_TYPE_RESERVED19 = (0x00000019), + RM_ENGINE_TYPE_RESERVED1a = (0x0000001a), + RM_ENGINE_TYPE_RESERVED1b = (0x0000001b), + RM_ENGINE_TYPE_RESERVED1c = (0x0000001c), RM_ENGINE_TYPE_NVDEC0 = (0x0000001d), RM_ENGINE_TYPE_NVDEC1 = (0x0000001e), RM_ENGINE_TYPE_NVDEC2 = (0x0000001f), @@ -81,8 +92,9 @@ typedef enum RM_ENGINE_TYPE_NVJPEG5 = (0x0000003a), RM_ENGINE_TYPE_NVJPEG6 = (0x0000003b), RM_ENGINE_TYPE_NVJPEG7 = (0x0000003c), - RM_ENGINE_TYPE_OFA = (0x0000003d), - RM_ENGINE_TYPE_LAST = (0x0000003e), + RM_ENGINE_TYPE_OFA0 = (0x0000003d), + RM_ENGINE_TYPE_RESERVED3e = (0x0000003e), + RM_ENGINE_TYPE_LAST = (0x0000003f), } RM_ENGINE_TYPE; // @@ -119,9 +131,9 @@ typedef enum #define RM_ENGINE_TYPE_IS_NVJPEG(i) (((i) >= RM_ENGINE_TYPE_NVJPEG0) && ((i) < RM_ENGINE_TYPE_NVJPEG(RM_ENGINE_TYPE_NVJPEG_SIZE))) #define RM_ENGINE_TYPE_NVJPEG_IDX(i) ((i) - RM_ENGINE_TYPE_NVJPEG0) -#define RM_ENGINE_TYPE_OFA(i) (RM_ENGINE_TYPE_OFA+(i)) -#define RM_ENGINE_TYPE_IS_OFA(i) (((i) >= RM_ENGINE_TYPE_OFA) && ((i) < RM_ENGINE_TYPE_OFA(RM_ENGINE_TYPE_OFA_SIZE))) -#define RM_ENGINE_TYPE_OFA_IDX(i) ((i) - RM_ENGINE_TYPE_OFA) +#define RM_ENGINE_TYPE_OFA(i) (RM_ENGINE_TYPE_OFA0+(i)) +#define RM_ENGINE_TYPE_IS_OFA(i) (((i) >= RM_ENGINE_TYPE_OFA0) && ((i) < RM_ENGINE_TYPE_OFA(RM_ENGINE_TYPE_OFA_SIZE))) +#define RM_ENGINE_TYPE_OFA_IDX(i) ((i) - RM_ENGINE_TYPE_OFA0) #define RM_ENGINE_TYPE_IS_VIDEO(i) (RM_ENGINE_TYPE_IS_NVENC(i) | \ RM_ENGINE_TYPE_IS_NVDEC(i) | \ @@ -140,6 +152,7 @@ typedef enum #define RM_ENGINE_RANGE_NVDEC() rangeMake(RM_ENGINE_TYPE_NVDEC(0), RM_ENGINE_TYPE_NVDEC(RM_ENGINE_TYPE_NVDEC_SIZE - 1)) #define RM_ENGINE_RANGE_NVENC() rangeMake(RM_ENGINE_TYPE_NVENC(0), RM_ENGINE_TYPE_NVENC(RM_ENGINE_TYPE_NVENC_SIZE - 1)) #define RM_ENGINE_RANGE_NVJPEG() rangeMake(RM_ENGINE_TYPE_NVJPEG(0), RM_ENGINE_TYPE_NVJPEG(RM_ENGINE_TYPE_NVJPEG_SIZE - 1)) +#define RM_ENGINE_RANGE_OFA() rangeMake(RM_ENGINE_TYPE_OFA(0), RM_ENGINE_TYPE_OFA(RM_ENGINE_TYPE_OFA_SIZE - 1)) // Bit Vectors MAKE_BITVECTOR(ENGTYPE_BIT_VECTOR, RM_ENGINE_TYPE_LAST); diff --git a/src/nvidia/inc/kernel/gpu/gpu_fabric_probe.h b/src/nvidia/inc/kernel/gpu/gpu_fabric_probe.h index 79642b3ee8..54e83a0e18 100644 --- a/src/nvidia/inc/kernel/gpu/gpu_fabric_probe.h +++ b/src/nvidia/inc/kernel/gpu/gpu_fabric_probe.h @@ -52,6 +52,7 @@ NV_STATUS gpuFabricProbeGetGpaAddressRange(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NV_STATUS gpuFabricProbeGetFlaAddress(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU64 *pFlaAddress); NV_STATUS gpuFabricProbeGetFlaAddressRange(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU64 *pFlaAddressRange); NV_STATUS gpuFabricProbeGetNumProbeReqs(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU64 *numProbes); +NV_STATUS gpuFabricProbeGetFabricCliqueId(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU32 *pFabricCliqueId); NvBool gpuFabricProbeIsReceived(GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel); NvBool gpuFabricProbeIsSuccess(GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel); diff --git a/src/nvidia/inc/kernel/gpu/gpu_shared_data_map.h b/src/nvidia/inc/kernel/gpu/gpu_shared_data_map.h index dbafe28af6..f1482408ff 100644 --- a/src/nvidia/inc/kernel/gpu/gpu_shared_data_map.h +++ b/src/nvidia/inc/kernel/gpu/gpu_shared_data_map.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -28,22 +28,29 @@ #include "gpu/mem_mgr/mem_desc.h" #include "class/cl00de.h" +#include "tmr.h" + // **************************************************************************** // Type definitions // **************************************************************************** +typedef struct RusdQueryCache RUSD_QUERY_CACHE; typedef struct GpuSharedDataMap { MEMORY_DESCRIPTOR *pMemDesc; NvP64 pMapBuffer; NvP64 pMapBufferPriv; + NvU64 lastPolledDataMask; NvU32 processId; + TMR_EVENT *pRusdRefreshTmrEvent; + NV00DE_SHARED_DATA data; -} GpuSharedDataMap; -typedef struct GspUserSharedData { - NvU32 gspAssertCount; -} GspUserSharedData; + // Private data to assist metrics query + RUSD_QUERY_CACHE *pRusdQueryCache; + NvU8 curGroup; + NvBool bWorkItemPending; +} GpuSharedDataMap; /** * Start data write, returns data struct to write into @@ -52,8 +59,12 @@ typedef struct GspUserSharedData { * call gpushareddataWriteFinish to push the new data into the user mapping */ NV00DE_SHARED_DATA * gpushareddataWriteStart(OBJGPU *pGpu); + // Finish data write, pushes data cached by above into mapped data void gpushareddataWriteFinish(OBJGPU *pGpu); +// Unmap and free memory in GpuSharedDataMap +void gpushareddataDestroy(OBJGPU *pGpu); + #endif /* GPU_SHARED_DATA_MAP_H */ diff --git a/src/nvidia/inc/kernel/gpu/gsp/gsp_fw_heap.h b/src/nvidia/inc/kernel/gpu/gsp/gsp_fw_heap.h index 57538db5af..d561fb109e 100644 --- a/src/nvidia/inc/kernel/gpu/gsp/gsp_fw_heap.h +++ b/src/nvidia/inc/kernel/gpu/gsp/gsp_fw_heap.h @@ -24,9 +24,13 @@ #ifndef GSP_FW_HEAP_H #define GSP_FW_HEAP_H +#include "rmconfig.h" + + // Static defines for the GSP FW WPR Heap #define GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS2 (0 << 20) // No FB heap usage -#define GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS3 (20 << 20) +#define GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS3_BAREMETAL (22 << 20) +#define GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS3_VGPU (36 << 20) // // Calibrated by observing RM init heap usage - the amount of GSP-RM heap memory @@ -64,16 +68,18 @@ // #define GSP_FW_HEAP_PARAM_CLIENT_ALLOC_SIZE ((48 << 10) * 2048) // Support 2048 channels -#define GSP_FW_HEAP_SIZE_VGPU_DEFAULT (549 << 20) // Default for all VGPU configs +#define GSP_FW_HEAP_SIZE_VGPU_DEFAULT (565 << 20) // Default for all VGPU configs + + // Min/max bounds for heap size override by regkey #define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS2_MIN_MB (64u) #define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS2_MAX_MB (256u) -#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MIN_MB (84u) -#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MAX_MB (276u) +#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MIN_MB (86u) +#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MAX_MB (278u) -#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_VGPU_MIN_MB (549u) -#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_VGPU_MAX_MB (1024u) +#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_VGPU_MIN_MB (565u) +#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_VGPU_MAX_MB (1040u) #endif // GSP_FW_HEAP_H diff --git a/src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h b/src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h index 86f2807765..6632ed1636 100644 --- a/src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h +++ b/src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h @@ -164,6 +164,8 @@ typedef struct GspSystemInfo NvU64 clPdbProperties; NvU32 Chipset; NvBool bGpuBehindBridge; + NvBool bFlrSupported; + NvBool b64bBar0Supported; NvBool bMnocAvailable; NvBool bUpstreamL0sUnsupported; NvBool bUpstreamL1Unsupported; diff --git a/src/nvidia/inc/kernel/gpu/intr/engine_idx.h b/src/nvidia/inc/kernel/gpu/intr/engine_idx.h index f8e1e5b3c2..464549e001 100644 --- a/src/nvidia/inc/kernel/gpu/intr/engine_idx.h +++ b/src/nvidia/inc/kernel/gpu/intr/engine_idx.h @@ -62,12 +62,22 @@ #define MC_ENGINE_IDX_CE8 23 #define MC_ENGINE_IDX_CE9 24 #define MC_ENGINE_IDX_CE_MAX MC_ENGINE_IDX_CE9 +#define MC_ENGINE_IDX_RESERVED25 25 +#define MC_ENGINE_IDX_RESERVED26 26 +#define MC_ENGINE_IDX_RESERVED27 27 +#define MC_ENGINE_IDX_RESERVED28 28 +#define MC_ENGINE_IDX_RESERVED29 29 +#define MC_ENGINE_IDX_RESERVED30 30 +#define MC_ENGINE_IDX_RESERVED31 31 +#define MC_ENGINE_IDX_RESERVED32 32 +#define MC_ENGINE_IDX_RESERVED33 33 +#define MC_ENGINE_IDX_RESERVED34 34 #define MC_ENGINE_IDX_VIC 35 #define MC_ENGINE_IDX_ISOHUB 36 #define MC_ENGINE_IDX_VGPU 37 -#define MC_ENGINE_IDX_MSENC 38 -#define MC_ENGINE_IDX_MSENC1 39 -#define MC_ENGINE_IDX_MSENC2 40 +#define MC_ENGINE_IDX_NVENC 38 +#define MC_ENGINE_IDX_NVENC1 39 +#define MC_ENGINE_IDX_NVENC2 40 #define MC_ENGINE_IDX_C2C 41 #define MC_ENGINE_IDX_LTC 42 #define MC_ENGINE_IDX_FBHUB 43 @@ -112,35 +122,35 @@ #define MC_ENGINE_IDX_XBAR 78 #define MC_ENGINE_IDX_ZPW 79 #define MC_ENGINE_IDX_OFA0 80 -#define MC_ENGINE_IDX_TEGRA 81 -#define MC_ENGINE_IDX_GR 82 +#define MC_ENGINE_IDX_RESERVED81 81 +#define MC_ENGINE_IDX_TEGRA 82 +#define MC_ENGINE_IDX_GR 83 #define MC_ENGINE_IDX_GR0 MC_ENGINE_IDX_GR -#define MC_ENGINE_IDX_GR1 83 -#define MC_ENGINE_IDX_GR2 84 -#define MC_ENGINE_IDX_GR3 85 -#define MC_ENGINE_IDX_GR4 86 -#define MC_ENGINE_IDX_GR5 87 -#define MC_ENGINE_IDX_GR6 88 -#define MC_ENGINE_IDX_GR7 89 -#define MC_ENGINE_IDX_ESCHED 90 +#define MC_ENGINE_IDX_GR1 84 +#define MC_ENGINE_IDX_GR2 85 +#define MC_ENGINE_IDX_GR3 86 +#define MC_ENGINE_IDX_GR4 87 +#define MC_ENGINE_IDX_GR5 88 +#define MC_ENGINE_IDX_GR6 89 +#define MC_ENGINE_IDX_GR7 90 +#define MC_ENGINE_IDX_ESCHED 91 #define MC_ENGINE_IDX_ESCHED__SIZE 64 -#define MC_ENGINE_IDX_GR_FECS_LOG 154 +#define MC_ENGINE_IDX_GR_FECS_LOG 155 #define MC_ENGINE_IDX_GR0_FECS_LOG MC_ENGINE_IDX_GR_FECS_LOG -#define MC_ENGINE_IDX_GR1_FECS_LOG 155 -#define MC_ENGINE_IDX_GR2_FECS_LOG 156 -#define MC_ENGINE_IDX_GR3_FECS_LOG 157 -#define MC_ENGINE_IDX_GR4_FECS_LOG 158 -#define MC_ENGINE_IDX_GR5_FECS_LOG 159 -#define MC_ENGINE_IDX_GR6_FECS_LOG 160 -#define MC_ENGINE_IDX_GR7_FECS_LOG 161 -#define MC_ENGINE_IDX_TMR_SWRL 162 -#define MC_ENGINE_IDX_DISP_GSP 163 -#define MC_ENGINE_IDX_REPLAYABLE_FAULT_CPU 164 -#define MC_ENGINE_IDX_NON_REPLAYABLE_FAULT_CPU 165 -#define MC_ENGINE_IDX_PXUC 166 -#define MC_ENGINE_IDX_MAX 167 // This must be kept as the max bit if - // we need to add more engines -#define MC_ENGINE_IDX_INVALID 0xFFFFFFFF +#define MC_ENGINE_IDX_GR1_FECS_LOG 156 +#define MC_ENGINE_IDX_GR2_FECS_LOG 157 +#define MC_ENGINE_IDX_GR3_FECS_LOG 158 +#define MC_ENGINE_IDX_GR4_FECS_LOG 159 +#define MC_ENGINE_IDX_GR5_FECS_LOG 160 +#define MC_ENGINE_IDX_GR6_FECS_LOG 161 +#define MC_ENGINE_IDX_GR7_FECS_LOG 162 +#define MC_ENGINE_IDX_TMR_SWRL 163 +#define MC_ENGINE_IDX_DISP_GSP 164 +#define MC_ENGINE_IDX_REPLAYABLE_FAULT_CPU 165 +#define MC_ENGINE_IDX_NON_REPLAYABLE_FAULT_CPU 166 +#define MC_ENGINE_IDX_PXUC 167 +// This must be kept as the max bit if we need to add more engines +#define MC_ENGINE_IDX_MAX 168 // Index GR reference #define MC_ENGINE_IDX_GRn(x) (MC_ENGINE_IDX_GR0 + (x)) @@ -150,7 +160,7 @@ #define MC_ENGINE_IDX_CE(x) (MC_ENGINE_IDX_CE0 + (x)) // Index MSENC reference -#define MC_ENGINE_IDX_MSENCn(x) (MC_ENGINE_IDX_MSENC + (x)) +#define MC_ENGINE_IDX_NVENCn(x) (MC_ENGINE_IDX_NVENC + (x)) // Index NVDEC reference #define MC_ENGINE_IDX_NVDECn(x) (MC_ENGINE_IDX_NVDEC + (x)) @@ -164,6 +174,9 @@ #define MC_ENGINE_IDX_IS_CE(x) \ ((MC_ENGINE_IDX_CE(0) <= (x)) && ((x) <= MC_ENGINE_IDX_CE_MAX)) +// Index OFA reference +#define MC_ENGINE_IDX_OFA(x) (MC_ENGINE_IDX_OFA0 + (x)) + MAKE_BITVECTOR(MC_ENGINE_BITVECTOR, MC_ENGINE_IDX_MAX); typedef MC_ENGINE_BITVECTOR *PMC_ENGINE_BITVECTOR; diff --git a/src/nvidia/inc/kernel/gpu/intr/intr_common.h b/src/nvidia/inc/kernel/gpu/intr/intr_common.h index 877e5ac9e0..a1c2039fe9 100644 --- a/src/nvidia/inc/kernel/gpu/intr/intr_common.h +++ b/src/nvidia/inc/kernel/gpu/intr/intr_common.h @@ -26,7 +26,13 @@ /*! Common defines used by both Intr and OBJINTRABLE */ -/*! Kinds of interrupts that a unit can have. */ +/*! Kinds of interrupts that a unit can have. + * + * Different interrupt vectors can route to the same MC_ENGINE_IDX_* (and its + * associated #IntrService). + * This enum is used to disambiguate which handler function within an + * #IntrService should be called depending on the actual interrupt vector. + */ typedef enum { /*! * Legacy concept of "stalling" interrupts. diff --git a/src/nvidia/inc/kernel/gpu/kern_gpu_power.h b/src/nvidia/inc/kernel/gpu/kern_gpu_power.h index bb5fc742fb..1cf504fb8f 100644 --- a/src/nvidia/inc/kernel/gpu/kern_gpu_power.h +++ b/src/nvidia/inc/kernel/gpu/kern_gpu_power.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2004-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -41,6 +41,7 @@ typedef enum // TODO-SC use mask for the bool variables typedef struct { + NvU32 refCount; GPU_GC6_STATE currentState; NvU32 executedStepMask; // step mask executed during entry sequence NvU32 stepMask[NV2080_CTRL_GC6_FLAVOR_ID_MAX]; // step mask cache diff --git a/src/nvidia/inc/kernel/gpu/mem_mgr/ce_utils.h b/src/nvidia/inc/kernel/gpu/mem_mgr/ce_utils.h index 7f814c4248..6ec30074a4 100644 --- a/src/nvidia/inc/kernel/gpu/mem_mgr/ce_utils.h +++ b/src/nvidia/inc/kernel/gpu/mem_mgr/ce_utils.h @@ -53,6 +53,7 @@ typedef struct NvU64 submittedWorkId; // Payload to poll for async completion } CEUTILS_MEMCOPY_PARAMS; +class KernelChannel; NVOC_PREFIX(ceutils) class CeUtils : Object { @@ -83,6 +84,9 @@ NVOC_PREFIX(ceutils) class CeUtils : Object NvU32 hTdCopyClass; NvU64 lastSubmittedPayload; NvU64 lastCompletedPayload; + + // Only used by fifo lite implementation + KernelChannel *pLiteKernelChannel; }; diff --git a/src/nvidia/inc/kernel/gpu/mem_mgr/mem_utils.h b/src/nvidia/inc/kernel/gpu/mem_mgr/mem_utils.h index ca15a1b525..a27b5f1243 100644 --- a/src/nvidia/inc/kernel/gpu/mem_mgr/mem_utils.h +++ b/src/nvidia/inc/kernel/gpu/mem_mgr/mem_utils.h @@ -28,7 +28,6 @@ #define CLEAR_HAL_ATTR(a) \ a = (a &~(DRF_NUM(OS32, _ATTR, _COMPR, 0x3) | \ - DRF_NUM(OS32, _ATTR, _TILED, 0x3) | \ DRF_NUM(OS32, _ATTR, _ZCULL, 0x3))); #define CLEAR_HAL_ATTR2(a) \ diff --git a/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.h b/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.h index d81430e3de..e9998c7803 100644 --- a/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.h +++ b/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -40,6 +40,7 @@ NvU32 findRegionID(PMA *pPma, NvU64 address); void pmaPrintBlockStatus(PMA_PAGESTATUS blockStatus); void pmaRegionPrint(PMA *pPma, PMA_REGION_DESCRIPTOR *pRegion, void *pMap); NvBool pmaStateCheck(PMA *pPma); +NV_STATUS pmaCheckRangeAgainstRegionDesc(PMA *pPma, NvU64 base, NvU64 size); // Temporary putting these here. TODO refactor them in the next CL. NV_STATUS _pmaEvictContiguous(PMA *pPma, void *pMap, NvU64 evictStart, NvU64 evictEnd, @@ -182,12 +183,16 @@ void pmaFreeList(PMA *pPma, PRANGELISTTYPE *ppList); * @param[in] physAddrBase The base address of this address tree * @param[in] pBlacklistPageBase Structure that contains the blacklisted pages * @param[in] blacklistCount Number of blacklisted pages + * @param[in] bBlacklistFromInforom Whether the blacklisted pages are coming from + * inforom (i.e., from heap/PMA init) or not + * (i.e., from ECC interrupt handling) * * @return NV_OK * NV_ERR_NO_MEMORY if memory allocation fails */ NV_STATUS pmaRegisterBlacklistInfo(PMA *pPma, NvU64 physAddrBase, - PPMA_BLACKLIST_ADDRESS pBlacklistPageBase, NvU32 blacklistCount); + PPMA_BLACKLIST_ADDRESS pBlacklistPageBase, NvU32 blacklistCount, + NvBool bBlacklistFromInforom); /*! * @brief Query blacklisting states tracked by PMA diff --git a/src/nvidia/inc/kernel/gpu/mem_mgr/virt_mem_allocator_common.h b/src/nvidia/inc/kernel/gpu/mem_mgr/virt_mem_allocator_common.h index 0180cf80d5..d69331997e 100644 --- a/src/nvidia/inc/kernel/gpu/mem_mgr/virt_mem_allocator_common.h +++ b/src/nvidia/inc/kernel/gpu/mem_mgr/virt_mem_allocator_common.h @@ -41,6 +41,7 @@ typedef struct ChannelDescendant ChannelDescendant; typedef struct ContextDma ContextDma; typedef struct Memory Memory; typedef struct EVENTNOTIFICATION EVENTNOTIFICATION; +typedef struct Device Device; //--------------------------------------------------------------------------- // @@ -87,8 +88,8 @@ void notifyFillNOTIFICATION(OBJGPU *pGpu, NV_STATUS CompletionStatus, NvBool TimeSupplied, NvU64 Time); -NV_STATUS notifyFillNotifierGPUVA (OBJGPU*, RsClient*, NvHandle, NvU64, NvV32, NvV16, NV_STATUS, NvU32); -NV_STATUS notifyFillNotifierGPUVATimestamp (OBJGPU*, RsClient*, NvHandle, NvU64, NvV32, NvV16, NV_STATUS, NvU32, NvU64); +NV_STATUS notifyFillNotifierGPUVA (OBJGPU*, Device*, NvHandle, NvU64, NvV32, NvV16, NV_STATUS, NvU32); +NV_STATUS notifyFillNotifierGPUVATimestamp (OBJGPU*, Device*, NvHandle, NvU64, NvV32, NvV16, NV_STATUS, NvU32, NvU64); NV_STATUS notifyFillNotifierMemory (OBJGPU*, Memory *, NvV32, NvV16, NV_STATUS, NvU32); NV_STATUS notifyFillNotifierMemoryTimestamp(OBJGPU*, Memory *, NvV32, NvV16, NV_STATUS, NvU32, NvU64); void notifyFillNvNotification(OBJGPU *pGpu, @@ -99,8 +100,8 @@ void notifyFillNvNotification(OBJGPU *pGpu, NvBool TimeSupplied, NvU64 Time); -NV_STATUS semaphoreFillGPUVA (OBJGPU*, RsClient*, NvHandle, NvU64, NvV32, NvV32, NvBool); -NV_STATUS semaphoreFillGPUVATimestamp(OBJGPU*, RsClient*, NvHandle, NvU64, NvV32, NvV32, NvBool, NvU64); +NV_STATUS semaphoreFillGPUVA (OBJGPU*, Device*, NvHandle, NvU64, NvV32, NvV32, NvBool); +NV_STATUS semaphoreFillGPUVATimestamp(OBJGPU*, Device*, NvHandle, NvU64, NvV32, NvV32, NvBool, NvU64); RM_ATTR_PAGE_SIZE dmaNvos32ToPageSizeAttr(NvU32 attr, NvU32 attr2); diff --git a/src/nvidia/inc/kernel/gpu/video/kernel_video_engine.h b/src/nvidia/inc/kernel/gpu/video/kernel_video_engine.h new file mode 100644 index 0000000000..5ccd89b383 --- /dev/null +++ b/src/nvidia/inc/kernel/gpu/video/kernel_video_engine.h @@ -0,0 +1,3 @@ + +#include "g_kernel_video_engine_nvoc.h" + diff --git a/src/nvidia/inc/kernel/gpuvideo/video_event.h b/src/nvidia/inc/kernel/gpuvideo/video_event.h new file mode 100644 index 0000000000..9c8cbb89b9 --- /dev/null +++ b/src/nvidia/inc/kernel/gpuvideo/video_event.h @@ -0,0 +1,241 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef VIDEO_EVENT_H +#define VIDEO_EVENT_H + +/*! +************** Defines used for Video HW event logging! *********************** +*/ + +/*! +* Defines a skip factor when event buffer is full, +* i.e. 1/(RM_VIDEO_TRACE_SURFACE_SKIP_FACTOR) of the event buffers +* will be skipped and over-written. +*/ +#define RM_VIDEO_TRACE_SURFACE_SKIP_FACTOR (16UL) + +/*! +* Defines max size of a variable data in one record. For event data has a size +* that is larger than this define, multiple event records will be used for logging. +*/ +#define RM_VIDEO_TRACE_MAX_VARIABLE_DATA_SIZE (0x1000UL) + +/*! +* Defines magic value for hardware video events +*/ +#define ENG_VIDEO_TRACE_EVENT_MAGIC_HI (0xdeadbeefUL) +#define ENG_VIDEO_TRACE_EVENT_MAGIC_LO (0xdead0001UL) + +/*! +* Define the type of the engine. Since engine uCode can not determine the actual id, +* such as NVENC0, NVENC1 etc., we will defer this to RM to determine the actual id +* and populate it in final event data structure. +*/ +typedef enum +{ + VIDEO_ENGINE_TYPE__NVDEC = 0, + VIDEO_ENGINE_TYPE__NVENC, + VIDEO_ENGINE_TYPE__NVJPG, + VIDEO_ENGINE_TYPE__OFA, + VIDEO_ENGINE_TYPE__NUM +} VIDEO_ENGINE_TYPE; + +/*! +* Defines video codec types +*/ +typedef enum +{ + VIDEO_ENGINE_CODEC_ID__OFA = 0, /* Only codec supported for OFA engine. */ + VIDEO_ENGINE_CODEC_ID__JPEG = 0, /* Only codec supported for NVJPEG engine. */ + VIDEO_ENGINE_CODEC_ID__MPEG2 = 0, + VIDEO_ENGINE_CODEC_ID__VC1, + VIDEO_ENGINE_CODEC_ID__H264, + VIDEO_ENGINE_CODEC_ID__MPEG4, + VIDEO_ENGINE_CODEC_ID__VP8, + VIDEO_ENGINE_CODEC_ID__VP9, + VIDEO_ENGINE_CODEC_ID__HEVC, + VIDEO_ENGINE_CODEC_ID__AVD, + VIDEO_ENGINE_CODEC_ID__NUM +} VIDEO_ENGINE_CODEC_ID; + +/*! +* Defines types of video events +*/ +typedef enum +{ + VIDEO_ENGINE_EVENT_ID__SESSION_START = 0, + VIDEO_ENGINE_EVENT_ID__SESSION_END, + VIDEO_ENGINE_EVENT_ID__POWER_STATE_CHANGE, + VIDEO_ENGINE_EVENT_ID__LOG_DATA, + VIDEO_ENGINE_EVENT_ID__NUM +} VIDEO_ENGINE_EVENT_ID; + +/*! +* Defines types of the log data of video events if VIDEO_ENGINE_EVENT__LOG_DATA_MAGIC present +* as first DWORD of log data. +*/ +typedef enum +{ + VIDEO_ENGINE_EVENT_LOG_DATA_TYPE__GENERIC = 0, /* Generic opaque data */ + VIDEO_ENGINE_EVENT_LOG_DATA_TYPE__STR, /* Log data can be interpret as string */ + VIDEO_ENGINE_EVENT_LOG_DATA_TYPE__BIN, /* Log data are binary data */ + VIDEO_ENGINE_EVENT_LOG_DATA_TYPE__NUM +} VIDEO_ENGINE_EVENT_LOG_DATA_TYPE; + +/*! +* Defines return status for VIDEO_ENGINE_EVENT_ID__SESSION_END +*/ +typedef enum +{ + VIDEO_ENGINE_STATUS__OK = 0, + VIDEO_ENGINE_STATUS__ERR, + VIDEO_ENGINE_STATUS__NUM +} VIDEO_ENGINE_STATUS; + +/*! +* Defines structs for various types of trace events +*/ +typedef struct { + NvU8 engine_type; + NvU8 engine_id; + NvU16 codec_id; + NvU32 reserved1; +} VIDEO_ENGINE_EVENT__SESSION_START; + +typedef struct { + NvU8 engine_type; + NvU8 engine_id; + NvU16 codec_id; + NvU32 status; +} VIDEO_ENGINE_EVENT__SESSION_END; + + +typedef struct { + NvU16 from; + NvU16 to; + NvU32 reserved2; +} VIDEO_ENGINE_EVENT__POWER_STATE_CHANGE; + +typedef struct +{ + NvU8 engine_type; + NvU8 engine_id; + NvU16 codec_id; + NvU32 size; /* size of data being logged in NvU32 */ +} VIDEO_ENGINE_EVENT__LOG_DATA; + +#define VIDEO_ENGINE_EVENT__LOG_DATA_MAGIC RM_VIDEO_TRACE_EVENT_MAGIC_HI + +typedef struct +{ + NvU32 magic; + VIDEO_ENGINE_EVENT_LOG_DATA_TYPE type; + NvU32 data[]; +} VIDEO_ENGINE_EVENT__LOG_DATA_HDR; + +/*! +* Defines the struct for a full trace record contains various event structs. +*/ +typedef struct +{ + + NvU32 magic_lo; + NvU32 magic_hi; + + union + { + NvU64 ts; + struct + { + NvU32 ts_lo; + NvU32 ts_hi; + }; + }; + + VIDEO_ENGINE_EVENT_ID event_id; + NvU32 seq_no; + + union { + + NvU64 event_data; + + VIDEO_ENGINE_EVENT__SESSION_START event_start; + VIDEO_ENGINE_EVENT__SESSION_END event_end; + VIDEO_ENGINE_EVENT__POWER_STATE_CHANGE event_pstate_change; + VIDEO_ENGINE_EVENT__LOG_DATA event_log_data; + }; + + // Client information from RM + NvU64 userInfo; + NvU32 context_id; + NvU32 pid; + NvU64 api_id; + NvU32 gfid; + NvU32 reserved; + +} VIDEO_ENGINE_EVENT__RECORD; + +#define VIDEO_ENGINE_EVENT__LOG_DATA_SIZE(s) (sizeof(VIDEO_ENGINE_EVENT__RECORD) + s.event_log_data.size) + +/*! +* Client information passing down by RM and saved at offset VIDEO_ENGINE_EVENT__LOG_INFO__OFFSET +* with the size of VIDEO_ENGINE_EVENT__LOG_INFO__SIZE in context allocation. +*/ +#define VIDEO_ENGINE_EVENT__LOG_INFO__OFFSET (0xFA0UL) +#define VIDEO_ENGINE_EVENT__LOG_INFO__SIZE (0x20UL) +#define VIDEO_ENGINE_EVENT__LOG_INFO__LOG_SIZE (5UL) +#define VIDEO_ENGINE_EVENT__KERNEL_PID (0xFFFFFFFFUL) +#define VIDEO_ENGINE_EVENT__KERNEL_CONTEXT (0xFFFFFFFFUL) + +typedef struct { + NvU64 userInfo; + NvU32 context_id; + NvU32 pid; + NvU32 gfid; + NvU8 engine_id; + NvU8 reserved3[31]; +} VIDEO_ENGINE_EVENT__LOG_INFO; + +/*! +* Data-structure for ringbuffer structure related to video ringbuffer surfaces. +*/ +typedef struct { + NvU32 bufferSize; + NvU32 readPtr; + NvU32 writePtr; + NvU32 flags; + NvU8 pData[]; +} VIDEO_TRACE_RING_BUFFER, *PVIDEO_TRACE_RING_BUFFER; + +/* Macro convert data offer to ringbuffer offset*/ +#define VIDEO_TRACE_RING_BUFFER__DATA_OFFSET(o) (o + sizeof(VIDEO_TRACE_RING_BUFFER)) +#define VIDEO_TRACE_RING_BUFFER__OFFSET(t) (&(((PVIDEO_TRACE_RING_BUFFER)0)->t)) +#define VIDEO_TRACE_RING_BUFFER__SIZEOF(t) (sizeof(((PVIDEO_TRACE_RING_BUFFER)0)->t)) + +#define VIDEO_TRACE_FLAG__LOGGING_ENABLED (0x00000001UL) +#define VIDEO_TRACE_FLAG__RESERVED (0xFFFFFFFEUL) + +#endif // VIDEO_EVENT_H diff --git a/src/nvidia/inc/kernel/os/os_stub.h b/src/nvidia/inc/kernel/os/os_stub.h index 2d8a590268..37ad642411 100644 --- a/src/nvidia/inc/kernel/os/os_stub.h +++ b/src/nvidia/inc/kernel/os/os_stub.h @@ -36,36 +36,17 @@ // Each of these stub functions returns a different type. Used to // stub out function pointers in OBJOS. // -OSQADbgRegistryInit stubOsQADbgRegistryInit; OSnv_rdcr4 stubOsnv_rdcr4; OSnv_rdxcr0 stubOsnv_rdxcr0; OSnv_cpuid stubOsnv_cpuid; OSnv_rdmsr stubOsnv_rdmsr; OSnv_wrmsr stubOsnv_wrmsr; -OSRobustChannelsDefaultState stubOsRobustChannelsDefaultState; OSSpinLoop stubOsSpinLoop; -OSDbgBreakpointEnabled stubOsDbgBreakpointEnabled; -OSQueueWorkItem stubOsQueueWorkItem; -OSQueueWorkItemWithFlags stubOsQueueWorkItemWithFlags; -OSQueueSystemWorkItem stubOsQueueSystemWorkItem; -OSSimEscapeWrite stubOsSimEscapeWrite; -OSSimEscapeWriteBuffer stubOsSimEscapeWriteBuffer; -OSSimEscapeRead stubOsSimEscapeRead; -OSSimEscapeReadBuffer stubOsSimEscapeReadBuffer; OSSetSurfaceName stubOsSetSurfaceName; -OSCallACPI_NVHG_GPUSTA stubOsCallWMI_NVHG_GPUSTA; -OSCallACPI_NVHG_MXDS stubOsCallWMI_NVHG_MXDS; -OSCallACPI_NVHG_MXMX stubOsCallWMI_NVHG_MXMX; -OSCallACPI_NVHG_DOS stubOsCallWMI_NVHG_DOS; -OSCallACPI_NVHG_DCS stubOsCallWMI_NVHG_DCS; -OSCheckCallback stubOsCheckCallback; -OSRCCallback stubOsRCCallback; -OSSetupVBlank stubOsSetupVBlank; OSObjectEventNotification stubOsObjectEventNotification; OSPageArrayGetPhysAddr stubOsPageArrayGetPhysAddr; OSInternalReserveFreeCallback stubOsInternalReserveFreeCallback; OSInternalReserveAllocCallback stubOsInternalReserveAllocCallback; -OSGetUefiVariable stubOsGetUefiVariable; #endif // OS_STUB_H diff --git a/src/nvidia/inc/kernel/rmapi/binary_api.h b/src/nvidia/inc/kernel/rmapi/binary_api.h index 9b461d57b5..df57afcf0b 100644 --- a/src/nvidia/inc/kernel/rmapi/binary_api.h +++ b/src/nvidia/inc/kernel/rmapi/binary_api.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/nvidia/inc/kernel/rmapi/control.h b/src/nvidia/inc/kernel/rmapi/control.h index c1f6c0e32e..98fda3034b 100644 --- a/src/nvidia/inc/kernel/rmapi/control.h +++ b/src/nvidia/inc/kernel/rmapi/control.h @@ -317,6 +317,18 @@ NV_STATUS embeddedParamCopyOut(RMAPI_PARAM_COPY *pParamCopy, RmCtrlParams *pRmC // is enabled; see g_bRsAccessEnabled. // + +/* + * On T234, RM is in kernel mode, so when RM is running in kernel mode it + * does not allow usermode clients like MODs to call control calls that are + * marked as KERNEL_PRIVILEGED. + * So defining new macro DISPLAY_PRIVILEGED(i.e PRIVILEGED) for Tegra and mark + * control calls needed by MODs with this so that MODs running as root can call + * these control calls. However keeping same privilege level for DGPUs which + * does not change the current behaviour. + */ +#define DISPLAY_PRIVILEGED KERNEL_PRIVILEGED + #endif // _CONTROL_H_ diff --git a/src/nvidia/inc/kernel/rmapi/rmapi.h b/src/nvidia/inc/kernel/rmapi/rmapi.h index 8482a6ab2b..74f0e96c6f 100644 --- a/src/nvidia/inc/kernel/rmapi/rmapi.h +++ b/src/nvidia/inc/kernel/rmapi/rmapi.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -38,6 +38,7 @@ typedef struct CALL_CONTEXT CALL_CONTEXT; typedef struct MEMORY_DESCRIPTOR MEMORY_DESCRIPTOR; typedef struct RS_RES_FREE_PARAMS_INTERNAL RS_RES_FREE_PARAMS_INTERNAL; typedef struct RS_LOCK_INFO RS_LOCK_INFO; +typedef struct NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS; typedef NvU32 NV_ADDRESS_SPACE; extern RsServer g_resServ; @@ -90,6 +91,15 @@ void rmapiLockRelease(void); */ NvBool rmapiLockIsOwner(void); +/** + * Check if current thread owns the RW API lock + */ +NvBool rmapiLockIsWriteOwner(void); + +/** + * Retrieve total RM API lock wait and hold times + */ +void rmapiLockGetTimes(NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS *); /** * Type of RM API client interface @@ -309,12 +319,13 @@ rmapiEpilogue RM_API_CONTEXT *pContext ); -void +NV_STATUS rmapiInitLockInfo ( - RM_API *pRmApi, - NvHandle hClient, - RS_LOCK_INFO *pLockInfo + RM_API *pRmApi, + NvHandle hClient, + NvHandle hSecondClient, + RS_LOCK_INFO *pLockInfo ); // diff --git a/src/nvidia/inc/kernel/virtualization/common_vgpu_mgr.h b/src/nvidia/inc/kernel/virtualization/common_vgpu_mgr.h index 2e55c178ad..bdfedd5f17 100644 --- a/src/nvidia/inc/kernel/virtualization/common_vgpu_mgr.h +++ b/src/nvidia/inc/kernel/virtualization/common_vgpu_mgr.h @@ -96,7 +96,7 @@ vgpuMgrReserveSystemChannelIDs(OBJGPU *pGpu, NvU32 gfid, NvU32 *pChidOffset, NvU32 *pChannelCount, - NvHandle hClient, + Device *pMigDevice, NvU32 numChannels, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *engineFifoList); @@ -106,7 +106,7 @@ vgpuMgrFreeSystemChannelIDs(OBJGPU *pGpu, NvU32 gfid, NvU32 *pChidOffset, NvU32 *pChannelCount, - NvHandle hClient, + Device *pMigDevice, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *engineFifoList); diff --git a/src/nvidia/inc/libraries/containers/list.h b/src/nvidia/inc/libraries/containers/list.h index 5c95512568..629f33c3c8 100644 --- a/src/nvidia/inc/libraries/containers/list.h +++ b/src/nvidia/inc/libraries/containers/list.h @@ -143,6 +143,7 @@ struct ListIterBase ListNode *pLast; #if PORT_IS_CHECKED_BUILD NvU32 versionNumber; + NvBool bValid; #endif }; diff --git a/src/nvidia/inc/libraries/containers/map.h b/src/nvidia/inc/libraries/containers/map.h index 868b3bb36e..861ab1d349 100644 --- a/src/nvidia/inc/libraries/containers/map.h +++ b/src/nvidia/inc/libraries/containers/map.h @@ -144,6 +144,7 @@ struct MapIterBase MapNode *pLast; #if PORT_IS_CHECKED_BUILD NvU32 versionNumber; + NvBool bValid; #endif }; diff --git a/src/nvidia/inc/libraries/containers/type_safety.h b/src/nvidia/inc/libraries/containers/type_safety.h index f5296be846..90a9afa9ab 100644 --- a/src/nvidia/inc/libraries/containers/type_safety.h +++ b/src/nvidia/inc/libraries/containers/type_safety.h @@ -33,6 +33,14 @@ #define NV_TYPEOF_SUPPORTED 0 #endif +// +// Validate whether a container iterator is valid. +// In checked builds, a container and its iterator get assigned a versionNumber. pIter gets version +// number once at the time of construction. pCont's versionNumber is initially zero and changes +// when pCont is modified. Any container modification invalidates all iterators. +// +#define CONT_ITER_IS_VALID(pCont, pIter) ((pCont)->versionNumber == (pIter)->versionNumber) + /** * Tag a non-intrusive container union with the following info: * valueSize : size of its element type for non-intrusive malloc diff --git a/src/nvidia/inc/libraries/containers/vector.h b/src/nvidia/inc/libraries/containers/vector.h index 039dcf7c3c..6554e5d56e 100644 --- a/src/nvidia/inc/libraries/containers/vector.h +++ b/src/nvidia/inc/libraries/containers/vector.h @@ -93,6 +93,7 @@ struct VectorIterBase NvBool bForward; #if PORT_IS_CHECKED_BUILD NvU32 versionNumber; + NvBool bValid; #endif }; @@ -123,6 +124,7 @@ struct VectorWrapper capacity, \ sizeof(*(pVector)->valueSize)) #define vectDestroy(pVector) vectDestroy_IMPL(&((pVector)->real.base)) +#define vectClear(pVector) vectClear_IMPL(&((pVector)->real.base)) #define vectCount(pVector) vectCount_IMPL(&((pVector)->real.base)) #define vectCapacity(pVector) vectCapacity_IMPL(&((pVector)->real.base)) #define vectIsEmpty(pVector) vectIsEmpty_IMPL(&((pVector)->real.base)) @@ -138,7 +140,6 @@ struct VectorWrapper vectIsValid_IMPL) #define vectRemove(pVector, index) \ vectRemove_IMPL(&((pVector)->real.base), index) -#define vectClear(pVector) vectDestroy(pVector) #define vectAppend(pVector, pValue) \ CONT_CAST_ELEM((pVector), \ vectAppend_IMPL(&(pVector)->real.base, \ @@ -175,6 +176,7 @@ NV_STATUS vectInit_IMPL(Vector *pVector, NvU32 capacity, NvU32 valueSize); void vectDestroy_IMPL(Vector *pVector); +void vectClear_IMPL(Vector *pVector); NvU32 vectCount_IMPL(Vector *pVector); NvU32 vectCapacity_IMPL(Vector *pVector); NvBool vectIsEmpty_IMPL(Vector *pVector); diff --git a/src/nvidia/inc/libraries/nvport/debug.h b/src/nvidia/inc/libraries/nvport/debug.h index fe7a94d7a4..c8e5d752cd 100644 --- a/src/nvidia/inc/libraries/nvport/debug.h +++ b/src/nvidia/inc/libraries/nvport/debug.h @@ -307,6 +307,10 @@ PORT_DEBUG_INLINE void portDbgExPrintfLevel(NvU32 level, const char *format, ... #endif // PORT_IS_KERNEL_BUILD #endif // NV_MODS +#if !defined(PORT_DUMP_STACK) +#define PORT_DUMP_STACK() do {} while (0) +#endif + #ifdef __cplusplus } #endif //__cplusplus diff --git a/src/nvidia/inc/libraries/nvport/inline/debug_unix_kernel_os.h b/src/nvidia/inc/libraries/nvport/inline/debug_unix_kernel_os.h index 094f5440a3..0748ae050d 100644 --- a/src/nvidia/inc/libraries/nvport/inline/debug_unix_kernel_os.h +++ b/src/nvidia/inc/libraries/nvport/inline/debug_unix_kernel_os.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -39,9 +39,13 @@ extern "C" { #endif #include "nv-kernel-interface-api.h" +#include "utils/nvprintf_level.h" +#include "os-interface.h" + void NV_API_CALL os_dbg_breakpoint(void); void NV_API_CALL out_string(const char *str); int NV_API_CALL nv_printf(NvU32 debuglevel, const char *format, ...); +void NV_API_CALL os_dump_stack(void); // No init/shutdown needed #define portDbgInitialize() @@ -58,15 +62,16 @@ portDbgPrintString out_string(str); } -#define portDbgPrintf(fmt, ...) nv_printf(0xFFFFFFFF, fmt, ##__VA_ARGS__) +#define portDbgPrintf(fmt, ...) nv_printf(NV_DBG_FORCE_LEVEL(LEVEL_INFO), fmt, ##__VA_ARGS__) #undef portDbgPrintf_SUPPORTED #define portDbgPrintf_SUPPORTED 1 -#define portDbgExPrintfLevel(level, fmt, ...) nv_printf(level, fmt, ##__VA_ARGS__) +#define portDbgExPrintfLevel(level, fmt, ...) nv_printf(NV_DBG_FORCE_LEVEL(level), fmt, ##__VA_ARGS__) #undef portDbgExPrintfLevel_SUPPORTED #define portDbgExPrintfLevel_SUPPORTED 1 #define PORT_BREAKPOINT() os_dbg_breakpoint() +#define PORT_DUMP_STACK() os_dump_stack() #ifdef __cplusplus } diff --git a/src/nvidia/inc/libraries/nvport/memory.h b/src/nvidia/inc/libraries/nvport/memory.h index 8c5531619b..b757b64c9e 100644 --- a/src/nvidia/inc/libraries/nvport/memory.h +++ b/src/nvidia/inc/libraries/nvport/memory.h @@ -904,7 +904,7 @@ void portMemExUnmapIOSpace(void *addr, NvU64 byteSize); * Has no effect unless PORT_MEM_TRACK_USE_CALLERINFO is also set. */ #if !defined(PORT_MEM_TRACK_USE_CALLERINFO_IP) -#if NVCPU_IS_RISCV64 +#if NVOS_IS_LIBOS #define PORT_MEM_TRACK_USE_CALLERINFO_IP 1 #else #define PORT_MEM_TRACK_USE_CALLERINFO_IP 0 diff --git a/src/nvidia/inc/libraries/resserv/rs_server.h b/src/nvidia/inc/libraries/resserv/rs_server.h index d3bc11f3b1..98db50617c 100644 --- a/src/nvidia/inc/libraries/resserv/rs_server.h +++ b/src/nvidia/inc/libraries/resserv/rs_server.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -524,10 +524,12 @@ extern NV_STATUS serverAllocApiCopyOut(RsServer *pServer, NV_STATUS status, API_ /** * Obtain a second client handle to lock if required for the allocation. - * @param[in] pParams Resource allocation parameters - * @param[in] phClient Client to lock, if any + * @param[in] externalClassId External class ID of resource + * @param[in] pAllocParams Class-specific allocation parameters + * + * @return Second client to lock, if any */ -extern NV_STATUS serverLookupSecondClient(RS_RES_ALLOC_PARAMS_INTERNAL *pParams, NvHandle *phClient); +extern NvHandle serverAllocLookupSecondClient(NvU32 externalClassId, void *pAllocParams); /** * Acquires a top-level lock. User-implemented. diff --git a/src/nvidia/inc/libraries/utils/nvassert.h b/src/nvidia/inc/libraries/utils/nvassert.h index b3a6e78225..cfab009081 100644 --- a/src/nvidia/inc/libraries/utils/nvassert.h +++ b/src/nvidia/inc/libraries/utils/nvassert.h @@ -98,7 +98,7 @@ extern "C" { // Hook NV_ASSERT into RCDB. #if !defined(NV_JOURNAL_ASSERT_ENABLE) -#if defined(NVRM) && (NVOS_IS_WINDOWS || NVOS_IS_UNIX || NVCPU_IS_RISCV64) && !defined(NVWATCH) && !defined(NV_MODS) +#if defined(NVRM) && (NVOS_IS_WINDOWS || NVOS_IS_UNIX || NVOS_IS_LIBOS) && !defined(NVWATCH) && !defined(NV_MODS) #define NV_JOURNAL_ASSERT_ENABLE 1 #else #define NV_JOURNAL_ASSERT_ENABLE 0 @@ -131,7 +131,7 @@ const char *nvAssertStatusToString(NV_STATUS nvStatusIn); * for both NVLOG and NV_PRINTF. * The _FUNC macros are used for pre-compiled headers on most platforms. */ -#if defined(GSP_PLUGIN_BUILD) || (defined(NVRM) && NVCPU_IS_RISCV64) +#if defined(GSP_PLUGIN_BUILD) || (defined(NVRM) && NVOS_IS_LIBOS) void nvAssertInit(void); void nvAssertDestroy(void); @@ -146,7 +146,8 @@ void nvAssertOkFailed(NvU32 status); #define NV_ASSERT_FAILED(exprStr) \ do { \ - NV_PRINTF(LEVEL_ERROR, "Assertion failed: " exprStr "\n"); \ + static const LIBOS_SECTION_LOGGING char exprStrArg[] = {exprStr}; \ + NV_PRINTF(LEVEL_ERROR, "Assertion failed: %s\n", exprStrArg); \ nvAssertFailed(); \ COVERITY_ASSERT_FAIL(); \ PORT_BREAKPOINT(); \ @@ -154,21 +155,28 @@ void nvAssertOkFailed(NvU32 status); #define NV_ASSERT_OK_FAILED(exprStr, status) \ do { \ - NV_PRINTF(LEVEL_ERROR, "Assertion failed: %s (0x%08X) returned from " \ - exprStr "\n", nvAssertStatusToString(status), status); \ + static const LIBOS_SECTION_LOGGING char exprStrArg[] = {exprStr}; \ + NV_PRINTF(LEVEL_ERROR, "Assertion failed: %s (0x%08X) returned from %s\n", \ + nvAssertStatusToString(status), status, exprStrArg); \ nvAssertOkFailed(status); \ COVERITY_ASSERT_FAIL(); \ PORT_BREAKPOINT(); \ } while(0) #define NV_CHECK_FAILED(level, exprStr) \ - NV_PRINTF(level, "Check failed: " exprStr "\n") + do { \ + static const LIBOS_SECTION_LOGGING char exprStrArg[] = {exprStr}; \ + NV_PRINTF(level, "Check failed: %s\n", exprStrArg); \ + } while(0) \ #define NV_CHECK_OK_FAILED(level, exprStr, status) \ - NV_PRINTF(level, "Check failed: %s (0x%08X) returned from " exprStr "\n", \ - nvAssertStatusToString(status), status) + do { \ + static const LIBOS_SECTION_LOGGING char exprStrArg[] = {exprStr}; \ + NV_PRINTF(level, "Check failed: %s (0x%08X) returned from %s\n", \ + nvAssertStatusToString(status), status, exprStrArg); \ + } while (0) -#else // defined(GSP_PLUGIN_BUILD) || (defined(NVRM) && NVCPU_IS_RISCV64) +#else // defined(GSP_PLUGIN_BUILD) || (defined(NVRM) && NVOS_IS_LIBOS) #if NV_ASSERT_FAILED_USES_STRINGS #define NV_ASSERT_FAILED_FUNC_COMMA_PARAM(exprStr) , exprStr, __FILE__, __LINE__ @@ -276,7 +284,7 @@ void nvCheckOkFailedNoLog(NvU32 level, NvU32 status NV_ASSERT_FAILED_FUNC_COMMA_ NV_ASSERT_FAILED_FUNC_COMMA_PARAM(exprStr)) \ } -#endif // defined(GSP_PLUGIN_BUILD) || (defined(NVRM) && NVCPU_IS_RISCV64) +#endif // defined(GSP_PLUGIN_BUILD) || (defined(NVRM) && NVOS_IS_LIBOS) /* * Defines for precompiled headers. @@ -284,7 +292,7 @@ void nvCheckOkFailedNoLog(NvU32 level, NvU32 status NV_ASSERT_FAILED_FUNC_COMMA_ * On platforms other than GSP-RM, the _INLINE macros cannot be used inside * precompiled headers due to conflicting NVLOG_PRINT_IDs. */ -#if defined(GSP_PLUGIN_BUILD) || (defined(NVRM) && NVCPU_IS_RISCV64) +#if defined(GSP_PLUGIN_BUILD) || (defined(NVRM) && NVOS_IS_LIBOS) #define NV_ASSERT_FAILED_PRECOMP NV_ASSERT_FAILED #else #define NV_ASSERT_FAILED_PRECOMP NV_ASSERT_FAILED_FUNC diff --git a/src/nvidia/inc/libraries/utils/nvprintf.h b/src/nvidia/inc/libraries/utils/nvprintf.h index 2588e0cbaa..d615f28cce 100644 --- a/src/nvidia/inc/libraries/utils/nvprintf.h +++ b/src/nvidia/inc/libraries/utils/nvprintf.h @@ -29,43 +29,13 @@ #ifndef _NV_UTILS_PRINTF_H_ #define _NV_UTILS_PRINTF_H_ +#include "utils/nvprintf_level.h" + #ifdef __cplusplus extern "C" { #endif - -/// @defgroup NV_PRINTF_LEVELS Printf verbosity levels -/// @{ -/// @brief Prints at this level are discarded -#define LEVEL_SILENT 0x0 -/// @brief Verbose debug logging level (e.g. signaling function entry) -#define LEVEL_INFO 0x1 -/// @brief Standard debug logging level (e.g. Illegal ctrcall call) -#define LEVEL_NOTICE 0x2 -/// @brief Warning logging level (e.g. feature not supported) -#define LEVEL_WARNING 0x3 -/// @brief Error logging level (e.g. resource allocation failed) -#define LEVEL_ERROR 0x4 -/// @brief Recoverable HW error (e.g. RC events) -#define LEVEL_HW_ERROR 0x5 -/// @brief Unrecoverable error (e.g. Bus timeout) -#define LEVEL_FATAL 0x6 -/// @} - -// Used only in nvlogFilterApplyRule() -#define NV_LEVEL_MAX LEVEL_FATAL - -/** - * @def NV_PRINTF_LEVEL_ENABLED(level) - * @brief This macro evaluates to 1 if prints of a given level will be compiled. - * - * By default, it is available on all builds that allow strings - */ -#ifndef NV_PRINTF_LEVEL_ENABLED -#define NV_PRINTF_LEVEL_ENABLED(level) ((level) >= NV_PRINTF_LEVEL) -#endif - -#if defined(GSP_PLUGIN_BUILD) || (defined(NVRM) && NVCPU_IS_RISCV64) +#if defined(GSP_PLUGIN_BUILD) || (defined(NVRM) && NVOS_IS_LIBOS) /** * GSPRM uses a different system for logging. @@ -89,11 +59,7 @@ extern "C" { #define NV_PRINTF_STRING_SECTION LIBOS_SECTION_LOGGING -#define MAKE_NV_PRINTF_STR(str) \ -({ \ - static NV_PRINTF_STRING_SECTION const char rm_pvt_str[] = str; \ - rm_pvt_str; \ -}) +#define MAKE_NV_PRINTF_STR MAKE_LIBOS_LOGGING_STR // NVLOG is not used on GSP-RM. #undef NVLOG_LEVEL @@ -109,7 +75,7 @@ void log_vgpu_log_entry(const NvU64 n_args, const NvU64 * args); #define NV_PRINTF(level, format, ...) do { \ if (NV_PRINTF_LEVEL_ENABLED(level)) \ { \ - LIBOS_LOG_INTERNAL(log_vgpu_log_entry, LOG_LEVEL_ERROR, \ + LIBOS_LOG_INTERNAL(log_vgpu_log_entry, level, \ format, ##__VA_ARGS__); \ } \ } while (0) @@ -117,7 +83,7 @@ void log_vgpu_log_entry(const NvU64 n_args, const NvU64 * args); #define NV_PRINTF_EX(module, level, format, ...) do { \ if (NV_PRINTF_LEVEL_ENABLED(level)) \ { \ - LIBOS_LOG_INTERNAL(log_vgpu_log_entry, LOG_LEVEL_ERROR, \ + LIBOS_LOG_INTERNAL(log_vgpu_log_entry, level, \ format, ##__VA_ARGS__); \ } \ } while (0) @@ -131,7 +97,7 @@ void log_rm_log_entry(const NvU64 n_args, const NvU64 * args); #define NV_PRINTF(level, format, ...) do { \ if (NV_PRINTF_LEVEL_ENABLED(level)) \ { \ - LIBOS_LOG_INTERNAL(log_rm_log_entry, LOG_LEVEL_ERROR, \ + LIBOS_LOG_INTERNAL(log_rm_log_entry, level, \ format, ##__VA_ARGS__); \ } \ } while (0) @@ -139,14 +105,14 @@ void log_rm_log_entry(const NvU64 n_args, const NvU64 * args); #define NV_PRINTF_EX(module, level, format, ...) do { \ if (NV_PRINTF_LEVEL_ENABLED(level)) \ { \ - LIBOS_LOG_INTERNAL(log_rm_log_entry, LOG_LEVEL_ERROR, \ + LIBOS_LOG_INTERNAL(log_rm_log_entry, level, \ format, ##__VA_ARGS__); \ } \ } while (0) #endif // NVOC -#else // defined(NVRM) && NVCPU_IS_RISCV64 +#else // defined(NVRM) && NVOS_IS_LIBOS /** * @defgroup NV_UTILS_PRINTF Utility Printing Macros @@ -365,7 +331,7 @@ void NVRM_PRINTF_FUNCTION(const char *file, #define NVLOG_PRINTF(...) #endif -#endif // defined(NVRM) && NVCPU_IS_RISCV64 +#endif // defined(NVRM) && NVOS_IS_LIBOS /** * @def NV_PRINTF_COND(condition, leveltrue, levelfalse, format, args...) diff --git a/src/nvidia/inc/libraries/utils/nvprintf_level.h b/src/nvidia/inc/libraries/utils/nvprintf_level.h new file mode 100644 index 0000000000..3da4aeb442 --- /dev/null +++ b/src/nvidia/inc/libraries/utils/nvprintf_level.h @@ -0,0 +1,57 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NV_UTILS_PRINTF_LEVEL_H +#define NV_UTILS_PRINTF_LEVEL_H + +/// @defgroup NV_PRINTF_LEVELS Printf verbosity levels +/// @{ +/// @brief Prints at this level are discarded +#define LEVEL_SILENT 0x0 +/// @brief Verbose debug logging level (e.g. signaling function entry) +#define LEVEL_INFO 0x1 +/// @brief Standard debug logging level (e.g. Illegal ctrcall call) +#define LEVEL_NOTICE 0x2 +/// @brief Warning logging level (e.g. feature not supported) +#define LEVEL_WARNING 0x3 +/// @brief Error logging level (e.g. resource allocation failed) +#define LEVEL_ERROR 0x4 +/// @brief Recoverable HW error (e.g. RC events) +#define LEVEL_HW_ERROR 0x5 +/// @brief Unrecoverable error (e.g. Bus timeout) +#define LEVEL_FATAL 0x6 +/// @} + +#define NV_LEVEL_MAX LEVEL_FATAL + +/** + * @def NV_PRINTF_LEVEL_ENABLED(level) + * @brief This macro evaluates to 1 if prints of a given level will be compiled. + * + * By default, it is available on all builds that allow strings + */ +#ifndef NV_PRINTF_LEVEL_ENABLED +#define NV_PRINTF_LEVEL_ENABLED(level) ((level) >= NV_PRINTF_LEVEL) +#endif + +#endif diff --git a/src/nvidia/interface/nv_sriov_defines.h b/src/nvidia/interface/nv_sriov_defines.h index 3d144780be..8208a5ff7d 100644 --- a/src/nvidia/interface/nv_sriov_defines.h +++ b/src/nvidia/interface/nv_sriov_defines.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -90,4 +90,5 @@ // used in VGPU-GSP RPC setup #define NV_VF_SCRATCH_REGISTER_GUEST_RPC_HI 0x3 -#define MAX_PARTITIONS_WITH_GFID (32) \ No newline at end of file +#define MAX_PARTITIONS_WITH_GFID (32) +#define MAX_PARTITIONS_WITH_GFID_MIG_ENABLED (7) diff --git a/src/nvidia/interface/nv_uvm_types.h b/src/nvidia/interface/nv_uvm_types.h index bed74610b3..2bf5b24259 100644 --- a/src/nvidia/interface/nv_uvm_types.h +++ b/src/nvidia/interface/nv_uvm_types.h @@ -104,6 +104,10 @@ typedef struct UvmGpuMemoryInfo_tag // Out: Set to TRUE, if the allocation is in sysmem. NvBool sysmem; + // Out: Set to TRUE, if this allocation is treated as EGM. + // sysmem is also TRUE when egm is TRUE. + NvBool egm; + // Out: Set to TRUE, if the allocation is a constructed // under a Device or Subdevice. // All permutations of sysmem and deviceDescendant are valid. @@ -125,6 +129,8 @@ typedef struct UvmGpuMemoryInfo_tag // Out: Uuid of the GPU to which the allocation belongs. // This is only valid if deviceDescendant is NV_TRUE. + // When egm is NV_TRUE, this is also the UUID of the GPU + // for which EGM is local. // Note: If the allocation is owned by a device in // an SLI group and the allocation is broadcast // across the SLI group, this UUID will be any one @@ -332,7 +338,7 @@ typedef struct UvmGpuPagingChannelAllocParams_tag // The max number of Copy Engines supported by a GPU. // The gpu ops build has a static assert that this is the correct number. -#define UVM_COPY_ENGINE_COUNT_MAX 10 +#define UVM_COPY_ENGINE_COUNT_MAX 64 typedef struct { @@ -566,11 +572,8 @@ typedef struct UvmPlatformInfo_tag // Out: ATS (Address Translation Services) is supported NvBool atsSupported; - // Out: True if HW trusted execution, such as AMD's SEV-SNP or Intel's TDX, - // is enabled in the VM, indicating that Confidential Computing must be - // also enabled in the GPU(s); these two security features are either both - // enabled, or both disabled. - NvBool confComputingEnabled; + // Out: AMD SEV (Secure Encrypted Virtualization) is enabled + NvBool sevEnabled; } UvmPlatformInfo; typedef struct UvmGpuClientInfo_tag @@ -683,6 +686,10 @@ typedef struct UvmGpuInfo_tag // to NVSwitch peers. NvBool connectedToSwitch; NvU64 nvswitchMemoryWindowStart; + + // local EGM properties + NvBool egmEnabled; + NvU8 egmPeerId; } UvmGpuInfo; typedef struct UvmGpuFbInfo_tag diff --git a/src/nvidia/interface/nvrm_registry.h b/src/nvidia/interface/nvrm_registry.h index 3216cad2b7..df02e1cbc1 100644 --- a/src/nvidia/interface/nvrm_registry.h +++ b/src/nvidia/interface/nvrm_registry.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1997-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1997-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -833,6 +833,14 @@ #define NV_REG_STR_RM_ENABLE_ADDRTREE_YES (0x00000001) #define NV_REG_STR_RM_ENABLE_ADDRTREE_NO (0x00000000) +// +// Type DWORD +// Disable global CeUtils instance creation after fifo scheduling enablement +// +#define NV_REG_STR_DISABLE_GLOBAL_CE_UTILS "RmDisableGlobalCeUtils" +#define NV_REG_STR_DISABLE_GLOBAL_CE_UTILS_YES (0x00000001) +#define NV_REG_STR_DISABLE_GLOBAL_CE_UTILS_NO (0x00000000) + #define NV_REG_STR_RM_SCRUB_BLOCK_SHIFT "RMScrubBlockShift" // Type DWORD // Encoding Numeric Value @@ -960,6 +968,15 @@ // Encoding -- NvS32 // Override GPU NUMA Node ID assigned by OS +#define NV_REG_STR_RESTORE_BAR1_SIZE_BUG_3249028_WAR "RMBar1RestoreSize" +#define NV_REG_STR_RESTORE_BAR1_SIZE_BUG_3249028_TRUE (0x00000001) +#define NV_REG_STR_RESTORE_BAR1_SIZE_BUG_3249028_FALSE (0x00000000) +// Type DWORD: +// Encoding -- Boolean +// Check if BAR1 size has been restored correctly by SBIOS across power transitions +// Default: enabled for Ampere and up +// + // // Type DWORD // Numa allocations allow for skipping reclaim less than a specified memory occupancy threshold. @@ -1145,6 +1162,26 @@ #define NV_REG_STR_RM_CTXSW_LOG_ENABLE_INTR_APC 0x00000003 #define NV_REG_STR_RM_CTXSW_LOG_DEFAULT NV_REG_STR_RM_CTXSW_LOG_DISABLE +// Type DWORD: Indicates if enabling video event tracing +// +// 0 - Disables Video event trace usage (default) +// > 0 - Enable video event trace and define sizes for different buffers +// bit 0 - 15: sizes of the hardware staging buffer in 4K pages +// bit 16 - 30: sizes of the event buffer in 4K pages +// bit 31 - 31: Enable always logging: +// By default, video engines only log video events when there is +// at least one eventbuffer bound and enabled. If this flag is set, +// video engines will always log events even without a consumer. This +// is helpful for debugging purposes. +// Example: 0x01000008 means a 32K staging buffer and a 1M event buffer. +#define NV_REG_STR_RM_VIDEO_EVENT_TRACE "RmVideoEventTrace" +#define NV_REG_STR_RM_VIDEO_EVENT_TRACE_DISABLED (0x00000000) +#define NV_REG_STR_RM_VIDEO_EVENT_TRACE_STAGING_BUFFER_SIZE_IN_4k 15:0 +#define NV_REG_STR_RM_VIDEO_EVENT_TRACE_EVENT_BUFFER_SIZE_IN_4k 30:16 +#define NV_REG_STR_RM_VIDEO_EVENT_TRACE_ALWAYS_LOG 31:31 +#define NV_REG_STR_RM_VIDEO_EVENT_TRACE_ALWAYS_LOG_DISABLED 0x00000000 +#define NV_REG_STR_RM_VIDEO_EVENT_TRACE_ALWAYS_LOG_ENABLED 0x00000001 + // // Type: DWORD // @@ -1744,6 +1781,13 @@ // 1 - Store active RM clients in a multimap to speed up lookups (currently only in thirdpartyp2p) // 0 - (Default) Linear list search for clients +// +// Type DWORD (Boolean) +// 1 - Measure API and GPU lock hold/wait times which can be retrieved with the +// NV0000_CTRL_CMD_SYSTEM_GET_LOCK_TIMES control call +// 0 - (Default) Don't measure lock hold/wait times +// +#define NV_REG_STR_RM_LOCK_TIME_COLLECT "RmLockTimeCollect" // // Type: DWORD (Boolean) @@ -1878,6 +1922,15 @@ #define NV_REG_STR_RM_GSPRM_PROFILING_DISABLE 0 #define NV_REG_STR_RM_GSPRM_PROFILING_ENABLE 1 +// +// Controls, GSP-RM start with boost clocks. +// 0 : disabled +// 1 : enabled (default) +// +#define NV_REG_STR_RM_BOOT_GSPRM_WITH_BOOST_CLOCKS "RmBootGspRmWithBoostClocks" +#define NV_REG_STR_RM_BOOT_GSPRM_WITH_BOOST_CLOCKS_DISABLED 0 +#define NV_REG_STR_RM_BOOT_GSPRM_WITH_BOOST_CLOCKS_ENABLED 1 + // // Enable Local EGM HW verification using RM/SW stack. // Must be specified with a peerID corresponding to local EGM @@ -1926,4 +1979,112 @@ #define NV_REG_STR_RM_DMA_ADJUST_PEER_MMIO_BF3_DISABLE 0 #define NV_REG_STR_RM_DMA_ADJUST_PEER_MMIO_BF3_ENABLE 1 +#define NV_REG_STR_RM_NVLINK_FORCED_LOOPBACK_ON_SWITCH "RMNvLinkForcedLoopbackOnSwitch" +#define NV_REG_STR_RM_NVLINK_FORCED_LOOPBACK_ON_SWITCH_MODE 0:0 +#define NV_REG_STR_RM_NVLINK_FORCED_LOOPBACK_ON_SWITCH_MODE_DEFAULT (0x00000000) +#define NV_REG_STR_RM_NVLINK_FORCED_LOOPBACK_ON_SWITCH_MODE_ENABLED (0x00000001) + +// +// Type: Dword +// Encoding: +// 0 - Iterative MMU Walker is not enabled. Normal recursive implementation is used. (default) +// 1 - Iterative MMU Walker is used +// +#define NV_REG_STR_RM_ITERATIVE_MMU_WALKER "RMUseIterativeMMUWalker" +#define NV_REG_STR_RM_ITERATIVE_MMU_WALKER_DISABLED 0x00000000 +#define NV_REG_STR_RM_ITERATIVE_MMU_WALKER_ENABLED 0x00000001 +#define NV_REG_STR_RM_ITERATIVE_MMU_WALKER_DEFAULT NV_REG_STR_RM_ITERATIVE_MMU_WALKER_DISABLED + +// +// Type DWORD +// This set of MIG regkeys specifies a set of allocation requests to be issued to the GPU on boot. +// MIG configuration contained within GPUMGR always supersedes these regkeys, if present and valid. +// The entire configuration specified by these regkeys is validated before being applied. An error +// reflected in whole or in part on these regkeys will cause them to be discarded entirely. +// +// RmMIGBootConfigurationGI is used to encode a series of GPU instance allocations. These are applied in order. +// RmMIGBootConfigurationCI is used to encode a series of CI instance allocations. +// The GI associated with each CI allocation entry is specified by RmMIGBootConfigurationCIAssignment. +// It is an error to specify a CI via RmMIGBootConfigurationCI without specifying the associated GPU +// instance entry via RmMIGBootConfigurationCIAssignment. The values for any CI assignment for a CI +// entry left unspecified must be 0. +// +// RmMIGBootConfigurationGI_N +// _FLAGS - determines granularity of GPU partitioning. See NV2080_CTRL_CMD_GPU_SET_PARTITIONS +// _PLACEMENT_LO - Optional placement span to allocate the partition into. Unused if HIAllocWithHandle(pRmApi, hclient, NV01_NULL_OBJECT, \ - NV01_NULL_OBJECT, NV01_ROOT, \ - &root_alloc_params, sizeof(root_alloc_params)); \ + if (bFirstDevice) \ + { \ + status = pRmApi->AllocWithHandle(pRmApi, hclient, NV01_NULL_OBJECT, \ + NV01_NULL_OBJECT, NV01_ROOT, \ + &root_alloc_params, sizeof(root_alloc_params)); \ + } \ + else \ + { \ + status = NV_OK; \ + } \ \ if (status == NV_OK) \ { \ @@ -240,7 +247,7 @@ static inline void NV_RM_RPC_SIM_UPDATE_DISP_CHANNEL_INFO(OBJGPU *pGpu, ...) { r } while(0) #define NV_RM_RPC_ALLOC_SHARE_DEVICE(pGpu, hclient, hdevice, hclientshare, htargetclient, htargetdevice, hclass, \ - allocflags, vasize, vamode, status) \ + allocflags, vasize, vamode, bFirstDevice, status) \ do \ { \ OBJRPC *pRpc = GPU_GET_RPC(pGpu); \ @@ -249,7 +256,7 @@ static inline void NV_RM_RPC_SIM_UPDATE_DISP_CHANNEL_INFO(OBJGPU *pGpu, ...) { r { \ NV_ASSERT(IS_GSP_CLIENT(pGpu)); \ NV_RM_RPC_ALLOC_SHARE_DEVICE_FWCLIENT(pGpu, hclient, hdevice, hclientshare, htargetclient, htargetdevice, hclass, \ - allocflags, vasize, vamode, status); \ + allocflags, vasize, vamode, bFirstDevice, status); \ } else if (pRpc == NULL) \ status = NV_ERR_INSUFFICIENT_RESOURCES; \ } \ @@ -444,16 +451,6 @@ static inline void NV_RM_RPC_SIM_UPDATE_DISP_CHANNEL_INFO(OBJGPU *pGpu, ...) { r status = NV_ERR_INSUFFICIENT_RESOURCES; \ } while(0) -#define NV_RM_RPC_SIM_LOAD_ESCAPE_FUNCTIONS(pos) \ - do \ - { \ - NV_ASSERT(pos); \ - /* load simulation escape read/write routines */ \ - pos->osSimEscapeRead = RmRpcSimEscapeRead; \ - pos->osSimEscapeWrite = RmRpcSimEscapeWrite; \ - } \ - while(0) - /* outgoing updates to the plugin */ #define NV_RM_RPC_SIM_UPDATE_DISP_CONTEXT_DMA(pGpu, hclient, pcontextdma, physaddrnew, \ physlimitnew, pagesize, ptekind) \ diff --git a/src/nvidia/kernel/inc/vgpu/rpc_global_enums.h b/src/nvidia/kernel/inc/vgpu/rpc_global_enums.h index cf3f71550c..56effe2e1e 100644 --- a/src/nvidia/kernel/inc/vgpu/rpc_global_enums.h +++ b/src/nvidia/kernel/inc/vgpu/rpc_global_enums.h @@ -207,7 +207,7 @@ enum { X(RM, CTRL_SET_HS_CREDITS) // 198 X(RM, CTRL_PM_AREA_PC_SAMPLER) // 199 X(RM, INVALIDATE_TLB) // 200 - X(RM, RESERVED_201) // 201 + X(RM, CTRL_GPU_QUERY_ECC_STATUS) // 201 X(RM, ECC_NOTIFIER_WRITE_ACK) // 202 X(RM, NUM_FUNCTIONS) //END #ifdef DEFINING_X_IN_RPC_GLOBAL_ENUMS_H @@ -249,10 +249,9 @@ enum { E(TIMED_SEMAPHORE_RELEASE) // 0x1018 E(NVLINK_IS_GPU_DEGRADED) // 0x1019 E(PFM_REQ_HNDLR_STATE_SYNC_CALLBACK) // 0x101a - E(GSP_SEND_USER_SHARED_DATA) // 0x101b - E(NVLINK_FAULT_UP) // 0x101c - E(GSP_LOCKDOWN_NOTICE) // 0x101d - E(MIG_CI_CONFIG_UPDATE) // 0x101e + E(NVLINK_FAULT_UP) // 0x101b + E(GSP_LOCKDOWN_NOTICE) // 0x101c + E(MIG_CI_CONFIG_UPDATE) // 0x101d E(NUM_EVENTS) // END #ifdef DEFINING_E_IN_RPC_GLOBAL_ENUMS_H }; diff --git a/src/nvidia/kernel/inc/vgpu/sdk-structures.h b/src/nvidia/kernel/inc/vgpu/sdk-structures.h index f7a0b1be47..aae3e9b5e6 100644 --- a/src/nvidia/kernel/inc/vgpu/sdk-structures.h +++ b/src/nvidia/kernel/inc/vgpu/sdk-structures.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -81,7 +81,9 @@ typedef struct vmiopd_SM_info { // NV_SCAL_FAMILY_MAX_FBPS 16 #define MAX_FBPS 16 //Maximum number of FBPs -#define OBJ_MAX_HEADS 4 +#define OBJ_MAX_HEADS_v03_00 4 +#define OBJ_MAX_HEADS_v24_08 8 + #define MAX_NVDEC_ENGINES 5 // Maximum number of NVDEC engines @@ -115,6 +117,7 @@ typedef struct vmiopd_SM_info { #define VM_UUID_SIZE_v21_02 16 #define NV2080_CTRL_FB_FS_INFO_MAX_QUERIES_v1A_1D 96 +#define NV2080_CTRL_FB_FS_INFO_MAX_QUERIES_v24_00 120 #define NV2080_CTRL_FB_FS_INFO_MAX_QUERY_SIZE_v1A_1D 24 #define NV2080_CTRL_GRMGR_GR_FS_INFO_MAX_QUERIES_v1A_1D 96 #define NV2080_CTRL_GRMGR_MAX_SMC_IDS_v1A_1D 8 @@ -125,6 +128,9 @@ typedef struct vmiopd_SM_info { #define NV0080_CTRL_GR_INFO_MAX_SIZE_21_01 (0x00000033) #define NV0080_CTRL_GR_INFO_MAX_SIZE_22_02 (0x00000034) #define NV0080_CTRL_GR_INFO_MAX_SIZE_23_00 (0x00000035) +#define NV0080_CTRL_GR_INFO_MAX_SIZE_24_02 (0x00000036) +#define NV0080_CTRL_GR_INFO_MAX_SIZE_24_03 (0x00000037) +#define NV0080_CTRL_GR_INFO_MAX_SIZE_24_07 (0x00000038) #define NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04 8 #define NV2080_CTRL_INTERNAL_GR_MAX_SM_v1B_05 256 #define NV2080_CTRL_INTERNAL_GR_MAX_SM_v1E_03 240 @@ -140,6 +146,31 @@ typedef struct vmiopd_SM_info { #define NV2080_CTRL_MAX_PCES_v21_0A 32 #define NV2080_CTRL_CE_CAPS_TBL_SIZE_v21_0A 2 +//NV2080_CTRL_PERF_PSTATES_INFO data union enums for r535 code +#define NV2080_CTRL_PERF_PSTATE_VERSION_INVALID_v23_02 0x00 +#define NV2080_CTRL_PERF_PSTATE_VERSION_MODEL_10_v23_02 0xFE +#define NV2080_CTRL_PERF_PSTATE_VERSION_2X_v23_02 0x20 +#define NV2080_CTRL_PERF_PSTATE_VERSION_3X_v23_02 0xFD +#define NV2080_CTRL_PERF_PSTATE_VERSION_30_v23_02 0x30 +#define NV2080_CTRL_PERF_PSTATE_VERSION_35_v23_02 0x35 +#define NV2080_CTRL_PERF_PSTATE_VERSION_40_v23_02 0x40 +#define NV2080_CTRL_PERF_PSTATE_VERSION_PMU_INIT_1X_v23_02 0xFC +#define NV2080_CTRL_PERF_PSTATE_VERSION_70_v23_02 0x70 +#define NV2080_CTRL_PERF_PSTATE_VERSION_DISABLED_v23_02 NV_U8_MAX + +//NV2080_CTRL_PERF_PSTATES_INFO data union enums for chips_a +#define NV2080_CTRL_PERF_PSTATES_TYPE_BASE_v24_01 0x00U +#define NV2080_CTRL_PERF_PSTATES_TYPE_MODEL_10_v24_01 0x01U +#define NV2080_CTRL_PERF_PSTATES_TYPE_2X_v24_01 0x02U +#define NV2080_CTRL_PERF_PSTATES_TYPE_3X_v24_01 0x03U +#define NV2080_CTRL_PERF_PSTATES_TYPE_30_v24_01 0x04U +#define NV2080_CTRL_PERF_PSTATES_TYPE_35_v24_01 0x05U +#define NV2080_CTRL_PERF_PSTATES_TYPE_PMU_INIT_1X_v24_01 0x07U +#define NV2080_CTRL_PERF_PSTATES_TYPE_70_v24_01 0x08U +#define NV2080_CTRL_PERF_PSTATES_TYPE_50_v24_01 0x09U +#define NV2080_CTRL_PERF_PSTATES_TYPE_5X_v24_01 0x0AU +#define NV2080_CTRL_PERF_PSTATES_TYPE_INVALID_v24_01 NV2080_CTRL_BOARDOBJGRP_CLASS_TYPE_INVALID + // Defined this intermediate RM-RPC structure for making RPC call from Guest as // we have the restriction of passing max 4kb of data to plugin and the // NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS is way more than that. @@ -218,6 +249,7 @@ typedef struct VGPU_BSP_CAPS #define NV2080_CTRL_GPU_ECC_UNIT_COUNT_v1A_04 (0x00000014) #define NV2080_CTRL_GPU_ECC_UNIT_COUNT_v1C_09 (0x00000016) #define NV2080_CTRL_GPU_ECC_UNIT_COUNT_v20_03 (0x00000018) +#define NV2080_CTRL_GPU_ECC_UNIT_COUNT_v24_06 (0x00000019) #define NV2080_ENGINE_TYPE_LAST_v18_01 (0x0000002a) #define NV2080_ENGINE_TYPE_LAST_v1C_09 (0x00000034) @@ -226,6 +258,7 @@ typedef struct VGPU_BSP_CAPS #define NV2080_ENGINE_TYPE_COPY_SIZE_v1A_0D (10) #define NV2080_ENGINE_TYPE_COPY_SIZE_v22_00 (10) +#define NV2080_ENGINE_TYPE_COPY_SIZE_v24_09 (64) #define NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE_v1A_0F (0x00000033) #define NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE_v1C_09 (0x00000034) @@ -248,6 +281,7 @@ typedef struct VGPU_BSP_CAPS #define NV2080_CTRL_FB_INFO_MAX_LIST_SIZE_1A_24 0x33 #define NV2080_CTRL_FB_INFO_MAX_LIST_SIZE_1E_01 0x35 #define NV2080_CTRL_FB_INFO_MAX_LIST_SIZE_1F_0F 0x36 +#define NV2080_CTRL_FB_INFO_MAX_LIST_SIZE_24_0A 0x37 #define NV2080_CTRL_PERF_MAX_LIMITS_v1C_0B 0x100 diff --git a/src/nvidia/kernel/inc/vgpu/vgpu_version.h b/src/nvidia/kernel/inc/vgpu/vgpu_version.h index 7ab8ed0300..a28a876eef 100644 --- a/src/nvidia/kernel/inc/vgpu/vgpu_version.h +++ b/src/nvidia/kernel/inc/vgpu/vgpu_version.h @@ -30,8 +30,8 @@ #define RPC_VERSION_FROM_VGX_VERSION(major, minor) ( DRF_NUM(_RPC, _VERSION_NUMBER, _MAJOR, major) | \ DRF_NUM(_RPC, _VERSION_NUMBER, _MINOR, minor)) -#define VGX_MAJOR_VERSION_NUMBER 0x23 -#define VGX_MINOR_VERSION_NUMBER 0x05 +#define VGX_MAJOR_VERSION_NUMBER 0x24 +#define VGX_MINOR_VERSION_NUMBER 0x0A #define VGX_MAJOR_VERSION_NUMBER_VGPU_12_0 0x1A #define VGX_MINOR_VERSION_NUMBER_VGPU_12_0 0x18 @@ -49,6 +49,7 @@ * 2. This is the first break in migration compatibility after a release. */ #define NV_VGPU_GRIDSW_INTERNAL_TO_EXTERNAL_VERSION_MAPPING \ + {{0x24, 0x0}, {0x24, 0x0A}, {0x13, 0x1}}, \ {{0x23, 0x0}, {0x23, 0x05}, {0x12, 0x1}}, \ {{0x22, 0x0}, {0x22, 0x02}, {0x11, 0x1}}, \ {{0x21, 0x0}, {0x21, 0x0C}, {0x10, 0x1}}, \ @@ -95,7 +96,7 @@ /* WARNING: Should be updated with each vGPU release, if there is a break in * migration compatibility during the development of that release. */ -#define NV_VGPU_MAX_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MAJOR 0x12 +#define NV_VGPU_MAX_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MAJOR 0x13 #define NV_VGPU_MAX_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MINOR 0x1 /* WARNING: Should be updated with each vGPU release, if minimum supported diff --git a/src/nvidia/kernel/nvd/nv/nvdctrl.c b/src/nvidia/kernel/nvd/nv/nvdctrl.c index 5a6f697abb..28c0b57926 100644 --- a/src/nvidia/kernel/nvd/nv/nvdctrl.c +++ b/src/nvidia/kernel/nvd/nv/nvdctrl.c @@ -234,6 +234,8 @@ subdeviceCtrlCmdNvdSetNocatJournalData_IMPL { OBJSYS *pSys = SYS_GET_INSTANCE(); Journal *pRcdb = SYS_GET_RCDB(pSys); + OBJGPU* pGpu = GPU_RES_GET_GPU(pSubdevice); + NOCAT_JOURNAL_PARAMS newEntry; switch (pReportParams->dataType) { @@ -242,9 +244,6 @@ subdeviceCtrlCmdNvdSetNocatJournalData_IMPL break; case NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_INSERT_RECORD: - { - NOCAT_JOURNAL_PARAMS newEntry; - portMemSet(&newEntry, 0, sizeof(newEntry)); // fill in the newEntry structure with the data from the insertData. @@ -276,8 +275,7 @@ subdeviceCtrlCmdNvdSetNocatJournalData_IMPL } pRcdb->nocatJournalDescriptor.nocatEventCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_INSERT_RECORDS_IDX]++; rcdbNocatInsertNocatError(NULL, &newEntry); - } - break; + break; case NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_SET_TAG: if ((pReportParams->nocatJournalData.tagData.tag[0] == '\0') || @@ -298,6 +296,21 @@ subdeviceCtrlCmdNvdSetNocatJournalData_IMPL } break; + case NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_RCLOG: + portMemSet(&newEntry, 0, sizeof(newEntry)); + + // fill in the newEntry structure rec type & source data. + newEntry.recType = NV2080_NOCAT_JOURNAL_REC_TYPE_BUGCHECK; + newEntry.pSource = "RCLOG"; + + // point to the payload of the nocat Journal Data for an rclog entry. + newEntry.pDiagBuffer = (void*)&pReportParams->nocatJournalData.rclog; + newEntry.diagBufferLen = sizeof(pReportParams->nocatJournalData.rclog); + + rcdbNocatInsertNocatError(pGpu, &newEntry); + break; + + default: break; } diff --git a/src/nvidia/kernel/vgpu/nv/rpc.c b/src/nvidia/kernel/vgpu/nv/rpc.c index 30a4964a7a..18189004e7 100644 --- a/src/nvidia/kernel/vgpu/nv/rpc.c +++ b/src/nvidia/kernel/vgpu/nv/rpc.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2008-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2008-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -154,7 +154,6 @@ static NV_STATUS _issueRpcAndWait(OBJGPU *pGpu, OBJRPC *pRpc) // should not be called in broadcast mode NV_ASSERT_OR_RETURN(!gpumgrGetBcEnabledStatus(pGpu), NV_ERR_INVALID_STATE); - NV_CHECK(LEVEL_ERROR, rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); if (bProfileRPC) { @@ -1303,6 +1302,10 @@ NV_STATUS rpcGspSetSystemInfo_v17_00 // Cache MNOC interface support rpcInfo->bMnocAvailable = pKernelBif->bMnocAvailable; + + // Cache FLR and 64b Bar0 support + rpcInfo->bFlrSupported = pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_FLR_SUPPORTED); + rpcInfo->b64bBar0Supported = pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_64BIT_BAR0_SUPPORTED); } if (IS_SIMULATION(pGpu)) @@ -1587,7 +1590,7 @@ NV_STATUS rpcRmApiControl_GSP GPU_LOCK_FLAGS_SAFE_LOCK_UPGRADE, RM_LOCK_MODULES_RPC, &gpuMaskRelease)); } - rmapiutilGetControlInfo(cmd, &ctrlFlags, &ctrlAccessRight); + (void) rmapiutilGetControlInfo(cmd, &ctrlFlags, &ctrlAccessRight); bCacheable = rmapiControlIsCacheable(ctrlFlags, ctrlAccessRight, NV_TRUE); pCallContext = resservGetTlsCallContext(); diff --git a/src/nvidia/src/kernel/compute/fabric.c b/src/nvidia/src/kernel/compute/fabric.c index e1e11dfa7f..84c3f33373 100644 --- a/src/nvidia/src/kernel/compute/fabric.c +++ b/src/nvidia/src/kernel/compute/fabric.c @@ -260,14 +260,17 @@ fabricConstruct_IMPL { NV_STATUS status = NV_OK; - pFabric->pMulticastFabricOpsMutex = portSyncMutexCreate(portMemAllocatorGetGlobalNonPaged()); + pFabric->pMulticastFabricOpsMutex = + portSyncMutexCreate(portMemAllocatorGetGlobalNonPaged()); + if (pFabric->pMulticastFabricOpsMutex == NULL) { status = NV_ERR_NO_MEMORY; goto fail; } - multimapInit(&pFabric->fabricMulticastCache, portMemAllocatorGetGlobalNonPaged()); + multimapInit(&pFabric->fabricMulticastCache, + portMemAllocatorGetGlobalNonPaged()); return NV_OK; @@ -293,32 +296,6 @@ fabricDestruct_IMPL } -NV_STATUS -fabricInitInbandMsgHdr -( - nvlink_inband_msg_header_t *pMsgHdr, - NvU32 type, - NvU32 len -) -{ - NV_STATUS status; - - portMemSet(pMsgHdr, 0, sizeof(*pMsgHdr)); - - status = osGetRandomBytes((NvU8 *)&pMsgHdr->requestId, - sizeof(pMsgHdr->requestId)); - if (status != NV_OK) - { - return status; - } - - pMsgHdr->magicId = NVLINK_INBAND_MSG_MAGIC_ID_FM; - pMsgHdr->type = type; - pMsgHdr->length = len; - - return NV_OK; -} - void fabricMulticastWaitOnTeamCleanupCallback ( @@ -332,7 +309,7 @@ fabricMulticastWaitOnTeamCleanupCallback fabricMulticastFabricOpsMutexAcquire(pFabric); pWq = (OS_WAIT_QUEUE *)fabricMulticastCleanupCacheGetUnderLock_IMPL(pFabric, - inbandReqId); + inbandReqId); fabricMulticastFabricOpsMutexRelease(pFabric); if (pWq == NULL) diff --git a/src/nvidia/src/kernel/compute/fm_session_api.c b/src/nvidia/src/kernel/compute/fm_session_api.c index 8d2d4b669f..c03ac0cbf4 100644 --- a/src/nvidia/src/kernel/compute/fm_session_api.c +++ b/src/nvidia/src/kernel/compute/fm_session_api.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -114,7 +114,8 @@ fmsessionapiConstruct_IMPL osRmCapInitDescriptor(&pFmSessionApi->dupedCapDescriptor); - if ((pCallContext->secInfo.privLevel >= RS_PRIV_LEVEL_KERNEL) && !RMCFG_FEATURE_PLATFORM_MODS) + if ((pCallContext->secInfo.privLevel >= RS_PRIV_LEVEL_KERNEL) + && !RMCFG_FEATURE_PLATFORM_MODS) { NV_PRINTF(LEVEL_ERROR, "only supported for usermode clients\n"); @@ -155,7 +156,6 @@ fmsessionapiConstruct_IMPL if (pFabric != NULL) { - fabricSetFmSessionFlags(pFabric, pAllocParams->flags); } @@ -212,4 +212,3 @@ fmsessionapiCtrlCmdClearFmState_IMPL return NV_OK; } - diff --git a/src/nvidia/src/kernel/core/bin_data_pvt.h b/src/nvidia/src/kernel/core/bin_data_pvt.h index 2ef4b9ee7b..a24181287a 100644 --- a/src/nvidia/src/kernel/core/bin_data_pvt.h +++ b/src/nvidia/src/kernel/core/bin_data_pvt.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2016-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2016-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -81,7 +81,7 @@ struct BINDATA_RUNTIME_INFO // #define BINDATA_IS_MUTABLE RMCFG_FEATURE_PLATFORM_GSP #if BINDATA_IS_MUTABLE -#define BINDATA_CONST +#define BINDATA_CONST __attribute__((section(".bindata"))) #else #define BINDATA_CONST const #endif diff --git a/src/nvidia/src/kernel/core/hal_mgr.c b/src/nvidia/src/kernel/core/hal_mgr.c index 7be422a9f0..3f59354858 100644 --- a/src/nvidia/src/kernel/core/hal_mgr.c +++ b/src/nvidia/src/kernel/core/hal_mgr.c @@ -186,7 +186,7 @@ halmgrGetHalForGpu_IMPL #else // NV_PRINTF_STRINGS_ALLOWED NV_PRINTF(LEVEL_INFO, "Matching 0x%x to %u\n", - pPmcBoot42 ? "PMC_BOOT_42" : "PMC_BOOT_0", + pPmcBoot42 ? pPmcBoot42 : pPmcBoot0, halImpl); #endif // NV_PRINTF_STRINGS_ALLOWED diff --git a/src/nvidia/src/kernel/core/locks.c b/src/nvidia/src/kernel/core/locks.c index 0a013ea474..77ceede7e6 100644 --- a/src/nvidia/src/kernel/core/locks.c +++ b/src/nvidia/src/kernel/core/locks.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -40,6 +40,7 @@ #include "kernel/gpu/intr/intr.h" #include #include "gpu/disp/kern_disp.h" +#include "ctrl/ctrl0000/ctrl0000system.h" // // GPU lock @@ -121,6 +122,16 @@ typedef struct // Lock call trace info. // LOCK_TRACE_INFO traceInfo; + + // + // Total time spent waiting to acquire GPU locks. + // + volatile NvU64 totalWaitTime; + + // + // Total time spent holding GPU locks. + // + volatile NvU64 totalHoldTime; } GPULOCKINFO; static GPULOCKINFO rmGpuLockInfo; @@ -473,6 +484,7 @@ static void _gpuLocksAcquireDisableInterrupts(NvU32 gpuInst, NvU32 flags) static NV_STATUS _rmGpuLocksAcquire(NvU32 gpuMask, NvU32 flags, NvU32 module, void *ra, NvU32 *pGpuLockedMask) { + OBJSYS *pSys = SYS_GET_INSTANCE(); NV_STATUS status = NV_OK; NvU32 gpuInst; NvU32 gpuMaskLocked = 0; @@ -483,6 +495,7 @@ _rmGpuLocksAcquire(NvU32 gpuMask, NvU32 flags, NvU32 module, void *ra, NvU32 *pG NvU64 priority = 0; NvU64 priorityPrev = 0; NvU64 timestamp; + NvU64 startWaitTime; NvBool bLockAll = NV_FALSE; bHighIrql = (portSyncExSafeToSleep() == NV_FALSE); @@ -519,7 +532,6 @@ _rmGpuLocksAcquire(NvU32 gpuMask, NvU32 flags, NvU32 module, void *ra, NvU32 *pG // if ((flags & GPU_LOCK_FLAGS_READ) && (module != RM_LOCK_MODULES_NONE)) { - OBJSYS *pSys = SYS_GET_INSTANCE(); if ((pSys->gpuLockModuleMask & NVBIT(module)) == 0) { flags &= ~RMAPI_LOCK_FLAGS_READ; @@ -616,6 +628,10 @@ _rmGpuLocksAcquire(NvU32 gpuMask, NvU32 flags, NvU32 module, void *ra, NvU32 *pG } } + // Get start wait time if measuring lock times + if (pSys->getProperty(pSys, PDB_PROP_SYS_RM_LOCK_TIME_COLLECT)) + osGetCurrentTick(&startWaitTime); + // // Now (attempt) to acquire the locks... // @@ -744,6 +760,14 @@ _rmGpuLocksAcquire(NvU32 gpuMask, NvU32 flags, NvU32 module, void *ra, NvU32 *pG ; } + // Update total GPU lock wait time if measuring lock times + if (status == NV_OK && pSys->getProperty(pSys, PDB_PROP_SYS_RM_LOCK_TIME_COLLECT)) + { + osGetCurrentTick(×tamp); + + portAtomicExAddU64(&rmGpuLockInfo.totalWaitTime, timestamp - startWaitTime); + } + // update gpusLockedMask rmGpuLockInfo.gpusLockedMask |= gpuMaskLocked; @@ -1200,6 +1224,7 @@ static NvU32 _rmGpuLocksRelease(NvU32 gpuMask, NvU32 flags, OBJGPU *pDpcGpu, void *ra) { static volatile NvU32 bug200413011_WAR_WakeUpMask; + OBJSYS *pSys = SYS_GET_INSTANCE(); GPULOCK *pGpuLock; NvU32 gpuMaskWakeup = 0; NvU32 gpuInst; @@ -1210,6 +1235,7 @@ _rmGpuLocksRelease(NvU32 gpuMask, NvU32 flags, OBJGPU *pDpcGpu, void *ra) NvU64 priority = 0; NvU64 priorityPrev = 0; NvU64 timestamp; + NvU64 startHoldTime = 0; NV_STATUS status; // @@ -1283,6 +1309,10 @@ _rmGpuLocksRelease(NvU32 gpuMask, NvU32 flags, OBJGPU *pDpcGpu, void *ra) pGpuLock = &rmGpuLockInfo.gpuLocks[gpuInst]; + // Start of GPU lock hold time is the first acquired GPU lock + if (pSys->getProperty(pSys, PDB_PROP_SYS_RM_LOCK_TIME_COLLECT)) + startHoldTime = pGpuLock->timestamp; + if (pGpuLock->count < 0) { if (!pGpuLock->bSignaled) @@ -1408,6 +1438,17 @@ _rmGpuLocksRelease(NvU32 gpuMask, NvU32 flags, OBJGPU *pDpcGpu, void *ra) status = NV_SEMA_RELEASE_SUCCEED; done: + // Update total GPU lock hold time if measuring lock times + if (status == NV_SEMA_RELEASE_SUCCEED && + pSys->getProperty(pSys, PDB_PROP_SYS_RM_LOCK_TIME_COLLECT) && + startHoldTime > 0) + { + osGetCurrentTick(×tamp); + + portAtomicExAddU64(&rmGpuLockInfo.totalHoldTime, + timestamp - startHoldTime); + } + threadPriorityRestore(); return status; @@ -1728,6 +1769,18 @@ rmGpuLockSetOwner(OS_THREAD_HANDLE threadId) return NV_OK; } +// +// rmGpuLockGetTimes +// +// Retrieve time spent waiting and holding GPU locks. +// +void +rmGpuLockGetTimes(NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS *pParams) +{ + pParams->holdGpuLock = rmGpuLockInfo.totalHoldTime; + pParams->waitGpuLock = rmGpuLockInfo.totalWaitTime; +} + // // rmDeviceGpuLockSetOwner // diff --git a/src/nvidia/src/kernel/core/system.c b/src/nvidia/src/kernel/core/system.c index 5c6e10dde6..6ae4010399 100644 --- a/src/nvidia/src/kernel/core/system.c +++ b/src/nvidia/src/kernel/core/system.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -153,6 +153,7 @@ sysConstruct_IMPL(OBJSYS *pSys) return NV_OK; failed: + _sysDeleteChildObjects(pSys); g_pSys = NULL; @@ -168,6 +169,7 @@ sysConstruct_IMPL(OBJSYS *pSys) void sysDestruct_IMPL(OBJSYS *pSys) { + // // Any of these operations might fail but go ahead and // attempt to free remaining resources before complaining. @@ -328,6 +330,12 @@ _sysRegistryOverrideResourceServer pSys->setProperty(pSys, PDB_PROP_SYS_CLIENT_HANDLE_LOOKUP, !!data32); } + if (osReadRegistryDword(pGpu, NV_REG_STR_RM_LOCK_TIME_COLLECT, + &data32) == NV_OK) + { + pSys->setProperty(pSys, PDB_PROP_SYS_RM_LOCK_TIME_COLLECT, !!data32); + } + if (osReadRegistryDword(pGpu, NV_REG_STR_RM_CLIENT_LIST_DEFERRED_FREE, &data32) == NV_OK) { @@ -339,6 +347,7 @@ _sysRegistryOverrideResourceServer { pSys->clientListDeferredFreeLimit = data32; } + } static void diff --git a/src/nvidia/src/kernel/core/thread_state.c b/src/nvidia/src/kernel/core/thread_state.c index fb7b37829f..50255109ae 100644 --- a/src/nvidia/src/kernel/core/thread_state.c +++ b/src/nvidia/src/kernel/core/thread_state.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -157,6 +157,7 @@ NV_STATUS threadStateGlobalAlloc(void) // Init the thread sequencer id counter to 0. threadStateDatabase.threadSeqCntr = 0; + threadStateDatabase.gspIsrThreadSeqCntr = 0; threadStateDatabase.spinlock = portSyncSpinlockCreate(portMemAllocatorGetGlobalNonPaged()); if (threadStateDatabase.spinlock == NULL) diff --git a/src/nvidia/src/kernel/diagnostics/journal.c b/src/nvidia/src/kernel/diagnostics/journal.c index 3dfa2192e8..e9de9c9006 100644 --- a/src/nvidia/src/kernel/diagnostics/journal.c +++ b/src/nvidia/src/kernel/diagnostics/journal.c @@ -713,10 +713,6 @@ rcdbGetRcDiagRecBoundaries_IMPL foundEnd = foundStart; } break; - - default: // should not happen.... - return NV_ERR_GENERIC; - break; } } // checking end is sufficient, because end can't be set w/o start being set first. @@ -2827,7 +2823,6 @@ rcdbAddRmGpuDump // from the interrupt context anyway, so queue a work item to come back // later and try again. // - OBJOS *pOS = SYS_GET_OS(pSys); NvU32 *pGpuInstance = NULL; // @@ -2859,8 +2854,8 @@ rcdbAddRmGpuDump } *pGpuInstance = gpuGetInstance(pGpu); - status = pOS->osQueueSystemWorkItem(_rcdbAddRmGpuDumpCallback, - pGpuInstance); + status = osQueueSystemWorkItem(_rcdbAddRmGpuDumpCallback, + pGpuInstance); if (status != NV_OK) { portMemFree(pGpuInstance); @@ -3630,7 +3625,9 @@ void rcdbInitNocatGpuCache_IMPL(OBJGPU *pGpu) Journal *pRcdb = SYS_GET_RCDB(pSys); #if NOCAT_PROBE_FB_MEMORY NvU8 *pCpuPtr; + NV_STATUS status; #endif + if (pGpu == NULL) { return; @@ -3647,7 +3644,9 @@ void rcdbInitNocatGpuCache_IMPL(OBJGPU *pGpu) { memdescCreateExisting(&pGpu->nocatGpuCache.fbTestMemDesc, pGpu, NOCAT_FBSIZETESTED, ADDR_FBMEM, NV_MEMORY_UNCACHED, MEMDESC_FLAGS_NONE); - if (memdescAlloc(&pGpu->nocatGpuCache.fbTestMemDesc) != NV_OK) + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_102, + (&pGpu->nocatGpuCache.fbTestMemDesc)); + if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "Could not allocate vidmem for NOCAT bar2 testing\n"); return; diff --git a/src/nvidia/src/kernel/diagnostics/nv_debug_dump.c b/src/nvidia/src/kernel/diagnostics/nv_debug_dump.c index f0088b404d..b5f3bc5e2e 100644 --- a/src/nvidia/src/kernel/diagnostics/nv_debug_dump.c +++ b/src/nvidia/src/kernel/diagnostics/nv_debug_dump.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -679,7 +679,8 @@ nvdAllocDebugBuffer_IMPL } // Allocate backing memory - status = memdescAlloc(pMemDesc); + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_53, + pMemDesc); if (status != NV_OK) { // Destroy the memory descriptor diff --git a/src/nvidia/src/kernel/diagnostics/nvlog_printf.c b/src/nvidia/src/kernel/diagnostics/nvlog_printf.c index 32a2c1ec58..6dfbb484ec 100644 --- a/src/nvidia/src/kernel/diagnostics/nvlog_printf.c +++ b/src/nvidia/src/kernel/diagnostics/nvlog_printf.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2002-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2002-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -225,7 +225,11 @@ _nvDbgPrepareString #if PORT_IS_FUNC_SUPPORTED(portDbgExPrintfLevel) static NvU32 _nvDbgLevelToPlatformLevel(NvBool bForce, NvU32 level) { +#if NVOS_IS_UNIX + return level; +#else return bForce ? LEVEL_FATAL : level; +#endif } #endif diff --git a/src/nvidia/src/kernel/disp/disp_sw.c b/src/nvidia/src/kernel/disp/disp_sw.c index 57d12af6f4..03ce58f7ca 100644 --- a/src/nvidia/src/kernel/disp/disp_sw.c +++ b/src/nvidia/src/kernel/disp/disp_sw.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -134,8 +134,7 @@ NV_STATUS dispswReleaseSemaphoreAndNotifierFill NvU32 releasevalue, NvU32 flags, NvU32 completionStatus, - RsClient *pClient, - NvHandle hEvent + Device *pDevice ) { CLI_DMA_MAPPING_INFO *pDmaMappingInfo; @@ -144,8 +143,8 @@ NV_STATUS dispswReleaseSemaphoreAndNotifierFill if (flags & F_SEMAPHORE_ADDR_VALID) { - bFound = CliGetDmaMappingInfo(pClient, - hEvent, + bFound = CliGetDmaMappingInfo(RES_GET_CLIENT(pDevice), + RES_GET_HANDLE(pDevice), vaSpace, gpuVA, gpumgrGetDeviceGpuMask(pGpu->deviceInstance), @@ -156,7 +155,7 @@ NV_STATUS dispswReleaseSemaphoreAndNotifierFill else if (flags & F_SEMAPHORE_RELEASE) { status = semaphoreFillGPUVA(pGpu, - pClient, + pDevice, vaSpace, gpuVA, releasevalue, @@ -167,7 +166,7 @@ NV_STATUS dispswReleaseSemaphoreAndNotifierFill else if (flags & F_NOTIFIER_FILL) { status = notifyFillNotifierGPUVA(pGpu, - pClient, + pDevice, vaSpace, gpuVA, releasevalue, /* Info32 */ diff --git a/src/nvidia/src/kernel/gpu/arch/ampere/kern_gpu_ga100.c b/src/nvidia/src/kernel/gpu/arch/ampere/kern_gpu_ga100.c index 3e7c75d7d7..d8a1137aaa 100644 --- a/src/nvidia/src/kernel/gpu/arch/ampere/kern_gpu_ga100.c +++ b/src/nvidia/src/kernel/gpu/arch/ampere/kern_gpu_ga100.c @@ -52,15 +52,13 @@ gpuFuseSupportsDisplay_GA100 * @return NV_OK if success, else appropriate NV_STATUS code */ NV_STATUS -gpuClearFbhubPoisonIntrForBug2924523_GA100_KERNEL +gpuClearFbhubPoisonIntrForBug2924523_GA100 ( OBJGPU *pGpu ) { + // INTR module is not stateloaded at gpuPostConstruct, so use HW default NvU32 intrVector = NV_PFB_FBHUB_POISON_INTR_VECTOR_HW_INIT; - NvU32 reg = NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(intrVector); - NvU32 bit = NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_BIT(intrVector); - NvV32 intr = 0; if (pGpu == NULL) return NV_OK; @@ -70,20 +68,10 @@ gpuClearFbhubPoisonIntrForBug2924523_GA100_KERNEL // to VBIOS IFR on GA100. If yes, clear the FBHUB Interrupt. This WAR is // required for Bug 2924523 as VBIOS IFR causes FBHUB Poison intr. // - intr = GPU_VREG_RD32_EX(pGpu, - NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF(reg), - NULL) & - NVBIT(bit); - - if (intr != 0) + if (intrIsVectorPending_HAL(pGpu, GPU_GET_INTR(pGpu), intrVector, NULL)) { - NV_PRINTF(LEVEL_ERROR, "FBHUB Interrupt detected = 0x%X. Clearing it.\n", intr); - - // Clear FBHUB Poison interrupt - GPU_VREG_WR32_EX(pGpu, - NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF(reg), - NVBIT(bit), - NULL); + NV_PRINTF(LEVEL_ERROR, "FBHUB Interrupt detected. Clearing it.\n"); + intrClearLeafVector_HAL(pGpu, GPU_GET_INTR(pGpu), intrVector, NULL); } return NV_OK; diff --git a/src/nvidia/src/kernel/gpu/arch/turing/kern_gpu_tu102.c b/src/nvidia/src/kernel/gpu/arch/turing/kern_gpu_tu102.c index 8ad221cb06..f251f423ab 100644 --- a/src/nvidia/src/kernel/gpu/arch/turing/kern_gpu_tu102.c +++ b/src/nvidia/src/kernel/gpu/arch/turing/kern_gpu_tu102.c @@ -62,6 +62,7 @@ gpuGetSriovCaps_TU102 pParams->bSriovHeavyEnabled = gpuIsWarBug200577889SriovHeavyEnabled(pGpu); pParams->bEmulateVFBar0TlbInvalidationRegister = pGpu->getProperty(pGpu, PDB_PROP_GPU_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE); pParams->bClientRmAllocatedCtxBuffer = gpuIsClientRmAllocatedCtxBufferEnabled(pGpu); + pParams->bNonPowerOf2ChannelCountSupported = gpuIsNonPowerOf2ChannelCountSupported(pGpu); return NV_OK; } diff --git a/src/nvidia/src/kernel/gpu/bif/arch/ampere/kernel_bif_ga100.c b/src/nvidia/src/kernel/gpu/bif/arch/ampere/kernel_bif_ga100.c index a0ac5cdc8b..771b9ce3b4 100644 --- a/src/nvidia/src/kernel/gpu/bif/arch/ampere/kernel_bif_ga100.c +++ b/src/nvidia/src/kernel/gpu/bif/arch/ampere/kernel_bif_ga100.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -24,8 +24,9 @@ /* ------------------------ Includes ---------------------------------------- */ #include "gpu/bif/kernel_bif.h" -#include "ampere/ga100/dev_nv_xve_addendum.h" - +#include "published/ampere/ga100/dev_nv_xve_addendum.h" +#include "published/ampere/ga100/dev_nv_xve.h" +#include "published/ampere/ga100/dev_boot.h" /* ------------------------ Public Functions -------------------------------- */ @@ -70,4 +71,262 @@ kbifInitRelaxedOrderingFromEmulatedConfigSpace_GA100 NvBool roEnabled = DRF_VAL(_XVE, _PASSTHROUGH_EMULATED_CONFIG, _RELAXED_ORDERING_ENABLE, passthroughEmulatedConfig); pKernelBif->setProperty(pKernelBif, PDB_PROP_KBIF_PCIE_RELAXED_ORDERING_SET_IN_EMULATED_CONFIG_SPACE, roEnabled); -} \ No newline at end of file +} + +/*! + * @brief Check and cache 64b BAR0 support + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif Kernel BIF object pointer + * + */ +void +kbifCache64bBar0Support_GA100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + NvU32 regVal = 0; + + // Read config register + if (GPU_BUS_CFG_RD32(pGpu, NV_XVE_DBG_CYA_0, + ®Val) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Unable to read NV_XVE_DBG_CYA_0\n"); + return; + } + + // Check if 64b BAR0 is supported + if (FLD_TEST_DRF(_XVE, _DBG_CYA_0, _BAR0_ADDR_WIDTH, + _64BIT, regVal)) + { + pKernelBif->setProperty(pKernelBif, PDB_PROP_KBIF_64BIT_BAR0_SUPPORTED, NV_TRUE); + } +} + +/*! + * @brief Restore the BAR0 register from the given config space buffer + * BAR0 register restore has to use the config cycle write. + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif Pointer to KernelBif object + * @param[in] handle PCI handle for GPU + * @param[in] bufConfigSpace Stored config space + */ +void +kbifRestoreBar0_GA100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif, + void *handle, + NvU32 *bufConfigSpace +) +{ + NvU32 bar0LoRegOffset; + NvU32 bar0HiRegOffset; + NvU32 *pBarRegOffsets = pKernelBif->barRegOffsets; + + if (pBarRegOffsets == NULL) + { + NV_PRINTF(LEVEL_ERROR, "pBarRegOffsets is NULL!\n"); + NV_ASSERT(pBarRegOffsets); + return; + } + + bar0LoRegOffset = pBarRegOffsets[NV_XVE_BAR0_LO_INDEX]; + bar0HiRegOffset = pBarRegOffsets[NV_XVE_BAR0_HI_INDEX]; + + osPciWriteDword(handle, bar0LoRegOffset, + bufConfigSpace[bar0LoRegOffset/sizeof(NvU32)]); + if (pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_64BIT_BAR0_SUPPORTED)) + { + osPciWriteDword(handle, bar0HiRegOffset, + bufConfigSpace[bar0HiRegOffset/sizeof(NvU32)]); + } +} + + +/*! + * @brief Check if any of the BAR register reads returns a valid value. + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif KernelBif object pointer + * + * @returns NV_TRUE if any BAR register read returns a valid value + * NV_FALSE if all the BAR registers return an invalid values + */ +NvBool +kbifAnyBarsAreValid_GA100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + NvU8 bus = gpuGetBus(pGpu); + NvU8 device = gpuGetDevice(pGpu); + NvU32 domain = gpuGetDomain(pGpu); + NvU16 vendorId; + NvU16 deviceId; + void *handle; + NvU32 bar0LoRegOffset; + NvU32 bar0HiRegOffset; + NvU32 bar1LoRegOffset; + NvU32 bar1HiRegOffset; + NvU32 *pBarRegOffsets = pKernelBif->barRegOffsets; + + if (pBarRegOffsets == NULL) + { + NV_PRINTF(LEVEL_ERROR, "pBarRegOffsets is NULL!\n"); + NV_ASSERT(pBarRegOffsets); + return NV_FALSE; + } + + bar0LoRegOffset = pBarRegOffsets[NV_XVE_BAR0_LO_INDEX]; + bar0HiRegOffset = pBarRegOffsets[NV_XVE_BAR0_HI_INDEX]; + bar1LoRegOffset = pBarRegOffsets[NV_XVE_BAR1_LO_INDEX]; + bar1HiRegOffset = pBarRegOffsets[NV_XVE_BAR1_HI_INDEX]; + + handle = osPciInitHandle(domain, bus, device, 0, &vendorId, &deviceId); + + // BAR0_HI register is valid only if 64b BAR0 is enabled + if (pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_64BIT_BAR0_SUPPORTED)) + { + if ((osPciReadDword(handle, bar0LoRegOffset) == + pKernelBif->cacheData.gpuBootConfigSpace[bar0LoRegOffset/sizeof(NvU32)]) && + (osPciReadDword(handle, bar0HiRegOffset) == + pKernelBif->cacheData.gpuBootConfigSpace[bar0HiRegOffset/sizeof(NvU32)])) + { + // BAR0 is valid + return NV_TRUE; + } + } + else + { + if (osPciReadDword(handle, bar0LoRegOffset) == + pKernelBif->cacheData.gpuBootConfigSpace[bar0LoRegOffset/sizeof(NvU32)]) + { + // BAR0 is valid + return NV_TRUE; + } + } + + // BAR1_LO and BAR1_HI registers are valid even if 64b BAR0 is disabled + if ((osPciReadDword(handle, bar1LoRegOffset) == + pKernelBif->cacheData.gpuBootConfigSpace[bar1LoRegOffset/sizeof(NvU32)]) && + (osPciReadDword(handle, bar1HiRegOffset) == + pKernelBif->cacheData.gpuBootConfigSpace[bar1HiRegOffset/sizeof(NvU32)])) + { + // BAR1 is valid + return NV_TRUE; + } + + return NV_FALSE; +} + + +/*! + * @brief Try restoring BAR registers and command register using config cycles + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif KernelBif object pointer + * + * @returns NV_OK on success + * NV_ERR_INVALID_READ if the register read returns unexpected value + */ +NV_STATUS +kbifRestoreBarsAndCommand_GA100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + void *handle; + NvU8 bus = gpuGetBus(pGpu); + NvU8 device = gpuGetDevice(pGpu); + NvU32 domain = gpuGetDomain(pGpu); + NvU16 vendorId; + NvU16 deviceId; + NvU32 *pBarRegOffsets = pKernelBif->barRegOffsets; + NvU32 i; + + handle = osPciInitHandle(domain, bus, device, 0, &vendorId, &deviceId); + + // Restore all BAR registers + for (i = 0; i < KBIF_NUM_BAR_OFFSET_ENTRIES; i++) + { + if (pBarRegOffsets[i] != KBIF_INVALID_BAR_REG_OFFSET) + { + osPciWriteDword(handle, pBarRegOffsets[i], + pKernelBif->cacheData.gpuBootConfigSpace[pBarRegOffsets[i]/sizeof(NvU32)]); + } + } + + // Restore Device Control register + osPciWriteDword(handle, NV_XVE_DEV_CTRL, + pKernelBif->cacheData.gpuBootConfigSpace[NV_XVE_DEV_CTRL/sizeof(NvU32)]); + + if (GPU_REG_RD32(pGpu, NV_PMC_BOOT_0) != pGpu->chipId0) + { + return NV_ERR_INVALID_READ; + } + + return NV_OK; +} + + +/*! + * @brief Store config space offsets of BAR registers into the KernelBif object. + * Keeping this sub-routine chip specific since NV_XVE_BAR*_LO/HI_INDEX could + * be changed for future chips + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif KernelBif object pointer + * @param[in] firstBarRegOffset Offset of first BAR register into the config space + */ +void +kbifStoreBarRegOffsets_GA100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif, + NvU32 firstBarRegOffset +) +{ + NvU32 i; + NvU32 currOffset; + NvU32 *pBarRegOffsets = pKernelBif->barRegOffsets; + + + // + // This array will have entries corresponding to + // BAR0_LO, BAR0_HI, BAR1_LO, BAR1_HI, BAR2_LO, BAR2_HI and BAR3 + // If 64b BAR0 is NOT enabled, BAR0_HI register is non-existant + // So for 64b BAR0 disabled case and if firstBarRegoffset is 0x10, this + // regoffset array will be {0x10, 0xFFFF, 0x14, 0x18, 0x1C, 0x20, 0x24} + // If 64b BAR0 is enabled, BAR3 register is non-existant. So in this case + // assuming firstBarRegoffset of 0x10, regoffsetArray will be + // {0x10, 0x14, 0x18, 0x1C, 0x20, 0x24, 0xFFFF} + // + currOffset = firstBarRegOffset; + for (i = 0; i < KBIF_NUM_BAR_OFFSET_ENTRIES; i++) + { + // If 64b BAR0 is NOT enabled, BAR0_HI register is non-existant + if ((i == NV_XVE_BAR0_HI_INDEX) && + pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_64BIT_BAR0_SUPPORTED)) + { + pBarRegOffsets[i] = KBIF_INVALID_BAR_REG_OFFSET; + continue; + } + + // If 64b BAR0 is enabled, BAR3 register is non-existant + if ((i == NV_XVE_BAR3_INDEX) && + pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_64BIT_BAR0_SUPPORTED)) + { + pBarRegOffsets[i] = KBIF_INVALID_BAR_REG_OFFSET; + continue; + } + + pBarRegOffsets[i] = currOffset; + currOffset = currOffset + 4; + } +} diff --git a/src/nvidia/src/kernel/gpu/bif/arch/ampere/kernel_bif_ga102.c b/src/nvidia/src/kernel/gpu/bif/arch/ampere/kernel_bif_ga102.c new file mode 100644 index 0000000000..fee7be7640 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/bif/arch/ampere/kernel_bif_ga102.c @@ -0,0 +1,83 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +/* ------------------------ Includes ---------------------------------------- */ +#include "gpu/bif/kernel_bif.h" +#include "published/ampere/ga102/dev_nv_pcfg_xve_regmap.h" + +// XVE register map for PCIe config space +static const NvU32 xveRegMapValid[] = NV_PCFG_XVE_REGISTER_VALID_MAP; +static const NvU32 xveRegMapWrite[] = NV_PCFG_XVE_REGISTER_WR_MAP; + +/* ------------------------ Public Functions -------------------------------- */ + +/*! + * This function setups the xve register map pointers + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif Pointer to KernelBif object + * @param[in] func PCIe function number + * + * @return 'NV_OK' if successful, an RM error code otherwise. + */ +NV_STATUS +kbifInitXveRegMap_GA102 +( + OBJGPU *pGpu, + KernelBif *pKernelBif, + NvU8 func +) +{ + extern NvU32 kbifInitXveRegMap_GM107(OBJGPU *pGpu, KernelBif *pKernelBif, NvU8 func); + NV_STATUS status = NV_OK; + NvU32 controlSize = 0; + + if (func == 0) + { + pKernelBif->xveRegmapRef[0].nFunc = 0; + pKernelBif->xveRegmapRef[0].xveRegMapValid = xveRegMapValid; + pKernelBif->xveRegmapRef[0].xveRegMapWrite = xveRegMapWrite; + pKernelBif->xveRegmapRef[0].numXveRegMapValid = sizeof(xveRegMapValid)/sizeof(xveRegMapValid[0]); + pKernelBif->xveRegmapRef[0].numXveRegMapWrite = sizeof(xveRegMapWrite)/sizeof(xveRegMapWrite[0]); + pKernelBif->xveRegmapRef[0].bufBootConfigSpace = pKernelBif->cacheData.gpuBootConfigSpace; + // Each MSIX table entry is 4 NvU32s + controlSize = kbifGetMSIXTableVectorControlSize_HAL(pGpu, pKernelBif); + if (pKernelBif->xveRegmapRef[0].bufMsixTable == NULL) + pKernelBif->xveRegmapRef[0].bufMsixTable = portMemAllocNonPaged(controlSize * 4 * sizeof(NvU32)); + NV_ASSERT_OR_RETURN(pKernelBif->xveRegmapRef[0].bufMsixTable != NULL, NV_ERR_NO_MEMORY); + } + else if (func == 1) + { + // Init regmap for Fn1 using older HAL + status = kbifInitXveRegMap_GM107(pGpu, pKernelBif, 1); + } + else + { + NV_PRINTF(LEVEL_ERROR, "Invalid argument, func: %d.\n", func); + NV_ASSERT(0); + status = NV_ERR_INVALID_ARGUMENT; + } + + return status; +} diff --git a/src/nvidia/src/kernel/gpu/bif/arch/hopper/kernel_bif_gh100.c b/src/nvidia/src/kernel/gpu/bif/arch/hopper/kernel_bif_gh100.c index b3c791cedc..c19dd71c19 100644 --- a/src/nvidia/src/kernel/gpu/bif/arch/hopper/kernel_bif_gh100.c +++ b/src/nvidia/src/kernel/gpu/bif/arch/hopper/kernel_bif_gh100.c @@ -34,6 +34,8 @@ #include "published/hopper/gh100/dev_xtl_ep_pri.h" #include "published/hopper/gh100/dev_xtl_ep_pcfg_gpu.h" #include "published/hopper/gh100/hwproject.h" +#include "published/hopper/gh100/dev_pmc.h" +#include "published/hopper/gh100/dev_vm.h" #include "os/os.h" @@ -732,6 +734,87 @@ kbifGetBusOptionsAddr_GH100 return status; } +/*! + * @brief Returns size of MSIX vector control table + * + * @param pGpu OBJGPU pointer + * @param pKernelBif Kernel BIF object pointer + */ +NvU32 +kbifGetMSIXTableVectorControlSize_GH100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + return NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL__SIZE_1; +} + + +/*! + * @brief Check and cache Function level reset support + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif Kernel BIF object pointer + * + */ +void +kbifCacheFlrSupport_GH100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + NvU32 regVal = 0; + + // Read config register + if (GPU_BUS_CFG_CYCLE_RD32(pGpu, NV_EP_PCFG_GPU_DEVICE_CAPABILITIES, + ®Val) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Unable to read NV_EP_PCFG_GPU_DEVICE_CAPABILITIES\n"); + return; + } + + // Check if FLR is supported + if (FLD_TEST_DRF(_EP_PCFG_GPU, _DEVICE_CAPABILITIES, _FUNCTION_LEVEL_RESET_CAPABILITY, + _SUPPORTED, regVal)) + { + pKernelBif->setProperty(pKernelBif, PDB_PROP_KBIF_FLR_SUPPORTED, NV_TRUE); + } +} + +/*! + * @brief Check and cache 64b BAR0 support + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif Kernel BIF object pointer + * + */ +void +kbifCache64bBar0Support_GH100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + NvU32 regVal = 0; + + // Read config register + if (GPU_BUS_CFG_CYCLE_RD32(pGpu, NV_EP_PCFG_GPU_BARREG0, + ®Val) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Unable to read NV_EP_PCFG_GPU_BARREG0\n"); + return; + } + + // Check if 64b BAR0 is supported + if (FLD_TEST_DRF(_EP_PCFG_GPU, _BARREG0, _REG_ADDR_TYPE, + _64BIT, regVal)) + { + pKernelBif->setProperty(pKernelBif, PDB_PROP_KBIF_64BIT_BAR0_SUPPORTED, NV_TRUE); + } +} + /*! * @brief: Get BAR information from PCIe config space * @@ -870,3 +953,179 @@ kbifCacheVFInfo_GH100 pGpu->sriovState.b64bitVFBar2 = barIs64Bit; } +/*! + * @brief Clears Bus Master Enable bit in command register, disabling + * Function 0 - from issuing any new requests to sysmem. + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif KernelBif object pointer + * + * @return NV_OK + */ +NV_STATUS +kbifStopSysMemRequests_GH100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif, + NvBool bStop +) +{ + NvU32 regVal; + + NV_ASSERT_OK_OR_RETURN(GPU_BUS_CFG_CYCLE_RD32(pGpu, NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS, + ®Val)); + + if (bStop) + { + regVal = FLD_SET_DRF(_EP_PCFG_GPU, _CTRL_CMD_AND_STATUS, _CMD_BUS_MASTER, _DISABLE, regVal); + } + else + { + regVal = FLD_SET_DRF(_EP_PCFG_GPU, _CTRL_CMD_AND_STATUS, _CMD_BUS_MASTER, _ENABLE, regVal); + } + + NV_ASSERT_OK_OR_RETURN(GPU_BUS_CFG_CYCLE_WR32(pGpu, NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS, + regVal)); + + return NV_OK; +} + +/*! + * @brief Waits for function issued transaction completions (sysmem to GPU) to arrive + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif KernelBif object pointer + * + * @return NV_OK + */ +NV_STATUS +kbifWaitForTransactionsComplete_GH100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + RMTIMEOUT timeout; + NvU32 regVal; + + NV_ASSERT_OK_OR_RETURN(GPU_BUS_CFG_CYCLE_RD32( + pGpu, NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS, ®Val)); + + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + + // Wait for number of pending transactions to go to 0 + while (DRF_VAL(_EP_PCFG_GPU, _DEVICE_CONTROL_STATUS, _TRANSACTIONS_PENDING, regVal) != 0) + { + NV_ASSERT_OK_OR_RETURN(gpuCheckTimeout(pGpu, &timeout)); + NV_ASSERT_OK_OR_RETURN(GPU_BUS_CFG_CYCLE_RD32( + pGpu, NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS, ®Val)); + } + + return NV_OK; +} + +/*! + * @brief Trigger FLR. + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif KernelBif object pointer + * + * @return NV_OK if successful. + */ +NV_STATUS +kbifTriggerFlr_GH100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + NvU32 regVal = 0; + NV_STATUS status = NV_OK; + + status = GPU_BUS_CFG_CYCLE_RD32(pGpu, NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS, + ®Val); + + if (status != NV_OK) + { + NV_ASSERT_FAILED("Config space read of device control failed\n"); + return status; + } + + regVal = FLD_SET_DRF_NUM(_EP_PCFG_GPU, _DEVICE_CONTROL_STATUS , + _INITIATE_FN_LVL_RST, 0x1, regVal); + + status = GPU_BUS_CFG_CYCLE_WR32(pGpu, NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS, + regVal); + + if (status != NV_OK) + { + NV_ASSERT_FAILED("FLR trigger failed\n"); + return status; + } + + return status; +} + +/*! + * @brief Try restoring BAR registers and command register using config cycles + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif KernelBif object pointer + * + * @return NV_OK on success + * NV_ERR_INVALID_READ if the register read returns unexpected value + * NV_ERR_OBJECT_NOT_FOUND if the object is not found + */ +NV_STATUS +kbifRestoreBarsAndCommand_GH100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + NvU32 *pBarRegOffsets = pKernelBif->barRegOffsets; + NvU32 barOffsetEntry; + + // Restore all BAR registers + for (barOffsetEntry = 0; barOffsetEntry < KBIF_NUM_BAR_OFFSET_ENTRIES; barOffsetEntry++) + { + if (pBarRegOffsets[barOffsetEntry] != KBIF_INVALID_BAR_REG_OFFSET) + { + GPU_BUS_CFG_CYCLE_WR32(pGpu, pBarRegOffsets[barOffsetEntry], + pKernelBif->cacheData.gpuBootConfigSpace[pBarRegOffsets[barOffsetEntry]/sizeof(NvU32)]); + } + } + + // Restore Device Control register + GPU_BUS_CFG_CYCLE_WR32(pGpu, NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS, + pKernelBif->cacheData.gpuBootConfigSpace[NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS/sizeof(NvU32)]); + + if (GPU_REG_RD32(pGpu, NV_PMC_BOOT_0) != pGpu->chipId0) + { + return NV_ERR_INVALID_READ; + } + + return NV_OK; +} + +/*! + * @brief HAL specific BIF software state initialization + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif KernelBif object pointer + * + * @return NV_OK on success + */ +NV_STATUS +kbifInit_GH100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + // Cache the offsets of BAR registers into an array for subsequent use + kbifStoreBarRegOffsets_HAL(pGpu, pKernelBif, NV_EP_PCFG_GPU_VF_BAR0); + + return NV_OK; +} + diff --git a/src/nvidia/src/kernel/gpu/bif/arch/maxwell/kernel_bif_gm107.c b/src/nvidia/src/kernel/gpu/bif/arch/maxwell/kernel_bif_gm107.c index cb717b6567..bd7c0c20fb 100644 --- a/src/nvidia/src/kernel/gpu/bif/arch/maxwell/kernel_bif_gm107.c +++ b/src/nvidia/src/kernel/gpu/bif/arch/maxwell/kernel_bif_gm107.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -28,8 +28,12 @@ #include "platform/chipset/chipset.h" #include "nvdevid.h" +#include "published/maxwell/gm107/dev_boot.h" #include "published/maxwell/gm107/dev_nv_xve.h" +#include "published/maxwell/gm107/dev_nv_pcfg_xve_addendum.h" +#include "published/maxwell/gm107/dev_nv_pcfg_xve1_addendum.h" + // Defines for C73 chipset registers #ifndef NV_XVR_VEND_XP1 #define NV_XVR_VEND_XP1 0x00000F04 /* RW-4R */ @@ -40,6 +44,11 @@ #define NV_XVR_VEND_XP1_IGNORE_L0S_EN 0x00000001 /* RW--V */ #endif +// XVE register map for PCIe config space +static const NvU32 xveRegMapValid[] = NV_PCFG_XVE_REGISTER_VALID_MAP; +static const NvU32 xveRegMapWrite[] = NV_PCFG_XVE_REGISTER_WR_MAP; +static const NvU32 xve1RegMapValid[] = NV_PCFG_XVE1_REGISTER_VALID_MAP; +static const NvU32 xve1RegMapWrite[] = NV_PCFG_XVE1_REGISTER_WR_MAP; /* ------------------------ Public Functions -------------------------------- */ @@ -664,3 +673,236 @@ kbifDisableSysmemAccess_GM107 return status; } +/*! + * This function setups the xve register map pointers + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif Pointer to KernelBif object + * @param[in] func PCIe function number + * + * @return 'NV_OK' if successful, an RM error code otherwise. + */ +NV_STATUS +kbifInitXveRegMap_GM107 +( + OBJGPU *pGpu, + KernelBif *pKernelBif, + NvU8 func +) +{ + if (func == 0) + { + pKernelBif->xveRegmapRef[0].nFunc = 0; + pKernelBif->xveRegmapRef[0].xveRegMapValid = xveRegMapValid; + pKernelBif->xveRegmapRef[0].xveRegMapWrite = xveRegMapWrite; + pKernelBif->xveRegmapRef[0].numXveRegMapValid = sizeof(xveRegMapValid)/sizeof(xveRegMapValid[0]); + pKernelBif->xveRegmapRef[0].numXveRegMapWrite = sizeof(xveRegMapWrite)/sizeof(xveRegMapWrite[0]); + pKernelBif->xveRegmapRef[0].bufBootConfigSpace = pKernelBif->cacheData.gpuBootConfigSpace; + // No MSIX for this GPU + pKernelBif->xveRegmapRef[0].bufMsixTable = NULL; + } + else if (func == 1) + { + pKernelBif->xveRegmapRef[1].nFunc = 1; + pKernelBif->xveRegmapRef[1].xveRegMapValid = xve1RegMapValid; + pKernelBif->xveRegmapRef[1].xveRegMapWrite = xve1RegMapWrite; + pKernelBif->xveRegmapRef[1].numXveRegMapValid = sizeof(xve1RegMapValid)/sizeof(xve1RegMapValid[0]); + pKernelBif->xveRegmapRef[1].numXveRegMapWrite = sizeof(xve1RegMapWrite)/sizeof(xve1RegMapWrite[0]); + pKernelBif->xveRegmapRef[1].bufBootConfigSpace = pKernelBif->cacheData.azaliaBootConfigSpace; + // No MSIX for this func + pKernelBif->xveRegmapRef[1].bufMsixTable = NULL; + } + else + { + NV_PRINTF(LEVEL_ERROR, "Invalid argument, func: %d.\n", func); + NV_ASSERT(0); + return NV_ERR_INVALID_ARGUMENT; + } + + return NV_OK; +} + +/*! + * @brief Clears Bus Master Enable bit in command register, disabling + * Function 0 - from issuing any new requests to sysmem. + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif KernelBif object pointer + * + * @return NV_OK + */ +NV_STATUS +kbifStopSysMemRequests_GM107 +( + OBJGPU *pGpu, + KernelBif *pKernelBif, + NvBool bStop +) +{ + NvU32 regVal; + + NV_ASSERT_OK_OR_RETURN(GPU_BUS_CFG_RD32(pGpu, NV_XVE_DEV_CTRL, ®Val)); + + if (bStop) + { + regVal = FLD_SET_DRF(_XVE, _DEV_CTRL, _CMD_BUS_MASTER, _DISABLED, regVal); + } + else + { + regVal = FLD_SET_DRF(_XVE, _DEV_CTRL, _CMD_BUS_MASTER, _ENABLED, regVal); + } + + NV_ASSERT_OK_OR_RETURN(GPU_BUS_CFG_WR32(pGpu, NV_XVE_DEV_CTRL, regVal)); + + return NV_OK; +} + + +/* + * @brief Restore the BAR0 register from the given config space buffer + * BAR0 register restore has to use the config cycle write. + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif Pointer to KernelBif object + * @param[in] handle PCI handle for GPU + * @param[in] bufConfigSpace Stored config space + */ +void +kbifRestoreBar0_GM107 +( + OBJGPU *pGpu, + KernelBif *pKernelBif, + void *handle, + NvU32 *bufConfigSpace +) +{ + // + // Not much ROI in storing BAR offsets for legacy chips since + // BAR offsets are not going to change ever for legacy chips + // + osPciWriteDword(handle, NV_XVE_BAR0, + bufConfigSpace[NV_XVE_BAR0/sizeof(NvU32)]); +} + + +/*! + * @brief Check if any of the BAR register reads returns a valid value. + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif KernelBif object pointer + * + * @returns NV_TRUE if any BAR register read returns a valid value + * NV_FALSE if all the BAR registers return an invalid values + */ +NvBool +kbifAnyBarsAreValid_GM107 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + NvU32 domain = gpuGetDomain(pGpu); + NvU8 bus = gpuGetBus(pGpu); + NvU8 device = gpuGetDevice(pGpu); + NvU16 vendorId, deviceId; + void *handle; + + handle = osPciInitHandle(domain, bus, device, 0, &vendorId, &deviceId); + + if (osPciReadDword(handle, NV_XVE_BAR0) == pKernelBif->cacheData.gpuBootConfigSpace[4]) + { + // BAR0 is valid + return NV_TRUE; + } + + if ((osPciReadDword(handle, NV_XVE_BAR1_LO) == pKernelBif->cacheData.gpuBootConfigSpace[5]) && + (osPciReadDword(handle, NV_XVE_BAR1_HI) == pKernelBif->cacheData.gpuBootConfigSpace[6])) + { + // BAR1 is valid + return NV_TRUE; + } + + return NV_FALSE; +} + +/*! + * @brief Try restoring BAR registers and command register using config cycles + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif KernelBif object pointer + * + * @returns NV_OK on success + * NV_ERR_INVALID_READ if the register read returns unexpected value + */ +NV_STATUS +kbifRestoreBarsAndCommand_GM107 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + NvU32 domain = gpuGetDomain(pGpu); + NvU8 bus = gpuGetBus(pGpu); + NvU8 device = gpuGetDevice(pGpu); + NvU16 vendorId, deviceId; + void *handle; + + handle = osPciInitHandle(domain, bus, device, 0, &vendorId, &deviceId); + + osPciWriteDword(handle, NV_XVE_BAR0, pKernelBif->cacheData.gpuBootConfigSpace[4]); + osPciWriteDword(handle, NV_XVE_BAR1_LO, pKernelBif->cacheData.gpuBootConfigSpace[5]); + osPciWriteDword(handle, NV_XVE_BAR1_HI, pKernelBif->cacheData.gpuBootConfigSpace[6]); + osPciWriteDword(handle, NV_XVE_BAR2_LO, pKernelBif->cacheData.gpuBootConfigSpace[7]); + osPciWriteDword(handle, NV_XVE_BAR2_HI, pKernelBif->cacheData.gpuBootConfigSpace[8]); + osPciWriteDword(handle, NV_XVE_BAR3, pKernelBif->cacheData.gpuBootConfigSpace[9]); + osPciWriteDword(handle, NV_XVE_DEV_CTRL, pKernelBif->cacheData.gpuBootConfigSpace[1]); + + if (GPU_REG_RD32(pGpu, NV_PMC_BOOT_0) != pGpu->chipId0) + { + return NV_ERR_INVALID_READ; + } + + return NV_OK; +} + +/*! + * @brief HAL specific BIF software state initialization + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif KernelBif object pointer + * + * @return NV_OK on success + */ +NV_STATUS +kbifInit_GM107 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + // Cache the offsets of BAR registers into an array for subsequent use + kbifStoreBarRegOffsets_HAL(pGpu, pKernelBif, NV_XVE_BAR0); + + return NV_OK; +} + +/*! + * @brief Destructor + * + * @param[in] pKernelBif + * + * @returns void + */ +void +kbifDestruct_GM107 +( + KernelBif *pKernelBif +) +{ + portMemFree(pKernelBif->xveRegmapRef[0].bufMsixTable); + pKernelBif->xveRegmapRef[0].bufMsixTable = NULL; +} + + + + diff --git a/src/nvidia/src/kernel/gpu/bif/arch/turing/kernel_bif_tu102.c b/src/nvidia/src/kernel/gpu/bif/arch/turing/kernel_bif_tu102.c index 961a58f8ef..760f10f63c 100644 --- a/src/nvidia/src/kernel/gpu/bif/arch/turing/kernel_bif_tu102.c +++ b/src/nvidia/src/kernel/gpu/bif/arch/turing/kernel_bif_tu102.c @@ -26,6 +26,7 @@ #include "gpu/bif/kernel_bif.h" #include "gpu/bus/kern_bus.h" #include "gpu/gpu.h" +#include "platform/chipset/chipset.h" #define NV_VGPU_EMU 0x0000FFFF:0x0000F000 /* RW--D */ @@ -35,6 +36,11 @@ #include "published/turing/tu102/dev_nv_xve.h" #include "published/turing/tu102/dev_vm.h" +#include "published/turing/tu102/dev_nv_pcfg_xve_regmap.h" + +// XVE register map for PCIe config space +static const NvU32 xveRegMapValid[] = NV_PCFG_XVE_REGISTER_VALID_MAP; +static const NvU32 xveRegMapWrite[] = NV_PCFG_XVE_REGISTER_WR_MAP; /* ------------------------ Public Functions -------------------------------- */ @@ -153,8 +159,9 @@ kbifGetVFSparseMmapRegions_TU102 offsetStart = DRF_BASE(NV_VGPU_EMU) + osPageSize; } - // For non-HyperV, trap MSI-X table page - if (!hypervisorIsType(OS_HYPERVISOR_HYPERV)) + // Trap MSI-X table page for non-Hyperv and Hyperv non-GSP cases + if (!hypervisorIsType(OS_HYPERVISOR_HYPERV) + ) { // Assert whenever the MSI-X table page is not immediately after // the NV_VGPU_EMU page, as it will break the current assumption. @@ -201,7 +208,40 @@ kbifGetVFSparseMmapRegions_TU102 return NV_OK; } -/*! @brief Fetch VF details such as no. of VFs, First VF offset etc +/*! + * @brief Check and cache Function level reset support + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif Kernel BIF object pointer + * + */ +void +kbifCacheFlrSupport_TU102 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + NvU32 regVal = 0; + + // Read config register + if (GPU_BUS_CFG_RD32(pGpu, NV_XVE_DEVICE_CAPABILITY, + ®Val) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Unable to read NV_XVE_DEVICE_CAPABILITY\n"); + return; + } + + // Check if FLR is supported + if (FLD_TEST_DRF(_XVE, _DEVICE_CAPABILITY, _FUNCTION_LEVEL_RESET, + _SUPPORTED, regVal)) + { + pKernelBif->setProperty(pKernelBif, PDB_PROP_KBIF_FLR_SUPPORTED, NV_TRUE); + } +} + +/*! + * @brief Fetch VF details such as no. of VFs, First VF offset etc * * @param[in] pGpu GPU object pointer * @param[in] pKernelBif Kernel BIF object pointer @@ -253,3 +293,146 @@ kbifCacheVFInfo_TU102 regVal = GPU_REG_RD32(pGpu, DEVICE_BASE(NV_PCFG) + NV_XVE_SRIOV_CAP_HDR12); pGpu->sriovState.b64bitVFBar2 = IS_BAR_64(regVal); } + +/*! + * @brief Waits for function issued transaction completions(sysmem to GPU) to arrive + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif Kernel BIF object pointer + */ +NV_STATUS +kbifWaitForTransactionsComplete_TU102 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + NvU32 domain = gpuGetDomain(pGpu); + NvU8 bus = gpuGetBus(pGpu); + NvU8 device = gpuGetDevice(pGpu); + void *handle = NULL; + NvU16 vendorId; + NvU16 deviceId; + RMTIMEOUT timeout; + + handle = osPciInitHandle(domain, bus, device, 0, &vendorId, &deviceId); + + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + + // Wait for number of pending transactions to go to 0 + while (DRF_VAL(_XVE, _DEVICE_CONTROL_STATUS, _TRANSACTIONS_PENDING, + osPciReadDword(handle, NV_XVE_DEVICE_CONTROL_STATUS)) != 0) + { + if (gpuCheckTimeout(pGpu, &timeout) == NV_ERR_TIMEOUT) + { + NV_PRINTF(LEVEL_ERROR, + "Timeout waiting for transactions pending to go to 0\n"); + DBG_BREAKPOINT(); + return NV_ERR_TIMEOUT; + } + } + + return NV_OK; +} + +/*! + * @brief Trigger FLR + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif Kernel BIF object pointer + * + * @return NV_OK if successful. + */ +NV_STATUS +kbifTriggerFlr_TU102 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + NvU32 domain = gpuGetDomain(pGpu); + NvU8 bus = gpuGetBus(pGpu); + NvU8 device = gpuGetDevice(pGpu); + void *handle = NULL; + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJCL *pCl = SYS_GET_CL(pSys); + NvU32 regVal = 0; + NvU16 vendorId = 0; + NvU16 deviceId = 0; + + handle = osPciInitHandle(domain, bus, device, 0, &vendorId, &deviceId); + + regVal = osPciReadDword(handle, NV_XVE_DEVICE_CONTROL_STATUS); + + regVal = FLD_SET_DRF_NUM(_XVE, _DEVICE_CONTROL_STATUS , + _INITIATE_FN_LVL_RST, 0x1, regVal); + + clPcieWriteDword(pCl, gpuGetDomain(pGpu), gpuGetBus(pGpu), + gpuGetDevice(pGpu), 0, NV_XVE_DEVICE_CONTROL_STATUS, + regVal); + + return NV_OK; +} + +/*! + * This function setups the xve register map pointers + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif Pointer to KernelBif object + * @param[in] func PCIe function number + * + * @return 'NV_OK' if successful, an RM error code otherwise. + */ +NV_STATUS +kbifInitXveRegMap_TU102 +( + OBJGPU *pGpu, + KernelBif *pKernelBif, + NvU8 func +) +{ + extern NvU32 kbifInitXveRegMap_GM107(OBJGPU *pGpu, KernelBif *pKernelBif, NvU8 func); + NV_STATUS status = NV_OK; + + if (func == 0) + { + pKernelBif->xveRegmapRef[0].nFunc = 0; + pKernelBif->xveRegmapRef[0].xveRegMapValid = xveRegMapValid; + pKernelBif->xveRegmapRef[0].xveRegMapWrite = xveRegMapWrite; + pKernelBif->xveRegmapRef[0].numXveRegMapValid = sizeof(xveRegMapValid)/sizeof(xveRegMapValid[0]); + pKernelBif->xveRegmapRef[0].numXveRegMapWrite = sizeof(xveRegMapWrite)/sizeof(xveRegMapWrite[0]); + pKernelBif->xveRegmapRef[0].bufBootConfigSpace = pKernelBif->cacheData.gpuBootConfigSpace; + // MSIX table buf not used in Turing, but it could be + pKernelBif->xveRegmapRef[0].bufMsixTable = NULL; + } + else if (func == 1) + { + // Init regmap for Fn1 using older HAL + status = kbifInitXveRegMap_GM107(pGpu, pKernelBif, 1); + } + else + { + NV_PRINTF(LEVEL_ERROR, "Invalid argument, func: %d.\n", func); + NV_ASSERT(0); + status = NV_ERR_INVALID_ARGUMENT; + } + + return status; +} + +/*! + * @brief Returns size of MSIX vector control table + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif Pointer to KernelBif object + */ +NvU32 +kbifGetMSIXTableVectorControlSize_TU102 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + return NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL__SIZE_1; +} + diff --git a/src/nvidia/src/kernel/gpu/bif/kernel_bif.c b/src/nvidia/src/kernel/gpu/bif/kernel_bif.c index 5abe957470..6a63381d97 100644 --- a/src/nvidia/src/kernel/gpu/bif/kernel_bif.c +++ b/src/nvidia/src/kernel/gpu/bif/kernel_bif.c @@ -74,7 +74,13 @@ kbifConstructEngine_IMPL kbifDisableP2PTransactions_HAL(pGpu, pKernelBif); // Cache MNOC interface support - kbifIsMnocSupported_HAL(pGpu, pKernelBif); + kbifCacheMnocSupport_HAL(pGpu, pKernelBif); + + // Cache FLR support + kbifCacheFlrSupport_HAL(pGpu, pKernelBif); + + // Cache 64B BAR0 support + kbifCache64bBar0Support_HAL(pGpu, pKernelBif); // Cache VF info kbifCacheVFInfo_HAL(pGpu, pKernelBif); @@ -101,7 +107,12 @@ kbifStateInitLocked_IMPL OBJSYS *pSys = SYS_GET_INSTANCE(); OBJOS *pOS = SYS_GET_OS(pSys); OBJCL *pCl = SYS_GET_CL(pSys); - NV_STATUS status = NV_OK; + + kbifInitXveRegMap_HAL(pGpu, pKernelBif, 1); + kbifInitXveRegMap_HAL(pGpu, pKernelBif, 0); + + // Do the HAL dependent init + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kbifInit_HAL(pGpu, pKernelBif)); // Return early if GPU is connected to an unsupported chipset if (pCl->getProperty(pCl, PDB_PROP_CL_UNSUPPORTED_CHIPSET)) @@ -110,11 +121,7 @@ kbifStateInitLocked_IMPL } // Initialize OS mapping and core logic - status = osInitMapping(pGpu); - if (status != NV_OK) - { - return status; - } + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, osInitMapping(pGpu)); // Initialize BIF static info kbifStaticInfoInit(pGpu, pKernelBif); @@ -133,7 +140,7 @@ kbifStateInitLocked_IMPL pKernelBif->setProperty(pKernelBif, PDB_PROP_KBIF_SUPPORT_NONCOHERENT, NV_FALSE); } - return status; + return NV_OK; } /*! @@ -341,6 +348,10 @@ kbifStaticInfoInit_IMPL pStaticInfo->bPcieGen4Capable); pKernelBif->setProperty(pKernelBif, PDB_PROP_KBIF_IS_C2C_LINK_UP, pStaticInfo->bIsC2CLinkUp); + pKernelBif->setProperty(pKernelBif, PDB_PROP_KBIF_DEVICE_IS_MULTIFUNCTION, + pStaticInfo->bIsDeviceMultiFunction); + pKernelBif->setProperty(pKernelBif, PDB_PROP_KBIF_GCX_PMU_CFG_SPACE_RESTORE, + pStaticInfo->bGcxPmuCfgSpaceRestore); pKernelBif->dmaWindowStartAddress = pStaticInfo->dmaWindowStartAddress; kBifStaticInfoInit_IMPL_exit: @@ -353,7 +364,7 @@ kbifStaticInfoInit_IMPL * @brief Initialize PCI-E config space bits based on chipset and GPU support. */ void -kbifInitPcieDeviceControlStatus +kbifInitPcieDeviceControlStatus_IMPL ( OBJGPU *pGpu, KernelBif *pKernelBif @@ -814,7 +825,8 @@ kbifControlGetPCIEInfo_IMPL NvU32 index = pBusInfo->index; NvU32 data = 0; - if (kbifGetBusIntfType_HAL(pKernelBif) != NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS) + if ((pKernelBif != NULL) && + (kbifGetBusIntfType_HAL(pKernelBif) != NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS)) { // KMD cannot handle error codes for this ctrl call, hence returning // NV_OK, once KMD fixes the bug:3545197, RM can return NV_ERR_NOT_SUPPORTED diff --git a/src/nvidia/src/kernel/gpu/bus/arch/ampere/kern_bus_ga100.c b/src/nvidia/src/kernel/gpu/bus/arch/ampere/kern_bus_ga100.c index 54f76ab295..49508e6965 100644 --- a/src/nvidia/src/kernel/gpu/bus/arch/ampere/kern_bus_ga100.c +++ b/src/nvidia/src/kernel/gpu/bus/arch/ampere/kern_bus_ga100.c @@ -21,9 +21,6 @@ * DEALINGS IN THE SOFTWARE. */ -// FIXME XXX -#define NVOC_KERNEL_NVLINK_H_PRIVATE_ACCESS_ALLOWED - #include "core/core.h" #include "gpu/gpu.h" @@ -45,6 +42,7 @@ #include "mem_mgr/virt_mem_mgr.h" #include +#include "published/ampere/ga100/dev_nv_xve.h" #include "published/ampere/ga100/dev_ram.h" // NV_RAMIN_ALLOC_SIZE #include "ctrl/ctrl2080/ctrl2080fla.h" // NV2080_CTRL_CMD_FLA_SETUP_INSTANCE_MEM_BLOCK @@ -925,7 +923,8 @@ kbusConstructFlaInstBlk_GA100 NV_ASSERT(status == NV_OK); - status = memdescAlloc(pKernelBus->flaInfo.pInstblkMemDesc); + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_89, + pKernelBus->flaInfo.pInstblkMemDesc); NV_ASSERT(status == NV_OK); @@ -1042,7 +1041,7 @@ kbusGetNvlinkP2PPeerId_GA100 // get the peer ID from the table // if ((knvlinkIsForcedConfig(pGpu0, pKernelNvlink0) || - pKernelNvlink0->bRegistryLinkOverride) && !bEgmPeer) + knvlinkAreLinksRegistryOverriden(pGpu0, pKernelNvlink0)) && !bEgmPeer) { if (knvlinkGetPeersNvlinkMaskFromHshub(pGpu0, pKernelNvlink0) != 0) { @@ -1063,8 +1062,18 @@ kbusGetNvlinkP2PPeerId_GA100 // auto-config. // + // // Return if there are no NVLink connections to the remote GPU - if (pKernelNvlink0->peerLinkMasks[gpuGetInstance(pGpu1)] == 0) + // + // skipping this check for knvlinkIsForcedConfig case since + // peerLinkMasks is not set for knvlinkIsForcedConfig + // this will be skipped only for reserving EGM peerId (bEgmPeer is true) + // when client has not provided EGM peerId mask in forced config + // tests. + // + if (!(knvlinkIsForcedConfig(pGpu0, pKernelNvlink0) || + knvlinkAreLinksRegistryOverriden(pGpu0, pKernelNvlink0)) && + (knvlinkGetPeerLinkMask(pGpu0, pKernelNvlink0, gpuGetInstance(pGpu1)) == 0)) { return NV_OK; } @@ -1427,3 +1436,79 @@ kbusGetNvlinkPeerId_GA100 LOWESTBITIDX_32(peerId); return peerId; } + +/*! +* @brief Cache the value of NV_XVE_RESIZE_BAR1_CTRL_SIZE +* +* @param[in] pGpu OBJGPU pointer +* @param[in] pKernelBus KernelBus pointer +* +*/ +void +kbusCacheBAR1ResizeSize_WAR_BUG_3249028_GA100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus +) +{ + NvU32 regVal = GPU_REG_RD32(pGpu, DEVICE_BASE(NV_PCFG) + NV_XVE_RESIZE_BAR1_CTRL); + pKernelBus->bar1ResizeSizeIndex = DRF_VAL(_XVE, _RESIZE_BAR1_CTRL, _BAR_SIZE, regVal); +} + +/*! +* @brief Restore the value of NV_XVE_RESIZE_BAR1_CTRL_SIZE if different +* from the cached value. +* Windows has a strict requirement that the PCIE config has to stay +* the same across power transitions. +* Early SBIOS implementing resize BAR do not restore properly +* the value of NV_XVE_RESIZE_BAR1_CTRL_SIZE. +* The reason of this WAR is to not crash the systems that have +* not been updated - yet. +* +* @param[in] pGpu OBJGPU pointer +* @param[in] pKernelBus KernelBus pointer +* +* @returns NV_STATUS +* +*/ +NV_STATUS +kbusRestoreBAR1ResizeSize_WAR_BUG_3249028_GA100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus +) +{ + NvU32 regVal; + NvU32 bar1ResizeSizeIndex; + + if (!pKernelBus->getProperty(pKernelBus, PDB_PROP_KBUS_RESTORE_BAR1_SIZE_BUG_3249028_WAR)) + { + return NV_OK; + } + + NV_ASSERT_OR_RETURN(pKernelBus->bar1ResizeSizeIndex >= NV_XVE_RESIZE_BAR1_CTRL_BAR_SIZE_MIN, + NV_ERR_INVALID_DATA); + + NV_ASSERT_OR_RETURN(pKernelBus->bar1ResizeSizeIndex <= NV_XVE_RESIZE_BAR1_CTRL_BAR_SIZE_MAX, + NV_ERR_INVALID_DATA); + + regVal = GPU_REG_RD32(pGpu, DEVICE_BASE(NV_PCFG) + NV_XVE_RESIZE_BAR1_CTRL); + bar1ResizeSizeIndex = DRF_VAL(_XVE, _RESIZE_BAR1_CTRL, _BAR_SIZE, regVal); + + if (bar1ResizeSizeIndex == pKernelBus->bar1ResizeSizeIndex) + { + // BAR1 size match. Nothing to do + return NV_OK; + } + + // BAR1 size changed. Warn and update + NV_PRINTF(LEVEL_WARNING, "BAR1 size mismatch: current: 0x%x, expected: 0x%x\n", + bar1ResizeSizeIndex, pKernelBus->bar1ResizeSizeIndex); + NV_PRINTF(LEVEL_WARNING, "Most likely SBIOS did not restore the BAR1 size\n"); + NV_PRINTF(LEVEL_WARNING, "Please update your SBIOS!\n"); + + regVal = FLD_SET_DRF_NUM(_XVE, _RESIZE_BAR1_CTRL, _BAR_SIZE, pKernelBus->bar1ResizeSizeIndex, regVal); + GPU_REG_WR32(pGpu, DEVICE_BASE(NV_PCFG) + NV_XVE_RESIZE_BAR1_CTRL, regVal); + + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/bus/arch/hopper/kern_bus_gh100.c b/src/nvidia/src/kernel/gpu/bus/arch/hopper/kern_bus_gh100.c index 8710bb7114..2feb9c52da 100644 --- a/src/nvidia/src/kernel/gpu/bus/arch/hopper/kern_bus_gh100.c +++ b/src/nvidia/src/kernel/gpu/bus/arch/hopper/kern_bus_gh100.c @@ -45,6 +45,7 @@ #include "published/hopper/gh100/dev_ram.h" #include "published/hopper/gh100/pri_nv_xal_ep.h" #include "published/hopper/gh100/pri_nv_xal_ep_p2p.h" +#include "published/hopper/gh100/dev_xtl_ep_pcfg_gpu.h" #include "published/hopper/gh100/dev_vm.h" #include "published/hopper/gh100/dev_mmu.h" #include "ctrl/ctrl2080/ctrl2080fla.h" // NV2080_CTRL_CMD_FLA_SETUP_INSTANCE_MEM_BLOCK @@ -296,7 +297,8 @@ kbusVerifyBar2_GH100 { memdescCreateExisting(&memDesc, pGpu, size, ADDR_FBMEM, NV_MEMORY_UNCACHED, MEMDESC_FLAGS_NONE); } - status = memdescAlloc(&memDesc); + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_95, + (&memDesc)); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, @@ -330,8 +332,7 @@ kbusVerifyBar2_GH100 // ========================================================== // Does the BAR0 window work? - NV_PRINTF((IS_EMULATION(pGpu)) ? LEVEL_ERROR : LEVEL_INFO, - "Testing BAR0 window...\n"); + NV_PRINTF_COND(IS_EMULATION(pGpu), LEVEL_ERROR, LEVEL_INFO, "Testing BAR0 window...\n"); bar0Window = kbusGetBAR0WindowVidOffset_HAL(pGpu, pKernelBus); bar0TestAddr = memdescGetPhysAddr(pMemDesc, AT_GPU, 0); @@ -389,8 +390,8 @@ kbusVerifyBar2_GH100 goto kbusVerifyBar2_failed; } - NV_PRINTF((IS_EMULATION(pGpu)) ? LEVEL_ERROR : LEVEL_INFO, - "Bar0 window tests successfully\n"); + NV_PRINTF_COND(IS_EMULATION(pGpu), LEVEL_ERROR, LEVEL_INFO, "Bar0 window tests successfully\n"); + GPU_REG_WR32(pGpu, DRF_BASE(NV_PRAMIN) + NvU64_LO32(bar0TestAddr & 0xffff), testData); kbusWriteBAR0WindowBase_HAL(pGpu, pKernelBus, NvU64_LO32(bar0Window >> 16)); @@ -405,9 +406,8 @@ kbusVerifyBar2_GH100 (NvU8 *)pKernelBus->virtualBar2[GPU_GFID_PF].pCpuMapping, (NvU8 *)bar2VirtualAddr, testMemorySize); - NV_PRINTF((IS_EMULATION(pGpu) == NV_TRUE) ? LEVEL_ERROR : LEVEL_INFO, - "MMUTest The physical address being targetted is 0x%llx\n", - testMemoryOffset); + NV_PRINTF_COND(IS_EMULATION(pGpu), LEVEL_ERROR, LEVEL_INFO, + "MMUTest The physical address being targetted is 0x%llx\n", testMemoryOffset); for(index = 0; index < testMemorySize; index += 4) { @@ -489,7 +489,7 @@ kbusVerifyBar2_GH100 kbusWriteBAR0WindowBase_HAL(pGpu, pKernelBus, NvU64_LO32(bar0Window >> 16)); - status = kbusFlush_HAL(pGpu, pKernelBus, BUS_FLUSH_VIDEO_MEMORY | BUS_FLUSH_USE_PCIE_READ); + status = kbusFlush_HAL(pGpu, pKernelBus, BUS_FLUSH_VIDEO_MEMORY); // Bail now if we have encountered any error if (status != NV_OK) @@ -532,8 +532,7 @@ kbusVerifyBar2_GH100 if (status == NV_OK) { - NV_PRINTF(IS_EMULATION(pGpu) ? LEVEL_ERROR : LEVEL_INFO, - "BAR2 virtual test passes\n"); + NV_PRINTF_COND(IS_EMULATION(pGpu), LEVEL_ERROR, LEVEL_INFO, "BAR2 virtual test passes\n"); } return status; @@ -565,59 +564,42 @@ kbusTeardownBar2CpuAperture_GH100 return NV_OK; } - if (KBUS_BAR2_TUNNELLED(pKernelBus)) + if (pKernelBus->virtualBar2[gfid].pPageLevels != NULL && + pKernelBus->virtualBar2[gfid].pPageLevelsMemDesc != NULL) { - // KBUS-TODO -- dead code path? - // KBUS_BAR2_TUNNELLED is never true on HOPPER+ - - // Unmap bar2 space - if (pKernelBus->virtualBar2[gfid].pCpuMapping) - { - // Remove the memory access filter - osMemRemoveFilter((NvU64)((NvUPtr)(pKernelBus->virtualBar2[gfid].pCpuMapping))); - portMemFree(pKernelBus->virtualBar2[gfid].pCpuMapping); - pKernelBus->virtualBar2[gfid].pCpuMapping = NULL; - } + memmgrMemDescEndTransfer(GPU_GET_MEMORY_MANAGER(pGpu), + pKernelBus->virtualBar2[gfid].pPageLevelsMemDesc, + TRANSFER_FLAGS_NONE); + pKernelBus->virtualBar2[gfid].pPageLevels = NULL; } - else - { - if (pKernelBus->virtualBar2[gfid].pPageLevels != NULL && - pKernelBus->virtualBar2[gfid].pPageLevelsMemDesc != NULL) - { - memmgrMemDescEndTransfer(GPU_GET_MEMORY_MANAGER(pGpu), - pKernelBus->virtualBar2[gfid].pPageLevelsMemDesc, - TRANSFER_FLAGS_NONE); - pKernelBus->virtualBar2[gfid].pPageLevels = NULL; - } - kbusDestroyCpuPointerForBusFlush_HAL(pGpu, pKernelBus); + kbusDestroyCpuPointerForBusFlush_HAL(pGpu, pKernelBus); - kbusFlushVirtualBar2_HAL(pGpu, pKernelBus, NV_FALSE, gfid); + kbusFlushVirtualBar2_HAL(pGpu, pKernelBus, NV_FALSE, gfid); - if (pKernelBus->virtualBar2[gfid].pCpuMapping) - { - osUnmapPciMemoryKernelOld(pGpu, (void*)pKernelBus->virtualBar2[gfid].pCpuMapping); - // Mark the BAR as un-initialized so that a later call - // to initbar2 can succeed. - pKernelBus->virtualBar2[gfid].pCpuMapping = NULL; - } + if (pKernelBus->virtualBar2[gfid].pCpuMapping) + { + osUnmapPciMemoryKernelOld(pGpu, (void*)pKernelBus->virtualBar2[gfid].pCpuMapping); + // Mark the BAR as un-initialized so that a later call + // to initbar2 can succeed. + pKernelBus->virtualBar2[gfid].pCpuMapping = NULL; + } - // - // make sure that the bar2 mode is physical so that the vesa extended - // linear framebuffer works after driver unload. Clear other bits to force - // vid. - // - // if BROKEN_FB, merely rewriting this to 0 (as it already was) causes - // FBACKTIMEOUT -- don't do it (Bug 594539) - // - if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_BROKEN_FB)) - { - GPU_VREG_FLD_WR_DRF_DEF(pGpu, _VIRTUAL_FUNCTION_PRIV_FUNC, _BAR2_BLOCK_LOW_ADDR, _MODE, _PHYSICAL); - // bug 1738008: temporary fix to unblock -inst_in_sys argument - // we tried to correct bar2 unbind sequence but didn't fix the real issue - // will fix this soon 4/8/16 - GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR); - } + // + // make sure that the bar2 mode is physical so that the vesa extended + // linear framebuffer works after driver unload. Clear other bits to force + // vid. + // + // if BROKEN_FB, merely rewriting this to 0 (as it already was) causes + // FBACKTIMEOUT -- don't do it (Bug 594539) + // + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_BROKEN_FB)) + { + GPU_VREG_FLD_WR_DRF_DEF(pGpu, _VIRTUAL_FUNCTION_PRIV_FUNC, _BAR2_BLOCK_LOW_ADDR, _MODE, _PHYSICAL); + // bug 1738008: temporary fix to unblock -inst_in_sys argument + // we tried to correct bar2 unbind sequence but didn't fix the real issue + // will fix this soon 4/8/16 + GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR); } return NV_OK; @@ -706,7 +688,7 @@ kbusFlushPcieForBar0Doorbell_GH100 KernelBus *pKernelBus ) { - return kbusFlush_HAL(pGpu, pKernelBus, BUS_FLUSH_VIDEO_MEMORY | BUS_FLUSH_USE_PCIE_READ); + return kbusFlush_HAL(pGpu, pKernelBus, BUS_FLUSH_VIDEO_MEMORY); } /*! @@ -998,8 +980,7 @@ kbusVerifyCoherentLink_GH100 // Skip the test if 0FB configuration is used. if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_ALL_INST_IN_SYSMEM)) { - NV_PRINTF(IS_EMULATION(pGpu) ? LEVEL_ERROR : LEVEL_INFO, - "Skipping Coherent link test\n"); + NV_PRINTF_COND(IS_EMULATION(pGpu), LEVEL_ERROR, LEVEL_INFO, "Skipping Coherent link test\n"); return NV_OK; } @@ -1060,8 +1041,7 @@ kbusVerifyCoherentLink_GH100 if (status == NV_OK) { - NV_PRINTF(IS_EMULATION(pGpu) ? LEVEL_ERROR : LEVEL_INFO, - "Coherent link test passes\n"); + NV_PRINTF_COND(IS_EMULATION(pGpu), LEVEL_ERROR, LEVEL_INFO, "Coherent link test passes\n"); } return status; @@ -1069,39 +1049,49 @@ kbusVerifyCoherentLink_GH100 } /** - * @brief Setup BAR1 P2P capability property. - * All Hopper+ are BAR1 P2P capable. + * @brief Check BAR1 P2P capability * * @param pGpu - * @param pBus + * @param pKernelBus + * @param gfid * - * @return void + * @return NV_TRUE if it is BAR1 P2P capable */ -void kbusSetupBar1P2PCapability_GH100 +NvBool +kbusIsBar1P2PCapable_GH100 ( - OBJGPU *pGpu, - KernelBus *pKernelBus + OBJGPU *pGpu, + KernelBus *pKernelBus, + NvU32 gfid ) { NvU64 bar1Size = kbusGetPciBarSize(pKernelBus, 1); + KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); NvU64 fbSize = pMemoryManager->Ram.fbUsableMemSize; + OBJEHEAP *pVASpaceHeap = vaspaceGetHeap(pKernelBus->bar1[gfid].pVAS); + NvU64 bar1VASize = pVASpaceHeap->rangeHi + 1; - // Make sure the BAR1 size is big enough to cover all FB - if((bar1Size >= fbSize) && (fbSize != 0)) - { - NV_PRINTF(LEVEL_INFO, "The gpu %d is BAR1 P2P capable.\n", pGpu->gpuInstance); - kbusSetBar1P2pCapable(pKernelBus, NV_TRUE); - } - else - { - NV_PRINTF(LEVEL_INFO, "The gpu %d is not BAR1 P2P capable.\n", pGpu->gpuInstance); - kbusSetBar1P2pCapable(pKernelBus, NV_FALSE); - } + if ((fbSize == 0) || (bar1Size == 0)) + return NV_FALSE; + + if (pKernelBif->forceP2PType != NV_REG_STR_RM_FORCE_P2P_TYPE_BAR1P2P) + return NV_FALSE; + + // + // GPU BAR1 supports the SYSMEM mapping for the bar1 doorbell, RM needs + // to make sure that BAR1 VA has 128KB space left for such cases after all + // FB statically mapped in BAR1. Bug 3869651 #14. + // + if ((bar1VASize < (32 * RM_PAGE_SIZE)) || + ((bar1VASize - (32 * RM_PAGE_SIZE)) < RM_ALIGN_UP(fbSize, RM_PAGE_SIZE_2M))) + return NV_FALSE; + + return NV_TRUE; } /*! - * @brief check if it can support BAR1 P2P between the GPUs + * @brief check if it can support BAR1 P2P between the specified GPUs * At the point this function is called, the system do not support C2C and * NVLINK P2P and the BAR1 P2P is the preferred option. * @@ -1110,7 +1100,7 @@ void kbusSetupBar1P2PCapability_GH100 * @param[in] pGpu1 (remote GPU) * @param[in] pKernelBus1 (remote GPU) * - * return NV_TRUE if the GPU support BAR1 P2P + * return NV_TRUE if it supports BAR1 P2P between the specified GPUs */ NvBool kbusIsPcieBar1P2PMappingSupported_GH100 @@ -1123,17 +1113,6 @@ kbusIsPcieBar1P2PMappingSupported_GH100 { NvU32 gpuInst0 = gpuGetInstance(pGpu0); NvU32 gpuInst1 = gpuGetInstance(pGpu1); - KernelBif *pKernelBif0 = GPU_GET_KERNEL_BIF(pGpu0); - NvU32 gpu0Gfid; - NvU32 gpu1Gfid; - NV_STATUS status = NV_OK; - - // Check if BAR1 P2P is disabled by a regkey - if ((pKernelBif0->forceP2PType != NV_REG_STR_RM_FORCE_P2P_TYPE_DEFAULT) && - (pKernelBif0->forceP2PType != NV_REG_STR_RM_FORCE_P2P_TYPE_BAR1P2P)) - { - return NV_FALSE; - } // Not loopback support if (pGpu0 == pGpu1) @@ -1141,21 +1120,9 @@ kbusIsPcieBar1P2PMappingSupported_GH100 return NV_FALSE; } - // Both of GPUs need to support BAR1P2P - if (!kbusIsBar1P2PCapable(pKernelBus0) || - !kbusIsBar1P2PCapable(pKernelBus1)) - { - return NV_FALSE; - } - - // - // TODO: To move this check to kbusSetupBar1P2PCapability. It should check bStaticBar1Enabled - // to determine if the GPU is Bar1P2P Capable. - // - NV_ASSERT_OK_OR_ELSE(status, vgpuGetCallingContextGfid(pGpu0, &gpu0Gfid), return NV_FALSE); - NV_ASSERT_OK_OR_ELSE(status, vgpuGetCallingContextGfid(pGpu1, &gpu1Gfid), return NV_FALSE); - if (!pKernelBus0->bar1[gpu0Gfid].bStaticBar1Enabled || - !pKernelBus1->bar1[gpu1Gfid].bStaticBar1Enabled) + // Both of GPUs need to have the static bar1 enabled + if (!kbusIsStaticBar1Enabled(pGpu0, pKernelBus0) || + !kbusIsStaticBar1Enabled(pGpu1, pKernelBus1)) { return NV_FALSE; } @@ -1759,27 +1726,11 @@ kbusRemoveP2PMappingForC2C_GH100 return status; } -NvBool -kbusNeedStaticBar1Mapping_GH100(OBJGPU *pGpu, KernelBus *pKernelBus) -{ - KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); - - // Check if BAR1 P2P is enabled by a regkey - if (pKernelBif->forceP2PType != NV_REG_STR_RM_FORCE_P2P_TYPE_BAR1P2P) - { - return NV_FALSE; - } - - // We need static Bar1 only when the GPU is BAR1 P2P capable. - return kbusIsBar1P2PCapable(pKernelBus); -} - /*! * @brief Setup static Bar1 mapping. * * @param[in] pGpu GPU pointer * @param[in] pKernelBus Kernel bus pointer - * @param[in] reservedFbSize The size to reserve in FB from the address 0 * @param[in] gfid The GFID * * @returns NV_OK on success, or rm_status from called functions on failure. @@ -1789,60 +1740,20 @@ kbusEnableStaticBar1Mapping_GH100 ( OBJGPU *pGpu, KernelBus *pKernelBus, - NvU64 reservedFbSize, NvU32 gfid ) { MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); MEMORY_DESCRIPTOR *pMemDesc = NULL; MEMORY_DESCRIPTOR *pDmaMemDesc = NULL; - NvU64 bar1Size = kbusGetPciBarSize(pKernelBus, 1); NV_STATUS status = NV_OK; - OBJEHEAP *pVASpaceHeap = vaspaceGetHeap(pKernelBus->bar1[gfid].pVAS); - NvU64 bar1Offset = RM_ALIGN_UP(reservedFbSize, RM_PAGE_SIZE_2M); + NvU64 bar1Offset = 0; NvU64 bar1MapSize; - NvU64 staticBar1PhyAddr; - - if (!kbusNeedStaticBar1Mapping_HAL(pGpu, pKernelBus)) - { - return NV_ERR_INVALID_STATE; - } - - NV_PRINTF(LEVEL_INFO, "Static bar1 size 0x%llx fb size 0x%llx\n", - bar1Size, pMemoryManager->Ram.fbUsableMemSize); - - // BAR1 VA size can be smaller than BAR1 size - bar1MapSize = NV_MIN(bar1Size, pVASpaceHeap->rangeHi); - bar1MapSize = NV_MIN(bar1MapSize, pMemoryManager->Ram.fbUsableMemSize); - - NV_ASSERT_OR_RETURN(bar1MapSize > bar1Offset, NV_ERR_INVALID_STATE); - - // Adjust the offset - bar1MapSize -= bar1Offset; - - // - // GPU BAR1 VA also supports the SYSMEM mapping, we need to reserve some - // spaces for such cases, like doorbell mapping which is not backed by - // FBMEM. - // - if ((bar1Size - (bar1MapSize + bar1Offset)) < (4 * RM_PAGE_SIZE_2M)) - { - // - // When BAR1 size much bigger than FB, then there are plenty of - // VA space left for other type of mapping. - // When BAR1 size is slightly bigger or equal FB, the available - // BAR1 VA is very limited. - // Here reserves 4 * 2MB blocks. - // !!! NOTE: Not sure how big Rm need to reserve - // TODO: Need to find a better solution, bug 3869651 - // - bar1MapSize -= 4 * RM_PAGE_SIZE_2M; - - NV_PRINTF(LEVEL_INFO, "Static bar1 reserved 8 MB from the top of FB\n"); - } + NvU64 bar1BusAddr; // align to 2MB page size - bar1MapSize = RM_ALIGN_UP(bar1MapSize, RM_PAGE_SIZE_2M); + bar1MapSize = RM_ALIGN_UP(pMemoryManager->Ram.fbUsableMemSize, + RM_PAGE_SIZE_2M); // // The static mapping is not backed by an allocated physical FB. @@ -1852,7 +1763,7 @@ kbusEnableStaticBar1Mapping_GH100 NV_MEMORY_CONTIGUOUS, ADDR_FBMEM, NV_MEMORY_UNCACHED, MEMDESC_FLAGS_NONE)); - memdescDescribe(pMemDesc, ADDR_FBMEM, bar1Offset, bar1MapSize); + memdescDescribe(pMemDesc, ADDR_FBMEM, 0, bar1MapSize); // Set to use RM_PAGE_SIZE_HUGE, 2MB memdescSetPageSize(pMemDesc, AT_GPU, RM_PAGE_SIZE_HUGE); @@ -1864,12 +1775,21 @@ kbusEnableStaticBar1Mapping_GH100 NV_ASSERT_OK_OR_GOTO(status, kbusMapFbAperture_HAL(pGpu, pKernelBus, pMemDesc, 0, &bar1Offset, &bar1MapSize, - BUS_MAP_FB_FLAGS_MAP_UNICAST | BUS_MAP_FB_FLAGS_MAP_OFFSET_FIXED, + BUS_MAP_FB_FLAGS_MAP_UNICAST | + BUS_MAP_FB_FLAGS_MAP_OFFSET_FIXED, NV01_NULL_OBJECT), cleanup_mem); - // Get the system physical address the base address of staticBar1 - staticBar1PhyAddr = gpumgrGetGpuPhysFbAddr(pGpu) + bar1Offset; + if(bar1Offset != 0) + { + // For static bar1 mapping, it should always be 0. + status = NV_ERR_INVALID_STATE; + NV_ASSERT(0); + goto cleanup_bus_map; + } + + // Get the system physical address of the Bar1 + bar1BusAddr = gpumgrGetGpuPhysFbAddr(pGpu); // // Create a memory descriptor to describe a SYSMEM target of the GPU @@ -1886,12 +1806,11 @@ kbusEnableStaticBar1Mapping_GH100 MEMDESC_FLAGS_NONE), cleanup_bus_map); - memdescDescribe(pDmaMemDesc, ADDR_SYSMEM, staticBar1PhyAddr, bar1MapSize); + memdescDescribe(pDmaMemDesc, ADDR_SYSMEM, bar1BusAddr, bar1MapSize); pKernelBus->bar1[gfid].bStaticBar1Enabled = NV_TRUE; pKernelBus->bar1[gfid].staticBar1.pVidMemDesc = pMemDesc; pKernelBus->bar1[gfid].staticBar1.pDmaMemDesc = pDmaMemDesc; - pKernelBus->bar1[gfid].staticBar1.base = bar1Offset; pKernelBus->bar1[gfid].staticBar1.size = bar1MapSize; NV_PRINTF(LEVEL_INFO, "Static bar1 mapped offset 0x%llx size 0x%llx\n", @@ -1928,46 +1847,48 @@ kbusEnableStaticBar1Mapping_GH100 * * @returns NV_OK on success, or rm_status from called functions on failure. */ -NV_STATUS -kbusDisableStaticBar1Mapping_GH100(OBJGPU *pGpu, KernelBus *pKernelBus, NvU32 gfid) +void +kbusDisableStaticBar1Mapping_GH100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + NvU32 gfid +) { - if (pKernelBus->bar1[gfid].bStaticBar1Enabled) - { - if (pKernelBus->bar1[gfid].staticBar1.pVidMemDesc != NULL) - { - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kbusUnmapFbAperture_HAL(pGpu, pKernelBus, - pKernelBus->bar1[gfid].staticBar1.pVidMemDesc, - pKernelBus->bar1[gfid].staticBar1.base, - pKernelBus->bar1[gfid].staticBar1.size, - BUS_MAP_FB_FLAGS_MAP_UNICAST | BUS_MAP_FB_FLAGS_MAP_OFFSET_FIXED)); - - memdescDestroy(pKernelBus->bar1[gfid].staticBar1.pVidMemDesc); + if (!pKernelBus->bar1[gfid].bStaticBar1Enabled) + return; - pKernelBus->bar1[gfid].staticBar1.pVidMemDesc = NULL; - } + pKernelBus->bar1[gfid].bStaticBar1Enabled = NV_FALSE; - memdescDestroy(pKernelBus->bar1[gfid].staticBar1.pDmaMemDesc); - pKernelBus->bar1[gfid].staticBar1.pDmaMemDesc = NULL; + NV_ASSERT_OK(kbusUnmapFbAperture_HAL(pGpu, pKernelBus, + pKernelBus->bar1[gfid].staticBar1.pVidMemDesc, + 0, + pKernelBus->bar1[gfid].staticBar1.size, + BUS_MAP_FB_FLAGS_MAP_UNICAST | + BUS_MAP_FB_FLAGS_MAP_OFFSET_FIXED)); - pKernelBus->bar1[gfid].bStaticBar1Enabled = NV_FALSE; - } + memdescDestroy(pKernelBus->bar1[gfid].staticBar1.pVidMemDesc); + pKernelBus->bar1[gfid].staticBar1.pVidMemDesc = NULL; - return NV_OK; + memdescDestroy(pKernelBus->bar1[gfid].staticBar1.pDmaMemDesc); + pKernelBus->bar1[gfid].staticBar1.pDmaMemDesc = NULL; } /*! * @brief To update the StaticBar1 PTE kind for the specified memory. * - * The staticbar1 only support GMK (generic memory kind) and other compressed kind. - * By default, the bar1 is statically mapped with GMK at boot when the static bar1 is enabled. + * The staticbar1 only support GMK and the compressed kind PTE. + * By default, the bar1 is statically mapped with GMK at boot when the + * static bar1 is enabled. * - * When to map a uncompressed kind memory, RM just return the static bar1 address which is mapped - * to the specified memory. + * When to map a uncompressed kind memory, RM just return the static + * bar1 address which is mapped to the specified memory. * - * When to map a compressed kind memory, RM must call this function to change the static mapped - * bar1 range to the specified memory from GMK to the compressed kind. And RM needs to - * call this function to change it back to GMK from the compressed kind after this mapping is released. + * When to map a compressed kind memory, RM must call this function to + * change the static mapped bar1 range to the specified memory from GMK + * to the compressed kind. And RM needs to call this function to change + * it back to GMK from the compressed kind after this mapping is + * released. * * @param[in] pGpu GPU pointer * @param[in] pKernelBus Kernel bus pointer @@ -1980,74 +1901,78 @@ kbusDisableStaticBar1Mapping_GH100(OBJGPU *pGpu, KernelBus *pKernelBus, NvU32 gf * return NV_OK on success */ NV_STATUS -_kbusUpdateStaticBAR1VAMapping_GH100 +kbusUpdateStaticBar1VAMapping_GH100 ( - OBJGPU *pGpu, - KernelBus *pKernelBus, + OBJGPU *pGpu, + KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, - NvU64 offset, - NvU64 length, - NvBool bRelease, - NvU32 gfid + NvU64 offset, + NvU64 length, + NvBool bRelease ) { NV_STATUS status = NV_OK; VirtMemAllocator *pDma = GPU_GET_DMA(pGpu); MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); - OBJVASPACE *pVAS = pKernelBus->bar1[gfid].pVAS; + OBJVASPACE *pVAS; NvU32 kind; - MEMORY_DESCRIPTOR *pTempMemDesc; - NvU64 vAddr; NvU64 vaLo; NvU64 vaHi; NvU64 physAddr; - NvU64 pageOffset; NvU64 mapLength; NvU64 pageSize; DMA_PAGE_ARRAY pageArray = {0}; - COMPR_INFO comprInfo; - NvBool bCompressed; + COMPR_INFO comprInfo = {0}; + NvU32 gfid; + + NV_ASSERT_OR_RETURN(vgpuGetCallingContextGfid(pGpu, &gfid) == NV_OK, + NV_ERR_INVALID_STATE); NV_ASSERT_OR_RETURN(pMemDesc != NULL, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(memdescGetAddressSpace(pMemDesc) == ADDR_FBMEM, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(memdescGetAddressSpace(pMemDesc) == ADDR_FBMEM, + NV_ERR_INVALID_ARGUMENT); // It only support contiguous memory - NV_ASSERT_OR_RETURN(memdescGetPteArraySize(pMemDesc, AT_GPU) == 1, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(memdescGetPteArraySize(pMemDesc, AT_GPU) == 1, + NV_ERR_INVALID_ARGUMENT); - pTempMemDesc = memdescGetMemDescFromGpu(pMemDesc, pGpu); + pVAS = pKernelBus->bar1[gfid].pVAS; - pageSize = memdescGetPageSize(pTempMemDesc, VAS_ADDRESS_TRANSLATION(pVAS)); + pageSize = memdescGetPageSize(pMemDesc, VAS_ADDRESS_TRANSLATION(pVAS)); - NV_ASSERT_OK_OR_RETURN(memmgrGetKindComprFromMemDesc(pMemoryManager, pTempMemDesc, 0, &kind, &comprInfo)); - bCompressed = memmgrIsKind_HAL(pMemoryManager, FB_IS_KIND_COMPRESSIBLE, kind); + NV_ASSERT_OK_OR_RETURN(memmgrGetKindComprFromMemDesc(pMemoryManager, + pMemDesc, 0, &kind, &comprInfo)); // Static BAR1 mapping only support >=2MB page size for compressed memory - NV_CHECK_OR_RETURN(LEVEL_WARNING, bCompressed && (pageSize >= RM_PAGE_SIZE_HUGE), NV_ERR_INVALID_STATE); + NV_CHECK_OR_RETURN(LEVEL_ERROR, + memmgrIsKind_HAL(pMemoryManager, FB_IS_KIND_COMPRESSIBLE, kind) && + (pageSize >= RM_PAGE_SIZE_HUGE), + NV_ERR_INVALID_STATE); if (bRelease) { // update the PTE kind to be the uncompressed kind - comprInfo.kind = memmgrGetUncompressedKind_HAL(pGpu, pMemoryManager, kind, NV_FALSE); + comprInfo.kind = memmgrGetUncompressedKind_HAL(pGpu, pMemoryManager, + kind, NV_FALSE); } - // Under static BAR1 mapping, BAR1 VA equal to physAddr - physAddr = memdescGetPhysAddr(pTempMemDesc, VAS_ADDRESS_TRANSLATION(pVAS), offset); - vAddr = RM_ALIGN_DOWN(physAddr, pageSize); - - pageOffset = physAddr & (pageSize - 1); - mapLength = RM_ALIGN_UP(pageOffset + length, pageSize); - - vaLo = vAddr; + // Under static BAR1 mapping, BAR1 VA equal to fb physAddr + physAddr = memdescGetPhysAddr(pMemDesc, + VAS_ADDRESS_TRANSLATION(pVAS), + offset); + vaLo = RM_ALIGN_DOWN(physAddr, pageSize); + mapLength = RM_ALIGN_UP(vaLo + length, pageSize); vaHi = vaLo + mapLength - 1; pageArray.count = 1; pageArray.pData = &physAddr; status = dmaUpdateVASpace_HAL(pGpu, pDma, pVAS, - pTempMemDesc, NULL, + pMemDesc, NULL, vaLo, vaHi, - DMA_UPDATE_VASPACE_FLAGS_UPDATE_KIND, // only change KIND + DMA_UPDATE_VASPACE_FLAGS_UPDATE_KIND | + DMA_UPDATE_VASPACE_FLAGS_UPDATE_COMPR, &pageArray, 0, &comprInfo, 0, NV_MMU_VER3_PTE_VALID_TRUE, @@ -2060,57 +1985,16 @@ _kbusUpdateStaticBAR1VAMapping_GH100 if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "error updating static bar1 VA space.\n"); + NV_PRINTF(LEVEL_ERROR, + "Failed to update static bar1 VA space, error 0x%x.\n", + status); } return status; } /*! - * @brief To unmap FB aperture for the specified memory under the static mapping. - * - * @param[in] pGpu GPU pointer - * @param[in] pKernelBus Kernel bus pointer - * @param[in] pMemDesc The memory to update - * @param[in] gfid The GFID - * - * return NV_OK on success - */ -NV_STATUS -kbusStaticUnmapFbAperture_GH100 -( - OBJGPU *pGpu, - KernelBus *pKernelBus, - MEMORY_DESCRIPTOR *pMemDesc, - NvU32 gfid -) -{ - MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); - NvBool bCompressedkind = memmgrIsKind_HAL(pMemoryManager, FB_IS_KIND_COMPRESSIBLE, - memdescGetPteKind(pMemDesc)); - - // - // For uncompressed type, nothing to do - // For compressed type, restore PTE kind to GMK - // - if (bCompressedkind) - { - NV_ASSERT_OK_OR_RETURN(_kbusUpdateStaticBAR1VAMapping_GH100(pGpu, pKernelBus, - pMemDesc, 0, memdescGetSize(pMemDesc), NV_TRUE, gfid)); - } - - // Nothing else to do on static mapping mode - NV_PRINTF(LEVEL_INFO, - "StaticBar1 unmapped at 0x%llx size 0x%llx%s\n", - memdescGetPhysAddr(pMemDesc, AT_GPU, 0), - memdescGetSize(pMemDesc), - bCompressedkind ? " [compressed]" : ""); - - return NV_OK; -} - -/*! - * @brief To map FB aperture for the specified memory under the static mapping. + * @brief To get FB aperture for the specified memory under the static mapping. * * @param[in] pGpu GPU pointer * @param[in] pKernelBus Kernel bus pointer @@ -2123,7 +2007,7 @@ kbusStaticUnmapFbAperture_GH100 * return NV_OK on success */ NV_STATUS -kbusStaticMapFbAperture_GH100 +kbusGetStaticFbAperture_GH100 ( OBJGPU *pGpu, KernelBus *pKernelBus, @@ -2134,42 +2018,31 @@ kbusStaticMapFbAperture_GH100 NvU32 gfid ) { - MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); NvU64 physAddr; - NvU32 status = NV_OK; - NvBool bCompressedkind = memmgrIsKind_HAL(pMemoryManager, FB_IS_KIND_COMPRESSIBLE, memdescGetPteKind(pMemDesc)); // It only support contiguous memory - NV_ASSERT_OR_RETURN(memdescGetPteArraySize(pMemDesc, AT_GPU) == 1, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(memdescGetPteArraySize(pMemDesc, AT_GPU) == 1, + NV_ERR_INVALID_ARGUMENT); physAddr = memdescGetPhysAddr(pMemDesc, AT_GPU, offset); - if (physAddr < pKernelBus->bar1[gfid].staticBar1.base || - physAddr + *pLength >= pKernelBus->bar1[gfid].staticBar1.size) + if ((physAddr + *pLength) >= pKernelBus->bar1[gfid].staticBar1.size) { NV_PRINTF(LEVEL_ERROR, - "0x%llx + 0x%llx is out of the range of the StaticBar1 map [0x%llx, 0x%llx]\n", - physAddr, *pLength, pKernelBus->bar1[gfid].staticBar1.base, - pKernelBus->bar1[gfid].staticBar1.base + pKernelBus->bar1[gfid].staticBar1.size); + "0x%llx + 0x%llx is out of the range of the static Bar1" + "map [0, 0x%llx]\n", + physAddr, *pLength, pKernelBus->bar1[gfid].staticBar1.size); return NV_ERR_INVALID_ARGUMENT; } - if (bCompressedkind) - { - // Update PTE to be the compressed kind - NV_ASSERT_OK_OR_RETURN(_kbusUpdateStaticBAR1VAMapping_GH100(pGpu, pKernelBus, pMemDesc, - offset, *pLength, NV_FALSE, gfid)); - } - - // When the static bar1 enabled, the Fb aperture offset is the physical address. + // + // When the static bar1 is enabled, the Fb aperture offset is the + // physical address. + // *pAperOffset = physAddr; - NV_PRINTF(LEVEL_INFO, "StaticBar1 mapped at 0x%llx size 0x%llx%s\n", - physAddr, *pLength, - bCompressedkind ? " [compressed]" : ""); - - return status; + return NV_OK; } void @@ -2459,8 +2332,7 @@ kbusSetupBindFla_GH100 NV_STATUS status = NV_OK; NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS params = {0}; MEMORY_DESCRIPTOR *pMemDesc; - RM_API *pRmApi = IS_GSP_CLIENT(pGpu) ? GPU_GET_PHYSICAL_RMAPI(pGpu) - : rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); pMemDesc = pKernelBus->flaInfo.pInstblkMemDesc; @@ -2608,3 +2480,83 @@ kbusGetEgmPeerId_GH100 return BUS_INVALID_PEER; } + +/*! +* @brief Cache the value of NV_EP_PCFG_GPU_PF_RESIZE_BAR_CTRL_BAR_SIZE +* +* @param[in] pGpu OBJGPU pointer +* @param[in] pKernelBus KernelBus pointer +*/ +void +kbusCacheBAR1ResizeSize_WAR_BUG_3249028_GH100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus +) +{ + NvU32 regVal; + + if (GPU_BUS_CFG_CYCLE_RD32(pGpu, NV_EP_PCFG_GPU_PF_RESIZE_BAR_CTRL, ®Val) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Unable to read NV_EP_PCFG_GPU_PF_RESIZE_BAR_CTRL\n"); + return; + } + pKernelBus->bar1ResizeSizeIndex = DRF_VAL(_EP_PCFG_GPU, _PF_RESIZE_BAR_CTRL, _BAR_SIZE, regVal); +} + + +/*! +* @brief Restore the value of NV_EP_PCFG_GPU_PF_RESIZE_BAR_CTRL if different from the +* cached value. Windows has a strict requirement that the PCIE config has to stay the +* same across power transitions. Early SBIOS implementing resize BAR do not restore properly +* the value of NV_EP_PCFG_GPU_PF_RESIZE_BAR_CTRL_BAR_SIZE. The reason of this WAR is to not +* crash the systems that have not beed updated - yet. +* +* @param[in] pGpu OBJGPU pointer +* @param[in] pKernelBus KernelBus pointer +* +* @returns NV_OK +*/ +NV_STATUS +kbusRestoreBAR1ResizeSize_WAR_BUG_3249028_GH100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus +) +{ + NvU32 regVal; + NvU32 bar1ResizeSizeIndex; + + if (!pKernelBus->getProperty(pKernelBus, PDB_PROP_KBUS_RESTORE_BAR1_SIZE_BUG_3249028_WAR)) + { + return NV_OK; + } + + NV_ASSERT_OR_RETURN(pKernelBus->bar1ResizeSizeIndex >= NV_EP_PCFG_GPU_PF_RESIZE_BAR_CTRL_BAR_SIZE_MIN, + NV_ERR_INVALID_DATA); + + if (GPU_BUS_CFG_CYCLE_RD32(pGpu, NV_EP_PCFG_GPU_PF_RESIZE_BAR_CTRL, ®Val) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Unable to read NV_EP_PCFG_GPU_PF_RESIZE_BAR_CTRL\n"); + return NV_ERR_NOT_SUPPORTED; + } + + bar1ResizeSizeIndex = DRF_VAL(_EP_PCFG_GPU, _PF_RESIZE_BAR_CTRL, _BAR_SIZE, regVal); + + if (bar1ResizeSizeIndex == pKernelBus->bar1ResizeSizeIndex) + { + // BAR1 size match. Nothing to do + return NV_OK; + } + + // BAR1 size changed. Warn and update + NV_PRINTF(LEVEL_WARNING, "BAR1 size mismatch: current: 0x%x, expected: 0x%x\n", + bar1ResizeSizeIndex, pKernelBus->bar1ResizeSizeIndex); + NV_PRINTF(LEVEL_WARNING, "Most likely SBIOS did not restore the BAR1 size\n"); + NV_PRINTF(LEVEL_WARNING, "Please update your SBIOS!\n"); + + regVal = FLD_SET_DRF_NUM(_EP_PCFG_GPU, _PF_RESIZE_BAR_CTRL, _BAR_SIZE, pKernelBus->bar1ResizeSizeIndex, regVal); + GPU_BUS_CFG_CYCLE_WR32(pGpu, NV_EP_PCFG_GPU_PF_RESIZE_BAR_CTRL, regVal); + + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c b/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c index e207d0e579..67a64f3a09 100644 --- a/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c +++ b/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c @@ -57,7 +57,6 @@ static void _kbusLinkP2P_GM107(OBJGPU *, KernelBus *); static NvU32 _kbusGetSizeOfBar2PageDir_GM107(NvU64 vaBase, NvU64 vaLimit, NvU64 vaPerEntry, NvU32 entrySize); -static NV_STATUS _kbusBar0TunnelCb_GM107(void *pPrivData, NvU64 addr, void *pData, NvU64 size, NvBool bRead); static NV_STATUS _kbusUpdateDebugStatistics(OBJGPU *pGpu); NV_STATUS _kbusMapAperture_GM107(OBJGPU *, KernelBus *, PMEMORY_DESCRIPTOR, OBJVASPACE *, NvU64, NvU64 *, @@ -103,8 +102,8 @@ kbusConstructHal_GM107(OBJGPU *pGpu, KernelBus *pKernelBus) pKernelBus->virtualBar2[GPU_GFID_PF].pVASpaceHeap = NULL; pKernelBus->virtualBar2[GPU_GFID_PF].pMapListMemory = NULL; - if (pGpu->getProperty(pGpu, PDB_PROP_GPU_BROKEN_FB) && - !pGpu->getProperty(pGpu, PDB_PROP_GPU_ZERO_FB)) + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_BROKEN_FB) || + pGpu->getProperty(pGpu, PDB_PROP_GPU_ZERO_FB)) { pKernelBus->bFbFlushDisabled = NV_TRUE; } @@ -158,8 +157,6 @@ kbusStatePreInitLocked_GM107 kbusDetermineBar1ApertureLength(pKernelBus, GPU_GFID_PF); - kbusSetupBar1P2PCapability(pGpu, pKernelBus); - if (NV_OK != kbusConstructVirtualBar2_HAL(pGpu, pKernelBus, GPU_GFID_PF)) { return NV_ERR_INSUFFICIENT_RESOURCES; @@ -339,7 +336,7 @@ kbusStateInitLocked_IMPL(OBJGPU *pGpu, KernelBus *pKernelBus) ConfidentialCompute *pConfCompute = GPU_GET_CONF_COMPUTE(pGpu); - if (IS_GSP_CLIENT(pGpu) && (pConfCompute != NULL) && + if (IS_GSP_CLIENT(pGpu) && (pConfCompute != NULL) && !(pConfCompute->ccStaticInfo.bIsBar1Trusted && pConfCompute->ccStaticInfo.bIsPcieTrusted)) { pKernelBus->bBarAccessBlocked = NV_TRUE; @@ -404,15 +401,22 @@ kbusStateInitLocked_IMPL(OBJGPU *pGpu, KernelBus *pKernelBus) return NV_OK; } +/** + * @brief Setup BAR2 during hibernate resume + * + * @param[in] pGpu + * @param[in] pKernelBus + * @param[in] flags + */ + NV_STATUS -kbusStateLoad_GM107 +kbusStatePreLoad_GM107 ( - OBJGPU *pGpu, + OBJGPU *pGpu, KernelBus *pKernelBus, - NvU32 flags + NvU32 flags ) { - if (flags & GPU_STATE_FLAGS_PRESERVING) { MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); @@ -434,25 +438,144 @@ kbusStateLoad_GM107 NV_ASSERT(IsTEGRA(pGpu)); } - if (!(flags & GPU_STATE_FLAGS_GC6_TRANSITION)) + NV_ASSERT_OK_OR_RETURN(kbusRestoreBar2_HAL(pKernelBus, flags)); + } + + return NV_OK; +} + +NV_STATUS +kbusStateLoad_GM107 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + NvU32 flags +) +{ + if (!IS_GPU_GC6_STATE_EXITING(pGpu)) + { + if (!IS_VIRTUAL_WITH_FULL_SRIOV(pGpu)) { - if (NULL == pKernelBus->virtualBar2[GPU_GFID_PF].pCpuMapping && - !KBUS_CPU_VISIBLE_BAR12_DISABLED(pGpu)) + if (flags & GPU_STATE_FLAGS_PM_TRANSITION) { - NV_ASSERT_OK_OR_RETURN(kbusSetupBar2CpuAperture_HAL(pGpu, pKernelBus, GPU_GFID_PF)); + // + // Restore the BAR1 size if we are coming out of suspend or hibernate/hybrid sleep, + // and the SBIOS did not restore it properly. + // Help for customers who did not update their SBIOS. + // + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kbusRestoreBAR1ResizeSize_WAR_BUG_3249028_HAL(pGpu, pKernelBus)); + } + else + { + // Cache the BAR1 size at driver load + kbusCacheBAR1ResizeSize_WAR_BUG_3249028_HAL(pGpu, pKernelBus); } } - NV_ASSERT_OK_OR_RETURN(kbusCommitBar2_HAL(pGpu, pKernelBus, flags)); + } + + return NV_OK; +} + +NV_STATUS +kbusRestoreBar2_GM107 +( + KernelBus *pKernelBus, + NvU32 flags +) +{ + OBJGPU *pGpu = ENG_GET_GPU(pKernelBus); + + NV_ASSERT_OR_RETURN(flags & GPU_STATE_FLAGS_PRESERVING, NV_ERR_INVALID_STATE); + + if (!(flags & GPU_STATE_FLAGS_GC6_TRANSITION)) + { + if (!RMCFG_FEATURE_PLATFORM_GSP && !KBUS_CPU_VISIBLE_BAR12_DISABLED(pGpu)) + { + // Get the CPU mapping. + NV_ASSERT_OK_OR_RETURN(kbusSetupBar2CpuAperture_HAL(pGpu, pKernelBus, GPU_GFID_PF)); + } + + { + // + // Only write PDEs here + // PTEs for visible range are lost/cleared, as monolithic needs BAR2 to set up FBSR CE channel + // PTEs for invisible range are restored + // + MMU_WALK *pBar2Walk = kbusGetBar2GmmuWalker_HAL(pKernelBus); + const GMMU_FMT *pBar2GmmuFmt = kbusGetBar2GmmuFmt_HAL(pKernelBus); + const MMU_FMT_LEVEL *pLevelFmt = NULL; + MMU_WALK_USER_CTX userCtx = {0}; + NvU64 origVidOffset = 0; + + // Check that Bar2 Page Dir starts at or after bar0 window vid offset + NV_ASSERT_OK_OR_RETURN(kbusSetupBar0WindowBeforeBar2Bootstrap_HAL(pGpu, pKernelBus, &origVidOffset)); + + // Setup walk user context. + userCtx.pGpu = pGpu; + NV_ASSERT_OK_OR_RETURN(mmuWalkSetUserCtx(pBar2Walk, &userCtx)); + + // We want to lock the small page table + pLevelFmt = mmuFmtFindLevelWithPageShift(pBar2GmmuFmt->pRoot, + RM_PAGE_SHIFT); + + if (pKernelBus->bar2[GPU_GFID_PF].cpuVisibleLimit != 0) + NV_ASSERT_OK_OR_RETURN(mmuWalkCommitPDEs(pBar2Walk, pLevelFmt, pKernelBus->bar2[GPU_GFID_PF].cpuVisibleBase, pKernelBus->bar2[GPU_GFID_PF].cpuVisibleLimit)); + + if (pKernelBus->bar2[GPU_GFID_PF].cpuInvisibleLimit != 0) + NV_ASSERT_OK_OR_RETURN(mmuWalkCommitPDEs(pBar2Walk, pLevelFmt, pKernelBus->bar2[GPU_GFID_PF].cpuInvisibleBase, pKernelBus->bar2[GPU_GFID_PF].cpuInvisibleLimit)); + + if (pKernelBus->bar2[GPU_GFID_PF].cpuVisibleLimit != 0) + { + NV_ASSERT_OK_OR_RETURN(mmuWalkSparsify(pBar2Walk, pKernelBus->bar2[GPU_GFID_PF].cpuVisibleBase, + pKernelBus->bar2[GPU_GFID_PF].cpuVisibleLimit, NV_FALSE)); + } + + kbusRestoreBar0WindowAfterBar2Bootstrap_HAL(pGpu, pKernelBus, origVidOffset); + } + } + + NV_ASSERT_OK_OR_RETURN(kbusCommitBar2_HAL(pGpu, pKernelBus, flags)); + + if (!RMCFG_FEATURE_PLATFORM_GSP) + { + if (!(flags & GPU_STATE_FLAGS_GC6_TRANSITION)) + { + RMTIMEOUT timeout; + + // + // Temporary WAR for Bug 3737096 + // Wait for BAR0/BAR2 to settle + // + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE); + do + { + NV_STATUS status = kbusVerifyBar2_HAL(pGpu, pKernelBus, NULL, NULL, 0, 0); + + if (status == NV_OK) + break; + else if (status == NV_ERR_TIMEOUT) + { + NV_PRINTF(LEVEL_ERROR, "kbusVerifyBar2_HAL() keeps failing.\n"); + DBG_BREAKPOINT(); + break; + } + + status = gpuCheckTimeout(pGpu, &timeout); + osSpinLoop(); + } while (1); + } - // - // If we are exiting GC6 and the SKIP_BAR2_TEST_GC6 is set for the - // chip, then don't verify BAR2. The time taken to verify causes a - // a hit on the GC6 exit times, so this verif only feature does not - // come for free. - // if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING) && !(IS_GPU_GC6_STATE_EXITING(pGpu) && pKernelBus->bSkipBar2TestOnGc6Exit)) { + // + // If we are exiting GC6 and the SKIP_BAR2_TEST_GC6 is set for the + // chip, then don't verify BAR2. The time taken to verify causes a + // a hit on the GC6 exit times, so this verif only feature does not + // come for free. + // + // Verify that BAR2 and the MMU actually works NV_ASSERT_OK_OR_RETURN(kbusVerifyBar2_HAL(pGpu, pKernelBus, NULL, NULL, 0, 0)); @@ -527,6 +650,22 @@ kbusStatePreUnload_GM107 return NV_OK; } +NV_STATUS +kbusStatePostUnload_GM107 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + NvU32 flags +) +{ + if ((flags & GPU_STATE_FLAGS_PRESERVING) && !(flags & GPU_STATE_FLAGS_GC6_TRANSITION)) + { + NV_ASSERT_OK(kbusTeardownBar2CpuAperture_HAL(pGpu, pKernelBus, GPU_GFID_PF)); + } + + return NV_OK; +} + NV_STATUS kbusStateUnload_GM107 ( @@ -555,19 +694,7 @@ kbusStateUnload_GM107 kbusUnlinkP2P_HAL(pGpu, pKernelBus); } - if (flags & GPU_STATE_FLAGS_PRESERVING) - { - if (!IS_GPU_GC6_STATE_ENTERING(pGpu)) - { - status = kbusTeardownBar2CpuAperture_HAL(pGpu, pKernelBus, GPU_GFID_PF); - if (!IS_VIRTUAL_WITH_SRIOV(pGpu)) - { - // Do not use BAR2 physical mode for bootstrapping BAR2 across S/R. - pKernelBus->bUsePhysicalBar2InitPagetable = NV_FALSE; - } - } - } - else + if (!(flags & GPU_STATE_FLAGS_PRESERVING)) { // Clear write mailbox data window info. pKernelBus->p2pPcie.writeMailboxBar1Addr = PCIE_P2P_INVALID_WRITE_MAILBOX_ADDR; @@ -607,7 +734,7 @@ kbusInitBar1_GM107(OBJGPU *pGpu, KernelBus *pKernelBus, NvU32 gfid) NvU32 gpuMask = 0; NvBool bSmoothTransitionEnabled = ((pGpu->uefiScanoutSurfaceSizeInMB != 0) && RMCFG_FEATURE_PLATFORM_WINDOWS_LDDM); - NvU32 bar1ReservedSize = 0; + NvBool bBar1P2PCapable; vaRangeMax = pKernelBus->bar1[gfid].apertureLength - 1; @@ -777,11 +904,13 @@ kbusInitBar1_GM107(OBJGPU *pGpu, KernelBus *pKernelBus, NvU32 gfid) // NV_ASSERT(pKernelBus->bar1[gfid].apertureLength <= kbusGetPciBarSize(pKernelBus, 1)); + bBar1P2PCapable = kbusIsBar1P2PCapable(pGpu, pKernelBus, gfid); + // // If we need to preserve a console mapping at the start of BAR1, we // need to allocate the VA space before anything else gets allocated. // - if (IS_GFID_PF(gfid) && + if (!bBar1P2PCapable && IS_GFID_PF(gfid) && (kbusIsPreserveBar1ConsoleEnabled(pKernelBus) || bSmoothTransitionEnabled)) { MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); @@ -847,7 +976,6 @@ kbusInitBar1_GM107(OBJGPU *pGpu, KernelBus *pKernelBus, NvU32 gfid) } pKernelBus->bBar1ConsolePreserved = NV_TRUE; - bar1ReservedSize += consoleSize; } else { @@ -858,11 +986,11 @@ kbusInitBar1_GM107(OBJGPU *pGpu, KernelBus *pKernelBus, NvU32 gfid) } } - if (kbusNeedStaticBar1Mapping_HAL(pGpu, pKernelBus)) + if (bBar1P2PCapable) { // Enable the static BAR1 mapping for the BAR1 P2P NV_ASSERT_OK_OR_GOTO(rmStatus, - kbusEnableStaticBar1Mapping_HAL(pGpu, pKernelBus, bar1ReservedSize, gfid), + kbusEnableStaticBar1Mapping_HAL(pGpu, pKernelBus, gfid), kbusInitBar1_failed); } else @@ -1008,7 +1136,7 @@ kbusDestroyBar1_GM107 if (pKernelBus->bar1[gfid].bStaticBar1Enabled) { - status = kbusDisableStaticBar1Mapping_HAL(pGpu, pKernelBus, gfid); + kbusDisableStaticBar1Mapping_HAL(pGpu, pKernelBus, gfid); } vmmDestroyVaspace(pVmm, pKernelBus->bar1[gfid].pVAS); @@ -1121,12 +1249,9 @@ kbusDestroyBar2_GM107(OBJGPU *pGpu, KernelBus *pKernelBus, NvU32 gfid) status = NV_ERR_GENERIC; } - if (KBUS_BAR2_ENABLED(pKernelBus)) + if (kbusTeardownBar2GpuVaSpace_HAL(pGpu, pKernelBus, gfid) != NV_OK) { - if (kbusTeardownBar2GpuVaSpace_HAL(pGpu, pKernelBus, gfid) != NV_OK) - { - status = NV_ERR_GENERIC; - } + status = NV_ERR_GENERIC; } if (IS_GFID_PF(gfid)) @@ -1197,72 +1322,26 @@ kbusSetupBar2CpuAperture_GM107(OBJGPU *pGpu, KernelBus *pKernelBus, NvU32 gfid) return NV_OK; } - if (KBUS_BAR2_TUNNELLED(pKernelBus)) + // + // Map bar2 space -- only map the space we use in the RM. Some 32b OSes are *cramped* + // for kernel virtual addresses. + // + if (NV_OK != osMapPciMemoryKernelOld(pGpu, pKernelBus->bar2[gfid].physAddr, + (pKernelBus->bar2[gfid].rmApertureLimit + 1), + NV_PROTECT_READ_WRITE, + (void**)&(pKernelBus->virtualBar2[gfid].pCpuMapping), + NV_MEMORY_WRITECOMBINED)) { - // - // Since GK20A doesn't support BAR2 accesses we tunnel all RM BAR2 accesses - // through the BAR0 window. For this we register a callback function with the - // OS layer which is called when RM accesses an address in the CPU BAR2 VA range. - // We skip the normal stuff we do init BAR2 (like init-ing BAR2 inst block) since - // they are not needed for GK20A. - // - - // - // Map bar2 space -- only map the space we use in the RM. Some 32b OSes are *cramped* - // for kernel virtual addresses. On GK20A, we just alloc CPU VA space since there is no - // actual bar2, and tunnel the "fake" bar2 accesses through the bar0 window. - // - pKernelBus->virtualBar2[gfid].pCpuMapping = portMemAllocNonPaged(pKernelBus->bar2[gfid].rmApertureLimit + 1); - if (pKernelBus->virtualBar2[gfid].pCpuMapping == NULL) - { - NV_PRINTF(LEVEL_ERROR, "- Unable to map bar2!\n"); - DBG_BREAKPOINT(); - return NV_ERR_NO_MEMORY; - } - - // - // Call the OS add mem filter routine now that bar2 is mapped - // Currently this is used to route bar2 accesses through bar0 on gk20A - // - status = osMemAddFilter((NvU64)((NvUPtr)(pKernelBus->virtualBar2[gfid].pCpuMapping)), - (NvU64)((NvUPtr)(pKernelBus->virtualBar2[gfid].pCpuMapping)) + - (pKernelBus->bar2[gfid].rmApertureLimit + 1), - _kbusBar0TunnelCb_GM107, - (void *)pGpu); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, - "Cannot add os mem filter for bar2 tunneling\n"); - DBG_BREAKPOINT(); - goto cleanup; - } + NV_PRINTF(LEVEL_ERROR, "- Unable to map bar2!\n"); + DBG_BREAKPOINT(); + return NV_ERR_GENERIC; } - else - { - // - // Map bar2 space -- only map the space we use in the RM. Some 32b OSes are *cramped* - // for kernel virtual addresses. - // - if (NV_OK != osMapPciMemoryKernelOld(pGpu, pKernelBus->bar2[gfid].physAddr, - (pKernelBus->bar2[gfid].rmApertureLimit + 1), - NV_PROTECT_READ_WRITE, - (void**)&(pKernelBus->virtualBar2[gfid].pCpuMapping), - NV_MEMORY_WRITECOMBINED)) - { - NV_PRINTF(LEVEL_ERROR, "- Unable to map bar2!\n"); - DBG_BREAKPOINT(); - return NV_ERR_GENERIC; - } - NV_PRINTF_COND(IS_EMULATION(pGpu), LEVEL_NOTICE, LEVEL_INFO, - "BAR0 Base Cpu Mapping @ 0x%p and BAR2 Base Cpu Mapping @ 0x%p\n", - pGpu->deviceMappings[0].gpuNvAddr->Reg032, - pKernelBus->virtualBar2[gfid].pCpuMapping); - - - } + NV_PRINTF_COND(IS_EMULATION(pGpu), LEVEL_NOTICE, LEVEL_INFO, + "BAR0 Base Cpu Mapping @ 0x%p and BAR2 Base Cpu Mapping @ 0x%p\n", + pGpu->deviceMappings[0].gpuNvAddr->Reg032, + pKernelBus->virtualBar2[gfid].pCpuMapping); -cleanup: if (status != NV_OK) { kbusTeardownBar2CpuAperture_HAL(pGpu, pKernelBus, gfid); @@ -1298,55 +1377,41 @@ kbusTeardownBar2CpuAperture_GM107 return NV_OK; } - if (KBUS_BAR2_TUNNELLED(pKernelBus)) + if (pKernelBus->virtualBar2[gfid].pPageLevels) { - // Unmap bar2 space - if (pKernelBus->virtualBar2[gfid].pCpuMapping) - { - // Remove the memory access filter - osMemRemoveFilter((NvU64)((NvUPtr)(pKernelBus->virtualBar2[gfid].pCpuMapping))); - portMemFree(pKernelBus->virtualBar2[gfid].pCpuMapping); - pKernelBus->virtualBar2[gfid].pCpuMapping = NULL; - } + memmgrMemDescEndTransfer(GPU_GET_MEMORY_MANAGER(pGpu), + pKernelBus->virtualBar2[gfid].pPageLevelsMemDesc, + TRANSFER_FLAGS_NONE); + pKernelBus->virtualBar2[gfid].pPageLevels = NULL; } - else - { - if (pKernelBus->virtualBar2[gfid].pPageLevels) - { - memmgrMemDescEndTransfer(GPU_GET_MEMORY_MANAGER(pGpu), - pKernelBus->virtualBar2[gfid].pPageLevelsMemDesc, - TRANSFER_FLAGS_NONE); - pKernelBus->virtualBar2[gfid].pPageLevels = NULL; - } - kbusDestroyCpuPointerForBusFlush_HAL(pGpu, pKernelBus); + kbusDestroyCpuPointerForBusFlush_HAL(pGpu, pKernelBus); - kbusFlushVirtualBar2_HAL(pGpu, pKernelBus, NV_FALSE, gfid); + kbusFlushVirtualBar2_HAL(pGpu, pKernelBus, NV_FALSE, gfid); - if (pKernelBus->virtualBar2[gfid].pCpuMapping) - { - osUnmapPciMemoryKernelOld(pGpu, (void*)pKernelBus->virtualBar2[gfid].pCpuMapping); - // Mark the BAR as un-initialized so that a later call - // to initbar2 can succeed. - pKernelBus->virtualBar2[gfid].pCpuMapping = NULL; - } + if (pKernelBus->virtualBar2[gfid].pCpuMapping) + { + osUnmapPciMemoryKernelOld(pGpu, (void*)pKernelBus->virtualBar2[gfid].pCpuMapping); + // Mark the BAR as un-initialized so that a later call + // to initbar2 can succeed. + pKernelBus->virtualBar2[gfid].pCpuMapping = NULL; + } - // - // make sure that the bar2 mode is physical so that the vesa extended - // linear framebuffer works after driver unload. Clear other bits to force - // vid. - // - // if BROKEN_FB, merely rewriting this to 0 (as it already was) causes - // FBACKTIMEOUT -- don't do it (Bug 594539) - // - if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_BROKEN_FB)) - { - GPU_FLD_WR_DRF_DEF(pGpu, _PBUS, _BAR2_BLOCK, _MODE, _PHYSICAL); - // bug 1738008: temporary fix to unblock -inst_in_sys argument - // we tried to correct bar2 unbind sequence but didn't fix the real issue - // will fix this soon 4/8/16 - GPU_REG_RD32(pGpu, NV_PBUS_BAR2_BLOCK); - } + // + // make sure that the bar2 mode is physical so that the vesa extended + // linear framebuffer works after driver unload. Clear other bits to force + // vid. + // + // if BROKEN_FB, merely rewriting this to 0 (as it already was) causes + // FBACKTIMEOUT -- don't do it (Bug 594539) + // + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_BROKEN_FB)) + { + GPU_FLD_WR_DRF_DEF(pGpu, _PBUS, _BAR2_BLOCK, _MODE, _PHYSICAL); + // bug 1738008: temporary fix to unblock -inst_in_sys argument + // we tried to correct bar2 unbind sequence but didn't fix the real issue + // will fix this soon 4/8/16 + GPU_REG_RD32(pGpu, NV_PBUS_BAR2_BLOCK); } return NV_OK; @@ -1413,7 +1478,8 @@ kbusSetupBar2GpuVaSpace_GM107 NV_ASSERT_OR_RETURN(status == NV_OK, status); } - status = memdescAlloc(pKernelBus->bar2[gfid].pInstBlkMemDesc); + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_63, + pKernelBus->bar2[gfid].pInstBlkMemDesc); NV_ASSERT_OR_RETURN(status == NV_OK, status); pKernelBus->bar2[gfid].instBlockBase = @@ -1479,7 +1545,8 @@ kbusSetupBar2GpuVaSpace_GM107 if (IS_GFID_VF(gfid)) { - status = memdescAlloc(pPageLevelsMemDesc); + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_64, + pPageLevelsMemDesc); NV_ASSERT_OR_GOTO(status == NV_OK, cleanup); pKernelBus->bar2[gfid].pdeBase = memdescGetPhysAddr(pPageLevelsMemDesc, @@ -1583,6 +1650,9 @@ kbusSetupBar2GpuVaSpace_GM107 status = mmuWalkReserveEntries(pWalk, pLevelFmt, pKernelBus->bar2[gfid].cpuVisibleBase, pKernelBus->bar2[gfid].cpuVisibleLimit, NV_FALSE); NV_ASSERT_OR_GOTO(NV_OK == status, cleanup); + + pKernelBus->bar2[gfid].cpuVisiblePgTblSize = pKernelBus->bar2[gfid].pageTblInit * pKernelBus->bar2[gfid].pageTblSize; + status = mmuWalkSparsify(pWalk, pKernelBus->bar2[gfid].cpuVisibleBase, pKernelBus->bar2[gfid].cpuVisibleLimit, @@ -2405,7 +2475,8 @@ kbusUpdateRmAperture_GM107 // So keep BAR2 in bootstrap mode to allow BAR0 window updates. // if ((ADDR_FBMEM == pKernelBus->PDEBAR2Aperture || - ADDR_FBMEM == pKernelBus->PTEBAR2Aperture) && + ADDR_FBMEM == pKernelBus->PTEBAR2Aperture || + pGpu->getProperty(pGpu, PDB_PROP_GPU_ZERO_FB)) && !kbusIsPhysicalBar2InitPagetableEnabled(pKernelBus) && pKernelBus->virtualBar2[gfid].pPageLevels == NULL && IS_GFID_PF(gfid)) { @@ -2432,11 +2503,9 @@ kbusUpdateRmAperture_GM107 { osFlushCpuWriteCombineBuffer(); - // PCIE_READ kbusFlush is more efficient and preferred. When not ready, use kbusSendSysmembar(). if (pKernelBus->pReadToFlush != NULL) { - NvU32 flushFlag = BUS_FLUSH_USE_PCIE_READ | - kbusGetFlushAperture(pKernelBus, + NvU32 flushFlag = kbusGetFlushAperture(pKernelBus, memdescGetAddressSpace(pKernelBus->virtualBar2[gfid].pPTEMemDesc)); kbusFlush_HAL(pGpu, pKernelBus, flushFlag); } @@ -2727,28 +2796,6 @@ kbusFlushSingle_GM107 NvU32 flags ) { - NvBool bCoherentCpuMapping = pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING); - - // - // Nothing to be done in the guest in the paravirtualization case or - // if guest is running in SRIOV heavy mode. - // - if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu) || - (IS_VIRTUAL(pGpu) && gpuIsWarBug200577889SriovHeavyEnabled(pGpu))) - { - return NV_OK; - } - - if (bCoherentCpuMapping) - { - // - // This function issues an HWSYNC. This is needed for synchronizing read/writes - // with NVLINK mappings. - // - portAtomicMemoryFenceFull(); - return NV_OK; - } - if (flags & BUS_FLUSH_SYSTEM_MEMORY) { portAtomicMemoryFenceFull(); @@ -2764,64 +2811,9 @@ kbusFlushSingle_GM107 return NV_OK; } - if (kbusIsBarAccessBlocked(pKernelBus)) - { - // If BAR has been blocked, there's nothing to flush for vidmem - return NV_OK; - } - - if (flags & BUS_FLUSH_VIDEO_MEMORY) + if ((flags & BUS_FLUSH_VIDEO_MEMORY) && !kbusIsFbFlushDisabled(pKernelBus)) { - // - // Read the FB address 0 in order to trigger a flush. - // This will not work with reflected mappings so only enable on VOLTA+ - // Note SRIOV guest does not have access to uflush register. - // - // TODO: remove the BUS_FLUSH_USE_PCIE_READ flag from RM and do this - // everywhere since it's faster than uflush. - // - if (IS_VIRTUAL(pGpu) || - (kbusIsReadCpuPointerToFlushEnabled(pKernelBus) && - (flags & BUS_FLUSH_USE_PCIE_READ))) - { - volatile NvU32 data; - NV_ASSERT(pKernelBus->pReadToFlush != NULL || pKernelBus->virtualBar2[GPU_GFID_PF].pCpuMapping != NULL); - - if (pKernelBus->pReadToFlush != NULL) - { - data = MEM_RD32(pKernelBus->pReadToFlush); - } - else if (pKernelBus->virtualBar2[GPU_GFID_PF].pCpuMapping != NULL) - { - // - // pReadToFlush is still not ready for use. So, use pCpuMapping - // instead which should already be mapped to FB addr 0 as - // BAR2 is in physical mode right now. - // - data = MEM_RD32(pKernelBus->virtualBar2[GPU_GFID_PF].pCpuMapping); - } - (void) data; - return NV_OK; - } - else - { - if (IS_GSP_CLIENT(pGpu)) - { - // - // on GSP client, we should use PCIE_READ to do video memory flush. - // A sysmembar flush that touches registers is done through RPC and has - // lower effeciency. For cases where it needs sysmembar, the caller site - // should use kbusSendSysmembarSingle_HAL explicitly. - // - NV_ASSERT(0); - - // This will dump a stack trace to assist debug on certain - // platforms. - osAssertFailed(); - } - - return kbusSendSysmembarSingle_HAL(pGpu, pKernelBus); - } + return kbusSendSysmembarSingle_HAL(pGpu, pKernelBus); } return NV_OK; @@ -2849,13 +2841,6 @@ kbusFlush_GM107(OBJGPU *pGpu, KernelBus *pKernelBus, NvU32 flags) return NV_OK; } - if (kbusIsFbFlushDisabled(pKernelBus)) - { - // Eliminate FB flushes, but keep mmu invalidates - NV_PRINTF(LEVEL_INFO, "disable_fb_flush flag, skipping flush.\n"); - return status; - } - // Wait for the flush to flow through SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY | SLI_LOOP_FLAGS_IGNORE_REENTRANCY); pKernelBus = GPU_GET_KERNEL_BUS(pGpu); @@ -2895,7 +2880,15 @@ _kbusMapAperture_GM107 NvU32 swizzId = KMIGMGR_SWIZZID_INVALID; NvU32 gfid; - NV_ASSERT_OK_OR_RETURN(vgpuGetCallingContextGfid(pGpu, &gfid)); + if (kbusIsStaticBar1Enabled(pGpu, pKernelBus) && + (memdescGetAddressSpace(pMemDesc) == ADDR_FBMEM)) + { + NV_ASSERT_OK_OR_RETURN(vgpuGetCallingContextGfid(pGpu, &gfid)); + + return kbusGetStaticFbAperture_HAL(pGpu, pKernelBus, pMemDesc, + offset, pAperOffset, + pLength, gfid); + } // Ensure that the BAR1 VA space is the same across all subdevices if (IsSLIEnabled(pGpu) && ((mapFlags & BUS_MAP_FB_FLAGS_MAP_UNICAST) == 0)) @@ -2904,14 +2897,6 @@ _kbusMapAperture_GM107 gpumgrSetBcEnabledStatus(pGpu, NV_TRUE); } - if (pKernelBus->bar1[gfid].bStaticBar1Enabled && - (memdescGetAddressSpace(pMemDesc) == ADDR_FBMEM)) - { - return kbusStaticMapFbAperture_HAL(pGpu, pKernelBus, pMemDesc, - offset, pAperOffset, - pLength, gfid); - } - if (mapFlags & BUS_MAP_FB_FLAGS_MAP_OFFSET_FIXED) { flags = FLD_SET_DRF(OS46, _FLAGS, _DMA_OFFSET_FIXED, _TRUE, flags); @@ -3017,14 +3002,12 @@ _kbusUnmapAperture_GM107 { NV_STATUS rmStatus = NV_OK; VirtMemAllocator *pDma = GPU_GET_DMA(pGpu); - NvU32 gfid; - - NV_ASSERT_OK_OR_RETURN(vgpuGetCallingContextGfid(pGpu, &gfid)); - if (pKernelBus->bar1[gfid].bStaticBar1Enabled && + if (kbusIsStaticBar1Enabled(pGpu, pKernelBus) && (memdescGetAddressSpace(pMemDesc) == ADDR_FBMEM)) { - return kbusStaticUnmapFbAperture_HAL(pGpu, pKernelBus, pMemDesc, gfid); + // No op for the static bar1 mode + return NV_OK; } rmStatus = dmaFreeMapping_HAL(pGpu, pDma, pVAS, aperOffset, pMemDesc, 0, NULL); @@ -3535,7 +3518,7 @@ kbusStateDestroy_GM107 // Call _kbusDestroyP2P_GM107 only in case of Linked SLI and Unlinked SLI. Bug 4182245 if ((pKernelBif != NULL) && ((!pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_P2P_READS_DISABLED) || !pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_P2P_WRITES_DISABLED)) && - (kbusIsP2pInitialized(pKernelBus))) && + (kbusIsP2pInitialized(pKernelBus))) && !gpuIsSelfHosted(pGpu)) { (void)_kbusDestroyP2P_GM107(pGpu, pKernelBus); @@ -3633,7 +3616,8 @@ kbusVerifyBar2_GM107 { memdescCreateExisting(&memDesc, pGpu, size, ADDR_FBMEM, NV_MEMORY_UNCACHED, MEMDESC_FLAGS_NONE); } - status = memdescAlloc(&memDesc); + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_65, + (&memDesc)); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, @@ -3655,6 +3639,7 @@ kbusVerifyBar2_GM107 testMemorySize = NvU64_LO32(size); testAddrSpace = kgmmuGetHwPteApertureFromMemdesc(GPU_GET_KERNEL_GMMU(pGpu), pMemDesc); + // Log error before starting test // ========================================================== // Does the BAR0 window work? @@ -3725,7 +3710,7 @@ kbusVerifyBar2_GM107 (testAddrSpace == NV_MMU_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY)) { // Flush GPU write before proceeding to next test (otherwise it may stomp over following CPU writes) - kbusFlush_HAL(pGpu, pKernelBus, BUS_FLUSH_VIDEO_MEMORY | BUS_FLUSH_USE_PCIE_READ); + kbusFlush_HAL(pGpu, pKernelBus, BUS_FLUSH_VIDEO_MEMORY); } // ========================================================== @@ -3750,7 +3735,7 @@ kbusVerifyBar2_GM107 if ((testAddrSpace == NV_MMU_PTE_APERTURE_SYSTEM_COHERENT_MEMORY) || (testAddrSpace == NV_MMU_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY)) { - kbusFlush_HAL(pGpu, pKernelBus, BUS_FLUSH_VIDEO_MEMORY | BUS_FLUSH_USE_PCIE_READ); + kbusFlush_HAL(pGpu, pKernelBus, BUS_FLUSH_VIDEO_MEMORY); } osFlushCpuWriteCombineBuffer(); @@ -3795,7 +3780,7 @@ kbusVerifyBar2_GM107 GPU_FLD_WR_DRF_NUM(pGpu, _PBUS, _BAR0_WINDOW, _BASE, NvU64_LO32(bar0Window >> 16)); GPU_FLD_WR_DRF_NUM(pGpu, _PBUS, _BAR0_WINDOW, _TARGET, oldAddrSpace); - status = kbusFlush_HAL(pGpu, pKernelBus, BUS_FLUSH_VIDEO_MEMORY | BUS_FLUSH_USE_PCIE_READ); + status = kbusFlush_HAL(pGpu, pKernelBus, BUS_FLUSH_VIDEO_MEMORY); // Bail now if we have encountered any error if (status != NV_OK) @@ -3826,6 +3811,7 @@ kbusVerifyBar2_GM107 } kbusVerifyBar2_failed: + if (bIsStandaloneTest) { if (pOffset != NULL) @@ -3839,6 +3825,7 @@ kbusVerifyBar2_GM107 if (status == NV_OK) { NV_PRINTF_COND(IS_EMULATION(pGpu), LEVEL_NOTICE, LEVEL_INFO, "BAR2 virtual test passes\n"); + } return status; @@ -4086,65 +4073,6 @@ NvU32 kbusGetSizeOfBar2PageDirs_GM107 return size; } -/*! - * @brief Tunnel bar2 accesses through bar0 window. - * - * This routine is used to re-direct the bar2 accesses which were mapped as - * type BUSBARMAP_TYPE_BAR through the bar0 window. This is a callback - * routine called by osMem[Rd|Wr]*, portMemSet and portMemCopy routines when they - * detect an address is in the bar2 range. - * - * @param[in] *pPrivData - Void pointer to callback-user-defined data. - * For the purpose here pPrivData just contains - * a pointer to pGpu - * @param[in] addr - The address to be tunneled. - * @param[in/out] *pData - Pointer to the data to be read/written. - * @param[in] size - Size of the data to be read/written. - * @param[in] bRead - Read/Write indicator. - * - * @returns NV_OK - if tunneling is successful. - * NV_ERR_INVALID_ARGUMENT if the addr argument is not valid - */ -static NV_STATUS -_kbusBar0TunnelCb_GM107 -( - void *pPrivData, - NvU64 addr, - void *pData, - NvU64 size, - NvBool bRead -) -{ - OBJGPU *pGpu = reinterpretCast(pPrivData, OBJGPU *); - KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); - VirtualBar2MapListIter it; - NvU32 offset; - - it = listIterAll(&pKernelBus->virtualBar2[GPU_GFID_PF].usedMapList); - while (listIterNext(&it)) - { - VirtualBar2MapEntry *pMap = it.pValue; - - // Check if there is a valid mapping for the address passed-in - if (addr >= (NvU64)((NvUPtr)pMap->pRtnPtr) && - (addr + size - 1) < ((NvU64)((NvUPtr)pMap->pRtnPtr) + pMap->pMemDesc->Size)) - { - // Re-direct the access through bar0 window - offset = (NvU32)(addr - (NvU64)((NvUPtr)pMap->pRtnPtr)); - return kbusMemAccessBar0Window_HAL( - pGpu, - pKernelBus, - memdescGetPhysAddr(pMap->pMemDesc, FORCE_VMMU_TRANSLATION(pMap->pMemDesc, AT_GPU), offset), - pData, - size, - bRead, - memdescGetAddressSpace(pMap->pMemDesc)); - } - } - - return NV_ERR_INVALID_ARGUMENT; -} - NvU64 kbusGetBAR0WindowAddress_GM107 ( @@ -4154,7 +4082,6 @@ kbusGetBAR0WindowAddress_GM107 return NV_PRAMIN_DATA008(0); } - /*! * @brief Returns the first available peer Id * @@ -4749,7 +4676,8 @@ kbusBar1InstBlkVasUpdate_GM107 NV_ASSERT_OR_RETURN(status == NV_OK, status); } - status = memdescAlloc(pKernelBus->bar1[gfid].pInstBlkMemDesc); + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_66, + pKernelBus->bar1[gfid].pInstBlkMemDesc); NV_ASSERT_OR_RETURN(status == NV_OK, status); status = memmgrMemDescMemSet(pMemoryManager, @@ -4772,7 +4700,7 @@ kbusBar1InstBlkVasUpdate_GM107 // (Re-)bind instance block so host fetches the new VAS state. // Flush to ensure host sees the latest. // - kbusFlush_HAL(pGpu, pKernelBus, BUS_FLUSH_VIDEO_MEMORY | BUS_FLUSH_USE_PCIE_READ); + kbusFlush_HAL(pGpu, pKernelBus, BUS_FLUSH_VIDEO_MEMORY); kbusSendSysmembar(pGpu, pKernelBus); return NV_OK; diff --git a/src/nvidia/src/kernel/gpu/bus/arch/pascal/kern_bus_gp100.c b/src/nvidia/src/kernel/gpu/bus/arch/pascal/kern_bus_gp100.c index 2339539833..dd4755de40 100644 --- a/src/nvidia/src/kernel/gpu/bus/arch/pascal/kern_bus_gp100.c +++ b/src/nvidia/src/kernel/gpu/bus/arch/pascal/kern_bus_gp100.c @@ -21,9 +21,6 @@ * DEALINGS IN THE SOFTWARE. */ -// FIXME XXX -#define NVOC_KERNEL_NVLINK_H_PRIVATE_ACCESS_ALLOWED - #include "core/core.h" #include "gpu/gpu.h" #include "mem_mgr/vaspace.h" @@ -515,8 +512,8 @@ _kbusRemoveNvlinkPeerMapping PDB_PROP_KBUS_NVLINK_DECONFIG_HSHUB_ON_NO_MAPPING)) { // Before removing the NVLink peer mapping in HSHUB flush both ends - kbusFlush_HAL(pGpu0, pKernelBus0, BUS_FLUSH_VIDEO_MEMORY | BUS_FLUSH_USE_PCIE_READ); - kbusFlush_HAL(pGpu1, GPU_GET_KERNEL_BUS(pGpu1), BUS_FLUSH_VIDEO_MEMORY | BUS_FLUSH_USE_PCIE_READ); + kbusFlush_HAL(pGpu0, pKernelBus0, BUS_FLUSH_VIDEO_MEMORY); + kbusFlush_HAL(pGpu1, GPU_GET_KERNEL_BUS(pGpu1), BUS_FLUSH_VIDEO_MEMORY); } if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu0)) @@ -586,7 +583,7 @@ _kbusRemoveNvlinkPeerMapping return status; } - bBufferReady = ((pKernelNvlink0->initializedLinks & pKernelNvlink0->peerLinkMasks[peerId]) != 0) ? NV_TRUE : NV_FALSE; + bBufferReady = ((knvlinkGetInitializedLinkMask(pGpu0, pKernelNvlink0) & knvlinkGetPeerLinkMask(pGpu0, pKernelNvlink0, peerId)) != 0) ? NV_TRUE : NV_FALSE; if (!pKernelNvlink0->getProperty(pKernelNvlink0, PDB_PROP_KNVLINK_CONFIG_REQUIRE_INITIALIZED_LINKS_CHECK) || !bBufferReady) { @@ -816,7 +813,7 @@ kbusGetNvlinkP2PPeerId_GP100 (knvlinkGetPeersNvlinkMaskFromHshub(pGpu0, pKernelNvlink0) != 0)) { if (knvlinkIsForcedConfig(pGpu0, pKernelNvlink0) || - pKernelNvlink0->bRegistryLinkOverride) + knvlinkAreLinksRegistryOverriden(pGpu0, pKernelNvlink0)) { *nvlinkPeer = kbusGetPeerIdFromTable_HAL(pGpu0, pKernelBus0, pGpu0->gpuInstance, diff --git a/src/nvidia/src/kernel/gpu/bus/arch/volta/kern_bus_gv100.c b/src/nvidia/src/kernel/gpu/bus/arch/volta/kern_bus_gv100.c index 1d9b2bee3c..2c38bdae87 100644 --- a/src/nvidia/src/kernel/gpu/bus/arch/volta/kern_bus_gv100.c +++ b/src/nvidia/src/kernel/gpu/bus/arch/volta/kern_bus_gv100.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2016-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -69,7 +69,8 @@ kbusSetupCpuPointerForBusFlush_GV100 NV_ASSERT_OR_GOTO(status == NV_OK, cleanup); // Allocate memory from reserved heap for flush - status = memdescAlloc(pKernelBus->pFlushMemDesc); + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_54, + pKernelBus->pFlushMemDesc); NV_ASSERT_OR_GOTO(status == NV_OK, cleanup); // @@ -214,7 +215,7 @@ kbusUnmapCoherentCpuMapping_GV100 } // Flush the memory since caller writes to the FB - kbusFlush_HAL(pGpu, GPU_GET_KERNEL_BUS(pGpu), BUS_FLUSH_VIDEO_MEMORY | BUS_FLUSH_USE_PCIE_READ); + kbusFlush_HAL(pGpu, GPU_GET_KERNEL_BUS(pGpu), BUS_FLUSH_VIDEO_MEMORY); return; } @@ -293,3 +294,95 @@ kbusTeardownCoherentCpuMapping_GV100 pKernelBus->coherentCpuMapping.bCoherentCpuMapping = NV_FALSE; } + +/*! + * @brief Lower level FB flush to push pending writes to FB/sysmem + * + * NOTE: Must be called inside a SLI loop + * + * @param[in] pGpu + * @param[in] KernelBus + * @param[in] flags Flags to indicate aperture and other behaviors + * @return NV_OK on success + * + */ +NV_STATUS +kbusFlushSingle_GV100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + NvU32 flags +) +{ + NvBool bCoherentCpuMapping = pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING); + + // + // Nothing to be done in the guest in the paravirtualization case or + // if guest is running in SRIOV heavy mode. + // + if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu) || + (IS_VIRTUAL(pGpu) && gpuIsWarBug200577889SriovHeavyEnabled(pGpu))) + { + return NV_OK; + } + + if (bCoherentCpuMapping) + { + // + // This function issues an HWSYNC. This is needed for synchronizing read/writes + // with NVLINK mappings. + // + portAtomicMemoryFenceFull(); + return NV_OK; + } + + if (flags & BUS_FLUSH_SYSTEM_MEMORY) + { + portAtomicMemoryFenceFull(); + } + + if (API_GPU_IN_RESET_SANITY_CHECK(pGpu) || API_GPU_IN_RECOVERY_SANITY_CHECK(pGpu) || + !API_GPU_ATTACHED_SANITY_CHECK(pGpu)) + { + // + // When the GPU is in full chip reset or lost + // We cannot expect to flush successfully so early return here + // + return NV_OK; + } + + if (kbusIsBarAccessBlocked(pKernelBus)) + { + // If BAR has been blocked, there's nothing to flush for vidmem + return NV_OK; + } + + if ((flags & BUS_FLUSH_VIDEO_MEMORY) && kbusIsReadCpuPointerToFlushEnabled(pKernelBus)) + { + volatile NvU32 data; + + // + // Read the FB address 0 in order to trigger a flush. + // This will not work with reflected mappings so only enable on VOLTA+ + // Note SRIOV guest does not have access to uflush register. + // + NV_ASSERT(pKernelBus->pReadToFlush != NULL || pKernelBus->virtualBar2[GPU_GFID_PF].pCpuMapping != NULL); + + if (pKernelBus->pReadToFlush != NULL) + { + data = MEM_RD32(pKernelBus->pReadToFlush); + } + else if (pKernelBus->virtualBar2[GPU_GFID_PF].pCpuMapping != NULL) + { + // + // pReadToFlush is still not ready for use. So, use pCpuMapping + // instead which should already be mapped to FB addr 0 as + // BAR2 is in physical mode right now. + // + data = MEM_RD32(pKernelBus->virtualBar2[GPU_GFID_PF].pCpuMapping); + } + (void) data; + } + + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/bus/kern_bus.c b/src/nvidia/src/kernel/gpu/bus/kern_bus.c index 24e28d7397..738f410415 100644 --- a/src/nvidia/src/kernel/gpu/bus/kern_bus.c +++ b/src/nvidia/src/kernel/gpu/bus/kern_bus.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -196,20 +196,25 @@ kbusInitRegistryOverrides(OBJGPU *pGpu, KernelBus *pKernelBus) pKernelBus->bP2pMailboxClientAllocated = !!data32; } + if (osReadRegistryDword(pGpu, NV_REG_STR_RESTORE_BAR1_SIZE_BUG_3249028_WAR, &data32) == NV_OK) + { + pKernelBus->setProperty(pKernelBus, PDB_PROP_KBUS_RESTORE_BAR1_SIZE_BUG_3249028_WAR, !!data32); + } + return NV_OK; } /** - * @brief Gets the BAR1 VA range for a client + * @brief Gets the BAR1 VA range for a device * * @param[in] pGpu * @param[in] pKernelBus - * @param[in] hClient Client handle + * @param[in] pDevice Device pointer * @param[out] pBar1VARange BAR1 VA range */ NV_STATUS -kbusGetBar1VARangeForClient_IMPL(OBJGPU *pGpu, KernelBus *pKernelBus, NvHandle hClient, NV_RANGE *pBar1VARange) +kbusGetBar1VARangeForDevice_IMPL(OBJGPU *pGpu, KernelBus *pKernelBus, Device *pDevice, NV_RANGE *pBar1VARange) { KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); OBJVASPACE *pBar1VAS = kbusGetBar1VASpace_HAL(pGpu, pKernelBus); @@ -219,8 +224,8 @@ kbusGetBar1VARangeForClient_IMPL(OBJGPU *pGpu, KernelBus *pKernelBus, NvHandle h *pBar1VARange = rangeMake(vaspaceGetVaStart(pBar1VAS), vaspaceGetVaLimit(pBar1VAS)); if ((pKernelMIGManager != NULL) && kmigmgrIsMIGMemPartitioningEnabled(pGpu, pKernelMIGManager) && - !rmclientIsCapableByHandle(hClient, NV_RM_CAP_SYS_SMC_MONITOR) && - !kmigmgrIsClientUsingDeviceProfiling(pGpu, pKernelMIGManager, hClient)) + !rmclientIsCapableByHandle(RES_GET_CLIENT_HANDLE(pDevice), NV_RM_CAP_SYS_SMC_MONITOR) && + !kmigmgrIsDeviceUsingDeviceProfiling(pGpu, pKernelMIGManager, pDevice)) { MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); @@ -228,8 +233,8 @@ kbusGetBar1VARangeForClient_IMPL(OBJGPU *pGpu, KernelBus *pKernelBus, NvHandle h *pBar1VARange = memmgrGetMIGPartitionableBAR1Range(pGpu, pMemoryManager); - NV_ASSERT_OK_OR_RETURN(kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, - hClient, &ref)); + NV_ASSERT_OK_OR_RETURN(kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + pDevice, &ref)); NV_ASSERT_OK_OR_RETURN(kmemsysSwizzIdToMIGMemRange(pGpu, pKernelMemorySystem, ref.pKernelMIGGpuInstance->swizzId, *pBar1VARange, pBar1VARange)); } @@ -332,13 +337,6 @@ kbusSendSysmembar_IMPL return NV_OK; } - if (kbusIsFbFlushDisabled(pKernelBus)) - { - // Eliminate FB flushes, but keep mmu invalidates - NV_PRINTF(LEVEL_INFO, "disable_fb_flush flag, skipping flush.\n"); - return NV_OK; - } - // Wait for the flush to flow through SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY | SLI_LOOP_FLAGS_IGNORE_REENTRANCY); pKernelBus = GPU_GET_KERNEL_BUS(pGpu); @@ -887,9 +885,10 @@ kbusCheckEngine_KERNEL return !!NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, RM_ENGINE_TYPE_NVDEC(GET_NVDEC_IDX(engDesc))); - case ENG_OFA: + case ENG_OFA(0): return !!NVGPU_GET_ENGINE_CAPS_MASK(rmEngineCaps, - RM_ENGINE_TYPE_OFA); + RM_ENGINE_TYPE_OFA(GET_OFA_IDX(engDesc))); + case ENG_NVJPEG(0): case ENG_NVJPEG(1): case ENG_NVJPEG(2): @@ -1233,27 +1232,37 @@ kbusGetNvlinkP2PPeerId_VGPU } /** - * @brief Check for any P2P references in to remote GPUs - * which are still have a P2P api object alive. + * @brief Check if the static bar1 is enabled * * @param[in] pGpu * @param[in] pKernelBus */ -NV_STATUS -kbusIsGpuP2pAlive_IMPL +NvBool +kbusIsStaticBar1Enabled_IMPL ( OBJGPU *pGpu, KernelBus *pKernelBus ) { - return (pKernelBus->totalP2pObjectsAliveRefCount > 0); + NvU32 gfid; + + return ((vgpuGetCallingContextGfid(pGpu, &gfid) == NV_OK) && + pKernelBus->bar1[gfid].bStaticBar1Enabled); } /** - * @brief Setup VF BAR2 during hibernate resume + * @brief Check for any P2P references in to remote GPUs + * which are still have a P2P api object alive. * * @param[in] pGpu * @param[in] pKernelBus - * @param[in] flags */ - +NV_STATUS +kbusIsGpuP2pAlive_IMPL +( + OBJGPU *pGpu, + KernelBus *pKernelBus +) +{ + return (pKernelBus->totalP2pObjectsAliveRefCount > 0); +} diff --git a/src/nvidia/src/kernel/gpu/bus/kern_bus_vbar2.c b/src/nvidia/src/kernel/gpu/bus/kern_bus_vbar2.c index 3360e17058..9e330fe08f 100644 --- a/src/nvidia/src/kernel/gpu/bus/kern_bus_vbar2.c +++ b/src/nvidia/src/kernel/gpu/bus/kern_bus_vbar2.c @@ -384,7 +384,7 @@ kbusInitVirtualBar2_VBAR2 pMemDesc = pKernelBus->virtualBar2[gfid].pPageLevelsMemDesc; - if (KBUS_BAR2_TUNNELLED(pKernelBus) || kbusIsBarAccessBlocked(pKernelBus)) + if (kbusIsBarAccessBlocked(pKernelBus)) { return NV_OK; } @@ -441,7 +441,7 @@ kbusPreInitVirtualBar2_VBAR2 pMemDesc = pKernelBus->virtualBar2[gfid].pPageLevelsMemDescForBootstrap; - if (KBUS_BAR2_TUNNELLED(pKernelBus) || kbusIsBarAccessBlocked(pKernelBus)) + if (kbusIsBarAccessBlocked(pKernelBus)) { return NV_OK; } @@ -486,7 +486,7 @@ _freeRmApertureMap_VBAR2 listRemove(&pKernelBus->virtualBar2[GPU_GFID_PF].cachedMapList, pMap); - if (!KBUS_BAR2_TUNNELLED(pKernelBus) && pKernelBus->virtualBar2[GPU_GFID_PF].pCpuMapping) + if (pKernelBus->virtualBar2[GPU_GFID_PF].pCpuMapping) { pBlockFree = pVASpaceHeap->eheapGetBlock(pVASpaceHeap, pMap->vAddr, NV_FALSE); @@ -689,8 +689,7 @@ kbusMapBar2ApertureCached_VBAR2 // Update the page tables if (pKernelBus->virtualBar2[GPU_GFID_PF].pCpuMapping == NULL || - (!KBUS_BAR2_TUNNELLED(pKernelBus) && - NV_OK != kbusUpdateRmAperture_HAL(pGpu, pKernelBus, pMemDesc, vAddr, + (NV_OK != kbusUpdateRmAperture_HAL(pGpu, pKernelBus, pMemDesc, vAddr, pMemDesc->PageCount * pMemDesc->pageArrayGranularity, UPDATE_RM_APERTURE_FLAGS_INVALIDATE))) { @@ -988,7 +987,7 @@ kbusUnmapBar2ApertureWithFlags_SCRATCH ) { portMemFree(*pCpuPtr); - kbusFlush_HAL(pGpu, pKernelBus, kbusGetFlushAperture(pKernelBus, memdescGetAddressSpace(pMemDesc)) | BUS_FLUSH_USE_PCIE_READ); + kbusFlush_HAL(pGpu, pKernelBus, kbusGetFlushAperture(pKernelBus, memdescGetAddressSpace(pMemDesc))); } /*! diff --git a/src/nvidia/src/kernel/gpu/bus/p2p.c b/src/nvidia/src/kernel/gpu/bus/p2p.c index 81eae841ef..065746d306 100644 --- a/src/nvidia/src/kernel/gpu/bus/p2p.c +++ b/src/nvidia/src/kernel/gpu/bus/p2p.c @@ -25,6 +25,7 @@ #include "core/locks.h" #include #include "gpu/gpu.h" +#include "gpu/subdevice/subdevice.h" #include "gpu/mem_sys/kern_mem_sys.h" #include "gpu/mem_mgr/mem_mgr.h" #include "kernel/mem_mgr/p2p.h" @@ -156,13 +157,10 @@ NV_STATUS _createThirdPartyP2PMappingExtent NV_STATUS status; KernelBus *pKernelBus; PCLI_THIRD_PARTY_P2P_MAPPING_EXTENT_INFO pExtentInfoTmp; - Device *pDevice; + Device *pDevice = GPU_RES_GET_DEVICE(pSubDevice); NvBool bGpuLockTaken = (rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu)) || rmGpuLockIsOwner()); - status = deviceGetByGpu(pClient, pGpu, NV_TRUE, &pDevice); - NV_ASSERT_OR_RETURN(status == NV_OK, NV_ERR_INVALID_STATE); - NV_PRINTF(LEVEL_INFO, "New allocation for address: 0x%llx\n", address); NV_ASSERT_OR_RETURN((pDevice != NULL), NV_ERR_INVALID_STATE); @@ -365,7 +363,7 @@ NV_STATUS RmThirdPartyP2PMappingFree NvU64 startOffset; PCLI_THIRD_PARTY_P2P_MAPPING_EXTENT_INFO pExtentInfo = NULL; PCLI_THIRD_PARTY_P2P_MAPPING_EXTENT_INFO pExtentInfoNext = NULL; - Device *pDevice; + Device *pDevice = GPU_RES_GET_DEVICE(pSubDevice); NvBool bGpuLockTaken; NvBool bVgpuRpc; @@ -376,10 +374,6 @@ NV_STATUS RmThirdPartyP2PMappingFree NV_ASSERT_OR_RETURN((pMappingInfo != NULL), NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN((pSubDevice != NULL), NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN((pThirdPartyP2PInfo != NULL), NV_ERR_INVALID_ARGUMENT); - - status = deviceGetByGpu(pClient, pGpu, NV_TRUE, &pDevice); - NV_ASSERT_OR_RETURN(status == NV_OK, NV_ERR_INVALID_STATE); - NV_ASSERT_OR_RETURN((pDevice != NULL), NV_ERR_INVALID_STATE); pKernelBus = GPU_GET_KERNEL_BUS(pGpu); @@ -1132,12 +1126,7 @@ CLI_THIRD_PARTY_P2P_VIDMEM_INFO* _createOrReuseVidmemInfoPersistent } pClientInternal = RES_GET_CLIENT(pThirdPartyP2PInternal); - - status = deviceGetByGpu(pClientInternal, pGpu, NV_TRUE, &pDevice); - if (status != NV_OK) - { - goto failed; - } + pDevice = GPU_RES_GET_DEVICE(pThirdPartyP2PInternal); // Dupe user client's hMemory status = pRmApi->DupObject(pRmApi, @@ -1236,11 +1225,6 @@ NV_STATUS RmP2PGetPagesPersistent( pThirdPartyP2PInternal = dynamicCast(pResourceRef->pResource, ThirdPartyP2P); - if (status != NV_OK) - { - return NV_ERR_INVALID_OBJECT_HANDLE; - } - pVidmemInfo = _createOrReuseVidmemInfoPersistent(pGpu, address, length, &offset, pThirdPartyP2P, pThirdPartyP2PInternal); diff --git a/src/nvidia/src/kernel/gpu/bus/p2p_api.c b/src/nvidia/src/kernel/gpu/bus/p2p_api.c index f3296a96cf..29e09be9f7 100644 --- a/src/nvidia/src/kernel/gpu/bus/p2p_api.c +++ b/src/nvidia/src/kernel/gpu/bus/p2p_api.c @@ -23,6 +23,7 @@ #include "core/core.h" #include "gpu/gpu.h" +#include "gpu/subdevice/subdevice.h" #include "gpu/bus/kern_bus.h" #include "gpu/bus/p2p_api.h" #include "gpu/bus/third_party_p2p.h" @@ -585,7 +586,8 @@ p2papiConstruct_IMPL DRF_DEF(_P2PAPI, _ATTRIBUTES, _REMOTE_EGM, _YES))); } - if (p2pConnectionType == P2P_CONNECTIVITY_PCIE_BAR1) + if ((p2pConnectionType == P2P_CONNECTIVITY_PCIE_BAR1) && + (pCallContext->secInfo.privLevel >= RS_PRIV_LEVEL_KERNEL)) { NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kbusGetBar1P2PDmaInfo_HAL(pLocalGpu, pRemoteGpu, diff --git a/src/nvidia/src/kernel/gpu/bus/third_party_p2p.c b/src/nvidia/src/kernel/gpu/bus/third_party_p2p.c index fc5a83255d..17c2b42329 100644 --- a/src/nvidia/src/kernel/gpu/bus/third_party_p2p.c +++ b/src/nvidia/src/kernel/gpu/bus/third_party_p2p.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2009-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -24,6 +24,7 @@ #include "core/core.h" #include "core/locks.h" #include "gpu/gpu.h" +#include "gpu/subdevice/subdevice.h" #include "gpu/bus/third_party_p2p.h" #include "platform/p2p/p2p_caps.h" #include "gpu/bus/kern_bus.h" @@ -40,6 +41,11 @@ // static volatile NvU64 vidmemInfoId = 0; +// +// A monotonic counter as ID that's assigned to every new 3rd party p2p class. +// +static volatile NvU64 p2pTokenId = 0; + // // We make sure that only one instance of NV50_THIRD_PARTY_P2P can be active at // a time per client per GPU. It simplifies tuple(VA,size) tracking/validation @@ -111,7 +117,7 @@ thirdpartyp2pConstruct_IMPL return NV_ERR_INVALID_ARGUMENT; } - p2pToken = CLI_ENCODEP2PTOKEN(pGpu->gpuId, hClient); + p2pToken = portAtomicExIncrementU64(&p2pTokenId);; } else if (type == CLI_THIRD_PARTY_P2P_TYPE_NVLINK) { @@ -120,7 +126,7 @@ thirdpartyp2pConstruct_IMPL return NV_ERR_INVALID_STATE; } - p2pToken = CLI_ENCODEP2PTOKEN(pGpu->gpuId, hClient); + p2pToken = portAtomicExIncrementU64(&p2pTokenId);; } else { diff --git a/src/nvidia/src/kernel/gpu/bus/third_party_p2p_ctrl.c b/src/nvidia/src/kernel/gpu/bus/third_party_p2p_ctrl.c index e721cf663f..5e770debcc 100644 --- a/src/nvidia/src/kernel/gpu/bus/third_party_p2p_ctrl.c +++ b/src/nvidia/src/kernel/gpu/bus/third_party_p2p_ctrl.c @@ -23,6 +23,7 @@ #include "core/core.h" #include "gpu/gpu.h" +#include "gpu/subdevice/subdevice.h" #include // FERMI_VASPACE_A #include #include "gpu/bus/third_party_p2p.h" diff --git a/src/nvidia/src/kernel/gpu/ccu/kernel_ccu.c b/src/nvidia/src/kernel/gpu/ccu/kernel_ccu.c index 056b4ac9c5..11b60ae473 100644 --- a/src/nvidia/src/kernel/gpu/ccu/kernel_ccu.c +++ b/src/nvidia/src/kernel/gpu/ccu/kernel_ccu.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -130,7 +130,8 @@ _kccuAllocMemory } // Allocate physical storage for the memory descriptor - status = memdescAlloc(pMemDesc); + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_55, + pMemDesc); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "CCU memdescAlloc failed for(%u) with status: 0x%x\n", idx, status); diff --git a/src/nvidia/src/kernel/gpu/ccu/kernel_ccu_api.c b/src/nvidia/src/kernel/gpu/ccu/kernel_ccu_api.c index a10a0c03de..1aa88d44c4 100644 --- a/src/nvidia/src/kernel/gpu/ccu/kernel_ccu_api.c +++ b/src/nvidia/src/kernel/gpu/ccu/kernel_ccu_api.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -61,7 +61,7 @@ _kccuapiMemdescGet ( KernelCcuApi *pKernelCcuApi, RmClient *pClient, - NvHandle hClient, + Device *pDevice, MEMORY_DESCRIPTOR **pMemDesc ) { @@ -84,7 +84,7 @@ _kccuapiMemdescGet } // In case of MIG - status = kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, &ref); + status = kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, &ref); if (status != NV_OK) { // Check if client is allowed to query for device counters @@ -120,7 +120,7 @@ kccuapiMap_IMPL NV_STATUS status = NV_OK; NvBool bKernel = NV_FALSE; RmClient *pClient = dynamicCast(pCallContext->pClient, RmClient); - NvHandle hClient = pCallContext->pClient->hClient; + Device *pDevice = GPU_RES_GET_DEVICE(pKernelCcuApi); NV_PRINTF(LEVEL_INFO, "Kernel Ccu Api: memdesc map\n"); @@ -135,7 +135,7 @@ kccuapiMap_IMPL pCpuMapping->processId = osGetCurrentProcess(); - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, _kccuapiMemdescGet(pKernelCcuApi, pClient, hClient, &pMemDesc)); + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, _kccuapiMemdescGet(pKernelCcuApi, pClient, pDevice, &pMemDesc)); if (pMemDesc == NULL) { @@ -170,7 +170,7 @@ kccuapiUnmap_IMPL { NV_STATUS status = NV_OK; NvBool bKernel = NV_FALSE; - NvHandle hClient = pCallContext->pClient->hClient; + Device *pDevice = GPU_RES_GET_DEVICE(pKernelCcuApi); RmClient *pClient = dynamicCast(pCallContext->pClient, RmClient); MEMORY_DESCRIPTOR *pMemDesc = NULL; @@ -185,7 +185,7 @@ kccuapiUnmap_IMPL return status; } - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, _kccuapiMemdescGet(pKernelCcuApi, pClient, hClient, &pMemDesc)); + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, _kccuapiMemdescGet(pKernelCcuApi, pClient, pDevice, &pMemDesc)); if (pMemDesc == NULL) { @@ -213,13 +213,13 @@ kccuapiGetMapAddrSpace_IMPL { NV_ADDRESS_SPACE addrSpace = 0; MEMORY_DESCRIPTOR *pMemDesc = NULL; - NvHandle hClient = pCallContext->pClient->hClient; + Device *pDevice = GPU_RES_GET_DEVICE(pKernelCcuApi); RmClient *pClient = dynamicCast(pCallContext->pClient, RmClient); OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelCcuApi); NV_PRINTF(LEVEL_INFO, "Kernel Ccu Api: get memdesc address-space\n"); - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, _kccuapiMemdescGet(pKernelCcuApi, pClient, hClient, &pMemDesc)); + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, _kccuapiMemdescGet(pKernelCcuApi, pClient, pDevice, &pMemDesc)); if (pMemDesc == NULL) { @@ -242,12 +242,12 @@ kccuapiGetMemoryMappingDescriptor_IMPL ) { MEMORY_DESCRIPTOR *pMemDesc = NULL; - NvHandle hClient = RES_GET_CLIENT_HANDLE(pKernelCcuApi); + Device *pDevice = GPU_RES_GET_DEVICE(pKernelCcuApi); RmClient *pClient = dynamicCast(RES_GET_CLIENT(pKernelCcuApi), RmClient); NV_PRINTF(LEVEL_INFO, "Kernel Ccu Api: get memdesc\n"); - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, _kccuapiMemdescGet(pKernelCcuApi, pClient, hClient, &pMemDesc)); + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, _kccuapiMemdescGet(pKernelCcuApi, pClient, pDevice, &pMemDesc)); if (pMemDesc == NULL) { @@ -270,7 +270,7 @@ kccuapiCtrlCmdSubscribe_IMPL MIG_INSTANCE_REF ref; MEMORY_DESCRIPTOR *pMemDesc = NULL; NV_STATUS status = NV_OK; - NvHandle hClient = RES_GET_CLIENT_HANDLE(pKernelCcuApi); + Device *pDevice = GPU_RES_GET_DEVICE(pKernelCcuApi); OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelCcuApi); KernelCcu *pKernelCcu = GPU_GET_KERNEL_CCU(pGpu); RmClient *pClient = dynamicCast(RES_GET_CLIENT(pKernelCcuApi), RmClient); @@ -300,7 +300,7 @@ kccuapiCtrlCmdSubscribe_IMPL } // In case of MIG - status = kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, &ref); + status = kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, &ref); if (status != NV_OK) { // Check if client is allowed to query for device counters or not diff --git a/src/nvidia/src/kernel/gpu/ce/arch/ampere/kernel_ce_ga100.c b/src/nvidia/src/kernel/gpu/ce/arch/ampere/kernel_ce_ga100.c index a25ab96374..b9c1be8ffe 100644 --- a/src/nvidia/src/kernel/gpu/ce/arch/ampere/kernel_ce_ga100.c +++ b/src/nvidia/src/kernel/gpu/ce/arch/ampere/kernel_ce_ga100.c @@ -475,7 +475,7 @@ kceGetMappings_GA100 } // Prepare the per-HSHUB/FBHUB available PCE mask - status = kceGetAvailableHubPceMask(pGpu, pTopoParams); + status = kceGetAvailableHubPceMask(pGpu, pKCe, pTopoParams); // A. Start with assigning PCEs for "SYSMEM" status = kceMapPceLceForSysmemLinks_HAL(pGpu, pKCe, diff --git a/src/nvidia/src/kernel/gpu/ce/arch/hopper/kernel_ce_gh100.c b/src/nvidia/src/kernel/gpu/ce/arch/hopper/kernel_ce_gh100.c index dcbef2102f..b9faa5d540 100644 --- a/src/nvidia/src/kernel/gpu/ce/arch/hopper/kernel_ce_gh100.c +++ b/src/nvidia/src/kernel/gpu/ce/arch/hopper/kernel_ce_gh100.c @@ -45,7 +45,6 @@ #define NV_CE_NUM_FBPCE 4 #define NV_CE_NUM_PCES_NO_LINK_CASE 12 #define NV_CE_MAX_PCE_PER_GRCE 2 -#define NV_CE_HSHUBNVL_ID_0 2 /* * Table for setting the PCE2LCE mapping for WAR configs that cannot be implemented @@ -893,7 +892,7 @@ kceGetMappings_GH100 } //Prepare the per-HSHUB/FBHUB available PCE mask - kceGetAvailableHubPceMask(pGpu, pTopoParams); + kceGetAvailableHubPceMask(pGpu, pKCe, pTopoParams); // Assign PCEs to "PEER"s if nvlink is enabled if (pKernelNvlink && !knvlinkIsForcedConfig(pGpu, pKernelNvlink)) @@ -932,181 +931,3 @@ kceGetMappings_GH100 NV_PRINTF(LEVEL_INFO, "status = %d, statusC2C = %d\n", status, statusC2C); return NV_OK; } - -NV_STATUS kceGetP2PCes_GH100(KernelCE *pKCe, OBJGPU *pGpu, NvU32 gpuMask, NvU32 *nvlinkP2PCeMask) -{ - // - // Currently Bug 4103154 requires an updated algorithm described below - // to assign the proper LCE. Cases without MODS enabled can default back - // to the previous version. - // - return kceGetP2PCes_GV100(pKCe, pGpu, gpuMask, nvlinkP2PCeMask); - - NvU32 gpuCount = gpumgrGetSubDeviceCount(gpuMask); - NvU32 minP2PLce = (NV_CE_EVEN_ASYNC_LCE_MASK | NV_CE_ODD_ASYNC_LCE_MASK) & NV_CE_MAX_LCE_MASK; - NvU32 i; - KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); - - if (pKernelNvlink == NULL) - { - return NV_WARN_NOTHING_TO_DO; - } - - if (knvlinkIsGpuConnectedToNvswitch(pGpu, pKernelNvlink)) - { - return kceGetP2PCes_GV100(pKCe, pGpu, gpuMask, nvlinkP2PCeMask); - } - - LOWESTBITIDX_32(minP2PLce); - *nvlinkP2PCeMask = 0; - - if (gpuCount == 1) - { - *nvlinkP2PCeMask |= NVBIT(minP2PLce); - for (i = minP2PLce; i < gpuGetNumCEs(pGpu); i++) - { - *nvlinkP2PCeMask |= NVBIT(i); - - } - } - else if (gpuCount > 2) - { - // if gpuCount > 2, this is an invalid request. Print warning and return NV_OK - NV_PRINTF(LEVEL_INFO, "GPU %d invalid request for gpuCount %d\n", gpuGetInstance(pGpu), gpuCount); - return NV_ERR_INVALID_STATE; - } - else - { - OBJGPU *pRemoteGpu = NULL; - KernelCE *pKCeLoop = NULL; - NvU32 peerLinkMask = 0; - NvU32 gpuInstance = 0; - NvU32 phyLinkId, status, targetPceMask, numPces; - - // - // The LCE returned should be the LCE which has the most PCEs mapped - // on the given HSHUB. This HSHUB should be determined by - // tracking where the majority of links are connected. - // - NvU32 linksPerHshub[NV_CE_MAX_HSHUBS] = {0}; - NvU32 maxLinksConnectedHshub = 0; - NvU32 maxConnectedHshubId = NV_CE_MAX_HSHUBS; - NvU32 lceAssignedMask = 0; - KernelCE *maxLcePerHshub[NV_CE_MAX_HSHUBS] = {0}; - - NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS params; - - if (pKernelNvlink != NULL) - { - // Get the remote GPU - while ((pRemoteGpu = gpumgrGetNextGpu(gpuMask, &gpuInstance)) != NULL) - { - if (pRemoteGpu != pGpu) - break; - } - - NV_ASSERT_OR_RETURN(pRemoteGpu != NULL, NV_ERR_INVALID_STATE); - gpuInstance = gpuGetInstance(pRemoteGpu); - - peerLinkMask = knvlinkGetLinkMaskToPeer(pGpu, pKernelNvlink, pRemoteGpu); - } - - portMemSet(¶ms, 0, sizeof(params)); - params.linkMask = peerLinkMask; - - status = knvlinkExecGspRmRpc(pGpu, pKernelNvlink, - NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS, - (void *)¶ms, sizeof(params)); - NV_ASSERT_OK_OR_RETURN(status); - - - FOR_EACH_INDEX_IN_MASK(32, phyLinkId, peerLinkMask) - { - NvU32 hshubId = params.hshubIds[phyLinkId]; - linksPerHshub[hshubId]++; - - if (linksPerHshub[hshubId] > maxLinksConnectedHshub) - { - maxLinksConnectedHshub = linksPerHshub[hshubId]; - maxConnectedHshubId = hshubId; - } - } - FOR_EACH_INDEX_IN_MASK_END; - - // - // Iterate through all Async LCEs to track which HSHUB should - // be using which LCE. This is decided based on the majority. If - // there is a tie, then LCE with the lower index is preferred. - // - KCE_ITER_ALL_BEGIN(pGpu, pKCeLoop, minP2PLce) - NvU32 localMaxPcePerHshub = 0; - KernelCE *localMaxLcePerHshub; - NvU32 localMaxHshub = NV_CE_MAX_HSHUBS; - - // if LCE is stubbed or LCE is already assigned to another peer - if (pKCeLoop->bStubbed) - { - continue; - } - - // LCE is already assigned to this peer - if ((pKCeLoop->nvlinkPeerMask & NVBIT(gpuInstance)) != 0) - { - maxLcePerHshub[maxConnectedHshubId] = pKCeLoop; - break; - } - // LCE is already assigned to another peer - else if (pKCeLoop->nvlinkPeerMask != 0) - { - continue; - } - - NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS params = {0}; - - params.ceEngineType = NV2080_ENGINE_TYPE_COPY(pKCeLoop->publicID); - status = knvlinkExecGspRmRpc(pGpu, pKernelNvlink, - NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK, - (void *)¶ms, sizeof(params)); - NV_ASSERT_OK_OR_RETURN(status); - - // - // An LCE may be utilized across several HSHUBs. Loop through all HSHUBs - // in order to decide which HSHUB holds the majority of this specific LCE. - // To help with this, create a mask of PCEs only on the HSHUB which the peer - // is most connected to by shifting the HSHUB PCE mask - // - - for (i = NV_CE_HSHUBNVL_ID_0; i < NV_CE_MAX_HSHUBS; i++) - { - targetPceMask = params.pceMask & ((NVBIT(NV_CE_PCE_PER_HSHUB) - 1) << ((i - NV_CE_HSHUBNVL_ID_0) * NV_CE_PCE_PER_HSHUB)); - numPces = nvPopCount32(targetPceMask); - if (numPces > localMaxPcePerHshub && !(lceAssignedMask & NVBIT(pKCeLoop->publicID))) - { - localMaxPcePerHshub = numPces; - localMaxLcePerHshub = pKCeLoop; - localMaxHshub = i; - } - } - - if (localMaxHshub < NV_CE_MAX_HSHUBS) - { - maxLcePerHshub[localMaxHshub] = localMaxLcePerHshub; - lceAssignedMask |= NVBIT(localMaxLcePerHshub->publicID); - } - - KCE_ITER_END - - if (maxLcePerHshub[maxConnectedHshubId] != NULL) - { - NV_PRINTF(LEVEL_INFO, - "GPU %d Assigning Peer %d to LCE %d\n", - gpuGetInstance(pGpu), gpuInstance, - maxLcePerHshub[maxConnectedHshubId]->publicID); - - maxLcePerHshub[maxConnectedHshubId]->nvlinkPeerMask = NVBIT(gpuInstance); - *nvlinkP2PCeMask = NVBIT(maxLcePerHshub[maxConnectedHshubId]->publicID); - } - } - - return NV_OK; -} diff --git a/src/nvidia/src/kernel/gpu/ce/kernel_ce.c b/src/nvidia/src/kernel/gpu/ce/kernel_ce.c index a6773fa723..0386851134 100644 --- a/src/nvidia/src/kernel/gpu/ce/kernel_ce.c +++ b/src/nvidia/src/kernel/gpu/ce/kernel_ce.c @@ -62,7 +62,10 @@ NV_STATUS kceConstructEngine_IMPL(OBJGPU *pGpu, KernelCE *pKCe, ENGDESCRIPTOR en } // OBJCE::isPresent would compute this first - pGpu->numCEs++; + if (IS_GSP_CLIENT(pGpu)) + { + pGpu->numCEs++; + } return NV_OK; } @@ -107,7 +110,7 @@ static void printCaps(OBJGPU *pGpu, KernelCE *pKCe, RM_ENGINE_TYPE rmEngineType, PRINT_CAP(_CE_CC_SECURE); } -void kceGetNvlinkCaps(OBJGPU *pGpu, KernelCE *pKCe, NvU8 *pKCeCaps) +void kceGetNvlinkCaps_IMPL(OBJGPU *pGpu, KernelCE *pKCe, NvU8 *pKCeCaps) { if (kceIsCeSysmemRead_HAL(pGpu, pKCe)) RMCTRL_SET_CAP(pKCeCaps, NV2080_CTRL_CE_CAPS, _CE_SYSMEM_READ); @@ -238,7 +241,7 @@ NV_STATUS kceUpdateClassDB_KERNEL(OBJGPU *pGpu, KernelCE *pKCe) // If this CE has no PCEs assigned, remove it from classDB if (stubbed) { - NV_PRINTF(LEVEL_INFO, "Stubbing CE %d\n", kceInst); + NV_PRINTF(LEVEL_INFO, "Stubbing KCE %d\n", kceInst); pKCe->bStubbed = NV_TRUE; status = gpuDeleteClassFromClassDBByEngTag(pGpu, ENG_CE(kceInst)); @@ -246,7 +249,7 @@ NV_STATUS kceUpdateClassDB_KERNEL(OBJGPU *pGpu, KernelCE *pKCe) else { // If a new CE needs to be added because of the new mappings - NV_PRINTF(LEVEL_INFO, "Unstubbing CE %d\n", kceInst); + NV_PRINTF(LEVEL_INFO, "Unstubbing KCE %d\n", kceInst); pKCe->bStubbed = NV_FALSE; status = gpuAddClassToClassDBByEngTag(pGpu, ENG_CE(kceInst)); @@ -441,6 +444,7 @@ NV_STATUS kceGetAvailableHubPceMask_IMPL ( OBJGPU *pGpu, + KernelCE *pKCe, NVLINK_TOPOLOGY_PARAMS *pTopoParams ) { diff --git a/src/nvidia/src/kernel/gpu/ce/kernel_ce_shared.c b/src/nvidia/src/kernel/gpu/ce/kernel_ce_shared.c index 41a94cf8e7..d848183686 100644 --- a/src/nvidia/src/kernel/gpu/ce/kernel_ce_shared.c +++ b/src/nvidia/src/kernel/gpu/ce/kernel_ce_shared.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -181,7 +181,7 @@ subdeviceCtrlCmdCeGetAllCaps_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); - ct_assert(ENG_CE__SIZE_1 <= sizeof(pCeCapsParams->capsTbl) / sizeof(pCeCapsParams->capsTbl[0])); + ct_assert(NV2080_CTRL_MAX_CES <= sizeof(pCeCapsParams->capsTbl) / sizeof(pCeCapsParams->capsTbl[0])); if (!RMCFG_FEATURE_PLATFORM_GSP) { @@ -216,7 +216,7 @@ subdeviceCtrlCmdCeGetAllCaps_IMPL if (pKCe->bStubbed) continue; - pCeCapsParams->present |= BIT(kceInst); + pCeCapsParams->present |= BIT64(kceInst); NvU8 *pKCeCaps = pCeCapsParams->capsTbl[kceInst]; diff --git a/src/nvidia/src/kernel/gpu/conf_compute/conf_compute.c b/src/nvidia/src/kernel/gpu/conf_compute/conf_compute.c index 374536ceb6..7c7c34e141 100644 --- a/src/nvidia/src/kernel/gpu/conf_compute/conf_compute.c +++ b/src/nvidia/src/kernel/gpu/conf_compute/conf_compute.c @@ -51,9 +51,6 @@ confComputeConstructEngine_IMPL(OBJGPU *pGpu, ConfidentialCompute *pConfCompute, ENGDESCRIPTOR engDesc) { - OBJSYS *pSys = SYS_GET_INSTANCE(); - NvU32 data = 0; - NvBool bForceEnableCC = 0; pConfCompute->pSpdm = NULL; portMemSet(&pConfCompute->ccStaticInfo, 0, sizeof(pConfCompute->ccStaticInfo)); pConfCompute->gspProxyRegkeys = 0; @@ -77,20 +74,6 @@ confComputeConstructEngine_IMPL(OBJGPU *pGpu, if (pConfCompute->getProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_ENABLED)) { - bForceEnableCC = (osReadRegistryDword(pGpu, NV_REG_STR_RM_CONFIDENTIAL_COMPUTE, &data) == NV_OK) && - FLD_TEST_DRF(_REG_STR, _RM_CONFIDENTIAL_COMPUTE, _ENABLED, _YES, data); - - if (!RMCFG_FEATURE_PLATFORM_GSP && !RMCFG_FEATURE_PLATFORM_MODS && !bForceEnableCC) - { - if (!(sysGetStaticConfig(pSys)->bOsCCEnabled)) - { - NV_PRINTF(LEVEL_ERROR, "CPU does not support confidential compute.\n"); - NV_ASSERT(0); - pConfCompute->setProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_ENABLED, NV_FALSE); - return NV_ERR_INVALID_OPERATION; - } - } - NV_CHECK_OR_RETURN(LEVEL_ERROR, confComputeIsGpuCcCapable_HAL(pGpu, pConfCompute), NV_ERR_INVALID_OPERATION); if (pGpu->getProperty(pGpu, PDB_PROP_GPU_APM_FEATURE_CAPABLE)) @@ -105,11 +88,10 @@ confComputeConstructEngine_IMPL(OBJGPU *pGpu, else if (pGpu->getProperty(pGpu, PDB_PROP_GPU_CC_FEATURE_CAPABLE)) { pConfCompute->setProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_CC_FEATURE_ENABLED, NV_TRUE); - pGpu->setProperty(pGpu, PDB_PROP_GPU_FASTPATH_SEQ_ENABLED, NV_TRUE); } else { - NV_PRINTF(LEVEL_ERROR, "GPU does not support confidential compute.\n"); + NV_PRINTF(LEVEL_ERROR, "GPU does not support confidential compute"); NV_ASSERT(0); return NV_ERR_INVALID_OPERATION; } @@ -439,8 +421,7 @@ confComputeStateInitLocked_IMPL ConfidentialCompute *pConfCompute ) { - RM_API *pRmApi = IS_GSP_CLIENT(pGpu) ? GPU_GET_PHYSICAL_RMAPI(pGpu) : - rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, pGpu->hInternalClient, diff --git a/src/nvidia/src/kernel/gpu/conf_compute/conf_compute_api.c b/src/nvidia/src/kernel/gpu/conf_compute/conf_compute_api.c index f918eaa7ab..28396ce6d0 100644 --- a/src/nvidia/src/kernel/gpu/conf_compute/conf_compute_api.c +++ b/src/nvidia/src/kernel/gpu/conf_compute/conf_compute_api.c @@ -235,8 +235,7 @@ confComputeApiCtrlCmdGetGpuCertificate_IMPL pGpu = GPU_RES_GET_GPU(pSubdevice); pConfCompute = GPU_GET_CONF_COMPUTE(pGpu); - if (pConfCompute != NULL && pConfCompute->pSpdm != NULL && - pConfCompute->getProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_SPDM_ENABLED)) + if (pConfCompute != NULL) { // Set max size of certificate buffers before calling SPDM. pParams->certChainSize = NV_CONF_COMPUTE_CERT_CHAIN_MAX_SIZE; @@ -272,8 +271,7 @@ confComputeApiCtrlCmdGetGpuAttestationReport_IMPL pGpu = GPU_RES_GET_GPU(pSubdevice); pConfCompute = GPU_GET_CONF_COMPUTE(pGpu); - if (pConfCompute != NULL && pConfCompute->pSpdm != NULL && - pConfCompute->getProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_SPDM_ENABLED)) + if (pConfCompute != NULL) { // Set max size of report buffers before calling SPDM. pParams->attestationReportSize = NV_CONF_COMPUTE_GPU_ATTESTATION_REPORT_MAX_SIZE; diff --git a/src/nvidia/src/kernel/gpu/deferred_api.c b/src/nvidia/src/kernel/gpu/deferred_api.c index 880fa7ddd1..06351a008c 100644 --- a/src/nvidia/src/kernel/gpu/deferred_api.c +++ b/src/nvidia/src/kernel/gpu/deferred_api.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -58,7 +58,6 @@ _Class5080GetDeferredApiInfo(DeferredApiObject *pDeferredApiObject, static NV_STATUS _Class5080AddDeferredApi(DeferredApiObject *pDeferredApiObject, - NvHandle hClient, NvHandle hDeferredApi, NV5080_CTRL_DEFERRED_API_PARAMS *pDeferredApi, NvU32 size, @@ -66,7 +65,6 @@ _Class5080AddDeferredApi(DeferredApiObject *pDeferredApiObject, static NV_STATUS _Class5080AddDeferredApiV2(DeferredApiObject *pDeferredApiObject, - NvHandle hClient, NvHandle hDeferredApi, NV5080_CTRL_DEFERRED_API_V2_PARAMS *pDeferredApi, NvU32 size); @@ -76,7 +74,6 @@ static NV_STATUS _Class5080AddDeferredApi ( DeferredApiObject *pDeferredApiObject, - NvHandle hClient, NvHandle hDeferredApi, NV5080_CTRL_DEFERRED_API_PARAMS *pDeferredApi, NvU32 size, @@ -86,12 +83,10 @@ _Class5080AddDeferredApi NV_STATUS rmStatus = NV_OK; DEFERRED_API_INFO *pCliDeferredApi; CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + NvHandle hClient = RES_GET_CLIENT_HANDLE(pDeferredApiObject); NV_ASSERT_OR_RETURN(pCallContext != NULL, NV_ERR_INVALID_STATE); - if (NV_OK != serverGetClientUnderLock(&g_resServ, hClient, NULL)) - return NV_ERR_INVALID_CLIENT; - // validate handle if (!serverutilValidateNewResourceHandle(hClient, hDeferredApi)) { @@ -103,7 +98,6 @@ _Class5080AddDeferredApi if (NULL != pCliDeferredApi) { // initialize the entry - pCliDeferredApi->Client = hClient; pCliDeferredApi->Handle = hDeferredApi; pCliDeferredApi->pDeferredApiInfo = (NvU8 *)pCliDeferredApi + sizeof(DEFERRED_API_INFO); pCliDeferredApi->Node.keyStart = pCliDeferredApi->Handle; @@ -132,7 +126,6 @@ static NV_STATUS _Class5080AddDeferredApiV2 ( DeferredApiObject *pDeferredApiObject, - NvHandle hClient, NvHandle hDeferredApi, NV5080_CTRL_DEFERRED_API_V2_PARAMS *pDeferredApi, NvU32 size @@ -141,12 +134,10 @@ _Class5080AddDeferredApiV2 NV_STATUS rmStatus = NV_OK; DEFERRED_API_INFO *pCliDeferredApi; CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + NvHandle hClient = RES_GET_CLIENT_HANDLE(pDeferredApiObject); NV_ASSERT_OR_RETURN(pCallContext != NULL, NV_ERR_INVALID_STATE); - if (NV_OK != serverGetClientUnderLock(&g_resServ, hClient, NULL)) - return NV_ERR_INVALID_CLIENT; - // validate handle if (!serverutilValidateNewResourceHandle(hClient, hDeferredApi)) { @@ -166,7 +157,6 @@ _Class5080AddDeferredApiV2 if (NULL != pCliDeferredApi) { // initialize the entry - pCliDeferredApi->Client = hClient; pCliDeferredApi->Handle = hDeferredApi; pCliDeferredApi->pDeferredApiInfo = (NvU8 *)pCliDeferredApi + sizeof(DEFERRED_API_INFO); pCliDeferredApi->Node.keyStart = pCliDeferredApi->Handle; @@ -389,7 +379,6 @@ defapiCtrlCmdDeferredApi_IMPL } return _Class5080AddDeferredApi(pDeferredApiObj, - RES_GET_CLIENT_HANDLE(pDeferredApiObj), pDeferredApi->hApiHandle, pDeferredApi, sizeof(NV5080_CTRL_DEFERRED_API_PARAMS), @@ -426,7 +415,6 @@ defapiCtrlCmdDeferredApiV2_IMPL } return _Class5080AddDeferredApiV2(pDeferredApiObj, - RES_GET_CLIENT_HANDLE(pDeferredApiObj), pDeferredApi->hApiHandle, pDeferredApi, sizeof(NV5080_CTRL_DEFERRED_API_V2_PARAMS)); @@ -588,7 +576,8 @@ _class5080DeferredApiV2 RmCtrlExecuteCookie rmCtrlExecuteCookie = {0}; RS_LOCK_INFO lockInfo = {0}; Subdevice *pSubdevice; - RsClient *pRsClient; + RsClient *pRsClient = RES_GET_CLIENT(pDeferredApiObject); + Device *pDevice = GPU_RES_GET_DEVICE(pDeferredApiObject); const struct NVOC_EXPORTED_METHOD_DEF *pEntry; LOCK_ACCESS_TYPE access; NvU32 releaseFlags = 0; @@ -596,7 +585,7 @@ _class5080DeferredApiV2 CALL_CONTEXT *pOldContext = NULL; portMemSet(&rmCtrlParams, 0, sizeof(RmCtrlParams)); - rmCtrlParams.hClient = pCliDeferredApi->Client; + rmCtrlParams.hClient = pRsClient->hClient; rmCtrlParams.pGpu = pGpu; rmCtrlParams.cmd = pDeferredApi->cmd; rmCtrlParams.flags = 0; @@ -622,13 +611,8 @@ _class5080DeferredApiV2 rmCtrlParams.flags |= NVOS54_FLAGS_IRQL_RAISED; } - rmStatus = serverGetClientUnderLock(&g_resServ, pCliDeferredApi->Client, &pRsClient); - if (rmStatus != NV_OK) - { - goto cleanup; - } - - rmStatus = subdeviceGetByGpu(pRsClient, pGpu, &pSubdevice); + rmStatus = subdeviceGetByDeviceAndGpu(pRsClient, pDevice, pGpu, + &pSubdevice); if (rmStatus != NV_OK) { goto cleanup; diff --git a/src/nvidia/src/kernel/gpu/device.c b/src/nvidia/src/kernel/gpu/device.c index 62d56d5863..4a8ebe1e73 100644 --- a/src/nvidia/src/kernel/gpu/device.c +++ b/src/nvidia/src/kernel/gpu/device.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -35,6 +35,7 @@ #include "resserv/rs_client.h" #include "resserv/rs_resource.h" #include "gpu/device/device.h" +#include "gpu/subdevice/subdevice.h" #include "class/cl0080.h" #include "core/locks.h" @@ -49,9 +50,15 @@ #include "Nvcm.h" #include "diagnostics/gpu_acct.h" #include "gpu/perf/kern_cuda_limit.h" +#include "kernel/gpu/mig_mgr/kernel_mig_manager.h" static NV_STATUS _deviceTeardown(Device *pDevice, CALL_CONTEXT *pCallContext); static NV_STATUS _deviceTeardownRef(Device *pDevice, CALL_CONTEXT *pCallContext); +static NV_STATUS _deviceInit(Device *pDevice, CALL_CONTEXT *pCallContext, + NvHandle hClient, NvHandle hDevice, NvU32 deviceInst, + NvHandle hClientShare, NvHandle hTargetClient, NvHandle hTargetDevice, + NvU64 vaSize, NvU64 vaStartInternal, NvU64 vaLimitInternal, + NvU32 allocFlags, NvU32 vaMode, NvBool *pbIsFirstDevice); NV_STATUS deviceConstruct_IMPL @@ -75,6 +82,7 @@ deviceConstruct_IMPL NvU64 vaStartInternal = 0; NvU64 vaLimitInternal = 0; NvU32 physicalAllocFlags; + NvBool bIsFirstDevice; if (pNv0080AllocParams == NULL) { @@ -120,9 +128,9 @@ deviceConstruct_IMPL } // add new device to client and set the device context - rmStatus = deviceInit(pDevice, pCallContext, pParams->hClient, pParams->hResource, deviceInst, - hClientShare, hTargetClient, hTargetDevice, vaSize, vaStartInternal, vaLimitInternal, - flags, vaMode); + rmStatus = _deviceInit(pDevice, pCallContext, pParams->hClient, pParams->hResource, deviceInst, + hClientShare, hTargetClient, hTargetDevice, vaSize, vaStartInternal, vaLimitInternal, + flags, vaMode, &bIsFirstDevice); if (rmStatus != NV_OK) return rmStatus; @@ -174,7 +182,8 @@ deviceConstruct_IMPL | NV_DEVICE_ALLOCATION_FLAGS_HOST_VGPU_DEVICE); NV_RM_RPC_ALLOC_SHARE_DEVICE(pGpu, pParams->hParent, pParams->hResource, pDevice->hClientShare, - hTargetClient, hTargetDevice, deviceClass, physicalAllocFlags, vaSize, vaMode, rmStatus); + hTargetClient, hTargetDevice, deviceClass, + physicalAllocFlags, vaSize, vaMode, bIsFirstDevice, rmStatus); if (rmStatus != NV_OK) { return rmStatus; @@ -227,6 +236,10 @@ deviceDestruct_IMPL { RsResourceRef *pResourceRef = pCallContext->pResourceRef; NvHandle hDevice = pResourceRef->hResource; + NvBool bClientInUse = NV_FALSE; + RsClient *pRsClient = pCallContext->pClient; + NvBool bNonOffloadVgpu = (IS_VIRTUAL(pGpu) && !IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)); + RS_ITERATOR it; if (rmStatus == NV_OK) { @@ -239,7 +252,41 @@ deviceDestruct_IMPL return; } - NV_RM_RPC_FREE(pGpu, hClient, NV01_NULL_OBJECT, hClient, rmStatus); + // check if there are any more devices in use. + it = clientRefIter(pRsClient, NULL, classId(Device), RS_ITERATE_CHILDREN, NV_TRUE); + + while (clientRefIterNext(it.pClient, &it)) + { + Device *pDeviceTest = dynamicCast(it.pResourceRef->pResource, Device); + NvBool bSameGpu = (GPU_RES_GET_GPU(pDeviceTest) == pGpu); + + if ((pDeviceTest != pDevice) && (bNonOffloadVgpu || bSameGpu)) + { + bClientInUse = NV_TRUE; + break; + } + } + + // check if there are any more KernelSMDebuggerSession in use. + it = clientRefIter(pRsClient, NULL, classId(KernelSMDebuggerSession), RS_ITERATE_CHILDREN, NV_TRUE); + + while (clientRefIterNext(it.pClient, &it)) + { + KernelSMDebuggerSession *pKernelSMDebuggerSession = dynamicCast(it.pResourceRef->pResource, KernelSMDebuggerSession); + + if (pKernelSMDebuggerSession != NULL && + (!IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) || GPU_RES_GET_GPU(pKernelSMDebuggerSession) == pGpu)) + { + bClientInUse = NV_TRUE; + break; + } + } + + // If neither any devices nor KernelSMDebuggerSession are in use, free up the client on host. + if (!bClientInUse) + { + NV_RM_RPC_FREE(pGpu, hClient, NV01_NULL_OBJECT, hClient, rmStatus); + } } } } // end of deviceDestruct_IMPL @@ -282,8 +329,8 @@ deviceInternalControlForward_IMPL // add a device with specified handle, instance num, within a specified client // (hClientShare also specified) // -NV_STATUS -deviceInit_IMPL +static NV_STATUS +_deviceInit ( Device *pDevice, CALL_CONTEXT *pCallContext, @@ -297,7 +344,8 @@ deviceInit_IMPL NvU64 vaStartInternal, NvU64 vaLimitInternal, NvU32 allocFlags, - NvU32 vaMode + NvU32 vaMode, + NvBool *pbIsFirstDevice ) { OBJGPU *pGpu; @@ -309,7 +357,15 @@ deviceInit_IMPL if (deviceInst >= NV_MAX_DEVICES) return NV_ERR_INVALID_ARGUMENT; - // Check if device inst already allocated, fail if this call succeeds + // Look up GPU and GPU Group + gpuInst = gpumgrGetPrimaryForDevice(deviceInst); + + if ((pGpu = gpumgrGetGpu(gpuInst)) == NULL) + { + return NV_ERR_INVALID_STATE; + } + + // Check if device inst already allocated, fail if this call succeeds. status = deviceGetByInstance(pCallContext->pClient, deviceInst, &pExistingDevice); if (status == NV_OK) { @@ -317,16 +373,13 @@ deviceInit_IMPL // RS-TODO: Status code should be NV_ERR_STATE_IN_USE, however keeping // existing code from CliAllocElement (for now) // - return NV_ERR_INSUFFICIENT_RESOURCES; + // Allow many Device objects on the same deviceInst in MIG mode. + // + if (!IS_MIG_ENABLED(pGpu) || IS_VIRTUAL(pGpu)) + return NV_ERR_INSUFFICIENT_RESOURCES; } - // Look up GPU and GPU Group - gpuInst = gpumgrGetPrimaryForDevice(deviceInst); - - if ((pGpu = gpumgrGetGpu(gpuInst)) == NULL) - { - return NV_ERR_INVALID_STATE; - } + *pbIsFirstDevice = (status != NV_OK); pDevice->hTargetClient = hTargetClient; pDevice->hTargetDevice = hTargetDevice; @@ -380,7 +433,7 @@ deviceInit_IMPL } return status; -} // end of deviceInit_IMPL() +} // // delete a device with a specified handle within a client diff --git a/src/nvidia/src/kernel/gpu/device_ctrl.c b/src/nvidia/src/kernel/gpu/device_ctrl.c index 28031504b5..fb9a03ca87 100644 --- a/src/nvidia/src/kernel/gpu/device_ctrl.c +++ b/src/nvidia/src/kernel/gpu/device_ctrl.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2004-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/nvidia/src/kernel/gpu/device_share.c b/src/nvidia/src/kernel/gpu/device_share.c index b74dae8e2f..b4722a3ce9 100644 --- a/src/nvidia/src/kernel/gpu/device_share.c +++ b/src/nvidia/src/kernel/gpu/device_share.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -132,7 +132,7 @@ deviceInitClientShare // else if (hClientShare == RES_GET_CLIENT_HANDLE(pDevice)) { - NvU32 flags = VASPACE_FLAGS_DEFAULT_PARAMS; + NvU32 flags = 0; NvU64 vaLimit; flags |= (deviceAllocFlags & NV_DEVICE_ALLOCATION_FLAGS_VASPACE_SHARED_MANAGEMENT) ? @@ -152,7 +152,6 @@ deviceInitClientShare } else { - flags |= VASPACE_FLAGS_DEFAULT_SIZE; // only needed for Tesla vaLimit = 0; } diff --git a/src/nvidia/src/kernel/gpu/disp/arch/v02/kern_disp_0207.c b/src/nvidia/src/kernel/gpu/disp/arch/v02/kern_disp_0207.c index 9ce32c2c21..17627e87d7 100644 --- a/src/nvidia/src/kernel/gpu/disp/arch/v02/kern_disp_0207.c +++ b/src/nvidia/src/kernel/gpu/disp/arch/v02/kern_disp_0207.c @@ -25,6 +25,8 @@ #include "gpu/gpu.h" #include "gpu/disp/kern_disp.h" +#include "gpu/disp/head/kernel_head.h" +#include "disp/v02_04/dev_disp.h" /*! * @brief - Compute the value LSR_MIN_TIME to be set for swap barrier @@ -57,10 +59,10 @@ kdispComputeLsrMinTimeValue_v02_07 NV_STATUS kdispGetRgScanLock_v02_01 ( - POBJGPU pGpu, + OBJGPU *pGpu, KernelDisplay *pKernelDisplay, NvU32 head0, - POBJGPU pPeerGpu, + OBJGPU *pPeerGpu, NvU32 head1, NvBool *pMasterScanLock, NvU32 *pMasterScanLockPin, @@ -109,3 +111,21 @@ kdispGetRgScanLock_v02_01 return rmStatus; } + +/*! + * @brief Get the LOADV counter + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelHead KernelHead object pointer + * + * @return the current LOADV counter + */ +NvU32 +kheadGetLoadVCounter_v02_04 +( + OBJGPU *pGpu, + KernelHead *pKernelHead +) +{ + return GPU_REG_RD32(pGpu, NV_PDISP_PIPE_IN_LOADV_COUNTER(pKernelHead->PublicId)); +} diff --git a/src/nvidia/src/kernel/gpu/disp/arch/v03/kern_disp_0300.c b/src/nvidia/src/kernel/gpu/disp/arch/v03/kern_disp_0300.c index 0226183dc8..4505971c5e 100644 --- a/src/nvidia/src/kernel/gpu/disp/arch/v03/kern_disp_0300.c +++ b/src/nvidia/src/kernel/gpu/disp/arch/v03/kern_disp_0300.c @@ -32,6 +32,7 @@ #include "gpu/gpu.h" #include "gpu/disp/kern_disp.h" +#include "gpu/disp/head/kernel_head.h" #include "gpu/external_device/gsync.h" #include "disp/v03_00/dev_disp.h" @@ -380,3 +381,21 @@ kdispSetSwapBarrierLsrMinTime_v03_00 GPU_REG_WR32(pGpu, NV_PDISP_FE_FLIPLOCK, dsiFliplock); } + +/*! + * @brief Get the LOADV counter + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelHead KernelHead object pointer + * + * @return the current LOADV counter + */ +NvU32 +kheadGetLoadVCounter_v03_00 +( + OBJGPU *pGpu, + KernelHead *pKernelHead +) +{ + return GPU_REG_RD32(pGpu, NV_PDISP_POSTCOMP_HEAD_LOADV_COUNTER(pKernelHead->PublicId)); +} diff --git a/src/nvidia/src/kernel/gpu/disp/disp_common_ctrl_acpi.c b/src/nvidia/src/kernel/gpu/disp/disp_common_ctrl_acpi.c index 70c64f6f45..e52e8a28d8 100644 --- a/src/nvidia/src/kernel/gpu/disp/disp_common_ctrl_acpi.c +++ b/src/nvidia/src/kernel/gpu/disp/disp_common_ctrl_acpi.c @@ -155,7 +155,6 @@ dispcmnCtrlCmdSystemExecuteAcpiMethod_IMPL KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); OBJSYS *pSys = SYS_GET_INSTANCE(); OBJPFM *pPfm = SYS_GET_PFM(pSys); - OBJOS *pOS = GPU_GET_OS(pGpu); NvU32 method = (NvU32)pAcpiMethodParams->method; NvU32 outStatus = 0; NvU16 inDataSize; // NOTE: must be NvU16, see below @@ -267,7 +266,7 @@ dispcmnCtrlCmdSystemExecuteAcpiMethod_IMPL } outDataSize = sizeof(NvU32); - outStatus = pOS->osCallACPI_NVHG_GPUSTA(pGpu, (NvU32*) pInOutData); + outStatus = osCallACPI_NVHG_GPUSTA(pGpu, (NvU32*) pInOutData); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXDS: @@ -290,7 +289,7 @@ dispcmnCtrlCmdSystemExecuteAcpiMethod_IMPL sizeof(NvU32)); outDataSize = sizeof(NvU32); - outStatus = pOS->osCallACPI_NVHG_MXDS(pGpu, acpiId, (NvU32*) pInOutData); + outStatus = osCallACPI_NVHG_MXDS(pGpu, acpiId, (NvU32*) pInOutData); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXDS: @@ -416,7 +415,7 @@ dispcmnCtrlCmdSystemExecuteAcpiMethod_IMPL acpiId = pfmFindAcpiId(pPfm, pGpu, displayMask); outDataSize = sizeof(NvU32); - outStatus = pOS->osCallACPI_NVHG_MXMX(pGpu, acpiId, (NvU32*) pInOutData); + outStatus = osCallACPI_NVHG_MXMX(pGpu, acpiId, (NvU32*) pInOutData); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOS: @@ -441,7 +440,7 @@ dispcmnCtrlCmdSystemExecuteAcpiMethod_IMPL acpiId = pfmFindAcpiId(pPfm, pGpu, displayMask); outDataSize = sizeof(NvU32); - outStatus = pOS->osCallACPI_NVHG_DOS(pGpu, acpiId, (NvU32*) pInOutData); + outStatus = osCallACPI_NVHG_DOS(pGpu, acpiId, (NvU32*) pInOutData); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_ROM: @@ -469,7 +468,7 @@ dispcmnCtrlCmdSystemExecuteAcpiMethod_IMPL portMemCopy(&acpiId, sizeof(NvU32), pInOutData, sizeof(NvU32)); outDataSize = sizeof(NvU32); - outStatus = pOS->osCallACPI_NVHG_DCS(pGpu, acpiId, (NvU32*) pInOutData); + outStatus = osCallACPI_NVHG_DCS(pGpu, acpiId, (NvU32*) pInOutData); break; } case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOD: diff --git a/src/nvidia/src/kernel/gpu/disp/disp_common_kern_ctrl_minimal.c b/src/nvidia/src/kernel/gpu/disp/disp_common_kern_ctrl_minimal.c index 969f525770..e3e2c7671f 100644 --- a/src/nvidia/src/kernel/gpu/disp/disp_common_kern_ctrl_minimal.c +++ b/src/nvidia/src/kernel/gpu/disp/disp_common_kern_ctrl_minimal.c @@ -37,6 +37,7 @@ #include "gpu/disp/disp_objs.h" #include "rmapi/rs_utils.h" #include "rmapi/rmapi.h" +#include "gpu/disp/head/kernel_head.h" NV_STATUS dispcmnCtrlCmdSystemGetHotplugUnplugState_IMPL @@ -217,7 +218,7 @@ NV_STATUS dispcmnCtrlCmdVRRSetRgLineActive_IMPL NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS *pParams ) { - POBJGPU pGpu = DISPAPI_GET_GPU(pDispCommon); + OBJGPU *pGpu = DISPAPI_GET_GPU(pDispCommon); NvHandle hClient = RES_GET_CLIENT_HANDLE(pDispCommon); NvHandle hParent = RES_GET_PARENT_HANDLE(pDispCommon); RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(DISPAPI_GET_GPU(pDispCommon)); @@ -264,3 +265,27 @@ NV_STATUS dispcmnCtrlCmdVRRSetRgLineActive_IMPL return status; } + +NV_STATUS +dispcmnCtrlCmdSystemGetVblankCounter_IMPL +( + DispCommon *pDispCommon, + NV0073_CTRL_SYSTEM_GET_VBLANK_COUNTER_PARAMS *pVBCounterParams +) +{ + OBJGPU *pGpu = DISPAPI_GET_GPU(pDispCommon); + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + KernelHead *pKernelHead; + + pKernelHead = KDISP_GET_HEAD(pKernelDisplay, pVBCounterParams->head); + + if (pKernelHead == NULL) + { + NV_PRINTF(LEVEL_ERROR, "invalid head number!\n"); + return NV_ERR_INVALID_ARGUMENT; + } + + pVBCounterParams->verticalBlankCounter = kheadGetLoadVCounter_HAL(pGpu, pKernelHead); + + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/disp/inst_mem/arch/v03/disp_inst_mem_0300.c b/src/nvidia/src/kernel/gpu/disp/inst_mem/arch/v03/disp_inst_mem_0300.c index 0bc361d1db..9d2042ba39 100644 --- a/src/nvidia/src/kernel/gpu/disp/inst_mem/arch/v03/disp_inst_mem_0300.c +++ b/src/nvidia/src/kernel/gpu/disp/inst_mem/arch/v03/disp_inst_mem_0300.c @@ -207,7 +207,8 @@ instmemCommitContextDma_v03_00 case ADDR_SYSMEM: case ADDR_REGMEM: // SOC Display always need _PHYSICAL_NVM flag to be set as display is not over PCI - if (pGpu->getProperty(pGpu, PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY)) + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY) || + pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_SOC_SDM)) { ctxDMAFlag |= SF_DEF(_DMA, _TARGET_NODE, _PHYSICAL_NVM); } diff --git a/src/nvidia/src/kernel/gpu/disp/inst_mem/disp_inst_mem.c b/src/nvidia/src/kernel/gpu/disp/inst_mem/disp_inst_mem.c index 6cc52a4b29..68d8372ef2 100644 --- a/src/nvidia/src/kernel/gpu/disp/inst_mem/disp_inst_mem.c +++ b/src/nvidia/src/kernel/gpu/disp/inst_mem/disp_inst_mem.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -308,8 +308,9 @@ instmemInitMemDesc MEMDESC_FLAGS_MEMORY_TYPE_DISPLAY_NISO), exit); - NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, - memdescAlloc(pInstMem->pAllocedInstMemDesc), + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_67, + pInstMem->pAllocedInstMemDesc); + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, status, exit); base = memdescGetPhysAddr(pInstMem->pAllocedInstMemDesc, AT_GPU, 0); diff --git a/src/nvidia/src/kernel/gpu/disp/vblank_callback/vblank.c b/src/nvidia/src/kernel/gpu/disp/vblank_callback/vblank.c index a6ad53320f..27878fef93 100644 --- a/src/nvidia/src/kernel/gpu/disp/vblank_callback/vblank.c +++ b/src/nvidia/src/kernel/gpu/disp/vblank_callback/vblank.c @@ -414,7 +414,6 @@ kheadProcessVblankCallbacks_IMPL VBLANKCALLBACK *pNext = NULL; VBLANKCALLBACK **ppPrev = NULL; NvBool done = NV_FALSE; - NvBool removed = NV_FALSE; NvBool bQueueDpc = NV_FALSE; NvU32 newstate; NvU32 Count = 0; @@ -519,18 +518,10 @@ kheadProcessVblankCallbacks_IMPL { pCallback->VBlankCount = Count; - removed = NV_FALSE; - // - // If this is not a persistent callback, unlink it before we call it. - // Otherwise, it may try to add itself again, and wont be able to. + // If this is not a persistent callback, unlink it. + // Otherwise, it may try to add itself again, and wont be able to add. // - if ( !(pCallback->Flags & VBLANK_CALLBACK_FLAG_PERSISTENT) ) - { - pCallback->Next = NULL; - *ppPrev = pNext; - removed = NV_TRUE; - } // Call the function now if (pCallback->Proc) @@ -599,17 +590,13 @@ kheadProcessVblankCallbacks_IMPL } else { - if (!removed) - { - // - // Yes, the proper way to terminate a persistent callback from within a callback is - // to make it non-persistant. This is what the cursor functions do, and so we should - // check again after the callback. - // - pCallback->Next = NULL; - *ppPrev = pNext; - removed = NV_TRUE; - } + // + // Yes, the proper way to terminate a persistent callback from within a callback is + // to make it non-persistant. This is what the cursor functions do, and so we should + // check again after the callback. + // + pCallback->Next = NULL; + *ppPrev = pNext; } } // This condition arises at wrap time which is about every 331 days at 150 Hz diff --git a/src/nvidia/src/kernel/gpu/disp/vblank_callback/vblank_callback.c b/src/nvidia/src/kernel/gpu/disp/vblank_callback/vblank_callback.c index b523afdec9..a2a784fc25 100644 --- a/src/nvidia/src/kernel/gpu/disp/vblank_callback/vblank_callback.c +++ b/src/nvidia/src/kernel/gpu/disp/vblank_callback/vblank_callback.c @@ -59,8 +59,6 @@ vblcbConstruct_IMPL RS_RES_ALLOC_PARAMS_INTERNAL *pParams ) { - OBJSYS *pSys = SYS_GET_INSTANCE(); - OBJOS *pOS = SYS_GET_OS(pSys); OBJGPU *pGpu = GPU_RES_GET_GPU(pVblankCallback); KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); KernelHead *pKernelHead = NULL; @@ -98,7 +96,7 @@ vblcbConstruct_IMPL pVblankCallback->CallBack.Next = NULL; kheadAddVblankCallback(pGpu, pKernelHead, &pVblankCallback->CallBack); - status = pOS->osSetupVBlank(pGpu, pAllocParams->pProc, pAllocParams->pParm1, pAllocParams->pParm2, pAllocParams->LogicalHead, &pVblankCallback->CallBack); + status = osSetupVBlank(pGpu, pAllocParams->pProc, pAllocParams->pParm1, pAllocParams->pParm2, pAllocParams->LogicalHead, &pVblankCallback->CallBack); if (status != NV_OK) { @@ -114,13 +112,11 @@ vblcbDestruct_IMPL VblankCallback *pVblankCallback ) { - OBJSYS *pSys = SYS_GET_INSTANCE(); - OBJOS *pOS = SYS_GET_OS(pSys); OBJGPU *pGpu = GPU_RES_GET_GPU(pVblankCallback); KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); KernelHead *pKernelHead = KDISP_GET_HEAD(pKernelDisplay, pVblankCallback->LogicalHead); - pOS->osSetupVBlank(pGpu, NULL, NULL, NULL, pVblankCallback->LogicalHead, NULL); + osSetupVBlank(pGpu, NULL, NULL, NULL, pVblankCallback->LogicalHead, NULL); kheadDeleteVblankCallback(pGpu, pKernelHead, &pVblankCallback->CallBack); } diff --git a/src/nvidia/src/kernel/gpu/eng_state.c b/src/nvidia/src/kernel/gpu/eng_state.c index f6af2ca50e..5bdfc2337c 100644 --- a/src/nvidia/src/kernel/gpu/eng_state.c +++ b/src/nvidia/src/kernel/gpu/eng_state.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -45,10 +45,14 @@ engstateConstructBase_IMPL pEngstate->engDesc = engDesc; pEngstate->currentState = ENGSTATE_STATE_UNDEFINED; + if (pEngstate->getProperty(pEngstate, PDB_PROP_ENGSTATE_IS_MISSING)) + return NV_ERR_NOT_SUPPORTED; + #if NV_PRINTF_STRINGS_ALLOWED nvDbgSnprintf(pEngstate->name, sizeof(pEngstate->name), "%s:%d", objGetClassName(pEngstate), ENGDESC_FIELD(pEngstate->engDesc, _INST)); #endif + return NV_OK; } @@ -154,6 +158,24 @@ engstateGetName_IMPL #endif } +void +engstateLogStateStatus_IMPL +( + OBJENGSTATE *pEngstate, + ENGSTATE_STATE targetState, + NV_STATUS targetStatus +) +{ + ENGSTATE_STATUS *status = &pEngstate->status[targetState]; + NV_ASSERT_OR_RETURN_VOID(targetState < ENGSTATE_STATE_COUNT); + + status->engStatus = targetStatus; + +#if NV_PRINTF_STRINGS_ALLOWED + portStringCopy(status->name, sizeof(status->name), engstateGetName(pEngstate), portStringLength(engstateGetName(pEngstate)) + 1); +#endif +} + /*! * @brief generic constructor */ diff --git a/src/nvidia/src/kernel/gpu/external_device/arch/kepler/kern_gsync_p2060.c b/src/nvidia/src/kernel/gpu/external_device/arch/kepler/kern_gsync_p2060.c index b25363ac50..f7d46c2144 100644 --- a/src/nvidia/src/kernel/gpu/external_device/arch/kepler/kern_gsync_p2060.c +++ b/src/nvidia/src/kernel/gpu/external_device/arch/kepler/kern_gsync_p2060.c @@ -834,7 +834,6 @@ extdevService_P2060 NvBool rmStatus ) { - OBJOS *pOS = GPU_GET_OS(pGpu); EXTDEV_INTR_DATA intrData; if (!rmStatus) @@ -862,10 +861,10 @@ extdevService_P2060 } // Attempt to queue a work item. - if (NV_OK != pOS->osQueueWorkItemWithFlags(pGpu, - _extdevService, - (void *)workerThreadData, - OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_SUBDEVICE_RW)) + if (NV_OK != osQueueWorkItemWithFlags(pGpu, + _extdevService, + (void *)workerThreadData, + OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_SUBDEVICE_RW)) { portMemFree((void *)workerThreadData); } @@ -3219,7 +3218,8 @@ gsyncSetMosaic_P2060 PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE)pExtDev; NV_STATUS rmStatus = NV_OK; OBJGPU *pTempGpu = NULL; - NvU8 mosaicReg, i; + NvU8 mosaicReg; + NvU32 i; NvU32 mosaicGroup = pParams->mosaicGroupNumber; if (mosaicGroup >= NV_P2060_MAX_MOSAIC_GROUPS) @@ -3355,23 +3355,23 @@ gsyncSetMosaic_P2060 * register informations in a human readable form. */ static void -DbgPrintP2060StatusRegister(NvU32 DebugLevel, NvU32 regStatus) +DbgPrintP2060StatusRegister(NvU32 regStatus) { if (DRF_VAL(_P2060, _STATUS, _SYNC_LOSS, regStatus)) - NV_PRINTF_EX(NV_PRINTF_MODULE, DebugLevel, "SYNC_LOSS "); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "SYNC_LOSS "); if (DRF_VAL(_P2060, _STATUS, _STEREO, regStatus)) - NV_PRINTF_EX(NV_PRINTF_MODULE, DebugLevel, "STEREO_LOCK "); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "STEREO_LOCK "); if (NV_P2060_STATUS_VCXO_LOCK == DRF_VAL(_P2060, _STATUS, _VCXO, regStatus)) - NV_PRINTF_EX(NV_PRINTF_MODULE, DebugLevel, "VCXO_LOCK "); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "VCXO_LOCK "); if (NV_P2060_STATUS_VCXO_NOLOCK_TOO_FAST == DRF_VAL(_P2060, _STATUS, _VCXO, regStatus)) - NV_PRINTF_EX(NV_PRINTF_MODULE, DebugLevel, "VCXO_NOLOCK_TOO_FAST "); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "VCXO_NOLOCK_TOO_FAST "); if (NV_P2060_STATUS_VCXO_NOLOCK_TOO_SLOW == DRF_VAL(_P2060, _STATUS, _VCXO, regStatus)) - NV_PRINTF_EX(NV_PRINTF_MODULE, DebugLevel, "VCXO_NOLOCK_TOO_SLOW "); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "VCXO_NOLOCK_TOO_SLOW "); if (NV_P2060_STATUS_VCXO_NOT_SERVO == DRF_VAL(_P2060, _STATUS, _VCXO, regStatus)) - NV_PRINTF_EX(NV_PRINTF_MODULE, DebugLevel, "VCXO_NOT_SERVO "); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "VCXO_NOT_SERVO "); } #else -#define DbgPrintP2060StatusRegister(DebugLevel, regStatus) +#define DbgPrintP2060StatusRegister(regStatus) #endif static NV_STATUS @@ -3548,9 +3548,9 @@ gsyncUpdateGsyncStatusSnapshot_P2060 NV_PRINTF(LEVEL_INFO, "Update P2060[%d] settled from 0x%x ( ", iface, oldStatus); - DbgPrintP2060StatusRegister(LEVEL_INFO, oldStatus); + DbgPrintP2060StatusRegister(oldStatus); NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, ") to 0x%x ( ", newStatus); - DbgPrintP2060StatusRegister(LEVEL_INFO, newStatus); + DbgPrintP2060StatusRegister(newStatus); NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, ")\n"); diffStatus = (oldStatus ^ newStatus); @@ -3650,7 +3650,7 @@ gsyncUpdateGsyncStatusSnapshot_P2060 { NV_PRINTF(LEVEL_INFO, "Event P2060[%d]: 0x%x (", iface, ifaceEvents[iface]); - gsyncDbgPrintGsyncEvents(LEVEL_INFO, ifaceEvents[iface], iface); + gsyncDbgPrintGsyncEvents(ifaceEvents[iface], iface); NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, ")\n"); // notify clients that something has happened! diff --git a/src/nvidia/src/kernel/gpu/external_device/gsync.c b/src/nvidia/src/kernel/gpu/external_device/gsync.c index 015ddeea52..6bb8471863 100644 --- a/src/nvidia/src/kernel/gpu/external_device/gsync.c +++ b/src/nvidia/src/kernel/gpu/external_device/gsync.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2008-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2008-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -1365,7 +1365,7 @@ gsyncSetLocalSync(OBJGSYNC *pGsync, { OBJGPU *pSourceGpu = NULL; OBJGPU *pTempGpu = NULL; - NvU8 i; + NvU32 i; NV_STATUS status = NV_OK; NV_ASSERT_OR_RETURN(pGsync && pGsync->pExtDev, NV_ERR_INVALID_DEVICE); @@ -2665,24 +2665,24 @@ gsyncConvertNewEventToOldEventNum #ifdef DEBUG void -gsyncDbgPrintGsyncEvents(NvU32 DebugLevel, NvU32 events, NvU32 iface) +gsyncDbgPrintGsyncEvents(NvU32 events, NvU32 iface) { if (events & NVBIT(NV30F1_GSYNC_NOTIFIERS_SYNC_LOSS(iface))) - NV_PRINTF_EX(NV_PRINTF_MODULE, DebugLevel, "SYNC_LOSS "); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "SYNC_LOSS "); if (events & NVBIT(NV30F1_GSYNC_NOTIFIERS_SYNC_GAIN(iface))) - NV_PRINTF_EX(NV_PRINTF_MODULE, DebugLevel, "SYNC_GAIN "); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "SYNC_GAIN "); if (events & NVBIT(NV30F1_GSYNC_NOTIFIERS_STEREO_LOSS(iface))) - NV_PRINTF_EX(NV_PRINTF_MODULE, DebugLevel, "STEREO_LOSS "); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "STEREO_LOSS "); if (events & NVBIT(NV30F1_GSYNC_NOTIFIERS_STEREO_GAIN(iface))) - NV_PRINTF_EX(NV_PRINTF_MODULE, DebugLevel, "STEREO_GAIN "); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "STEREO_GAIN "); if (events & NVBIT(NV30F1_GSYNC_NOTIFIERS_HOUSE_GAIN)) - NV_PRINTF_EX(NV_PRINTF_MODULE, DebugLevel, "HOUSE_GAIN "); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "HOUSE_GAIN "); if (events & NVBIT(NV30F1_GSYNC_NOTIFIERS_HOUSE_LOSS)) - NV_PRINTF_EX(NV_PRINTF_MODULE, DebugLevel, "HOUSE LOSS "); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "HOUSE LOSS "); if (events & NVBIT(NV30F1_GSYNC_NOTIFIERS_RJ45_GAIN)) - NV_PRINTF_EX(NV_PRINTF_MODULE, DebugLevel, "RJ45 GAIN "); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "RJ45 GAIN "); if (events & NVBIT(NV30F1_GSYNC_NOTIFIERS_RJ45_LOSS)) - NV_PRINTF_EX(NV_PRINTF_MODULE, DebugLevel, "RJ45 LOSS "); + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "RJ45 LOSS "); } #endif // DEBUG diff --git a/src/nvidia/src/kernel/gpu/external_device/kern_external_device.c b/src/nvidia/src/kernel/gpu/external_device/kern_external_device.c index 4490443ddd..e5783aede9 100644 --- a/src/nvidia/src/kernel/gpu/external_device/kern_external_device.c +++ b/src/nvidia/src/kernel/gpu/external_device/kern_external_device.c @@ -27,6 +27,7 @@ #include "gpu/external_device/external_device.h" #include "gpu_mgr/gpu_mgr.h" #include "kernel/gpu/i2c/i2c_api.h" +#include "gpu/disp/kern_disp_max.h" static PDACEXTERNALDEVICE extdevGetExtDev diff --git a/src/nvidia/src/kernel/gpu/falcon/kernel_falcon.c b/src/nvidia/src/kernel/gpu/falcon/kernel_falcon.c index c8c0caddbe..f90aa165ea 100644 --- a/src/nvidia/src/kernel/gpu/falcon/kernel_falcon.c +++ b/src/nvidia/src/kernel/gpu/falcon/kernel_falcon.c @@ -30,6 +30,7 @@ #include "gpu/fifo/kernel_channel_group_api.h" #include "gpu/intr/intr.h" #include "gpu/subdevice/subdevice.h" +#include "gpu/device/device.h" #include "gpu/mem_mgr/mem_mgr.h" #include "gpu/mem_mgr/mem_desc.h" #include "mem_mgr/gpu_vaspace.h" @@ -134,9 +135,9 @@ static NV_STATUS _kflcnAllocAndMapCtxBuffer NV_ASSERT_OK_OR_GOTO(status, memdescSetCtxBufPool(pCtxMemDesc, pCtxBufPool), done); - NV_ASSERT_OK_OR_GOTO(status, - memdescAllocList(pCtxMemDesc, memdescU32ToAddrSpaceList(pKernelFalcon->addrSpaceList)), - done); + memdescTagAllocList(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_115, + pCtxMemDesc, memdescU32ToAddrSpaceList(pKernelFalcon->addrSpaceList)); + NV_ASSERT_OK_OR_GOTO(status, status, done); NV_ASSERT_OK_OR_GOTO(status, memmgrMemDescMemSet(GPU_GET_MEMORY_MANAGER(pGpu), pCtxMemDesc, 0, @@ -173,14 +174,15 @@ static NV_STATUS _kflcnPromoteContext { RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); RsClient *pClient = RES_GET_CLIENT(pKernelChannel); + Device *pDevice = GPU_RES_GET_DEVICE(pKernelChannel); Subdevice *pSubdevice; RM_ENGINE_TYPE rmEngineType; ENGINE_CTX_DESCRIPTOR *pEngCtx; NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS rmCtrlParams = {0}; OBJGVASPACE *pGVAS = dynamicCast(pKernelChannel->pVAS, OBJGVASPACE); - NV_ASSERT_OK_OR_RETURN(subdeviceGetByGpu(pClient, pGpu, &pSubdevice)); NV_ASSERT_OR_RETURN(gpumgrGetSubDeviceInstanceFromGpu(pGpu) == 0, NV_ERR_INVALID_STATE); + NV_ASSERT_OK_OR_RETURN(subdeviceGetByInstance(pClient, RES_GET_HANDLE(pDevice), 0, &pSubdevice)); pEngCtx = pKernelChannel->pKernelChannelGroupApi->pKernelChannelGroup->ppEngCtxDesc[0]; NV_ASSERT_OR_RETURN(pEngCtx != NULL, NV_ERR_INVALID_ARGUMENT); @@ -286,6 +288,7 @@ NV_STATUS kflcnFreeContext_IMPL NvU32 classNum ) { + NV_STATUS status = NV_OK; MEMORY_DESCRIPTOR *pCtxMemDesc = NULL; NV_ASSERT_OR_RETURN(pKernelChannel != NULL, NV_ERR_INVALID_CHANNEL); @@ -308,11 +311,12 @@ NV_STATUS kflcnFreeContext_IMPL } kchannelUnmapEngineCtxBuf(pGpu, pKernelChannel, pKernelFalcon->physEngDesc); - kchannelSetEngineContextMemDesc(pGpu, pKernelChannel, pKernelFalcon->physEngDesc, NULL); + NV_ASSERT_OK_OR_CAPTURE_FIRST_ERROR(status, + kchannelSetEngineContextMemDesc(pGpu, pKernelChannel, pKernelFalcon->physEngDesc, NULL)); memdescFree(pCtxMemDesc); memdescDestroy(pCtxMemDesc); - return NV_OK; + return status; } NV_STATUS gkflcnConstruct_IMPL @@ -344,7 +348,7 @@ void gkflcnRegisterIntrService_IMPL(OBJGPU *pGpu, GenericKernelFalcon *pGenericK NV_PRINTF(LEVEL_INFO, "physEngDesc 0x%x\n", pKernelFalcon->physEngDesc); if (!IS_NVDEC(pKernelFalcon->physEngDesc) && - pKernelFalcon->physEngDesc != ENG_OFA && + !IS_OFA(pKernelFalcon->physEngDesc) && !IS_NVJPEG(pKernelFalcon->physEngDesc) && !IS_MSENC(pKernelFalcon->physEngDesc)) return; @@ -381,9 +385,11 @@ NV_STATUS gkflcnServiceNotificationInterrupt_IMPL(OBJGPU *pGpu, GenericKernelFal NvU32 nvdecIdx = idxMc - MC_ENGINE_IDX_NVDECn(0); rmEngineType = RM_ENGINE_TYPE_NVDEC(nvdecIdx); } - else if (idxMc == MC_ENGINE_IDX_OFA0) + else if (MC_ENGINE_IDX_OFA(0) <= idxMc && + idxMc < MC_ENGINE_IDX_OFA(RM_ENGINE_TYPE_OFA_SIZE)) { - rmEngineType = RM_ENGINE_TYPE_OFA; + NvU32 ofaIdx = idxMc - MC_ENGINE_IDX_OFA(0); + rmEngineType = RM_ENGINE_TYPE_OFA(ofaIdx); } else if (MC_ENGINE_IDX_NVJPEGn(0) <= idxMc && idxMc < MC_ENGINE_IDX_NVJPEGn(RM_ENGINE_TYPE_NVJPEG_SIZE)) @@ -391,10 +397,10 @@ NV_STATUS gkflcnServiceNotificationInterrupt_IMPL(OBJGPU *pGpu, GenericKernelFal NvU32 nvjpgIdx = idxMc - MC_ENGINE_IDX_NVJPEGn(0); rmEngineType = RM_ENGINE_TYPE_NVJPEG(nvjpgIdx); } - else if (MC_ENGINE_IDX_MSENCn(0) <= idxMc && - idxMc < MC_ENGINE_IDX_MSENCn(RM_ENGINE_TYPE_NVENC_SIZE)) + else if (MC_ENGINE_IDX_NVENCn(0) <= idxMc && + idxMc < MC_ENGINE_IDX_NVENCn(RM_ENGINE_TYPE_NVENC_SIZE)) { - NvU32 msencIdx = idxMc - MC_ENGINE_IDX_MSENCn(0); + NvU32 msencIdx = idxMc - MC_ENGINE_IDX_NVENCn(0); rmEngineType = RM_ENGINE_TYPE_NVENC(msencIdx); } diff --git a/src/nvidia/src/kernel/gpu/falcon/kernel_falcon_ctrl.c b/src/nvidia/src/kernel/gpu/falcon/kernel_falcon_ctrl.c index 16a7fdd7b8..1322ce8895 100644 --- a/src/nvidia/src/kernel/gpu/falcon/kernel_falcon_ctrl.c +++ b/src/nvidia/src/kernel/gpu/falcon/kernel_falcon_ctrl.c @@ -36,7 +36,7 @@ NV_STATUS subdeviceCtrlCmdFlcnGetCtxBufferInfo_IMPL NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS *pParams ) { - POBJGPU pGpu = GPU_RES_GET_GPU(pSubdevice); + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); PMEMORY_DESCRIPTOR pMemDesc, pRootMemDesc; RsClient *pUserClient; KernelChannel *pKernelChannel = NULL; @@ -164,7 +164,7 @@ subdeviceCtrlCmdFlcnGetCtxBufferSize_IMPL NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS *pParams ) { - POBJGPU pGpu = GPU_RES_GET_GPU(pSubdevice); + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); PMEMORY_DESCRIPTOR pMemDesc; KernelChannel *pKernelChannel = NULL; NV_STATUS status = NV_OK; diff --git a/src/nvidia/src/kernel/gpu/fifo/arch/hopper/kernel_fifo_gh100.c b/src/nvidia/src/kernel/gpu/fifo/arch/hopper/kernel_fifo_gh100.c index 0c9872ad46..b53467d9e6 100644 --- a/src/nvidia/src/kernel/gpu/fifo/arch/hopper/kernel_fifo_gh100.c +++ b/src/nvidia/src/kernel/gpu/fifo/arch/hopper/kernel_fifo_gh100.c @@ -113,6 +113,7 @@ kfifoConstructUsermodeMemdescs_GH100 err); memdescSetPteKind(*ppMemDesc, memmgrGetMessageKind_HAL(pGpu, pMemoryManager)); memdescSetFlag(*ppMemDesc, MEMDESC_FLAGS_MAP_SYSCOH_OVER_BAR1, NV_TRUE); + memdescSetPageSize(*ppMemDesc, AT_GPU, RM_PAGE_SIZE); } NV_ASSERT_OK_OR_GOTO(status, diff --git a/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_channel_gm107.c b/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_channel_gm107.c index 38fdb9941e..1c0983d5b1 100644 --- a/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_channel_gm107.c +++ b/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_channel_gm107.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -255,7 +255,8 @@ NV_STATUS kchannelAllocMem_GM107 } } - status = memdescAllocList(pInstanceBlock->pInstanceBlockDesc, pInstAllocList); + memdescTagAllocList(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_116, + pInstanceBlock->pInstanceBlockDesc, pInstAllocList); if (status == NV_OK) { MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); diff --git a/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_fifo_gm107.c b/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_fifo_gm107.c index 44908b7c84..cf7d39afb2 100644 --- a/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_fifo_gm107.c +++ b/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_fifo_gm107.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -146,7 +146,8 @@ _kfifoAllocDummyPage return status; } - status = memdescAllocList(pKernelFifo->pDummyPageMemDesc, pKernelFifo->pInstAllocList); + memdescTagAllocList(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_80, + pKernelFifo->pDummyPageMemDesc, pKernelFifo->pInstAllocList); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "Could not allocate dummy page\n"); @@ -1244,7 +1245,8 @@ kfifoPreAllocUserD_GM107 } else { - status = memdescAlloc(pUserdInfo->userdPhysDesc[currentGpuInst]); + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_81, + pUserdInfo->userdPhysDesc[currentGpuInst]); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, @@ -1267,7 +1269,7 @@ kfifoPreAllocUserD_GM107 (memdescGetAddressSpace(pUserdInfo->userdPhysDesc[currentGpuInst]) == ADDR_FBMEM)) { - NV_PRINTF(LEVEL_INFO, "Mapping USERD with coherent link.\n"); + NV_PRINTF(LEVEL_INFO, "Mapping USERD with coherent link (USERD in FBMEM).\n"); NV_ASSERT(pGpu->getProperty(pGpu, PDB_PROP_GPU_ATS_SUPPORTED)); NV_ASSERT(pUserdInfo->userdPhysDesc[currentGpuInst]->_flags & MEMDESC_FLAGS_PHYSICALLY_CONTIGUOUS); @@ -1277,6 +1279,22 @@ kfifoPreAllocUserD_GM107 pUserdInfo->userdPhysDesc[currentGpuInst]->PteAdjust; } } + // + // get sysmem mapping for USERD if USERD is in sysmem and reflected BAR access is not allowed + // + else if ((bCoherentCpuMapping && + memdescGetAddressSpace(pUserdInfo->userdPhysDesc[currentGpuInst]) == ADDR_SYSMEM && + !kbusIsReflectedMappingAccessAllowed(pKernelBus)) || + pGpu->getProperty(pGpu, PDB_PROP_GPU_BAR1_BAR2_DISABLED)) + { + NV_PRINTF(LEVEL_INFO, "Mapping USERD with coherent link (USERD in SYSMEM).\n"); + + if (bFifoFirstInit) + { + pUserdInfo->userdBar1MapStartOffset = + memdescGetPhysAddr(pUserdInfo->userdPhysDesc[currentGpuInst], AT_CPU, 0); + } + } else { // vGpu may boot with partitioning enabled but that's not true for host RM @@ -1291,17 +1309,17 @@ kfifoPreAllocUserD_GM107 status = kbusMapFbAperture_HAL(pGpu, pKernelBus, pUserdInfo->userdPhysDesc[currentGpuInst], 0, &pUserdInfo->userdBar1MapStartOffset, &temp, mapFlags | BUS_MAP_FB_FLAGS_PRE_INIT, NULL); - } - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "Could not map USERD to BAR1\n"); - DBG_BREAKPOINT(); - goto fail; - } + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Could not map USERD to BAR1\n"); + DBG_BREAKPOINT(); + goto fail; + } - // Add current GPU to list of GPUs referencing pFifo userD bar1 - pUserdInfo->userdBar1RefMask |= NVBIT(pGpu->gpuInstance); + // Add current GPU to list of GPUs referencing pFifo userD bar1 + pUserdInfo->userdBar1RefMask |= NVBIT(pGpu->gpuInstance); + } } if (bFifoFirstInit) @@ -1315,6 +1333,18 @@ kfifoPreAllocUserD_GM107 pUserdInfo->userdPhysDesc[currentGpuInst]); status = pUserdInfo->userdBar1CpuPtr == NULL ? NV_ERR_GENERIC : NV_OK; } + else if ((bCoherentCpuMapping && + memdescGetAddressSpace(pUserdInfo->userdPhysDesc[currentGpuInst]) == ADDR_SYSMEM && + !kbusIsReflectedMappingAccessAllowed(pKernelBus)) || + pGpu->getProperty(pGpu, PDB_PROP_GPU_BAR1_BAR2_DISABLED)) + { + status = osMapPciMemoryKernelOld(pGpu, + pUserdInfo->userdBar1MapStartOffset, + pUserdInfo->userdBar1MapSize, + NV_PROTECT_READ_WRITE, + (void**)&pUserdInfo->userdBar1CpuPtr, + NV_MEMORY_UNCACHED); + } else { // Cpu map the BAR1 snoop range diff --git a/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_channel_group_gv100.c b/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_channel_group_gv100.c index f370a58c99..07774cc1ef 100644 --- a/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_channel_group_gv100.c +++ b/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_channel_group_gv100.c @@ -112,7 +112,8 @@ kchangrpAllocFaultMethodBuffers_GV100 goto fail; } - status = memdescAlloc(pFaultMthdBuf->pMemDesc); + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_34, + pFaultMthdBuf->pMemDesc); if (status != NV_OK) { DBG_BREAKPOINT(); diff --git a/src/nvidia/src/kernel/gpu/fifo/kernel_channel.c b/src/nvidia/src/kernel/gpu/fifo/kernel_channel.c index c5fa51d152..c7f74008ea 100644 --- a/src/nvidia/src/kernel/gpu/fifo/kernel_channel.c +++ b/src/nvidia/src/kernel/gpu/fifo/kernel_channel.c @@ -28,6 +28,7 @@ #include "kernel/gpu/fifo/kernel_channel.h" #include "kernel/core/locks.h" +#include "gpu/subdevice/subdevice.h" #include "kernel/diagnostics/gpu_acct.h" #include "kernel/gpu/conf_compute/conf_compute.h" #include "kernel/gpu/device/device.h" @@ -484,7 +485,7 @@ kchannelConstruct_IMPL } else if (!RMCFG_FEATURE_PLATFORM_GSP) { - NV_ASSERT_OK(kchannelGetNotifierInfo(pGpu, pRsClient, + NV_ASSERT_OK(kchannelGetNotifierInfo(pGpu, pDevice, pKernelChannel->hErrorContext, &pKernelChannel->pErrContextMemDesc, &pKernelChannel->errorContextType, @@ -498,7 +499,7 @@ kchannelConstruct_IMPL } else if (!RMCFG_FEATURE_PLATFORM_GSP) { - NV_ASSERT_OK(kchannelGetNotifierInfo(pGpu, pRsClient, + NV_ASSERT_OK(kchannelGetNotifierInfo(pGpu, pDevice, pKernelChannel->hEccErrorContext, &pKernelChannel->pEccErrContextMemDesc, &pKernelChannel->eccErrorContextType, @@ -593,11 +594,11 @@ kchannelConstruct_IMPL // If hKernelCtxShare is nonzero, the ChannelGroup is not internal // either, so it should have the same parent as hParent. // - NV_ASSERT_OR_ELSE( + NV_ASSERT_TRUE_OR_GOTO(status, pKernelCtxShareRef->pParentRef != NULL && pKernelCtxShareRef->pParentRef->hResource == hParent, - status = NV_ERR_INVALID_OBJECT_PARENT; - goto cleanup); + NV_ERR_INVALID_OBJECT_PARENT, + cleanup); } else { @@ -630,22 +631,31 @@ kchannelConstruct_IMPL cleanup); } - pKernelChannel->pKernelCtxShareApi = dynamicCast(pKernelCtxShareRef->pResource, KernelCtxShareApi); - NV_ASSERT_OR_ELSE(pKernelChannel->pKernelCtxShareApi != NULL, status = NV_ERR_INVALID_OBJECT; goto cleanup); - NV_ASSERT_OR_ELSE(pKernelChannel->pKernelCtxShareApi->pShareData != NULL, status = NV_ERR_INVALID_OBJECT; goto cleanup); + pKernelChannel->pKernelCtxShareApi = dynamicCast( + pKernelCtxShareRef->pResource, + KernelCtxShareApi); + NV_ASSERT_TRUE_OR_GOTO(status, + pKernelChannel->pKernelCtxShareApi != NULL, + NV_ERR_INVALID_OBJECT, + cleanup); + NV_ASSERT_TRUE_OR_GOTO(status, + pKernelChannel->pKernelCtxShareApi->pShareData != + NULL, + NV_ERR_INVALID_OBJECT, + cleanup); pKernelChannel->pVAS = pKernelChannel->pKernelCtxShareApi->pShareData->pVAS; - NV_ASSERT_OR_ELSE(pKernelChannel->pVAS != NULL, status = NV_ERR_INVALID_OBJECT; goto cleanup); + NV_ASSERT_TRUE_OR_GOTO(status, + pKernelChannel->pVAS != NULL, + NV_ERR_INVALID_OBJECT, + cleanup); if (kfifoIsPerRunlistChramSupportedInHw(pKernelFifo)) { // TSG should always have a valid engine Id. - if (!RM_ENGINE_TYPE_IS_VALID(pKernelChannelGroup->engineType)) - { - NV_ASSERT( - RM_ENGINE_TYPE_IS_VALID(pKernelChannelGroup->engineType)); - status = NV_ERR_INVALID_STATE; - goto cleanup; - } + NV_ASSERT_TRUE_OR_GOTO(status, + RM_ENGINE_TYPE_IS_VALID(pKernelChannelGroup->engineType), + NV_ERR_INVALID_STATE, + cleanup); if (NV2080_ENGINE_TYPE_IS_VALID(pChannelGpfifoParams->engineType)) { @@ -899,10 +909,18 @@ kchannelConstruct_IMPL // We depend on VASpace if it was provided if (pChannelGpfifoParams->hVASpace != NV01_NULL_OBJECT) { - NV_ASSERT_OK_OR_GOTO(status, clientGetResourceRef(pRsClient, pChannelGpfifoParams->hVASpace, &pVASpaceRef), cleanup); - NV_ASSERT_OR_ELSE(pVASpaceRef != NULL, status = NV_ERR_INVALID_OBJECT; goto cleanup); - - NV_ASSERT_OK_OR_GOTO(status, refAddDependant(pVASpaceRef, pResourceRef), cleanup); + NV_ASSERT_OK_OR_GOTO(status, + clientGetResourceRef(pRsClient, + pChannelGpfifoParams->hVASpace, + &pVASpaceRef), + cleanup); + NV_ASSERT_TRUE_OR_GOTO(status, + pVASpaceRef != NULL, + NV_ERR_INVALID_OBJECT, + cleanup); + NV_ASSERT_OK_OR_GOTO(status, + refAddDependant(pVASpaceRef, pResourceRef), + cleanup); } // @@ -1759,15 +1777,15 @@ NV_STATUS kchannelGetNotifierInfo ( OBJGPU *pGpu, - RsClient *pRsClient, + Device *pDevice, NvHandle hErrorContext, MEMORY_DESCRIPTOR **ppMemDesc, ErrorNotifierType *pNotifierType, NvU64 *pOffset ) { - NvHandle hDevice; - Device *pDevice = NULL; + RsClient *pRsClient = RES_GET_CLIENT(pDevice); + NvHandle hDevice = RES_GET_HANDLE(pDevice); ContextDma *pContextDma = NULL; Memory *pMemory = NULL; @@ -1784,11 +1802,6 @@ kchannelGetNotifierInfo return NV_OK; } - NV_ASSERT_OK_OR_RETURN(deviceGetByInstance(pRsClient, - gpuGetDeviceInstance(pGpu), - &pDevice)); - hDevice = RES_GET_HANDLE(pDevice); - if (memGetByHandleAndDevice(pRsClient, hErrorContext, hDevice, &pMemory) == NV_OK) { @@ -2485,7 +2498,10 @@ _kchannelSendChannelAllocRpc FIFO_INSTANCE_BLOCK *pInstanceBlock = pKernelChannel->pFifoHalData[subdevInst]; NvU32 runqueue = DRF_VAL(OS04, _FLAGS, _GROUP_CHANNEL_RUNQUEUE, pChannelGpfifoParams->flags); - NV_ASSERT_OR_ELSE(pInstanceBlock != NULL, status = NV_ERR_INVALID_STATE; goto cleanup); + NV_ASSERT_TRUE_OR_GOTO(status, + pInstanceBlock != NULL, + NV_ERR_INVALID_STATE, + cleanup); portMemCopy(&pRpcParams->errorNotifierMem, sizeof pRpcParams->errorNotifierMem, @@ -2582,16 +2598,23 @@ _kchannelSendChannelAllocRpc } } - NV_RM_RPC_ALLOC_CHANNEL(pGpu, RES_GET_CLIENT_HANDLE(pKernelChannel), RES_GET_PARENT_HANDLE(pKernelChannel), - RES_GET_HANDLE(pKernelChannel), RES_GET_EXT_CLASS_ID(pKernelChannel), - pRpcParams, &pKernelChannel->ChID, status); - NV_ASSERT_OR_ELSE(status == NV_OK, goto cleanup); + NV_RM_RPC_ALLOC_CHANNEL(pGpu, + RES_GET_CLIENT_HANDLE(pKernelChannel), + RES_GET_PARENT_HANDLE(pKernelChannel), + RES_GET_HANDLE(pKernelChannel), + RES_GET_EXT_CLASS_ID(pKernelChannel), + pRpcParams, + &pKernelChannel->ChID, + status); + NV_ASSERT_OK_OR_GOTO(status, status, cleanup); NV_PRINTF(LEVEL_INFO, - "Alloc Channel chid %d, hClient:0x%x, " - "hParent:0x%x, hObject:0x%x, hClass:0x%x\n", pKernelChannel->ChID, - RES_GET_CLIENT_HANDLE(pKernelChannel), RES_GET_PARENT_HANDLE(pKernelChannel), - RES_GET_HANDLE(pKernelChannel), RES_GET_EXT_CLASS_ID(pKernelChannel)); + "Alloc Channel chid %d, hClient:0x%x, hParent:0x%x, hObject:0x%x, hClass:0x%x\n", + pKernelChannel->ChID, + RES_GET_CLIENT_HANDLE(pKernelChannel), + RES_GET_PARENT_HANDLE(pKernelChannel), + RES_GET_HANDLE(pKernelChannel), + RES_GET_EXT_CLASS_ID(pKernelChannel)); cleanup: portMemFree(pRpcParams); @@ -2961,7 +2984,7 @@ kchannelCtrlCmdSetErrorNotifier_IMPL rmStatus = krcErrorSetNotifier(pGpu, GPU_GET_KERNEL_RC(pGpu), pKernelChannel, - ROBUST_CHANNEL_GR_ERROR_SW_NOTIFY, + ROBUST_CHANNEL_GR_EXCEPTION, kchannelGetEngineType(pKernelChannel), scope); return rmStatus; @@ -3092,17 +3115,13 @@ kchannelCtrlCmdGpfifoGetWorkSubmitToken_IMPL NvBool bIsModsVgpu = NV_FALSE; - NvBool bIsVgpuRpcNeeded = bIsModsVgpu || (IS_VIRTUAL(pGpu) && + NvBool bIsVgpuRpcNeeded = (bIsModsVgpu || (IS_VIRTUAL(pGpu) && !(IS_VIRTUAL_WITH_SRIOV(pGpu) && !bIsMIGEnabled && - kfifoIsPerRunlistChramEnabled(pKernelFifo))); + kfifoIsPerRunlistChramEnabled(pKernelFifo)))) && + (!pKernelFifo->bGuestGenenratesWorkSubmitToken); // // vGPU: - // - // Since host is taking care of channel allocations for the guest - // we must call into the host to get the worksubmit token. This - // should go away once the guest starts managing its own channels. - // - // RPC not needed for SR-IOV vGpu + // If required call into the host to get the worksubmit token. // if (bIsVgpuRpcNeeded) { @@ -3129,11 +3148,7 @@ kchannelCtrlCmdGpfifoGetWorkSubmitToken_IMPL } } - // - // For GSP client or MODS vGPU guest, pTokenParams->workSubmitToken already filled by RPC. - // For baremetal RM, generate it here. - // - if (!bIsModsVgpu) + if (!bIsModsVgpu || pKernelFifo->bGuestGenenratesWorkSubmitToken) { NV_ASSERT_OR_RETURN(pKernelChannel->pKernelChannelGroupApi != NULL, NV_ERR_INVALID_STATE); NV_ASSERT_OR_RETURN(pKernelChannel->pKernelChannelGroupApi->pKernelChannelGroup != NULL, NV_ERR_INVALID_STATE); @@ -3280,7 +3295,7 @@ kchannelGetChildIterator ( KernelChannel *pKernelChannel, NvU32 classID, - NvU32 engineID, + RM_ENGINE_TYPE engineID, KernelChannelChildIterator *pIter ) { diff --git a/src/nvidia/src/kernel/gpu/fifo/kernel_fifo.c b/src/nvidia/src/kernel/gpu/fifo/kernel_fifo.c index 19dbe52d4e..bbdb7089c7 100644 --- a/src/nvidia/src/kernel/gpu/fifo/kernel_fifo.c +++ b/src/nvidia/src/kernel/gpu/fifo/kernel_fifo.c @@ -21,9 +21,6 @@ * DEALINGS IN THE SOFTWARE. */ -// FIXME XXX -#define NVOC_KERNEL_GRAPHICS_MANAGER_H_PRIVATE_ACCESS_ALLOWED - #include "kernel/gpu/fifo/kernel_fifo.h" #include "kernel/gpu/fifo/kernel_channel.h" #include "kernel/gpu/fifo/kernel_channel_group.h" @@ -1019,7 +1016,7 @@ kfifoChidMgrReserveSystemChids_IMPL NvU32 gfid, NvU32 *pChidOffset, NvU32 *pChannelCount, - NvHandle hMigClient, + Device *pMigDevice, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList ) @@ -1084,7 +1081,7 @@ kfifoChidMgrReserveSystemChids_IMPL status = kfifoSetChidOffset(pGpu, pKernelFifo, pChidMgr, (NvU32)offset, numChannels, gfid, pChidOffset, pChannelCount, - hMigClient, engineFifoListNumEntries, pEngineFifoList); + pMigDevice, engineFifoListNumEntries, pEngineFifoList); if (status != NV_OK) { @@ -1123,7 +1120,7 @@ kfifoChidMgrReserveSystemChids_IMPL cleanup: portMemFree(pChidMgr->ppVirtualChIDHeap[gfid]); NV_ASSERT(kfifoSetChidOffset(pGpu, pKernelFifo, pChidMgr, 0, 0, - gfid, pChidOffset, pChannelCount, hMigClient, + gfid, pChidOffset, pChannelCount, pMigDevice, engineFifoListNumEntries, pEngineFifoList) == NV_OK); NV_ASSERT(pChidMgr->pGlobalChIDHeap->eheapFree(pChidMgr->pGlobalChIDHeap, offset) == NV_OK); portMemFree(pIsolationID); @@ -1140,7 +1137,7 @@ kfifoChidMgrFreeSystemChids_IMPL NvU32 gfid, NvU32 *pChidOffset, NvU32 *pChannelCount, - NvHandle hMigClient, + Device *pMigDevice, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList ) @@ -1184,7 +1181,7 @@ kfifoChidMgrFreeSystemChids_IMPL } tmpStatus = kfifoSetChidOffset(pGpu, pKernelFifo, pChidMgr, 0, 0, - gfid, pChidOffset, pChannelCount, hMigClient, + gfid, pChidOffset, pChannelCount, pMigDevice, engineFifoListNumEntries, pEngineFifoList); if (tmpStatus != NV_OK) { @@ -1873,7 +1870,7 @@ kfifoGetHostDeviceInfoTable_KERNEL OBJGPU *pGpu, KernelFifo *pKernelFifo, ENGINE_INFO *pEngineInfo, - NvHandle hMigClient + Device *pMigDevice ) { NV_STATUS status = NV_OK; @@ -1907,18 +1904,15 @@ kfifoGetHostDeviceInfoTable_KERNEL } else { - RsClient *pClient; + RsClient *pClient = RES_GET_CLIENT(pMigDevice); Subdevice *pSubdevice; - hClient = hMigClient; - NV_ASSERT_OK_OR_RETURN( - serverGetClientUnderLock(&g_resServ, hClient, &pClient)); - - NV_ASSERT_OK_OR_RETURN(subdeviceGetByGpu(pClient, pGpu, &pSubdevice)); + subdeviceGetByInstance(pClient, RES_GET_HANDLE(pMigDevice), 0, &pSubdevice)); GPU_RES_SET_THREAD_BC_STATE(pSubdevice); + hClient = pClient->hClient; hObject = RES_GET_HANDLE(pSubdevice); } } @@ -2622,7 +2616,8 @@ kfifoRunlistAllocBuffers_IMPL } } - status = memdescAlloc(ppMemDesc[counter]); + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_101, + ppMemDesc[counter]); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "Runlist buffer mem alloc failed 0x%08x\n", @@ -2657,10 +2652,10 @@ kfifoGetMaxSubcontextFromGr_KERNEL KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); NV_ASSERT_OR_RETURN(pKernelGraphicsManager != NULL, 0); - NV_ASSERT_OR_RETURN(pKernelGraphicsManager->legacyKgraphicsStaticInfo.bInitialized, 0); - NV_ASSERT_OR_RETURN(pKernelGraphicsManager->legacyKgraphicsStaticInfo.pGrInfo != NULL, 0); + NV_ASSERT_OR_RETURN(kgrmgrGetLegacyKGraphicsStaticInfo(pGpu, pKernelGraphicsManager)->bInitialized, 0); + NV_ASSERT_OR_RETURN(kgrmgrGetLegacyKGraphicsStaticInfo(pGpu, pKernelGraphicsManager)->pGrInfo != NULL, 0); - return pKernelGraphicsManager->legacyKgraphicsStaticInfo.pGrInfo->infoList[NV0080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT].data; + return kgrmgrGetLegacyKGraphicsStaticInfo(pGpu, pKernelGraphicsManager)->pGrInfo->infoList[NV0080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT].data; } NvU32 @@ -3110,7 +3105,7 @@ kfifoSetChidOffset_IMPL NvU32 gfid, NvU32 *pChidOffset, NvU32 *pChannelCount, - NvU32 hMigClient, + Device *pMigDevice, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList ) @@ -3137,7 +3132,7 @@ kfifoSetChidOffset_IMPL } NV_ASSERT_OK_OR_GOTO(status, kfifoProgramChIdTable_HAL(pGpu, pKernelFifo, pChidMgr, offset, numChannels, gfid, - hMigClient, engineFifoListNumEntries, pEngineFifoList), cleanup); + pMigDevice, engineFifoListNumEntries, pEngineFifoList), cleanup); cleanup: @@ -3374,9 +3369,9 @@ kfifoGetGuestEngineLookupTable_IMPL {NV2080_ENGINE_TYPE_COPY7, MC_ENGINE_IDX_CE7}, {NV2080_ENGINE_TYPE_COPY8, MC_ENGINE_IDX_CE8}, {NV2080_ENGINE_TYPE_COPY9, MC_ENGINE_IDX_CE9}, - {NV2080_ENGINE_TYPE_NVENC0, MC_ENGINE_IDX_MSENC}, - {NV2080_ENGINE_TYPE_NVENC1, MC_ENGINE_IDX_MSENC1}, - {NV2080_ENGINE_TYPE_NVENC2, MC_ENGINE_IDX_MSENC2}, + {NV2080_ENGINE_TYPE_NVENC0, MC_ENGINE_IDX_NVENC}, + {NV2080_ENGINE_TYPE_NVENC1, MC_ENGINE_IDX_NVENC1}, + {NV2080_ENGINE_TYPE_NVENC2, MC_ENGINE_IDX_NVENC2}, {NV2080_ENGINE_TYPE_NVDEC0, MC_ENGINE_IDX_NVDEC0}, {NV2080_ENGINE_TYPE_NVDEC1, MC_ENGINE_IDX_NVDEC1}, {NV2080_ENGINE_TYPE_NVDEC2, MC_ENGINE_IDX_NVDEC2}, @@ -3395,14 +3390,14 @@ kfifoGetGuestEngineLookupTable_IMPL {NV2080_ENGINE_TYPE_NVJPEG5, MC_ENGINE_IDX_NVJPEG5}, {NV2080_ENGINE_TYPE_NVJPEG6, MC_ENGINE_IDX_NVJPEG6}, {NV2080_ENGINE_TYPE_NVJPEG7, MC_ENGINE_IDX_NVJPEG7}, - {NV2080_ENGINE_TYPE_OFA, MC_ENGINE_IDX_OFA0}, + {NV2080_ENGINE_TYPE_OFA0, MC_ENGINE_IDX_OFA0}, }; // // To trap NV2080_ENGINE_TYPE expansions. // Please update the table guestEngineLookupTable if this assertion is triggered. // - ct_assert(NV2080_ENGINE_TYPE_LAST == 0x0000003e); + ct_assert(NV2080_ENGINE_TYPE_LAST == 0x0000003f); *pEngLookupTblSize = NV_ARRAY_ELEMENTS(guestEngineLookupTable); @@ -3424,13 +3419,16 @@ kfifoGetMaxSecureChannels_KERNEL RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS numSecureChannelsParams = {0}; - NV_ASSERT_OK_OR_RETURN( - pRmApi->Control(pRmApi, - pGpu->hInternalClient, - pGpu->hInternalSubdevice, - NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS, - &numSecureChannelsParams, - sizeof(numSecureChannelsParams))); + if (gpuIsCCFeatureEnabled(pGpu)) + { + NV_ASSERT_OK_OR_RETURN( + pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS, + &numSecureChannelsParams, + sizeof(numSecureChannelsParams))); + } pKernelFifo->maxSec2SecureChannels = numSecureChannelsParams.maxSec2SecureChannels; pKernelFifo->maxCeSecureChannels = numSecureChannelsParams.maxCeSecureChannels; diff --git a/src/nvidia/src/kernel/gpu/fifo/kernel_sched_mgr.c b/src/nvidia/src/kernel/gpu/fifo/kernel_sched_mgr.c index 4d2c220ffe..99f3cd6c81 100644 --- a/src/nvidia/src/kernel/gpu/fifo/kernel_sched_mgr.c +++ b/src/nvidia/src/kernel/gpu/fifo/kernel_sched_mgr.c @@ -102,7 +102,7 @@ kschedmgrConstructPolicy_IMPL portDbgPrintf("NVRM: GPU at %04x:%02x:%02x.0 has software scheduler %s with policy %s.\n", domain, bus, device, - pKernelSchedMgr->bIsSchedSwEnabled ? "ENABLED" : "DISABLED", + pKernelSchedMgr->bIsSchedSwEnabled ? MAKE_NV_PRINTF_STR("ENABLED") : MAKE_NV_PRINTF_STR("DISABLED"), schedPolicyName); } else @@ -111,7 +111,7 @@ kschedmgrConstructPolicy_IMPL NV_PRINTF(LEVEL_INFO, "GPU at %04x:%02x:%02x.0 has software scheduler %s with policy %s.\n", domain, bus, device, - pKernelSchedMgr->bIsSchedSwEnabled ? "ENABLED" : "DISABLED", + pKernelSchedMgr->bIsSchedSwEnabled ? MAKE_NV_PRINTF_STR("ENABLED") : MAKE_NV_PRINTF_STR("DISABLED"), schedPolicyName); } diff --git a/src/nvidia/src/kernel/gpu/fifo/usermode_api.c b/src/nvidia/src/kernel/gpu/fifo/usermode_api.c index fa870a1446..44e2f4ffd3 100644 --- a/src/nvidia/src/kernel/gpu/fifo/usermode_api.c +++ b/src/nvidia/src/kernel/gpu/fifo/usermode_api.c @@ -44,29 +44,25 @@ usrmodeConstruct_IMPL NvBool bBar1Mapping = NV_FALSE; NvBool bPrivMapping = NV_FALSE; MEMORY_DESCRIPTOR *pMemDesc = pKernelFifo->pRegVF; + NvU32 memClassId = NV01_MEMORY_LOCAL_PRIVILEGED; // Copy-construction has already been done by the base Memory class if (RS_IS_COPY_CTOR(pParams)) { + UserModeApi *pUserModeSrc = dynamicCast(pParams->pSrcRef->pResource, UserModeApi); + + pUserModeApi->bInternalMmio = pUserModeSrc->bInternalMmio; + pUserModeApi->bPrivMapping = pUserModeSrc->bPrivMapping; + return NV_OK; } - // - // We check pKernelFifo->pBar1VF because for some reason RM allows HOPPER_USERMODE_A on ADA. - // This is a WAR until we root cause. - // - if (hClass >= HOPPER_USERMODE_A && pAllocParams != NULL && pKernelFifo->pBar1VF != NULL) + if (hClass >= HOPPER_USERMODE_A && pAllocParams != NULL) { bBar1Mapping = pAllocParams->bBar1Mapping; bPrivMapping = pAllocParams->bPriv; } - if (pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING) || - pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_ALL_INST_IN_SYSMEM)) - { - bBar1Mapping = NV_FALSE; - } - NV_CHECK_OR_RETURN(LEVEL_ERROR, !bPrivMapping || bBar1Mapping, NV_ERR_INVALID_PARAMETER); @@ -75,15 +71,33 @@ usrmodeConstruct_IMPL !bPrivMapping || pCallContext->secInfo.privLevel >= RS_PRIV_LEVEL_KERNEL, NV_ERR_INSUFFICIENT_PERMISSIONS); + // + // In order to map only internal MMIO, pAllocParams->bBar1Mapping must be set to true, + // and clients need not map to CPU. This parameter might be renamed in the future to indicate + // that it is both for BAR1 use and internal MMIO use. + // + pUserModeApi->bInternalMmio = bBar1Mapping; + pUserModeApi->bPrivMapping = bPrivMapping; + + // + // On coherent platforms, we don't support BAR1 mapping of doorbell, but we still support internal MMIO. + // This check transparently returns a BAR0 CPU mapping on these platforms. + // + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING) || + pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_ALL_INST_IN_SYSMEM)) + { + bBar1Mapping = NV_FALSE; + } + if (bBar1Mapping) { pMemDesc = bPrivMapping ? pKernelFifo->pBar1PrivVF : pKernelFifo->pBar1VF; + memClassId = NV01_MEMORY_SYSTEM; } NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - memConstructCommon(pMemory, - bBar1Mapping? NV01_MEMORY_SYSTEM : NV01_MEMORY_LOCAL_PRIVILEGED, - 0, pMemDesc, 0, NULL, 0, 0, 0, 0, NVOS32_MEM_TAG_NONE, NULL)); + memConstructCommon(pMemory, memClassId, 0, pMemDesc, 0, NULL, + 0, 0, 0, 0, NVOS32_MEM_TAG_NONE, NULL)); memdescAddRef(pMemDesc); return NV_OK; } @@ -92,3 +106,28 @@ NvBool usrmodeCanCopy_IMPL(UserModeApi *pUserModeApi){ return NV_TRUE; } + +NV_STATUS +usrmodeGetMemInterMapParams_IMPL +( + UserModeApi *pUserModeApi, + RMRES_MEM_INTER_MAP_PARAMS *pParams +) +{ + // + // We need to always return the correct memdesc for GPU mapping, regardless of what is used on the CPU. + // We do this by overriding the regular pParams returned from memGetMemInterMapParams + // + Memory *pMemory = staticCast(pUserModeApi, Memory); + OBJGPU *pGpu = pMemory->pGpu; + KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, memGetMemInterMapParams_IMPL(pMemory, pParams)); + + NV_CHECK_OR_RETURN(LEVEL_ERROR, pUserModeApi->bInternalMmio, NV_ERR_INVALID_PARAMETER); + + pParams->pSrcMemDesc = pUserModeApi->bPrivMapping ? pKernelFifo->pBar1PrivVF : pKernelFifo->pBar1VF; + + return NV_OK; + +} diff --git a/src/nvidia/src/kernel/gpu/fifo/uvm_channel_retainer.c b/src/nvidia/src/kernel/gpu/fifo/uvm_channel_retainer.c index 32098a8cef..ce77b9bf4e 100644 --- a/src/nvidia/src/kernel/gpu/fifo/uvm_channel_retainer.c +++ b/src/nvidia/src/kernel/gpu/fifo/uvm_channel_retainer.c @@ -133,8 +133,6 @@ uvmchanrtnrIsAllocationAllowed_IMPL ) { - NvBool bIsAllowed = NV_FALSE; - RS_PRIV_LEVEL privLevel = pCallContext->secInfo.privLevel; OBJGPU *pGpu = GPU_RES_GET_GPU(pUvmChannelRetainer); NV_ASSERT_OR_RETURN(pKernelChannel != NULL, NV_FALSE); @@ -145,18 +143,9 @@ uvmchanrtnrIsAllocationAllowed_IMPL NV_ASSERT_OR_RETURN(vgpuGetCallingContextGfid(pGpu, &gfid) == NV_OK, NV_FALSE); if (IS_GFID_VF(gfid)) { - bIsAllowed = (gfid == kchannelGetGfid(pKernelChannel)); - } - else - { - NvHandle hClient = pCallContext->pClient->hClient; - bIsAllowed = rmclientIsAdminByHandle(hClient, privLevel) || hypervisorCheckForObjectAccess(hClient); + return (gfid == kchannelGetGfid(pKernelChannel)); } } - else - { - bIsAllowed = ((privLevel >= RS_PRIV_LEVEL_KERNEL) && - (pCallContext->secInfo.paramLocation == PARAM_LOCATION_KERNEL)); - } - return bIsAllowed; + + return NV_TRUE; } diff --git a/src/nvidia/src/kernel/gpu/fsp/arch/hopper/kern_fsp_gh100.c b/src/nvidia/src/kernel/gpu/fsp/arch/hopper/kern_fsp_gh100.c index de030bafa9..3d4a8d85f3 100644 --- a/src/nvidia/src/kernel/gpu/fsp/arch/hopper/kern_fsp_gh100.c +++ b/src/nvidia/src/kernel/gpu/fsp/arch/hopper/kern_fsp_gh100.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -30,6 +30,8 @@ #include "gpu/fsp/kern_fsp.h" #include "gpu/fsp/kern_fsp_retval.h" #include "gpu/gsp/kernel_gsp.h" +#include "gpu/mem_mgr/mem_mgr.h" +#include "gpu/pmu/kern_pmu.h" #include "published/hopper/gh100/dev_fsp_pri.h" #include "published/hopper/gh100/dev_fsp_addendum.h" @@ -844,10 +846,11 @@ kfspSetupGspImages pGspImageMapSize = NV_ALIGN_UP(pGspImageSize, 0x1000); status = memdescCreate(&pKernelFsp->pGspFmcMemdesc, pGpu, pGspImageMapSize, - 0, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_UNCACHED, flags); + 0, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_CACHED, flags); NV_ASSERT_OR_GOTO(status == NV_OK, failed); - status = memdescAlloc(pKernelFsp->pGspFmcMemdesc); + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_7, + pKernelFsp->pGspFmcMemdesc); NV_ASSERT_OR_GOTO(status == NV_OK, failed); status = memdescMap(pKernelFsp->pGspFmcMemdesc, 0, pGspImageMapSize, NV_TRUE, @@ -972,6 +975,8 @@ kfspDumpDebugState_GH100 DRF_VAL(_GFW, _FSP_UCODE_VERSION, _MINOR, fspUcodeVersion)); } + NV_PRINTF(LEVEL_ERROR, "GPU %04x:%02x:%02x\n", + gpuGetDomain(pGpu), gpuGetBus(pGpu), gpuGetDevice(pGpu)); NV_PRINTF(LEVEL_ERROR, "NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(0) = 0x%x\n", GPU_REG_RD32(pGpu, NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(0))); NV_PRINTF(LEVEL_ERROR, "NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(1) = 0x%x\n", @@ -1097,10 +1102,11 @@ kfspSendBootCommands_GH100 // flags = MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY; status = memdescCreate(&pKernelFsp->pSysmemFrtsMemdesc, pGpu, frtsSize, - 0, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_UNCACHED, flags); + 0, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_CACHED, flags); NV_ASSERT_OR_GOTO(status == NV_OK, failed); - status = memdescAlloc(pKernelFsp->pSysmemFrtsMemdesc); + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_8, + pKernelFsp->pSysmemFrtsMemdesc); NV_ASSERT_OR_GOTO(status == NV_OK, failed); // Set up a kernel mapping for future use in RM @@ -1129,10 +1135,12 @@ kfspSendBootCommands_GH100 // future, this code will need to be updated. // Bug 200711957 has more info and tracks longer term improvements. // - const NvU32 ESTIMATED_RESERVE_FB = 0x200000; // Offset from end of FB to be used by FSP - pCotPayload->frtsVidmemOffset = ESTIMATED_RESERVE_FB; + NvU32 FRTS_OFFSET_FROM_END = + memmgrGetFBEndReserveSizeEstimate_HAL(pGpu, GPU_GET_MEMORY_MANAGER(pGpu)); + + pCotPayload->frtsVidmemOffset = FRTS_OFFSET_FROM_END; pCotPayload->frtsVidmemSize = frtsSize; } diff --git a/src/nvidia/src/kernel/gpu/fsp/kern_fsp.c b/src/nvidia/src/kernel/gpu/fsp/kern_fsp.c index 9f1fb0da0b..38b7f2370e 100644 --- a/src/nvidia/src/kernel/gpu/fsp/kern_fsp.c +++ b/src/nvidia/src/kernel/gpu/fsp/kern_fsp.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -74,7 +74,7 @@ kfspInitRegistryOverrides if (((osReadRegistryDword(pGpu, NV_REG_STR_RM_DISABLE_FSP, &data) == NV_OK) && (data == NV_REG_STR_RM_DISABLE_FSP_YES) && IS_EMULATION(pGpu)) || - IS_FMODEL(pGpu)) + IS_FMODEL(pGpu) || IS_RTLSIM(pGpu)) { // // Force disable FSP engine, used only on emulation because some @@ -103,8 +103,10 @@ kfspInitRegistryOverrides } } - // Inst-in-sys must only set up FRTS in SYSMEM. This includes FB broken. - if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_ALL_INST_IN_SYSMEM)) + // Inst-in-sys must only set up FRTS in SYSMEM. This includes FB broken and cache only. + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_ALL_INST_IN_SYSMEM) || + pGpu->getProperty(pGpu, PDB_PROP_GPU_BROKEN_FB) || + gpuIsCacheOnlyModeEnabled(pGpu)) { pKernelFsp->setProperty(pKernelFsp, PDB_PROP_KFSP_DISABLE_FRTS_VIDMEM, NV_TRUE); } diff --git a/src/nvidia/src/kernel/gpu/gpu.c b/src/nvidia/src/kernel/gpu/gpu.c index 06189d40b8..3f3da30907 100644 --- a/src/nvidia/src/kernel/gpu/gpu.c +++ b/src/nvidia/src/kernel/gpu/gpu.c @@ -56,6 +56,7 @@ #include "gpu/sec2/kernel_sec2.h" #include "gpu/gsp/kernel_gsp.h" +#include "gpu/video/kernel_video_engine.h" #include "platform/platform.h" #include "platform/chipset/chipset.h" #include "kernel/gpu/host_eng/host_eng.h" @@ -100,6 +101,7 @@ typedef struct GPUCHILDTYPE GPUCHILDTYPE; static NV_STATUS gpuRemoveMissingEngines(OBJGPU *); // local static function +static NV_STATUS _gpuChildrenPresentInit(OBJGPU *pGpu); static NV_STATUS gpuCreateChildObjects(OBJGPU *, NvBool); static NV_STATUS gpuStatePreLoad(OBJGPU *, NvU32); static NV_STATUS gpuStatePostLoad(OBJGPU *, NvU32); @@ -359,7 +361,7 @@ gpuPostConstruct_IMPL if (rmStatus != NV_OK) return rmStatus; - pGpu->setProperty(pGpu, PDB_PROP_GPU_MOVE_CTX_BUFFERS_TO_PMA, + pGpu->setProperty(pGpu, PDB_PROP_GPU_MOVE_CTX_BUFFERS_TO_PMA, gpuIsCtxBufAllocInPmaSupported_HAL(pGpu)); // // gpuDetermineVirtualMode inits hPci but only for virtualization case. So if @@ -380,18 +382,8 @@ gpuPostConstruct_IMPL // pGpu->sriovState.virtualRegPhysOffset = gpuGetVirtRegPhysOffset_HAL(pGpu); - // - // Check if FBHUB Poison interrupt is triggered before RM Init due - // to VBIOS IFR on GA100. If yes, clear the FBHUB Interrupt. This WAR is - // required for Bug 2924523 where VBIOS IFR causes FBHUB Poison intr. - // We need to clear this before RM Init begins, as an FBHUB Poison as part of - // RM Init is a valid interrupt - // - // Additional details which might be of interest exist in bug 200620015 - // comments 43-45 pertaining to the necessity of the WAR so close to the - // register write enablement. - // - gpuClearFbhubPoisonIntrForBug2924523_HAL(pGpu); + NV_ASSERT_OK_OR_RETURN( + _gpuChildrenPresentInit(pGpu)); // // Initialize engine order before engine init/load/etc @@ -457,6 +449,19 @@ gpuPostConstruct_IMPL if (rmStatus != NV_OK) return rmStatus; + // + // Check if FBHUB Poison interrupt is triggered before RM Init due + // to VBIOS IFR on GA100. If yes, clear the FBHUB Interrupt. This WAR is + // required for Bug 2924523 where VBIOS IFR causes FBHUB Poison intr. + // We need to clear this before RM Init begins, as an FBHUB Poison as part of + // RM Init is a valid interrupt + // + // Additional details which might be of interest exist in bug 200620015 + // comments 43-45 pertaining to the necessity of the WAR so close to the + // register write enablement. + // + gpuClearFbhubPoisonIntrForBug2924523_HAL(pGpu); + if (IS_SIMULATION(pGpu) && !IS_VIRTUAL(pGpu)) { // @@ -582,7 +587,12 @@ static NV_STATUS _gpuRmApiControl // internal handles, we can skip the resource server overhead and make a // direct function call instead. // - if (hClient == pGpu->hInternalClient && hObject == pGpu->hInternalSubdevice) + // This optimization should be skipped on vGPU Guests as they should always + // go through the resource server. The resource server is responsible for + // deciding whether to RPC to the HOST (ROUTE_TO_VGPU_HOST) or call the + // implementation on the guest. + // + if (!IS_VIRTUAL(pGpu) && hClient == pGpu->hInternalClient && hObject == pGpu->hInternalSubdevice) { NV_ASSERT_OR_RETURN(pGpu->pCachedSubdevice && pGpu->pCachedRsClient, NV_ERR_INVALID_STATE); @@ -806,7 +816,7 @@ static NV_STATUS _gpuAllocateInternalObjects NV_ASSERT_OK_OR_GOTO(status, serverGetClientUnderLock(&g_resServ, pGpu->hInternalClient, &pGpu->pCachedRsClient), done); - NV_ASSERT_OK_OR_GOTO(status, subdeviceGetByGpu(pGpu->pCachedRsClient, pGpu, + NV_ASSERT_OK_OR_GOTO(status, subdeviceGetByHandle(pGpu->pCachedRsClient, pGpu->hInternalSubdevice, &pGpu->pCachedSubdevice), done); } @@ -1054,16 +1064,13 @@ _gpuChildNvocClassInfoGet const NVOC_CLASS_INFO **ppClassInfo ) { - NvU32 numChildPresent; - const GPUCHILDPRESENT *const pChildrenPresent = - gpuGetChildrenPresent_HAL(pGpu, &numChildPresent); - NvU32 i; + NvU32 i; - for (i = 0U; i < numChildPresent; i++) + for (i = 0U; i < pGpu->numChildrenPresent; i++) { - if (classId == pChildrenPresent[i].classId) + if (classId == pGpu->pChildrenPresent[i].classId) { - *ppClassInfo = pChildrenPresent[i].pClassInfo; + *ppClassInfo = pGpu->pChildrenPresent[i].pClassInfo; return NV_OK; } } @@ -1334,7 +1341,7 @@ gpuCreateObject_IMPL } status = engstateConstructBase(pEngstate, pGpu, childInfo.engDesc); - NV_ASSERT_OR_GOTO(status == NV_OK, gpuCreateObject_exit); + NV_CHECK_OR_GOTO(LEVEL_INFO, status == NV_OK, gpuCreateObject_exit); engstateLogStateTransitionPre(pEngstate, ENGSTATE_STATE_CONSTRUCT, &engTransitionData); status = engstateConstructEngine(pGpu, pEngstate, childInfo.engDesc); @@ -1406,10 +1413,10 @@ gpuDestruct_IMPL } // Free GPU shared data - memdescUnmap(pGpu->userSharedData.pMemDesc, NV_TRUE, 0, - pGpu->userSharedData.pMapBuffer, pGpu->userSharedData.pMapBufferPriv); - memdescFree(pGpu->userSharedData.pMemDesc); - memdescDestroy(pGpu->userSharedData.pMemDesc); + if (pGpu->userSharedData.pMemDesc != NULL) + { + gpushareddataDestroy(pGpu); + } // Free children in reverse order from construction for (typeNum = GPU_NUM_CHILD_TYPES - 1; typeNum >= 0; typeNum--) @@ -1491,6 +1498,25 @@ gpuDestruct_IMPL gpuDestructPhysical(pGpu); } +/*! + * @brief Initializes @ref OBJGPU::pChildrenPresent data + * + * @param[in] pGpu + * + * @return @ref NV_OK + * Success + */ +static NV_STATUS +_gpuChildrenPresentInit +( + OBJGPU *pGpu +) +{ + pGpu->pChildrenPresent = + gpuGetChildrenPresent_HAL(pGpu, &pGpu->numChildrenPresent); + return NV_OK; +} + static NV_STATUS gpuCreateChildObjects ( @@ -1553,19 +1579,16 @@ gpuShouldCreateObject ) { NvBool retVal = NV_FALSE; - NvU32 numChildPresent; - const GPUCHILDPRESENT *const pChildPresentList = - gpuGetChildrenPresent_HAL(pGpu, &numChildPresent); NvU32 childIdx; // Let the HAL confirm that we should create an object for this engine. - for (childIdx = 0; childIdx < numChildPresent; childIdx++) + for (childIdx = 0; childIdx < pGpu->numChildrenPresent; childIdx++) { if ((ENGDESC_FIELD(pChildInfo->engDesc, _CLASS) == - pChildPresentList[childIdx].classId)) + pGpu->pChildrenPresent[childIdx].classId)) { retVal = (ENGDESC_FIELD(pChildInfo->engDesc, _INST) < - pChildPresentList[childIdx].instances); + pGpu->pChildrenPresent[childIdx].instances); break; } } @@ -2058,6 +2081,8 @@ gpuStatePreInit_IMPL NV_ASSERT_OK_OR_RETURN(gpuConstructUserRegisterAccessMap(pGpu)); NV_ASSERT_OK_OR_RETURN(gpuBuildGenericKernelFalconList(pGpu)); + NV_ASSERT_OK_OR_RETURN(gpuBuildKernelVideoEngineList(pGpu)); + // // Must be called after _gpuInitChipInfo since gpuDetermineMIGSupport_HAL // reads chip revision and that is available only after _gpuInitChipInfo. @@ -2084,10 +2109,13 @@ gpuStatePreInit_IMPL continue; } - engstateLogStateTransitionPre(pEngstate, ENGSTATE_STATE_PRE_INIT, &engTransitionData); - rmStatus = engstateStatePreInit(pGpu, pEngstate); - engstateLogStateTransitionPost(pEngstate, ENGSTATE_STATE_PRE_INIT, &engTransitionData); - + rmStatus = gpuLoadFailurePathTest(pGpu, NV_REG_STR_GPU_LOAD_FAILURE_TEST_STAGE_PREINIT, curEngDescIdx, NV_FALSE); + if (rmStatus == NV_OK) + { + engstateLogStateTransitionPre(pEngstate, ENGSTATE_STATE_PRE_INIT, &engTransitionData); + rmStatus = engstateStatePreInit(pGpu, pEngstate); + engstateLogStateTransitionPost(pEngstate, ENGSTATE_STATE_PRE_INIT, &engTransitionData); + } if (rmStatus == NV_ERR_NOT_SUPPORTED) { switch (curEngDescriptor) @@ -2134,6 +2162,12 @@ gpuStatePreInit_IMPL } } + // RM User Shared Data is currently unable to support VGPU due to isolation requirements + if (IS_VIRTUAL(pGpu)) + { + gpuDeleteClassFromClassDBByClassId(pGpu, RM_USER_SHARED_DATA); + } + gpuInitOptimusSettings(pGpu); return rmStatus; @@ -2184,9 +2218,13 @@ gpuStateInit_IMPL continue; } - engstateLogStateTransitionPre(pEngstate, ENGSTATE_STATE_INIT, &engTransitionData); - rmStatus = engstateStateInit(pGpu, pEngstate); - engstateLogStateTransitionPost(pEngstate, ENGSTATE_STATE_INIT, &engTransitionData); + rmStatus = gpuLoadFailurePathTest(pGpu, NV_REG_STR_GPU_LOAD_FAILURE_TEST_STAGE_INIT, curEngDescIdx, NV_FALSE); + if (rmStatus == NV_OK) + { + engstateLogStateTransitionPre(pEngstate, ENGSTATE_STATE_INIT, &engTransitionData); + rmStatus = engstateStateInit(pGpu, pEngstate); + engstateLogStateTransitionPost(pEngstate, ENGSTATE_STATE_INIT, &engTransitionData); + } // RMCONFIG: Bail on errors unless the feature/object/engine/class // is simply unsupported @@ -2270,14 +2308,17 @@ gpuStatePreLoad continue; } - RMTRACE_ENGINE_PROFILE_EVENT("gpuStatePreLoadEngStart", curEngDescriptor, pGpu->registerAccess.regReadCount, pGpu->registerAccess.regWriteCount); - - engstateLogStateTransitionPre(pEngstate, ENGSTATE_STATE_PRE_LOAD, &engTransitionData); - rmStatus = engstateStatePreLoad(pGpu, pEngstate, flags); - engstateLogStateTransitionPost(pEngstate, ENGSTATE_STATE_PRE_LOAD, &engTransitionData); + rmStatus = gpuLoadFailurePathTest(pGpu, NV_REG_STR_GPU_LOAD_FAILURE_TEST_STAGE_PRELOAD, curEngDescIdx, NV_FALSE); + if (rmStatus == NV_OK) + { + RMTRACE_ENGINE_PROFILE_EVENT("gpuStatePreLoadEngStart", curEngDescriptor, pGpu->registerAccess.regReadCount, pGpu->registerAccess.regWriteCount); - RMTRACE_ENGINE_PROFILE_EVENT("gpuStatePreLoadEngEnd", curEngDescriptor, pGpu->registerAccess.regReadCount, pGpu->registerAccess.regWriteCount); + engstateLogStateTransitionPre(pEngstate, ENGSTATE_STATE_PRE_LOAD, &engTransitionData); + rmStatus = engstateStatePreLoad(pGpu, pEngstate, flags); + engstateLogStateTransitionPost(pEngstate, ENGSTATE_STATE_PRE_LOAD, &engTransitionData); + RMTRACE_ENGINE_PROFILE_EVENT("gpuStatePreLoadEngEnd", curEngDescriptor, pGpu->registerAccess.regReadCount, pGpu->registerAccess.regWriteCount); + } // // An engine load leaving the broadcast status to NV_TRUE // will most likely mess up the pre-load of the next engines @@ -2371,12 +2412,15 @@ gpuStateLoad_IMPL continue; } - RMTRACE_ENGINE_PROFILE_EVENT("gpuStateLoadEngStart", curEngDescriptor, pGpu->registerAccess.regReadCount, pGpu->registerAccess.regWriteCount); - - engstateLogStateTransitionPre(pEngstate, ENGSTATE_STATE_LOAD, &engTransitionData); - rmStatus = engstateStateLoad(pGpu, pEngstate, flags); - engstateLogStateTransitionPost(pEngstate, ENGSTATE_STATE_LOAD, &engTransitionData); + rmStatus = gpuLoadFailurePathTest(pGpu, NV_REG_STR_GPU_LOAD_FAILURE_TEST_STAGE_LOAD, curEngDescIdx, NV_FALSE); + if (rmStatus == NV_OK) + { + RMTRACE_ENGINE_PROFILE_EVENT("gpuStateLoadEngStart", curEngDescriptor, pGpu->registerAccess.regReadCount, pGpu->registerAccess.regWriteCount); + engstateLogStateTransitionPre(pEngstate, ENGSTATE_STATE_LOAD, &engTransitionData); + rmStatus = engstateStateLoad(pGpu, pEngstate, flags); + engstateLogStateTransitionPost(pEngstate, ENGSTATE_STATE_LOAD, &engTransitionData); + } // TODO: This is temporary and may be dead with TESLA if (rmStatus == NV_ERR_INVALID_ADDRESS) @@ -2397,7 +2441,9 @@ gpuStateLoad_IMPL if (rmStatus == NV_ERR_NOT_SUPPORTED) rmStatus = NV_OK; if (rmStatus != NV_OK) + { goto gpuStateLoad_exit; + } // // Release and re-acquire the lock to allow interrupts @@ -2412,6 +2458,9 @@ gpuStateLoad_IMPL RMTRACE_ENGINE_PROFILE_EVENT("gpuStateLoadEngEnd", curEngDescriptor, pGpu->registerAccess.regReadCount, pGpu->registerAccess.regWriteCount); } + // Video logging is not a required feature, don't override existing status + NV_CHECK(LEVEL_ERROR, gpuInitVideoLogging(pGpu) == NV_OK); + rmStatus = gpuInitVmmuInfo(pGpu); if (rmStatus != NV_OK) { @@ -2743,12 +2792,15 @@ gpuStatePostLoad continue; } - RMTRACE_ENGINE_PROFILE_EVENT("gpuStatePostLoadEngStart", curEngDescriptor, pGpu->registerAccess.regReadCount, pGpu->registerAccess.regWriteCount); - engstateLogStateTransitionPre(pEngstate, ENGSTATE_STATE_POST_LOAD, &engTransitionData); - rmStatus = engstateStatePostLoad(pGpu, pEngstate, flags); - engstateLogStateTransitionPost(pEngstate, ENGSTATE_STATE_POST_LOAD, &engTransitionData); - RMTRACE_ENGINE_PROFILE_EVENT("gpuStatePostLoadEngEnd", curEngDescriptor, pGpu->registerAccess.regReadCount, pGpu->registerAccess.regWriteCount); - + rmStatus = gpuLoadFailurePathTest(pGpu, NV_REG_STR_GPU_LOAD_FAILURE_TEST_STAGE_POSTLOAD, curEngDescIdx, NV_FALSE); + if (rmStatus == NV_OK) + { + RMTRACE_ENGINE_PROFILE_EVENT("gpuStatePostLoadEngStart", curEngDescriptor, pGpu->registerAccess.regReadCount, pGpu->registerAccess.regWriteCount); + engstateLogStateTransitionPre(pEngstate, ENGSTATE_STATE_POST_LOAD, &engTransitionData); + rmStatus = engstateStatePostLoad(pGpu, pEngstate, flags); + engstateLogStateTransitionPost(pEngstate, ENGSTATE_STATE_POST_LOAD, &engTransitionData); + RMTRACE_ENGINE_PROFILE_EVENT("gpuStatePostLoadEngEnd", curEngDescriptor, pGpu->registerAccess.regReadCount, pGpu->registerAccess.regWriteCount); + } // RMCONFIG: Bail on errors unless the feature/object/engine/class // is simply unsupported if (rmStatus == NV_ERR_NOT_SUPPORTED) @@ -2811,6 +2863,10 @@ gpuStatePostLoad NV_ASSERT_OR_GOTO(gpuFabricProbeStart(pGpu, &pGpu->pGpuFabricProbeInfoKernel) == NV_OK, gpuStatePostLoad_exit); + // terminate the load failure test + if (rmStatus == NV_OK) + gpuLoadFailurePathTest(pGpu, NV_REG_STR_GPU_LOAD_FAILURE_TEST_STAGE_POSTLOAD, 0, NV_TRUE); + gpuStatePostLoad_exit: return rmStatus; } @@ -2935,6 +2991,7 @@ gpuStateUnload_IMPL // Set indicator that state is currently unloading. pGpu->bStateUnloading = NV_TRUE; + { rmStatus = gpuStatePreUnload(pGpu, flags); } @@ -2942,6 +2999,8 @@ gpuStateUnload_IMPL if (rmStatus != NV_OK) return rmStatus; + gpuFreeVideoLogging(pGpu); + engDescriptorList = gpuGetUnloadEngineDescriptors(pGpu); numEngDescriptors = gpuGetNumEngDescriptors(pGpu); @@ -3181,6 +3240,8 @@ gpuStateDestroy_IMPL _gpuFreeInternalObjects(pGpu); gpuDestroyGenericKernelFalconList(pGpu); + gpuDestroyKernelVideoEngineList(pGpu); + portMemFree(pGpu->gspSupportedEngines); pGpu->gspSupportedEngines = NULL; @@ -3944,7 +4005,7 @@ static const EXTERN_TO_INTERNAL_ENGINE_ID rmClientEngineTable[] = { RM_ENGINE_TYPE_NVJPEG5, classId(OBJNVJPG) , 5, NV_TRUE }, { RM_ENGINE_TYPE_NVJPEG6, classId(OBJNVJPG) , 6, NV_TRUE }, { RM_ENGINE_TYPE_NVJPEG7, classId(OBJNVJPG) , 7, NV_TRUE }, - { RM_ENGINE_TYPE_OFA, classId(OBJOFA) , 0, NV_TRUE }, + { RM_ENGINE_TYPE_OFA0, classId(OBJOFA) , 0, NV_TRUE }, { RM_ENGINE_TYPE_DPU, classId(OBJDPU) , 0, NV_FALSE }, { RM_ENGINE_TYPE_PMU, classId(Pmu) , 0, NV_FALSE }, { RM_ENGINE_TYPE_FBFLCN, classId(OBJFBFLCN) , 0, NV_FALSE }, @@ -4487,6 +4548,100 @@ void gpuDestroyGenericKernelFalconList_IMPL(OBJGPU *pGpu) pGpu->numGenericKernelFalcons = 0; } +NvBool +gpuIsVideoTraceLogSupported +( + OBJGPU *pGpu +) +{ + return !RMCFG_FEATURE_PLATFORM_MODS && !IS_SIMULATION(pGpu) && pGpu->bVideoTraceLogSupported; +} + +NV_STATUS gpuBuildKernelVideoEngineList_IMPL(OBJGPU *pGpu) +{ + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV_STATUS status = NV_OK; + NvU32 numKernelVideoEngines = 0; + NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS *pParams; + NvU32 i; + + pParams = portMemAllocNonPaged(sizeof(*pParams)); + NV_ASSERT_OR_RETURN(pParams != NULL, NV_ERR_NO_MEMORY); + + portMemSet(pParams, 0, sizeof(*pParams)); + + NV_ASSERT_OK_OR_GOTO( + status, + pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_GET_CONSTRUCTED_FALCON_INFO, + pParams, sizeof(*pParams)), + done); + + for (i = 0; i < pParams->numConstructedFalcons; i++) + { + ENGDESCRIPTOR physEngDesc = pParams->constructedFalconsTable[i].engDesc; + + if (!IS_VIDEO_ENGINE(physEngDesc)) + { + continue; + } + + NV_ASSERT_OR_ELSE(numKernelVideoEngines < NV_ARRAY_ELEMENTS(pGpu->kernelVideoEngines), + status = NV_ERR_INVALID_STATE; goto done;); + + NV_ASSERT_OK_OR_GOTO( + status, + objCreate(&pGpu->kernelVideoEngines[numKernelVideoEngines], pGpu, KernelVideoEngine, pGpu, physEngDesc), + done); + numKernelVideoEngines++; + } + + pGpu->numKernelVideoEngines = numKernelVideoEngines; + +done: + portMemFree(pParams); + if (status != NV_OK) + { + gpuDestroyKernelVideoEngineList(pGpu); + } + return status; +} + +NV_STATUS gpuInitVideoLogging_IMPL(OBJGPU *pGpu) +{ + NvU32 i; + for (i = 0; i < pGpu->numKernelVideoEngines; i++) + { + if (pGpu->kernelVideoEngines[i] != NULL) + { + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kvidengInitLogging(pGpu, pGpu->kernelVideoEngines[i])); + } + } + return NV_OK; +} + +void gpuFreeVideoLogging_IMPL(OBJGPU *pGpu) +{ + NvU32 i; + for (i = 0; i < pGpu->numKernelVideoEngines; i++) + { + if (pGpu->kernelVideoEngines[i] != NULL) + { + kvidengFreeLogging(pGpu, pGpu->kernelVideoEngines[i]); + } + } +} + +void gpuDestroyKernelVideoEngineList_IMPL(OBJGPU *pGpu) +{ + NvU32 i; + for (i = 0; i < NV_ARRAY_ELEMENTS(pGpu->kernelVideoEngines); i++) + { + objDelete(pGpu->kernelVideoEngines[i]); + pGpu->kernelVideoEngines[i] = NULL; + } + pGpu->numKernelVideoEngines = 0; +} GenericKernelFalcon * gpuGetGenericKernelFalconForEngine_IMPL @@ -4552,7 +4707,7 @@ gpuFindChildPresent(const GPUCHILDPRESENT *pChildPresentList, NvU32 numChildPres * @param[out] Current state of GFID */ NV_STATUS -gpuGetGfidState(OBJGPU *pGpu, NvU32 gfid, GFID_ALLOC_STATUS *pState) +gpuGetGfidState_IMPL(OBJGPU *pGpu, NvU32 gfid, GFID_ALLOC_STATUS *pState) { if (!gpuIsSriovEnabled(pGpu)) return NV_OK; @@ -4619,14 +4774,11 @@ gpuGetNextInEngineOrderList(OBJGPU *pGpu, ENGLIST_ITER *pIt, PENGDESCRIPTOR pEng NvBool bReverse = !!(pIt->flags & (GCO_LIST_UNLOAD | GCO_LIST_DESTROY)); const GPUCHILDORDER *pChildOrderList; NvU32 numChildOrder; - const GPUCHILDPRESENT *pChildPresentList; - NvU32 numChildPresent; const GPUCHILDPRESENT *pCurChildPresent; const GPUCHILDORDER *pCurChildOrder; NvBool bAdvance = NV_FALSE; pChildOrderList = gpuGetChildrenOrder_HAL(pGpu, &numChildOrder); - pChildPresentList = gpuGetChildrenPresent_HAL(pGpu, &numChildPresent); if (!pIt->bStarted) { @@ -4650,7 +4802,8 @@ gpuGetNextInEngineOrderList(OBJGPU *pGpu, ENGLIST_ITER *pIt, PENGDESCRIPTOR pEng continue; } - pCurChildPresent = gpuFindChildPresent(pChildPresentList, numChildPresent, pCurChildOrder->classId); + pCurChildPresent = gpuFindChildPresent(pGpu->pChildrenPresent, + pGpu->numChildrenPresent, pCurChildOrder->classId); if (!pCurChildPresent) { @@ -4738,19 +4891,27 @@ gpuInitDispIpHal_IMPL } void __nvoc_init_funcTable_KernelDisplay(KernelDisplay *, RmHalspecOwner *); + void __nvoc_init_dataField_KernelDisplay(KernelDisplay*, RmHalspecOwner* ); __nvoc_init_funcTable_KernelDisplay(pKernelDisplay, pRmHalspecOwner); + __nvoc_init_dataField_KernelDisplay(pKernelDisplay, pRmHalspecOwner); void __nvoc_init_funcTable_DisplayInstanceMemory(DisplayInstanceMemory *, RmHalspecOwner *); + void __nvoc_init_dataField_DisplayInstanceMemory(DisplayInstanceMemory *, RmHalspecOwner *); __nvoc_init_funcTable_DisplayInstanceMemory(KERNEL_DISPLAY_GET_INST_MEM(pKernelDisplay), pRmHalspecOwner); + __nvoc_init_dataField_DisplayInstanceMemory(KERNEL_DISPLAY_GET_INST_MEM(pKernelDisplay), + pRmHalspecOwner); void __nvoc_init_funcTable_KernelHead(KernelHead *, RmHalspecOwner *); + void __nvoc_init_dataField_KernelHead(KernelHead *, RmHalspecOwner *); NvU32 headIdx; for (headIdx = 0; headIdx < OBJ_MAX_HEADS; headIdx++) { __nvoc_init_funcTable_KernelHead(KDISP_GET_HEAD(pKernelDisplay, headIdx), pRmHalspecOwner); + __nvoc_init_dataField_KernelHead(KDISP_GET_HEAD(pKernelDisplay, headIdx), + pRmHalspecOwner); } return NV_OK; @@ -4936,12 +5097,15 @@ gpuReadBusConfigCycle_IMPL NvU32 *pData ) { - NvU32 domain = gpuGetDomain(pGpu); - NvU8 bus = gpuGetBus(pGpu); - NvU8 device = gpuGetDevice(pGpu); - NvU8 function = 0; + NvU32 domain = gpuGetDomain(pGpu); + NvU8 bus = gpuGetBus(pGpu); + NvU8 device = gpuGetDevice(pGpu); + NvU8 function = 0; + NvBool bIsCCFeatureEnabled = NV_FALSE; + + bIsCCFeatureEnabled = gpuIsCCFeatureEnabled(pGpu); - if (IS_PASSTHRU(pGpu)) + if (IS_PASSTHRU(pGpu) && !bIsCCFeatureEnabled) { gpuReadVgpuConfigReg_HAL(pGpu, index, pData); } @@ -5114,3 +5278,143 @@ gpuSetGC6SBIOSCapabilities_IMPL(OBJGPU *pGpu) return NV_OK; } +NV_STATUS gpuSimEscapeWrite(OBJGPU *pGpu, const char *path, NvU32 Index, NvU32 Size, NvU32 Value) +{ + NV_ASSERT_OR_RETURN(Size <= (sizeof Value), NV_ERR_INVALID_ARGUMENT); + + if (pGpu->bUseRpcSimEscapes) + { + return RmRpcSimEscapeWrite(pGpu, path, Index, Size, Value); + } + return osSimEscapeWrite(pGpu, path, Index, Size, Value); +} + +NV_STATUS gpuSimEscapeWriteBuffer(OBJGPU *pGpu, const char *path, NvU32 Index, NvU32 Size, void* pBuffer) +{ + return osSimEscapeWriteBuffer(pGpu, path, Index, Size, pBuffer); +} + +NV_STATUS gpuSimEscapeRead(OBJGPU *pGpu, const char *path, NvU32 Index, NvU32 Size, NvU32 *Value) +{ + NV_ASSERT_OR_RETURN(Size <= (sizeof *Value), NV_ERR_INVALID_ARGUMENT); + + // + // Zero-initialize because the functions below don't fill in entire Value + // for Size < 4 + // + NvU32 readValue = 0; + NV_STATUS status; + + if (pGpu->bUseRpcSimEscapes) + { + status = RmRpcSimEscapeRead(pGpu, path, Index, Size, &readValue); + } + else + { + status = osSimEscapeRead(pGpu, path, Index, Size, &readValue); + } + + *Value = readValue; + return status; +} + +NV_STATUS gpuSimEscapeReadBuffer(OBJGPU *pGpu, const char *path, NvU32 Index, NvU32 Size, void* pBuffer) +{ + return osSimEscapeReadBuffer(pGpu, path, Index, Size, pBuffer); +} + +// +// Only supported with Windows, Debug or Develop driver, or with Release drivers instrumented builds. +// Instrumented build: add "RMCFG_FEATURE_ENABLED=RMTEST" to nvmake command line +// Todo: add OpenRM/GSP support +// +#if defined(GPU_LOAD_FAILURE_TEST_SUPPORTED) +NV_STATUS +gpuLoadFailurePathTest_IMPL +( + OBJGPU *pGpu, + NvU32 engStage, + NvU32 engDescIdx, + NvBool bStopTest +) +{ + NV_STATUS rmStatus = NV_OK; + + // Check that test is enabled and in the stating stage + if (!FLD_TEST_DRF(_REG_STR, _GPU_LOAD_FAILURE_TEST, _STATUS, _START, pGpu->loadFailurePathTestControl)) + { + return NV_OK; + } + + // Not supported for suspend/resume + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_PM_RESUME_CODEPATH)) + { + return NV_OK; + } + + // Stop the test + if (bStopTest) + { + pGpu->loadFailurePathTestControl = FLD_SET_DRF(_REG_STR, _GPU_LOAD_FAILURE_TEST, _STATUS, _FINISHED, pGpu->loadFailurePathTestControl); + goto writeRegistryAndExit; + } + + NvU32 regEngStage = DRF_VAL(_REG_STR, _GPU_LOAD_FAILURE_TEST, _STAGE, pGpu->loadFailurePathTestControl); + NvU32 regEngDescIdx = DRF_VAL(_REG_STR, _GPU_LOAD_FAILURE_TEST, _ENGINEINDEX, pGpu->loadFailurePathTestControl); + + // Check that we are not yet in the targeted stage (preinit, init, preload, load or postload) + if (engStage < regEngStage) + { + return NV_OK; + } + + // Check that we are in the next stage + if (engStage > regEngStage) + { + // Reset engine index to 0 and move to next index + regEngDescIdx = 0; + regEngStage = engStage; + } + + // Check that the engine is the next one to be tested + if (engDescIdx < regEngDescIdx) + { + return NV_OK; + } + + // At this point we fail the engine + rmStatus = NV_ERR_GENERIC; + + // Update registry key for next step + pGpu->loadFailurePathTestControl = FLD_SET_DRF(_REG_STR, _GPU_LOAD_FAILURE_TEST, _STATUS, _RUNNING, pGpu->loadFailurePathTestControl); + pGpu->loadFailurePathTestControl = FLD_SET_DRF_NUM(_REG_STR, _GPU_LOAD_FAILURE_TEST, _STAGE, regEngStage, pGpu->loadFailurePathTestControl); + pGpu->loadFailurePathTestControl = FLD_SET_DRF_NUM(_REG_STR, _GPU_LOAD_FAILURE_TEST, _ENGINEINDEX, regEngDescIdx + 1, pGpu->loadFailurePathTestControl); + +writeRegistryAndExit: + osWriteRegistryDword(pGpu, + NV_REG_STR_GPU_LOAD_FAILURE_TEST, + pGpu->loadFailurePathTestControl); + + switch (engStage) + { + case NV_REG_STR_GPU_LOAD_FAILURE_TEST_STAGE_PREINIT: + NV_PRINTF(LEVEL_ERROR, "Failing GPU PreInit for Engine ID 0x%x (%d)\n", engDescIdx, engDescIdx); + break; + case NV_REG_STR_GPU_LOAD_FAILURE_TEST_STAGE_INIT: + NV_PRINTF(LEVEL_ERROR, "Failing GPU Init for Engine ID 0x%x (%d)\n", engDescIdx, engDescIdx); + break; + case NV_REG_STR_GPU_LOAD_FAILURE_TEST_STAGE_PRELOAD: + NV_PRINTF(LEVEL_ERROR, "Failing GPU PreLoad for Engine ID 0x%x (%d)\n", engDescIdx, engDescIdx); + break; + case NV_REG_STR_GPU_LOAD_FAILURE_TEST_STAGE_LOAD: + NV_PRINTF(LEVEL_ERROR, "Failing GPU Load for Engine ID 0x%x (%d)\n", engDescIdx, engDescIdx); + break; + case NV_REG_STR_GPU_LOAD_FAILURE_TEST_STAGE_POSTLOAD: + NV_PRINTF(LEVEL_ERROR, "Failing GPU PostLoad for Engine ID 0x%x (%d)\n", engDescIdx, engDescIdx); + break; + } + + + return rmStatus; +} +#endif diff --git a/src/nvidia/src/kernel/gpu/gpu_engine_type.c b/src/nvidia/src/kernel/gpu/gpu_engine_type.c index 663766543c..399b195e0c 100644 --- a/src/nvidia/src/kernel/gpu/gpu_engine_type.c +++ b/src/nvidia/src/kernel/gpu/gpu_engine_type.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -26,7 +26,6 @@ * @brief ENGINE_TYPE controls */ - #include "kernel/gpu/gpu.h" #include "kernel/gpu/nvbitmask.h" @@ -105,7 +104,7 @@ RM_ENGINE_TYPE gpuGetRmEngineType_IMPL(NvU32 index) case NV2080_ENGINE_TYPE_NVJPEG5: return RM_ENGINE_TYPE_NVJPEG5; case NV2080_ENGINE_TYPE_NVJPEG6: return RM_ENGINE_TYPE_NVJPEG6; case NV2080_ENGINE_TYPE_NVJPEG7: return RM_ENGINE_TYPE_NVJPEG7; - case NV2080_ENGINE_TYPE_OFA: return RM_ENGINE_TYPE_OFA; + case NV2080_ENGINE_TYPE_OFA0: return RM_ENGINE_TYPE_OFA0; default: break; } @@ -179,7 +178,7 @@ NvU32 gpuGetNv2080EngineType_IMPL(RM_ENGINE_TYPE index) case RM_ENGINE_TYPE_NVJPEG5: return NV2080_ENGINE_TYPE_NVJPEG5; case RM_ENGINE_TYPE_NVJPEG6: return NV2080_ENGINE_TYPE_NVJPEG6; case RM_ENGINE_TYPE_NVJPEG7: return NV2080_ENGINE_TYPE_NVJPEG7; - case RM_ENGINE_TYPE_OFA: return NV2080_ENGINE_TYPE_OFA; + case RM_ENGINE_TYPE_OFA0: return NV2080_ENGINE_TYPE_OFA0; default: break; } diff --git a/src/nvidia/src/kernel/gpu/gpu_fabric_probe.c b/src/nvidia/src/kernel/gpu/gpu_fabric_probe.c index 4feb835d35..970df3296e 100644 --- a/src/nvidia/src/kernel/gpu/gpu_fabric_probe.c +++ b/src/nvidia/src/kernel/gpu/gpu_fabric_probe.c @@ -29,6 +29,7 @@ #include "gpu/gpu.h" #include "os/os.h" +#include "nvport/atomic.h" #include "utils/nvprintf.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" #include "gpu/gpu_fabric_probe.h" @@ -39,7 +40,7 @@ // Structure to hold gpu probe information typedef struct GPU_FABRIC_PROBE_INFO_KERNEL { - NvBool bProbeRespRcvd; + volatile NvU32 probeRespRcvd; NvU8 bwMode; OBJGPU *pGpu; @@ -59,9 +60,6 @@ _gpuFabricProbeFullSanityCheck return NV_ERR_NOT_SUPPORTED; } - LOCK_ASSERT_AND_RETURN(rmDeviceGpuLockIsOwner( - gpuGetInstance(pGpuFabricProbeInfoKernel->pGpu))); - if (!gpuFabricProbeIsReceived(pGpuFabricProbeInfoKernel)) { return NV_ERR_NOT_READY; @@ -69,6 +67,9 @@ _gpuFabricProbeFullSanityCheck if (!gpuFabricProbeIsSuccess(pGpuFabricProbeInfoKernel)) { + NV_PRINTF(LEVEL_ERROR, "Fabric Probe failed: 0x%x\n", + pGpuFabricProbeInfoKernel->probeResponseMsg.msgHdr.status); + return pGpuFabricProbeInfoKernel->probeResponseMsg.msgHdr.status; } @@ -86,7 +87,7 @@ gpuFabricProbeGetGpuFabricHandle status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfoKernel); - NV_CHECK_OR_RETURN(LEVEL_ERROR, status == NV_OK, status); + NV_CHECK_OR_RETURN(LEVEL_SILENT, status == NV_OK, status); *pHandle = pGpuFabricProbeInfoKernel->probeResponseMsg.probeRsp.gpuHandle; @@ -104,7 +105,7 @@ gpuFabricProbeGetGfId status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfoKernel); - NV_CHECK_OR_RETURN(LEVEL_ERROR, status == NV_OK, status); + NV_CHECK_OR_RETURN(LEVEL_SILENT, status == NV_OK, status); *pGfId = pGpuFabricProbeInfoKernel->probeResponseMsg.probeRsp.gfId; @@ -122,7 +123,7 @@ gpuFabricProbeGetfmCaps status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfoKernel); - NV_CHECK_OR_RETURN(LEVEL_ERROR, status == NV_OK, status); + NV_CHECK_OR_RETURN(LEVEL_SILENT, status == NV_OK, status); *pFmCaps = pGpuFabricProbeInfoKernel->probeResponseMsg.probeRsp.fmCaps; @@ -140,7 +141,7 @@ gpuFabricProbeGetClusterUuid status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfoKernel); - NV_CHECK_OR_RETURN(LEVEL_ERROR, status == NV_OK, status); + NV_CHECK_OR_RETURN(LEVEL_SILENT, status == NV_OK, status); portMemCopy(&pClusterUuid->uuid[0], sizeof(pClusterUuid->uuid), @@ -161,7 +162,7 @@ gpuFabricProbeGetFabricPartitionId status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfoKernel); - NV_CHECK_OR_RETURN(LEVEL_ERROR, status == NV_OK, status); + NV_CHECK_OR_RETURN(LEVEL_SILENT, status == NV_OK, status); *pFabricPartitionId = pGpuFabricProbeInfoKernel->probeResponseMsg.probeRsp.fabricPartitionId; @@ -179,7 +180,7 @@ gpuFabricProbeGetGpaAddress status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfoKernel); - NV_CHECK_OR_RETURN(LEVEL_ERROR, status == NV_OK, status); + NV_CHECK_OR_RETURN(LEVEL_SILENT, status == NV_OK, status); *pGpaAddress = pGpuFabricProbeInfoKernel->probeResponseMsg.probeRsp.gpaAddress; @@ -197,7 +198,7 @@ gpuFabricProbeGetGpaAddressRange status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfoKernel); - NV_CHECK_OR_RETURN(LEVEL_ERROR, status == NV_OK, status); + NV_CHECK_OR_RETURN(LEVEL_SILENT, status == NV_OK, status); *pGpaAddressRange = pGpuFabricProbeInfoKernel->probeResponseMsg.probeRsp.gpaAddressRange; @@ -215,7 +216,7 @@ gpuFabricProbeGetFlaAddress status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfoKernel); - NV_CHECK_OR_RETURN(LEVEL_ERROR, status == NV_OK, status); + NV_CHECK_OR_RETURN(LEVEL_SILENT, status == NV_OK, status); *pFlaAddress = pGpuFabricProbeInfoKernel->probeResponseMsg.probeRsp.flaAddress; @@ -233,7 +234,7 @@ gpuFabricProbeGetFlaAddressRange status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfoKernel); - NV_CHECK_OR_RETURN(LEVEL_ERROR, status == NV_OK, status); + NV_CHECK_OR_RETURN(LEVEL_SILENT, status == NV_OK, status); *pFlaAddressRange = pGpuFabricProbeInfoKernel->probeResponseMsg.probeRsp.flaAddressRange; @@ -275,6 +276,24 @@ gpuFabricProbeGetNumProbeReqs return NV_OK; } +NV_STATUS +gpuFabricProbeGetFabricCliqueId +( + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel, + NvU32 *pFabricCliqueId +) +{ + NV_STATUS status; + + status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfoKernel); + + NV_CHECK_OR_RETURN(LEVEL_SILENT, status == NV_OK, status); + + *pFabricCliqueId = pGpuFabricProbeInfoKernel->probeResponseMsg.probeRsp.cliqueId; + + return NV_OK; +} + NvBool gpuFabricProbeIsReceived ( @@ -286,11 +305,7 @@ gpuFabricProbeIsReceived return NV_FALSE; } - LOCK_ASSERT_AND_RETURN_BOOL(rmDeviceGpuLockIsOwner( - gpuGetInstance(pGpuFabricProbeInfoKernel->pGpu)), - NV_FALSE); - - return pGpuFabricProbeInfoKernel->bProbeRespRcvd; + return !!portAtomicOrU32(&pGpuFabricProbeInfoKernel->probeRespRcvd, 0); } NvBool @@ -307,10 +322,6 @@ gpuFabricProbeIsSuccess return NV_FALSE; } - LOCK_ASSERT_AND_RETURN_BOOL(rmDeviceGpuLockIsOwner(gpuGetInstance( - pGpuFabricProbeInfoKernel->pGpu)), - NV_FALSE); - pProbeResponseMsg = &pGpuFabricProbeInfoKernel->probeResponseMsg; pProbeRespMsgHdr = &pProbeResponseMsg->msgHdr; @@ -328,9 +339,6 @@ gpuFabricProbeGetFmStatus return NV_ERR_NOT_SUPPORTED; } - LOCK_ASSERT_AND_RETURN(rmDeviceGpuLockIsOwner( - gpuGetInstance(pGpuFabricProbeInfoKernel->pGpu))); - return pGpuFabricProbeInfoKernel->probeResponseMsg.msgHdr.status; } @@ -433,11 +441,12 @@ _gpuFabricProbeReceiveKernel pProbeRespMsg, sizeof(*pProbeRespMsg)); + portAtomicMemoryFenceFull(); // // TODO - Add additional check with versioning to continue with the // timer and send lower version requests // - pGpuFabricProbeInfoKernel->bProbeRespRcvd = NV_TRUE; + portAtomicSetU32(&pGpuFabricProbeInfoKernel->probeRespRcvd, 1); status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfoKernel); NV_CHECK_OR_RETURN(LEVEL_ERROR, status == NV_OK, status); @@ -645,7 +654,7 @@ _gpuFabricProbeInvalidate KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); FABRIC_VASPACE *pFabricVAS = dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE); - pGpuFabricProbeInfoKernel->bProbeRespRcvd = NV_FALSE; + portAtomicSetU32(&pGpuFabricProbeInfoKernel->probeRespRcvd, 0); if (pKernelNvlink != NULL) knvlinkClearUniqueFabricBaseAddress_HAL(pGpu, pKernelNvlink); @@ -798,8 +807,11 @@ gpuFabricProbeGetlinkMaskToBeReduced NV_STATUS status; status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfoKernel); - NV_CHECK_OR_RETURN(LEVEL_ERROR, status == NV_OK, status); - *linkMaskToBeReduced = pGpuFabricProbeInfoKernel->probeResponseMsg.probeRsp.linkMaskToBeReduced; + NV_CHECK_OR_RETURN(LEVEL_SILENT, status == NV_OK, status); + + *linkMaskToBeReduced = + pGpuFabricProbeInfoKernel->probeResponseMsg.probeRsp.linkMaskToBeReduced; + return NV_OK; } diff --git a/src/nvidia/src/kernel/gpu/gpu_gspclient.c b/src/nvidia/src/kernel/gpu/gpu_gspclient.c index 1a96ee0e71..85c7633dae 100644 --- a/src/nvidia/src/kernel/gpu/gpu_gspclient.c +++ b/src/nvidia/src/kernel/gpu/gpu_gspclient.c @@ -26,9 +26,6 @@ * @brief GSP Client (CPU RM) specific GPU routines reside in this file. */ -// FIXME XXX -#define NVOC_KERNEL_GRAPHICS_MANAGER_H_PRIVATE_ACCESS_ALLOWED - #include "core/core.h" #include "gpu/gpu.h" #include "ctrl/ctrl2080.h" @@ -310,8 +307,8 @@ gpuGetLitterValues_FWCLIENT const NV2080_CTRL_INTERNAL_STATIC_GR_INFO *pGrInfo; NvU32 i; - NV_ASSERT_OR_RETURN(pKernelGraphicsManager->legacyKgraphicsStaticInfo.bInitialized, 0); - pGrInfo = pKernelGraphicsManager->legacyKgraphicsStaticInfo.pGrInfo; + NV_ASSERT_OR_RETURN(kgrmgrGetLegacyKGraphicsStaticInfo(pGpu, pKernelGraphicsManager)->bInitialized, 0); + pGrInfo = kgrmgrGetLegacyKGraphicsStaticInfo(pGpu, pKernelGraphicsManager)->pGrInfo; NV_ASSERT_OR_RETURN(pGrInfo != NULL, 0); for (i = 0; i < NV_ARRAY_ELEMENTS(pGrInfo->infoList); i++) diff --git a/src/nvidia/src/kernel/gpu/gpu_registry.c b/src/nvidia/src/kernel/gpu/gpu_registry.c index 09adc32d06..0937c77f83 100644 --- a/src/nvidia/src/kernel/gpu/gpu_registry.c +++ b/src/nvidia/src/kernel/gpu/gpu_registry.c @@ -128,13 +128,12 @@ gpuInitRegistryOverrides_KERNEL } } + NV_PRINTF(LEVEL_INFO, "SRIOV status[%d].\n", pGpu->bSriovEnabled); } if (pGpu->bSriovEnabled && (IS_GSP_CLIENT(pGpu) || RMCFG_FEATURE_PLATFORM_GSP)) { - { - pGpu->bVgpuGspPluginOffloadEnabled = NV_TRUE; - } + pGpu->bVgpuGspPluginOffloadEnabled = NV_TRUE; } if (osReadRegistryDword(pGpu, NV_REG_STR_RM_CLIENT_RM_ALLOCATED_CTX_BUFFER, &data32) == NV_OK) @@ -148,6 +147,14 @@ gpuInitRegistryOverrides_KERNEL { pGpu->bClientRmAllocatedCtxBuffer = NV_TRUE; } + else if (pGpu->getProperty(pGpu, PDB_PROP_GPU_ZERO_FB) && + (pGpu->bSriovEnabled || IS_VIRTUAL_WITH_SRIOV(pGpu))) + { + // For zero-FB config + SRIOV + pGpu->bClientRmAllocatedCtxBuffer = NV_TRUE; + NV_PRINTF(LEVEL_INFO, + "Enabled Client RM managed context buffer for zero-FB + SRIOV.\n"); + } else if ( RMCFG_FEATURE_MODS_FEATURES || !(pGpu->bSriovEnabled || IS_VIRTUAL(pGpu)) ) { // TODO : enable this feature on mods @@ -185,6 +192,18 @@ gpuInitRegistryOverrides_KERNEL pGpu->bBf3WarBug4040336Enabled = (data32 == NV_REG_STR_RM_DMA_ADJUST_PEER_MMIO_BF3_ENABLE); } + if (osReadRegistryDword(pGpu, NV_REG_STR_RM_ITERATIVE_MMU_WALKER, &data32) == NV_OK) + { + pGpu->bIterativeMmuWalker = (data32 == NV_REG_STR_RM_ITERATIVE_MMU_WALKER_ENABLED); + } + +#if defined(GPU_LOAD_FAILURE_TEST_SUPPORTED) + if (osReadRegistryDword(pGpu, NV_REG_STR_GPU_LOAD_FAILURE_TEST, &data32) == NV_OK) + { + pGpu->loadFailurePathTestControl = data32; + } +#endif + return NV_OK; } diff --git a/src/nvidia/src/kernel/gpu/gpu_resource.c b/src/nvidia/src/kernel/gpu/gpu_resource.c index dc0f358376..7244e67452 100644 --- a/src/nvidia/src/kernel/gpu/gpu_resource.c +++ b/src/nvidia/src/kernel/gpu/gpu_resource.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2016-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2016-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -250,11 +250,27 @@ gpuresShareCallback_IMPL KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); MIG_INSTANCE_REF refClient; MIG_INSTANCE_REF refResource; + RsResourceRef *pInvokingDeviceRef; + Device *pInvokingDevice; + + NV_ASSERT_OR_RETURN(pParentRef != NULL, NV_ERR_INVALID_ARGUMENT); + + if (pParentRef->internalClassId == classId(Device)) + { + pInvokingDeviceRef = pParentRef; + } + else + { + NV_ASSERT_OK_OR_RETURN( + refFindAncestorOfType(pParentRef, classId(Device), &pInvokingDeviceRef)); + } + + pInvokingDevice = dynamicCast(pInvokingDeviceRef->pResource, Device); if (bMIGInUse && - (kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, pInvokingClient->hClient, + (kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pInvokingDevice, &refClient) == NV_OK) && - (kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, RES_GET_CLIENT_HANDLE(pGpuResource), + (kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, GPU_RES_GET_DEVICE(pGpuResource), &refResource) == NV_OK)) { // Ignore execution partition differences when sharing diff --git a/src/nvidia/src/kernel/gpu/gpu_rmapi.c b/src/nvidia/src/kernel/gpu/gpu_rmapi.c index f61b55353d..aa00aa6108 100644 --- a/src/nvidia/src/kernel/gpu/gpu_rmapi.c +++ b/src/nvidia/src/kernel/gpu/gpu_rmapi.c @@ -310,7 +310,7 @@ _gpuFilterSubDeviceEventInfo ) { MIG_INSTANCE_REF ref; - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice->pDevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); NvU32 engineIdx; RM_ENGINE_TYPE rmEngineType; RM_ENGINE_TYPE localRmEngineType; @@ -325,10 +325,12 @@ _gpuFilterSubDeviceEventInfo if (!IS_MIG_IN_USE(pGpu)) return NV_OK; - // Retrieve instance reference for this client - status = kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, &ref); + // Retrieve instance reference for this Device + status = kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, &ref); if (status != NV_OK) { + NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + // // Privileged or has the mig monitor capability, unsubscribed clients // may be notified with no filtering, but other unsubscribed clients @@ -719,17 +721,35 @@ gpuGetProcWithObject_IMPL if ((pKernelMIGManager != NULL) && (pRef->pKernelMIGGpuInstance != NULL)) { MIG_INSTANCE_REF clientRef = kmigmgrMakeNoMIGReference(); - if ((kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, - &clientRef) != NV_OK)) - continue; + RS_ITERATOR it = clientRefIter(pRsClient, NULL, classId(Device), RS_ITERATE_CHILDREN, NV_TRUE); + NvBool bClientHasMatchingInstance = NV_FALSE; - // Check partition subscription against requested partition - if ((pRef->pKernelMIGGpuInstance != clientRef.pKernelMIGGpuInstance) || - ((pRef->pMIGComputeInstance != NULL) && - (pRef->pMIGComputeInstance != clientRef.pMIGComputeInstance))) + // Find matching MIG instance in devices under this Client + while (clientRefIterNext(pRsClient, &it)) { - continue; + pDevice = dynamicCast(it.pResourceRef->pResource, Device); + + if ((GPU_RES_GET_GPU(pDevice) != pGpu) || + (kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, + &clientRef) != NV_OK)) + { + continue; + } + + // Check partition subscription against requested partition + if ((pRef->pKernelMIGGpuInstance != clientRef.pKernelMIGGpuInstance) || + ((pRef->pMIGComputeInstance != NULL) && + (pRef->pMIGComputeInstance != clientRef.pMIGComputeInstance))) + { + continue; + } + + bClientHasMatchingInstance = NV_TRUE; + break; } + + if (!bClientHasMatchingInstance) + continue; } } @@ -966,61 +986,70 @@ gpuFindClientInfoWithPidIterator_IMPL ((subPid != 0) && (pClient->ProcID == pid) && (pClient->SubProcessID == subPid))) { RS_PRIV_LEVEL privLevel = rmclientGetCachedPrivilege(pClient); + RS_ITERATOR it; + hClient = pRsClient->hClient; // Skip reporting of kernel mode and internal RM clients if ((privLevel >= RS_PRIV_LEVEL_KERNEL) && rmclientIsAdmin(pClient, privLevel)) continue; - if (deviceGetByGpu(pRsClient, pGpu, NV_TRUE, &pDevice) != NV_OK) - continue; + it = clientRefIter(pRsClient, NULL, classId(Device), RS_ITERATE_CHILDREN, NV_TRUE); - if (IS_MIG_IN_USE(pGpu)) + while (clientRefIterNext(pRsClient, &it)) { - KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); - MIG_INSTANCE_REF clientRef = kmigmgrMakeNoMIGReference(); + pDevice = dynamicCast(it.pResourceRef->pResource, Device); - if (kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, - &clientRef) != NV_OK) - { + if (GPU_RES_GET_GPU(pDevice) != pGpu) continue; - } - gpuInstanceId = clientRef.pKernelMIGGpuInstance->swizzId; - if (clientRef.pMIGComputeInstance != NULL) + if (IS_MIG_IN_USE(pGpu)) { - computeInstanceId = clientRef.pMIGComputeInstance->id; - } + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + MIG_INSTANCE_REF clientRef = kmigmgrMakeNoMIGReference(); - // Check instance subscription against requested instance reference - if (!bGlobalInfo && - !kmigmgrAreMIGReferencesSame(pRef, &clientRef)) - { - continue; - } + if (kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, + &clientRef) != NV_OK) + { + continue; + } - if (kmigmgrIsMIGReferenceValid(pRef)) - { - pHeap = pRef->pKernelMIGGpuInstance->pMemoryPartitionHeap; + gpuInstanceId = clientRef.pKernelMIGGpuInstance->swizzId; + if (clientRef.pMIGComputeInstance != NULL) + { + computeInstanceId = clientRef.pMIGComputeInstance->id; + } + + // Check instance subscription against requested instance reference + if (!bGlobalInfo && + !kmigmgrAreMIGReferencesSame(pRef, &clientRef)) + { + continue; + } + + if (kmigmgrIsMIGReferenceValid(pRef)) + { + pHeap = pRef->pKernelMIGGpuInstance->pMemoryPartitionHeap; + } } - } - hDevice = RES_GET_HANDLE(pDevice); + hDevice = RES_GET_HANDLE(pDevice); - switch (internalClassId) - { - case (classId(Memory)): + switch (internalClassId) { - // TODO - - // When single process spanning across multiple GI or CI by creating multiple - // clients, RM needs to provide the unique list being used by the client - _gpuCollectMemInfo(hClient, hDevice, pHeap, - &pData->vidMemUsage, ((subPid != 0) ? NV_TRUE : NV_FALSE), - bGlobalInfo); - break; + case (classId(Memory)): + { + // TODO - + // When single process spanning across multiple GI or CI by creating multiple + // clients, RM needs to provide the unique list being used by the client + _gpuCollectMemInfo(hClient, hDevice, pHeap, + &pData->vidMemUsage, ((subPid != 0) ? NV_TRUE : NV_FALSE), + bGlobalInfo); + break; + } + default: + return NV_ERR_INVALID_ARGUMENT; } - default: - return NV_ERR_INVALID_ARGUMENT; } } } diff --git a/src/nvidia/src/kernel/gpu/gpu_suspend.c b/src/nvidia/src/kernel/gpu/gpu_suspend.c index f6088ac44b..33203cecdb 100644 --- a/src/nvidia/src/kernel/gpu/gpu_suspend.c +++ b/src/nvidia/src/kernel/gpu/gpu_suspend.c @@ -237,6 +237,7 @@ gpuPowerManagementResume(OBJGPU *pGpu, NvU32 oldLevel, NvU32 flags) goto done; } } + } // This is a no-op in CPU-RM diff --git a/src/nvidia/src/kernel/gpu/gpu_user_shared_data.c b/src/nvidia/src/kernel/gpu/gpu_user_shared_data.c index e478178698..475da9af1d 100644 --- a/src/nvidia/src/kernel/gpu/gpu_user_shared_data.c +++ b/src/nvidia/src/kernel/gpu/gpu_user_shared_data.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -23,13 +23,19 @@ #include "gpu/gpu_user_shared_data.h" #include "gpu/gpu.h" -#include "gpu/subdevice/subdevice.h" +#include "gpu/device/device.h" #include "os/os.h" #include "rmapi/client.h" #include "rmapi/rmapi.h" +#include "rmapi/rs_utils.h" #include "class/cl00de.h" #include "class/cl003e.h" // NV01_MEMORY_SYSTEM +#include "gpu/mig_mgr/kernel_mig_manager.h" + +static NV_STATUS _gpushareddataInitGsp(GpuUserSharedData *pData, NvBool bInit); +static NV_STATUS _gpushareddataRequestDataPoll(GpuUserSharedData *pData, NvU64 polledDataMask); + NV_STATUS gpushareddataConstruct_IMPL ( @@ -40,10 +46,16 @@ gpushareddataConstruct_IMPL { NV_STATUS status = NV_OK; Memory *pMemory = staticCast(pData, Memory); + OBJGPU *pGpu = pMemory->pGpu; // pGpu is initialized in the Memory class constructor + MEMORY_DESCRIPTOR **ppMemDesc = &(pGpu->userSharedData.pMemDesc); + NV00DE_ALLOC_PARAMETERS *pAllocParams = (NV00DE_ALLOC_PARAMETERS*)(pParams->pAllocParams); + + NV_ASSERT_OR_RETURN(!RMCFG_FEATURE_PLATFORM_GSP, NV_ERR_NOT_SUPPORTED); - // pGpu is initialied in the Memory class constructor - OBJGPU *pGpu = pMemory->pGpu; - MEMORY_DESCRIPTOR **ppMemDesc = &(pGpu->userSharedData.pMemDesc); + if (IS_VIRTUAL(pGpu)) + { + return NV_ERR_NOT_SUPPORTED; + } if (RS_IS_COPY_CTOR(pParams)) { @@ -52,11 +64,19 @@ gpushareddataConstruct_IMPL if (*ppMemDesc == NULL) { + OBJSYS *pSys = SYS_GET_INSTANCE(); + + // RUSD is not yet supported when CPU CC is enabled. See bug 4148522. + if ((sysGetStaticConfig(pSys))->bOsCCEnabled) + return NV_ERR_NOT_SUPPORTED; + // Create a kernel-side mapping for writing the data if one is not already present NV_ASSERT_OK_OR_RETURN(memdescCreate(ppMemDesc, pGpu, sizeof(NV00DE_SHARED_DATA), 0, NV_TRUE, - ADDR_SYSMEM, NV_MEMORY_CACHED, MEMDESC_FLAGS_USER_READ_ONLY)); + ADDR_SYSMEM, NV_MEMORY_CACHED, MEMDESC_FLAGS_USER_READ_ONLY)); - NV_ASSERT_OK_OR_GOTO(status, memdescAlloc(*ppMemDesc), err); + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_35, + (*ppMemDesc)); + NV_ASSERT_OK_OR_GOTO(status, status, err); NV_ASSERT_OK_OR_GOTO(status, @@ -64,27 +84,70 @@ gpushareddataConstruct_IMPL NV_TRUE, NV_PROTECT_READ_WRITE, &pGpu->userSharedData.pMapBuffer, &pGpu->userSharedData.pMapBufferPriv), - err); + err); portMemSet(pGpu->userSharedData.pMapBuffer, 0, sizeof(NV00DE_SHARED_DATA)); // Initial write from cached data - gpuUpdateUserSharedData_KERNEL(pGpu); + gpuUpdateUserSharedData(pGpu); + + if (IS_GSP_CLIENT(pGpu)) + { + // Init system memdesc on GSP + _gpushareddataInitGsp(pData, NV_TRUE); + } + } + + if (pAllocParams->polledDataMask != 0U) + { + NV_ASSERT_OK_OR_RETURN(_gpushareddataRequestDataPoll(pData, pAllocParams->polledDataMask)); } NV_ASSERT_OK_OR_RETURN(memConstructCommon(pMemory, NV01_MEMORY_SYSTEM, 0, *ppMemDesc, 0, NULL, 0, 0, 0, 0, NVOS32_MEM_TAG_NONE, NULL)); memdescAddRef(pGpu->userSharedData.pMemDesc); + return NV_OK; -err: +err: // Only for global memdesc construct fail cleanup memdescFree(*ppMemDesc); memdescDestroy(*ppMemDesc); *ppMemDesc = NULL; return status; } +void +gpushareddataDestruct_IMPL(GpuUserSharedData *pData) +{ + Memory *pMemory = staticCast(pData, Memory); + OBJGPU *pGpu = pMemory->pGpu; + + NV_ASSERT_OR_RETURN_VOID(!RMCFG_FEATURE_PLATFORM_GSP); + + if (!pMemory->bConstructed || (pMemory->pMemDesc == NULL)) + { + return; + } + + _gpushareddataRequestDataPoll(pData, 0U); + + memdescRemoveRef(pGpu->userSharedData.pMemDesc); + memDestructCommon(pMemory); + + if (pGpu->userSharedData.pMemDesc->RefCount <= 1) + { + NV_ASSERT(pGpu->userSharedData.pMemDesc->RefCount == 1); + + if (IS_GSP_CLIENT(pGpu)) + { + _gpushareddataInitGsp(pData, NV_FALSE); + } + + gpushareddataDestroy(pGpu); + } +} + NvBool gpushareddataCanCopy_IMPL(GpuUserSharedData *pData) { @@ -98,14 +161,14 @@ NV00DE_SHARED_DATA * gpushareddataWriteStart(OBJGPU *pGpu) void gpushareddataWriteFinish(OBJGPU *pGpu) { - gpuUpdateUserSharedData_HAL(pGpu); + gpuUpdateUserSharedData(pGpu); } -void gpuUpdateUserSharedData_KERNEL(OBJGPU *pGpu) +void gpuUpdateUserSharedData_IMPL(OBJGPU *pGpu) { NV00DE_SHARED_DATA *pSharedData = (NV00DE_SHARED_DATA*)(pGpu->userSharedData.pMapBuffer); const NvU32 data_offset = sizeof(pSharedData->seq); - const NvU32 data_size = sizeof(NV00DE_SHARED_DATA) - data_offset; + const NvU32 data_size = NV_OFFSETOF(NV00DE_SHARED_DATA, clkPublicDomainInfos) - data_offset; if (pSharedData == NULL) return; @@ -114,9 +177,122 @@ void gpuUpdateUserSharedData_KERNEL(OBJGPU *pGpu) portAtomicMemoryFenceStore(); // Push cached data to mapped buffer - portMemCopy((NvU8*)pSharedData + data_offset, data_size, - (NvU8*)&pGpu->userSharedData.data + data_offset, data_size); + if (IS_MIG_ENABLED(pGpu)) + { + // Global Bar1 data is inaccurate if MIG is enabled, invalidate + portMemSet((NvU8*)pSharedData + data_offset, 0, data_size); + } + else + { + portMemCopy((NvU8*)pSharedData + data_offset, data_size, + (NvU8*)&pGpu->userSharedData.data + data_offset, data_size); + } portAtomicMemoryFenceStore(); portAtomicIncrementU32(&pSharedData->seq); } + +static NV_STATUS +_gpushareddataInitGsp +( + GpuUserSharedData *pData, + NvBool bInit +) +{ + NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS params = { 0 }; + OBJGPU *pGpu = staticCast(pData, Memory)->pGpu; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + if (bInit) + params.physAddr = memdescGetPhysAddr(pGpu->userSharedData.pMemDesc, AT_GPU, 0); + else + params.physAddr = 0ULL; + + // Link up Memdesc on GSP-side + NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_INIT_USER_SHARED_DATA, + ¶ms, sizeof(params))); + return NV_OK; +} + +void +gpushareddataDestroy +( + OBJGPU *pGpu +) +{ + GpuSharedDataMap *pData = &pGpu->userSharedData; + + memdescUnmap(pData->pMemDesc, NV_TRUE, 0, + pData->pMapBuffer, + pData->pMapBufferPriv); + memdescFree(pData->pMemDesc); + memdescDestroy(pData->pMemDesc); + pData->pMemDesc = NULL; + pData->pMapBuffer = NULL; + pData->pMapBufferPriv = NULL; +} + +static NV_STATUS +_gpushareddataRequestDataPoll +( + GpuUserSharedData *pData, + NvU64 polledDataMask +) +{ + OBJGPU *pGpu = staticCast(pData, Memory)->pGpu; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS params; + NvU64 polledDataUnion = 0U; + RmClient **ppClient; + + if (polledDataMask == pData->polledDataMask) + return NV_OK; // Nothing to do + + pData->polledDataMask = polledDataMask; + + // Iterate over all clients to get all RUSD objects + for (ppClient = serverutilGetFirstClientUnderLock(); + ppClient != NULL; + ppClient = serverutilGetNextClientUnderLock(ppClient)) + { + // Collect mask of all data requested by any existing RUSD objects + RS_ITERATOR iter = clientRefIter(staticCast(*ppClient, RsClient), NULL, + classId(GpuUserSharedData), RS_ITERATE_DESCENDANTS, NV_TRUE); + while (clientRefIterNext(iter.pClient, &iter)) + { + // Ignore RUSD objects on GPUs that don't match the RUSD object this poll request came from + GpuUserSharedData *pIterData = dynamicCast(iter.pResourceRef->pResource, GpuUserSharedData); + if ((pIterData != NULL) && (staticCast(pIterData, Memory)->pGpu == pGpu)) + { + polledDataUnion |= pIterData->polledDataMask; + } + } + } + + if (polledDataUnion == pGpu->userSharedData.lastPolledDataMask) + return NV_OK; // Nothing to do + + params.polledDataMask = polledDataUnion; + + // Send updated data request to GSP + NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL, + ¶ms, sizeof(params))); + + pGpu->userSharedData.lastPolledDataMask = polledDataUnion; + + return NV_OK; +} + +NV_STATUS +gpushareddataCtrlCmdRequestDataPoll_IMPL +( + GpuUserSharedData *pData, + NV00DE_CTRL_REQUEST_DATA_POLL_PARAMS *pParams +) +{ + return _gpushareddataRequestDataPoll(pData, pParams->polledDataMask); +} diff --git a/src/nvidia/src/kernel/gpu/gr/arch/ampere/kgrmgr_ga100.c b/src/nvidia/src/kernel/gpu/gr/arch/ampere/kgrmgr_ga100.c new file mode 100644 index 0000000000..f1c15e782b --- /dev/null +++ b/src/nvidia/src/kernel/gpu/gr/arch/ampere/kgrmgr_ga100.c @@ -0,0 +1,48 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "kernel/gpu/gr/kernel_graphics_manager.h" + +/*! + * @brief Get the VEID count for the given GPC count + */ +NV_STATUS +kgrmgrGetVeidsFromGpcCount_GA100 +( + OBJGPU *pGpu, + KernelGraphicsManager *pKernelGraphicsManager, + NvU32 gpcCount, + NvU32 *pVeidCount +) +{ + NvU32 veidStepSize; + + NV_ASSERT_OR_RETURN(pVeidCount != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(gpcCount > 0, NV_ERR_INVALID_ARGUMENT); + + NV_ASSERT_OK_OR_RETURN(kgrmgrGetVeidStepSize(pGpu, pKernelGraphicsManager, &veidStepSize)); + *pVeidCount = gpcCount * veidStepSize; + + return NV_OK; +} + diff --git a/src/nvidia/src/kernel/gpu/gr/arch/maxwell/kgraphics_gm200.c b/src/nvidia/src/kernel/gpu/gr/arch/maxwell/kgraphics_gm200.c index 828d0180d9..d92f833e41 100644 --- a/src/nvidia/src/kernel/gpu/gr/arch/maxwell/kgraphics_gm200.c +++ b/src/nvidia/src/kernel/gpu/gr/arch/maxwell/kgraphics_gm200.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -59,6 +59,7 @@ kgraphicsAllocGrGlobalCtxBuffers_GM200 MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); CTX_BUF_POOL_INFO *pCtxBufPool; const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo; + NV_STATUS status; NV_ASSERT_OR_RETURN(!gpumgrGetBcEnabledStatus(pGpu), NV_ERR_INVALID_STATE); @@ -172,8 +173,9 @@ kgraphicsAllocGrGlobalCtxBuffers_GM200 memmgrSetMemDescPageSize_HAL(pGpu, pMemoryManager, *ppMemDesc, AT_GPU, RM_ATTR_PAGE_SIZE_4KB); NV_ASSERT_OK_OR_RETURN(memdescSetCtxBufPool(*ppMemDesc, pCtxBufPool)); } - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - memdescAllocList(*ppMemDesc, pCtxAttr[GR_GLOBALCTX_BUFFER_BUNDLE_CB].pAllocList)); + + memdescTagAllocList(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_CIRCULAR_BUFFER, *ppMemDesc, pCtxAttr[GR_GLOBALCTX_BUFFER_BUNDLE_CB].pAllocList); + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, status); } // Page Pool @@ -197,8 +199,9 @@ kgraphicsAllocGrGlobalCtxBuffers_GM200 memmgrSetMemDescPageSize_HAL(pGpu, pMemoryManager, *ppMemDesc, AT_GPU, RM_ATTR_PAGE_SIZE_4KB); NV_ASSERT_OK_OR_RETURN(memdescSetCtxBufPool(*ppMemDesc, pCtxBufPool)); } - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - memdescAllocList(*ppMemDesc, pCtxAttr[GR_GLOBALCTX_BUFFER_PAGEPOOL].pAllocList)); + + memdescTagAllocList(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_PAGE_POOL, *ppMemDesc, pCtxAttr[GR_GLOBALCTX_BUFFER_PAGEPOOL].pAllocList); + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, status); } // Attribute Buffer @@ -222,8 +225,11 @@ kgraphicsAllocGrGlobalCtxBuffers_GM200 memmgrSetMemDescPageSize_HAL(pGpu, pMemoryManager, *ppMemDesc, AT_GPU, RM_ATTR_PAGE_SIZE_4KB); NV_ASSERT_OK_OR_RETURN(memdescSetCtxBufPool(*ppMemDesc, pCtxBufPool)); } - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - memdescAllocList(*ppMemDesc, pCtxAttr[GR_GLOBALCTX_BUFFER_ATTRIBUTE_CB].pAllocList)); + + + memdescTagAllocList(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_ATTR_BUFFER, *ppMemDesc, pCtxAttr[GR_GLOBALCTX_BUFFER_ATTRIBUTE_CB].pAllocList); + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, status); + memdescSetName(pGpu, *ppMemDesc, NV_RM_SURF_NAME_GR_CIRCULAR_BUFFER, NULL); } @@ -257,8 +263,8 @@ kgraphicsAllocGrGlobalCtxBuffers_GM200 memmgrSetMemDescPageSize_HAL(pGpu, pMemoryManager, *ppMemDesc, AT_GPU, RM_ATTR_PAGE_SIZE_4KB); NV_ASSERT_OK_OR_RETURN(memdescSetCtxBufPool(*ppMemDesc, pCtxBufPool)); } - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - memdescAllocList(*ppMemDesc, pCtxAttr[GR_GLOBALCTX_BUFFER_PRIV_ACCESS_MAP].pAllocList)); + memdescTagAllocList(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_ACCESS_MAP, *ppMemDesc, pCtxAttr[GR_GLOBALCTX_BUFFER_PRIV_ACCESS_MAP].pAllocList); + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, status); } // @@ -289,9 +295,9 @@ kgraphicsAllocGrGlobalCtxBuffers_GM200 NV_ASSERT_OK_OR_RETURN(memdescSetCtxBufPool(*ppMemDesc, pCtxBufPool)); } - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - memdescAllocList(*ppMemDesc, - pCtxAttr[GR_GLOBALCTX_BUFFER_UNRESTRICTED_PRIV_ACCESS_MAP].pAllocList)); + memdescTagAllocList(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_ACCESS_MAP, *ppMemDesc, + pCtxAttr[GR_GLOBALCTX_BUFFER_UNRESTRICTED_PRIV_ACCESS_MAP].pAllocList); + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, status); } } } diff --git a/src/nvidia/src/kernel/gpu/gr/arch/pascal/kgraphics_gp100.c b/src/nvidia/src/kernel/gpu/gr/arch/pascal/kgraphics_gp100.c index b539b0f79c..b6e141c24a 100644 --- a/src/nvidia/src/kernel/gpu/gr/arch/pascal/kgraphics_gp100.c +++ b/src/nvidia/src/kernel/gpu/gr/arch/pascal/kgraphics_gp100.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -27,6 +27,7 @@ #include "kernel/gpu/mem_mgr/mem_mgr.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" #include "kernel/gpu/intr/engine_idx.h" +#include "kernel/gpu/bus/kern_bus.h" #include "nvRmReg.h" #include "ctrl/ctrl0080/ctrl0080fifo.h" @@ -155,6 +156,7 @@ kgraphicsAllocGlobalCtxBuffers_GP100 NvU32 fecsBufferAlign = 0x0; GR_GLOBALCTX_BUFFERS *pCtxBuffers; GR_BUFFER_ATTR *pCtxAttr; + NV_STATUS status; // SKIP FECS buffer allocation for Virtual context if (IS_GFID_VF(gfid)) @@ -224,8 +226,9 @@ kgraphicsAllocGlobalCtxBuffers_GP100 NV_ASSERT_OK_OR_RETURN(memdescSetCtxBufPool(*ppMemDesc, pCtxBufPool)); } - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - memdescAllocList(*ppMemDesc, pCtxAttr[GR_GLOBALCTX_BUFFER_FECS_EVENT].pAllocList)); + memdescTagAllocList(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_108, + (*ppMemDesc), (pCtxAttr[GR_GLOBALCTX_BUFFER_FECS_EVENT].pAllocList)); + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, status); } return NV_OK; diff --git a/src/nvidia/src/kernel/gpu/gr/arch/turing/kgraphics_tu102.c b/src/nvidia/src/kernel/gpu/gr/arch/turing/kgraphics_tu102.c index 9e80be27ad..1ca621927a 100644 --- a/src/nvidia/src/kernel/gpu/gr/arch/turing/kgraphics_tu102.c +++ b/src/nvidia/src/kernel/gpu/gr/arch/turing/kgraphics_tu102.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -146,8 +146,9 @@ kgraphicsAllocGrGlobalCtxBuffers_TU102 memmgrSetMemDescPageSize_HAL(pGpu, pMemoryManager, *ppMemDesc, AT_GPU, RM_ATTR_PAGE_SIZE_4KB); NV_ASSERT_OK_OR_RETURN(memdescSetCtxBufPool(*ppMemDesc, pCtxBufPool)); } - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - memdescAllocList(*ppMemDesc, pCtxAttr[GR_GLOBALCTX_BUFFER_RTV_CB].pAllocList)); + memdescTagAllocList(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_113, + (*ppMemDesc), pCtxAttr[GR_GLOBALCTX_BUFFER_RTV_CB].pAllocList); + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, status); } status = kgraphicsAllocGrGlobalCtxBuffers_GP100(pGpu, pKernelGraphics, gfid, pKernelGraphicsContext); diff --git a/src/nvidia/src/kernel/gpu/gr/fecs_event_list.c b/src/nvidia/src/kernel/gpu/gr/fecs_event_list.c index f4c09a8696..4582901040 100644 --- a/src/nvidia/src/kernel/gpu/gr/fecs_event_list.c +++ b/src/nvidia/src/kernel/gpu/gr/fecs_event_list.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -30,9 +30,6 @@ * * \***************************************************************************/ -// FIXME XXX -#define NVOC_GPU_INSTANCE_SUBSCRIPTION_H_PRIVATE_ACCESS_ALLOWED - #include "kernel/gpu/gr/kernel_graphics.h" #include "kernel/rmapi/event.h" #include "kernel/rmapi/event_buffer.h" @@ -45,14 +42,17 @@ #include "kernel/gpu/bus/kern_bus.h" #include "kernel/gpu/mem_mgr/mem_mgr.h" #include "kernel/gpu/fifo/kernel_channel.h" +#include "kernel/gpu/subdevice/subdevice.h" #include "kernel/virtualization/hypervisor/hypervisor.h" #include "rmapi/client.h" +#include "objtmr.h" #include "class/cl90cdtypes.h" #include "ctrl/ctrl90cd.h" #define NV_FECS_TRACE_MAX_TIMESTAMPS 5 #define NV_FECS_TRACE_MAGIC_INVALIDATED 0xdededede // magic number for entries that have been read +#define NV_FECS_TRACE_CALLBACK_TIME_NS 33333333 // Approximating 30Hz callback typedef struct { @@ -712,6 +712,97 @@ fecsBufferChanged return NV_FALSE; } +static void +_fecsOsWorkItem +( + NvU32 gpuInstance, + void *data +) +{ + OBJGPU *pGpu = gpumgrGetGpu(gpuInstance); + KernelGraphicsManager *pKernelGraphicsManager; + + NV_CHECK_OR_RETURN_VOID(LEVEL_ERROR, pGpu != NULL); + pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); + + nvEventBufferFecsCallback(pGpu, NULL); + kgrmgrClearFecsCallbackScheduled(pGpu, pKernelGraphicsManager); +} + +static NV_STATUS +_fecsTimerCallback +( + OBJGPU *pGpu, + OBJTMR *pTmr, + TMR_EVENT *pTmrEvent +) +{ + NV_STATUS status = NV_OK; + KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); + NvU32 i; + + // If any Kgraphics have events, schedule work item + for (i = 0; i < GPU_MAX_GRS; i++) + { + KernelGraphics *pKernelGraphics = GPU_GET_KERNEL_GRAPHICS(pGpu, i); + + if (pKernelGraphics == NULL) + continue; + + if (fecsBufferChanged(pGpu, pKernelGraphics) && kgrmgrSignalFecsCallbackScheduled(pGpu, pKernelGraphicsManager)) + { + NV_CHECK_OK(status, LEVEL_ERROR, osQueueWorkItemWithFlags(pGpu, _fecsOsWorkItem, NULL, OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_DEVICE_RW)); + + if (status != NV_OK) + kgrmgrClearFecsCallbackScheduled(pGpu, pKernelGraphicsManager); + + break; + } + } + + // TMR_FLAG_RECUR does not work, so reschedule it here. + NV_CHECK_OK_OR_CAPTURE_FIRST_ERROR(status, LEVEL_ERROR, tmrEventScheduleRel(pTmr, pTmrEvent, NV_FECS_TRACE_CALLBACK_TIME_NS)); + + return status; +} + +static NV_STATUS +_fecsTimerCreate +( + OBJGPU *pGpu +) +{ + OBJTMR *pTmr = GPU_GET_TIMER(pGpu); + NvU32 timerFlags = TMR_FLAG_RECUR; + // Unix needs to use the OS timer to avoid corrupting records, but Windows doesn't have an OS timer implementation + timerFlags |= TMR_FLAG_USE_OS_TIMER; + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + tmrEventCreate(pTmr, &pGpu->pFecsTimerEvent, _fecsTimerCallback, NULL, timerFlags)); + + // This won't be a true 30Hz timer as the callbacks are scheduled from the time they're called + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + tmrEventScheduleRel(pTmr, pGpu->pFecsTimerEvent, NV_FECS_TRACE_CALLBACK_TIME_NS)); + + return NV_OK; +} + +static void +_fecsTimerDestroy +( + OBJGPU *pGpu +) +{ + if (pGpu->pFecsTimerEvent != NULL) + { + OBJTMR *pTmr = GPU_GET_TIMER(pGpu); + + tmrEventCancel(pTmr, pGpu->pFecsTimerEvent); + tmrEventDestroy(pTmr, pGpu->pFecsTimerEvent); + pGpu->pFecsTimerEvent = NULL; + } +} + /** * @brief The callback function that transfers FECS Buffer entries to an EventBuffer */ @@ -885,7 +976,7 @@ fecsAddBindpoint OBJGPU *pGpu, RmClient *pClient, RsResourceRef *pEventBufferRef, - NvHandle hNotifier, + Subdevice *pNotifier, NvBool bAllUsers, NV2080_CTRL_GR_FECS_BIND_EVTBUF_LOD levelOfDetail, NvU32 eventFilter, @@ -896,13 +987,13 @@ fecsAddBindpoint NV_STATUS status; NvHandle hClient = staticCast(pClient, RsClient)->hClient; NvHandle hEventBuffer = pEventBufferRef->hResource; + NvHandle hNotifier = RES_GET_HANDLE(pNotifier); EventBuffer *pEventBuffer; NvBool bAdmin = osIsAdministrator(); NvU32 eventMask = 0; NvU64 targetUser; NvS32 gpuConsumerCount = pGpu->fecsCtxswLogConsumerCount; NvBool bFecsBindingActive = (pGpu->fecsCtxswLogConsumerCount > 0); - NvBool bScheduled = NV_FALSE; NvBool bIntrDriven = NV_FALSE; KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); NvBool bMIGInUse = IS_MIG_IN_USE(pGpu); @@ -1038,7 +1129,7 @@ fecsAddBindpoint if (bMIGInUse) { - if (kmigmgrIsClientUsingDeviceProfiling(pGpu, pKernelMIGManager, hClient)) + if (kmigmgrIsDeviceUsingDeviceProfiling(pGpu, pKernelMIGManager, GPU_RES_GET_DEVICE(pNotifier))) { pBind->swizzId = NV2080_CTRL_GPU_PARTITION_ID_INVALID; } @@ -1050,7 +1141,7 @@ fecsAddBindpoint if (status != NV_OK) goto done; - if (pGPUInstanceSubscription->pKernelMIGGpuInstance == NULL) + if (gisubscriptionGetMIGGPUInstance(pGPUInstanceSubscription) == NULL) { if (pReasonCode != NULL) *pReasonCode = NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NOT_ENABLED; @@ -1059,7 +1150,7 @@ fecsAddBindpoint goto done; } - pBind->swizzId = pGPUInstanceSubscription->pKernelMIGGpuInstance->swizzId; + pBind->swizzId = gisubscriptionGetMIGGPUInstance(pGPUInstanceSubscription)->swizzId; } } @@ -1090,18 +1181,7 @@ fecsAddBindpoint if (!bFecsBindingActive && !bIntrDriven) { - status = osSchedule1SecondCallback(pGpu, - nvEventBufferFecsCallback, - NULL, - NV_OS_1HZ_REPEAT); - - if (status != NV_OK) - { - status = NV_ERR_INSUFFICIENT_RESOURCES; - goto done; - } - - bScheduled = NV_TRUE; + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, _fecsTimerCreate(pGpu), done); } done: @@ -1110,8 +1190,7 @@ fecsAddBindpoint if (gpuConsumerCount != pGpu->fecsCtxswLogConsumerCount) fecsRemoveBindpoint(pGpu, targetUser, pBind); - if (bScheduled) - osRemove1SecondRepeatingCallback(pGpu, nvEventBufferFecsCallback, NULL); + _fecsTimerDestroy(pGpu); } return status; @@ -1165,7 +1244,7 @@ fecsRemoveBindpoint if (!bIntrDriven) { - osRemove1SecondRepeatingCallback(pGpu, nvEventBufferFecsCallback, NULL); + _fecsTimerDestroy(pGpu); } } } diff --git a/src/nvidia/src/kernel/gpu/gr/kernel_graphics.c b/src/nvidia/src/kernel/gpu/gr/kernel_graphics.c index 410024afcd..4bfa7a64ff 100644 --- a/src/nvidia/src/kernel/gpu/gr/kernel_graphics.c +++ b/src/nvidia/src/kernel/gpu/gr/kernel_graphics.c @@ -95,6 +95,10 @@ static NV_STATUS _kgraphicsMapGlobalCtxBuffer(OBJGPU *pGpu, KernelGraphics *pKer KernelGraphicsContext *, GR_GLOBALCTX_BUFFER, NvBool bIsReadOnly); static NV_STATUS _kgraphicsPostSchedulingEnableHandler(OBJGPU *, void *); +static void _kgraphicsInitProdRegistryOverrides(OBJGPU *pGpu, KernelGraphics *pKernelGraphics) +{ +} + NV_STATUS kgraphicsConstructEngine_IMPL ( @@ -213,6 +217,7 @@ kgraphicsConstructEngine_IMPL NV_ASSERT_OK_OR_RETURN(fecsCtxswLoggingInit(pGpu, pKernelGraphics, &pKernelGraphics->pFecsTraceInfo)); + _kgraphicsInitProdRegistryOverrides(pGpu, pKernelGraphics); return NV_OK; } @@ -295,10 +300,11 @@ kgraphicsStateInitLocked_IMPL // first as a part of Fifo post load. Hence, add the golden channel // creation as a fifo post-scheduling-enablement callback. // - kfifoAddSchedulingHandler(pGpu, GPU_GET_KERNEL_FIFO(pGpu), - _kgraphicsPostSchedulingEnableHandler, - (void *)((NvUPtr)(pKernelGraphics->instance)), - NULL, NULL); + NV_ASSERT_OK_OR_RETURN( + kfifoAddSchedulingHandler(pGpu, GPU_GET_KERNEL_FIFO(pGpu), + _kgraphicsPostSchedulingEnableHandler, + (void *)((NvUPtr)(pKernelGraphics->instance)), + NULL, NULL)); } return NV_OK; @@ -1768,7 +1774,7 @@ kgraphicsCreateGoldenImageChannel_IMPL portMemSet(&nv2080AllocParams, 0, sizeof(nv2080AllocParams)); nv2080AllocParams.subDeviceId = gpumgrGetSubDeviceInstanceFromGpu(pGpu); - NV_CHECK_OK(status, LEVEL_WARNING, + NV_CHECK_OK(status, LEVEL_SILENT, pRmApi->AllocWithHandle(pRmApi, hClientId, hDeviceId, @@ -2020,7 +2026,8 @@ kgraphicsCreateGoldenImageChannel_IMPL } NV_ASSERT_OK( - vaspaceReserveMempool(pKernelChannel->pVAS, pGpu, hClientId, + vaspaceReserveMempool(pKernelChannel->pVAS, pGpu, + GPU_RES_GET_DEVICE(pKernelChannel), reserveSize, RM_PAGE_SIZE, VASPACE_RESERVE_FLAGS_NONE)); } @@ -2097,13 +2104,16 @@ void kgraphicsFreeGlobalCtxBuffers_IMPL FOR_EACH_IN_ENUM(GR_GLOBALCTX_BUFFER, buff) { - if (pCtxBuffers->memDesc[buff] != NULL) - bEvict = NV_TRUE; + { + + if (pCtxBuffers->memDesc[buff] != NULL) + bEvict = NV_TRUE; - memdescFree(pCtxBuffers->memDesc[buff]); - memdescDestroy(pCtxBuffers->memDesc[buff]); - pCtxBuffers->memDesc[buff] = NULL; - pCtxBuffers->bInitialized[buff] = NV_FALSE; + memdescFree(pCtxBuffers->memDesc[buff]); + memdescDestroy(pCtxBuffers->memDesc[buff]); + pCtxBuffers->memDesc[buff] = NULL; + pCtxBuffers->bInitialized[buff] = NV_FALSE; + } } FOR_EACH_IN_ENUM_END; @@ -2330,7 +2340,7 @@ _kgraphicsCtrlCmdGrGetInfoV2 return NV_ERR_INVALID_ARGUMENT; } - if (kmigmgrIsClientUsingDeviceProfiling(pGpu, pKernelMIGManager, RES_GET_CLIENT_HANDLE(pDevice))) + if (kmigmgrIsDeviceUsingDeviceProfiling(pGpu, pKernelMIGManager, pDevice)) { NvU32 grIdx; for (grIdx = 0; grIdx < GPU_MAX_GRS; grIdx++) @@ -2604,16 +2614,15 @@ subdeviceCtrlCmdKGrGetSmToGpcTpcMappings_IMPL { OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); KernelGraphics *pKernelGraphics; - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); const KGRAPHICS_STATIC_INFO *pStaticInfo; NvU32 i; - LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); - if (kmigmgrIsClientUsingDeviceProfiling(pGpu, pKernelMIGManager, hClient)) + if (kmigmgrIsDeviceUsingDeviceProfiling(pGpu, pKernelMIGManager, pDevice)) { return NV_ERR_NOT_SUPPORTED; } @@ -2652,7 +2661,6 @@ subdeviceCtrlCmdKGrGetGlobalSmOrder_IMPL NV_STATUS status = NV_OK; OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); KernelGraphics *pKernelGraphics; - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); @@ -2661,7 +2669,7 @@ subdeviceCtrlCmdKGrGetGlobalSmOrder_IMPL LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); - if (kmigmgrIsClientUsingDeviceProfiling(pGpu, pKernelMIGManager, hClient)) + if (kmigmgrIsDeviceUsingDeviceProfiling(pGpu, pKernelMIGManager, pDevice)) { return NV_ERR_NOT_SUPPORTED; } @@ -2710,7 +2718,6 @@ subdeviceCtrlCmdKGrGetSmIssueRateModifier_IMPL { OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); KernelGraphics *pKernelGraphics; - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); const KGRAPHICS_STATIC_INFO *pStaticInfo; @@ -2718,7 +2725,7 @@ subdeviceCtrlCmdKGrGetSmIssueRateModifier_IMPL LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); - if (kmigmgrIsClientUsingDeviceProfiling(pGpu, pKernelMIGManager, hClient)) + if (kmigmgrIsDeviceUsingDeviceProfiling(pGpu, pKernelMIGManager, pDevice)) { NvU32 grIdx; for (grIdx = 0; grIdx < GPU_MAX_GRS; grIdx++) @@ -2769,7 +2776,6 @@ subdeviceCtrlCmdKGrGetGpcMask_IMPL { NV_STATUS status = NV_OK; OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); KernelGraphics *pKernelGraphics; @@ -2779,7 +2785,7 @@ subdeviceCtrlCmdKGrGetGpcMask_IMPL LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); if (!IS_MIG_IN_USE(pGpu) || - kmigmgrIsClientUsingDeviceProfiling(pGpu, pKernelMIGManager, hClient)) + kmigmgrIsDeviceUsingDeviceProfiling(pGpu, pKernelMIGManager, pDevice)) { pParams->gpcMask = kgrmgrGetLegacyGpcMask(pGpu, pKernelGraphicsManager); } @@ -2816,7 +2822,6 @@ subdeviceCtrlCmdKGrGetTpcMask_IMPL { NV_STATUS status = NV_OK; OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); KernelGraphics *pKernelGraphics; @@ -2827,7 +2832,7 @@ subdeviceCtrlCmdKGrGetTpcMask_IMPL LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); if (!IS_MIG_IN_USE(pGpu) || - kmigmgrIsClientUsingDeviceProfiling(pGpu, pKernelMIGManager, hClient)) + kmigmgrIsDeviceUsingDeviceProfiling(pGpu, pKernelMIGManager, pDevice)) { pParams->tpcMask = kgrmgrGetLegacyTpcMask(pGpu, pKernelGraphicsManager, pParams->gpcId); } @@ -2900,7 +2905,6 @@ subdeviceCtrlCmdKGrGetPpcMask_IMPL ) { OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); KernelGraphics *pKernelGraphics; @@ -2909,7 +2913,7 @@ subdeviceCtrlCmdKGrGetPpcMask_IMPL LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); - if (kmigmgrIsClientUsingDeviceProfiling(pGpu, pKernelMIGManager, hClient)) + if (kmigmgrIsDeviceUsingDeviceProfiling(pGpu, pKernelMIGManager, pDevice)) { NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kgrmgrGetLegacyPpcMask(pGpu, pKernelGraphicsManager, pParams->gpcId, &pParams->ppcMask)); } @@ -2954,10 +2958,9 @@ subdeviceCtrlCmdKGrFecsBindEvtbufForUid_IMPL RsResourceRef *pEventBufferRef = NULL; OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); - NvHandle hNotifier = RES_GET_HANDLE(pSubdevice); NvBool bMIGInUse = IS_MIG_IN_USE(pGpu); - LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); NV_ASSERT_OK_OR_RETURN( serverutilGetResourceRefWithType(hClient, pParams->hEventBuffer, classId(EventBuffer), &pEventBufferRef)); @@ -2971,7 +2974,7 @@ subdeviceCtrlCmdKGrFecsBindEvtbufForUid_IMPL status = fecsAddBindpoint(pGpu, pClient, pEventBufferRef, - hNotifier, + pSubdevice, pParams->bAllUsers, pParams->levelOfDetail, pParams->eventFilter, @@ -2999,10 +3002,9 @@ subdeviceCtrlCmdKGrFecsBindEvtbufForUidV2_IMPL RsResourceRef *pEventBufferRef = NULL; OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); - NvHandle hNotifier = RES_GET_HANDLE(pSubdevice); pParams->reasonCode = NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NONE; - LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); NV_ASSERT_OK_OR_RETURN( serverutilGetResourceRefWithType(hClient, pParams->hEventBuffer, classId(EventBuffer), &pEventBufferRef)); @@ -3013,7 +3015,7 @@ subdeviceCtrlCmdKGrFecsBindEvtbufForUidV2_IMPL status = fecsAddBindpoint(pGpu, pClient, pEventBufferRef, - hNotifier, + pSubdevice, pParams->bAllUsers, pParams->levelOfDetail, pParams->eventFilter, @@ -3038,7 +3040,6 @@ subdeviceCtrlCmdKGrGetPhysGpcMask_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); KernelGraphics *pKernelGraphics; const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo; - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); NvU32 grIdx = 0; @@ -3056,7 +3057,7 @@ subdeviceCtrlCmdKGrGetPhysGpcMask_IMPL // For valid subscription - Return physical GPC mask after validating that // a physical syspipe exist in given GPU instance // - else if (kmigmgrIsClientUsingDeviceProfiling(pGpu, pKernelMIGManager, hClient)) + else if (kmigmgrIsDeviceUsingDeviceProfiling(pGpu, pKernelMIGManager, pDevice)) { NV_ASSERT_OR_RETURN(pParams->physSyspipeId < GPU_MAX_GRS, NV_ERR_INVALID_ARGUMENT); grIdx = pParams->physSyspipeId; @@ -3106,7 +3107,6 @@ subdeviceCtrlCmdKGrGetZcullMask_IMPL ) { OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); NV2080_CTRL_GR_ROUTE_INFO grRouteInfo; @@ -3116,7 +3116,7 @@ subdeviceCtrlCmdKGrGetZcullMask_IMPL LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); - if (kmigmgrIsClientUsingDeviceProfiling(pGpu, pKernelMIGManager, hClient)) + if (kmigmgrIsDeviceUsingDeviceProfiling(pGpu, pKernelMIGManager, pDevice)) { pParams->zcullMask = kgrmgrGetLegacyZcullMask(pGpu, pKernelGraphicsManager, pParams->gpcId); } @@ -3211,7 +3211,7 @@ subdeviceCtrlCmdKGrCtxswPmMode_IMPL KernelGraphicsContext *pKernelGraphicsContext; RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); if (pParams->pmMode != NV2080_CTRL_CTXSW_PM_MODE_NO_CTXSW) { diff --git a/src/nvidia/src/kernel/gpu/gr/kernel_graphics_context.c b/src/nvidia/src/kernel/gpu/gr/kernel_graphics_context.c index fd6233ce2e..e6ca6e807f 100644 --- a/src/nvidia/src/kernel/gpu/gr/kernel_graphics_context.c +++ b/src/nvidia/src/kernel/gpu/gr/kernel_graphics_context.c @@ -21,9 +21,6 @@ * DEALINGS IN THE SOFTWARE. */ -// FIXME XXX -#define NVOC_KERNEL_GRAPHICS_OBJECT_H_PRIVATE_ACCESS_ALLOWED - #define NVOC_KERNEL_GRAPHICS_CONTEXT_H_PRIVATE_ACCESS_ALLOWED #include "kernel/gpu/gr/kernel_graphics_context.h" @@ -670,6 +667,43 @@ kgrctxRecordMmuFault_IMPL } } +/*! + * @brief getter for active debugger interator + */ +KernelSMDebuggerSessionListIter +kgrctxGetDebuggerSessionIter_IMPL +( + OBJGPU *pGpu, + KernelGraphicsContext *pKernelGraphicsContext +) +{ + return listIterAll(&pKernelGraphicsContext->pShared->activeDebuggers); +} + +/*! add active debugger session */ +NvBool +kgrctxRegisterKernelSMDebuggerSession_IMPL +( + OBJGPU *pGpu, + KernelGraphicsContext *pKernelGraphicsContext, + KernelSMDebuggerSession *pKernelSMDebuggerSession +) +{ + return listAppendValue(&pKernelGraphicsContext->pShared->activeDebuggers, &pKernelSMDebuggerSession) != NULL; +} + +/*! remove active debugger session */ +void +kgrctxDeregisterKernelSMDebuggerSession_IMPL +( + OBJGPU *pGpu, + KernelGraphicsContext *pKernelGraphicsContext, + KernelSMDebuggerSession *pKernelSMDebuggerSession +) +{ + listRemoveFirstByValue(&pKernelGraphicsContext->pShared->activeDebuggers, &pKernelSMDebuggerSession); +} + /*! * @brief Determine whether channels in this context are associated with GR engine * @@ -1130,8 +1164,10 @@ kgrctxAllocMainCtxBuffer_IMPL memmgrSetMemDescPageSize_HAL(pGpu, pMemoryManager, pGrCtxBufferMemDesc, AT_GPU, RM_ATTR_PAGE_SIZE_4KB)); NV_ASSERT_OK_OR_RETURN(memdescSetCtxBufPool(pGrCtxBufferMemDesc, pCtxBufPool)); - NV_ASSERT_OK_OR_RETURN( - memdescAllocList(pGrCtxBufferMemDesc, pAttr->pAllocList)); + + NV_STATUS status; + memdescTagAllocList(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_CONTEXT_BUFFER, pGrCtxBufferMemDesc, pAttr->pAllocList); + NV_ASSERT_OK_OR_RETURN(status); NV_ASSERT_OK_OR_RETURN( kchannelSetEngineContextMemDesc(pGpu, pKernelChannel, @@ -1196,8 +1232,10 @@ kgrctxAllocPatchBuffer_IMPL memdescSetCtxBufPool(*ppMemDesc, pCtxBufPool), failed); + memdescTagAllocList(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_117, + (*ppMemDesc), pAttr->pAllocList); NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, - memdescAllocList(*ppMemDesc, pAttr->pAllocList), + status, failed); return NV_OK; @@ -1280,8 +1318,10 @@ kgrctxAllocPmBuffer_IMPL NV_ASSERT_OK_OR_GOTO(status, memdescSetCtxBufPool(*ppMemDesc, pCtxBufPool), error); + memdescTagAllocList(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_118, + (*ppMemDesc), pAttr->pAllocList); NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, - memdescAllocList(*ppMemDesc, pAttr->pAllocList), + status, error); return NV_OK; @@ -1317,11 +1357,11 @@ kgrctxAllocCtxBuffers_IMPL NV_ASSERT(!gpumgrGetBcEnabledStatus(pGpu)); - NV_ASSERT_OR_RETURN(pKernelGraphicsObject->pKernelGraphicsContext != NULL, NV_ERR_INVALID_STATE); + NV_ASSERT_OR_RETURN(kgrobjGetKernelGraphicsContext(pGpu, pKernelGraphicsObject) != NULL, NV_ERR_INVALID_STATE); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kgrctxGetUnicast(pGpu, - pKernelGraphicsObject->pKernelGraphicsContext, + kgrobjGetKernelGraphicsContext(pGpu, pKernelGraphicsObject), &pKernelGraphicsContextUnicast)); // Allocate the GR ctx buffer if required @@ -1360,7 +1400,7 @@ kgrctxAllocCtxBuffers_IMPL if (kgrctxShouldPreAllocPmBuffer_HAL(pGpu, pKernelGraphicsContext, pChannelDescendant->pKernelChannel)) { NV_ASSERT_OK_OR_RETURN( - kgrctxAllocPmBuffer(pGpu, pKernelGraphicsObject->pKernelGraphicsContext, + kgrctxAllocPmBuffer(pGpu, kgrobjGetKernelGraphicsContext(pGpu, pKernelGraphicsObject), pKernelGraphics, pChannelDescendant->pKernelChannel)); } @@ -1374,7 +1414,7 @@ kgrctxAllocCtxBuffers_IMPL { NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kgraphicsAllocGrGlobalCtxBuffers_HAL(pGpu, pKernelGraphics, gfid, - pKernelGraphicsObject->pKernelGraphicsContext)); + kgrobjGetKernelGraphicsContext(pGpu, pKernelGraphicsObject))); } // Allocate global context for this gfid if they haven't been already @@ -1554,7 +1594,7 @@ kgrctxMapCtxBuffers_IMPL NV_ASSERT(!gpumgrGetBcEnabledStatus(pGpu)); NV_ASSERT_OK_OR_RETURN( - kgrctxGetUnicast(pGpu, pKernelGraphicsObject->pKernelGraphicsContext, &pKernelGraphicsContextUnicast)); + kgrctxGetUnicast(pGpu, kgrobjGetKernelGraphicsContext(pGpu, pKernelGraphicsObject), &pKernelGraphicsContextUnicast)); pGVAS = dynamicCast(pKernelChannel->pVAS, OBJGVASPACE); if (gvaspaceIsExternallyOwned(pGVAS)) @@ -2000,10 +2040,15 @@ kgrctxSetupDeferredPmBuffer_IMPL KernelGraphicsContextUnicast *pKernelGraphicsContextUnicast; OBJGVASPACE *pGVAS = dynamicCast(pKernelChannel->pVAS, OBJGVASPACE); NV_STATUS status = NV_OK; + Device *pDevice = GPU_RES_GET_DEVICE(pKernelChannel); Subdevice *pSubdevice; NV_ASSERT_OK_OR_RETURN( - subdeviceGetByGpu(RES_GET_CLIENT(pKernelChannel), pGpu, &pSubdevice)); + subdeviceGetByInstance( + RES_GET_CLIENT(pKernelChannel), + RES_GET_HANDLE(pDevice), + gpumgrGetSubDeviceInstanceFromGpu(pGpu), + &pSubdevice)); GPU_RES_SET_THREAD_BC_STATE(pSubdevice); @@ -2343,27 +2388,24 @@ kgrctxUnmapAssociatedCtxBuffers_IMPL // channels could be using these mappings, and we must wait for both // channels to be detached before we remove them. // - if (pKernelChannel->pKernelChannelGroupApi->pKernelChannelGroup->pChanList != NULL) { - CHANNEL_NODE *pChanNode; - CHANNEL_LIST *pChanList; + RS_ORDERED_ITERATOR it; + RsResourceRef *pScopeRef = RES_GET_REF(pKernelChannel); - pChanList = pKernelChannel->pKernelChannelGroupApi->pKernelChannelGroup->pChanList; + // Iterate over all channels in this TSG and check for duplicate VAS + if (!pKernelChannel->pKernelChannelGroupApi->pKernelChannelGroup->bAllocatedByRm) + pScopeRef = RES_GET_REF(pKernelChannel->pKernelChannelGroupApi); - for (pChanNode = pChanList->pHead; pChanNode; pChanNode = pChanNode->pNext) + it = kchannelGetIter(RES_GET_CLIENT(pKernelChannel), pScopeRef); + while (clientRefOrderedIterNext(it.pClient, &it)) { - // Skip the channel we are looking to unmap - if (kchannelGetDebugTag(pKernelChannel) == kchannelGetDebugTag(pChanNode->pKernelChannel)) + KernelChannel *pLoopKernelChannel = dynamicCast(it.pResourceRef->pResource, KernelChannel); + NV_ASSERT_OR_RETURN_VOID(pLoopKernelChannel != NULL); + + if (pLoopKernelChannel == pKernelChannel) continue; - - if (pKernelChannel->pVAS == pChanNode->pKernelChannel->pVAS) - { - NV_PRINTF(LEVEL_INFO, "TSG %d Channel %d shares a pVAS with channel %d\n", - pKernelChannel->pKernelChannelGroupApi->pKernelChannelGroup->grpID, - kchannelGetDebugTag(pKernelChannel), - kchannelGetDebugTag(pChanNode->pKernelChannel)); - return; - } + + NV_CHECK_OR_RETURN_VOID(LEVEL_SILENT, pLoopKernelChannel->pVAS != pKernelChannel->pVAS); } } @@ -2567,13 +2609,13 @@ void kgrctxUnmapBuffers_KERNEL NV_STATUS status; NV2080_CTRL_GR_ROUTE_INFO grRouteInfo; KernelGraphics *pKernelGraphics; - NvHandle hClient = RES_GET_CLIENT_HANDLE(pKernelGraphicsContext); + Device *pDevice = GPU_RES_GET_DEVICE(pKernelGraphicsContext); NvHandle hParent = RES_GET_PARENT_HANDLE(pKernelGraphicsContext); portMemSet(&grRouteInfo, 0, sizeof(grRouteInfo)); kgrmgrCtrlSetChannelHandle(hParent, &grRouteInfo); NV_ASSERT_OK_OR_ELSE(status, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &grRouteInfo, &pKernelGraphics), + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, &grRouteInfo, &pKernelGraphics), return; ); kgrctxUnmapAssociatedCtxBuffers(pGpu, pKernelGraphicsContext, pKernelGraphics, pKernelChannel); @@ -2606,7 +2648,8 @@ kgrctxUnmapMainCtxBuffer_IMPL { // TODO remove Channel, ENG_GR dependencies kchannelUnmapEngineCtxBuf(pGpu, pKernelChannel, ENG_GR(kgraphicsGetInstance(pGpu, pKernelGraphics))); - kchannelSetEngineContextMemDesc(pGpu, pKernelChannel, ENG_GR(kgraphicsGetInstance(pGpu, pKernelGraphics)), NULL); + NV_ASSERT_OR_RETURN_VOID( + kchannelSetEngineContextMemDesc(pGpu, pKernelChannel, ENG_GR(kgraphicsGetInstance(pGpu, pKernelGraphics)), NULL) == NV_OK); } } @@ -2984,7 +3027,7 @@ kgrctxUnmapCtxBuffers_IMPL NV_ASSERT_OK_OR_RETURN( kgrctxGetUnicast(pGpu, - pKernelGraphicsObject->pKernelGraphicsContext, + kgrobjGetKernelGraphicsContext(pGpu, pKernelGraphicsObject), &pKernelGraphicsContextUnicast)); kgrmgrGetGrObjectType(classNum, &objType); @@ -3389,14 +3432,14 @@ shrkgrctxInit_IMPL KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); KernelGraphics *pKernelGraphics; NV2080_CTRL_GR_ROUTE_INFO grRouteInfo; - NvHandle hClient = RES_GET_CLIENT_HANDLE(pKernelGraphicsContext); + Device *pDevice = GPU_RES_GET_DEVICE(pKernelGraphicsContext); NvHandle hParent = RES_GET_PARENT_HANDLE(pKernelGraphicsContext); portMemSet(&grRouteInfo, 0, sizeof(grRouteInfo)); kgrmgrCtrlSetChannelHandle(hParent, &grRouteInfo); NV_CHECK_OK_OR_CAPTURE_FIRST_ERROR(status, LEVEL_ERROR, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &grRouteInfo, &pKernelGraphics)); + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, &grRouteInfo, &pKernelGraphics)); if (status != NV_OK) SLI_LOOP_BREAK; @@ -3412,6 +3455,8 @@ shrkgrctxInit_IMPL } SLI_LOOP_END; + listInit(&pKernelGraphicsContextShared->activeDebuggers, portMemAllocatorGetGlobalNonPaged()); + if (status != NV_OK) shrkgrctxTeardown_IMPL(pGpu, pKernelGraphicsContextShared, pKernelGraphicsContext); @@ -3459,12 +3504,13 @@ shrkgrctxConstructUnicast_IMPL } /*! - * @brief Destruct shared kernel graphics context. (Does nothing) + * @brief Destruct shared kernel graphics context. */ void shrkgrctxDestruct_IMPL(KernelGraphicsContextShared *pKernelGraphicsContextShared) { - return; + NV_ASSERT(listCount(&pKernelGraphicsContextShared->activeDebuggers) == 0); + listDestroy(&pKernelGraphicsContextShared->activeDebuggers); } /*! @@ -3559,14 +3605,14 @@ void shrkgrctxDetach_IMPL { OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelChannel); KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); - NvHandle hClient = RES_GET_CLIENT_HANDLE(pKernelChannel); + Device *pDevice = GPU_RES_GET_DEVICE(pKernelChannel); NV2080_CTRL_GR_ROUTE_INFO grRouteInfo = {0}; KernelGraphics *pKernelGraphics; NV_STATUS status; kgrmgrCtrlSetChannelHandle(RES_GET_HANDLE(pKernelChannel), &grRouteInfo); NV_ASSERT_OK_OR_ELSE(status, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &grRouteInfo, &pKernelGraphics), + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, &grRouteInfo, &pKernelGraphics), return;); SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY | SLI_LOOP_FLAGS_IGNORE_REENTRANCY) diff --git a/src/nvidia/src/kernel/gpu/gr/kernel_graphics_manager.c b/src/nvidia/src/kernel/gpu/gr/kernel_graphics_manager.c index 756d8af5ce..e586341059 100644 --- a/src/nvidia/src/kernel/gpu/gr/kernel_graphics_manager.c +++ b/src/nvidia/src/kernel/gpu/gr/kernel_graphics_manager.c @@ -32,6 +32,7 @@ #include "kernel/rmapi/client.h" #include "kernel/rmapi/client_resource.h" +#include "nvRmReg.h" // COMPUTE #include "class/clb0c0.h" @@ -291,6 +292,15 @@ kgrmgrCtrlSetChannelHandle_IMPL } } +static void +_kgrmgrInitRegistryOverrides +( + OBJGPU *pGpu, + KernelGraphicsManager *pKernelGraphicsManager +) +{ +} + NV_STATUS kgrmgrConstructEngine_IMPL ( @@ -299,6 +309,8 @@ kgrmgrConstructEngine_IMPL ENGDESCRIPTOR engDesc ) { + _kgrmgrInitRegistryOverrides(pGpu, pKernelGraphicsManager); + return NV_OK; } @@ -364,50 +376,6 @@ kgrmgrSetLegacyKgraphicsStaticInfo_IMPL pKernelGraphicsManager->legacyKgraphicsStaticInfo.pGrInfo = NULL; } -/*! - * @brief Retrieves associated KernelGraphics engine for given client / route info - * - * @param[in] pGpu - * @param[in] pKernelGraphicsManager - * @param[in] hClient Client handle - * @param[in] grRouteInfo Client-provided info to direct GR accesses - * @param[out] ppKernelGraphics (Optional) Ptr to store appropriate KernelGraphics *, if desired. - */ -NV_STATUS -kgrmgrCtrlRouteKGR_IMPL -( - OBJGPU *pGpu, - KernelGraphicsManager *pKernelGraphicsManager, - NvHandle hClient, - const NV2080_CTRL_GR_ROUTE_INFO *pGrRouteInfo, - KernelGraphics **ppKernelGraphics -) -{ - RsClient *pClient; - Device *pDevice; - - if (!IS_MIG_IN_USE(pGpu)) - { - KernelGraphics *pKernelGraphics = GPU_GET_KERNEL_GRAPHICS(pGpu, 0); - - NV_ASSERT_OR_RETURN(pKernelGraphics != NULL, NV_ERR_INVALID_STATE); - - if (ppKernelGraphics != NULL) - *ppKernelGraphics = pKernelGraphics; - - return NV_OK; - } - - NV_ASSERT_OK_OR_RETURN( - serverGetClientUnderLock(&g_resServ, hClient, &pClient)); - - NV_ASSERT_OK_OR_RETURN( - deviceGetByGpu(pClient, pGpu, NV_TRUE, &pDevice)); - - return kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, - pGrRouteInfo, ppKernelGraphics); -} - /*! * @brief Retrieves associated KernelGraphics engine for given device / route info * @@ -698,7 +666,7 @@ kgrmgrAllocVeidsForGrIdx_IMPL KERNEL_MIG_GPU_INSTANCE *pKernelMIGGPUInstance ) { - NvU32 maxVeidsPerGpc; + NvU32 veidStepSize; NvU32 veidStart = 0; NvU32 veidEnd = 0; NvU32 GPUInstanceVeidEnd; @@ -710,18 +678,18 @@ kgrmgrAllocVeidsForGrIdx_IMPL NV_ASSERT_OR_RETURN(pKernelGraphicsManager->grIdxVeidMask[grIdx] == 0, NV_ERR_INVALID_STATE); NV_ASSERT_OK_OR_RETURN( - kgrmgrGetMaxVeidsPerGpc(pGpu, pKernelGraphicsManager, &maxVeidsPerGpc)); + kgrmgrGetVeidStepSize(pGpu, pKernelGraphicsManager, &veidStepSize)); // We statically assign VEIDs to a GR based on the number of GPCs connected to it - if (veidCount % maxVeidsPerGpc != 0) + if (veidCount % veidStepSize != 0) { - NV_PRINTF(LEVEL_ERROR, "veidCount %d is not aligned to maxVeidsPerGpc=%d\n", veidCount, maxVeidsPerGpc); + NV_PRINTF(LEVEL_ERROR, "veidCount %d is not aligned to veidStepSize=%d\n", veidCount, veidStepSize); return NV_ERR_INVALID_ARGUMENT; } NV_ASSERT_OR_RETURN(veidSpanOffset != KMIGMGR_SPAN_OFFSET_INVALID, NV_ERR_INVALID_ARGUMENT); - veidStart = (veidSpanOffset * maxVeidsPerGpc) + pKernelMIGGPUInstance->resourceAllocation.veidOffset; + veidStart = (veidSpanOffset * veidStepSize) + pKernelMIGGPUInstance->resourceAllocation.veidOffset; veidEnd = veidStart + veidCount - 1; NV_ASSERT_OR_RETURN(veidStart < veidEnd, NV_ERR_INVALID_STATE); @@ -742,7 +710,14 @@ kgrmgrAllocVeidsForGrIdx_IMPL // VEID range should not overlap with existing VEIDs in use NV_ASSERT_OR_RETURN((pKernelGraphicsManager->veidInUseMask & reqVeidMask) == 0, NV_ERR_STATE_IN_USE); - NV_ASSERT_OR_RETURN((GPUInstanceFreeVeidMask & reqVeidMask) == reqVeidMask, NV_ERR_INSUFFICIENT_RESOURCES); + + // + // For swizzId 0, client can use any range of VEIDs if not used, so we don't + // need to do the range check + // + NV_ASSERT_OR_RETURN(((pKernelMIGGPUInstance->swizzId == 0) || + ((GPUInstanceFreeVeidMask & reqVeidMask) == reqVeidMask)), + NV_ERR_INSUFFICIENT_RESOURCES); // mark each VEID in the range as "in use" pKernelGraphicsManager->veidInUseMask |= reqVeidMask; @@ -770,30 +745,22 @@ kgrmgrClearVeidsForGrIdx_IMPL pKernelGraphicsManager->grIdxVeidMask[grIdx] = 0; } -/*! - * @brief Function to get max VEID count per GPC +/*! + * @brief Get VEID step size */ NV_STATUS -kgrmgrGetMaxVeidsPerGpc_IMPL +kgrmgrGetVeidStepSize_IMPL ( OBJGPU *pGpu, KernelGraphicsManager *pKernelGraphicsManager, - NvU32 *pMaxVeidsPerGpc + NvU32 *pVeidStepSize ) { - NvU32 maxVeids; - NvU32 maxGpcCount; - - NV_ASSERT_OR_RETURN(pMaxVeidsPerGpc != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pVeidStepSize != NULL, NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN(pKernelGraphicsManager->legacyKgraphicsStaticInfo.bInitialized, NV_ERR_INVALID_STATE); NV_ASSERT_OR_RETURN(pKernelGraphicsManager->legacyKgraphicsStaticInfo.pGrInfo != NULL, NV_ERR_INVALID_STATE); - maxVeids = pKernelGraphicsManager->legacyKgraphicsStaticInfo.pGrInfo->infoList[NV0080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT].data; - - maxGpcCount = gpuGetLitterValues_HAL(pGpu, NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS); - NV_ASSERT_OR_RETURN(maxGpcCount != 0, NV_ERR_INSUFFICIENT_RESOURCES); - - *pMaxVeidsPerGpc = (maxVeids / maxGpcCount); + *pVeidStepSize = pKernelGraphicsManager->legacyKgraphicsStaticInfo.pGrInfo->infoList[NV0080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG].data; return NV_OK; } @@ -1039,7 +1006,7 @@ kgrmgrCheckVeidsRequest_IMPL KERNEL_MIG_GPU_INSTANCE *pKernelMIGGPUInstance ) { - NvU32 maxVeidsPerGpc; + NvU32 veidStepSize; NvU32 veidStart = 0; NvU32 veidEnd = 0; NvU32 GPUInstanceVeidEnd; @@ -1048,15 +1015,15 @@ kgrmgrCheckVeidsRequest_IMPL NvU64 veidMask; NV_ASSERT_OK_OR_RETURN( - kgrmgrGetMaxVeidsPerGpc(pGpu, pKernelGraphicsManager, &maxVeidsPerGpc)); + kgrmgrGetVeidStepSize(pGpu, pKernelGraphicsManager, &veidStepSize)); NV_ASSERT_OR_RETURN(pSpanStart != NULL, NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN(pInUseMask != NULL, NV_ERR_INVALID_ARGUMENT); // We statically assign VEIDs to a GR based on the number of GPCs connected to it - if (veidCount % maxVeidsPerGpc != 0) + if (veidCount % veidStepSize != 0) { - NV_PRINTF(LEVEL_ERROR, "veidCount %d is not aligned to maxVeidsPerGpc=%d\n", veidCount, maxVeidsPerGpc); + NV_PRINTF(LEVEL_ERROR, "veidCount %d is not aligned to veidStepSize=%d\n", veidCount, veidStepSize); return NV_ERR_INVALID_ARGUMENT; } @@ -1070,7 +1037,7 @@ kgrmgrCheckVeidsRequest_IMPL if (*pSpanStart != KMIGMGR_SPAN_OFFSET_INVALID) { - veidStart = (*pSpanStart * maxVeidsPerGpc) + pKernelMIGGPUInstance->resourceAllocation.veidOffset; + veidStart = (*pSpanStart * veidStepSize) + pKernelMIGGPUInstance->resourceAllocation.veidOffset; veidEnd = veidStart + veidCount - 1; NV_ASSERT_OR_RETURN(veidStart < veidEnd, NV_ERR_INVALID_STATE); @@ -1082,7 +1049,7 @@ kgrmgrCheckVeidsRequest_IMPL NvU64 reqVeidMask = DRF_SHIFTMASK64(veidCount - 1:0); NvU32 i; - for (i = pKernelMIGGPUInstance->resourceAllocation.veidOffset; i <= GPUInstanceVeidEnd; i += maxVeidsPerGpc) + for (i = pKernelMIGGPUInstance->resourceAllocation.veidOffset; i <= GPUInstanceVeidEnd; i += veidStepSize) { // See if requested slots are available within this range if (((GPUInstanceFreeVeidMask >> i) & reqVeidMask) == reqVeidMask) @@ -1100,14 +1067,47 @@ kgrmgrCheckVeidsRequest_IMPL veidMask = DRF_SHIFTMASK64(veidEnd:veidStart); NV_ASSERT_OR_RETURN(veidMask != 0x0, NV_ERR_INVALID_STATE); - NV_CHECK_OR_RETURN(LEVEL_ERROR, (GPUInstanceVeidMask & veidMask) == veidMask, NV_ERR_INSUFFICIENT_RESOURCES); + // + // For swizzId 0, client can use any range of VEIDs if not used, so we don't + // need to do the range check + // + NV_CHECK_OR_RETURN(LEVEL_ERROR, + ((pKernelMIGGPUInstance->swizzId == 0) || + (GPUInstanceVeidMask & veidMask) == veidMask), + NV_ERR_INSUFFICIENT_RESOURCES); // VEID range should not overlap with existing VEIDs in use NV_ASSERT_OR_RETURN((*pInUseMask & veidMask) == 0, NV_ERR_STATE_IN_USE); NV_ASSERT(veidStart >= pKernelMIGGPUInstance->resourceAllocation.veidOffset); - *pSpanStart = (veidStart - pKernelMIGGPUInstance->resourceAllocation.veidOffset) / maxVeidsPerGpc; + *pSpanStart = (veidStart - pKernelMIGGPUInstance->resourceAllocation.veidOffset) / veidStepSize; *pInUseMask |= veidMask; return NV_OK; } + +/*! + * @brief Atomically set fecs callback scheduled, return NV_TRUE if wasn't scheduled + */ +NvBool +kgrmgrSignalFecsCallbackScheduled_IMPL +( + OBJGPU *pGpu, + KernelGraphicsManager *pKernelGraphicsManager +) +{ + return portAtomicCompareAndSwapU32(&pKernelGraphicsManager->fecsCallbackScheduled, 1, 0); +} + +/*! + * @brief Atomically clear fecs callback scheduled + */ +void +kgrmgrClearFecsCallbackScheduled_IMPL +( + OBJGPU *pGpu, + KernelGraphicsManager *pKernelGraphicsManager +) +{ + portAtomicSetU32(&pKernelGraphicsManager->fecsCallbackScheduled, 0); +} diff --git a/src/nvidia/src/kernel/gpu/gr/kernel_graphics_object.c b/src/nvidia/src/kernel/gpu/gr/kernel_graphics_object.c index 5ca02b98f1..61ff7250db 100644 --- a/src/nvidia/src/kernel/gpu/gr/kernel_graphics_object.c +++ b/src/nvidia/src/kernel/gpu/gr/kernel_graphics_object.c @@ -61,6 +61,7 @@ kgrobjPromoteContext_IMPL NvU32 entryCount; RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); NV_STATUS status; + Device *pDevice = GPU_RES_GET_DEVICE(pKernelGraphicsObject); Subdevice *pSubdevice; ChannelDescendant *pChannelDescendant = staticCast(pKernelGraphicsObject, ChannelDescendant); @@ -68,7 +69,11 @@ kgrobjPromoteContext_IMPL return NV_OK; NV_ASSERT_OK_OR_RETURN( - subdeviceGetByGpu(RES_GET_CLIENT(pKernelGraphicsObject), pGpu, &pSubdevice)); + subdeviceGetByDeviceAndGpu( + RES_GET_CLIENT(pKernelGraphicsObject), + pDevice, + pGpu, + &pSubdevice)); GPU_RES_SET_THREAD_BC_STATE(pSubdevice); @@ -189,8 +194,6 @@ _kgrAlloc NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kgrobjSetComputeMmio_HAL(pGpu, pKernelGraphicsObject)); - listInit(&pKernelGraphicsObject->activeDebuggers, portMemAllocatorGetGlobalNonPaged()); - // Ensure that ctx buffer information is initialized if (!IS_MODS_AMODEL(pGpu)) { @@ -244,14 +247,14 @@ static void _kgrobjDestruct KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); KernelGraphics *pKernelGraphics; NV2080_CTRL_GR_ROUTE_INFO grRouteInfo = {0}; - NvHandle hClient = RES_GET_CLIENT_HANDLE(pChannelDescendant); + Device *pDevice = GPU_RES_GET_DEVICE(pChannelDescendant); NvHandle hParent = RES_GET_PARENT_HANDLE(pChannelDescendant); NvU32 classNum = pChannelDescendant->resourceDesc.externalClassId; // If MIG is enabled, perform GR instance routing based upon parent channel handle kgrmgrCtrlSetChannelHandle(hParent, &grRouteInfo); NV_ASSERT_OK_OR_CAPTURE_FIRST_ERROR(status, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &grRouteInfo, &pKernelGraphics)); + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, &grRouteInfo, &pKernelGraphics)); if (status != NV_OK) SLI_LOOP_CONTINUE; @@ -259,9 +262,6 @@ static void _kgrobjDestruct // Free Compute Mmio mapping kgrobjFreeComputeMmio_HAL(pGpu, pKernelGraphicsObject); - NV_ASSERT(listCount(&pKernelGraphicsObject->activeDebuggers) == 0); - listDestroy(&pKernelGraphicsObject->activeDebuggers); - if (bDestructor) kgrctxDecObjectCount_HAL(pGpu, pKernelGraphicsObject->pKernelGraphicsContext, classNum); @@ -292,7 +292,7 @@ kgrobjConstruct_IMPL KernelChannel *pKernelChannel = pChannelDescendant->pKernelChannel; NV_STATUS status = NV_OK; OBJGPU *pGpu = GPU_RES_GET_GPU(pChannelDescendant); - NvHandle hClient = pCallContext->pClient->hClient; + Device *pDevice = GPU_RES_GET_DEVICE(pKernelGraphicsObject); NV_ASSERT_OR_RETURN(pKernelChannel != NULL, NV_ERR_INVALID_STATE); @@ -334,7 +334,7 @@ kgrobjConstruct_IMPL // If MIG is enabled, perform GR instance routing based upon parent channel handle kgrmgrCtrlSetChannelHandle(pParams->hParent, &grRouteInfo); NV_ASSERT_OK_OR_CAPTURE_FIRST_ERROR(status, - kgrmgrCtrlRouteKGR(pGpu, pKernelGraphicsManager, hClient, &grRouteInfo, &pKernelGraphics)); + kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, &grRouteInfo, &pKernelGraphics)); if (status != NV_OK) SLI_LOOP_BREAK; diff --git a/src/nvidia/src/kernel/gpu/gr/kernel_sm_debugger_session.c b/src/nvidia/src/kernel/gpu/gr/kernel_sm_debugger_session.c index 45a465ae73..dd28f8b35e 100644 --- a/src/nvidia/src/kernel/gpu/gr/kernel_sm_debugger_session.c +++ b/src/nvidia/src/kernel/gpu/gr/kernel_sm_debugger_session.c @@ -174,10 +174,11 @@ _ksmdbgssnInitClient { NVC637_ALLOCATION_PARAMETERS nvC637AllocParams; MIG_INSTANCE_REF ref; + Device *pDevice = GPU_RES_GET_DEVICE(pKernelSMDebuggerSession); portMemSet(&nvC637AllocParams, 0, sizeof(nvC637AllocParams)); NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, pKernelSMDebuggerSession->hDebuggerClient, &ref), + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, &ref), failed); NV_ASSERT_OK_OR_GOTO(status, @@ -228,6 +229,7 @@ ksmdbgssnConstruct_IMPL NvHandle hSubdevice; NV_STATUS status = NV_OK; RsClient *pAppClient; + Device *pAppDevice; Subdevice *pSubdevice; RsResourceRef *pGrResourceRef; RsResourceRef *pParentRef; @@ -316,7 +318,13 @@ ksmdbgssnConstruct_IMPL NV_CHECK_OR_RETURN(LEVEL_ERROR, pGpu == GPU_RES_GET_GPU(pKernelSMDebuggerSession->pObject), NV_ERR_INVALID_ARGUMENT); - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, subdeviceGetByGpu(pAppClient, pGpu, &pSubdevice)); + pAppDevice = GPU_RES_GET_DEVICE(pKernelSMDebuggerSession->pObject); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + subdeviceGetByInstance(pAppClient, + RES_GET_HANDLE(pAppDevice), + gpumgrGetSubDeviceInstanceFromGpu(pGpu), + &pSubdevice)); GPU_RES_SET_THREAD_BC_STATE(pSubdevice); @@ -330,7 +338,7 @@ ksmdbgssnConstruct_IMPL pKernelSMDebuggerSession->hSubdevice = hSubdevice; // Insert it into this Object's debugger list - if (listAppendValue(&pKernelSMDebuggerSession->pObject->activeDebuggers, &pKernelSMDebuggerSession) == NULL) + if (!kgrctxRegisterKernelSMDebuggerSession(pGpu, kgrobjGetKernelGraphicsContext(pGpu, pKernelSMDebuggerSession->pObject), pKernelSMDebuggerSession)) { NV_PRINTF(LEVEL_ERROR, "Failed to insert Debugger into channel list, handle = 0x%x\n", @@ -440,12 +448,13 @@ ksmdbgssnFreeCallback_IMPL ) { RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelSMDebuggerSession); // This should free the entire hierarchy of objects. pRmApi->Free(pRmApi, pKernelSMDebuggerSession->hInternalClient, pKernelSMDebuggerSession->hInternalClient); // Remove it from the pObject debugger list - listRemoveFirstByValue(&pKernelSMDebuggerSession->pObject->activeDebuggers, &pKernelSMDebuggerSession); + kgrctxDeregisterKernelSMDebuggerSession(pGpu, kgrobjGetKernelGraphicsContext(pGpu, pKernelSMDebuggerSession->pObject), pKernelSMDebuggerSession); } diff --git a/src/nvidia/src/kernel/gpu/gr/kernel_sm_debugger_session_ctrl.c b/src/nvidia/src/kernel/gpu/gr/kernel_sm_debugger_session_ctrl.c index e4d42b759c..f98315161e 100644 --- a/src/nvidia/src/kernel/gpu/gr/kernel_sm_debugger_session_ctrl.c +++ b/src/nvidia/src/kernel/gpu/gr/kernel_sm_debugger_session_ctrl.c @@ -32,9 +32,6 @@ #define NVOC_KERNEL_SM_DEBUGGER_SESSION_H_PRIVATE_ACCESS_ALLOWED -// FIXME XXX -#define NVOC_KERNEL_GRAPHICS_OBJECT_H_PRIVATE_ACCESS_ALLOWED - #include "kernel/rmapi/control.h" #include "kernel/rmapi/rmapi.h" #include "kernel/os/os.h" @@ -869,7 +866,7 @@ ksmdbgssnCtrlCmdDebugReadAllSmErrorStates_IMPL { NV_ASSERT_OK( kgrctxLookupMmuFault(pGpu, - pKernelSMDebuggerSession->pObject->pKernelGraphicsContext, + kgrobjGetKernelGraphicsContext(pGpu, pKernelSMDebuggerSession->pObject), &pParams->mmuFault)); } @@ -913,7 +910,7 @@ ksmdbgssnCtrlCmdDebugClearAllSmErrorStates_IMPL if (IS_VIRTUAL_WITH_SRIOV(pGpu)) { NV_ASSERT_OK( - kgrctxClearMmuFault(pGpu, pKernelSMDebuggerSession->pObject->pKernelGraphicsContext)); + kgrctxClearMmuFault(pGpu, kgrobjGetKernelGraphicsContext(pGpu, pKernelSMDebuggerSession->pObject))); } return rmStatus; @@ -958,7 +955,7 @@ ksmdbgssnCtrlCmdDebugReadMMUFaultInfo_IMPL NV_ASSERT_OK_OR_RETURN( kgrctxLookupMmuFaultInfo(pGpu, - pKernelSMDebuggerSession->pObject->pKernelGraphicsContext, + kgrobjGetKernelGraphicsContext(pGpu, pKernelSMDebuggerSession->pObject), pParams)); return NV_OK; diff --git a/src/nvidia/src/kernel/gpu/gsp/arch/ampere/kernel_gsp_ga102.c b/src/nvidia/src/kernel/gpu/gsp/arch/ampere/kernel_gsp_ga102.c index 39b0beb063..3409f3c481 100644 --- a/src/nvidia/src/kernel/gpu/gsp/arch/ampere/kernel_gsp_ga102.c +++ b/src/nvidia/src/kernel/gpu/gsp/arch/ampere/kernel_gsp_ga102.c @@ -63,19 +63,20 @@ kgspConfigureFalcon_GA102 falconConfig.bIsPmcDeviceEngine = NV_FALSE; falconConfig.physEngDesc = ENG_GSP; - // Enable CrashCat monitoring - falconConfig.crashcatEngConfig.bEnable = NV_TRUE; - falconConfig.crashcatEngConfig.pName = MAKE_NV_PRINTF_STR("GSP"); - falconConfig.crashcatEngConfig.errorId = GSP_ERROR; ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu); - if (pCC != NULL && pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_CC_FEATURE_ENABLED)) - { - // No CrashCat queue when CC is enabled, as it's not encrypted - falconConfig.crashcatEngConfig.allocQueueSize = 0; - } - else + + // + // No CrashCat queue when CC is enabled, as it's not encrypted. + // Don't bother enabling the host-side decoding either, as CrashCat + // currently only supports sysmem queue reporting on GA10x+. + // + if (pCC == NULL || !pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_CC_FEATURE_ENABLED)) { + // Enable CrashCat monitoring + falconConfig.crashcatEngConfig.bEnable = NV_TRUE; + falconConfig.crashcatEngConfig.pName = MAKE_NV_PRINTF_STR("GSP"); + falconConfig.crashcatEngConfig.errorId = GSP_ERROR; falconConfig.crashcatEngConfig.allocQueueSize = RM_PAGE_SIZE; } diff --git a/src/nvidia/src/kernel/gpu/gsp/arch/hopper/kernel_gsp_gh100.c b/src/nvidia/src/kernel/gpu/gsp/arch/hopper/kernel_gsp_gh100.c index 22371e4a0b..ea701b3d9c 100644 --- a/src/nvidia/src/kernel/gpu/gsp/arch/hopper/kernel_gsp_gh100.c +++ b/src/nvidia/src/kernel/gpu/gsp/arch/hopper/kernel_gsp_gh100.c @@ -159,8 +159,10 @@ kgspAllocBootArgs_GH100 flags), _kgspAllocBootArgs_exit_cleanup); + memdescTagAlloc(nvStatus, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_56, + pKernelGsp->pGspFmcArgumentsDescriptor); NV_ASSERT_OK_OR_GOTO(nvStatus, - memdescAlloc(pKernelGsp->pGspFmcArgumentsDescriptor), + nvStatus, _kgspAllocBootArgs_exit_cleanup); NV_ASSERT_OK_OR_GOTO(nvStatus, diff --git a/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_tu102.c b/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_tu102.c index b5a7543714..bc43f498c9 100644 --- a/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_tu102.c +++ b/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_tu102.c @@ -37,6 +37,7 @@ #include "os/os.h" #include "nverror.h" #include "gsp/gsp_error.h" +#include "nvrm_registry.h" #include "crashcat/crashcat_report.h" #include "published/turing/tu102/dev_gsp.h" @@ -126,8 +127,9 @@ kgspAllocBootArgs_TU102 flags), _kgspAllocBootArgs_exit_cleanup); - NV_ASSERT_OK_OR_GOTO(nvStatus, - memdescAlloc(pKernelGsp->pWprMetaDescriptor), + memdescTagAlloc(nvStatus, NV_FB_ALLOC_RM_INTERNAL_OWNER_WPR_METADATA, + pKernelGsp->pWprMetaDescriptor); + NV_ASSERT_OK_OR_GOTO(nvStatus, nvStatus, _kgspAllocBootArgs_exit_cleanup); NV_ASSERT_OK_OR_GOTO(nvStatus, @@ -152,8 +154,9 @@ kgspAllocBootArgs_TU102 flags), _kgspAllocBootArgs_exit_cleanup); - NV_ASSERT_OK_OR_GOTO(nvStatus, - memdescAlloc(pKernelGsp->pLibosInitArgumentsDescriptor), + memdescTagAlloc(nvStatus, NV_FB_ALLOC_RM_INTERNAL_OWNER_LIBOS_ARGS, + pKernelGsp->pLibosInitArgumentsDescriptor); + NV_ASSERT_OK_OR_GOTO(nvStatus, nvStatus, _kgspAllocBootArgs_exit_cleanup); NV_ASSERT_OK_OR_GOTO(nvStatus, @@ -176,8 +179,9 @@ kgspAllocBootArgs_TU102 flags), _kgspAllocBootArgs_exit_cleanup); - NV_ASSERT_OK_OR_GOTO(nvStatus, - memdescAlloc(pKernelGsp->pGspArgumentsDescriptor), + memdescTagAlloc(nvStatus, NV_FB_ALLOC_RM_INTERNAL_OWNER_BOOTLOADER_ARGS, + pKernelGsp->pGspArgumentsDescriptor); + NV_ASSERT_OK_OR_GOTO(nvStatus, nvStatus, _kgspAllocBootArgs_exit_cleanup); NV_ASSERT_OK_OR_GOTO(nvStatus, @@ -514,6 +518,7 @@ kgspCalculateFbLayout_TU102 NvU64 vbiosReservedOffset; NvU64 mmuLockLo, mmuLockHi; NvBool bIsMmuLockValid; + NvU32 data; ct_assert(sizeof(*pWprMeta) == 256); @@ -628,11 +633,22 @@ kgspCalculateFbLayout_TU102 pWprMeta->sizeOfCrashReportQueue = (NvU32)memdescGetSize(pCrashCatQueueMemDesc); } + if ((osReadRegistryDword(pGpu, NV_REG_STR_RM_BOOT_GSPRM_WITH_BOOST_CLOCKS, &data) == NV_OK) && + (data == NV_REG_STR_RM_BOOT_GSPRM_WITH_BOOST_CLOCKS_DISABLED)) + { + pKernelGsp->bBootGspRmWithBoostClocks = NV_FALSE; + } + pWprMeta->bootCount = 0; pWprMeta->verified = 0; pWprMeta->revision = GSP_FW_WPR_META_REVISION; pWprMeta->magic = GSP_FW_WPR_META_MAGIC; + if (pKernelGsp->bBootGspRmWithBoostClocks) + { + pWprMeta->flags |= GSP_FW_FLAGS_CLOCK_BOOST; + } + #if 0 NV_PRINTF(LEVEL_ERROR, "WPR meta data offset: 0x%016llx\n", pWprMeta->gspFwWprStart); NV_PRINTF(LEVEL_ERROR, " magic: 0x%016llx\n", pWprMeta->magic); @@ -1062,7 +1078,7 @@ kgspSavePowerMgmtState_TU102 gspfwSRMeta.magic = GSP_FW_SR_META_MAGIC; gspfwSRMeta.revision = GSP_FW_SR_META_REVISION; gspfwSRMeta.sizeOfSuspendResumeData = pKernelGsp->pWprMeta->gspFwWprEnd - pKernelGsp->pWprMeta->gspFwWprStart; - + gspfwSRMeta.flags = pKernelGsp->pWprMeta->flags; NV_ASSERT_OK_OR_GOTO(nvStatus, kgspCreateRadix3(pGpu, @@ -1087,8 +1103,9 @@ kgspSavePowerMgmtState_TU102 MEMDESC_FLAGS_NONE), exit_fail_cleanup); - NV_ASSERT_OK_OR_GOTO(nvStatus, - memdescAlloc(pKernelGsp->pSRMetaDescriptor), + memdescTagAlloc(nvStatus, NV_FB_ALLOC_RM_INTERNAL_OWNER_SR_METADATA, + pKernelGsp->pSRMetaDescriptor); + NV_ASSERT_OK_OR_GOTO(nvStatus, nvStatus, exit_fail_cleanup); // Copy SR Metadata Structure diff --git a/src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c b/src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c index b8a24fc681..3dc93c43d2 100644 --- a/src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c +++ b/src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c @@ -60,7 +60,6 @@ #include "kernel/gpu/pmu/kern_pmu.h" #include "gpu/perf/kern_perf.h" #include "core/locks.h" -#include "kernel/gpu/intr/intr.h" #define RPC_STRUCTURES #define RPC_GENERIC_UNION @@ -401,22 +400,11 @@ _kgspRpcRCTriggered CHID_MGR *pChidMgr; NvU32 status = NV_OK; RM_ENGINE_TYPE rmEngineType = gpuGetRmEngineType(rpc_params->nv2080EngineType); + NvBool bIsCcEnabled = NV_FALSE; // check if there's a PCI-E error pending either in device status or in AER krcCheckBusError_HAL(pGpu, pKernelRc); - // - // If we have received a special msg from GSP then ack back immediately - // that we are done writing notifiers since we would have already processed the - // other RC msgs that trigger notifier writes before this one. - // - if (rpc_params->exceptType == ROBUST_CHANNEL_FAST_PATH_ERROR) - { - NV_RM_RPC_ECC_NOTIFIER_WRITE_ACK(pGpu, status); - NV_ASSERT_OK(status); - return status; - } - status = kfifoGetChidMgrFromType(pGpu, pKernelFifo, ENGINE_INFO_TYPE_RM_ENGINE_TYPE, (NvU32)rmEngineType, @@ -431,8 +419,10 @@ _kgspRpcRCTriggered pKernelChannel != NULL, NV_ERR_INVALID_CHANNEL); + bIsCcEnabled = gpuIsCCFeatureEnabled(pGpu); + // With CC enabled, CPU-RM needs to write error notifiers - if (gpuIsCCFeatureEnabled(pGpu)) + if (bIsCcEnabled) { NV_ASSERT_OK_OR_RETURN(krcErrorSetNotifier(pGpu, pKernelRc, pKernelChannel, @@ -728,15 +718,13 @@ _kgspRpcSimRead NvU32 i; KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); - OBJSYS *pSys = SYS_GET_INSTANCE(); - OBJOS *pOS = SYS_GET_OS(pSys); NV_ASSERT_OR_RETURN(rpc_params->count <= sizeof(pKernelGsp->pSimAccessBuf->data), NV_ERR_BUFFER_TOO_SMALL); for (i = rpc_params->index; i < count; i++) { NvU32 data; - pOS->osSimEscapeRead(pGpu, rpc_params->path, i, 4, &data); + gpuSimEscapeRead(pGpu, rpc_params->path, i, 4, &data); pKernelGsp->pSimAccessBuf->data[i] = data; } @@ -758,10 +746,8 @@ _kgspRpcSimWrite if (IS_SIMULATION(pGpu)) { KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); - OBJSYS *pSys = SYS_GET_INSTANCE(); - OBJOS *pOS = SYS_GET_OS(pSys); - pOS->osSimEscapeWrite(pGpu, rpc_params->path, rpc_params->index, rpc_params->count, rpc_params->data); + gpuSimEscapeWrite(pGpu, rpc_params->path, rpc_params->index, rpc_params->count, rpc_params->data); pKernelGsp->pSimAccessBuf->seq++; return NV_OK; } @@ -778,18 +764,23 @@ _kgspRpcSemaphoreScheduleCallback( RPC_PARAMS(semaphore_schedule_callback, _v17_00); NV_STATUS status; RsClient *pClient; + Device *pDevice; status = serverGetClientUnderLock(&g_resServ, rpc_params->hClient, &pClient); if (status != NV_OK) return status; + status = deviceGetByHandle(pClient, rpc_params->hEvent, &pDevice); + if (status != NV_OK) + return status; + return dispswReleaseSemaphoreAndNotifierFill(pGpu, rpc_params->GPUVA, rpc_params->hVASpace, rpc_params->ReleaseValue, rpc_params->Flags, rpc_params->completionStatus, - pClient, rpc_params->hEvent); + pDevice); } static NV_STATUS @@ -801,18 +792,23 @@ _kgspRpcTimedSemaphoreRelease( RPC_PARAMS(timed_semaphore_release, _v01_00); NV_STATUS status; RsClient *pClient; + Device *pDevice; status = serverGetClientUnderLock(&g_resServ, rpc_params->hClient, &pClient); if (status != NV_OK) return status; + status = deviceGetByHandle(pClient, rpc_params->hDevice, &pDevice); + if (status != NV_OK) + return status; + return tsemaRelease_HAL(pGpu, rpc_params->semaphoreVA, rpc_params->notifierVA, rpc_params->hVASpace, rpc_params->releaseValue, rpc_params->completionStatus, - pClient); + pDevice); } @@ -891,23 +887,6 @@ _kgspRpcGspExtdevIntrService return NV_OK; } -static void -_kgspRpcGspSendUserSharedData -( - OBJGPU *pGpu, - OBJRPC *pRpc -) -{ - RPC_PARAMS(gsp_send_user_shared_data, _v17_00); - NV00DE_SHARED_DATA *pSharedData = gpushareddataWriteStart(pGpu); - GspUserSharedData *pRpcData = (GspUserSharedData*)(&rpc_params->data); - - // Copy over all GSP-owned data - pSharedData->gspAssertCount = pRpcData->gspAssertCount; - - gpushareddataWriteFinish(pGpu); -} - static void _kgspRpcMigCiConfigUpdateCallback ( NvU32 gpuInstance, @@ -933,7 +912,6 @@ _kgspRpcMigCiConfigUpdate ) { NV_STATUS status; - OBJOS *pOS = GPU_GET_OS(pGpu); struct MIG_CI_UPDATE_CALLBACK_PARAMS *pParams; RPC_PARAMS(vgpu_gsp_mig_ci_config, _v21_03); @@ -952,10 +930,10 @@ _kgspRpcMigCiConfigUpdate rpc_params->execPartId, (sizeof(NvU32) * rpc_params->execPartCount)); pParams->gfid = rpc_params->gfid; pParams->bDelete = rpc_params->bDelete; - status = pOS->osQueueWorkItemWithFlags(pGpu, - _kgspRpcMigCiConfigUpdateCallback, - (void *)pParams, - OS_QUEUE_WORKITEM_FLAGS_LOCK_API_RW | OS_QUEUE_WORKITEM_FLAGS_LOCK_GPUS_RW); + status = osQueueWorkItemWithFlags(pGpu, + _kgspRpcMigCiConfigUpdateCallback, + (void *)pParams, + OS_QUEUE_WORKITEM_FLAGS_LOCK_API_RW | OS_QUEUE_WORKITEM_FLAGS_LOCK_GPUS_RW); if (status != NV_OK) { portMemFree(pParams); @@ -1194,10 +1172,6 @@ _kgspProcessRpcEvent nvStatus = _kgspRpcMigCiConfigUpdate(pGpu, pRpc); break; - case NV_VGPU_MSG_EVENT_GSP_SEND_USER_SHARED_DATA: - _kgspRpcGspSendUserSharedData(pGpu, pRpc); - break; - case NV_VGPU_MSG_EVENT_GSP_LOCKDOWN_NOTICE: _kgspRpcGspLockdownNotice(pGpu, pRpc); break; @@ -1702,6 +1676,24 @@ _kgspGenerateInitArgId(const char *name) return id; } +static void +_kgspUnmapTaskLogBuf(OBJGPU *pGpu, RM_LIBOS_LOG_MEM *pLog) +{ + // release log memory for this task. + if (pLog->pTaskLogBuffer != NULL) + { + memdescUnmapInternal(pGpu, pLog->pTaskLogDescriptor, TRANSFER_FLAGS_NONE); + pLog->pTaskLogBuffer = NULL; + } + + if (pLog->pTaskLogDescriptor != NULL) + { + memdescFree(pLog->pTaskLogDescriptor); + memdescDestroy(pLog->pTaskLogDescriptor); + pLog->pTaskLogDescriptor = NULL; + } +} + /*! * Free vgpu partition LIBOS task logging structures */ @@ -1713,40 +1705,19 @@ _kgspFreeLibosVgpuPartitionLoggingStructures NvU32 gfid ) { - libosLogDestroy(&pKernelGsp->logDecodeVgpuPartition[gfid - 1]); - - // release the vgpu task log buffer memory - RM_LIBOS_LOG_MEM *pGspPluginVgpuTaskLog = &pKernelGsp->gspPluginVgpuTaskLogMem[gfid - 1]; - - if (pGspPluginVgpuTaskLog->pTaskLogBuffer != NULL) - { - memdescUnmapInternal(pGpu, pGspPluginVgpuTaskLog->pTaskLogDescriptor, TRANSFER_FLAGS_NONE); - - pGspPluginVgpuTaskLog->pTaskLogBuffer = NULL; - } - - if (pGspPluginVgpuTaskLog->pTaskLogDescriptor != NULL) + RM_LIBOS_LOG_MEM *vgpuLogBuffers[] = { - memdescFree(pGspPluginVgpuTaskLog->pTaskLogDescriptor); - memdescDestroy(pGspPluginVgpuTaskLog->pTaskLogDescriptor); - pGspPluginVgpuTaskLog->pTaskLogDescriptor = NULL; - } - - // release the init task log buffer memory - RM_LIBOS_LOG_MEM *pGspPluginInitTaskLog = &pKernelGsp->gspPluginInitTaskLogMem[gfid - 1]; - - if (pGspPluginInitTaskLog->pTaskLogBuffer != NULL) - { - memdescUnmapInternal(pGpu, pGspPluginInitTaskLog->pTaskLogDescriptor, TRANSFER_FLAGS_NONE); + pKernelGsp->gspPluginInitTaskLogMem, + pKernelGsp->gspPluginVgpuTaskLogMem + }; - pGspPluginInitTaskLog->pTaskLogBuffer = NULL; - } + libosLogDestroy(&pKernelGsp->logDecodeVgpuPartition[gfid - 1]); - if (pGspPluginInitTaskLog->pTaskLogDescriptor != NULL) + // release all the vgpu tasks' log buffer memory + for (NvU32 i = 0; i < NV_ARRAY_ELEMENTS(vgpuLogBuffers); ++i) { - memdescFree(pGspPluginInitTaskLog->pTaskLogDescriptor); - memdescDestroy(pGspPluginInitTaskLog->pTaskLogDescriptor); - pGspPluginInitTaskLog->pTaskLogDescriptor = NULL; + RM_LIBOS_LOG_MEM *pTaskLog = &vgpuLogBuffers[i][gfid - 1]; + _kgspUnmapTaskLogBuf(pGpu, pTaskLog); } } @@ -1790,9 +1761,23 @@ kgspInitVgpuPartitionLogging_IMPL NvU64 vgpuTaskLogBuffSize ) { + struct + { + const char *szMemoryId; + const char *szPrefix; + const char *elfSectionName; + NvU64 bufOffset; + NvU64 bufSize; + RM_LIBOS_LOG_MEM *taskLogArr; + } logInitValues[] = + { + {"LOGINIT", "INIT", ".fwlogging_init", initTaskLogBUffOffset, initTaskLogBUffSize, pKernelGsp->gspPluginInitTaskLogMem}, + {"LOGVGPU", "VGPU", ".fwlogging_vgpu", vgpuTaskLogBUffOffset, vgpuTaskLogBuffSize, pKernelGsp->gspPluginVgpuTaskLogMem} + }; + ct_assert(NV_ARRAY_ELEMENTS(logInitValues) <= LIBOS_LOG_MAX_LOGS); + NV_STATUS nvStatus = NV_OK; - RM_LIBOS_LOG_MEM *pGspPluginVgpuTaskLog = NULL; - RM_LIBOS_LOG_MEM *pGspPluginInitTaskLog = NULL; + RM_LIBOS_LOG_MEM *pTaskLog = NULL; char vm_string[8], sourceName[SOURCE_NAME_MAX_LENGTH]; if (gfid > MAX_PARTITIONS_WITH_GFID) @@ -1807,91 +1792,45 @@ kgspInitVgpuPartitionLogging_IMPL nvDbgSnprintf(sourceName, SOURCE_NAME_MAX_LENGTH, "V%02d", gfid); libosLogCreateEx(&pKernelGsp->logDecodeVgpuPartition[gfid - 1], sourceName); - // Setup logging for vgpu task in vgpu partition + // Setup logging for each task in vgpu partition + for (NvU32 i = 0; i < NV_ARRAY_ELEMENTS(logInitValues); ++i) { - pGspPluginVgpuTaskLog = &pKernelGsp->gspPluginVgpuTaskLogMem[gfid - 1]; + pTaskLog = &logInitValues[i].taskLogArr[gfid - 1]; NvP64 pVa = NvP64_NULL; - NV_ASSERT_OK_OR_GOTO(nvStatus, - memdescCreate(&pGspPluginVgpuTaskLog->pTaskLogDescriptor, + memdescCreate(&pTaskLog->pTaskLogDescriptor, pGpu, - vgpuTaskLogBuffSize, + logInitValues[i].bufSize, RM_PAGE_SIZE, NV_TRUE, ADDR_FBMEM, NV_MEMORY_CACHED, MEMDESC_FLAGS_NONE), error_cleanup); + memdescDescribe(pTaskLog->pTaskLogDescriptor, ADDR_FBMEM, logInitValues[i].bufOffset, logInitValues[i].bufSize); - memdescDescribe(pGspPluginVgpuTaskLog->pTaskLogDescriptor, ADDR_FBMEM, vgpuTaskLogBUffOffset, vgpuTaskLogBuffSize); - - pVa = memdescMapInternal(pGpu, pGspPluginVgpuTaskLog->pTaskLogDescriptor, TRANSFER_FLAGS_NONE); - + pVa = memdescMapInternal(pGpu, pTaskLog->pTaskLogDescriptor, TRANSFER_FLAGS_NONE); if (pVa != NvP64_NULL) { - pGspPluginVgpuTaskLog->pTaskLogBuffer = pVa; - portMemSet(pGspPluginVgpuTaskLog->pTaskLogBuffer, 0, vgpuTaskLogBuffSize); + pTaskLog->pTaskLogBuffer = pVa; + portMemSet(pTaskLog->pTaskLogBuffer, 0, logInitValues[i].bufSize); - pGspPluginVgpuTaskLog->id8 = _kgspGenerateInitArgId("LOGVGPU"); + pTaskLog->id8 = _kgspGenerateInitArgId(logInitValues[i].szMemoryId); - nvDbgSnprintf(vm_string, sizeof(vm_string), "VGPU%d", gfid); + nvDbgSnprintf(vm_string, sizeof(vm_string), "%s%d", logInitValues[i].szPrefix, gfid); libosLogAddLogEx(&pKernelGsp->logDecodeVgpuPartition[gfid - 1], - pGspPluginVgpuTaskLog->pTaskLogBuffer, - memdescGetSize(pGspPluginVgpuTaskLog->pTaskLogDescriptor), + pTaskLog->pTaskLogBuffer, + memdescGetSize(pTaskLog->pTaskLogDescriptor), pGpu->gpuInstance, (gpuGetChipArch(pGpu) >> GPU_ARCH_SHIFT), gpuGetChipImpl(pGpu), vm_string, - ".fwlogging_vgpu"); + logInitValues[i].elfSectionName); } else { - NV_PRINTF(LEVEL_ERROR, "Failed to map memory for vgpu task log buffer for vGPU partition \n"); - nvStatus = NV_ERR_INSUFFICIENT_RESOURCES; - goto error_cleanup; - } - } - - // Setup logging for init task in vgpu partition - { - pGspPluginInitTaskLog = &pKernelGsp->gspPluginInitTaskLogMem[gfid - 1]; - NvP64 pVa = NvP64_NULL; - - NV_ASSERT_OK_OR_GOTO(nvStatus, - memdescCreate(&pGspPluginInitTaskLog->pTaskLogDescriptor, - pGpu, - initTaskLogBUffSize, - RM_PAGE_SIZE, - NV_TRUE, ADDR_FBMEM, NV_MEMORY_CACHED, - MEMDESC_FLAGS_NONE), - error_cleanup); - - memdescDescribe(pGspPluginInitTaskLog->pTaskLogDescriptor, ADDR_FBMEM, initTaskLogBUffOffset, initTaskLogBUffSize); - - pVa = memdescMapInternal(pGpu, pGspPluginInitTaskLog->pTaskLogDescriptor, TRANSFER_FLAGS_NONE); - - if (pVa != NvP64_NULL) - { - pGspPluginInitTaskLog->pTaskLogBuffer = pVa; - portMemSet(pGspPluginInitTaskLog->pTaskLogBuffer, 0, initTaskLogBUffSize); - - pGspPluginInitTaskLog->id8 = _kgspGenerateInitArgId("LOGINIT"); - - nvDbgSnprintf(vm_string, sizeof(vm_string), "INIT%d", gfid); - - libosLogAddLogEx(&pKernelGsp->logDecodeVgpuPartition[gfid - 1], - pGspPluginInitTaskLog->pTaskLogBuffer, - memdescGetSize(pGspPluginInitTaskLog->pTaskLogDescriptor), - pGpu->gpuInstance, - (gpuGetChipArch(pGpu) >> GPU_ARCH_SHIFT), - gpuGetChipImpl(pGpu), - vm_string, - ".fwlogging_init"); - } - else - { - NV_PRINTF(LEVEL_ERROR, "Failed to map memory for init task log buffer for vGPU partition \n"); + NV_PRINTF(LEVEL_ERROR, "Failed to map memory for %s task log buffer for vGPU partition \n", logInitValues[i].szPrefix); nvStatus = NV_ERR_INSUFFICIENT_RESOURCES; goto error_cleanup; } @@ -1995,15 +1934,15 @@ _kgspInitLibosLoggingStructures const char *elfSectionName; } logInitValues[] = { - {"LOGINIT", "INIT", 0x10000, ".fwlogging_init"}, // 64KB for stack traces + {"LOGINIT", "INIT", 0x10000, ".fwlogging_init"}, // 64KB for stack traces #if defined(DEVELOP) || defined(DEBUG) // The interrupt task is in the rm elf, so they share the same logging elf too {"LOGINTR", "INTR", 0x40000, ".fwlogging_rm"}, // 256KB ISR debug log on develop/debug builds - {"LOGRM", "RM", 0x40000, ".fwlogging_rm"} // 256KB RM debug log on develop/debug builds + {"LOGRM", "RM", 0x40000, ".fwlogging_rm"} // 256KB RM debug log on develop/debug builds #else // The interrupt task is in the rm elf, so they share the same logging elf too {"LOGINTR", "INTR", 0x10000, ".fwlogging_rm"}, // 64KB ISR debug log on develop/debug builds - {"LOGRM", "RM", 0x10000, ".fwlogging_rm"} // 64KB RM debug log on release builds + {"LOGRM", "RM", 0x10000, ".fwlogging_rm"} // 64KB RM debug log on release builds #endif }; ct_assert(NV_ARRAY_ELEMENTS(logInitValues) <= LIBOS_LOG_MAX_LOGS); @@ -2040,8 +1979,9 @@ _kgspInitLibosLoggingStructures flags), error_cleanup); - NV_ASSERT_OK_OR_GOTO(nvStatus, - memdescAlloc(pLog->pTaskLogDescriptor), + memdescTagAlloc(nvStatus, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_12, pLog->pTaskLogDescriptor); + NV_ASSERT_OK_OR_GOTO(nvStatus, nvStatus, error_cleanup); NV_ASSERT_OK_OR_GOTO(nvStatus, @@ -2147,9 +2087,9 @@ _kgspAllocSimAccessBuffer(OBJGPU *pGpu, KernelGsp *pKernelGsp) MEMDESC_FLAGS_NONE), error_cleanup); - NV_ASSERT_OK_OR_GOTO(nvStatus, - memdescAlloc(pKernelGsp->pMemDesc_simAccessBuf), - error_cleanup); + memdescTagAlloc(nvStatus, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_13, pKernelGsp->pMemDesc_simAccessBuf); + NV_ASSERT_OK_OR_GOTO(nvStatus, nvStatus, error_cleanup); NV_ASSERT_OK_OR_GOTO(nvStatus, memdescMap(pKernelGsp->pMemDesc_simAccessBuf, 0, @@ -2810,9 +2750,9 @@ kgspPrepareBootBinaryImage_IMPL flags), fail); - NV_ASSERT_OK_OR_GOTO(status, - memdescAlloc(pKernelGsp->pGspRmBootUcodeMemdesc), - fail); + memdescTagAlloc(status, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_15, pKernelGsp->pGspRmBootUcodeMemdesc); + NV_ASSERT_OK_OR_GOTO(status, status, fail); NV_ASSERT_OK_OR_GOTO(status, memdescMap(pKernelGsp->pGspRmBootUcodeMemdesc, 0, @@ -2903,8 +2843,9 @@ _kgspCreateSignatureMemdesc NV_ALIGN_UP(pGspFw->signatureSize, 256), 256, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_CACHED, flags)); - NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, - memdescAlloc(pKernelGsp->pSignatureMemdesc), fail_create); + memdescTagAlloc(status, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_16, pKernelGsp->pSignatureMemdesc); + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, status, fail_create); pSignatureVa = memdescMapInternal(pGpu, pKernelGsp->pSignatureMemdesc, TRANSFER_FLAGS_NONE); NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, @@ -3164,7 +3105,9 @@ kgspCreateRadix3_IMPL flags), done); - NV_ASSERT_OK_OR_GOTO(status, memdescAlloc(*ppMemdescRadix3), error_ret); + memdescTagAlloc(status, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_17, (*ppMemdescRadix3)); + NV_ASSERT_OK_OR_GOTO(status, status, error_ret); // Create kernel mapping. NV_ASSERT_OK_OR_GOTO(status, @@ -3732,7 +3675,7 @@ _kgspCalculateFwHeapSize // factor here. Instead, it's just extra margin to keep us from exhausting // the heap at runtime. // - NvU64 heapSize = pKernelGsp->fwHeapParamOsCarveoutSize + + NvU64 heapSize = kgspGetFwHeapParamOsCarveoutSize_HAL(pGpu, pKernelGsp) + pKernelGsp->fwHeapParamBaseSize + NV_ALIGN_UP(GSP_FW_HEAP_PARAM_SIZE_PER_GB_FB * fbSizeGB, 1 << 20) + NV_ALIGN_UP(GSP_FW_HEAP_PARAM_CLIENT_ALLOC_SIZE, 1 << 20); diff --git a/src/nvidia/src/kernel/gpu/gsp/kernel_gsp_booter.c b/src/nvidia/src/kernel/gpu/gsp/kernel_gsp_booter.c index 607ff7dc17..5b3c987383 100644 --- a/src/nvidia/src/kernel/gpu/gsp/kernel_gsp_booter.c +++ b/src/nvidia/src/kernel/gpu/gsp/kernel_gsp_booter.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -341,7 +341,8 @@ s_allocateUcodeFromBinArchive memdescCreate(&pUcode->pUcodeMemDesc, pGpu, pUcode->size, 16, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_UNCACHED, MEMDESC_FLAGS_NONE), out); - status = memdescAlloc(pUcode->pUcodeMemDesc); + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_57, + pUcode->pUcodeMemDesc); if (status != NV_OK) { goto out; diff --git a/src/nvidia/src/kernel/gpu/gsp/kernel_gsp_fwsec.c b/src/nvidia/src/kernel/gpu/gsp/kernel_gsp_fwsec.c index 2361d187e7..e3788498b1 100644 --- a/src/nvidia/src/kernel/gpu/gsp/kernel_gsp_fwsec.c +++ b/src/nvidia/src/kernel/gpu/gsp/kernel_gsp_fwsec.c @@ -791,13 +791,15 @@ s_vbiosFillFlcnUcodeFromDescV2 memdescCreate(&pUcode->pDataMemDesc, pGpu, dataSizeAligned, 256, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_UNCACHED, MEMDESC_FLAGS_PHYSICALLY_CONTIGUOUS)); - status = memdescAlloc(pUcode->pCodeMemDesc); + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_9, + pUcode->pCodeMemDesc); if (status != NV_OK) { return status; } - status = memdescAlloc(pUcode->pDataMemDesc); + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_10, + pUcode->pDataMemDesc); if (status != NV_OK) { return status; @@ -969,7 +971,8 @@ s_vbiosFillFlcnUcodeFromDescV3 memdescCreate(&pUcode->pUcodeMemDesc, pGpu, pUcode->size, 256, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_UNCACHED, MEMDESC_FLAGS_NONE)); - status = memdescAlloc(pUcode->pUcodeMemDesc); + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_11, + pUcode->pUcodeMemDesc); if (status != NV_OK) { return status; diff --git a/src/nvidia/src/kernel/gpu/gsp/message_queue_cpu.c b/src/nvidia/src/kernel/gpu/gsp/message_queue_cpu.c index 514b5fd56c..525c785c8b 100644 --- a/src/nvidia/src/kernel/gpu/gsp/message_queue_cpu.c +++ b/src/nvidia/src/kernel/gpu/gsp/message_queue_cpu.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -256,9 +256,9 @@ GspMsgQueuesInit memdescSetFlag(pMQCollection->pSharedMemDesc, MEMDESC_FLAGS_KERNEL_MODE, NV_TRUE); - NV_ASSERT_OK_OR_GOTO(nvStatus, - memdescAlloc(pMQCollection->pSharedMemDesc), - error_ret); + memdescTagAlloc(nvStatus, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_58, + pMQCollection->pSharedMemDesc); + NV_ASSERT_OK_OR_GOTO(nvStatus, nvStatus, error_ret); // Create kernel mapping for command queue. NV_ASSERT_OK_OR_GOTO(nvStatus, diff --git a/src/nvidia/src/kernel/gpu/hwpm/profiler_v2/kern_profiler_v2.c b/src/nvidia/src/kernel/gpu/hwpm/profiler_v2/kern_profiler_v2.c index 2ecc213bd4..f05271246b 100644 --- a/src/nvidia/src/kernel/gpu/hwpm/profiler_v2/kern_profiler_v2.c +++ b/src/nvidia/src/kernel/gpu/hwpm/profiler_v2/kern_profiler_v2.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -41,16 +41,17 @@ _isDeviceProfilingPermitted(OBJGPU *pGpu, ProfilerBase *pProf, API_SECURITY_INFO } static NvBool -_isMemoryProfilingPermitted(OBJGPU *pGpu, ProfilerBase *pProf, NvHandle hClient) +_isMemoryProfilingPermitted(OBJGPU *pGpu, ProfilerBase *pProf) { NvBool bSmcGpuPartitioningEnabled = IS_MIG_IN_USE(pGpu); KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + Device *pDevice = GPU_RES_GET_DEVICE(pProf); - if (bSmcGpuPartitioningEnabled && !kmigmgrIsClientUsingDeviceProfiling(pGpu, pKernelMIGManager, hClient)) + if (bSmcGpuPartitioningEnabled && !kmigmgrIsDeviceUsingDeviceProfiling(pGpu, pKernelMIGManager, pDevice)) { MIG_INSTANCE_REF ref; - if (kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, &ref) != NV_OK) + if (kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, &ref) != NV_OK) return NV_FALSE; if (!kmigmgrIsMIGReferenceValid(&ref)) @@ -116,11 +117,10 @@ profilerDevQueryCapabilities_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pProfDev); ProfilerBase *pProfBase = staticCast(pProfDev, ProfilerBase); API_SECURITY_INFO *pSecInfo = pParams->pSecInfo; - NvHandle hClient = pCallContext->pClient->hClient; NvBool bAnyProfilingPermitted = NV_FALSE; pClientPermissions->bMemoryProfilingPermitted = - _isMemoryProfilingPermitted(pGpu, pProfBase, hClient); + _isMemoryProfilingPermitted(pGpu, pProfBase); pClientPermissions->bAdminProfilingPermitted = NV_FALSE; if (pSecInfo->privLevel >= RS_PRIV_LEVEL_USER_ROOT) diff --git a/src/nvidia/src/kernel/gpu/hwpm/profiler_v2/kern_profiler_v2_ctrl.c b/src/nvidia/src/kernel/gpu/hwpm/profiler_v2/kern_profiler_v2_ctrl.c index c63a51af6c..b9546c5453 100644 --- a/src/nvidia/src/kernel/gpu/hwpm/profiler_v2/kern_profiler_v2_ctrl.c +++ b/src/nvidia/src/kernel/gpu/hwpm/profiler_v2/kern_profiler_v2_ctrl.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -298,6 +298,7 @@ profilerBaseCtrlCmdAllocPmaStream_IMPL &internalParams, sizeof(internalParams)), fail); pParams->pmaChannelIdx = internalParams.pmaChannelIdx; + if (serverutilGetResourceRef(hClient, pParams->hMemPmaBytesAvailable, &pMemoryRef) == NV_OK && serverutilGetResourceRef(hClient, pParams->hMemPmaBuffer, &pMemoryRef) == NV_OK) { diff --git a/src/nvidia/src/kernel/gpu/intr/intr.c b/src/nvidia/src/kernel/gpu/intr/intr.c index 0822a114f7..b158d96156 100644 --- a/src/nvidia/src/kernel/gpu/intr/intr.c +++ b/src/nvidia/src/kernel/gpu/intr/intr.c @@ -166,16 +166,6 @@ subdeviceCtrlCmdMcServiceInterrupts_IMPL RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams; NV_STATUS status = NV_OK; - // - // Force kernel-RM to service interrupts from GSP-RM. This will allow - // kernel-RM to write notifiers and send an ack back to GSP. - // GSP waits for this ack before clearing fast path POSSIBLE_ERR interrupt. - // - if (pGpu->getProperty(pGpu, PDB_PROP_GPU_FASTPATH_SEQ_ENABLED)) - { - intrServiceStallSingle_HAL(pGpu, pIntr, MC_ENGINE_IDX_GSP, NV_TRUE); - } - NV_RM_RPC_CONTROL(pGpu, pRmCtrlParams->hClient, pRmCtrlParams->hObject, pRmCtrlParams->cmd, pRmCtrlParams->pParams, pRmCtrlParams->paramsSize, status); if (status != NV_OK) @@ -1238,6 +1228,13 @@ intrDestroyInterruptTable_IMPL Intr *pIntr ) { + for (INTR_TREE tree = 0; tree < NV_ARRAY_ELEMENTS(pIntr->vectorToMcIdx); + ++tree) + { + portMemFree(pIntr->vectorToMcIdx[tree]); + pIntr->vectorToMcIdx[tree] = NULL; + pIntr->vectorToMcIdxCounts[tree] = 0; + } vectDestroy(&pIntr->intrTable); return NV_OK; } @@ -1434,14 +1431,14 @@ _intrServiceStallExactList if (bRequiresPossibleErrorNotifier) { - if (pGpu->getProperty(pGpu, PDB_PROP_GPU_FASTPATH_SEQ_ENABLED)) - { - } - else - { - // info32 contains shadowed value of ERR_CONT - gpuNotifySubDeviceEvent(pGpu, NV2080_NOTIFIERS_POSSIBLE_ERROR, NULL, 0, intrReadErrCont_HAL(pGpu, pIntr), 0); - } + // + // Notify CUDA there may be an error in ERR_CONT that they may miss because we're + // about to clear it out of the NV_CTRL tree backing ERR_CONT before the interrupt + // is serviced. + // + // info32 contains shadowed value of ERR_CONT + // + gpuNotifySubDeviceEvent(pGpu, NV2080_NOTIFIERS_POSSIBLE_ERROR, NULL, 0, intrReadErrCont_HAL(pGpu, pIntr), 0); } for (iter = vectIterAll(pIntrTable); vectIterNext(&iter);) @@ -1496,10 +1493,14 @@ _intrServiceStallExactList if (bRequiresPossibleErrorNotifier) { - { - // info32 contains shadowed value of ERR_CONT - gpuNotifySubDeviceEvent(pGpu, NV2080_NOTIFIERS_POSSIBLE_ERROR, NULL, 0, intrReadErrCont_HAL(pGpu, pIntr), 0); - } + // + // Notify CUDA there may be an error in ERR_CONT that they may miss because we're + // about to clear it out of the NV_CTRL tree backing ERR_CONT before the interrupt + // is serviced. + // + // info32 contains shadowed value of ERR_CONT + // + gpuNotifySubDeviceEvent(pGpu, NV2080_NOTIFIERS_POSSIBLE_ERROR, NULL, 0, intrReadErrCont_HAL(pGpu, pIntr), 0); } if (bIntrStuck) @@ -1731,3 +1732,26 @@ intrGetIntrTopLockedMask_IMPL NV_ASSERT(ret != 0); return ret; } + + +NV_STATUS intrSetInterruptEntry_IMPL +( + Intr *pIntr, + INTR_TREE tree, + NvU32 vector, + const InterruptEntry *pEntry +) +{ + NV_ASSERT_OR_RETURN(pEntry != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(tree < NV_ARRAY_ELEMENTS(pIntr->vectorToMcIdx), + NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pIntr->vectorToMcIdx[tree] != NULL, + NV_ERR_INVALID_STATE); + NV_ASSERT_OR_RETURN(vector < pIntr->vectorToMcIdxCounts[tree], + NV_ERR_INVALID_STATE); + NV_ASSERT_OR_RETURN( + pIntr->vectorToMcIdx[tree][vector].mcEngine == MC_ENGINE_IDX_NULL, + NV_ERR_INVALID_STATE); + pIntr->vectorToMcIdx[tree][vector] = *pEntry; + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/kern_gpu_power.c b/src/nvidia/src/kernel/gpu/kern_gpu_power.c index fe16c2e34f..4263a6e7c5 100644 --- a/src/nvidia/src/kernel/gpu/kern_gpu_power.c +++ b/src/nvidia/src/kernel/gpu/kern_gpu_power.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2012-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2012-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -30,6 +30,7 @@ #include "diagnostics/tracer.h" #include "jt.h" #include "ctrl/ctrl2080/ctrl2080power.h" +#include "gpu/subdevice/subdevice.h" #include "g_journal_pb.h" @@ -201,7 +202,7 @@ gpuGc6Entry_IMPL( * NV_ERR Otherwise */ NV_STATUS -gpuGc6EntryGpuPowerOff(OBJGPU *pGpu) +gpuGc6EntryGpuPowerOff_IMPL(OBJGPU *pGpu) { NV_STATUS status = NV_OK; @@ -664,3 +665,49 @@ _gpuGc6ExitStateLoad(OBJGPU *pGpu, NV2080_CTRL_GC6_EXIT_PARAMS *pParams) return status; } +/*! + * @brief: This command executes the steps of GC6 entry sequence + * + * @param[in] pSubDevice + * @param[in] pParams + * + * @return + * NV_OK Success + * NV_ERR_INVALID_ARGUMENT Invalid action + * NV_ERR_NOT_SUPPORTED Chip doesn't support the feature + * NV_ERR_NOT_READY Chip not ready to execute operation + * NV_ERR_INVALID_STATE Chip unable to execute command at current state + * NV_ERR_TIMEOUT RM timed out when trying to complete call + * NV_ERR_GENERIC Generic error (bad state or stuck) + */ +NV_STATUS +subdeviceCtrlCmdGc6Entry_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_GC6_ENTRY_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + return gpuGc6Entry(pGpu, pParams); +} + +/*! + * @brief: This command executes the steps of GC6 exit sequence + * + * @param[in] pSubDevice + * @param[in] pParams + * + * @return + * NV_OK Success + * NV_ERR_GENERIC Generic error (bad state or stuck) + */ +NV_STATUS +subdeviceCtrlCmdGc6Exit_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_GC6_EXIT_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + return gpuGc6Exit(pGpu, pParams); +} diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/ampere/mem_mgr_ga100.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/ampere/mem_mgr_ga100.c index 9eae275558..bb7f7c465d 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/arch/ampere/mem_mgr_ga100.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/ampere/mem_mgr_ga100.c @@ -116,7 +116,7 @@ memmgrScrubRegistryOverrides_GA100 pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_VIRTUALIZATION_MODE_HOST_VGPU) || IS_VIRTUAL_WITHOUT_SRIOV(pGpu) || RMCFG_FEATURE_PLATFORM_GSP || - (pGpu->getProperty(pGpu, PDB_PROP_GPU_BROKEN_FB) && !gpuIsCacheOnlyModeEnabled(pGpu)) || + pGpu->getProperty(pGpu, PDB_PROP_GPU_BROKEN_FB) || IsSLIEnabled(pGpu)) { pMemoryManager->bScrubOnFreeEnabled = NV_FALSE; @@ -368,8 +368,8 @@ memmgrGetBlackListPages_GA100 while (baseIndex < NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_PAGES) { - RM_API *pRmApi = IS_GSP_CLIENT(pGpu) ? GPU_GET_PHYSICAL_RMAPI(pGpu) - : rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + portMemSet(pBlParams, 0, sizeof(*pBlParams)); pBlParams->baseIndex = baseIndex; @@ -500,7 +500,16 @@ memmgrIsApertureSupportedByFla_GA100 NV_ADDRESS_SPACE aperture ) { - if (aperture == ADDR_FBMEM) + // + // TODO: Bug 3802992: ADDR_EGM will be removed once the new design as part + // of bug 3802992 is implemented wherein EGM would be represented using + // ADDR_SYSMEM itself. + // + if ((aperture == ADDR_FBMEM) + || (aperture == ADDR_EGM) || + ((aperture == ADDR_SYSMEM) && + memmgrIsLocalEgmEnabled(pMemoryManager)) + ) { return NV_TRUE; } diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/fbsr_gm107.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/fbsr_gm107.c index 47377a0707..c92323d1e8 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/fbsr_gm107.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/fbsr_gm107.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2009-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -253,7 +253,8 @@ fbsrInit_GM107(OBJGPU *pGpu, OBJFBSR *pFbsr) goto fail; } - status = memdescAlloc(pFbsr->pSysMemDesc); + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_126, + pFbsr->pSysMemDesc); if (status != NV_OK) { NV_ASSERT(status == NV_OK); @@ -417,7 +418,8 @@ fbsrBegin_GM107(OBJGPU *pGpu, OBJFBSR *pFbsr, FBSR_OP_TYPE op) break; } - status = memdescAlloc(pFbsr->pSysMemDesc); + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_127, + pFbsr->pSysMemDesc); if (status != NV_OK) { NV_ASSERT(status == NV_OK); @@ -796,6 +798,7 @@ fbsrEnd_GM107(OBJGPU *pGpu, OBJFBSR *pFbsr) void fbsrCopyMemoryMemDesc_GM107(OBJGPU *pGpu, OBJFBSR *pFbsr, MEMORY_DESCRIPTOR *pVidMemDesc) { + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); NV_STATUS status = NV_OK; NV_ASSERT(!gpumgrGetBcEnabledStatus(pGpu)); @@ -867,7 +870,8 @@ fbsrCopyMemoryMemDesc_GM107(OBJGPU *pGpu, OBJFBSR *pFbsr, MEMORY_DESCRIPTOR *pVi MEMDESC_FLAGS_NONE); if (status == NV_OK) { - status = memdescAlloc(pStandbyBuffer); + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_128, + pStandbyBuffer); if (status != NV_OK ) { memdescDestroy(pStandbyBuffer); @@ -901,8 +905,17 @@ fbsrCopyMemoryMemDesc_GM107(OBJGPU *pGpu, OBJFBSR *pFbsr, MEMORY_DESCRIPTOR *pVi case FBSR_TYPE_PAGED_DMA: case FBSR_TYPE_DMA: { + TRANSFER_SURFACE vidSurface = {0}; + TRANSFER_SURFACE sysSurface = {0}; + + vidSurface.pMemDesc = pVidMemDesc; + sysSurface.pMemDesc = pFbsr->pSysMemDesc; + sysSurface.offset = pFbsr->sysOffset; + if (pFbsr->op == FBSR_OP_RESTORE) { + NV_ASSERT_OK(memmgrMemCopy(pMemoryManager, &vidSurface, &sysSurface, pVidMemDesc->Size, + TRANSFER_FLAGS_PREFER_CE | TRANSFER_FLAGS_CE_PRI_DEFER_FLUSH)); } else { @@ -912,16 +925,31 @@ fbsrCopyMemoryMemDesc_GM107(OBJGPU *pGpu, OBJFBSR *pFbsr, MEMORY_DESCRIPTOR *pVi pFbsr->sysOffset, pVidMemDesc, 0, pVidMemDesc->Size); } + else + { + NV_ASSERT_OK(memmgrMemCopy(pMemoryManager, &sysSurface, &vidSurface, pVidMemDesc->Size, + TRANSFER_FLAGS_PREFER_CE | TRANSFER_FLAGS_CE_PRI_DEFER_FLUSH)); + } } break; } case FBSR_TYPE_PERSISTENT: { + TRANSFER_SURFACE vidSurface = {0}; + TRANSFER_SURFACE sysSurface = {0}; + + vidSurface.pMemDesc = pVidMemDesc; + sysSurface.pMemDesc = memdescGetStandbyBuffer(pVidMemDesc); + if (pFbsr->op == FBSR_OP_RESTORE) { + NV_ASSERT_OK(memmgrMemCopy(pMemoryManager, &vidSurface, &sysSurface, pVidMemDesc->Size, + TRANSFER_FLAGS_PREFER_CE | TRANSFER_FLAGS_CE_PRI_DEFER_FLUSH)); } else { + NV_ASSERT_OK(memmgrMemCopy(pMemoryManager, &sysSurface, &vidSurface, pVidMemDesc->Size, + TRANSFER_FLAGS_PREFER_CE | TRANSFER_FLAGS_CE_PRI_DEFER_FLUSH)); } break; } @@ -976,11 +1004,20 @@ fbsrCopyMemoryMemDesc_GM107(OBJGPU *pGpu, OBJFBSR *pFbsr, MEMORY_DESCRIPTOR *pVi } } + TRANSFER_SURFACE vidSurface = {0}; + vidSurface.pMemDesc = pVidMemDesc; + vidSurface.offset = vidOffset; + + TRANSFER_SURFACE sysSurface = {0}; + sysSurface.pMemDesc = pFbsr->pSysMemDesc; + if (pFbsr->op == FBSR_OP_RESTORE) { + NV_ASSERT_OK(memmgrMemCopy(pMemoryManager, &vidSurface, &sysSurface, copySize, TRANSFER_FLAGS_PREFER_CE)); } else { + NV_ASSERT_OK(memmgrMemCopy(pMemoryManager, &sysSurface, &vidSurface, copySize, TRANSFER_FLAGS_PREFER_CE)); } if (pFbsr->op == FBSR_OP_SAVE) @@ -1071,11 +1108,20 @@ fbsrCopyMemoryMemDesc_GM107(OBJGPU *pGpu, OBJFBSR *pFbsr, MEMORY_DESCRIPTOR *pVi } } + TRANSFER_SURFACE vidSurface = {0}; + vidSurface.pMemDesc = pVidMemDesc; + vidSurface.offset = vidOffset; + + TRANSFER_SURFACE sysSurface = {0}; + sysSurface.pMemDesc = pFbsr->pSysMemDesc; + if (pFbsr->op == FBSR_OP_RESTORE) { + NV_ASSERT_OK(memmgrMemCopy(pMemoryManager, &vidSurface, &sysSurface, copySize, TRANSFER_FLAGS_PREFER_CE)); } else { + NV_ASSERT_OK(memmgrMemCopy(pMemoryManager, &sysSurface, &vidSurface, copySize, TRANSFER_FLAGS_PREFER_CE)); } if (pFbsr->op == FBSR_OP_SAVE) @@ -1123,11 +1169,20 @@ fbsrCopyMemoryMemDesc_GM107(OBJGPU *pGpu, OBJFBSR *pFbsr, MEMORY_DESCRIPTOR *pVi } } + TRANSFER_SURFACE vidSurface = {0}; + vidSurface.pMemDesc = pVidMemDesc; + vidSurface.offset = vidOffset; + + TRANSFER_SURFACE sysSurface = {0}; + sysSurface.pMemDesc = pFbsr->pSysMemDesc; + if (pFbsr->op == FBSR_OP_RESTORE) { + NV_ASSERT_OK(memmgrMemCopy(pMemoryManager, &vidSurface, &sysSurface, copySize, TRANSFER_FLAGS_PREFER_CE)); } else { + NV_ASSERT_OK(memmgrMemCopy(pMemoryManager, &sysSurface, &vidSurface, copySize, TRANSFER_FLAGS_PREFER_CE)); } if (pFbsr->op == FBSR_OP_SAVE) diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_cmn_gm107.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_cmn_gm107.c new file mode 100644 index 0000000000..d540d7db51 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_cmn_gm107.c @@ -0,0 +1,110 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2006-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "core/core.h" +#include "gpu/gpu.h" +#include "gpu/mem_mgr/mem_mgr.h" +#include "gpu/mem_sys/kern_mem_sys.h" +#include "gpu/mem_mgr/mem_desc.h" + +/* + * This function returns attributes associated with the memory object + * at the given offset. + */ +NV_STATUS +memmgrGetSurfacePhysAttr_GM107 +( + OBJGPU *pGpu, + MemoryManager *pMemoryManager, + Memory *pMemory, + NvU64 *pOffset, + NvU32 *pMemAperture, + NvU32 *pMemKind, + NvU32 *pComprOffset, + NvU32 *pComprKind, + NvU32 *pLineMin, + NvU32 *pLineMax, + NvU32 *pZCullId, + NvU32 *pGpuCacheAttr, + NvU32 *pGpuP2PCacheAttr, + NvU64 *contigSegmentSize +) +{ + NV_STATUS rmStatus; + PMEMORY_DESCRIPTOR pMemDesc = memdescGetMemDescFromGpu(pMemory->pMemDesc, pGpu); + COMPR_INFO comprInfo; + NvU32 unused; + + NV_ASSERT(pMemDesc); + + rmStatus = memdescFillMemdescForPhysAttr(pMemDesc, AT_GPU, pOffset, pMemAperture, + pMemKind, pZCullId, pGpuCacheAttr, pGpuP2PCacheAttr, + contigSegmentSize); + if (NV_OK != rmStatus) + { + return rmStatus; + } + + if ((!memmgrIsKind_HAL(pMemoryManager, FB_IS_KIND_COMPRESSIBLE, *pMemKind)) || + !FB_HWRESID_CTAGID_VAL_FERMI(memdescGetHwResId(pMemDesc))) + { + *pComprKind = 0; + return NV_OK; + } + + // vGPU: pPrivate->pCompTags is not + // currently initialized in the guest RM + // vGPU does not use compression tags yet. + // GSPTODO: sort out ctags + if (IS_VIRTUAL(pGpu) || IS_GSP_CLIENT(pGpu)) + { + *pComprOffset = 0x0; + *pLineMin = 0x0; + *pLineMax = 0x0; + return NV_OK; + } + + rmStatus = memmgrGetKindComprFromMemDesc(pMemoryManager, pMemDesc, 0, &unused, &comprInfo); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "dmaGetKidnCompr failed: %x\n", rmStatus); + return rmStatus; + } + + if (memmgrIsKind_HAL(pMemoryManager, FB_IS_KIND_COMPRESSIBLE, comprInfo.kind)) + { + *pLineMin = comprInfo.compTagLineMin; + *pLineMax = comprInfo.compPageIndexHi - comprInfo.compPageIndexLo + comprInfo.compTagLineMin; + *pComprOffset = comprInfo.compPageIndexLo; + *pComprKind = 1; + } + else + { + // No coverage at all (stripped by release/reacquire or invalid hw res). + *pLineMin = ~0; + *pLineMax = ~0; + *pComprKind = 0; + } + return NV_OK; +} + diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm107.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm107.c index 3a41486b89..5d01e3e6b2 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm107.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm107.c @@ -255,22 +255,38 @@ static void memmgrSetZbcReferenced ( OBJGPU *pGpu, + NvHandle hClient, + NvHandle hDevice, NvBool bZbcSurfacesExist ) { RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS params = {0}; + RsClient *pClient; + Subdevice *pSubdevice; + NvHandle hSubdevice; + NvU32 subDevInst; // Allocations are RPCed to host, so they are counted there if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu)) return; params.bZbcSurfacesExist = bZbcSurfacesExist; + + NV_ASSERT_OR_RETURN_VOID( + serverGetClientUnderLock(&g_resServ, hClient, &pClient) == NV_OK); + + subDevInst = gpumgrGetSubDeviceInstanceFromGpu(pGpu); + + NV_ASSERT_OR_RETURN_VOID(subdeviceGetByInstance(pClient, hDevice, subDevInst, &pSubdevice) == NV_OK); + + hSubdevice = RES_GET_HANDLE(pSubdevice); + NV_ASSERT_OK( pRmApi->Control( pRmApi, - pGpu->hInternalClient, - pGpu->hInternalSubdevice, + hClient, + hSubdevice, NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED, ¶ms, sizeof(params))); @@ -290,7 +306,7 @@ memmgrAllocHal_GM107 { KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); NV_STATUS status = NV_OK; - NvU32 comprAttr, tiledAttr, zcullAttr, type; + NvU32 comprAttr, zcullAttr, type; NvU32 cacheAttr; NvU32 format, kind, bAlignPhase; NvU32 retAttr = pFbAllocInfo->retAttr; @@ -302,7 +318,6 @@ memmgrAllocHal_GM107 // get the specified attribute values comprAttr = DRF_VAL(OS32, _ATTR, _COMPR, pFbAllocInfo->pageFormat->attr); - tiledAttr = DRF_VAL(OS32, _ATTR, _TILED, pFbAllocInfo->pageFormat->attr); zcullAttr = DRF_VAL(OS32, _ATTR, _ZCULL, pFbAllocInfo->pageFormat->attr); format = DRF_VAL(OS32, _ATTR, _FORMAT, pFbAllocInfo->pageFormat->attr); cacheAttr = DRF_VAL(OS32, _ATTR2, _GPU_CACHEABLE, pFbAllocInfo->pageFormat->attr2); @@ -321,9 +336,6 @@ memmgrAllocHal_GM107 // So the caller is urged to verify integrity. // if ( - // Tiling is not supported in nv50+ - (tiledAttr == NVOS32_ATTR_TILED_REQUIRED) || - (tiledAttr == NVOS32_ATTR_TILED_DEFERRED) || // check the value of compression attribute // attributes verification for compressed surfaces !(memmgrVerifyComprAttrs_HAL(pMemoryManager, type, format, comprAttr)) || @@ -335,9 +347,6 @@ memmgrAllocHal_GM107 return NV_ERR_INVALID_ARGUMENT; } - // Fermi does not support tiling - retAttr = FLD_SET_DRF(OS32, _ATTR, _TILED, _NONE, retAttr); - if (cacheAttr == NVOS32_ATTR2_GPU_CACHEABLE_DEFAULT) { // @@ -481,7 +490,7 @@ memmgrAllocHal_GM107 pMemoryManager->zbcSurfaces, pFbAllocInfo->hwResId); if (pMemoryManager->zbcSurfaces == 1) - memmgrSetZbcReferenced(pGpu, NV_TRUE); + memmgrSetZbcReferenced(pGpu, pFbAllocInfo->hClient, pFbAllocInfo->hDevice, NV_TRUE); } } else @@ -551,7 +560,7 @@ memmgrFreeHal_GM107 pMemoryManager->zbcSurfaces--; if (pMemoryManager->zbcSurfaces == 0) - memmgrSetZbcReferenced(pGpu, NV_FALSE); + memmgrSetZbcReferenced(pGpu, pFbAllocInfo->hClient, pFbAllocInfo->hDevice, NV_FALSE); } NV_PRINTF(LEVEL_INFO, @@ -566,83 +575,6 @@ memmgrFreeHal_GM107 return NV_OK; } -NV_STATUS -memmgrGetSurfacePhysAttr_GM107 -( - OBJGPU *pGpu, - MemoryManager *pMemoryManager, - Memory *pMemory, - NvU64 *pOffset, - NvU32 *pMemAperture, - NvU32 *pMemKind, - NvU32 *pComprOffset, - NvU32 *pComprKind, - NvU32 *pLineMin, - NvU32 *pLineMax, - NvU32 *pZCullId, - NvU32 *pGpuCacheAttr, - NvU32 *pGpuP2PCacheAttr, - NvU64 *contigSegmentSize -) -{ - NV_STATUS rmStatus; - PMEMORY_DESCRIPTOR pMemDesc = memdescGetMemDescFromGpu(pMemory->pMemDesc, pGpu); - COMPR_INFO comprInfo; - NvU32 unused; - - NV_ASSERT(pMemDesc); - - rmStatus = memmgrFillMemdescForPhysAttr(pGpu, pMemoryManager, pMemDesc, AT_GPU, pOffset, pMemAperture, - pMemKind, pZCullId, pGpuCacheAttr, pGpuP2PCacheAttr, - contigSegmentSize); - if (NV_OK != rmStatus) - { - return rmStatus; - } - - if ((!memmgrIsKind_HAL(pMemoryManager, FB_IS_KIND_COMPRESSIBLE, *pMemKind)) || - !FB_HWRESID_CTAGID_VAL_FERMI(memdescGetHwResId(pMemDesc))) - { - *pComprKind = 0; - return NV_OK; - } - // vGPU: pPrivate->pCompTags is not - // currently initialized in the guest RM - // vGPU does not use compression tags yet. - // GSPTODO: sort out ctags - if (IS_VIRTUAL(pGpu) || IS_GSP_CLIENT(pGpu)) - { - *pComprOffset = 0x0; - *pLineMin = 0x0; - *pLineMax = 0x0; - return NV_OK; - } - - rmStatus = memmgrGetKindComprFromMemDesc(pMemoryManager, pMemDesc, 0, &unused, &comprInfo); - if (rmStatus != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "dmaGetKidnCompr failed: %x\n", rmStatus); - return rmStatus; - } - - if (memmgrIsKind_HAL(pMemoryManager, FB_IS_KIND_COMPRESSIBLE, comprInfo.kind)) - { - *pLineMin = comprInfo.compTagLineMin; - *pLineMax = comprInfo.compPageIndexHi - comprInfo.compPageIndexLo + comprInfo.compTagLineMin; - *pComprOffset = comprInfo.compPageIndexLo; - *pComprKind = 1; - } - else - { - // No coverage at all (stripped by release/reacquire or invalid hw res). - *pLineMin = ~0; - *pLineMax = ~0; - *pComprKind = 0; - } - - return NV_OK; -} - NV_STATUS memmgrGetBAR1InfoForDevice_GM107 ( @@ -670,7 +602,11 @@ memmgrGetBAR1InfoForDevice_GM107 NV2080_CTRL_FB_GET_INFO_V2_PARAMS fbInfoParams = {0}; Subdevice *pSubdevice; - NV_ASSERT_OK_OR_RETURN(subdeviceGetByGpu(pClient, pGpu, &pSubdevice)); + NV_ASSERT_OK_OR_RETURN( + subdeviceGetByInstance(pClient, + RES_GET_HANDLE(pDevice), + gpumgrGetSubDeviceInstanceFromGpu(pGpu), + &pSubdevice)); fbInfoParams.fbInfoList[0].index = NV2080_CTRL_FB_INFO_INDEX_BAR1_SIZE; fbInfoParams.fbInfoList[1].index = NV2080_CTRL_FB_INFO_INDEX_BAR1_AVAIL_SIZE; @@ -698,7 +634,7 @@ memmgrGetBAR1InfoForDevice_GM107 NV_ASSERT_OR_RETURN(pBar1VAS != NULL, NV_ERR_INVALID_STATE); pVASHeap = vaspaceGetHeap(pBar1VAS); - NV_ASSERT_OK_OR_RETURN(kbusGetBar1VARangeForClient(pGpu, pKernelBus, pClient->hClient, &bar1VARange)); + NV_ASSERT_OK_OR_RETURN(kbusGetBar1VARangeForDevice(pGpu, pKernelBus, pDevice, &bar1VARange)); bar1Info->bar1Size = (NvU32)(rangeLength(bar1VARange) / 1024); bar1Info->bankSwizzleAlignment = vaspaceGetBigPageSize(pBar1VAS); @@ -1549,8 +1485,7 @@ memmgrGetBlackListPages_GM107 } portMemSet(pParams, 0, sizeof(*pParams)); - pRmApi = IS_GSP_CLIENT(pGpu) ? GPU_GET_PHYSICAL_RMAPI(pGpu) : - rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); status = pRmApi->Control(pRmApi, pGpu->hInternalClient, @@ -1653,3 +1588,15 @@ memmgrGetBlackListPagesForHeap_GM107 // Failure to read offlined pages from host is not fatal return NV_OK; } + +NvU32 +memmgrGetFBEndReserveSizeEstimate_GM107 +( + OBJGPU *pGpu, + MemoryManager *pMemoryManager +) +{ + const NvU32 ESTIMATED_RESERVE_FB = 0x200000; + + return ESTIMATED_RESERVE_FB; +} diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_utils_gm107.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_utils_gm107.c index 4e75d4b0ff..fcc2fb9ea5 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_utils_gm107.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_utils_gm107.c @@ -71,10 +71,6 @@ static NV_STATUS _memUtilsMapUserd_GM107(OBJGPU *pGpu, MemoryManager *pMemoryMan OBJCHANNEL *pChannel, NvHandle hClientId, NvHandle hDeviceId, NvHandle hChannelId, NvBool bUseRmApiForBar1); static NV_STATUS _memUtilsAllocateReductionSema(OBJGPU *pGpu, MemoryManager *pMemoryManager, OBJCHANNEL *pChannel); -static NvU32 _ceChannelScheduleBatchWork_GM107(OBJGPU *pGpu, MemoryManager *pMemoryManager, OBJCHANNEL *pChannel, - RmPhysAddr src, NV_ADDRESS_SPACE srcAddressSpace, NvU32 srcCpuCacheAttrib, - RmPhysAddr dst, NV_ADDRESS_SPACE dstAddressSpace, NvU32 dstCpuCacheAttrib, - NvU64 size, NvBool bMemcopy); static NvU32 _ceChannelScheduleWork_GM107(OBJGPU *pGpu, MemoryManager *pMemoryManager, OBJCHANNEL *pChannel, RmPhysAddr src, NV_ADDRESS_SPACE srcAddressSpace, NvU32 srcCpuCacheAttrib, RmPhysAddr dst, NV_ADDRESS_SPACE dstAddressSpace, NvU32 dstCpuCacheAttrib, @@ -219,6 +215,7 @@ _memUtilsChannelAllocatePB_GM107 NvHandle hVirtMem; NvU32 hClass; NvU32 attr; + NvU32 flags = 0; NvU32 attrNotifier = NVOS32_ATTR_NONE; RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); @@ -229,6 +226,8 @@ _memUtilsChannelAllocatePB_GM107 hClass = NV01_MEMORY_LOCAL_USER; attr = DRF_DEF(OS32, _ATTR, _LOCATION, _VIDMEM) | DRF_DEF(OS32, _ATTR, _COHERENCY, _UNCACHED); + + flags = NVOS32_ALLOC_FLAGS_PERSISTENT_VIDMEM; attrNotifier = attr; break; @@ -277,7 +276,7 @@ _memUtilsChannelAllocatePB_GM107 memAllocParams.size = size; memAllocParams.attr = attr; memAllocParams.attr2 = NVOS32_ATTR2_NONE; - memAllocParams.flags = 0; + memAllocParams.flags = flags; memAllocParams.internalflags = NVOS32_ALLOC_INTERNAL_FLAGS_SKIP_SCRUB; // @@ -1507,168 +1506,6 @@ memmgrMemUtilsMemSetBlocking_GM107 return NV_OK; } -/*! - * Do a Blocking Memset - * - * @param[in] pCHannel OBJCHANNEL pointer - * @param[in] base Offset in FB - * @param[in] size size to scrub - * @returns NV_STATUS - */ - -NV_STATUS -memmgrMemUtilsMemSetBatched_GM107 -( - OBJGPU *pGpu, - MemoryManager *pMemoryManager, - OBJCHANNEL *pChannel, - RmPhysAddr base, - NvU64 size -) -{ - NvU32 blocksPushed = 0; - - NV_ASSERT_OR_RETURN(pChannel->pbCpuVA != NULL, NV_ERR_GENERIC); - NV_ASSERT_OR_RETURN(pChannel->pControlGPFifo != NULL, NV_ERR_GENERIC); - - blocksPushed = _ceChannelScheduleBatchWork_GM107(pGpu, pMemoryManager, pChannel, - 0, 0, 0, // src parameters - base, ADDR_FBMEM, 0, // dst parameters - size, - NV_FALSE); // memcopy - - if (blocksPushed > 0) - { - NvU8 *semAddr = pChannel->pbCpuVA + pChannel->finishPayloadOffset; - NV_STATUS timeoutStatus = NV_OK; - RMTIMEOUT timeout; - - gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); - - while(MEM_RD32(semAddr) != pChannel->finishPayload) - { - NV_PRINTF(LEVEL_INFO, "Semaphore Payload is 0x%x last is 0x%x\n", - MEM_RD32(semAddr), pChannel->finishPayload); - - if (timeoutStatus == NV_ERR_TIMEOUT) - { - NV_PRINTF(LEVEL_ERROR, - "Timed Out waiting for CE semaphore!\n"); - - NV_PRINTF(LEVEL_ERROR, - "GET=0x%x, PUT=0x%x, GPGET=0x%x, GPPUT=0x%x\n", - MEM_RD32(&pChannel->pControlGPFifo->Get), - MEM_RD32(&pChannel->pControlGPFifo->Put), - MEM_RD32(&pChannel->pControlGPFifo->GPGet), - MEM_RD32(&pChannel->pControlGPFifo->GPPut)); - - DBG_BREAKPOINT_REASON(NV_ERR_TIMEOUT); - return NV_ERR_GENERIC; - } - - // - // mcServiceList() can be enabled for debugging purposes - // mcServiceListPgSafe(pGpu, GPU_GET_MC(pGpu), MC_ENGINES_ALL, NV_FALSE); - // - - osSpinLoop(); - timeoutStatus = gpuCheckTimeout(pGpu, &timeout); - } - } - - return NV_OK; -} - -/*! - * Do a Blocking Memcopy - * - * @param[in] pChannel OBJCHANNEL pointer - * @param[in] src Offset of src to copy from - * @param[in] srcAddressSpace source surface address space type - * @param[in] srcCpuCacheAttrib source surface address space attributes - * @param[in] dst Offset of dst to scrub/copy to - * @param[in] dstAddressSpace destination surface address space type - * @param[in] dstCpuCacheAttrib destination surface address space attributes - * @param[in] size size to scrub - * @returns NV_STATUS - */ -NV_STATUS -memmgrMemUtilsMemCopyBatched_GM107 -( - OBJGPU *pGpu, - MemoryManager *pMemoryManager, - OBJCHANNEL *pChannel, - RmPhysAddr src, - NV_ADDRESS_SPACE srcAddressSpace, - NvU32 srcCpuCacheAttrib, - RmPhysAddr dst, - NV_ADDRESS_SPACE dstAddressSpace, - NvU32 dstCpuCacheAttrib, - NvU64 size -) -{ - NV_ASSERT_OR_RETURN(pChannel->pbCpuVA != NULL, NV_ERR_GENERIC); - NV_ASSERT_OR_RETURN(pChannel->pControlGPFifo != NULL, NV_ERR_GENERIC); - - NvU32 blocksPushed = _ceChannelScheduleBatchWork_GM107(pGpu, pMemoryManager, pChannel, - src, srcAddressSpace, srcCpuCacheAttrib, // src parameters - dst, dstAddressSpace, dstCpuCacheAttrib, // dst parameters - size, - NV_TRUE); // memcopy; - - if (blocksPushed > 0) - { - NvU8 *semAddr = pChannel->pbCpuVA + pChannel->finishPayloadOffset; - NV_STATUS timeoutStatus = NV_OK; - RMTIMEOUT timeout; - - // - // Originally the flag is 0, but to WAR bug 2441762, add flag - // GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE to bypass using threadStateCheckTimeout - // - gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE); - - while (MEM_RD32(semAddr) != pChannel->finishPayload) - { - NV_PRINTF(LEVEL_INFO, "Semaphore Payload is 0x%x last is 0x%x\n", - MEM_RD32(semAddr), pChannel->finishPayload); - - NV_PRINTF(LEVEL_INFO, - "GET=0x%x, PUT=0x%x, GPGET=0x%x, GPPUT=0x%x\n", - MEM_RD32(&pChannel->pControlGPFifo->Get), - MEM_RD32(&pChannel->pControlGPFifo->Put), - MEM_RD32(&pChannel->pControlGPFifo->GPGet), - MEM_RD32(&pChannel->pControlGPFifo->GPPut)); - - if (timeoutStatus == NV_ERR_TIMEOUT) - { - NV_PRINTF(LEVEL_ERROR, - "Timed Out waiting for CE semaphore\n"); - - NV_PRINTF(LEVEL_ERROR, - "GET=0x%x, PUT=0x%x, GPGET=0x%x, GPPUT=0x%x\n", - MEM_RD32(&pChannel->pControlGPFifo->Get), - MEM_RD32(&pChannel->pControlGPFifo->Put), - MEM_RD32(&pChannel->pControlGPFifo->GPGet), - MEM_RD32(&pChannel->pControlGPFifo->GPPut)); - - DBG_BREAKPOINT_REASON(NV_ERR_TIMEOUT); - return NV_ERR_GENERIC; - } - - // - // mcServiceList() can be enabled for debugging purposes - // mcServiceListPgSafe(pGpu, GPU_GET_MC(pGpu), MC_ENGINES_ALL, NV_FALSE); - // - - osSpinLoop(); - timeoutStatus = gpuCheckTimeout(pGpu, &timeout); - } - } - - return NV_OK; -} - /*! * This function allocates the ECC scrubber * @@ -1806,91 +1643,6 @@ _getSpaceInPb(OBJCHANNEL *pChannel) } -/*! - * This function allows batch mode of submitting work. - * The work is submitted to Host only when the pushbuffer runs out of space. - * - * @param[in] pChannel OBJCHANNEL pointer - * @param[in] src Offset of src to copy from - * @param[in] srcAddressSpace source surface address space type - * @param[in] srcCpuCacheAttrib source surface address space attributes - * @param[in] dst Offset of dst to scrub/copy to - * @param[in] dstAddressSpace destination surface address space type - * @param[in] dstCpuCacheAttrib destination surface address space attributes - * @param[in] size size to scrub/copy - * @param[in] bMemcopy NV_TRUE for memory copy / NV_FALSE for scrubbing - * @returns Bool - */ -static NvU32 -_ceChannelScheduleBatchWork_GM107 -( - OBJGPU *pGpu, - MemoryManager *pMemoryManager, - OBJCHANNEL *pChannel, - RmPhysAddr src, - NV_ADDRESS_SPACE srcAddressSpace, - NvU32 srcCpuCacheAttrib, - RmPhysAddr dst, - NV_ADDRESS_SPACE dstAddressSpace, - NvU32 dstCpuCacheAttrib, - NvU64 size, - NvBool bMemcopy -) -{ - NvU32 spaceInPb; - NvU32 bytesPushed; - NvU32 *ptr; - NvU32 blocksPushed = 0; - - spaceInPb = pChannel->channelPbSize - pChannel->channelPutOffset; - NV_ASSERT_OR_RETURN(spaceInPb >= pChannel->methodSizePerBlock, 0); - NV_ASSERT_OR_RETURN(pChannel->pbCpuVA != NULL, 0); - NV_ASSERT_OR_RETURN(pChannel->pControlGPFifo != NULL, 0); - - // Support for sending semaphore release only work. - if (size > 0) - { - NV_PRINTF(LEVEL_INFO, "Space in PB is %d and starting fill at 0x%x\n", - spaceInPb, pChannel->channelPutOffset); - - ptr = (NvU32 *)(pChannel->pbCpuVA + pChannel->channelPutOffset); - - bytesPushed = _ceChannelPushMethodsBlock_GM107(pGpu, pMemoryManager, pChannel, - src, srcAddressSpace, srcCpuCacheAttrib, // src parameters - dst, dstAddressSpace, dstCpuCacheAttrib, // dst parameters - size, &ptr, NV_FALSE, NV_FALSE, NV_FALSE, bMemcopy); - pChannel->finishPayload += NvU64_LO32(size); - NV_ASSERT(NvU64_HI32(size) == 0); - NV_ASSERT(bytesPushed != 0); - } - - spaceInPb = pChannel->channelPbSize - pChannel->channelPutOffset; - - // - // Submit a semaphore release only work followed by a GPFIFO update. - // We do this in the following cases: - // 1. We run out of pushbuffer space - // 2. Flush remaining/last work - // - if (spaceInPb < pChannel->methodSizePerBlock || (pChannel->channelPutOffset && !size)) - { - ptr = (NvU32 *)(pChannel->pbCpuVA + pChannel->channelPutOffset); - - bytesPushed = _ceChannelPushMethodsBlock_GM107(pGpu, pMemoryManager, pChannel, - 0, 0, 0, // src parameters - 0, 0, 0, // dst parameters - 0, &ptr, NV_FALSE, NV_FALSE, NV_TRUE, bMemcopy); - - NV_ASSERT(bytesPushed != 0); - - _ceChannelUpdateGpFifo_GM107(pGpu, pMemoryManager, pChannel, 0, pChannel->channelPutOffset); - blocksPushed = 1; - pChannel->channelPutOffset = 0; - } - - return blocksPushed; -} - /*! * This function manages the PushBUffer * It will insert methods into the PB, manage wrap around diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/virt_mem_allocator_gm107.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/virt_mem_allocator_gm107.c index ddad855904..fc2857c58a 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/virt_mem_allocator_gm107.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/virt_mem_allocator_gm107.c @@ -428,10 +428,13 @@ dmaAllocMapping_GM107 // RM allocating one comptagline per 64KB allocation (From Pascal to Turing). // See bug 3909010 // + // Skipping it for Raw mode, See bug 4036809 + // if ((pLocals->pageSize == RM_PAGE_SIZE) && - memmgrIsKind_HAL(pMemoryManager, FB_IS_KIND_COMPRESSIBLE, pLocals->kind)) + memmgrIsKind_HAL(pMemoryManager, FB_IS_KIND_COMPRESSIBLE, pLocals->kind) && + !(pMemorySystemConfig->bUseRawModeComptaglineAllocation)) { - NV_PRINTF(LEVEL_WARNING, "Requested 4K mapping on compressible sufrace. Overriding to physical page granularity..."); + NV_PRINTF(LEVEL_WARNING, "Requested 4K mapping on compressible sufrace. Overriding to physical page granularity...\n"); pLocals->pageSize = pLocals->physPageSize; } @@ -971,10 +974,8 @@ dmaAllocMapping_GM107 SLI_LOOP_BREAK; } } - else if ((memdescGetAddressSpace(pLocals->pTempMemDesc) == ADDR_EGM)) + else if (memdescIsEgm(pLocals->pTempMemDesc)) { - NV_ASSERT(memdescGetFlag(pLocals->pTempMemDesc, MEMDESC_FLAGS_ALLOC_FROM_EGM)); - pLocals->aperture = NV_MMU_PTE_APERTURE_PEER_MEMORY; if (pLocals->p2p) @@ -1721,6 +1722,17 @@ dmaUpdateVASpace_GF100 NvBool bIsIndirectPeer; VAS_PTE_UPDATE_TYPE update_type; + { + OBJGVASPACE *pGVAS = dynamicCast(pVAS, OBJGVASPACE); + if (bFillPteMem && + (pGVAS->flags & VASPACE_FLAGS_BAR_BAR1) && + (flags & DMA_UPDATE_VASPACE_FLAGS_UPDATE_VALID) && + (SF_VAL(_MMU, _PTE_VALID, valid) == NV_MMU_PTE_VALID_FALSE)) + { + bSparse = NV_TRUE; + } + } + priv = (flags & DMA_UPDATE_VASPACE_FLAGS_PRIV) ? NV_MMU_PTE_PRIVILEGE_TRUE : NV_MMU_PTE_PRIVILEGE_FALSE; tlbLock = (flags & DMA_UPDATE_VASPACE_FLAGS_TLB_LOCK) ? NV_MMU_PTE_LOCK_TRUE : NV_MMU_PTE_LOCK_FALSE; readOnly = (flags & DMA_UPDATE_VASPACE_FLAGS_READ_ONLY) ? NV_MMU_PTE_READ_ONLY_TRUE : NV_MMU_PTE_READ_ONLY_FALSE; @@ -1736,18 +1748,6 @@ dmaUpdateVASpace_GF100 NV_ASSERT_OR_RETURN(pageSize == vaSpaceBigPageSize, NV_ERR_INVALID_STATE); } - if (pGpu->bEnableBar1SparseForFillPteMemUnmap) - { - OBJGVASPACE *pGVAS = dynamicCast(pVAS, OBJGVASPACE); - if (bFillPteMem && - (pGVAS->flags & VASPACE_FLAGS_BAR_BAR1) && - (flags & DMA_UPDATE_VASPACE_FLAGS_UPDATE_VALID) && - (SF_VAL(_MMU, _PTE_VALID, valid) == NV_MMU_PTE_VALID_FALSE)) - { - bSparse = NV_TRUE; - } - } - // // Determine whether we are invalidating or revoking privileges, so we know // whether to flush page accesses or not. ReadDisable and writeDisable have @@ -2118,8 +2118,7 @@ dmaUpdateVASpace_GF100 if ((NULL == pTgtPteMem) && DMA_TLB_INVALIDATE == deferInvalidate) { kbusFlush_HAL(pGpu, pKernelBus, BUS_FLUSH_VIDEO_MEMORY | - BUS_FLUSH_SYSTEM_MEMORY | - BUS_FLUSH_USE_PCIE_READ); + BUS_FLUSH_SYSTEM_MEMORY); gvaspaceInvalidateTlb(pGVAS, pGpu, update_type); } @@ -2560,8 +2559,7 @@ _dmaApplyWarForBug2720120 // Flush PTE writes to vidmem and issue TLB invalidate kbusFlush_HAL(pGpu, pKernelBus, BUS_FLUSH_VIDEO_MEMORY | - BUS_FLUSH_SYSTEM_MEMORY | - BUS_FLUSH_USE_PCIE_READ); + BUS_FLUSH_SYSTEM_MEMORY); gvaspaceInvalidateTlb(pGVAS, pGpu, PTE_UPGRADE); return NV_OK; diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/pascal/mem_mgr_scrub_gp100.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/pascal/mem_mgr_scrub_gp100.c index 5574811470..b9eb994adf 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/arch/pascal/mem_mgr_scrub_gp100.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/pascal/mem_mgr_scrub_gp100.c @@ -31,53 +31,21 @@ #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" #include "kernel/gpu/fifo/kernel_fifo.h" -static NV_STATUS _memmgrPostSchedulingEnableHandler_GP100(OBJGPU *, void *); -static NV_STATUS _memmgrPreSchedulingDisableHandler_GP100(OBJGPU *, void *); - /*! - * Scrub initialization routine - * - * @returns NV_OK on success, NV_ERR_GENERIC on failure + * Performs initialization that is dependant on work done in gpuStateLoad() such + * as channel initialization. */ NV_STATUS -memmgrScrubInit_GP100 +memmgrScrubHandlePostSchedulingEnable_GP100 ( OBJGPU *pGpu, MemoryManager *pMemoryManager ) -{ - if (memmgrIsScrubOnFreeEnabled(pMemoryManager)) - { - NV_ASSERT_OK_OR_RETURN(kfifoAddSchedulingHandler(pGpu, - GPU_GET_KERNEL_FIFO(pGpu), - _memmgrPostSchedulingEnableHandler_GP100, NULL, - _memmgrPreSchedulingDisableHandler_GP100, NULL)); - } - - return NV_OK; -} - -/*! - * Performs initialization that is dependant on work done in gpuStateLoad() such - * as channel initialization. - * - * @param[in] pGpu OBJGPU pointer - * @param[in] pUnusedData Callback data which is unused - * - * @returns NV_OK on success, NV_ERR_GENERIC on failure - */ -static NV_STATUS -_memmgrPostSchedulingEnableHandler_GP100 -( - OBJGPU *pGpu, - void *pUnusedData -) { Heap *pHeap = GPU_GET_HEAP(pGpu); NvBool bIsMIGEnabled = IS_MIG_ENABLED(pGpu); KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); NvBool bIsVgpuLegacyPolicy = (pKernelMIGManager != NULL) && kmigmgrUseLegacyVgpuPolicy(pGpu, pKernelMIGManager); - MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); // // Disabling scrub on free for SLI, waiting on the bug:1915380 @@ -94,36 +62,20 @@ _memmgrPostSchedulingEnableHandler_GP100 return NV_OK; } -NV_STATUS -memmgrScrubHandlePostSchedulingEnable_GP100 -( - OBJGPU *pGpu, - MemoryManager *pMemoryManager -) -{ - return _memmgrPostSchedulingEnableHandler_GP100(pGpu, NULL); -} - /*! * Performs cleanup on resources that need to be freed before StateUnload routes * are called - * - * @param[in] pGpu OBJGPU pointer - * @param[in] pUnusedData Unused callback data - * - * @returns NV_OK */ -static NV_STATUS -_memmgrPreSchedulingDisableHandler_GP100 +NV_STATUS +memmgrScrubHandlePreSchedulingDisable_GP100 ( - OBJGPU *pGpu, - void *pUnusedData + OBJGPU *pGpu, + MemoryManager *pMemoryManager ) { Heap *pHeap = GPU_GET_HEAP(pGpu); OBJMEMSCRUB *pMemscrub = NULL; NvBool bIsMIGEnabled = IS_MIG_ENABLED(pGpu); - MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); NvBool bIsMIGInUse = IS_MIG_IN_USE(pGpu); KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); NvBool bIsVgpuLegacyPolicy = (pKernelMIGManager != NULL) && kmigmgrUseLegacyVgpuPolicy(pGpu, pKernelMIGManager); @@ -152,33 +104,3 @@ _memmgrPreSchedulingDisableHandler_GP100 return NV_OK; } - -NV_STATUS -memmgrScrubHandlePreSchedulingDisable_GP100 -( - OBJGPU *pGpu, - MemoryManager *pMemoryManager -) -{ - return _memmgrPreSchedulingDisableHandler_GP100(pGpu, NULL); -} - -/*! - * FB scrub cleanup routine. Deallocates any dynamic memory used. - * - * @returns NV_OK on success, NV_ERR_GENERIC on failure - */ -void -memmgrScrubDestroy_GP100 -( - OBJGPU *pGpu, - MemoryManager *pMemoryManager -) -{ - if (memmgrIsScrubOnFreeEnabled(pMemoryManager)) - { - kfifoRemoveSchedulingHandler(pGpu, GPU_GET_KERNEL_FIFO(pGpu), - _memmgrPostSchedulingEnableHandler_GP100, NULL, - _memmgrPreSchedulingDisableHandler_GP100, NULL); - } -} diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/ce_utils.c b/src/nvidia/src/kernel/gpu/mem_mgr/ce_utils.c index 6b5001ea47..42670f4bfc 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/ce_utils.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/ce_utils.c @@ -63,6 +63,13 @@ ceutilsConstruct_IMPL NvBool bMIGInUse = IS_MIG_IN_USE(pGpu); MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + pCeUtils->pGpu = pGpu; + + if (FLD_TEST_DRF(0050_CEUTILS, _FLAGS, _FIFO_LITE, _TRUE, allocFlags)) + { + return NV_ERR_NOT_SUPPORTED; + } + // Allocate channel with RM internal client RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); RmClient *pClient; @@ -121,6 +128,17 @@ ceutilsConstruct_IMPL pChannel->type = CE_SCRUBBER_CHANNEL; } + // For self-hosted Hopper, we can only use VA copy or faster scrubber + if (gpuIsSelfHosted(pGpu)) + { + if (!pChannel->bUseVasForCeCopy && + (pChannel->type != FAST_SCRUBBER_CHANNEL)) + { + status = NV_ERR_NOT_SUPPORTED; + goto free_channel; + } + } + // Set up various channel resources status = channelSetupIDs(pChannel, pGpu, pChannel->bUseVasForCeCopy, bMIGInUse); NV_ASSERT_OR_GOTO(status == NV_OK, free_client); @@ -137,8 +155,6 @@ ceutilsConstruct_IMPL status = memmgrMemUtilsCopyEngineInitialize_HAL(pGpu, pMemoryManager, pChannel); NV_ASSERT_OR_GOTO(status == NV_OK, free_channel); - pCeUtils->pGpu = pGpu; - return status; free_channel: @@ -243,11 +259,7 @@ ceutilsServiceInterrupts_IMPL(CeUtils *pCeUtils) // if the lock is held, service any interrupts on the owned CE to make progress. // Bug 2527660 is filed to remove this change. // - // pChannel is null when PMA scrub requests are handled in vGPU plugin. - // In this case vGpu plugin allocates scrubber channel in PF domain so - // above mention deadlock is not present here. - // - if ((pChannel != NULL) && (rmDeviceGpuLockIsOwner(pChannel->pGpu->gpuInstance))) + if (rmDeviceGpuLockIsOwner(pChannel->pGpu->gpuInstance)) { channelServiceScrubberInterrupts(pChannel); } @@ -344,6 +356,12 @@ _ceutilsSubmitPushBuffer } else { + if (gpuIsSelfHosted(pChannel->pGpu)) + { + // Self-hosted Hopper only supports VA copy or fast scrubber + NV_ASSERT_OR_RETURN(pChannel->bUseVasForCeCopy, NV_ERR_NOT_SUPPORTED); + } + methodsLength = channelFillCePb(pChannel, putIndex, bPipelined, bInsertFinishPayload, pChannelPbInfo); } @@ -401,8 +419,7 @@ ceutilsMemset_IMPL return NV_ERR_INVALID_ARGUMENT; } - if ((memdescGetAddressSpace(pMemDesc) != ADDR_FBMEM) || - (pMemDesc->pGpu != pCeUtils->pChannel->pGpu)) + if (pMemDesc->pGpu != pCeUtils->pChannel->pGpu) { NV_PRINTF(LEVEL_ERROR, "Invalid memory descriptor passed.\n"); return NV_ERR_INVALID_ARGUMENT; @@ -512,13 +529,6 @@ ceutilsMemcopy_IMPL return NV_ERR_INVALID_ARGUMENT; } - if ((memdescGetAddressSpace(pSrcMemDesc) != ADDR_FBMEM) && - (memdescGetAddressSpace(pDstMemDesc) != ADDR_FBMEM)) - { - NV_PRINTF(LEVEL_ERROR, "Either Dst or Src memory should be in vidmem.\n"); - return NV_ERR_INVALID_ARGUMENT; - } - if ((pSrcMemDesc->pGpu != pCeUtils->pChannel->pGpu) || (pDstMemDesc->pGpu != pCeUtils->pChannel->pGpu)) { diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/channel_utils.c b/src/nvidia/src/kernel/gpu/mem_mgr/channel_utils.c index c346fb23c6..73c0bb68c8 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/channel_utils.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/channel_utils.c @@ -23,6 +23,7 @@ #include "kernel/gpu/intr/intr.h" #include "kernel/gpu/fifo/kernel_fifo.h" +#include "kernel/gpu/fifo/kernel_channel.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" #include "utils/nvassert.h" #include "core/locks.h" @@ -32,12 +33,10 @@ #include "kernel/gpu/mem_mgr/channel_utils.h" #include "class/clcba2.h" - #define SEC2_WL_METHOD_ARRAY_SIZE 16 #define SHA_256_HASH_SIZE_BYTE 32 /* Static helper functions */ -static void channelPushAddress(OBJCHANNEL *pChannel, CHANNEL_PB_INFO *pChannelPbInfo, NvU32 **ppPtr); static NvU32 channelPushMemoryProperties(OBJCHANNEL *pChannel, CHANNEL_PB_INFO *pChannelPbInfo, NvU32 **ppPtr); static void channelPushMethod(OBJCHANNEL *pChannel, CHANNEL_PB_INFO *pChannelPbInfo, NvBool bPipelined, NvBool bInsertFinishPayload, @@ -247,7 +246,10 @@ channelWaitForFinishPayload if (rmDeviceGpuLockIsOwner(pGpu->gpuInstance)) { - channelServiceScrubberInterrupts(pChannel); + if (!kfifoIsLiteModeEnabled_HAL(pGpu, GPU_GET_KERNEL_FIFO(pGpu))) + { + channelServiceScrubberInterrupts(pChannel); + } } else { @@ -301,7 +303,10 @@ channelWaitForFreeEntry if (rmDeviceGpuLockIsOwner(pGpu->gpuInstance)) { - channelServiceScrubberInterrupts(pChannel); + if (!kfifoIsLiteModeEnabled_HAL(pGpu, GPU_GET_KERNEL_FIFO(pGpu))) + { + channelServiceScrubberInterrupts(pChannel); + } } else { @@ -387,7 +392,6 @@ channelFillGpFifo pChannel->pbCpuVA = NULL; } - // need to flush WRC buffer osFlushCpuWriteCombineBuffer(); // write GP put @@ -420,11 +424,6 @@ channelFillGpFifo return NV_ERR_GENERIC; } - // - // removing the FIFO Lite Mode handling - // Refer older _ceChannelUpdateGpFifo_GF100 code for implementation - // - // Update doorbell with work submission token if (pChannel->bUseDoorbellRegister) { @@ -507,21 +506,18 @@ channelFillPbFastScrub else flushValue = DRF_DEF(B0B5, _LAUNCH_DMA, _FLUSH_ENABLE, _FALSE); - NV_PUSH_INC_2U(RM_SUBCHANNEL, NVC8B5_OFFSET_OUT_UPPER, - DRF_NUM(C8B5, _OFFSET_OUT_UPPER, _UPPER, NvU64_HI32(pChannelPbInfo->dstAddr)), - NVC8B5_OFFSET_OUT_LOWER, - DRF_NUM(C8B5, _OFFSET_OUT_LOWER, _VALUE,NvU64_LO32(pChannelPbInfo->dstAddr))); + NV_PUSH_INC_2U(RM_SUBCHANNEL, + NVC8B5_OFFSET_OUT_UPPER, NvU64_HI32(pChannelPbInfo->dstAddr), + NVC8B5_OFFSET_OUT_LOWER, NvU64_LO32(pChannelPbInfo->dstAddr)); NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC8B5_LINE_LENGTH_IN, pChannelPbInfo->size); if (semaValue) { - NV_PUSH_INC_3U(RM_SUBCHANNEL, NVC8B5_SET_SEMAPHORE_A, - DRF_NUM(C8B5, _SET_SEMAPHORE_A, _UPPER, NvU64_HI32(pChannel->pbGpuVA + pChannel->finishPayloadOffset)), - NVC8B5_SET_SEMAPHORE_B, - DRF_NUM(C8B5, _SET_SEMAPHORE_B, _LOWER, NvU64_LO32(pChannel->pbGpuVA + pChannel->finishPayloadOffset)), - NVC8B5_SET_SEMAPHORE_PAYLOAD, - pChannelPbInfo->payload); + NV_PUSH_INC_3U(RM_SUBCHANNEL, + NVC8B5_SET_SEMAPHORE_A, NvU64_HI32(pChannel->pbGpuVA + pChannel->finishPayloadOffset), + NVC8B5_SET_SEMAPHORE_B, NvU64_LO32(pChannel->pbGpuVA + pChannel->finishPayloadOffset), + NVC8B5_SET_SEMAPHORE_PAYLOAD, pChannelPbInfo->payload); } NV_PUSH_INC_1U(RM_SUBCHANNEL, NVC8B5_SET_MEMORY_SCRUB_PARAMETERS, @@ -551,10 +547,9 @@ channelFillPbFastScrub pSemaAddr = (pChannel->pbGpuVA+pChannel->semaOffset); - NV_PUSH_INC_4U(RM_SUBCHANNEL, NVC86F_SEM_ADDR_LO, - DRF_NUM(C86F, _SEM_ADDR_LO, _OFFSET, NvU64_LO32(pSemaAddr) >> 2), - NVC86F_SEM_ADDR_HI, - DRF_NUM(C86F, _SEM_ADDR_HI, _OFFSET, NvU64_HI32(pSemaAddr)), + NV_PUSH_INC_4U(RM_SUBCHANNEL, + NVC86F_SEM_ADDR_LO, NvU64_LO32(pSemaAddr), + NVC86F_SEM_ADDR_HI, NvU64_HI32(pSemaAddr), NVC86F_SEM_PAYLOAD_LO, putIndex, NVC86F_SEM_PAYLOAD_HI, 0); @@ -589,14 +584,11 @@ channelAddHostSema // denotes that HOST has read all the methods needed for this memory operation // and safely assume that this GPFIFO and PB entry can be reused. // - NV_PUSH_INC_4U(RM_SUBCHANNEL, NV906F_SEMAPHOREA, - DRF_NUM(906F, _SEMAPHOREA_OFFSET, _UPPER, NvU64_HI32(pSemaAddr)), - NV906F_SEMAPHOREB, - DRF_NUM(906F, _SEMAPHOREB_OFFSET, _LOWER, NvU64_LO32(pSemaAddr) >> 2), - NV906F_SEMAPHOREC, - putIndex, - NV906F_SEMAPHORED, - data); + NV_PUSH_INC_4U(RM_SUBCHANNEL, + NV906F_SEMAPHOREA, NvU64_HI32(pSemaAddr), + NV906F_SEMAPHOREB, NvU64_LO32(pSemaAddr), + NV906F_SEMAPHOREC, putIndex, + NV906F_SEMAPHORED, data); *ppPtr = pPtr; } @@ -624,11 +616,9 @@ channelFillCePb NV_PUSH_INC_1U(RM_SUBCHANNEL, NV906F_SET_OBJECT, pChannel->classEngineID); - // Side effect - pushed target aperture and REMAP method for memset + // Side effect - pushed target addresses, aperture and REMAP method for memset launchType = channelPushMemoryProperties(pChannel, pChannelPbInfo, &pPtr); - // Side effect - pushed addresses - channelPushAddress(pChannel, pChannelPbInfo, &pPtr); NV_PUSH_INC_1U(RM_SUBCHANNEL, NVB0B5_LINE_LENGTH_IN, pChannelPbInfo->size); if (bInsertFinishPayload) @@ -638,12 +628,10 @@ channelFillCePb // Do not support client semaphore for now NV_ASSERT(pChannelPbInfo->clientSemaAddr == 0); - NV_PUSH_INC_3U(RM_SUBCHANNEL, NVB0B5_SET_SEMAPHORE_A, - DRF_NUM(B0B5, _SET_SEMAPHORE_A, _UPPER, NvU64_HI32(pChannel->pbGpuVA + pChannel->finishPayloadOffset)), - NVB0B5_SET_SEMAPHORE_B, - DRF_NUM(B0B5, _SET_SEMAPHORE_B, _LOWER, NvU64_LO32(pChannel->pbGpuVA + pChannel->finishPayloadOffset)), - NVB0B5_SET_SEMAPHORE_PAYLOAD, - pChannelPbInfo->payload); + NV_PUSH_INC_3U(RM_SUBCHANNEL, + NVB0B5_SET_SEMAPHORE_A, NvU64_HI32(pChannel->pbGpuVA + pChannel->finishPayloadOffset), + NVB0B5_SET_SEMAPHORE_B, NvU64_LO32(pChannel->pbGpuVA + pChannel->finishPayloadOffset), + NVB0B5_SET_SEMAPHORE_PAYLOAD, pChannelPbInfo->payload); } // Side effect - pushed LAUNCH_DMA methods @@ -831,6 +819,8 @@ channelPushMemoryProperties NV_ADDRESS_SPACE srcAddressSpace = pChannelPbInfo->srcAddressSpace; NvU32 dstCpuCacheAttrib = pChannelPbInfo->dstCpuCacheAttrib; NvU32 srcCpuCacheAttrib = pChannelPbInfo->srcCpuCacheAttrib; + NvU64 dstAddr = pChannelPbInfo->dstAddr; + NvU64 srcAddr = pChannelPbInfo->srcAddr; NvU32 data = 0; NvU32 retVal = 0; @@ -862,6 +852,20 @@ channelPushMemoryProperties } NV_PUSH_INC_1U(RM_SUBCHANNEL, NVB0B5_SET_SRC_PHYS_MODE, data); + + if (pChannel->bUseVasForCeCopy && srcAddressSpace == ADDR_FBMEM) + { + srcAddr = srcAddr + pChannel->fbAliasVA - pChannel->startFbOffset; + retVal |= DRF_DEF(B0B5, _LAUNCH_DMA, _SRC_TYPE, _VIRTUAL); + } + else + { + retVal |= DRF_DEF(B0B5, _LAUNCH_DMA, _SRC_TYPE, _PHYSICAL); + } + + NV_PUSH_INC_2U(RM_SUBCHANNEL, + NVB0B5_OFFSET_IN_UPPER, NvU64_HI32(srcAddr), + NVB0B5_OFFSET_IN_LOWER, NvU64_LO32(srcAddr)); } // Push dst addr properties @@ -879,61 +883,25 @@ channelPushMemoryProperties } NV_PUSH_INC_1U(RM_SUBCHANNEL, NVB0B5_SET_DST_PHYS_MODE, data); - - if (pChannel->bUseVasForCeCopy) - { - retVal = DRF_DEF(B0B5, _LAUNCH_DMA, _DST_TYPE, _VIRTUAL) | - DRF_DEF(B0B5, _LAUNCH_DMA, _SRC_TYPE, _VIRTUAL); - } - else - { - retVal = DRF_DEF(B0B5, _LAUNCH_DMA, _DST_TYPE, _PHYSICAL) | - DRF_DEF(B0B5, _LAUNCH_DMA, _SRC_TYPE, _PHYSICAL); - } - *ppPtr = pPtr; - return retVal; -} - - -static void -channelPushAddress -( - OBJCHANNEL *pChannel, - CHANNEL_PB_INFO *pChannelPbInfo, - NvU32 **ppPtr -) -{ - NvU64 dstAddr = pChannelPbInfo->dstAddr; - NvU64 srcAddr = pChannelPbInfo->srcAddr; - NvU32 *pPtr = *ppPtr; - - // Linear translation to map the PA to VA - if (pChannel->bUseVasForCeCopy) + if (pChannel->bUseVasForCeCopy && dstAddressSpace == ADDR_FBMEM) { dstAddr = dstAddr + pChannel->fbAliasVA - pChannel->startFbOffset; - srcAddr = srcAddr + pChannel->fbAliasVA - pChannel->startFbOffset; + retVal |= DRF_DEF(B0B5, _LAUNCH_DMA, _DST_TYPE, _VIRTUAL); } - - // Set dst addr - NV_PUSH_INC_2U(RM_SUBCHANNEL, NVB0B5_OFFSET_OUT_UPPER, - DRF_NUM(B0B5, _OFFSET_OUT_UPPER, _UPPER, NvU64_HI32(dstAddr)), - NVB0B5_OFFSET_OUT_LOWER, - DRF_NUM(B0B5, _OFFSET_OUT_LOWER, _VALUE, NvU64_LO32(dstAddr))); - - // Set src addr if memcopy - if (pChannelPbInfo->bCeMemcopy) + else { - NV_PUSH_INC_2U(RM_SUBCHANNEL, NVB0B5_OFFSET_IN_UPPER, - DRF_NUM(B0B5, _OFFSET_IN_UPPER, _UPPER, NvU64_HI32(srcAddr)), - NVB0B5_OFFSET_IN_LOWER, - DRF_NUM(B0B5, _OFFSET_IN_LOWER, _VALUE, NvU64_LO32(srcAddr))); + retVal |= DRF_DEF(B0B5, _LAUNCH_DMA, _DST_TYPE, _PHYSICAL); } + NV_PUSH_INC_2U(RM_SUBCHANNEL, + NVB0B5_OFFSET_OUT_UPPER, NvU64_HI32(dstAddr), + NVB0B5_OFFSET_OUT_LOWER, NvU64_LO32(dstAddr)); + *ppPtr = pPtr; + return retVal; } - static void channelPushMethod ( diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/context_dma.c b/src/nvidia/src/kernel/gpu/mem_mgr/context_dma.c index 22334d09a9..62e1ed1a90 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/context_dma.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/context_dma.c @@ -476,9 +476,20 @@ _ctxdmaConstruct gpuSetThreadBcState(pGpu, !pContextDma->bUnicast); - rmStatus = deviceGetByGpu(pClient, pGpu, NV_TRUE, &pDevice); - if (rmStatus != NV_OK) - return NV_ERR_INVALID_OBJECT_PARENT; + if (hSubDevice == 0) + { + // + // We verified that pMemory is parented by Device. + // pGpu == NULL & hSubdevice == 0 errors out above. + // + pDevice = pMemory->pDevice; + } + else + { + rmStatus = deviceGetByGpu(pClient, pGpu, NV_TRUE, &pDevice); + if (rmStatus != NV_OK) + return NV_ERR_INVALID_OBJECT_PARENT; + } pContextDma->pDevice = pDevice; diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/dma.c b/src/nvidia/src/kernel/gpu/mem_mgr/dma.c index dc6188a5b6..f4fc03e261 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/dma.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/dma.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -157,10 +157,14 @@ dmaAllocMap_IMPL if ((pKernelMIGManager != NULL) && kmigmgrIsMIGMemPartitioningEnabled(pGpu, pKernelMIGManager)) { - NvHandle hClient = RES_GET_CLIENT_HANDLE(pVirtualMemory); + RsClient *pClient = RES_GET_CLIENT(pVirtualMemory); + NvHandle hDevice = RES_GET_PARENT_HANDLE(pVirtualMemory); MIG_INSTANCE_REF ref; + Device *pDevice; - NV_ASSERT_OK_OR_RETURN(kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, &ref)); + NV_ASSERT_OK_OR_RETURN(deviceGetByHandle(pClient, hDevice, &pDevice)); + + NV_ASSERT_OK_OR_RETURN(kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, &ref)); swizzId = ref.pKernelMIGGpuInstance->swizzId; } diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/fbsr.c b/src/nvidia/src/kernel/gpu/mem_mgr/fbsr.c index b4d412b973..57655a9587 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/fbsr.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/fbsr.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2009-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2009-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -75,7 +75,8 @@ fbsrReserveSysMemoryForPowerMgmt_IMPL if (status != NV_OK) return status; - status = memdescAlloc(pFbsr->pSysReservedMemDesc); + memdescTagAlloc(status, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_18, pFbsr->pSysReservedMemDesc); if (status != NV_OK) { memdescDestroy(pFbsr->pSysReservedMemDesc); @@ -102,13 +103,3 @@ fbsrFreeReservedSysMemoryForPowerMgmt_IMPL(OBJFBSR *pFbsr) pFbsr->pSysReservedMemDesc = NULL; } } - -/*! - * @brief create channel for FB save/restore. - * - * @param[in] pGpu OBJGPU pointer - * @param[in] pFbsr OBJFBSR pointer - * - * @returns status - */ - diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/heap.c b/src/nvidia/src/kernel/gpu/mem_mgr/heap.c index b3a6bc55dd..42798e40a6 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/heap.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/heap.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -57,7 +57,7 @@ typedef enum // // Statics // -static NV_STATUS _heapBlockFree(OBJGPU *, Heap *, MEM_BLOCK *); +static NV_STATUS _heapBlockFree(OBJGPU *, Heap *, NvHandle, NvHandle, MEM_BLOCK *); static void _heapSetTexturePlacement(Heap *, NvU32, NvU32, NvBool*, NvU32*, NvU8*); static NV_STATUS _heapGetMaxFree(Heap *, NvU64 *, NvU64 *); @@ -737,7 +737,7 @@ heapDestruct_IMPL pBlock->allocedMemDesc = NV_FALSE; } - _heapBlockFree(pGpu, pHeap, pBlock); + _heapBlockFree(pGpu, pHeap, NV01_NULL_OBJECT, NV01_NULL_OBJECT, pBlock); // restart scanning the list, if the heap->pBlockList changed if (pBlockFirst != pHeap->pBlockList) @@ -1218,7 +1218,8 @@ _heapBlacklistSingleChunk // Allocate memory for this page. This is marked as an internal RM allocation // and will be saved/restored during suspend/resume // - status = memdescAlloc(pBlacklistChunk->pMemDesc); + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_78, + pBlacklistChunk->pMemDesc); if (NV_OK != status) { // no use for the memdesc if page couldn't be allocated @@ -1932,6 +1933,8 @@ static NV_STATUS _heapBlockFree ( OBJGPU *pGpu, Heap *pHeap, + NvHandle hClient, + NvHandle hDevice, MEM_BLOCK *pBlock ) { @@ -1999,6 +2002,8 @@ static NV_STATUS _heapBlockFree pFbAllocInfo->pageFormat->attr = pBlock->hwResource.attr; pFbAllocInfo->pageFormat->attr2 = pBlock->hwResource.attr2; pFbAllocInfo->ctagOffset = pBlock->hwResource.ctagOffset; + pFbAllocInfo->hClient = hClient; + pFbAllocInfo->hDevice = hDevice; memmgrFreeHwResources(pGpu, pMemoryManager, pFbAllocInfo); @@ -2271,6 +2276,8 @@ heapFree_IMPL ( OBJGPU *pGpu, Heap *pHeap, + NvHandle hClient, + NvHandle hDevice, NvU32 owner, MEMORY_DESCRIPTOR *pMemDesc ) @@ -2352,7 +2359,7 @@ heapFree_IMPL // pMemDesc->PteKind = 0; } - if ((status = _heapBlockFree(pGpu, pHeap, pBlock)) != NV_OK) + if ((status = _heapBlockFree(pGpu, pHeap, hClient, hDevice, pBlock)) != NV_OK) { NV_ASSERT(0); } @@ -2417,7 +2424,7 @@ heapFree_IMPL continue; } - if (NV_OK != (status = _heapBlockFree(pGpu, pHeap, pBlock))) + if (NV_OK != (status = _heapBlockFree(pGpu, pHeap, hClient, hDevice, pBlock))) return status; // check if we need to dynamically blacklist the page @@ -2755,7 +2762,6 @@ NV_STATUS heapAllocHint_IMPL NvU64 pageSize = 0; NvU32 flags; NvU32 owner; - NvU32 tiledAttr; // Check for valid size. NV_ASSERT_OR_RETURN((pAllocHint->pSize != NULL), NV_ERR_INVALID_ARGUMENT); @@ -2936,28 +2942,7 @@ NV_STATUS heapAllocHint_IMPL *pAllocHint->pHeight = pFbAllocInfo->height; pAllocHint->pad = pFbAllocInfo->pad; - // Special Case for Tiled Allocations - // Adjust the size so we don't use the partial tile areas - tiledAttr = DRF_VAL(OS32, _ATTR, _TILED, *pAllocHint->pAttr); - if (tiledAttr) - { - *pAllocHint->pSize = pFbAllocInfo->pitch * pFbAllocInfo->height; - if (pFbAllocInfo->size > *pAllocHint->pSize) - { - pAllocHint->pad += (pFbAllocInfo->size - *pAllocHint->pSize); - } - else if (pFbAllocInfo->size != *pAllocHint->pSize) - { - NV_PRINTF(LEVEL_ERROR, - "nvrm: Hint Allocation Size Error %llx %llx\n", - pFbAllocInfo->size, *pAllocHint->pSize); - DBG_BREAKPOINT(); - } - } - else - { - *pAllocHint->pSize = pFbAllocInfo->size; // returned to caller - } + *pAllocHint->pSize = pFbAllocInfo->size; // returned to caller pAllocHint->alignAdjust = 0; @@ -2984,7 +2969,6 @@ NV_STATUS heapHwAlloc_IMPL NV_STATUS status = NV_OK; FB_ALLOC_INFO *pFbAllocInfo = NULL; FB_ALLOC_PAGE_FORMAT *pFbAllocPageFormat = NULL; - NvU32 tiledAttr; NvU64 pageSize = 0; NV_MEMORY_HW_RESOURCES_ALLOCATION_PARAMS *pUserParams = pHwAlloc->pUserParams; @@ -3129,28 +3113,7 @@ NV_STATUS heapHwAlloc_IMPL pUserParams->kind = pFbAllocInfo->pageFormat->kind; pHwAlloc->hwResId = pFbAllocInfo->hwResId; - // Special Case for Tiled Allocations - // Adjust the size so we don't use the partial tile areas - tiledAttr = DRF_VAL(OS32, _ATTR, _TILED, pFbAllocInfo->pageFormat->attr); - if (tiledAttr) - { - pUserParams->size = pFbAllocInfo->pitch * pFbAllocInfo->height; - if (pFbAllocInfo->size > pUserParams->size) - { - pHwAlloc->pad += (NvU64_LO32(pFbAllocInfo->size) - pUserParams->size); - } - else if (pFbAllocInfo->size != pUserParams->size) - { - NV_PRINTF(LEVEL_ERROR, - "nvrm: Hint Allocation Size Error %llx %llx\n", - pFbAllocInfo->size, pUserParams->size); - DBG_BREAKPOINT(); - } - } - else - { - pUserParams->size = pFbAllocInfo->size; // returned to caller - } + pUserParams->size = pFbAllocInfo->size; // returned to caller pHwAlloc->hwResource.attr = pFbAllocInfo->retAttr; pHwAlloc->hwResource.attr2 = pFbAllocInfo->retAttr2; @@ -3204,6 +3167,8 @@ void heapHwFree_IMPL pFbAllocInfo->size = pMemory->Length; pFbAllocInfo->format = memdescGetPteKind(pMemory->pMemDesc); pFbAllocInfo->offset = ~0; + pFbAllocInfo->hClient = RES_GET_CLIENT_HANDLE(pMemory); + pFbAllocInfo->hDevice = RES_GET_HANDLE(pMemory->pDevice); // // vGPU: @@ -4107,7 +4072,7 @@ _heapAllocNoncontig pCurrBlock = pSavedAllocList->noncontigAllocListNext; - unwindStatus = _heapBlockFree(pGpu, pHeap, pSavedAllocList); + unwindStatus = _heapBlockFree(pGpu, pHeap, hClient, pFbAllocInfo->hDevice, pSavedAllocList); if (unwindStatus != NV_OK) { @@ -4326,7 +4291,8 @@ heapBlackListPages_IMPL // Allocate memory for this page. This is marked as an internal RM // allocation and WILL be saved/restored during suspend/resume. // - status = memdescAlloc(pBlackList->pBlacklistChunks[j].pMemDesc); + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_79, + pBlackList->pBlacklistChunks[j].pMemDesc); if (NV_OK != status) { // No use for the memdesc if the page couldn't be allocated diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_ctrl.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_ctrl.c index b0594e4e6c..2ec8c99eb6 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_ctrl.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_ctrl.c @@ -32,9 +32,10 @@ #include "core/core.h" #include "os/os.h" #include "gpu/mem_sys/kern_mem_sys.h" -#include "gpu/mem_mgr/mem_mgr.h" #include "gpu/mem_mgr/heap.h" #include "platform/platform.h" +#include "gpu/mem_mgr/mem_mgr.h" + #include "gpu/mem_mgr/mem_desc.h" #include "rmapi/client_resource.h" #include "rmapi/control.h" @@ -171,7 +172,7 @@ memCtrlCmdGetSurfaceInfoLvm_IMPL case NV0041_CTRL_SURFACE_INFO_INDEX_PHYS_ATTR: { if (pMemory->pHwResource != NULL) - data = pMemory->pHwResource->attr & (DRF_SHIFTMASK(NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_PAGE_SIZE) | DRF_SHIFTMASK(NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY)); + data = pMemory->pHwResource->attr & (DRF_SHIFTMASK(NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_PAGE_SIZE) | DRF_SHIFTMASK(NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY) | DRF_SHIFTMASK(NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_FORMAT)); break; } case NV0041_CTRL_SURFACE_INFO_INDEX_ADDR_SPACE_TYPE: @@ -234,6 +235,29 @@ memCtrlCmdGetSurfaceInfoLvm_IMPL } +NV_STATUS +memCtrlCmdGetSurfacePhysAttrLvm_IMPL +( + Memory *pMemory, + NV0041_CTRL_GET_SURFACE_PHYS_ATTR_PARAMS *pGPAP +) +{ + OBJGPU *pGpu = pMemory->pGpu; + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + NvU32 _zcullId, _lineMin, _lineMax; + NV_STATUS status = NV_OK; + + // get desired new attributes + status = memmgrGetSurfacePhysAttr_HAL(pGpu, pMemoryManager, pMemory, &pGPAP->memOffset, &pGPAP->memAperture, + &pGPAP->memFormat, &pGPAP->comprOffset, &pGPAP->comprFormat, + &_lineMin, &_lineMax, &_zcullId, + &pGPAP->gpuCacheAttr, &pGPAP->gpuP2PCacheAttr, + &pGPAP->contigSegmentSize); + + return status; +} + + NV_STATUS memCtrlCmdSurfaceFlushGpuCache_IMPL ( diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_desc.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_desc.c index 2eb6ff0f92..a5f21602a3 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_desc.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_desc.c @@ -370,6 +370,7 @@ memdescCreate pMemDesc->gfid = GPU_GFID_PF; pMemDesc->bUsingSuballocator = NV_FALSE; pMemDesc->bDeferredFree = NV_FALSE; + pMemDesc->numaNode = NV0000_CTRL_NO_NUMA_NODE; pMemDesc->libosRegionHandle = 0; pMemDesc->baseVirtualAddress = 0; @@ -549,6 +550,13 @@ memdescDestroy MEM_DESC_DESTROY_CALLBACK *pCb = memdescGetDestroyCallbackList(pMemDesc); MEM_DESC_DESTROY_CALLBACK *pNext; + if (pMemDesc->_flags & MEMDESC_FLAGS_RESTORE_PTE_KIND_ON_FREE) + { + NV_ASSERT_OK(kbusUpdateStaticBar1VAMapping_HAL(pMemDesc->pGpu, + GPU_GET_KERNEL_BUS(pMemDesc->pGpu), pMemDesc, + 0, memdescGetSize(pMemDesc), NV_TRUE)); + } + if (pMemDesc->_flags & MEMDESC_FLAGS_DUMMY_TOPLEVEL) { // When called from RmFreeFrameBuffer() and memdescFree could not do it because it is unallocated. @@ -618,6 +626,12 @@ memdescDestroy portMemFree(pMemDesc->pSubMemDescList); pMemDesc->pSubMemDescList = NULL; + if (pMemDesc->pPteEgmMappings != NULL) + { + portMemFree(pMemDesc->pPteEgmMappings); + pMemDesc->pPteEgmMappings = NULL; + } + if (pMemDesc->_pParentDescriptor) { if ((pMemDesc->_flags & MEMDESC_FLAGS_PRE_ALLOCATED) == 0) @@ -695,6 +709,50 @@ _memdescAllocVprRegion return NV_ERR_NOT_SUPPORTED; } +/*! + * @brief Allocate and populate the EGM array based off of the already + * populated _pteArray of the memdesc + * + * @param[in] pMemDesc Memory descriptor to allocate EGM array in + * @param[in] pMemoryManager Memory manager for EGM base addr + * + * @returns NV_OK on successful allocation. NV_ERR if not. + */ +static NV_INLINE NV_STATUS +_memdescAllocEgmArray +( + MEMORY_DESCRIPTOR *pMemDesc, + MemoryManager *pMemoryManager +) +{ + // + // Since we allocate an extra PTE, we need to account for that in case we + // need it for the EGM array. This is why there is a '+ 1' for pageCount. + // + NvU64 i; + NvU64 pageCount = pMemDesc->PageCount + 1; + + if (pMemDesc->_flags & MEMDESC_FLAGS_PHYSICALLY_CONTIGUOUS) + { + pageCount = 1; + } + + if (pMemDesc->pPteEgmMappings == NULL) + { + pMemDesc->pPteEgmMappings = portMemAllocNonPaged(sizeof(RmPhysAddr) * pageCount); + } + + NV_ASSERT_OR_RETURN(pMemDesc->pPteEgmMappings != NULL, NV_ERR_NO_MEMORY); + + for (i = 0; i < pageCount; i++) + { + pMemDesc->pPteEgmMappings[i] = pMemDesc->_pteArray[i] - + pMemoryManager->localEgmBasePhysAddr; + } + + return NV_OK; +} + /*! * @brief Lower memdesc allocation layer. Provides underlying allocation * functionality. @@ -727,6 +785,7 @@ _memdescAllocInternal switch (pMemDesc->_addressSpace) { + case ADDR_EGM: case ADDR_SYSMEM: // System memory can be obtained from osAllocPages status = osAllocPages(pMemDesc); @@ -734,6 +793,13 @@ _memdescAllocInternal { goto done; } + if (memdescIsEgm(pMemDesc)) + { + NV_ASSERT_OK_OR_GOTO(status, + _memdescAllocEgmArray(pMemDesc, + GPU_GET_MEMORY_MANAGER(pGpu)), + done); + } // // The pages have been allocated, so mark the descriptor as @@ -748,6 +814,7 @@ _memdescAllocInternal // used. // if (!memdescGetFlag(pMemDesc, MEMDESC_FLAGS_CPU_ONLY) && + !memdescIsEgm(pMemDesc) && !memdescGetFlag(pMemDesc, MEMDESC_FLAGS_SKIP_IOMMU_MAPPING)) { status = memdescMapIommu(pMemDesc, pGpu->busInfo.iovaspaceId); @@ -789,67 +856,6 @@ _memdescAllocInternal } break; - case ADDR_EGM: - { - MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); - NvU64 i; - - - NV_ASSERT_OK_OR_GOTO(status, osAllocPages(pMemDesc), done); - - pMemDesc->Allocated = NV_TRUE; - - // - // EGM address in the GMMU PTE should be zero base address and so - // the EGM base address is subtracted from the allocated EGM - // address. HSHUB later adds the socket local EGM base system physical address(SPA) - // before sending the transaction to TH500. zero-base address is - // required in passthrough virtualization where guest physical address - // is programmed in the GMMU PTE and the SPA is available only in - // the HSHUB registers. - // - // zero-base address is possible only when the EGM base address is - // available. There are platforms(like off-DUT MODS and dGPU MODS) - // where this is not available and full address is populated in - // the GMMU PTE itself and HSHUB is not programmed to add the SPA. - // - if (pMemoryManager->localEgmBasePhysAddr != 0) - { - for (i = 0; i < memdescGetPteArraySize(pMemDesc, AT_GPU); i++) - { - RmPhysAddr addr = memdescGetPhysAddr(pMemDesc, AT_GPU, i * pMemDesc->pageArrayGranularity); - NV_ASSERT_TRUE_OR_GOTO(status, addr > pMemoryManager->localEgmBasePhysAddr, - NV_ERR_INVALID_STATE, done); - memdescSetPte(pMemDesc, AT_GPU, i, addr - pMemoryManager->localEgmBasePhysAddr); - NV_PRINTF(LEVEL_INFO, "EGM allocation. pte index: %lld addr: 0x%llx zero-base addr: 0x%llx\n", - i, addr, addr - pMemoryManager->localEgmBasePhysAddr); - } - } - - if ((pMemDesc->_flags & MEMDESC_FLAGS_PHYSICALLY_CONTIGUOUS) && - RMCFG_FEATURE_PLATFORM_MODS) - { - if (pMemDesc->Alignment > RM_PAGE_SIZE) - { - RmPhysAddr addr = memdescGetPhysAddr(pMemDesc, AT_CPU, 0); - NvU64 offset; - - NV_ASSERT((addr & (RM_PAGE_SIZE - 1)) == 0); - - NV_ASSERT((pMemDesc->Alignment & (pMemDesc->Alignment - 1)) == 0); - offset = addr & (pMemDesc->Alignment - 1); - - if (offset) - { - NV_ASSERT((pMemDesc->PageCount * pMemDesc->pageArrayGranularity - pMemDesc->Size) >= offset); - NV_ASSERT(pMemDesc->PteAdjust == 0); - pMemDesc->PteAdjust += NvU64_LO32(pMemDesc->Alignment - offset); - } - } - } - - break; - } case ADDR_FBMEM: { Heap *pHeap = pMemDesc->pHeap; @@ -1031,8 +1037,14 @@ _memdescAllocInternal done: if (status == NV_OK) + { memdescPrintMemdesc(pMemDesc, NV_TRUE, MAKE_NV_PRINTF_STR("memdesc allocated")); - + } + else if (pMemDesc->pPteEgmMappings != NULL) + { + portMemFree(pMemDesc->pPteEgmMappings); + pMemDesc->pPteEgmMappings = NULL; + } portMemFree(pFbAllocPageFormat); portMemFree(pFbAllocInfo); @@ -2270,7 +2282,7 @@ void memdescUnmapInternal (mapType == MEMDESC_MAP_INTERNAL_TYPE_SYSMEM_DIRECT || mapType == MEMDESC_MAP_INTERNAL_TYPE_BAR2)) { kbusFlush_HAL(pGpu, GPU_GET_KERNEL_BUS(pGpu), - kbusGetFlushAperture(GPU_GET_KERNEL_BUS(pGpu), memdescGetAddressSpace(pMemDesc)) | BUS_FLUSH_USE_PCIE_READ); + kbusGetFlushAperture(GPU_GET_KERNEL_BUS(pGpu), memdescGetAddressSpace(pMemDesc))); } } @@ -2345,7 +2357,7 @@ memdescDescribe } pMemDesc->Size = Size; - pMemDesc->ActualSize = Size; + pMemDesc->ActualSize = NV_ROUNDUP(Size, pMemDesc->pageArrayGranularity); pMemDesc->_flags |= MEMDESC_FLAGS_PHYSICALLY_CONTIGUOUS; pMemDesc->_addressSpace = AddressSpace; pMemDesc->_pteArray[0] = Base & ~RM_PAGE_MASK; @@ -2553,6 +2565,9 @@ memdescCreateSubMem MEMORY_DESCRIPTOR *pLast; MEMORY_DESCRIPTOR *pNew; OBJGPU *pGpuChild; + const NvU64 pageArrayGranularity = pMemDesc->pageArrayGranularity; + const NvU64 pageArrayGranularityMask = pMemDesc->pageArrayGranularity - 1; + const NvU32 pageArrayGranularityShift = BIT_IDX_64(pMemDesc->pageArrayGranularity); // Default to the original memdesc's GPU if none is specified if (pGpu == NULL) @@ -2615,6 +2630,12 @@ memdescCreateSubMem else pMemDescNew->_flags &= ~MEMDESC_FLAGS_KERNEL_MODE; + // + // This flag used to indicate the memdesc needs to restore pte kind + // when it is freed. It should only not be set for any sub memDesc. + // + pMemDescNew->_flags &= ~MEMDESC_FLAGS_RESTORE_PTE_KIND_ON_FREE; + pMemDescNew->Size = Size; pMemDescNew->_pteKind = pMemDesc->_pteKind; pMemDescNew->_hwResId = pMemDesc->_hwResId; @@ -2623,6 +2644,7 @@ memdescCreateSubMem else pMemDescNew->_flags &= ~MEMDESC_FLAGS_ENCRYPTED; pMemDescNew->_pageSize = pMemDesc->_pageSize; + pMemDescNew->pageArrayGranularity = pageArrayGranularity; pMemDescNew->_gpuCacheAttrib = pMemDesc->_gpuCacheAttrib; pMemDescNew->_gpuP2PCacheAttrib = pMemDesc->_gpuP2PCacheAttrib; pMemDescNew->gfid = pMemDesc->gfid; @@ -2630,6 +2652,7 @@ memdescCreateSubMem pMemDescNew->_pParentDescriptor = pMemDesc; pMemDesc->childDescriptorCnt++; pMemDescNew->bRmExclusiveUse = pMemDesc->bRmExclusiveUse; + pMemDescNew->numaNode = pMemDesc->numaNode; pMemDescNew->subMemOffset = Offset; @@ -2642,8 +2665,15 @@ memdescCreateSubMem { // Compute the base address, then fill it in RmPhysAddr Base = pMemDesc->_pteArray[0] + pMemDesc->PteAdjust + Offset; - pMemDescNew->_pteArray[0] = Base & ~RM_PAGE_MASK; - pMemDescNew->PteAdjust = NvU64_LO32(Base) & RM_PAGE_MASK; + pMemDescNew->_pteArray[0] = Base & ~pageArrayGranularityMask; + pMemDescNew->PteAdjust = NvU64_LO32(Base) & pageArrayGranularityMask; + if (memdescIsEgm(pMemDesc)) + { + NV_ASSERT_OK_OR_GOTO(status, + _memdescAllocEgmArray(pMemDescNew, + GPU_GET_MEMORY_MANAGER(pGpu)), + fail); + } } else { @@ -2655,8 +2685,8 @@ memdescCreateSubMem Adjust = pMemDesc->PteAdjust + Offset; // Break it down into pages (PageIndex) and bytes (PteAdjust) - PageIndex = (NvU32)(Adjust >> RM_PAGE_SHIFT); - pMemDescNew->PteAdjust = NvU64_LO32(Adjust) & RM_PAGE_MASK; + PageIndex = (NvU32)(Adjust >> pageArrayGranularityShift); + pMemDescNew->PteAdjust = NvU64_LO32(Adjust) & pageArrayGranularityMask; // Fill in the PTEs; remember to copy the extra PTE, in case we need it if (pMemDesc->PageCount) @@ -2685,10 +2715,18 @@ memdescCreateSubMem pMemDescNew->_pteArray[i] = pMemDescNew->_pteArray[i - 1] + pMemDescNew->pageArrayGranularity; } } + if (memdescIsEgm(pMemDesc)) + { + NV_ASSERT_OK_OR_GOTO(status, + _memdescAllocEgmArray(pMemDescNew, + GPU_GET_MEMORY_MANAGER(pGpu)), + fail); + } } } if ((pMemDesc->_addressSpace == ADDR_SYSMEM) && + !memdescIsEgm(pMemDesc) && !memdescGetFlag(memdescGetMemDescFromGpu(pMemDesc, pGpu), MEMDESC_FLAGS_CPU_ONLY) && !memdescGetFlag(memdescGetMemDescFromGpu(pMemDesc, pGpu), MEMDESC_FLAGS_MAP_SYSCOH_OVER_BAR1) && !memdescGetFlag(memdescGetMemDescFromGpu(pMemDesc, pGpu), MEMDESC_FLAGS_SKIP_IOMMU_MAPPING)) @@ -2750,6 +2788,10 @@ memdescCreateSubMem *ppMemDescNew = pMemDescNew; return NV_OK; + +fail: + memdescDestroy(pMemDescNew); + return status; } /*! @@ -2903,6 +2945,8 @@ void memdescGetPhysAddrsForGpu(MEMORY_DESCRIPTOR *pMemDesc, NvU64 pageIndex; RmPhysAddr *pteArray = memdescGetPteArrayForGpu(pMemDesc, pGpu, addressTranslation); const NvBool contiguous = (memdescGetPteArraySize(pMemDesc, addressTranslation) == 1); + const NvU64 pageArrayGranularityMask = pMemDesc->pageArrayGranularity - 1; + const NvU32 pageArrayGranularityShift = BIT_IDX_64(pMemDesc->pageArrayGranularity); NV_ASSERT(!memdescHasSubDeviceMemDescs(pMemDesc)); offset += pMemDesc->PteAdjust; @@ -2915,9 +2959,9 @@ void memdescGetPhysAddrsForGpu(MEMORY_DESCRIPTOR *pMemDesc, } else { - pageIndex = offset >> RM_PAGE_SHIFT; + pageIndex = offset >> pageArrayGranularityShift; NV_CHECK_OR_RETURN_VOID(LEVEL_ERROR, pageIndex < pMemDesc->PageCount); - pAddresses[i] = pteArray[pageIndex] + (offset & RM_PAGE_MASK); + pAddresses[i] = pteArray[pageIndex] + (offset & pageArrayGranularityMask); } offset += stride; @@ -3127,10 +3171,17 @@ memdescGetPteArrayForGpu // Imported ADDR_FABRIC_V2 memdescs are device-less. if (pGpu != NULL) { - PIOVAMAPPING pIovaMap = memdescGetIommuMap(pMemDesc, pGpu->busInfo.iovaspaceId); - if (pIovaMap != NULL) + if (memdescIsEgm(pMemDesc) && (pMemDesc->pPteEgmMappings != NULL)) { - return pIovaMap->iovaArray; + return pMemDesc->pPteEgmMappings; + } + { + PIOVAMAPPING pIovaMap = memdescGetIommuMap(pMemDesc, + pGpu->busInfo.iovaspaceId); + if (pIovaMap != NULL) + { + return pIovaMap->iovaArray; + } } } @@ -4838,3 +4889,119 @@ memdescSetPageArrayGranularity return NV_OK; } + +NV_STATUS +memdescFillMemdescForPhysAttr +( + MEMORY_DESCRIPTOR *pMemDesc, + ADDRESS_TRANSLATION addressTranslation, + NvU64 *pOffset, + NvU32 *pMemAperture, + NvU32 *pMemKind, + NvU32 *pZCullId, + NvU32 *pGpuCacheAttr, + NvU32 *pGpuP2PCacheAttr, + NvU64 *contigSegmentSize +) +{ + NvU64 surfOffset = *pOffset, surfBase, surfLimit; + NvU32 zcbitmap; + + surfBase = memdescGetPhysAddr(pMemDesc, addressTranslation, 0); + surfLimit = surfBase + pMemDesc->Size - 1; + *pMemKind = memdescGetPteKind(pMemDesc); + + *pOffset = memdescGetPhysAddr(pMemDesc, addressTranslation, surfOffset); + + if (memdescGetAddressSpace(pMemDesc) == ADDR_FBMEM ) + *pMemAperture = NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR_APERTURE_VIDMEM; + else if (memdescGetAddressSpace(pMemDesc) == ADDR_SYSMEM) + *pMemAperture = NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR_APERTURE_SYSMEM; + else if (memdescGetAddressSpace(pMemDesc) == ADDR_EGM) + *pMemAperture = NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR_APERTURE_SYSMEM; + else if (memdescGetAddressSpace(pMemDesc) == ADDR_VIRTUAL ) + { + // + // XXX we could theoretically find whatever phys mem object is plugged + // in at surfOffset w/in the virt object... that'd mean scanning + // pMemory->DmaMappingList + // + return NV_ERR_NOT_SUPPORTED; + } + else + return NV_ERR_GENERIC; + + if (memdescGetGpuCacheAttrib(pMemDesc) == NV_MEMORY_CACHED) + { + *pGpuCacheAttr = NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED; + } + else if (memdescGetGpuCacheAttrib(pMemDesc) == NV_MEMORY_UNCACHED) + { + *pGpuCacheAttr = NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_UNCACHED; + } + else + { + *pGpuCacheAttr = NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED_UNKNOWN; + } + + if (memdescGetGpuP2PCacheAttrib(pMemDesc) == NV_MEMORY_CACHED) + { + *pGpuP2PCacheAttr = NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED; + } + else if (memdescGetGpuP2PCacheAttrib(pMemDesc) == NV_MEMORY_UNCACHED) + { + *pGpuP2PCacheAttr = NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_UNCACHED; + } + else + { + *pGpuP2PCacheAttr = NV0041_CTRL_GET_SURFACE_PHYS_ATTR_GPU_CACHED_UNKNOWN; + } + + zcbitmap = FB_HWRESID_ZCULL_VAL_FERMI(memdescGetHwResId(pMemDesc)); //bitmap form... need a scalar + for ( *pZCullId = 0; zcbitmap; zcbitmap >>= 1, *pZCullId += 1) {;;;} + *pZCullId -= 1; // side effect if there is no zcull id of setting ~0 + + *contigSegmentSize = surfLimit - (surfBase + surfOffset) + 1; + + if ( !memdescGetContiguity(pMemDesc, addressTranslation)) + { + // XXX overly conservative. we could scan the PTEs to find out if more pages are contig. + NvU64 surfOffsetLimitSame4KBPage = (4*1024)*((surfBase + surfOffset)/(4*1024)) + (4*1024) - 1; + if ( surfLimit >= surfOffsetLimitSame4KBPage ) + *contigSegmentSize = surfOffsetLimitSame4KBPage - (surfBase + surfOffset) + 1; + } + + return NV_OK; +} + +NvBool +memdescIsEgm +( + MEMORY_DESCRIPTOR *pMemDesc +) +{ + NV_ADDRESS_SPACE addrSpace = memdescGetAddressSpace(pMemDesc); + MemoryManager *pMemoryManager; + + if (pMemDesc->pGpu == NULL) + { + return NV_FALSE; + } + + pMemoryManager = GPU_GET_MEMORY_MANAGER(pMemDesc->pGpu); + if (pMemoryManager == NULL) + { + return NV_FALSE; + } + + if ((addrSpace == ADDR_EGM) || + (memmgrIsLocalEgmEnabled(pMemoryManager) && + (addrSpace == ADDR_SYSMEM) && + (memdescGetNumaNode(pMemDesc) != NV0000_CTRL_NO_NUMA_NODE))) + { + return NV_TRUE; + } + + return NV_FALSE; +} + diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c index 0457aeaf3c..5842f932af 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c @@ -37,6 +37,7 @@ #include "core/thread_state.h" #include "nvRmReg.h" #include "gpu/fsp/kern_fsp.h" +#include "gpu/pmu/kern_pmu.h" #include "gpu/mem_mgr/phys_mem_allocator/numa.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" #include "kernel/rmapi/rs_utils.h" @@ -75,6 +76,7 @@ memmgrConstructEngine_IMPL pMemoryManager->overrideInitHeapMin = 0; pMemoryManager->overrideHeapMax = ~0ULL; + pMemoryManager->Ram.fbOverrideSizeMb = ~0ULL; // Create the children rmStatus = _memmgrCreateChildObjects(pMemoryManager); @@ -115,7 +117,6 @@ _memmgrInitRegistryOverrides(OBJGPU *pGpu, MemoryManager *pMemoryManager) NvU32 data32; // Check for ram size override. - pMemoryManager->Ram.fbOverrideSizeMb = (NvU64)~0; if ((osReadRegistryDword(pGpu, NV_REG_STR_OVERRIDE_FB_SIZE, &data32) == NV_OK) && (data32 != 0)) { @@ -124,6 +125,10 @@ _memmgrInitRegistryOverrides(OBJGPU *pGpu, MemoryManager *pMemoryManager) // Used to override heap sizing at create pMemoryManager->Ram.fbOverrideSizeMb = data32; } + else + { + pMemoryManager->Ram.fbOverrideSizeMb = ~0ULL; + } // // Scrub on Free is enabled by default for GK110+ @@ -264,6 +269,12 @@ _memmgrInitRegistryOverrides(OBJGPU *pGpu, MemoryManager *pMemoryManager) pMemoryManager->bPmaAddrTree = NV_TRUE; NV_PRINTF(LEVEL_ERROR, "Enabled address tree for PMA for MODS.\n"); } + + if (osReadRegistryDword(pGpu, NV_REG_STR_DISABLE_GLOBAL_CE_UTILS, &data32) == NV_OK && + data32 == NV_REG_STR_DISABLE_GLOBAL_CE_UTILS_YES) + { + pMemoryManager->bDisableGlobalCeUtils = NV_TRUE; + } } NV_STATUS @@ -289,6 +300,148 @@ memmgrStatePreInitLocked_IMPL return NV_OK; } +static NV_STATUS +memmgrTestCeUtils +( + OBJGPU *pGpu, + MemoryManager *pMemoryManager +) +{ + MEMORY_DESCRIPTOR *pVidMemDesc = NULL; + MEMORY_DESCRIPTOR *pSysMemDesc = NULL; + TRANSFER_SURFACE vidSurface = {0}; + TRANSFER_SURFACE sysSurface = {0}; + NvU32 vidmemData = 0xAABBCCDD; + NvU32 sysmemData = 0x11223345; + NV_STATUS status; + + NV_ASSERT_OR_RETURN(pMemoryManager->pCeUtils != NULL, NV_ERR_INVALID_STATE); + + if (pMemoryManager->pCeUtils->pLiteKernelChannel != NULL) + { + // + // BUG 4167899: Temporarily skip test in case of lite mode + // It sometimes fails when called from acrGatherWprInformation_GM200() + // However, ACR is initialized without issues + // + return NV_OK; + } + + NV_ASSERT_OK_OR_GOTO(status, + memdescCreate(&pVidMemDesc, pGpu, sizeof vidmemData, RM_PAGE_SIZE, NV_TRUE, ADDR_FBMEM, + NV_MEMORY_UNCACHED, MEMDESC_FLAGS_NONE), + failed); + memdescTagAlloc(status, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_19, pVidMemDesc); + NV_ASSERT_OK_OR_GOTO(status, status, failed); + vidSurface.pMemDesc = pVidMemDesc; + + NV_ASSERT_OK_OR_GOTO(status, + memdescCreate(&pSysMemDesc, pGpu, sizeof sysmemData, 0, NV_TRUE, ADDR_SYSMEM, + NV_MEMORY_UNCACHED, MEMDESC_FLAGS_NONE), + failed); + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_138, + pSysMemDesc); + NV_ASSERT_OK_OR_GOTO(status, status, failed); + sysSurface.pMemDesc = pSysMemDesc; + + NV_ASSERT_OK_OR_GOTO(status, memmgrMemWrite(pMemoryManager, &vidSurface, &vidmemData, sizeof vidmemData, TRANSFER_FLAGS_NONE), failed); + NV_ASSERT_OK_OR_GOTO(status, memmgrMemWrite(pMemoryManager, &sysSurface, &sysmemData, sizeof sysmemData, TRANSFER_FLAGS_NONE), failed); + NV_ASSERT_OK_OR_GOTO(status, memmgrMemCopy (pMemoryManager, &sysSurface, &vidSurface, sizeof vidmemData, TRANSFER_FLAGS_PREFER_CE), failed); + NV_ASSERT_OK_OR_GOTO(status, memmgrMemRead (pMemoryManager, &sysSurface, &sysmemData, sizeof sysmemData, TRANSFER_FLAGS_NONE), failed); + NV_ASSERT_TRUE_OR_GOTO(status, sysmemData == vidmemData, NV_ERR_INVALID_STATE, failed); + +failed: + memdescFree(pVidMemDesc); + memdescDestroy(pVidMemDesc); + memdescFree(pSysMemDesc); + memdescDestroy(pSysMemDesc); + + return status; +} + +NV_STATUS +memmgrInitInternalChannels_IMPL +( + OBJGPU *pGpu, + MemoryManager *pMemoryManager +) +{ + NV_ASSERT_OK_OR_RETURN(memmgrScrubHandlePostSchedulingEnable_HAL(pGpu, pMemoryManager)); + + if (pMemoryManager->bDisableGlobalCeUtils || + pGpu->getProperty(pGpu, PDB_PROP_GPU_BROKEN_FB) || + pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_ALL_INST_IN_SYSMEM) || + pGpu->getProperty(pGpu, PDB_PROP_GPU_ZERO_FB) || + gpuIsCacheOnlyModeEnabled(pGpu) || + (IS_VIRTUAL(pGpu) && !IS_VIRTUAL_WITH_FULL_SRIOV(pGpu)) || + IS_SIMULATION(pGpu) || + IsDFPGA(pGpu)) + { + NV_PRINTF(LEVEL_INFO, "Skipping global CeUtils creation (unsupported platform)\n"); + + return NV_OK; + } + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_VIRTUALIZATION_MODE_HOST_VGPU) || + !memmgrIsPmaInitialized(pMemoryManager) || + RMCFG_FEATURE_PLATFORM_GSP || + RMCFG_FEATURE_PLATFORM_WINDOWS || + IS_MIG_ENABLED(pGpu) || + gpuIsCCorApmFeatureEnabled(pGpu) || + IsSLIEnabled(pGpu) || + RMCFG_FEATURE_ARCH_PPC64LE || + RMCFG_FEATURE_ARCH_AARCH64) + { + // BUG 4167899: Temporarily skip CeUtils creation on platforms where it fails + NV_PRINTF(LEVEL_INFO, "Skipping global CeUtils creation\n"); + + return NV_OK; + } + + NV_PRINTF(LEVEL_INFO, "Initializing global CeUtils instance\n"); + + NV_ASSERT_OK_OR_RETURN(memmgrInitCeUtils(pMemoryManager, NV_FALSE)); + + return NV_OK; +} + +NV_STATUS +memmgrDestroyInternalChannels_IMPL +( + OBJGPU *pGpu, + MemoryManager *pMemoryManager +) +{ + NV_PRINTF(LEVEL_INFO, "Destroying global CeUtils instance\n"); + + memmgrDestroyCeUtils(pMemoryManager, NV_FALSE); + + NV_ASSERT_OK_OR_RETURN(memmgrScrubHandlePreSchedulingDisable_HAL(pGpu, pMemoryManager)); + + return NV_OK; +} + +static NV_STATUS +memmgrPostSchedulingEnableHandler +( + OBJGPU *pGpu, + void *pUnusedData +) +{ + return memmgrInitInternalChannels(pGpu, GPU_GET_MEMORY_MANAGER(pGpu)); +} + +static NV_STATUS +memmgrPreSchedulingDisableHandler +( + OBJGPU *pGpu, + void *pUnusedData +) +{ + return memmgrDestroyInternalChannels(pGpu, GPU_GET_MEMORY_MANAGER(pGpu)); +} + NV_STATUS memmgrStateInitLocked_IMPL ( @@ -312,7 +465,12 @@ memmgrStateInitLocked_IMPL memmgrEnableDynamicPageOfflining_HAL(pGpu, pMemoryManager); memmgrScrubRegistryOverrides_HAL(pGpu, pMemoryManager); + memmgrScrubInit_HAL(pGpu, pMemoryManager); + NV_ASSERT_OK_OR_RETURN(kfifoAddSchedulingHandler(pGpu, + GPU_GET_KERNEL_FIFO(pGpu), + memmgrPostSchedulingEnableHandler, NULL, + memmgrPreSchedulingDisableHandler, NULL)); // // Allocate framebuffer heap. All memory must be allocated from here to keep the world @@ -433,7 +591,8 @@ memmgrVerifyGspDmaOps_IMPL NV_TRUE, ADDR_FBMEM, NV_MEMORY_UNCACHED, 0); NV_ASSERT_OR_RETURN(status == NV_OK, status); - status = memdescAlloc(pMemDesc); + memdescTagAlloc(status, + NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_20, pMemDesc); NV_ASSERT_OR_GOTO(status == NV_OK, failed); surf.pMemDesc = pMemDesc; @@ -512,6 +671,15 @@ memmgrStatePreUnload_IMPL NV_ASSERT((flags & GPU_STATE_FLAGS_PRESERVING) || pMemoryManager->zbcSurfaces == 0); + if (flags & GPU_STATE_FLAGS_PRESERVING) + { + // + // fifo won't send a PreSchedulingDisable callback on StateUnload + // destroy the channel manually, so that a CeUtils lite instance can be created for FBSR + // + memmgrDestroyCeUtils(pMemoryManager, NV_TRUE); + } + if (memmgrIsPmaEnabled(pMemoryManager) && memmgrIsPmaSupportedOnPlatform(pMemoryManager) && osNumaOnliningEnabled(pGpu->pOsGpuInfo) && @@ -613,6 +781,9 @@ memmgrStateDestroy_IMPL pMemoryManager->bLocalEgmEnabled = NV_FALSE; } + kfifoRemoveSchedulingHandler(pGpu, GPU_GET_KERNEL_FIFO(pGpu), + memmgrPostSchedulingEnableHandler, NULL, + memmgrPreSchedulingDisableHandler, NULL); memmgrScrubDestroy_HAL(pGpu, pMemoryManager); } @@ -709,7 +880,7 @@ memmgrCreateHeap_IMPL status = heapInit(pGpu, newHeap, pMemoryManager->heapStartOffset, size - pMemoryManager->heapStartOffset, HEAP_TYPE_RM_GLOBAL, GPU_GFID_PF, NULL); - NV_ASSERT_OR_RETURN(NV_OK == status, status); + NV_ASSERT_OK_OR_RETURN(status); if ((memmgrIsPmaInitialized(pMemoryManager)) && (pMemoryManager->pHeap->bHasFbRegions)) { @@ -718,6 +889,10 @@ memmgrCreateHeap_IMPL NV_ASSERT_OR_RETURN(status == NV_OK, status); } + NV_ASSERT_OK_OR_RETURN(memmgrValidateFBEndReservation_HAL(pGpu, pMemoryManager)); + + NV_ASSERT_OK_OR_RETURN(memmgrReserveMemoryForPmu_HAL(pGpu, pMemoryManager)); + // Reserve vidmem for FSP usage, including FRTS, WPR2 status = memmgrReserveMemoryForFsp(pGpu, pMemoryManager); if (status != NV_OK) @@ -1243,7 +1418,25 @@ memmgrDeterminePageSize_IMPL { addrSpace = memmgrAllocGetAddrSpace(pMemoryManager, pageFormatFlags, *pRetAttr); - bIsBigPageSupported = memmgrLargePageSupported(pMemoryManager, addrSpace); + // + // Bug 4270864: Temp hack until sysmem supports higher order allocations. + // We allow EGM to get allocated at higher page size. + // + if (memmgrIsLocalEgmEnabled(pMemoryManager) && + addrSpace == ADDR_SYSMEM && + FLD_TEST_DRF(OS32, _ATTR2, _FIXED_NUMA_NODE_ID, _YES, *pRetAttr2) && + // + // Bug 4270868: MODS has test cases which pass FIXED_NUMA_NODE_ID, + // but invalid node_id. Will remove once MODS tests get fixed. + // + !RMCFG_FEATURE_MODS_FEATURES) + { + bIsBigPageSupported = NV_TRUE; + } + else + { + bIsBigPageSupported = memmgrLargePageSupported(pMemoryManager, addrSpace); + } pageSizeAttr = dmaNvos32ToPageSizeAttr(*pRetAttr, *pRetAttr2); // @@ -1585,10 +1778,6 @@ memmgrCalcReservedFbSpace_IMPL if (!pMemoryManager->Ram.fbUsableMemSize) return; - // If reserved memory requirements have already been calculated, don't do it again. - if (pMemoryManager->bLddmReservedMemoryCalculated) - return; - memmgrCalcReservedFbSpaceHal_HAL(pGpu, pMemoryManager, &rsvdFastSize, &rsvdSlowSize, &rsvdISOSize); // If we have regions defined, fill in the per-segment reserved memory requirement @@ -1668,8 +1857,6 @@ memmgrCalcReservedFbSpace_IMPL pMemoryManager->Ram.fbRegion[idxISORegion].rsvdSize += rsvdISOSize; pMemoryManager->Ram.fbRegion[idxSlowRegion].rsvdSize += rsvdSlowSize; pMemoryManager->Ram.fbRegion[idxFastRegion].rsvdSize += rsvdFastSize; - - pMemoryManager->bLddmReservedMemoryCalculated = NV_TRUE; } } @@ -1800,6 +1987,7 @@ NV_STATUS memmgrFree_IMPL portMemSet(pFbAllocInfo, 0, sizeof(FB_ALLOC_INFO)); portMemSet(pFbAllocPageFormat, 0, sizeof(FB_ALLOC_PAGE_FORMAT)); pFbAllocInfo->hClient = hClient; + pFbAllocInfo->hDevice = hDevice; pFbAllocInfo->pageFormat = pFbAllocPageFormat; // @@ -1848,7 +2036,7 @@ NV_STATUS memmgrFree_IMPL return NV_OK; } - return heapFree(pGpu, pHeap, owner, pMemDesc); + return heapFree(pGpu, pHeap, hClient, hDevice, owner, pMemDesc); } NV_STATUS @@ -1992,24 +2180,25 @@ memmgrSetPartitionableMem_IMPL if ((!gpuIsCCorApmFeatureEnabled(pGpu) || IS_MIG_ENABLED(pGpu)) && !(pmaConfig & PMA_QUERY_NUMA_ONLINED)) { + NvU64 maxUsedPmaSize = 2 * RM_PAGE_SIZE_128K; // // PMA should be completely free at this point, otherwise we risk // not setting the right partitionable range (pmaGetLargestFree's // offset argument is not implemented as of this writing, so we // only get the base address of the region that contains it). There - // is a known allocation from the top-level scrubber channel that + // is a known allocation from the top-level scrubber/CeUtils channel that // is expected to be no larger than 128K. Issue a warning for any // other uses. // - if ((size > RM_PAGE_SIZE_128K) && - (freeMem < (size - RM_PAGE_SIZE_128K))) + if ((size > maxUsedPmaSize) && + (freeMem < (size - maxUsedPmaSize))) { NV_PRINTF(LEVEL_ERROR, - "Assumption that PMA is empty (after accounting for the top-level scrubber) is not met!\n"); + "Assumption that PMA is empty (after accounting for the top-level scrubber and CeUtils) is not met!\n"); NV_PRINTF(LEVEL_ERROR, " free space = 0x%llx bytes, total space = 0x%llx bytes\n", freeMem, size); - NV_ASSERT_OR_RETURN(freeMem >= (size - RM_PAGE_SIZE_128K), + NV_ASSERT_OR_RETURN(freeMem >= (size - maxUsedPmaSize), NV_ERR_INVALID_STATE); } } @@ -2295,17 +2484,6 @@ memmgrAllocMIGGPUInstanceMemory_PF NvS32 numaNodeId; NvU64 partitionBaseAddr = pAddrRange->lo; NvU64 partitionSize = rangeLength(*pAddrRange); - NvU64 unalignedPartitionBaseAddr = partitionBaseAddr; - NvU64 memblockSize = 0; - - NV_ASSERT_OK_OR_RETURN(osNumaMemblockSize(&memblockSize)); - // - // Align the partition base and size to memblock size - // Some FB memory is wasted here if it is not already aligned. - // - partitionBaseAddr = NV_ALIGN_UP64(unalignedPartitionBaseAddr, memblockSize); - partitionSize -= (partitionBaseAddr - unalignedPartitionBaseAddr); - partitionSize = NV_ALIGN_DOWN64(partitionSize, memblockSize); if (kmigmgrGetSwizzIdInUseMask(pGpu, pKernelMIGManager) == 0x0) { @@ -2684,7 +2862,7 @@ memmgrPageLevelPoolsGetInfo_IMPL ( OBJGPU *pGpu, MemoryManager *pMemoryManager, - NvHandle hClient, + Device *pDevice, RM_POOL_ALLOC_MEM_RESERVE_INFO **ppMemPoolInfo ) { @@ -2704,7 +2882,7 @@ memmgrPageLevelPoolsGetInfo_IMPL { MIG_INSTANCE_REF ref; NV_ASSERT_OK_OR_RETURN( - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, &ref)); + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, &ref)); pMemPool = ref.pKernelMIGGpuInstance->pPageTableMemPool; } else @@ -3201,47 +3379,6 @@ memmgrGetTopLevelScrubberStatus_IMPL *pbTopLevelScrubberConstructed = bTopLevelScrubberConstructed; } -/** - * @brief Save pre-MIG top level scrubber constructed status and teardown if constructed - */ -NV_STATUS -memmgrSaveAndDestroyTopLevelScrubber_IMPL -( - OBJGPU *pGpu, - MemoryManager *pMemoryManager -) -{ - // Save the pre-MIG top-level scrubber status for later - memmgrGetTopLevelScrubberStatus(pGpu, pMemoryManager, NULL, &pMemoryManager->MIGMemoryPartitioningInfo.bNonMIGTopLevelScrubber); - - // Destroy the top level scrubber if it exists - if (pMemoryManager->MIGMemoryPartitioningInfo.bNonMIGTopLevelScrubber) - { - // Delete top level scrubber - NV_ASSERT_OK_OR_RETURN(memmgrScrubHandlePreSchedulingDisable_HAL(pGpu, pMemoryManager)); - } - - return NV_OK; -} - -/** - * @brief Init top level scrubber if previous status was constructed - */ -NV_STATUS -memmgrInitSavedTopLevelScrubber_IMPL -( - OBJGPU *pGpu, - MemoryManager *pMemoryManager -) -{ - if (!pMemoryManager->MIGMemoryPartitioningInfo.bNonMIGTopLevelScrubber) - return NV_OK; - - NV_ASSERT_OK_OR_RETURN(memmgrScrubHandlePostSchedulingEnable_HAL(pGpu, pMemoryManager)); - - return NV_OK; -} - /*! * @brief Return the full address range for the partition assigend for the vGPU. * @@ -3337,6 +3474,51 @@ memmgrDiscoverMIGPartitionableMemoryRange_VF return NV_OK; } +NV_STATUS +memmgrValidateFBEndReservation_PF +( + OBJGPU *pGpu, + MemoryManager *pMemoryManager +) +{ + NV_STATUS status; + + NV_ASSERT_TRUE_OR_GOTO(status, + (pGpu != NULL) && + (pMemoryManager != NULL), + NV_ERR_INVALID_ARGUMENT, + memmgrValidateFBEndReservation_PF_exit); + + // If we reserved more memory from RM than we previously estimated + if (pMemoryManager->rsvdMemorySize > memmgrGetFBEndReserveSizeEstimate_HAL(pGpu, pMemoryManager)) + { + NV_PRINTF(LEVEL_ERROR, + "End of FB reservation was not enough (%u vs %u). Failing to boot.\n", + memmgrGetFBEndReserveSizeEstimate_HAL(pGpu, pMemoryManager), + pMemoryManager->rsvdMemorySize); + + NV_ASSERT_OK_OR_GOTO(status, + NV_ERR_INSUFFICIENT_RESOURCES, + memmgrValidateFBEndReservation_PF_exit); + } + +memmgrValidateFBEndReservation_PF_exit: + return status; +} + +NV_STATUS +memmgrReserveMemoryForPmu_MONOLITHIC +( + OBJGPU *pGpu, + MemoryManager *pMemoryManager +) +{ + NV_STATUS status = NV_OK; + + return status; +} + + NV_STATUS memmgrReserveMemoryForFsp_IMPL ( @@ -3498,20 +3680,47 @@ memmgrInitCeUtils_IMPL NvBool bFifoLite ) { + OBJGPU *pGpu = ENG_GET_GPU(pMemoryManager); NV0050_ALLOCATION_PARAMETERS ceUtilsParams = {0}; NV_ASSERT_OR_RETURN(pMemoryManager->pCeUtils == NULL, NV_ERR_INVALID_STATE); + if (!bFifoLite && pMemoryManager->pCeUtilsSuspended != NULL) + { + pMemoryManager->pCeUtils = pMemoryManager->pCeUtilsSuspended; + pMemoryManager->pCeUtilsSuspended = NULL; + return NV_OK; + } + ceUtilsParams.flags = bFifoLite ? DRF_DEF(0050_CEUTILS, _FLAGS, _FIFO_LITE, _TRUE) : 0; - return objCreate(&pMemoryManager->pCeUtils, pMemoryManager, CeUtils, ENG_GET_GPU(pMemoryManager), NULL, &ceUtilsParams); + + NV_ASSERT_OK_OR_RETURN(objCreate(&pMemoryManager->pCeUtils, pMemoryManager, CeUtils, ENG_GET_GPU(pMemoryManager), NULL, &ceUtilsParams)); + + NV_STATUS status = memmgrTestCeUtils(pGpu, pMemoryManager); + NV_ASSERT_OK(status); + if (status != NV_OK) + { + memmgrDestroyCeUtils(pMemoryManager, NV_FALSE); + } + + return status; } void memmgrDestroyCeUtils_IMPL ( - MemoryManager *pMemoryManager + MemoryManager *pMemoryManager, + NvBool bSuspendCeUtils ) { - objDelete(pMemoryManager->pCeUtils); + if (bSuspendCeUtils) + { + NV_ASSERT_OR_RETURN_VOID(pMemoryManager->pCeUtilsSuspended == NULL); + pMemoryManager->pCeUtilsSuspended = pMemoryManager->pCeUtils; + } + else + { + objDelete(pMemoryManager->pCeUtils); + } pMemoryManager->pCeUtils = NULL; } diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_ctrl.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_ctrl.c index a58d08a3da..40ebe4e52f 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_ctrl.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_ctrl.c @@ -353,7 +353,7 @@ subdeviceCtrlCmdFbGetMemAlignment_IMPL NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); NvHandle hObject = RES_GET_HANDLE(pSubdevice); - Heap *pHeap = vidmemGetHeap(pGpu, pDevice, NV_FALSE); + Heap *pHeap = vidmemGetHeap(pGpu, pDevice, NV_FALSE, NV_FALSE); HEAP_ALLOC_HINT_PARAMS AllocHint = {0}; NvU32 i; NvU64 _size, _alignment; @@ -645,8 +645,6 @@ subdeviceCtrlCmdFbGetFBRegionInfo_IMPL LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); - memmgrCalcReservedFbSpace(pGpu, pMemoryManager); - pGFBRIParams->numFBRegions = 0; // @@ -824,3 +822,4 @@ subdeviceCtrlCmdGbGetSemaphoreSurfaceLayout_IMPL return NV_OK; } + diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_gsp_client.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_gsp_client.c index 6ee4470885..ef879b0237 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_gsp_client.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_gsp_client.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -165,15 +165,12 @@ memmgrPreInitReservedMemory_FWCLIENT tmpAddr += BUS_COHERENT_LINK_TEST_BUFFER_SIZE; } - if (KBUS_BAR2_ENABLED(pKernelBus)) - { - // - // This has to be the very *last* thing in reserved memory as it - // will may grow past the 1MB reserved memory window. We cannot - // size it until memsysStateInitLockedHal_GK104. - // - memmgrReserveBar2BackingStore(pGpu, pMemoryManager, &tmpAddr); - } + // + // This has to be the very *last* thing in reserved memory as it + // will may grow past the 1MB reserved memory window. We cannot + // size it until memsysStateInitLockedHal_GK104. + // + memmgrReserveBar2BackingStore(pGpu, pMemoryManager, &tmpAddr); NV_ASSERT(NvU64_LO32(tmpAddr) == tmpAddr); pMemoryManager->rsvdMemorySize = NvU64_LO32(tmpAddr); diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_pwr_mgmt.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_pwr_mgmt.c index d8df1ef1e1..5928ccf507 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_pwr_mgmt.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_pwr_mgmt.c @@ -294,8 +294,17 @@ _memmgrAllocFbsrReservedRanges // Alloc the Memory descriptors for Fbsr Reserved regions, if not allocated. if (pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_BEFORE_BAR2PTE] == NULL) { - // Allocate Vid Mem descriptor for RM INSTANCE memory from start to BAR2PTE - size = memdescGetPhysAddr(pKernelBus->virtualBar2[GPU_GFID_PF].pPTEMemDesc, AT_GPU, 0) - pMemoryManager->rsvdMemoryBase; + if(IS_VIRTUAL_WITH_SRIOV(pGpu)) + { + // Allocate Vid Mem descriptor for RM INSTANCE memory from start to BAR2 PDE base. + size = memdescGetPhysAddr(pKernelBus->virtualBar2[GPU_GFID_PF].pPageLevelsMemDesc, AT_GPU, 0) - pMemoryManager->rsvdMemoryBase; + } + else + { + // Allocate Vid Mem descriptor for RM INSTANCE memory from start to BAR2PTE + size = memdescGetPhysAddr(pKernelBus->virtualBar2[GPU_GFID_PF].pPTEMemDesc, AT_GPU, 0) - pMemoryManager->rsvdMemoryBase; + } + NV_ASSERT_OK_OR_GOTO(status, memdescCreate(&pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_BEFORE_BAR2PTE], pGpu, size, 0, NV_TRUE, ADDR_FBMEM, @@ -308,14 +317,20 @@ _memmgrAllocFbsrReservedRanges if (pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_AFTER_BAR2PTE] == NULL) { - // Allocate Mem descriptors for AFTER_BAR2PTE, GSP HEAP, WPR, NON WPR and VGA Workspace regions + RmPhysAddr afterBar2PteRegionStart = 0; + NvU64 afterBar2PteRegionSize = 0; + + /* + * Allocate Mem descriptors for AFTER_BAR2PTE, GSP HEAP, WPR, NON WPR and VGA Workspace regions. + */ if (IS_GSP_CLIENT(pGpu)) { KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); - RmPhysAddr afterBar2PteRegionStart = memdescGetPhysAddr(pKernelBus->virtualBar2[GPU_GFID_PF].pPTEMemDesc, AT_GPU, 0) + + NvU64 afterBar2PteRegionEnd = 0; + afterBar2PteRegionStart = memdescGetPhysAddr(pKernelBus->virtualBar2[GPU_GFID_PF].pPTEMemDesc, AT_GPU, 0) + pKernelBus->virtualBar2[GPU_GFID_PF].pPTEMemDesc->Size; - NvU64 afterBar2PteRegionEnd = pMemoryManager->rsvdMemoryBase + pMemoryManager->rsvdMemorySize; - NvU64 afterBar2PteRegionSize = afterBar2PteRegionEnd - afterBar2PteRegionStart; + afterBar2PteRegionEnd = pMemoryManager->rsvdMemoryBase + pMemoryManager->rsvdMemorySize; + afterBar2PteRegionSize = afterBar2PteRegionEnd - afterBar2PteRegionStart; NvU64 gspHeapRegionStart = afterBar2PteRegionEnd; NvU64 gspHeapRegionSize = pKernelGsp->pWprMeta->gspFwRsvdStart - gspHeapRegionStart; NvU64 gspNonWprRegionSize = pKernelGsp->pWprMeta->gspFwWprStart - pKernelGsp->pWprMeta->gspFwRsvdStart; @@ -364,17 +379,34 @@ _memmgrAllocFbsrReservedRanges // Allocate Vid Mem descriptor for RM INSTANCE memory, specific to VGA i.e. after BAR2PTE to end. else { - NvU64 fbAddrSpaceSize = _memmgrGetFbEndExcludingLostOnSuspendRegions(pGpu, pMemoryManager); - size = (fbAddrSpaceSize) - memdescGetPhysAddr(pKernelBus->virtualBar2[GPU_GFID_PF].pPTEMemDesc, AT_GPU, 0) - pKernelBus->virtualBar2[GPU_GFID_PF].pPTEMemDesc->Size; + NvU64 fbAddrSpaceSize = _memmgrGetFbEndExcludingLostOnSuspendRegions(pGpu, pMemoryManager); + + if (IS_VIRTUAL_WITH_SRIOV(pGpu)) + { + /* + * From BAR2 region we skip BAR2 PDEs and CPU visible region PTEs as we rebuild them on restore. + * But we need to save CPU invisible region PTEs across S/R, hence AFTER_BAR2PTE range starts + * after CPU visible region PTEs ends. + */ + afterBar2PteRegionStart = pKernelBus->bar2[GPU_GFID_PF].pteBase + + pKernelBus->bar2[GPU_GFID_PF].cpuVisiblePgTblSize; + } + else + { + afterBar2PteRegionStart = memdescGetPhysAddr(pKernelBus->virtualBar2[GPU_GFID_PF].pPTEMemDesc, AT_GPU, 0) + + pKernelBus->virtualBar2[GPU_GFID_PF].pPTEMemDesc->Size; + } + + afterBar2PteRegionSize = fbAddrSpaceSize - afterBar2PteRegionStart; NV_ASSERT_OK_OR_GOTO(status, memdescCreate(&pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_AFTER_BAR2PTE], - pGpu, size, 0, NV_TRUE, ADDR_FBMEM, + pGpu, afterBar2PteRegionSize, 0, NV_TRUE, ADDR_FBMEM, NV_MEMORY_UNCACHED, MEMDESC_FLAGS_NONE), fail); memdescDescribe(pMemoryManager->fbsrReservedRanges[FBSR_RESERVED_INST_MEMORY_AFTER_BAR2PTE], ADDR_FBMEM, - memdescGetPhysAddr(pKernelBus->virtualBar2[GPU_GFID_PF].pPTEMemDesc, AT_GPU, 0) + pKernelBus->virtualBar2[GPU_GFID_PF].pPTEMemDesc->Size, size); + afterBar2PteRegionStart, afterBar2PteRegionSize); } } @@ -524,7 +556,7 @@ _memmgrWalkHeap(OBJGPU *pGpu, MemoryManager *pMemoryManager, OBJFBSR *pFbsr) * Error otherwise. */ NV_STATUS -memmgrAddMemNode +memmgrAddMemNode_IMPL ( OBJGPU *pGpu, MemoryManager *pMemoryManager, diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_regions.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_regions.c index dafb2d37e2..b47f84b894 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_regions.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_regions.c @@ -555,5 +555,4 @@ memmgrClearFbRegions_IMPL pMemoryManager->Ram.numFBRegions = 0; pMemoryManager->Ram.numFBRegionPriority = 0; pMemoryManager->Ram.reservedMemSize = 0; - pMemoryManager->bLddmReservedMemoryCalculated = NV_FALSE; } diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_scrub.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_scrub.c index d3f77fceca..0ec5ec1268 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_scrub.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_scrub.c @@ -713,7 +713,7 @@ _scrubCheckAndSubmit goto exit; } - _scrubWaitAndSave(pScrubber, pList, pagesToScrubCheck); + _scrubWaitAndSave(pScrubber, pScrubListCopy, pagesToScrubCheck); for (iter = 0; iter < pageCount; iter++) { diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_utils.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_utils.c index 8f5ccf0863..dedb7d16e8 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_utils.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_utils.c @@ -36,6 +36,8 @@ #include "gpu/bus/kern_bus.h" +#include "gpu/mem_mgr/ce_utils.h" + #include "kernel/gpu/conf_compute/ccsl.h" #include "class/cl0005.h" // NV01_EVENT @@ -56,34 +58,47 @@ memmgrGetMemTransferType ( MemoryManager *pMemoryManager, TRANSFER_SURFACE *pDst, - TRANSFER_SURFACE *pSrc + TRANSFER_SURFACE *pSrc, + NvU32 flags ) { TRANSFER_TYPE transferType = TRANSFER_TYPE_PROCESSOR; - OBJGPU *pGpu = ENG_GET_GPU(pMemoryManager); - KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + OBJGPU *pGpu = ENG_GET_GPU(pMemoryManager); + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); - // - // In case of copy, both dest and src will be passed - // In case of memset/memread/memwrite either dest or src will be passed - // - if ((pDst != NULL) && (pSrc != NULL) && - (memdescGetAddressSpace(pDst->pMemDesc) == ADDR_SYSMEM) && - (memdescGetAddressSpace(pSrc->pMemDesc) == ADDR_SYSMEM)) + if (flags & TRANSFER_FLAGS_PREFER_CE) { - transferType = TRANSFER_TYPE_PROCESSOR; + if (IS_SIMULATION(pGpu) && pSrc != NULL) + { + // + // This is significantly faster on fmodel for S/R (5min vs. 5sec) because of the + // backdoor memory reads and writes. + // Memset is not currently supported + // + return TRANSFER_TYPE_BAR0; + } + + if (pMemoryManager->pCeUtils != NULL) + { + return TRANSFER_TYPE_CE; + } + + NV_PRINTF(LEVEL_WARNING, "Can't copy using CE, falling back to other methods\n"); } - else if (((pDst != NULL) && - (memdescGetAddressSpace(pDst->pMemDesc) == ADDR_SYSMEM)) || - ((pSrc != NULL) && - (memdescGetAddressSpace(pSrc->pMemDesc) == ADDR_SYSMEM))) + + if ((pDst == NULL || memdescGetAddressSpace(pDst->pMemDesc) == ADDR_SYSMEM) && + (pSrc == NULL || memdescGetAddressSpace(pSrc->pMemDesc) == ADDR_SYSMEM)) { + // + // If the operation only touches sysmem, use processor copy + // transferType = TRANSFER_TYPE_PROCESSOR; } else if (kbusIsBarAccessBlocked(pKernelBus)) { transferType = TRANSFER_TYPE_GSP_DMA; } + return transferType; } @@ -110,7 +125,9 @@ _memmgrAllocAndMapSurface memdescCreate(ppMemDesc, pGpu, size, RM_PAGE_SIZE, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_UNCACHED, flags)); - NV_ASSERT_OK_OR_GOTO(status, memdescAlloc(*ppMemDesc), failed); + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_77, + (*ppMemDesc)); + NV_ASSERT_OK_OR_GOTO(status, status, failed); NV_ASSERT_OK_OR_GOTO(status, memdescMapOld(*ppMemDesc, 0, size, NV_TRUE, NV_PROTECT_READ_WRITE, @@ -508,13 +525,74 @@ memmgrMemCopyWithTransferType } break; case TRANSFER_TYPE_CE: - NV_PRINTF(LEVEL_INFO, "Add call to CE\n"); + { + NV_ASSERT_OR_RETURN(pMemoryManager->pCeUtils != NULL, NV_ERR_INVALID_STATE); + + CEUTILS_MEMCOPY_PARAMS params = {0}; + + params.pDstMemDesc = pDstInfo->pMemDesc; + params.dstOffset = pDstInfo->offset; + params.pSrcMemDesc = pSrcInfo->pMemDesc; + params.srcOffset = pSrcInfo->offset; + params.length = size; + + return ceutilsMemcopy(pMemoryManager->pCeUtils, ¶ms); + } + break; + case TRANSFER_TYPE_CE_PRI: + NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_STATE); + break; + case TRANSFER_TYPE_BAR0: + NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_STATE); break; } return NV_OK; } +static NV_STATUS +_memmgrMemReadOrWriteUsingStagingBuffer +( + MemoryManager *pMemoryManager, + TRANSFER_SURFACE *pAlloc, + void *pBuf, + NvU64 size, + NvU32 transferType, + NvBool bRead +) +{ + MEMORY_DESCRIPTOR *pStagingBuf = NULL; + void *pStagingBufMap = NULL; + void *pStagingBufPriv = NULL; + TRANSFER_SURFACE staging = {0}; + TRANSFER_SURFACE *pSrc = bRead ? pAlloc : &staging; + TRANSFER_SURFACE *pDst = bRead ? &staging : pAlloc; + NV_STATUS status = NV_OK; + + + NV_ASSERT_OK_OR_RETURN( + _memmgrAllocAndMapSurface(ENG_GET_GPU(pMemoryManager), size, &pStagingBuf, &pStagingBufMap, + &pStagingBufPriv)); + staging.pMemDesc = pStagingBuf; + + if (!bRead) + { + portMemCopy(pStagingBufMap, size, pBuf, size); + } + + NV_ASSERT_OK_OR_GOTO(status, memmgrMemCopyWithTransferType(pMemoryManager, pDst, pSrc, size, transferType, 0), failed); + + if (bRead) + { + portMemCopy(pBuf, size, pStagingBufMap, size); + } + +failed: + _memmgrUnmapAndFreeSurface(pStagingBuf, pStagingBufMap, pStagingBufPriv); + + return status; +} + /*! * @brief This function is used for setting a memory region to a constant state * using a specified memory transfer technique @@ -567,8 +645,27 @@ memmgrMemSetWithTransferType } break; case TRANSFER_TYPE_CE: - NV_PRINTF(LEVEL_INFO, "Add call to CE\n"); + { + NV_ASSERT_OR_RETURN(pMemoryManager->pCeUtils != NULL, NV_ERR_INVALID_STATE); + + CEUTILS_MEMSET_PARAMS params = {0}; + + params.pMemDesc = pDstInfo->pMemDesc; + params.offset = pDstInfo->offset; + params.length = size; + params.pattern = value; + + return ceutilsMemset(pMemoryManager->pCeUtils, ¶ms); + } + break; + case TRANSFER_TYPE_CE_PRI: + NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_STATE); + break; + case TRANSFER_TYPE_BAR0: + NV_PRINTF(LEVEL_ERROR, "BAR0 memset unimplemented\n"); + NV_ASSERT(0); break; + } return NV_OK; @@ -718,7 +815,11 @@ memmgrMemWriteWithTransferType } break; case TRANSFER_TYPE_CE: - NV_PRINTF(LEVEL_INFO, "Add call to CE\n"); + case TRANSFER_TYPE_CE_PRI: + case TRANSFER_TYPE_BAR0: + NV_ASSERT_OK_OR_RETURN( + _memmgrMemReadOrWriteUsingStagingBuffer(pMemoryManager, pDstInfo, pBuf, size, + transferType, NV_FALSE /* bRead */)); break; } @@ -788,7 +889,11 @@ memmgrMemReadWithTransferType } break; case TRANSFER_TYPE_CE: - NV_PRINTF(LEVEL_INFO, "Add call to CE\n"); + case TRANSFER_TYPE_CE_PRI: + case TRANSFER_TYPE_BAR0: + NV_ASSERT_OK_OR_RETURN( + _memmgrMemReadOrWriteUsingStagingBuffer(pMemoryManager, pSrcInfo, pBuf, size, + transferType, NV_TRUE /* bRead */)); break; } @@ -938,7 +1043,7 @@ memmgrMemCopy_IMPL ) { TRANSFER_TYPE transferType = memmgrGetMemTransferType(pMemoryManager, - pDstInfo, pSrcInfo); + pDstInfo, pSrcInfo, flags); return memmgrMemCopyWithTransferType(pMemoryManager, pDstInfo, pSrcInfo, size, transferType, flags); @@ -963,7 +1068,7 @@ memmgrMemSet_IMPL ) { TRANSFER_TYPE transferType = memmgrGetMemTransferType(pMemoryManager, - pDstInfo, NULL); + pDstInfo, NULL, flags); return memmgrMemSetWithTransferType(pMemoryManager, pDstInfo, value, size, transferType, flags); @@ -987,7 +1092,7 @@ memmgrMemDescMemSet_IMPL { TRANSFER_SURFACE transferSurface = {.offset = 0, .pMemDesc = pMemDesc}; TRANSFER_TYPE transferType = memmgrGetMemTransferType(pMemoryManager, - &transferSurface, NULL); + &transferSurface, NULL, flags); return memmgrMemSetWithTransferType(pMemoryManager, &transferSurface, value, (NvU32)memdescGetSize(pMemDesc), @@ -1014,7 +1119,7 @@ memmgrMemWrite_IMPL ) { TRANSFER_TYPE transferType = memmgrGetMemTransferType(pMemoryManager, - pDstInfo, NULL); + pDstInfo, NULL, flags); return memmgrMemWriteWithTransferType(pMemoryManager, pDstInfo, pBuf, size, transferType, flags); @@ -1040,7 +1145,7 @@ memmgrMemRead_IMPL ) { TRANSFER_TYPE transferType = memmgrGetMemTransferType(pMemoryManager, - NULL, pSrcInfo); + NULL, pSrcInfo, flags); return memmgrMemReadWithTransferType(pMemoryManager, pSrcInfo, pBuf, size, transferType, flags); @@ -1063,7 +1168,7 @@ memmgrMemBeginTransfer_IMPL ) { TRANSFER_TYPE transferType = memmgrGetMemTransferType(pMemoryManager, - pTransferInfo, NULL); + pTransferInfo, NULL, flags); MEMORY_DESCRIPTOR *pMemDesc = pTransferInfo->pMemDesc; NvU64 offset = pTransferInfo->offset; OBJGPU *pGpu = ENG_GET_GPU(pMemoryManager); @@ -1104,6 +1209,8 @@ memmgrMemBeginTransfer_IMPL break; case TRANSFER_TYPE_GSP_DMA: case TRANSFER_TYPE_CE: + case TRANSFER_TYPE_CE_PRI: + case TRANSFER_TYPE_BAR0: if (flags & TRANSFER_FLAGS_SHADOW_ALLOC) { NV_ASSERT_OR_RETURN((pPtr = portMemAllocNonPaged(memSz)), NULL); @@ -1137,7 +1244,7 @@ memmgrMemEndTransfer_IMPL ) { TRANSFER_TYPE transferType = memmgrGetMemTransferType(pMemoryManager, - pTransferInfo, NULL); + pTransferInfo, NULL, flags); MEMORY_DESCRIPTOR *pMemDesc = pTransferInfo->pMemDesc; NvU64 offset = pTransferInfo->offset; OBJGPU *pGpu = ENG_GET_GPU(pMemoryManager); @@ -1169,6 +1276,8 @@ memmgrMemEndTransfer_IMPL return; case TRANSFER_TYPE_GSP_DMA: case TRANSFER_TYPE_CE: + case TRANSFER_TYPE_CE_PRI: + case TRANSFER_TYPE_BAR0: if (pMapping != NULL) { NV_ASSERT_OK(memmgrMemWrite(pMemoryManager, pTransferInfo, pMapping, memSz, flags)); diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/method_notification.c b/src/nvidia/src/kernel/gpu/mem_mgr/method_notification.c index 68edc4f8cf..e4db3fe971 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/method_notification.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/method_notification.c @@ -270,7 +270,7 @@ NV_STATUS notifyFillNotifierArray * Notifier write is skipped when CPU kernel mapping is missing. * * @param[in] pGpu OBJGPU pointer - * @param[in] hClient NvU32 client handle + * @param[in] pDevice Device pointer * @param[in] hMemoryCtx Handle of a memory object to which NotifyGPUVABase belongs * @param[in] NotifyGPUVABase 64b GPU VA base address of semaphore * @param[in] Info32 32b info part @@ -286,7 +286,7 @@ NV_STATUS notifyFillNotifierArray NV_STATUS notifyFillNotifierGPUVATimestamp ( OBJGPU *pGpu, - RsClient *pClient, + Device *pDevice, NvHandle hMemoryCtx, NvU64 NotifyGPUVABase, NvV32 Info32, @@ -302,17 +302,11 @@ NV_STATUS notifyFillNotifierGPUVATimestamp NvU64 offset; NvU32 subdeviceInstance; NOTIFICATION *pNotifier; - Device *pDevice; - NV_STATUS status; - - status = deviceGetByGpu(pClient, pGpu, NV_TRUE, &pDevice); - if (status != NV_OK) - return status; notifyGPUVA = NotifyGPUVABase + (Index * sizeof(NOTIFICATION)); // Memory context is required for mapping lookup - bFound = CliGetDmaMappingInfo(pClient, + bFound = CliGetDmaMappingInfo(RES_GET_CLIENT(pDevice), RES_GET_HANDLE(pDevice), hMemoryCtx, notifyGPUVA, @@ -376,7 +370,7 @@ NV_STATUS notifyFillNotifierGPUVATimestamp * Gets current time and routes data to notifyFillNotifierGPUVATimestamp * * @param[in] pGpu OBJGPU pointer - * @param[in] hClient NvU32 client handle + * @param[in] pDevice Device pointer * @param[in] hMemoryCtx Handle of a memory object to which NotifyGPUVABase belongs * @param[in] NotifyGPUVABase 64b GPU VA base address of semaphore * @param[in] Info32 32b info part @@ -390,7 +384,7 @@ NV_STATUS notifyFillNotifierGPUVATimestamp NV_STATUS notifyFillNotifierGPUVA ( OBJGPU *pGpu, - RsClient *pClient, + Device *pDevice, NvHandle hMemoryCtx, NvU64 NotifyGPUVABase, NvV32 Info32, @@ -405,7 +399,7 @@ NV_STATUS notifyFillNotifierGPUVA tmrGetCurrentTime(pTmr, &Time); return notifyFillNotifierGPUVATimestamp(pGpu, - pClient, + pDevice, hMemoryCtx, NotifyGPUVABase, Info32, @@ -539,7 +533,7 @@ NV_STATUS notifyFillNotifierMemory * Semaphore write is skipped when CPU kernel mapping is missing. * * @param[in] pGpu OBJGPU pointer - * @param[in] hClient NvU32 client handle + * @param[in] pDevice Device pointer * @param[in] SemaphoreGPUVABase 64b GPU VA base address of semaphore * @param[in] ReleaseValue NvU32 value to write to semaphore upon release * @param[in] Index index of semaphore in semaphore array @@ -552,7 +546,7 @@ NV_STATUS notifyFillNotifierMemory NV_STATUS semaphoreFillGPUVATimestamp ( OBJGPU *pGpu, - RsClient *pClient, + Device *pDevice, NvHandle hMemCtx, NvU64 SemaphoreGPUVABase, NvV32 ReleaseValue, @@ -570,12 +564,6 @@ NV_STATUS semaphoreFillGPUVATimestamp NvGpuSemaphore *pSemaphore; NvBool bBcState = gpumgrGetBcEnabledStatus(pGpu); NvBool bFound; - Device *pDevice; - NV_STATUS status; - - status = deviceGetByGpu(pClient, pGpu, NV_TRUE, &pDevice); - if (status != NV_OK) - return status; if (!portSafeMulU64((NvU64) Index, (NvU64) sizeof(NvGpuSemaphore), @@ -587,7 +575,7 @@ NV_STATUS semaphoreFillGPUVATimestamp return NV_ERR_INVALID_ARGUMENT; } - bFound = CliGetDmaMappingInfo(pClient, + bFound = CliGetDmaMappingInfo(RES_GET_CLIENT(pDevice), RES_GET_HANDLE(pDevice), hMemCtx, semaphoreGPUVA, @@ -660,7 +648,7 @@ NV_STATUS semaphoreFillGPUVATimestamp * semaphoreFillGPUVATimestamp. * * @param[in] pGpu OBJGPU pointer - * @param[in] hClient NvU32 client handle + * @param[in] pDevice Device pointer * @param[in] SemaphoreGPUVABase 64b GPU VA base address of semaphore * @param[in] ReleaseValue NvU32 value to write to semaphore upon release * @param[in] Index index of semaphore in semaphore array @@ -670,7 +658,7 @@ NV_STATUS semaphoreFillGPUVATimestamp NV_STATUS semaphoreFillGPUVA ( OBJGPU *pGpu, - RsClient *pClient, + Device *pDevice, NvHandle hMemCtx, NvU64 SemaphoreGPUVABase, NvV32 ReleaseValue, @@ -684,7 +672,7 @@ NV_STATUS semaphoreFillGPUVA tmrGetCurrentTime(pTmr, &Time); return semaphoreFillGPUVATimestamp(pGpu, - pClient, + pDevice, hMemCtx, SemaphoreGPUVABase, ReleaseValue, diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/numa.c b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/numa.c index c35b423d82..260ba63111 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/numa.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/numa.c @@ -167,6 +167,35 @@ static NvBool _pmaCheckFreeFramesToSkipReclaim(PMA *pPma) (pPma->pmaStats.num2mbPages * (_PMA_2MB >> PMA_PAGE_SHIFT) * pPma->numaReclaimSkipThreshold)); } +/*! + * Translate a page returned by kernel to internal PMA page offset. + * @return NV_OK if the translation is successful. + * NV_ERR_INVALID_STATE if the address is out of bound of PMA region + */ +static NV_STATUS +_pmaTranslateKernelPage +( + PMA *pPma, + NvU64 sysPhysAddr, + NvU64 pageSize, + NvU64 *pGpaPhysAddr +) +{ + NV_ASSERT_OR_RETURN(pGpaPhysAddr != NULL, NV_ERR_INVALID_ARGUMENT); + + // Check returned page against online region + if ((sysPhysAddr < pPma->coherentCpuFbBase) || + ((sysPhysAddr + pageSize) > (pPma->coherentCpuFbBase + pPma->coherentCpuFbSize))) + { + return NV_ERR_INVALID_STATE; + } + + *pGpaPhysAddr = sysPhysAddr - pPma->coherentCpuFbBase; + + // Check returned page against internal PMA structures + return pmaCheckRangeAgainstRegionDesc(pPma, *pGpaPhysAddr, pageSize); +} + /*! * @brief Allocate contiguous memory for Numa * @@ -209,8 +238,15 @@ NV_STATUS _pmaNumaAllocateRange // Skip the first page as it is refcounted at allocation. osAllocAcquirePage(sysPhysAddr + (1 << osPageShift), (actualSize >> osPageShift) - 1); - gpaPhysAddr = sysPhysAddr - pPma->coherentCpuFbBase; - NV_ASSERT(gpaPhysAddr < pPma->coherentCpuFbBase); + // GPA needs to be acquired by shifting by the ATS aperture base address + status = _pmaTranslateKernelPage(pPma, sysPhysAddr, actualSize, &gpaPhysAddr); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Alloc from OS invalid for sysPhysAddr = 0x%llx actualSize = 0x%llx!\n", + sysPhysAddr, actualSize); + goto exit; + } + *allocatedCount = 1; if (bScrubOnAlloc) @@ -246,6 +282,7 @@ NV_STATUS _pmaNumaAllocateRange goto allocated; } +exit: portSyncSpinlockAcquire(pPma->pPmaLock); NV_PRINTF(LEVEL_INFO, "Allocate from OS failed for allocation size = %lld!\n", @@ -350,14 +387,19 @@ static NV_STATUS _pmaNumaAllocatePages status = osAllocPagesNode((int)numaNodeId, (NvLength) pageSize, flags, &sysPhysAddr); if (status != NV_OK) { - NV_PRINTF(LEVEL_INFO, "Alloc from OS failed for i= %lld allocationCount = %lld pageSize = %lld!\n", + NV_PRINTF(LEVEL_ERROR, "Alloc from OS failed for i= %lld allocationCount = %lld pageSize = %lld!\n", i, (NvU64) allocationCount, (NvU64) pageSize); break; } // GPA needs to be acquired by shifting by the ATS aperture base address - NV_ASSERT(sysPhysAddr >= pPma->coherentCpuFbBase); - pPages[i] = sysPhysAddr - pPma->coherentCpuFbBase; + status = _pmaTranslateKernelPage(pPma, sysPhysAddr, pageSize, &pPages[i]); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Alloc from OS invalid for i= %lld allocationCount = %lld pageSize = %lld!\n", + i, (NvU64) allocationCount, (NvU64) pageSize); + break; + } // Skip the first page as it is refcounted at allocation. osAllocAcquirePage(sysPhysAddr + (1 << osPageShift), (pageSize >> osPageShift) - 1); @@ -507,7 +549,8 @@ NV_STATUS pmaNumaAllocate if (contigFlag) { - if (((NvU64)allocationCount) * ((NvU64) pageSize) > NV_U32_MAX) + NvU64 contigTotal; + if (!portSafeMulU64(allocationCount, pageSize, &contigTotal) || contigTotal > NV_U32_MAX) { NV_PRINTF(LEVEL_FATAL, "Cannot allocate more than 4GB contiguous memory in one call.\n"); return NV_ERR_INVALID_ARGUMENT; diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.c b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.c index c396583187..2501717126 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.c @@ -537,7 +537,7 @@ pmaRegisterRegion PMA_SCRUB_INITIALIZE); } - status = pmaRegisterBlacklistInfo(pPma, physBase, pBlacklistPageBase, blacklistCount); + status = pmaRegisterBlacklistInfo(pPma, physBase, pBlacklistPageBase, blacklistCount, NV_TRUE); if (status != NV_OK) { pPma->pMapInfo->pmaMapDestroy(pMap); @@ -1963,7 +1963,7 @@ pmaAddToBlacklistTracking { blacklistPages.physOffset = physAddr; blacklistPages.bIsDynamic = NV_TRUE; - status = pmaRegisterBlacklistInfo(pPma, 0, &blacklistPages, 1); + status = pmaRegisterBlacklistInfo(pPma, 0, &blacklistPages, 1, NV_FALSE); } return status; } diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.c b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.c index 7cb7d4d952..bd6fddecf0 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.c @@ -228,6 +228,27 @@ pmaStateCheck(PMA *pPma) return NV_TRUE; } +NV_STATUS +pmaCheckRangeAgainstRegionDesc +( + PMA *pPma, + NvU64 base, + NvU64 size +) +{ + PMA_REGION_DESCRIPTOR *pRegionDesc; + NvU32 regId = findRegionID(pPma, base); + pRegionDesc = pPma->pRegDescriptors[regId]; + + if ((base < pRegionDesc->base) || + ((base + size - 1) > pRegionDesc->limit)) + { + return NV_ERR_INVALID_STATE; + } + + return NV_OK; +} + void pmaSetBlockStateAttribUnderPmaLock ( @@ -252,6 +273,9 @@ pmaSetBlockStateAttribUnderPmaLock numFrames = size >> PMA_PAGE_SHIFT; baseFrame = (base - pPma->pRegDescriptors[regId]->base) >> PMA_PAGE_SHIFT; + // Ensure accessing the frame data would not go out of bound in lower level + NV_ASSERT_OR_RETURN_VOID((base + size - 1) <= pPma->pRegDescriptors[regId]->limit); + for (i = 0; i < numFrames; i++) { pPma->pMapInfo->pmaMapChangeStateAttribEx(pMap, (baseFrame + i), pmaState, pmaStateWriteMask); @@ -1215,7 +1239,8 @@ pmaRegisterBlacklistInfo PMA *pPma, NvU64 physAddrBase, PMA_BLACKLIST_ADDRESS *pBlacklistPageBase, - NvU32 blacklistCount + NvU32 blacklistCount, + NvBool bBlacklistFromInforom ) { NvU32 i; @@ -1260,24 +1285,37 @@ pmaRegisterBlacklistInfo // won't check for ATTRIB_BLACKLIST. So pages need to be blacklisted // directly through the kernel. // - // Use physOffset without 64K alignment, because kernel may use a different - // page size. - // // This is only needed for NUMA systems that auto online NUMA memory. // Other systems (e.g., P9) already do blacklisting in nvidia-persistenced. // if (pPma->bNuma && pPma->bNumaAutoOnline) { - NV_STATUS status; - - NV_PRINTF(LEVEL_INFO, - "NUMA enabled - blacklisting page through kernel at address 0x%llx (GPA) 0x%llx (SPA)\n", - pBlacklistPageBase[blacklistEntryIn].physOffset, - pBlacklistPageBase[blacklistEntryIn].physOffset + pPma->coherentCpuFbBase); - status = osOfflinePageAtAddress(pBlacklistPageBase[blacklistEntryIn].physOffset + pPma->coherentCpuFbBase); - if (status != NV_OK) + // + // Only blacklist pages from inforom (i.e., during heap/PMA init) need + // to be blacklisted with kernel here. The blacklist pages stored in + // inforom need to remain blacklisted persistently across GPU resets - + // kernel won't automatically blacklist these so RM must do it + // explicitly here. + // + // Blacklist pages not from inforom (i.e., from ECC interrupt handling) + // do not need to be blacklisted with kernel. This is because the ECC + // interrupt will automatically trigger kernel itself to blacklist the page. + // + if (bBlacklistFromInforom) { - NV_PRINTF(LEVEL_ERROR, "osOfflinePageAtAddress() failed with status: %d\n", status); + NV_STATUS status; + + // Use physOffset without 64K alignment, because kernel may use a different page size. + NV_PRINTF(LEVEL_INFO, + "NUMA enabled - blacklisting page through kernel at address 0x%llx (GPA) 0x%llx (SPA)\n", + pBlacklistPageBase[blacklistEntryIn].physOffset, + pBlacklistPageBase[blacklistEntryIn].physOffset + pPma->coherentCpuFbBase); + + status = osOfflinePageAtAddress(pBlacklistPageBase[blacklistEntryIn].physOffset + pPma->coherentCpuFbBase); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "osOfflinePageAtAddress() failed with status: %d\n", status); + } } } diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/sem_surf.c b/src/nvidia/src/kernel/gpu/mem_mgr/sem_surf.c index 31d569f308..be0b05467f 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/sem_surf.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/sem_surf.c @@ -903,7 +903,8 @@ semsurfDestruct_IMPL pNextValueListeners = listNext(&pIndexListeners->listeners, pValueListeners); - if (!pValueListeners->pListeners) + if (!pValueListeners->pListeners && + (pValueListeners->newValue == 0)) { listRemove(&pIndexListeners->listeners, pValueListeners); portMemFree(pValueListeners); @@ -1559,7 +1560,8 @@ _semsurfDelWaiter ", value %" NvU64_fmtu ".\n", hClient, hSemaphoreSurf, notificationHandle, index, waitValue); - if (!pValueListeners->pListeners) + if (!pValueListeners->pListeners && + (pValueListeners->newValue == 0)) { listRemove(&pIndexListeners->listeners, pValueListeners); portMemFree(pValueListeners); diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/vaspace_api.c b/src/nvidia/src/kernel/gpu/mem_mgr/vaspace_api.c index a2124a747d..9b96cc81f4 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/vaspace_api.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/vaspace_api.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2012-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2012-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -43,7 +43,7 @@ /* ------------------ static and helper functions prototypes------------------*/ static NvU32 translateAllocFlagsToVASpaceFlags(NvU32 allocFlags, NvU32 *translatedFlags); static NvU32 translatePageSizeToVASpaceFlags(NV_VASPACE_ALLOCATION_PARAMETERS *pNvVASpaceAllocParams); -static NV_STATUS _vaspaceapiManagePageLevelsForSplitVaSpace(OBJGPU *pGpu, NvHandle hClient, NvU32 gpuMask, NvU32 flags, VASPACEAPI_MANAGE_PAGE_LEVELS_ACTION action); +static NV_STATUS _vaspaceapiManagePageLevelsForSplitVaSpace(OBJGPU *pGpu, Device *pDevice, NvU32 gpuMask, NvU32 flags, VASPACEAPI_MANAGE_PAGE_LEVELS_ACTION action); NvBool vaspaceapiCanCopy_IMPL(VaSpaceApi *pResource) @@ -59,14 +59,12 @@ vaspaceapiConstruct_IMPL RS_RES_ALLOC_PARAMS_INTERNAL *pParams ) { - NvHandle hClient = pCallContext->pClient->hClient; RsResourceRef *pResourceRef = pCallContext->pResourceRef; NvHandle hParent = pResourceRef->pParentRef->hResource; NV_VASPACE_ALLOCATION_PARAMETERS *pNvVASpaceAllocParams; NvU32 allocFlags; NvU32 flags = 0; NvU32 gpuMask = 0; - NvU32 gpuMaskInitial = 0; OBJVMM *pVmm = SYS_GET_VMM(SYS_GET_INSTANCE()); OBJVASPACE *pVAS = NULL; NvU64 vasLimit = 0; @@ -76,7 +74,7 @@ vaspaceapiConstruct_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pVaspaceApi); KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); OBJGPUGRP *pGpuGrp = GPU_RES_GET_GPUGRP(pVaspaceApi); - Device *pDevice; + Device *pDevice = GPU_RES_GET_DEVICE(pVaspaceApi); NvBool bLockAcquired = NV_FALSE; MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); @@ -85,31 +83,15 @@ vaspaceapiConstruct_IMPL if (RS_IS_COPY_CTOR(pParams)) { - if (!rmGpuGroupLockIsOwner(pGpu->gpuInstance, GPU_LOCK_GRP_ALL, &gpuMask)) - { - // - // If we hold some GPU locks already then acquiring more GPU locks - // may violate lock ordering and cause dead-lock. To avoid dead-lock in this case, - // attempt to take the locks with a conditional acquire. - // - gpuMaskInitial = rmGpuLocksGetOwnedMask(); - NvU32 lockFlag = (gpuMaskInitial == 0) - ? GPUS_LOCK_FLAGS_NONE - : GPU_LOCK_FLAGS_COND_ACQUIRE; - - NV_ASSERT_OK_OR_RETURN(rmGpuGroupLockAcquire(pGpu->gpuInstance, - GPU_LOCK_GRP_ALL, - lockFlag, - RM_LOCK_MODULES_MEM, - &gpuMask)); - - bLockAcquired = NV_TRUE; - } + NV_ASSERT_OK_OR_RETURN(rmGpuGroupLockAcquire(pGpu->gpuInstance, + GPU_LOCK_GRP_ALL, + GPU_LOCK_FLAGS_SAFE_LOCK_UPGRADE, + RM_LOCK_MODULES_MEM, + &gpuMask)); status = vaspaceapiCopyConstruct_IMPL(pVaspaceApi, pCallContext, pParams); - if (bLockAcquired) - rmGpuGroupLockRelease(gpuMask & (~gpuMaskInitial), GPUS_LOCK_FLAGS_NONE); + rmGpuGroupLockRelease(gpuMask, GPUS_LOCK_FLAGS_NONE); return status; } @@ -124,8 +106,6 @@ vaspaceapiConstruct_IMPL // Translate & validate flags NV_CHECK_OK_OR_RETURN(LEVEL_WARNING, translateAllocFlagsToVASpaceFlags(allocFlags, &flags)); - NV_ASSERT_OK_OR_RETURN(deviceGetByGpu(pCallContext->pClient, pGpu, NV_TRUE, &pDevice)); - // // Make sure this GPU is not already locked by this thread // Ideally this thread shouldn't have locked any GPU in the system but @@ -147,7 +127,7 @@ vaspaceapiConstruct_IMPL gpuMask = gpumgrGetGpuMask(pGpu); } - status = _vaspaceapiManagePageLevelsForSplitVaSpace(pGpu, hClient, gpuMask, flags, VASPACEAPI_MANAGE_PAGE_LEVELS_RESERVE); + status = _vaspaceapiManagePageLevelsForSplitVaSpace(pGpu, pDevice, gpuMask, flags, VASPACEAPI_MANAGE_PAGE_LEVELS_RESERVE); NV_ASSERT_OR_RETURN(status == NV_OK, status); //-------------------------------------------------------------------------------- @@ -195,7 +175,7 @@ vaspaceapiConstruct_IMPL { MIG_INSTANCE_REF ref; NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, &ref), + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, &ref), done); } @@ -334,25 +314,17 @@ vaspaceapiConstruct_IMPL // Get flags for the requested big page size flags |= translatePageSizeToVASpaceFlags(pNvVASpaceAllocParams); - if (0 != originalVaSize) + if (originalVaSize != 0) { - // FLA VASpace can start from any base (!= 0) - if (flags & VASPACE_FLAGS_FLA) - { - vasLimit = originalVaBase + originalVaSize - 1; - if (vasLimit < originalVaBase) - { - NV_PRINTF(LEVEL_ERROR, - "Integer overflow !!! Invalid parameters for vaBase:%llx, vaSize:%llx\n", - originalVaBase, - originalVaSize); - status = NV_ERR_INVALID_ARGUMENT; - NV_ASSERT_OR_GOTO(0, done); - } - } - else + vasLimit = originalVaBase + originalVaSize - 1; + if (vasLimit < originalVaBase) { - vasLimit = originalVaSize - 1; + NV_PRINTF(LEVEL_ERROR, + "Integer overflow !!! Invalid parameters for vaBase:%llx, vaSize:%llx\n", + originalVaBase, + originalVaSize); + status = NV_ERR_INVALID_ARGUMENT; + NV_ASSERT_OR_GOTO(0, done); } } @@ -393,21 +365,21 @@ vaspaceapiConstruct_IMPL NV_PRINTF(LEVEL_INFO, "Created vaspaceapi 0x%x, hParent 0x%x, device 0x%x, client 0x%x, varef" " 0x%p, parentref 0x%p\n", pResourceRef->hResource, hParent, - RES_GET_HANDLE(pDevice), hClient, pResourceRef, + RES_GET_HANDLE(pDevice), RES_GET_CLIENT_HANDLE(pDevice), pResourceRef, pCallContext->pResourceRef->pParentRef); // Return the actual VAS base and size. pNvVASpaceAllocParams->vaBase = vaspaceGetVaStart(pVAS); - pNvVASpaceAllocParams->vaSize = vaspaceGetVaLimit(pVAS) + 1; + pNvVASpaceAllocParams->vaSize = (vaspaceGetVaLimit(pVAS) - pNvVASpaceAllocParams->vaBase) + 1; done: if (status == NV_OK) { - (void)_vaspaceapiManagePageLevelsForSplitVaSpace(pGpu, hClient, gpuMask, flags, VASPACEAPI_MANAGE_PAGE_LEVELS_TRIM); + (void)_vaspaceapiManagePageLevelsForSplitVaSpace(pGpu, pDevice, gpuMask, flags, VASPACEAPI_MANAGE_PAGE_LEVELS_TRIM); } else { - (void)_vaspaceapiManagePageLevelsForSplitVaSpace(pGpu, hClient, gpuMask, flags, VASPACEAPI_MANAGE_PAGE_LEVELS_RELEASE); + (void)_vaspaceapiManagePageLevelsForSplitVaSpace(pGpu, pDevice, gpuMask, flags, VASPACEAPI_MANAGE_PAGE_LEVELS_RELEASE); } if (bLockAcquired) @@ -437,14 +409,10 @@ vaspaceapiCopyConstruct_IMPL NvHandle hParent = pCallContext->pResourceRef->pParentRef->hResource; NvHandle hVASpace = pCallContext->pResourceRef->hResource; OBJVASPACE *pVAS = pSrcVaspaceApi->pVASpace; - Device *pDevice; NvBool bFlaVA = NV_FALSE; NV_ASSERT_OR_RETURN(pVAS, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OK_OR_RETURN(deviceGetByGpu(pCallContext->pClient, pGpu, NV_TRUE, &pDevice)); - - bFlaVA = ((IS_VIRTUAL_WITH_SRIOV(pGpu) && !gpuIsWarBug200577889SriovHeavyEnabled(pGpu)) || IS_GSP_CLIENT(pGpu)) && (vaspaceGetFlags(pVAS) & VASPACE_FLAGS_FLA); @@ -469,9 +437,8 @@ vaspaceapiCopyConstruct_IMPL "Shared vaspaceapi 0x%x, device 0x%x, client 0x%x, as vaspace 0x%x for " "hParent 0x%x device 0x%x client 0x%x varef 0x%p, deviceref 0x%p\n", hVASpaceSrc, pSrcRef->pParentRef->hResource, hClientSrc, - hVASpace, hParent, RES_GET_HANDLE(pDevice), hClient, - pCallContext->pResourceRef, - pCallContext->pResourceRef->pParentRef); + hVASpace, hParent, RES_GET_HANDLE(GPU_RES_GET_DEVICE(pVaspaceApi)), + hClient, pCallContext->pResourceRef, pCallContext->pResourceRef->pParentRef); vaspaceIncRefCnt(pVAS); pVaspaceApi->pVASpace = pVAS; @@ -498,8 +465,8 @@ vaspaceapiDestruct_IMPL(VaSpaceApi *pVaspaceApi) RsClient *pRsClient; CALL_CONTEXT *pCallContext; RS_RES_FREE_PARAMS_INTERNAL *pParams; - Device *pDevice; - NvBool bBar1VA = NV_FALSE; + Device *pDevice = GPU_RES_GET_DEVICE(pVaspaceApi); + NvBool bBar1VA = NV_FALSE; NvBool bFlaVA = NV_FALSE; GPU_RES_SET_THREAD_BC_STATE(pVaspaceApi); @@ -510,17 +477,6 @@ vaspaceapiDestruct_IMPL(VaSpaceApi *pVaspaceApi) hParent = pCallContext->pResourceRef->pParentRef->hResource; hVASpace = pCallContext->pResourceRef->hResource; - status = deviceGetByGpu(pCallContext->pClient, pGpu, NV_TRUE, &pDevice); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_INFO, - "No device found vaspaceapi 0x%x, hParent 0x%x, client 0x%x varef 0x%p," - " deviceref 0x%p\n", hVASpace, hParent, hClient, - pCallContext->pResourceRef, - pCallContext->pResourceRef->pParentRef); - return; - } - if (IS_VIRTUAL_WITH_SRIOV(pGpu) && !gpuIsWarBug200577889SriovHeavyEnabled(pGpu)) { bBar1VA = !!(vaspaceGetFlags(pVaspaceApi->pVASpace) & VASPACE_FLAGS_BAR_BAR1); @@ -535,7 +491,7 @@ vaspaceapiDestruct_IMPL(VaSpaceApi *pVaspaceApi) pGVAS = dynamicCast(pVaspaceApi->pVASpace, OBJGVASPACE); if (pGVAS != NULL) { - (void)_vaspaceapiManagePageLevelsForSplitVaSpace(pGpu, hClient, pVaspaceApi->pVASpace->gpuMask, pGVAS->flags, + (void)_vaspaceapiManagePageLevelsForSplitVaSpace(pGpu, pDevice, pVaspaceApi->pVASpace->gpuMask, pGVAS->flags, VASPACEAPI_MANAGE_PAGE_LEVELS_RELEASE); } @@ -705,7 +661,7 @@ static NvU32 translatePageSizeToVASpaceFlags(NV_VASPACE_ALLOCATION_PARAMETERS *p * return directly when that is not the case. * * @param[in] pGpu OBJGPU pointer - * @param[in] hClient Handle of the client + * @param[in] pDevice Device pointer * @param[in] gpuMask GPU mask * @param[in] flags Flags for the corresponding VA allocation * @param[in] action Requested action to manage the page levels @@ -714,7 +670,7 @@ static NV_STATUS _vaspaceapiManagePageLevelsForSplitVaSpace ( OBJGPU *pGpu, - NvHandle hClient, + Device *pDevice, NvU32 gpuMask, NvU32 flags, VASPACEAPI_MANAGE_PAGE_LEVELS_ACTION action @@ -752,7 +708,7 @@ _vaspaceapiManagePageLevelsForSplitVaSpace // need to thoutoughly test it against SMC sanities before enabling // this function on non Client-RM environment. // - NV_ASSERT_OK_OR_RETURN(memmgrPageLevelPoolsGetInfo(pGpu, pMemoryManager, hClient, &pMemPool)); + NV_ASSERT_OK_OR_RETURN(memmgrPageLevelPoolsGetInfo(pGpu, pMemoryManager, pDevice, &pMemPool)); if (action == VASPACEAPI_MANAGE_PAGE_LEVELS_RESERVE) { diff --git a/src/nvidia/src/kernel/gpu/mem_sys/arch/ampere/kern_mem_sys_ga100.c b/src/nvidia/src/kernel/gpu/mem_sys/arch/ampere/kern_mem_sys_ga100.c index f0564549b2..cbc9919de8 100644 --- a/src/nvidia/src/kernel/gpu/mem_sys/arch/ampere/kern_mem_sys_ga100.c +++ b/src/nvidia/src/kernel/gpu/mem_sys/arch/ampere/kern_mem_sys_ga100.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -110,7 +110,8 @@ kmemsysInitFlushSysmemBuffer_GA100 if (status != NV_OK) return status; - status = memdescAlloc(pKernelMemorySystem->pSysmemFlushBufferMemDesc); + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_139, + pKernelMemorySystem->pSysmemFlushBufferMemDesc); if (status != NV_OK) { diff --git a/src/nvidia/src/kernel/gpu/mem_sys/arch/hopper/kern_mem_sys_gh100.c b/src/nvidia/src/kernel/gpu/mem_sys/arch/hopper/kern_mem_sys_gh100.c index 9bbbd7786b..f87dc9f9b2 100644 --- a/src/nvidia/src/kernel/gpu/mem_sys/arch/hopper/kern_mem_sys_gh100.c +++ b/src/nvidia/src/kernel/gpu/mem_sys/arch/hopper/kern_mem_sys_gh100.c @@ -195,9 +195,7 @@ kmemsysDoCacheOp_GH100 #ifdef DEBUG if (cnt > 1) { - NvU32 intr0 = 0; - intr0 = GPU_REG_RD32(pGpu, NV_XAL_EP_INTR_0); - NV_ASSERT(DRF_VAL(_XAL_EP, _INTR_0, _FB_ACK_TIMEOUT, intr0) != NV_XAL_EP_INTR_0_FB_ACK_TIMEOUT_PENDING); + NV_ASSERT(kmemsysAssertFbAckTimeoutPending_HAL(pGpu, pKernelMemorySystem) == NV_FALSE); } #endif // DEBUG @@ -575,6 +573,27 @@ kmemsysSwizzIdToVmmuSegmentsRange_GH100 return NV_OK; } + +/* + * @brief Function to check if an FB ACK timeout occured. Used only for Debug. + */ +NvBool +kmemsysAssertFbAckTimeoutPending_GH100 +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem +) +{ +#ifdef DEBUG + NvU32 intr0 = 0; + intr0 = GPU_REG_RD32(pGpu, NV_XAL_EP_INTR_0); + return DRF_VAL(_XAL_EP, _INTR_0, _FB_ACK_TIMEOUT, intr0) == NV_XAL_EP_INTR_0_FB_ACK_TIMEOUT_PENDING; +#else + return NV_FALSE; +#endif +} + + /*! * Utility function used to read registers and ignore PRI errors */ diff --git a/src/nvidia/src/kernel/gpu/mem_sys/arch/maxwell/kern_mem_sys_gm107.c b/src/nvidia/src/kernel/gpu/mem_sys/arch/maxwell/kern_mem_sys_gm107.c index d7c8886ae0..c2b6d43de4 100644 --- a/src/nvidia/src/kernel/gpu/mem_sys/arch/maxwell/kern_mem_sys_gm107.c +++ b/src/nvidia/src/kernel/gpu/mem_sys/arch/maxwell/kern_mem_sys_gm107.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2006-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -240,7 +240,8 @@ kmemsysInitFlushSysmemBuffer_GM107 if (status != NV_OK) return status; - status = memdescAlloc(pKernelMemorySystem->pSysmemFlushBufferMemDesc); + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_140, + pKernelMemorySystem->pSysmemFlushBufferMemDesc); // // Check if the memory allocation failed (probably due to no available @@ -300,7 +301,8 @@ kmemsysInitFlushSysmemBuffer_GM107 osDmaSetAddressSize(pGpu->pOsGpuInfo, flushBufferDmaAddressSize); } - status = memdescAlloc(pKernelMemorySystem->pSysmemFlushBufferMemDesc); + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_141, + pKernelMemorySystem->pSysmemFlushBufferMemDesc); // Restore it back to what HW supports if (gpuGetPhysAddrWidth_HAL(pGpu, ADDR_SYSMEM) > flushBufferDmaAddressSize) diff --git a/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys.c b/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys.c index f964bb3833..18903cebe2 100644 --- a/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys.c +++ b/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -138,11 +138,13 @@ NV_STATUS kmemsysStateInitLocked_IMPL pGpu->setProperty(pGpu, PDB_PROP_GPU_ATS_SUPPORTED, NV_TRUE); } - + } + if (IS_GSP_CLIENT(pGpu) || IS_VIRTUAL_WITH_SRIOV(pGpu)) + { // - // PDB_PROP_GPU_C2C_SYSMEM is already set in physical RM but not in - // in Kernel-RM where it is actually consumed. setting PDB_PROP_GPU_C2C_SYSMEM - // in Kernel-RM when the platform is self-hosted and the C2C links are up, which + // PDB_PROP_GPU_C2C_SYSMEM is already set in physical-RM but not in + // in Kernel-RM/Guest-RM where it is actually consumed. setting PDB_PROP_GPU_C2C_SYSMEM + // in Kernel-RM/Guest-RM when the platform is self-hosted and the C2C links are up, which // indicate the C2C is connected to CPU and Physical-RM would have set up the HSHUB // to route sysmem through C2C. // @@ -311,6 +313,7 @@ kmemsysDestruct_IMPL pKernelMemorySystem->pSysmemFlushBufferMemDesc = NULL; portMemSet(pKernelMemorySystem->gpuInstanceMemConfig, 0, sizeof(pKernelMemorySystem->gpuInstanceMemConfig)); + } NV_STATUS @@ -531,6 +534,7 @@ kmemsysGetMIGGPUInstanceMemInfo_IMPL NvU64 vmmuSegmentSize; NvU64 startAddr; NvU64 endAddr; + NvU64 partitionSize; NV_ASSERT_OR_RETURN(pAddrRange != NULL, NV_ERR_INVALID_ARGUMENT); *pAddrRange = NV_RANGE_EMPTY; @@ -556,7 +560,27 @@ kmemsysGetMIGGPUInstanceMemInfo_IMPL NV_ASSERT_OR_RETURN((vmmuSegmentSize != 0), NV_ERR_INVALID_STATE); startAddr = pKernelMemorySystem->gpuInstanceMemConfig[swizzId].startingVmmuSegment * vmmuSegmentSize; - endAddr = startAddr + (pKernelMemorySystem->gpuInstanceMemConfig[swizzId].memSizeInVmmuSegment * vmmuSegmentSize) - 1; + partitionSize = pKernelMemorySystem->gpuInstanceMemConfig[swizzId].memSizeInVmmuSegment * vmmuSegmentSize; + + if (osNumaOnliningEnabled(pGpu->pOsGpuInfo)) + { + NvU64 memblockSize; + NvU64 alignedStartAddr; + + NV_ASSERT_OK_OR_RETURN(osNumaMemblockSize(&memblockSize)); + + // + // Align the partition start address and size to memblock size + // Some FB memory is wasted here if it is not already aligned. + // + alignedStartAddr = NV_ALIGN_UP64(startAddr, memblockSize); + partitionSize -= (alignedStartAddr - startAddr); + startAddr = alignedStartAddr; + partitionSize = NV_ALIGN_DOWN64(partitionSize, memblockSize); + } + + endAddr = startAddr + partitionSize - 1; + *pAddrRange = rangeMake(startAddr, endAddr); return NV_OK; @@ -809,26 +833,29 @@ kmemsysSetupCoherentCpuLink_IMPL // numaOnlineSize = NV_ALIGN_DOWN64(fbSize - totalRsvdBytes, memblockSize); - pKernelMemorySystem->numaOnlineBase = numaOnlineBase; - pKernelMemorySystem->numaOnlineSize = numaOnlineSize; - - NV_PRINTF(LEVEL_INFO, "fbSize: 0x%llx NUMA reserved memory size: 0x%llx online memory size: 0x%llx\n", - fbSize, totalRsvdBytes, numaOnlineSize); - // - // TODO: Bug 1945658: Soldier through on GPU memory add - // failure(which is often possible because of missing auto online - // setting) and instead check for failure on stateLoad. - // Any failure in StateInit results in gpuStateDestroy not getting called. - // kgspUnloadRm_IMPL from gpuStateDestroy also doesn't get called leaving - // GSP in unclean state and requiring GPU reset to recover from that. - // - // kmemsysNumaAddMemory_HAL by itself cannot be called from stateLoad - // because the memory mapping that follows this call site comes from linear - // kernel virtual address when memory is added to the kernel vs the - // VMALLOC_START region when memory is not added. - // - NV_ASSERT_OK(kmemsysNumaAddMemory_HAL(pGpu, pKernelMemorySystem, 0, 0, - numaOnlineSize, &numaNodeId)); + NV_PRINTF(LEVEL_INFO, + "fbSize: 0x%llx NUMA reserved memory size: 0x%llx online memory size: 0x%llx\n", + fbSize, totalRsvdBytes, numaOnlineSize); + if (osNumaOnliningEnabled(pGpu->pOsGpuInfo)) + { + pKernelMemorySystem->numaOnlineBase = numaOnlineBase; + pKernelMemorySystem->numaOnlineSize = numaOnlineSize; + // + // TODO: Bug 1945658: Soldier through on GPU memory add + // failure(which is often possible because of missing auto online + // setting) and instead check for failure on stateLoad. + // Any failure in StateInit results in gpuStateDestroy not getting called. + // kgspUnloadRm_IMPL from gpuStateDestroy also doesn't get called leaving + // GSP in unclean state and requiring GPU reset to recover from that. + // + // kmemsysNumaAddMemory_HAL by itself cannot be called from stateLoad + // because the memory mapping that follows this call site comes from linear + // kernel virtual address when memory is added to the kernel vs the + // VMALLOC_START region when memory is not added. + // + NV_ASSERT_OK(kmemsysNumaAddMemory_HAL(pGpu, pKernelMemorySystem, 0, 0, + numaOnlineSize, &numaNodeId)); + } pGpu->numaNodeId = numaNodeId; NV_ASSERT_OK_OR_RETURN(kbusCreateCoherentCpuMapping_HAL(pGpu, pKernelBus, numaOnlineSize, bFlush)); diff --git a/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys_ctrl.c b/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys_ctrl.c index 4a317db036..35069b98aa 100644 --- a/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys_ctrl.c +++ b/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys_ctrl.c @@ -71,7 +71,7 @@ _fbGetFbInfos(OBJGPU *pGpu, RsClient *pClient, Device *pDevice, NvHandle hObject if (bIsMIGInUse) { bIsClientMIGMonitor = !RMCFG_FEATURE_PLATFORM_GSP && rmclientIsCapableByHandle(pClient->hClient, NV_RM_CAP_SYS_SMC_MONITOR); - bIsClientMIGProfiler = kmigmgrIsClientUsingDeviceProfiling(pGpu, pKernelMIGManager, pClient->hClient); + bIsClientMIGProfiler = kmigmgrIsDeviceUsingDeviceProfiling(pGpu, pKernelMIGManager, pDevice); } // @@ -308,12 +308,21 @@ _fbGetFbInfos(OBJGPU *pGpu, RsClient *pClient, Device *pDevice, NvHandle hObject } else { - const MEMORY_SYSTEM_STATIC_CONFIG *pMemsysConfig = - kmemsysGetStaticConfig(pGpu, pKernelMemorySystem); - NV_ASSERT(0 == NvU64_HI32(pMemoryManager->Ram.fbTotalMemSizeMb << 10)); - data = NvU64_LO32(NV_MIN((pMemoryManager->Ram.fbTotalMemSizeMb << 10), - (pMemoryManager->Ram.fbOverrideSizeMb << 10)) - - pMemsysConfig->fbOverrideStartKb); + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_ZERO_FB)) + { + data = 0; + NV_PRINTF(LEVEL_INFO, + "[zero-FB, No local RAM] TOTAL_RAM_SIZE = 0\n"); + } + else + { + const MEMORY_SYSTEM_STATIC_CONFIG *pMemsysConfig = + kmemsysGetStaticConfig(pGpu, pKernelMemorySystem); + NV_ASSERT(0 == NvU64_HI32(pMemoryManager->Ram.fbTotalMemSizeMb << 10)); + data = NvU64_LO32(NV_MIN((pMemoryManager->Ram.fbTotalMemSizeMb << 10), + (pMemoryManager->Ram.fbOverrideSizeMb << 10)) + - pMemsysConfig->fbOverrideStartKb); + } break; } } @@ -341,10 +350,19 @@ _fbGetFbInfos(OBJGPU *pGpu, RsClient *pClient, Device *pDevice, NvHandle hObject data = heapSizeKb; break; } - NV_ASSERT(0 == NvU64_HI32(pMemoryManager->Ram.fbTotalMemSizeMb << 10)); - data = NvU64_LO32(NV_MIN((pMemoryManager->Ram.fbTotalMemSizeMb << 10), - (pMemoryManager->Ram.fbOverrideSizeMb << 10)) - - pMemsysConfig->fbOverrideStartKb); + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_ZERO_FB)) + { + data = 0; + NV_PRINTF(LEVEL_INFO, + "[zero-FB, No local RAM] RAM_SIZE = 0\n"); + } + else + { + NV_ASSERT(0 == NvU64_HI32(pMemoryManager->Ram.fbTotalMemSizeMb << 10)); + data = NvU64_LO32(NV_MIN((pMemoryManager->Ram.fbTotalMemSizeMb << 10), + (pMemoryManager->Ram.fbOverrideSizeMb << 10)) + - pMemsysConfig->fbOverrideStartKb); + } break; } case NV2080_CTRL_FB_INFO_INDEX_USABLE_RAM_SIZE: @@ -371,10 +389,19 @@ _fbGetFbInfos(OBJGPU *pGpu, RsClient *pClient, Device *pDevice, NvHandle hObject data = heapSizeKb; break; } - NV_ASSERT(0 == NvU64_HI32(pMemoryManager->Ram.fbUsableMemSize >> 10)); - data = NvU64_LO32(NV_MIN((pMemoryManager->Ram.fbUsableMemSize >> 10 ), - (pMemoryManager->Ram.fbOverrideSizeMb << 10)) - - pMemsysConfig->fbOverrideStartKb); + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_ZERO_FB)) + { + data = 0; + NV_PRINTF(LEVEL_INFO, + "[zero-FB, No local RAM] USABLE_RAM_SIZE = 0\n"); + } + else + { + NV_ASSERT(0 == NvU64_HI32(pMemoryManager->Ram.fbUsableMemSize >> 10)); + data = NvU64_LO32(NV_MIN((pMemoryManager->Ram.fbUsableMemSize >> 10 ), + (pMemoryManager->Ram.fbOverrideSizeMb << 10)) + - pMemsysConfig->fbOverrideStartKb); + } break; } case NV2080_CTRL_FB_INFO_INDEX_HEAP_SIZE: @@ -391,6 +418,14 @@ _fbGetFbInfos(OBJGPU *pGpu, RsClient *pClient, Device *pDevice, NvHandle hObject { NvU64 size; + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_ZERO_FB)) + { + data = 0; + NV_PRINTF(LEVEL_INFO, + "[zero-FB, No local RAM HEAP] HEAP_SIZE = 0\n"); + break; + } + heapGetUsableSize(pHeap, &size); NV_ASSERT(NvU64_HI32(size >> 10) == 0); data = NvU64_LO32(size >> 10); @@ -430,8 +465,8 @@ _fbGetFbInfos(OBJGPU *pGpu, RsClient *pClient, Device *pDevice, NvHandle hObject data = NvU64_LO32(pMemsysConfig->fbOverrideStartKb); NV_ASSERT(((NvU64) data << 10ULL) == pMemsysConfig->fbOverrideStartKb); } - else - { + else + { // // Returns start of heap in kbytes. This is zero unless // VGA display memory is reserved. @@ -537,7 +572,6 @@ _fbGetFbInfos(OBJGPU *pGpu, RsClient *pClient, Device *pDevice, NvHandle hObject } else { - memmgrCalcReservedFbSpace(pGpu, pMemoryManager); // heap size in kbytes data = memmgrGetReservedHeapSizeMb_HAL(pGpu, pMemoryManager) << 10; } @@ -785,6 +819,18 @@ _fbGetFbInfos(OBJGPU *pGpu, RsClient *pClient, Device *pDevice, NvHandle hObject } break; } + case NV2080_CTRL_FB_INFO_INDEX_IS_ZERO_FB: + { + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_ZERO_FB)) + { + data = 1; + } + else + { + data = 0; + } + break; + } default: { data = 0; @@ -1283,7 +1329,7 @@ subdeviceCtrlCmdFbFlushGpuCache_IMPL NvBool bWriteback = NV_FALSE; NvBool bInvalidate = NV_FALSE; - LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); // Either WriteBack or Invalidate are required for Cache Ops if (FLD_TEST_DRF(2080, _CTRL_FB_FLUSH_GPU_CACHE_FLAGS, _WRITE_BACK, diff --git a/src/nvidia/src/kernel/gpu/mig_mgr/compute_instance_subscription.c b/src/nvidia/src/kernel/gpu/mig_mgr/compute_instance_subscription.c index fdd869e5c3..cf43fa5145 100644 --- a/src/nvidia/src/kernel/gpu/mig_mgr/compute_instance_subscription.c +++ b/src/nvidia/src/kernel/gpu/mig_mgr/compute_instance_subscription.c @@ -30,9 +30,6 @@ #define NVOC_COMPUTE_INSTANCE_SUBSCRIPTION_H_PRIVATE_ACCESS_ALLOWED -// FIXME XXX -#define NVOC_GPU_INSTANCE_SUBSCRIPTION_H_PRIVATE_ACCESS_ALLOWED - #include "core/core.h" #include "gpu/gpu.h" #include "core/system.h" @@ -79,10 +76,10 @@ cisubscriptionConstruct_IMPL } NV_CHECK_OR_RETURN(LEVEL_SILENT, pUserParams->execPartitionId < KMIGMGR_MAX_COMPUTE_INSTANCES, NV_ERR_INVALID_ARGUMENT); - NV_CHECK_OR_RETURN(LEVEL_SILENT, pGPUInstanceSubscription->pKernelMIGGpuInstance != NULL, NV_ERR_INVALID_STATE); - NV_CHECK_OR_RETURN(LEVEL_SILENT, pGPUInstanceSubscription->pKernelMIGGpuInstance->bValid, NV_ERR_INVALID_STATE); + NV_CHECK_OR_RETURN(LEVEL_SILENT, gisubscriptionGetMIGGPUInstance(pGPUInstanceSubscription) != NULL, NV_ERR_INVALID_STATE); + NV_CHECK_OR_RETURN(LEVEL_SILENT, gisubscriptionGetMIGGPUInstance(pGPUInstanceSubscription)->bValid, NV_ERR_INVALID_STATE); - pMIGComputeInstance = &pGPUInstanceSubscription->pKernelMIGGpuInstance->MIGComputeInstance[pUserParams->execPartitionId]; + pMIGComputeInstance = &gisubscriptionGetMIGGPUInstance(pGPUInstanceSubscription)->MIGComputeInstance[pUserParams->execPartitionId]; NV_CHECK_OR_RETURN(LEVEL_SILENT, pMIGComputeInstance->bValid, NV_ERR_INVALID_ARGUMENT); // diff --git a/src/nvidia/src/kernel/gpu/mig_mgr/gpu_instance_subscription.c b/src/nvidia/src/kernel/gpu/mig_mgr/gpu_instance_subscription.c index 35c4d688c8..85c1140012 100644 --- a/src/nvidia/src/kernel/gpu/mig_mgr/gpu_instance_subscription.c +++ b/src/nvidia/src/kernel/gpu/mig_mgr/gpu_instance_subscription.c @@ -28,10 +28,6 @@ * *****************************************************************************/ -// FIXME XXX -#define NVOC_KERNEL_GRAPHICS_MANAGER_H_PRIVATE_ACCESS_ALLOWED -#define NVOC_COMPUTE_INSTANCE_SUBSCRIPTION_H_PRIVATE_ACCESS_ALLOWED - #define NVOC_GPU_INSTANCE_SUBSCRIPTION_H_PRIVATE_ACCESS_ALLOWED #include "core/core.h" @@ -61,12 +57,14 @@ _gisubscriptionClientSharesVASCrossPartition NvU32 targetedSwizzId ) { - NV_STATUS status = NV_OK; OBJGPU *pGpu = GPU_RES_GET_GPU(pGPUInstanceSubscription); KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + RsClient *pRsClientShare; RsResourceRef *pDeviceRef; Device *pDevice; MIG_INSTANCE_REF shareRef; + RS_ITERATOR it; + NvBool bClientShareHasMatchingInstance = NV_FALSE; NV_ASSERT_OR_RETURN(pGPUInstanceSubscription != NULL, NV_TRUE); @@ -92,12 +90,30 @@ _gisubscriptionClientSharesVASCrossPartition // is subscribed to a different GPU instance than the subscription request, or // if the sharing client isn't subscribed to any GPU instance. // - status = kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, - pDevice->hClientShare, - &shareRef); + NV_ASSERT_OK_OR_RETURN( + serverGetClientUnderLock(&g_resServ, pDevice->hClientShare, &pRsClientShare)); + it = clientRefIter(pRsClientShare, NULL, classId(Device), RS_ITERATE_CHILDREN, NV_TRUE); - return (status != NV_OK) || (shareRef.pKernelMIGGpuInstance->swizzId != targetedSwizzId); + while (clientRefIterNext(pRsClientShare, &it)) + { + pDevice = dynamicCast(it.pResourceRef->pResource, Device); + + if ((pGpu != GPU_RES_GET_GPU(pDevice)) || + (kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, + &shareRef) != NV_OK)) + { + continue; + } + + if (shareRef.pKernelMIGGpuInstance->swizzId == targetedSwizzId) + { + bClientShareHasMatchingInstance = NV_TRUE; + break; + } + } + + return !bClientShareHasMatchingInstance; } NV_STATUS @@ -438,6 +454,16 @@ gisubscriptionCtrlCmdExecPartitionsCreate_IMPL { return NV_ERR_NOT_SUPPORTED; } + + { + NvU32 i; + + for (i = 0; i < pParams->execPartCount; i++) + { + gpumgrCacheCreateComputeInstance(pGpu, pKernelMIGGpuInstance->swizzId, + pParams->execPartId[i]); + } + } } else { @@ -473,6 +499,9 @@ gisubscriptionCtrlCmdExecPartitionsCreate_IMPL NV_ASSERT_OK_OR_RETURN( kmigmgrCreateComputeInstances_HAL(pGpu, pKernelMIGManager, pKernelMIGGpuInstance, NV_FALSE, restore, &pParams->execPartId[i], NV_TRUE)); + + gpumgrCacheCreateComputeInstance(pGpu, pKernelMIGGpuInstance->swizzId, + pParams->execPartId[i]); } } @@ -560,6 +589,8 @@ gisubscriptionCtrlCmdExecPartitionsDelete_IMPL { return NV_ERR_NOT_SUPPORTED; } + gpumgrCacheDestroyComputeInstance(pGpu, pKernelMIGGpuInstance->swizzId, + pParams->execPartId[execPartIdx]); } // @@ -628,7 +659,7 @@ gisubscriptionCtrlCmdExecPartitionsGet_IMPL (void)cisubscriptionGetComputeInstanceSubscription(RES_GET_CLIENT(pGPUInstanceSubscription), RES_GET_HANDLE(pGPUInstanceSubscription), &pComputeInstanceSubscription); if (pComputeInstanceSubscription != NULL) { - pTargetComputeInstanceInfo = pComputeInstanceSubscription->pMIGComputeInstance; + pTargetComputeInstanceInfo = cisubscriptionGetMIGComputeInstance(pComputeInstanceSubscription); } else if (!bEnumerateAll) { @@ -666,7 +697,7 @@ gisubscriptionCtrlCmdExecPartitionsGet_IMPL pOutInfo->nvJpgCount = kmigmgrCountEnginesOfType(&pMIGComputeInstance->resourceAllocation.engines, RM_ENGINE_TYPE_NVJPG); pOutInfo->ofaCount = kmigmgrCountEnginesOfType(&pMIGComputeInstance->resourceAllocation.engines, - RM_ENGINE_TYPE_OFA); + RM_ENGINE_TYPE_OFA(0)); pOutInfo->sharedEngFlag = pMIGComputeInstance->sharedEngFlag; pOutInfo->veidStartOffset = pMIGComputeInstance->resourceAllocation.veidOffset; pOutInfo->smCount = pMIGComputeInstance->resourceAllocation.smCount; @@ -1132,13 +1163,13 @@ gisubscriptionCtrlCmdExecPartitionsGetProfileCapacity_IMPL NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kmigmgrGetComputeProfileFromSize(pGpu, pKernelMIGManager, pParams->computeSize, &profile)); NV_ASSERT_OK_OR_RETURN( - kgrmgrGetMaxVeidsPerGpc(pGpu, pKernelGraphicsManager, &veidStepSize)); + kgrmgrGetVeidStepSize(pGpu, pKernelGraphicsManager, &veidStepSize)); // Create a mask for VEIDs associated with this GPU instance veidMask = DRF_SHIFTMASK64(profile.veidCount - 1:0); GPUInstanceVeidEnd = pKernelMIGGpuInstance->resourceAllocation.veidOffset + pKernelMIGGpuInstance->resourceAllocation.veidCount - 1; GPUInstanceVeidMask = DRF_SHIFTMASK64(GPUInstanceVeidEnd:pKernelMIGGpuInstance->resourceAllocation.veidOffset); - GPUInstanceFreeVeidMask = GPUInstanceVeidMask & ~pKernelGraphicsManager->veidInUseMask; + GPUInstanceFreeVeidMask = GPUInstanceVeidMask &~ (kgrmgrGetVeidInUseMask(pGpu, pKernelGraphicsManager)); GPUInstancePseudoMask = GPUInstanceFreeVeidMask; veidSlotCount = 0; availableSpanCount = 0; diff --git a/src/nvidia/src/kernel/gpu/mig_mgr/kernel_mig_manager.c b/src/nvidia/src/kernel/gpu/mig_mgr/kernel_mig_manager.c index df9a0ce50c..8a16bcae92 100644 --- a/src/nvidia/src/kernel/gpu/mig_mgr/kernel_mig_manager.c +++ b/src/nvidia/src/kernel/gpu/mig_mgr/kernel_mig_manager.c @@ -23,12 +23,6 @@ #define NVOC_KERNEL_MIG_MANAGER_H_PRIVATE_ACCESS_ALLOWED -// FIXME XXX -#define NVOC_KERNEL_GRAPHICS_MANAGER_H_PRIVATE_ACCESS_ALLOWED -#define NVOC_GPU_INSTANCE_SUBSCRIPTION_H_PRIVATE_ACCESS_ALLOWED -#define NVOC_COMPUTE_INSTANCE_SUBSCRIPTION_H_PRIVATE_ACCESS_ALLOWED -#define NVOC_KERNEL_NVLINK_H_PRIVATE_ACCESS_ALLOWED - #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" #include "kernel/gpu/gr/kernel_graphics.h" #include "kernel/gpu/rc/kernel_rc.h" @@ -50,6 +44,7 @@ #include "gpu/mem_mgr/mem_scrub.h" #include "vgpu/rpc.h" #include "virtualization/kernel_vgpu_mgr.h" +#include "virtualization/hypervisor/hypervisor.h" #include "kernel/gpu/gr/kernel_graphics_manager.h" #include "kernel/gpu/gr/kernel_graphics.h" #include "kernel/core/locks.h" @@ -65,6 +60,28 @@ struct KERNEL_MIG_MANAGER_PRIVATE_DATA KERNEL_MIG_MANAGER_STATIC_INFO staticInfo; }; +typedef struct +{ + struct + { + NvBool bValid; + NvU32 flags; + NV_RANGE placement; + } GIs[NV2080_CTRL_GPU_MAX_PARTITIONS]; + struct + { + NvBool bValid; + NvU32 flags; + NvU32 ceCount; + NvU32 nvEncCount; + NvU32 nvDecCount; + NvU32 nvJpgCount; + NvU32 ofaCount; + NvU32 spanStart; + NvU32 GIIdx; + } CIs[NVC637_CTRL_MAX_EXEC_PARTITIONS]; +} MIG_BOOT_CONFIG; + /*! * @brief Function to increment gi/ci refcount */ @@ -226,6 +243,8 @@ kmigmgrCountEnginesOfType_IMPL range = RM_ENGINE_RANGE_NVENC(); else if (RM_ENGINE_TYPE_IS_NVJPEG(rmEngineType)) range = RM_ENGINE_RANGE_NVJPEG(); + else if (RM_ENGINE_TYPE_IS_OFA(rmEngineType)) + range = RM_ENGINE_RANGE_OFA(); bitVectorClrAll(&mask); bitVectorSetRange(&mask, range); @@ -488,9 +507,12 @@ kmigmgrGetLocalEngineMask_IMPL bitVectorSetRange(pLocalEngineMask, range); } - count = kmigmgrCountEnginesOfType(pPhysicalEngineMask, RM_ENGINE_TYPE_OFA); + count = kmigmgrCountEnginesOfType(pPhysicalEngineMask, RM_ENGINE_TYPE_OFA(0)); if (count > 0) - bitVectorSet(pLocalEngineMask, RM_ENGINE_TYPE_OFA); + { + range = rangeMake(RM_ENGINE_TYPE_OFA(0), RM_ENGINE_TYPE_OFA(count - 1)); + bitVectorSetRange(pLocalEngineMask, range); + } } /*! @@ -724,7 +746,7 @@ _kmigmgrHandlePostSchedulingEnableCallback if (!IS_MIG_ENABLED(pGpu) && !IS_VIRTUAL(pGpu) && pGpu->getProperty(pGpu, PDB_PROP_GPU_RESETLESS_MIG_SUPPORTED) && - (gpumgrIsSystemMIGEnabled(gpuGetDBDF(pGpu)) || pKernelMIGManager->bMIGAutoOnlineEnabled)) + (gpumgrIsSystemMIGEnabled(gpuGetDBDF(pGpu)) || pKernelMIGManager->bMIGAutoOnlineEnabled || pKernelMIGManager->bBootConfigSupported)) { RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS params; @@ -759,7 +781,7 @@ _kmigmgrHandlePostSchedulingEnableCallback kmigmgrDetectReducedConfig_HAL(pGpu, pKernelMIGManager); } - NV_ASSERT_OK(kmigmgrRestoreFromPersistence_HAL(pGpu, pKernelMIGManager)); + NV_ASSERT_OK_OR_RETURN(kmigmgrRestoreFromPersistence_HAL(pGpu, pKernelMIGManager)); return NV_OK; } @@ -907,6 +929,8 @@ kmigmgrStateInitLocked_IMPL if (kmigmgrIsDevinitMIGBitSet_HAL(pGpu, pKernelMIGManager)) pKernelMIGManager->bMIGEnabled = NV_TRUE; + gpumgrCacheSetMIGEnabled(pGpu, pKernelMIGManager->bMIGEnabled); + NV_CHECK_OR_RETURN(LEVEL_SILENT, kmigmgrIsMIGSupported(pGpu, pKernelMIGManager), NV_OK); // Setup a callback to initialize state at the very end of GPU post load @@ -947,6 +971,17 @@ kmigmgrInitRegistryOverrides_IMPL KernelMIGManager *pKernelMIGManager ) { + NvU32 data32; + + // Read boot config feature flags regkey + if (osReadRegistryDword(pGpu, NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_FEATURE_FLAGS, &data32) != NV_OK) + { + data32 = DRF_DEF(_REG_STR_RM, _MIG_BOOT_CONFIGURATION_FEATURE_FLAGS, _SUPPORTED, _DEFAULT) | + DRF_DEF(_REG_STR_RM, _MIG_BOOT_CONFIGURATION_FEATURE_FLAGS, _AUTO_UPDATE, _DEFAULT); + } + + pKernelMIGManager->bBootConfigSupported = FLD_TEST_DRF(_REG_STR_RM, _MIG_BOOT_CONFIGURATION_FEATURE_FLAGS, _SUPPORTED, _TRUE, data32); + pKernelMIGManager->bAutoUpdateBootConfig = FLD_TEST_DRF(_REG_STR_RM, _MIG_BOOT_CONFIGURATION_FEATURE_FLAGS, _SUPPORTED, _TRUE, data32); } /** @@ -1486,7 +1521,7 @@ kmigmgrIsEnginePartitionable_IMPL RM_ENGINE_TYPE_IS_NVDEC(rmEngineType) || RM_ENGINE_TYPE_IS_NVENC(rmEngineType) || RM_ENGINE_TYPE_IS_NVJPEG(rmEngineType) || - (rmEngineType == RM_ENGINE_TYPE_OFA)); + RM_ENGINE_TYPE_IS_OFA(rmEngineType)); } /*! @@ -1790,7 +1825,12 @@ kmigmgrRestoreFromPersistence_PF } bTopologyValid = (GIIdx < NV_ARRAY_ELEMENTS(pTopologySave->saveGI)); - NV_CHECK_OR_RETURN(LEVEL_SILENT, bTopologyValid, NV_OK); + if (!bTopologyValid) + { + // The boot config is honored only if no topology was saved previously (e.g. on reboot) + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kmigmgrRestoreFromBootConfig_HAL(pGpu, pKernelMIGManager)); + return NV_OK; + } if (!IS_MIG_ENABLED(pGpu)) { @@ -2112,39 +2152,6 @@ kmigmgrIsDeviceProfilingInUse_IMPL return pKernelMIGManager->bDeviceProfilingInUse; } -/*! - * @brief Function to check if specific client is subscribed to DeviceProfiling - */ -NvBool -kmigmgrIsClientUsingDeviceProfiling_IMPL -( - OBJGPU *pGpu, - KernelMIGManager *pKernelMIGManager, - NvHandle hClient -) -{ - RsClient *pRsClient; - Device *pDevice; - NV_STATUS status; - - NV_CHECK_OR_RETURN(LEVEL_SILENT, IS_MIG_ENABLED(pGpu), NV_FALSE); - - if (!kmigmgrIsDeviceProfilingInUse(pGpu, pKernelMIGManager)) - { - return NV_FALSE; - } - - NV_CHECK_OK_OR_ELSE(status, LEVEL_ERROR, - serverGetClientUnderLock(&g_resServ, hClient, &pRsClient), - return NV_FALSE; ); - - NV_CHECK_OK_OR_ELSE(status, LEVEL_ERROR, - deviceGetByGpu(pRsClient, pGpu, NV_TRUE, &pDevice), - return NV_FALSE; ); - - return kmigmgrIsDeviceUsingDeviceProfiling(pGpu, pKernelMIGManager, pDevice); -} - /*! * @brief Function to check if specific device is subscribed to DeviceProfiling */ @@ -2168,6 +2175,7 @@ kmigmgrIsDeviceUsingDeviceProfiling_IMPL return NV_FALSE; } + NV_ASSERT_OR_RETURN(pDevice != NULL, NV_ERR_INVALID_ARGUMENT); pRsClient = RES_GET_CLIENT(pDevice); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, @@ -2236,6 +2244,7 @@ kmigmgrGetInstanceRefFromDevice_IMPL return NV_ERR_INVALID_STATE; } + NV_ASSERT_OR_RETURN(pDevice != NULL, NV_ERR_INVALID_ARGUMENT); pRsClient = RES_GET_CLIENT(pDevice); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, @@ -2245,19 +2254,19 @@ kmigmgrGetInstanceRefFromDevice_IMPL gisubscriptionGetGPUInstanceSubscription(pRsClient, RES_GET_HANDLE(pSubdevice), &pGPUInstanceSubscription)); - ref.pKernelMIGGpuInstance = pGPUInstanceSubscription->pKernelMIGGpuInstance; + ref.pKernelMIGGpuInstance = gisubscriptionGetMIGGPUInstance(pGPUInstanceSubscription); status = cisubscriptionGetComputeInstanceSubscription(pRsClient, RES_GET_HANDLE(pGPUInstanceSubscription), &pComputeInstanceSubscription); if (status == NV_OK) { - ref = kmigmgrMakeCIReference(pGPUInstanceSubscription->pKernelMIGGpuInstance, - pComputeInstanceSubscription->pMIGComputeInstance); + ref = kmigmgrMakeCIReference(gisubscriptionGetMIGGPUInstance(pGPUInstanceSubscription), + cisubscriptionGetMIGComputeInstance(pComputeInstanceSubscription)); } else { - ref = kmigmgrMakeGIReference(pGPUInstanceSubscription->pKernelMIGGpuInstance); + ref = kmigmgrMakeGIReference(gisubscriptionGetMIGGPUInstance(pGPUInstanceSubscription)); // Quash status, this is optional status = NV_OK; } @@ -2267,38 +2276,6 @@ kmigmgrGetInstanceRefFromDevice_IMPL return status; } -/*! - * @brief Retrieves instance(s) associated with a client, if applicable - */ -NV_STATUS -kmigmgrGetInstanceRefFromClient_IMPL -( - OBJGPU *pGpu, - KernelMIGManager *pKernelMIGManager, - NvHandle hClient, - MIG_INSTANCE_REF *pRef -) -{ - RsClient *pRsClient; - Device *pDevice; - - NV_ASSERT_OR_RETURN(pRef != NULL, NV_ERR_INVALID_ARGUMENT); - *pRef = kmigmgrMakeNoMIGReference(); - - if (!IS_MIG_IN_USE(pGpu)) - { - return NV_ERR_INVALID_STATE; - } - - NV_ASSERT_OK_OR_RETURN(serverGetClientUnderLock(&g_resServ, hClient, &pRsClient)); - - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - deviceGetByGpu(pRsClient, pGpu, NV_TRUE, &pDevice)); - - return kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, - pDevice, pRef); -} - /*! * @brief Retrieves GPU instance heap associated with a device, if applicable */ @@ -2317,6 +2294,7 @@ kmigmgrGetMemoryPartitionHeapFromDevice_IMPL NV_ASSERT_OR_RETURN(IS_MIG_IN_USE(pGpu), NV_ERR_INVALID_STATE); + NV_ASSERT_OR_RETURN(pDevice != NULL, NV_ERR_INVALID_ARGUMENT); hClient = RES_GET_CLIENT_HANDLE(pDevice); rmStatus = kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, &ref); @@ -2401,7 +2379,7 @@ kmigmgrPrintGPUInstanceInfo_IMPL NvU32 jpgCount = kmigmgrCountEnginesOfType(&pKernelMIGGpuInstance->resourceAllocation.engines, RM_ENGINE_TYPE_NVJPG); NvU32 ofaCount = kmigmgrCountEnginesOfType(&pKernelMIGGpuInstance->resourceAllocation.engines, - RM_ENGINE_TYPE_OFA); + RM_ENGINE_TYPE_OFA(0)); #define PADDING_STR "-----------------------------------------------------------------" @@ -2542,29 +2520,6 @@ kmigmgrSetGPUInstanceInfo_IMPL pKernelMIGGpuInstance->pMemoryPartitionHeap = pMemoryPartitionHeap; pKernelMIGGpuInstance->partitionFlag = partitionFlag; - // - // Offloading of VGPU to GSP requires that the memRange in KERNEL_MIG_GPU_INSTANCE - // be populated, as the plugin will query only within GSP for GPU INSTANCE information. - // CPU-RM is the entity which actually calculates and allocates memory, so with - // VGPU offloaded, GSP-RM must be updated with the memRange info. - // - if (IS_GSP_CLIENT(pGpu) && !IS_VIRTUAL(pGpu) && IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)) - { - RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS memParams; - - memParams.swizzId = pKernelMIGGpuInstance->swizzId; - memParams.memAddrRange.lo = pKernelMIGGpuInstance->memRange.lo; - memParams.memAddrRange.hi = pKernelMIGGpuInstance->memRange.hi; - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - pRmApi->Control(pRmApi, - pGpu->hInternalClient, - pGpu->hInternalSubdevice, - NV2080_CTRL_CMD_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE, - &memParams, - sizeof(memParams))); - } - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kmigmgrGetProfileByPartitionFlag(pGpu, pKernelMIGManager, partitionFlag, &pKernelMIGGpuInstance->pProfile)); @@ -2667,7 +2622,7 @@ kmigmgrGetLocalToGlobalEngineType_IMPL if (kmigmgrEngineTypeXlate(&ref.pMIGComputeInstance->resourceAllocation.localEngines, localEngType, &ref.pMIGComputeInstance->resourceAllocation.engines, &localEngType) != NV_OK) { - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_INFO, "Compute instance Local Engine type 0x%x is not allocated to Compute instance\n", localEngType); return NV_ERR_INVALID_ARGUMENT; @@ -2721,7 +2676,7 @@ kmigmgrGetGlobalToLocalEngineType_IMPL if (kmigmgrEngineTypeXlate(&ref.pKernelMIGGpuInstance->resourceAllocation.engines, globalEngType, &ref.pKernelMIGGpuInstance->resourceAllocation.localEngines, &globalEngType) != NV_OK) { - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_INFO, "Global Engine type 0x%x is not allocated to GPU instance\n", globalEngType); return NV_ERR_INVALID_ARGUMENT; @@ -2779,7 +2734,7 @@ kmigmgrFilterEngineList_IMPL if (bMIGInUse) { NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, RES_GET_CLIENT_HANDLE(pSubdevice), &ref)); + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, GPU_RES_GET_DEVICE(pSubdevice), &ref)); } *pEngineCount = 0; @@ -2852,7 +2807,7 @@ kmigmgrFilterEnginePartnerList_IMPL } NV_ASSERT_OK_OR_RETURN( - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, RES_GET_CLIENT_HANDLE(pSubdevice), &ref)); + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, GPU_RES_GET_DEVICE(pSubdevice), &ref)); for (i = 0; i < pPartnerListParams->numPartners; ++i) { @@ -2991,6 +2946,8 @@ kmigmgrSetPartitioningMode_IMPL pKernelMIGManager->bMIGEnabled = (params.smcMode == NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_ENABLED); + gpumgrCacheSetMIGEnabled(pGpu, pKernelMIGManager->bMIGEnabled); + // MIG Mode might not have been enabled yet, so load static info if enabled if (IS_MIG_ENABLED(pGpu)) { @@ -3005,6 +2962,9 @@ kmigmgrSetPartitioningMode_IMPL NV_ASSERT_OK_OR_RETURN(kmemsysPopulateMIGGPUInstanceMemConfig_HAL(pGpu, pKernelMemorySystem)); } + // Trigger RUSD data update when MIG state changes + gpushareddataWriteFinish(pGpu); + if (pKccu) { kccuMigShrBufHandler_HAL(pGpu, pKccu, pKernelMIGManager->bMIGEnabled); @@ -3101,6 +3061,8 @@ kmigmgrDetectReducedConfig_KERNEL const KERNEL_MIG_MANAGER_STATIC_INFO *pStaticInfo = kmigmgrGetStaticInfo(pGpu, pKernelMIGManager); NvU32 i; + NV_ASSERT_OR_RETURN_VOID(pStaticInfo != NULL); + for (i = 0; i < pStaticInfo->pCIProfiles->profileCount; ++i) { // Reduced config A100 does not support 1/8 compute size @@ -3446,7 +3408,6 @@ kmigmgrCreateComputeInstances_VF NvU32 i; NvU64 shadowCTSInUseMask; NvU64 shadowVeidInUseMask; - NvU32 maxVeidsPerGpc; KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); KMIGMGR_CONFIGURE_INSTANCE_REQUEST *pConfigRequestPerCi = NULL; NvBool bIsCTSRequired = kmigmgrIsCTSAlignmentRequired_HAL(pGpu, pKernelMIGManager); @@ -3471,10 +3432,6 @@ kmigmgrCreateComputeInstances_VF portMemSet(pConfigRequestPerCi, 0, sizeof(*pConfigRequestPerCi) * KMIGMGR_MAX_COMPUTE_INSTANCES); - NV_ASSERT_OK_OR_GOTO(status, - kgrmgrGetMaxVeidsPerGpc(pGpu, pKernelGraphicsManager, &maxVeidsPerGpc), - done); - // Check that there's enough open compute instance slots, and count used GPCs freeSlots = 0; inUseGpcCount = 0; @@ -3519,7 +3476,7 @@ kmigmgrCreateComputeInstances_VF bitVectorCopy(&shadowExclusiveEngMask, &pKernelMIGGpuInstance->exclusiveEngMask); bitVectorCopy(&shadowSharedEngMask, &pKernelMIGGpuInstance->sharedEngMask); shadowCTSInUseMask = pKernelMIGGpuInstance->ctsIdsInUseMask; - shadowVeidInUseMask = pKernelGraphicsManager->veidInUseMask; + shadowVeidInUseMask = kgrmgrGetVeidInUseMask(pGpu, pKernelGraphicsManager); for (CIIdx = 0; CIIdx < count; ++CIIdx) { NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE *pCIProfile; @@ -3546,13 +3503,19 @@ kmigmgrCreateComputeInstances_VF spanStart = KMIGMGR_SPAN_OFFSET_INVALID; if (FLD_TEST_REF(NVC637_CTRL_DMA_EXEC_PARTITIONS_CREATE_REQUEST_AT_SPAN, _TRUE, params.inst.request.requestFlags)) { + NvU32 veidStepSize; + + NV_ASSERT_OK_OR_GOTO(status, + kgrmgrGetVeidStepSize(pGpu, pKernelGraphicsManager, &veidStepSize), + done); + // // Select spanStart from spanStart field, else calculate the spanStart using the veid offset passed in. // This is done specifically to accomodate legacy flows which don't have knowledge of the new spanStart field // spanStart = (params.inst.request.pReqComputeInstanceInfo[CIIdx].spanStart != 0) - ? params.inst.request.pReqComputeInstanceInfo[CIIdx].spanStart - : params.inst.request.pReqComputeInstanceInfo[CIIdx].veidStartOffset / maxVeidsPerGpc; + ? params.inst.request.pReqComputeInstanceInfo[CIIdx].spanStart + : params.inst.request.pReqComputeInstanceInfo[CIIdx].veidStartOffset / veidStepSize; } } else @@ -3564,7 +3527,7 @@ kmigmgrCreateComputeInstances_VF pCIProfile = &pConfigRequestPerCi[CIIdx].profile; ctsId = KMIGMGR_CTSID_INVALID; if ((kmigmgrGetComputeProfileFromSmCount(pGpu, pKernelMIGManager, smCount, pCIProfile) == NV_OK) || - (kmigmgrGetComputeProfileFromGpcCount(pGpu, pKernelMIGManager, gpcCount, pCIProfile) == NV_OK)) + (kmigmgrGetComputeProfileFromGpcCount_HAL(pGpu, pKernelMIGManager, gpcCount, pCIProfile) == NV_OK)) { // CTS and Span allocation is done early to help prevent spurious requests if (bIsCTSRequired) @@ -3589,12 +3552,16 @@ kmigmgrCreateComputeInstances_VF } else { + // Don't know how to allocate GfxGpc in VF yet NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, kmigmgrGetFreeCTSId(pGpu, pKernelMIGManager, &ctsId, pKernelMIGGpuInstance->pProfile->validCTSIdMask, + 0x0, shadowCTSInUseMask, - pCIProfile->computeSize), + pCIProfile->computeSize, + NV_FALSE, + NV_FALSE), done); } @@ -3608,7 +3575,6 @@ kmigmgrCreateComputeInstances_VF pCIProfile->computeSize = KMIGMGR_COMPUTE_SIZE_INVALID; pCIProfile->gpcCount = gpcCount; pCIProfile->smCount = gpcCount * (pKernelMIGGpuInstance->pProfile->smCount / pKernelMIGGpuInstance->pProfile->gpcCount); - pCIProfile->veidCount = maxVeidsPerGpc * gpcCount; // Force non-profile requests to go through VEID allocator pConfigRequestPerCi[CIIdx].veidSpanStart = KMIGMGR_SPAN_OFFSET_INVALID; @@ -3758,7 +3724,7 @@ kmigmgrCreateComputeInstances_VF // Set Shared/Exclusive Engine Masks for OFAs restored bitVectorClrAll(&engines); - bitVectorSetRange(&engines, rangeMake(RM_ENGINE_TYPE_OFA, RM_ENGINE_TYPE_OFA)); + bitVectorSetRange(&engines, RM_ENGINE_RANGE_OFA()); bitVectorAnd(&engines, &engines, &pResourceAllocation->engines); if ((pMIGComputeInstance->sharedEngFlag & NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_OFA) != 0x0) bitVectorOr(&shadowSharedEngMask, &shadowSharedEngMask, &engines); @@ -3850,7 +3816,7 @@ kmigmgrCreateComputeInstances_VF kmigmgrAllocateInstanceEngines(&pKernelMIGGpuInstance->resourceAllocation.engines, ((pMIGComputeInstance->sharedEngFlag & NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_OFA) != 0x0), - rangeMake(RM_ENGINE_TYPE_OFA, RM_ENGINE_TYPE_OFA), + RM_ENGINE_RANGE_OFA(), ofaCount, &pResourceAllocation->engines, &shadowExclusiveEngMask, @@ -4153,7 +4119,6 @@ kmigmgrCreateComputeInstances_FWCLIENT RM_ENGINE_TYPE localEngineType; RM_ENGINE_TYPE globalEngineType; NvU32 globalGrIdx; - NvU32 maxVeidsPerGpc; NvU64 shadowVeidInUseMask; NV_ASSERT_OR_RETURN(pKernelMIGGpuInstance != NULL, NV_ERR_INVALID_ARGUMENT); @@ -4179,10 +4144,6 @@ kmigmgrCreateComputeInstances_FWCLIENT portMemSet(pConfigRequestPerCi, 0x0, sizeof(*pConfigRequestPerCi) * KMIGMGR_MAX_COMPUTE_INSTANCES); - NV_ASSERT_OK_OR_GOTO(status, - kgrmgrGetMaxVeidsPerGpc(pGpu, GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu), &maxVeidsPerGpc), - done); - info = params.inst.restore.pComputeInstanceSave->ciInfo; if (kmigmgrIsCTSAlignmentRequired_HAL(pGpu, pKernelMIGManager)) @@ -4251,7 +4212,7 @@ kmigmgrCreateComputeInstances_FWCLIENT pConfigRequestPerCi[0].profile.veidCount = pComputeResourceAllocation->veidCount; pConfigRequestPerCi[0].veidSpanStart = info.spanStart; - shadowVeidInUseMask = pKernelGraphicsManager->veidInUseMask; + shadowVeidInUseMask = kgrmgrGetVeidInUseMask(pGpu, pKernelGraphicsManager); NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, kgrmgrCheckVeidsRequest(pGpu, pKernelGraphicsManager, &shadowVeidInUseMask, @@ -4260,6 +4221,16 @@ kmigmgrCreateComputeInstances_FWCLIENT pKernelMIGGpuInstance), done); + + NV_ASSERT(pKernelMIGGpuInstance->MIGComputeInstance[CIIdx].id == KMIGMGR_COMPUTE_INSTANCE_ID_INVALID); + + pMIGComputeInstance->spanStart = pConfigRequestPerCi[0].veidSpanStart; + + portMemCopy(&pKernelMIGGpuInstance->MIGComputeInstance[CIIdx], + sizeof(pKernelMIGGpuInstance->MIGComputeInstance[CIIdx]), + pMIGComputeInstance, + sizeof(*pMIGComputeInstance)); + // Configure the GR engines for each compute instance status = kmigmgrConfigureGPUInstance(pGpu, pKernelMIGManager, pKernelMIGGpuInstance->swizzId, pConfigRequestPerCi, @@ -4268,6 +4239,7 @@ kmigmgrCreateComputeInstances_FWCLIENT // Do our best to deconfigure the engines we configured so far, then bail if (status != NV_OK) { + portMemSet(&pKernelMIGGpuInstance->MIGComputeInstance[CIIdx], 0x0, sizeof(pKernelMIGGpuInstance->MIGComputeInstance[CIIdx])); portMemSet(pConfigRequestPerCi, 0x0, sizeof(*pConfigRequestPerCi) * KMIGMGR_MAX_COMPUTE_INSTANCES); // Quash status. This is best-effort cleanup (void)kmigmgrConfigureGPUInstance(pGpu, pKernelMIGManager, pKernelMIGGpuInstance->swizzId, @@ -4277,15 +4249,6 @@ kmigmgrCreateComputeInstances_FWCLIENT goto done; } - NV_ASSERT(pKernelMIGGpuInstance->MIGComputeInstance[CIIdx].id == KMIGMGR_COMPUTE_INSTANCE_ID_INVALID); - - pMIGComputeInstance->spanStart = pConfigRequestPerCi[0].veidSpanStart; - - portMemCopy(&pKernelMIGGpuInstance->MIGComputeInstance[CIIdx], - sizeof(pKernelMIGGpuInstance->MIGComputeInstance[CIIdx]), - pMIGComputeInstance, - sizeof(*pMIGComputeInstance)); - // // Register instance with the capability framework only if it explicitly // requested. Otherwise, we rely on the persistent state. @@ -5279,24 +5242,31 @@ kmigmgrPrintSubscribingClients_IMPL { RmClient *pClient = *ppClient; RsClient *pRsClient = staticCast(pClient, RsClient); - NvHandle hClient = pRsClient->hClient; MIG_INSTANCE_REF ref; RS_PRIV_LEVEL privLevel = rmclientGetCachedPrivilege(pClient); + RS_ITERATOR it = clientRefIter(pRsClient, NULL, classId(Device), RS_ITERATE_CHILDREN, NV_TRUE); - NV_STATUS status = kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, - hClient, - &ref); + while (clientRefIterNext(pRsClient, &it)) + { + NV_STATUS status; + Device *pDevice = dynamicCast(it.pResourceRef->pResource, Device); - if (status != NV_OK) - continue; + if (pDevice == NULL) + continue; - if (ref.pKernelMIGGpuInstance->swizzId != swizzId) - continue; + status = kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + pDevice, &ref); + if (status != NV_OK) + continue; + + if (ref.pKernelMIGGpuInstance->swizzId != swizzId) + continue; - (void)privLevel; - NV_PRINTF(LEVEL_INFO, "%s client %x currently subscribed to swizzId %u\n", - (privLevel >= RS_PRIV_LEVEL_KERNEL) ? "Kernel" : "Usermode", - hClient, swizzId); + (void)privLevel; + NV_PRINTF(LEVEL_INFO, "%s client %x device %x currently subscribed to swizzId %u\n", + (privLevel >= RS_PRIV_LEVEL_KERNEL) ? "Kernel" : "Usermode", + pRsClient->hClient, RES_GET_HANDLE(pDevice), swizzId); + } } } @@ -5392,8 +5362,8 @@ kmigmgrSetMIGState_FWCLIENT // Destroy the top level scrubber if it exists // NV_ASSERT_OK_OR_GOTO(rmStatus, - memmgrSaveAndDestroyTopLevelScrubber(pGpu, pMemoryManager), - cleanup_destroyTopLevelScrubber); + memmgrDestroyInternalChannels(pGpu, pMemoryManager), + cleanup_destroyInternalChannels); // // Preexisting channel and memory allocation checks should be done after @@ -5419,7 +5389,7 @@ kmigmgrSetMIGState_FWCLIENT NvU32 linkId; //TODO: Remove below code once a more robust SRT is available to test for this condition - FOR_EACH_INDEX_IN_MASK(32, linkId, pKernelNvlink->enabledLinks) + FOR_EACH_INDEX_IN_MASK(32, linkId, knvlinkGetEnabledLinkMask(pGpu, pKernelNvlink)) { NV2080_CTRL_NVLINK_CORE_CALLBACK_PARAMS params; @@ -5563,9 +5533,9 @@ kmigmgrSetMIGState_FWCLIENT { // Init top level scrubber if it existed before NV_ASSERT_OK_OR_CAPTURE_FIRST_ERROR(rmStatus, - memmgrInitSavedTopLevelScrubber(pGpu, pMemoryManager)); + memmgrInitInternalChannels(pGpu, pMemoryManager)); } -cleanup_destroyTopLevelScrubber: +cleanup_destroyInternalChannels: // Set kmigmgr state to reflect MIG disabled while reconfiguring for NON-MIG pKernelMIGManager->bMIGEnabled = NV_FALSE; @@ -6103,7 +6073,7 @@ subdeviceCtrlCmdGpuGetActivePartitionIds_IMPL ct_assert(NV2080_CTRL_GPU_MAX_PARTITIONS == KMIGMGR_MAX_GPU_INSTANCES); - LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); if ((pKernelMIGManager == NULL) || !pGpu->getProperty(pGpu, PDB_PROP_GPU_MIG_SUPPORTED)) { @@ -6307,8 +6277,6 @@ _kmigmgrProcessGPUInstanceEntry { NV_STATUS status = NV_OK; NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS *pParams = portMemAllocNonPaged(sizeof(*pParams)); - CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); - RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams; RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); NV_CHECK_OR_RETURN(LEVEL_ERROR, pParams != NULL, NV_ERR_NO_MEMORY); @@ -6342,8 +6310,8 @@ _kmigmgrProcessGPUInstanceEntry { NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, pRmApi->Control(pRmApi, - pRmCtrlParams->hClient, - pRmCtrlParams->hObject, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_GPU_INSTANCES, pParams, sizeof(*pParams)), @@ -6376,12 +6344,18 @@ _kmigmgrProcessGPUInstanceEntry { NV_ASSERT_OK_OR_GOTO(status, pRmApi->Control(pRmApi, - pRmCtrlParams->hClient, - pRmCtrlParams->hObject, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_GPU_INSTANCES, pParams, sizeof(*pParams)), cleanup_params); + + gpumgrCacheDestroyGpuInstance(pGpu, pEntry->swizzId); + } + else + { + gpumgrCacheCreateGpuInstance(pGpu, pEntry->swizzId); } // Step 7, 8: If this is the last gpu instance to go, disable MIG @@ -6403,8 +6377,8 @@ _kmigmgrProcessGPUInstanceEntry // Reuse the same RPC information we prepared earlier, but flip the bValid bit pParams->partitionInfo[0].bValid = NV_FALSE; NV_ASSERT_OK(pRmApi->Control(pRmApi, - pRmCtrlParams->hClient, - pRmCtrlParams->hObject, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_GPU_INSTANCES, pParams, sizeof(*pParams))); @@ -6508,10 +6482,10 @@ subdeviceCtrlCmdGpuSetPartitions_IMPL // Invalidate gpu instances which has been created for (j = 0; j < i; j++) { - pParams->partitionInfo[i].bValid = !pParams->partitionInfo[i].bValid; + pParams->partitionInfo[j].bValid = !pParams->partitionInfo[j].bValid; NV_ASSERT_OK( - _kmigmgrProcessGPUInstanceEntry(pGpu, pKernelMIGManager, &pParams->partitionInfo[i])); - pParams->partitionInfo[i].bValid = !pParams->partitionInfo[i].bValid; + _kmigmgrProcessGPUInstanceEntry(pGpu, pKernelMIGManager, &pParams->partitionInfo[j])); + pParams->partitionInfo[j].bValid = !pParams->partitionInfo[j].bValid; } return rmStatus; @@ -6537,7 +6511,7 @@ subdeviceCtrlCmdGpuGetPartitions_IMPL ct_assert(NV2080_CTRL_GPU_MAX_PARTITIONS == KMIGMGR_MAX_GPU_INSTANCES); ct_assert(NV2080_CTRL_GPU_MAX_GPC_PER_SMC == KGRMGR_MAX_GPC); - LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); pRpcParams = portMemAllocNonPaged(sizeof(*pRpcParams)); NV_CHECK_OR_RETURN(LEVEL_INFO, pRpcParams != NULL, NV_ERR_NO_MEMORY); @@ -6601,7 +6575,8 @@ subdeviceCtrlCmdGpuGetPartitions_IMPL } else { - rmStatus = kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, &ref); + rmStatus = kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + GPU_RES_GET_DEVICE(pSubdevice), &ref); if (rmStatus != NV_OK) { // set the valid gpu instance count to "0" and return @@ -6650,9 +6625,10 @@ subdeviceCtrlCmdGpuGetPartitions_IMPL pParams->queryPartitionInfo[i].nvJpgCount = kmigmgrCountEnginesOfType(&pResourceAllocation->engines, RM_ENGINE_TYPE_NVJPG); pParams->queryPartitionInfo[i].nvOfaCount = - kmigmgrCountEnginesOfType(&pResourceAllocation->engines, RM_ENGINE_TYPE_OFA); + kmigmgrCountEnginesOfType(&pResourceAllocation->engines, RM_ENGINE_TYPE_OFA(0)); pParams->queryPartitionInfo[i].memSize = rangeLength(ref.pKernelMIGGpuInstance->memRange); pParams->queryPartitionInfo[i].validCTSIdMask = ref.pKernelMIGGpuInstance->pProfile->validCTSIdMask; + pParams->queryPartitionInfo[i].validGfxCTSIdMask = ref.pKernelMIGGpuInstance->pProfile->validGfxCTSIdMask; pParams->queryPartitionInfo[i].bValid = NV_TRUE; { @@ -6853,7 +6829,7 @@ subdeviceCtrlCmdGpuGetComputeProfiles_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); const KERNEL_MIG_MANAGER_STATIC_INFO *pStaticInfo = kmigmgrGetStaticInfo(pGpu, pKernelMIGManager); - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); NvU32 maxSmCount = NV_U32_MAX; MIG_INSTANCE_REF ref; NvU32 entryCount; @@ -6868,7 +6844,7 @@ subdeviceCtrlCmdGpuGetComputeProfiles_IMPL // is not fatal as we still want to allow compute profiles for entire GPU view // to be queried without a specific GPU instance. // - if (kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hClient, &ref) == NV_OK) + if (kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, &ref) == NV_OK) { maxSmCount = ref.pKernelMIGGpuInstance->pProfile->smCount; } @@ -7093,23 +7069,25 @@ kmigmgrGetComputeProfileFromGpcCount_IMPL NvBool bReducedConfig = kmigmgrIsA100ReducedConfig(pGpu, pKernelMIGManager); NvU32 compSize; NvU32 maxGpc; + NvU32 maxMIG; NvU32 i; NV_ASSERT_OR_RETURN(pProfile != NULL, NV_ERR_INVALID_ARGUMENT); NV_CHECK_OR_RETURN(LEVEL_ERROR, pStaticInfo != NULL, NV_ERR_OBJECT_NOT_FOUND); NV_CHECK_OR_RETURN(LEVEL_WARNING, pStaticInfo->pCIProfiles != NULL, NV_ERR_OBJECT_NOT_FOUND); - maxGpc = pKernelGraphicsManager->legacyKgraphicsStaticInfo.pGrInfo->infoList[NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS].data; + maxMIG = kgrmgrGetLegacyKGraphicsStaticInfo(pGpu, pKernelGraphicsManager)->pGrInfo->infoList[NV2080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES].data; + maxGpc = kgrmgrGetLegacyKGraphicsStaticInfo(pGpu, pKernelGraphicsManager)->pGrInfo->infoList[NV2080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS].data; if (bReducedConfig) maxGpc /= 2; - if (gpcCount <= (maxGpc / 8)) + if ((gpcCount <= (maxGpc / 8)) && ((maxMIG / 8) > 0)) compSize = NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_EIGHTH; - else if (gpcCount <= (maxGpc / 4)) + else if ((gpcCount <= (maxGpc / 4)) && ((maxMIG / 4) > 0)) compSize = NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_QUARTER; - else if (gpcCount <= ((maxGpc / 2) - 1)) + else if ((gpcCount <= ((maxGpc / 2) - 1)) && (((maxMIG / 2) - 1) > 0)) compSize = NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_MINI_HALF; - else if (gpcCount <= (maxGpc / 2)) + else if ((gpcCount <= (maxGpc / 2)) && ((maxMIG / 2) > 0)) compSize = NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_HALF; else compSize = NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_FULL; @@ -7118,11 +7096,16 @@ kmigmgrGetComputeProfileFromGpcCount_IMPL { if (pStaticInfo->pCIProfiles->profiles[i].computeSize == compSize) { + if (pStaticInfo->pCIProfiles->profiles[i].gpcCount != gpcCount) + { + NV_PRINTF(LEVEL_INFO, "GPC count %d doesn't match compute size %d \n", gpcCount, compSize); + } portMemCopy(pProfile, sizeof(*pProfile), &pStaticInfo->pCIProfiles->profiles[i], sizeof(pStaticInfo->pCIProfiles->profiles[i])); return NV_OK; } } + NV_PRINTF(LEVEL_INFO, "Found no Compute Profile for gpcCount=%d\n", gpcCount); return NV_ERR_OBJECT_NOT_FOUND; } @@ -7256,10 +7239,14 @@ kmigmgrComputeProfileSizeToCTSIdRange_IMPL * * @param[IN] pGpu * @param[IN] pMIGManager - * @param[OUT] pCtsId CTS ID to be used if NV_OK returned - * @param[IN] globalValidCtsMask Mask of CTS IDs which could possibly be allocated - * @param[IN] ctsIdsInUseMask Mask of CTS IDs currently in use - * @param[IN] profileSize Profile size to get a CTS ID for + * @param[OUT] pCtsId CTS ID to be used if NV_OK returned + * @param[IN] globalValidCtsMask Mask of CTS IDs which could possibly be allocated + * @param[IN] globalValidGfxCtsMask Mask of Gfx capable CTS IDs which could possibly be allocated. + * Unused if bRestrictWithGfx is NV_FALSE + * @param[IN] ctsIdsInUseMask Mask of CTS IDs currently in use + * @param[IN] profileSize Profile size to get a CTS ID for + * @param[IN] bRestrictWithGfx Whether to restrict the CTS ID chosen with Gfx info + * @param[IN] bGfxRequested Whether Gfx info is requested. Unused if bRestrictWithGfx is NV_FALSE * * @return Returns NV_STATUS * NV_OK @@ -7273,9 +7260,12 @@ kmigmgrGetFreeCTSId_IMPL OBJGPU *pGpu, KernelMIGManager *pKernelMIGManager, NvU32 *pCtsId, - NvU64 globalValidCtsMask, - NvU64 ctsIdsInUseMask, - NvU32 profileSize + NvU64 globalValidCtsMask, + NvU64 globalValidGfxCtsMask, + NvU64 ctsIdsInUseMask, + NvU32 profileSize, + NvBool bRestrictWithGfx, + NvBool bGfxRequested ) { NV_RANGE ctsRange = kmigmgrComputeProfileSizeToCTSIdRange(profileSize); @@ -7328,6 +7318,7 @@ kmigmgrGetFreeCTSId_IMPL FOR_EACH_INDEX_IN_MASK_END; *pCtsId = idealCTSId; + return NV_OK; } @@ -7621,3 +7612,288 @@ kmigmgrIsCTSIdAvailable_IMPL FOR_EACH_INDEX_IN_MASK_END; return !!((ctsIdValidMask & ~invalidMask) & NVBIT64(ctsId)); } + +/*! + * @brief Read MIG boot config from the registry + * + * @param[IN] pGpu + * @param[IN] pKernelMIGManager + */ +static NvBool +_kmigmgrReadBootConfig +( + OBJGPU *pGpu, + KernelMIGManager *pKernelMIGManager, + MIG_BOOT_CONFIG *pBootConfig +) +{ + NvU32 data32; + NvBool bCIAssignmentPresent = NV_FALSE; + + ct_assert(NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_GI__SIZE == NV_ARRAY_ELEMENTS(pBootConfig->GIs)); + ct_assert(NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_CI__SIZE == NV_ARRAY_ELEMENTS(pBootConfig->CIs)); + ct_assert(NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_CI_ASSIGNMENT_GI__SIZE == NV_ARRAY_ELEMENTS(pBootConfig->CIs)); + + // Read GPU instance config regkeys + for (NvU32 i = 0; i < NV_ARRAY_ELEMENTS(pBootConfig->GIs); i++) + { + char regStr[sizeof(NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_GI(0))]; + + nvDbgSnprintf(regStr, sizeof(regStr), NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_GI(%u), i); + if (osReadRegistryDword(pGpu, regStr, &data32) != NV_OK) + { + // Do not break here, so we could later check if there are any holes in the config + continue; + } + + pBootConfig->GIs[i].flags = DRF_VAL(_REG_STR_RM, _MIG_BOOT_CONFIGURATION_GI, _FLAGS, data32); + pBootConfig->GIs[i].placement.lo = DRF_VAL(_REG_STR_RM, _MIG_BOOT_CONFIGURATION_GI, _PLACEMENT_LO, data32); + pBootConfig->GIs[i].placement.hi = DRF_VAL(_REG_STR_RM, _MIG_BOOT_CONFIGURATION_GI, _PLACEMENT_HI, data32); + + if (DRF_VAL(_REG_STR_RM, _MIG_BOOT_CONFIGURATION_GI, _REQ_DEC_JPG_OFA, data32)) + { + pBootConfig->GIs[i].flags |= DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE); + } + + if (!rangeIsEmpty(pBootConfig->GIs[i].placement)) + { + pBootConfig->GIs[i].flags |= DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _PLACE_AT_SPAN, _ENABLE); + } + + NV_PRINTF(LEVEL_INFO, "Found a GI config regkey '%s': flags=0x%x, placementLo=%llu, placementHi=%llu\n", + regStr, pBootConfig->GIs[i].flags, pBootConfig->GIs[i].placement.lo, + pBootConfig->GIs[i].placement.hi); + + // Ensure that the specified flags are valid + if (!kmigmgrIsGPUInstanceCombinationValid_HAL(pGpu, pKernelMIGManager, pBootConfig->GIs[i].flags)) + { + NV_PRINTF(LEVEL_ERROR, "Invalid partition flags 0x%x in %s\n", pBootConfig->GIs[i].flags, regStr); + return NV_FALSE; + } + + pBootConfig->GIs[i].bValid = NV_TRUE; + } + + // Read compute instance assignment regkey + if (osReadRegistryDword(pGpu, NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_CI_ASSIGNMENT, &data32) == NV_OK) + { + NV_PRINTF(LEVEL_INFO, "Found a CI assignment regkey '" NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_CI_ASSIGNMENT "': value=%x", data32); + + for (NvU32 i = 0; i < NV_ARRAY_ELEMENTS(pBootConfig->CIs); i++) + { + pBootConfig->CIs[i].GIIdx = DRF_VAL(_REG_STR_RM, _MIG_BOOT_CONFIGURATION_CI_ASSIGNMENT, _GI(i), data32); + } + + bCIAssignmentPresent = NV_TRUE; + } + + // Read compute instance config regkeys + for (NvU32 i = 0; i < NV_ARRAY_ELEMENTS(pBootConfig->CIs); i++) + { + char regStr[sizeof(NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_CI(0))]; + + nvDbgSnprintf(regStr, sizeof(regStr), NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_CI(%u), i); + if (osReadRegistryDword(pGpu, regStr, &data32) != NV_OK) + { + // If the CI entry is not specified, its assignment should be 0 + if (pBootConfig->CIs[i].GIIdx != 0) + { + NV_PRINTF(LEVEL_ERROR, "CI assignment for GI #%u must be 0\n", i); + return NV_FALSE; + } + + // Do not break here, so we could later check if there are any holes in the config + continue; + } + + // The CI assigment regkey must be present if there are any CIs being specified + if (!bCIAssignmentPresent) + { + NV_PRINTF(LEVEL_ERROR, "Regkey '" NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_CI_ASSIGNMENT "' is missing\n"); + return NV_FALSE; + } + + pBootConfig->CIs[i].flags = DRF_VAL(_REG_STR_RM, _MIG_BOOT_CONFIGURATION_CI, _FLAGS, data32); + pBootConfig->CIs[i].spanStart = DRF_VAL(_REG_STR_RM, _MIG_BOOT_CONFIGURATION_CI, _PLACEMENT_LO, data32); + pBootConfig->CIs[i].ceCount = DRF_VAL(_REG_STR_RM, _MIG_BOOT_CONFIGURATION_CI, _CES, data32); + pBootConfig->CIs[i].nvDecCount = DRF_VAL(_REG_STR_RM, _MIG_BOOT_CONFIGURATION_CI, _DECS, data32); + pBootConfig->CIs[i].nvEncCount = DRF_VAL(_REG_STR_RM, _MIG_BOOT_CONFIGURATION_CI, _ENCS, data32); + pBootConfig->CIs[i].nvJpgCount = DRF_VAL(_REG_STR_RM, _MIG_BOOT_CONFIGURATION_CI, _JPGS, data32); + pBootConfig->CIs[i].ofaCount = DRF_VAL(_REG_STR_RM, _MIG_BOOT_CONFIGURATION_CI, _OFAS, data32); + pBootConfig->CIs[i].bValid = NV_TRUE; + + NV_PRINTF(LEVEL_INFO, "Found a CI config regkey '%s': flags=0x%x, placementLo=%u, CEs=%u, DECs=%u, ENCs=%u, JPGs=%u, OFAs=%u\n", + regStr, pBootConfig->CIs[i].flags, pBootConfig->CIs[i].spanStart, pBootConfig->CIs[i].ceCount, + pBootConfig->CIs[i].nvDecCount, pBootConfig->CIs[i].nvEncCount, pBootConfig->CIs[i].nvJpgCount, + pBootConfig->CIs[i].ofaCount); + } + + // Check that the GPU instances config has no holes + for (NvU32 i = 0; i < NV_ARRAY_ELEMENTS(pBootConfig->GIs) - 1; i++) + { + if (!pBootConfig->GIs[i].bValid && pBootConfig->GIs[i + 1].bValid) + { + NV_PRINTF(LEVEL_ERROR, "Regkey '" NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_GI(%u) "' is missing\n", i); + return NV_FALSE; + } + } + + // Check that the compute instances config has no holes + for (NvU32 i = 0; i < NV_ARRAY_ELEMENTS(pBootConfig->CIs) - 1; i++) + { + if (!pBootConfig->CIs[i].bValid && pBootConfig->CIs[i + 1].bValid) + { + NV_PRINTF(LEVEL_ERROR, "Regkey '" NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_CI(%u) "' is missing\n", i); + return NV_FALSE; + } + } + + return NV_TRUE; +} + +/*! + * @brief Create GPU and compute instances based on the boot config + * + * @param[IN] pGpu + * @param[IN] pKernelMIGManager + */ +NV_STATUS +kmigmgrRestoreFromBootConfig_PF +( + OBJGPU *pGpu, + KernelMIGManager *pKernelMIGManager +) +{ + NV_STATUS status = NV_OK; + NvU32 GIIdx; + NvU32 CIIdx; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + NV2080_CTRL_GPU_SET_PARTITION_INFO partitionInfo[NV2080_CTRL_GPU_MAX_PARTITIONS] = {0}; + MIG_BOOT_CONFIG bootConfig = {0}; + + // Check that boot config is supported + NV_CHECK_OR_RETURN(LEVEL_INFO, pKernelMIGManager->bBootConfigSupported, NV_OK); + + // If MIG isn't enabled, nothing to do + NV_CHECK_OR_RETURN(LEVEL_INFO, IS_MIG_ENABLED(pGpu), NV_OK); + + // Read the boot config from the registry + NV_CHECK_OR_RETURN(LEVEL_INFO, + _kmigmgrReadBootConfig(pGpu, pKernelMIGManager, &bootConfig), + NV_ERR_INVALID_PARAMETER); + + // Create the GPU instances + for (GIIdx = 0; GIIdx < NV_ARRAY_ELEMENTS(bootConfig.GIs); GIIdx++) + { + if (!bootConfig.GIs[GIIdx].bValid) + { + break; + } + + partitionInfo[GIIdx].bValid = NV_TRUE; + partitionInfo[GIIdx].partitionFlag = bootConfig.GIs[GIIdx].flags; + partitionInfo[GIIdx].placement.lo = bootConfig.GIs[GIIdx].placement.lo; + partitionInfo[GIIdx].placement.hi = bootConfig.GIs[GIIdx].placement.hi; + + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + _kmigmgrProcessGPUInstanceEntry(pGpu, pKernelMIGManager, &partitionInfo[GIIdx]), + cleanupGI); + } + + // Create the compute instances + for (CIIdx = 0; CIIdx < NV2080_CTRL_GPU_MAX_PARTITIONS; CIIdx++) + { + KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance = NULL; + NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE computeProfileInfo = {0}; + NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS createParams = {0}; + + if (!bootConfig.CIs[CIIdx].bValid) + { + break; + } + + // Find what compute profile corresponds to the specified partition flags + NV_CHECK_OK_OR_ELSE(status, LEVEL_ERROR, + kmigmgrGetComputeProfileFromSize(pGpu, pKernelMIGManager, bootConfig.CIs[CIIdx].flags, &computeProfileInfo), + NV_PRINTF(LEVEL_ERROR, "Invalid partition flags 0x%x for CI #%u\n", bootConfig.CIs[CIIdx].flags, CIIdx); + goto cleanupCI); + + NV_ASSERT_OK_OR_GOTO(status, + kmigmgrGetGPUInstanceInfo(pGpu, pKernelMIGManager, + partitionInfo[bootConfig.CIs[CIIdx].GIIdx].swizzId, + &pKernelMIGGpuInstance), + cleanupCI); + + createParams.execPartCount = 1; + createParams.flags = DRF_DEF(C637_CTRL, _DMA_EXEC_PARTITIONS_CREATE_REQUEST, _AT_SPAN, _TRUE); + createParams.execPartInfo[0].gpcCount = computeProfileInfo.gpcCount; + createParams.execPartInfo[0].smCount = computeProfileInfo.smCount; + createParams.execPartInfo[0].computeSize = computeProfileInfo.computeSize; + createParams.execPartInfo[0].ceCount = bootConfig.CIs[CIIdx].ceCount; + createParams.execPartInfo[0].nvEncCount = bootConfig.CIs[CIIdx].nvEncCount; + createParams.execPartInfo[0].nvDecCount = bootConfig.CIs[CIIdx].nvDecCount; + createParams.execPartInfo[0].nvJpgCount = bootConfig.CIs[CIIdx].nvJpgCount; + createParams.execPartInfo[0].ofaCount = bootConfig.CIs[CIIdx].ofaCount; + createParams.execPartInfo[0].spanStart = bootConfig.CIs[CIIdx].spanStart; + createParams.execPartInfo[0].sharedEngFlag = NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_CE | + NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_NVDEC | + NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_NVENC | + NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_OFA | + NVC637_CTRL_EXEC_PARTITIONS_SHARED_FLAG_NVJPG; + + NV_ASSERT_OK_OR_GOTO(status, + pRmApi->Control(pRmApi, + pKernelMIGGpuInstance->instanceHandles.hClient, + pKernelMIGGpuInstance->instanceHandles.hSubscription, + NVC637_CTRL_CMD_EXEC_PARTITIONS_CREATE, + &createParams, + sizeof(createParams)), + cleanupCI); + } + + return NV_OK; + +cleanupCI: + // Remove all compute instances on the created GPU instances + for (NvU32 i = 0; i < CIIdx; i++) + { + NvU32 tmpStatus; + KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance = NULL; + NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS getParams = {0}; + NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS deleteParams = {0}; + + NV_ASSERT_OK_OR_ELSE(tmpStatus, + kmigmgrGetGPUInstanceInfo(pGpu, pKernelMIGManager, partitionInfo[i].swizzId, &pKernelMIGGpuInstance), + continue); + + NV_ASSERT_OK_OR_ELSE(tmpStatus, + pRmApi->Control(pRmApi, + pKernelMIGGpuInstance->instanceHandles.hClient, + pKernelMIGGpuInstance->instanceHandles.hSubscription, + NVC637_CTRL_CMD_EXEC_PARTITIONS_GET, + &getParams, + sizeof(getParams)), + continue); + + deleteParams.execPartCount = getParams.execPartCount; + portMemCopy(deleteParams.execPartId, sizeof(deleteParams.execPartId), + getParams.execPartId, sizeof(getParams.execPartId)); + + NV_ASSERT_OK(pRmApi->Control(pRmApi, + pKernelMIGGpuInstance->instanceHandles.hClient, + pKernelMIGGpuInstance->instanceHandles.hSubscription, + NVC637_CTRL_CMD_EXEC_PARTITIONS_DELETE, + &deleteParams, + sizeof(deleteParams))); + } + +cleanupGI: + // Invalidate the created GPU instances + for (NvU32 i = 0; i < GIIdx; i++) + { + partitionInfo[i].bValid = NV_FALSE; + NV_ASSERT_OK(_kmigmgrProcessGPUInstanceEntry(pGpu, pKernelMIGManager, &partitionInfo[i])); + } + + return status; +} diff --git a/src/nvidia/src/kernel/gpu/mmu/arch/ampere/kern_gmmu_ga100.c b/src/nvidia/src/kernel/gpu/mmu/arch/ampere/kern_gmmu_ga100.c index 53ed35d4fc..be80941184 100644 --- a/src/nvidia/src/kernel/gpu/mmu/arch/ampere/kern_gmmu_ga100.c +++ b/src/nvidia/src/kernel/gpu/mmu/arch/ampere/kern_gmmu_ga100.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -169,7 +169,9 @@ kgmmuSetupWarForBug2720120_GA100 kgmmuGetPTEAperture(pKernelGmmu), kgmmuGetPTEAttr(pKernelGmmu), 0)); - NV_ASSERT_OK_OR_GOTO(status, memdescAlloc(pKernelGmmu->pWarSmallPageTable), failed); + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_WAR_PT, + pKernelGmmu->pWarSmallPageTable); + NV_ASSERT_OK_OR_GOTO(status, status, failed); switch (memdescGetAddressSpace(pKernelGmmu->pWarSmallPageTable)) { @@ -225,7 +227,9 @@ kgmmuSetupWarForBug2720120_GA100 kgmmuGetPTEAperture(pKernelGmmu), kgmmuGetPTEAttr(pKernelGmmu), 0), failed); - NV_ASSERT_OK_OR_GOTO(status, memdescAlloc(pKernelGmmu->pWarPageDirectory0), failed); + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_WAR_PD, + pKernelGmmu->pWarPageDirectory0); + NV_ASSERT_OK_OR_GOTO(status, status, failed); entryIndexHi = mmuFmtLevelEntryCount(pPageDir0) - 1; switch (memdescGetAddressSpace(pKernelGmmu->pWarPageDirectory0)) diff --git a/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_gh100.c b/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_gh100.c index bbc05c1db3..8c79e9c0da 100644 --- a/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_gh100.c +++ b/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_gh100.c @@ -272,7 +272,7 @@ kgmmuTranslatePdePcfFromHw_GH100 NvU32 *pPdePcfSw ) { - if (!aperture) + if (aperture == GMMU_APERTURE_INVALID) { switch (pdePcfHw) { @@ -487,7 +487,8 @@ kgmmuFaultBufferAllocSharedMemory_GH100 return status; } - status = memdescAlloc(pMemDesc); + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_131, + pMemDesc); if (status != NV_OK) { goto destroy_memdesc; diff --git a/src/nvidia/src/kernel/gpu/mmu/arch/maxwell/kern_gmmu_gm107.c b/src/nvidia/src/kernel/gpu/mmu/arch/maxwell/kern_gmmu_gm107.c index 7e8a472e3f..b53805218f 100644 --- a/src/nvidia/src/kernel/gpu/mmu/arch/maxwell/kern_gmmu_gm107.c +++ b/src/nvidia/src/kernel/gpu/mmu/arch/maxwell/kern_gmmu_gm107.c @@ -138,7 +138,7 @@ kgmmuInvalidateTlb_GM107 // Not using range-based invalidate. params.regVal = FLD_SET_DRF(_PFB_PRI, _MMU_INVALIDATE, _ALL_VA, _TRUE, params.regVal); - if ((NULL != pRootPageDir) && !pGpu->getProperty(pGpu, PDB_PROP_GPU_SRIOV_HEAVY_FORCE_INVALIDATE_ALL_PDBS_WAR_BUG3896322)) + if (NULL != pRootPageDir) { // Invalidatating only one VAS. params.regVal = FLD_SET_DRF(_PFB_PRI, _MMU_INVALIDATE, _ALL_PDB, _FALSE, params.regVal); diff --git a/src/nvidia/src/kernel/gpu/mmu/bar2_walk.c b/src/nvidia/src/kernel/gpu/mmu/bar2_walk.c index e2c1955acb..26d524d60a 100644 --- a/src/nvidia/src/kernel/gpu/mmu/bar2_walk.c +++ b/src/nvidia/src/kernel/gpu/mmu/bar2_walk.c @@ -611,7 +611,8 @@ _bar2WalkCBLevelAlloc break; case ADDR_SYSMEM: - status = memdescAlloc(pMemDesc); + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_142, + pMemDesc); NV_ASSERT_OR_GOTO(NV_OK == status, cleanup); break; } @@ -700,7 +701,8 @@ _bar2WalkCBLevelAlloc break; case ADDR_SYSMEM: - status = memdescAlloc(pMemDesc); + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_143, + pMemDesc); NV_ASSERT_OR_GOTO(NV_OK == status, cleanup); break; } diff --git a/src/nvidia/src/kernel/gpu/mmu/gmmu_trace.c b/src/nvidia/src/kernel/gpu/mmu/gmmu_trace.c index 19df2a3333..0ee299b913 100644 --- a/src/nvidia/src/kernel/gpu/mmu/gmmu_trace.c +++ b/src/nvidia/src/kernel/gpu/mmu/gmmu_trace.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -179,7 +179,11 @@ _gmmuPrintPa NvU32 peerIndex ) { +#if NV_PRINTF_STRINGS_ALLOWED NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "%s", _decodeAperture[aperture]); +#else + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "%c", _decodeAperture[aperture]); +#endif if (GMMU_APERTURE_PEER == aperture) { NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_INFO, "[%d]", peerIndex); diff --git a/src/nvidia/src/kernel/gpu/mmu/gmmu_walk.c b/src/nvidia/src/kernel/gpu/mmu/gmmu_walk.c index 51196d46a2..b8544c73fd 100644 --- a/src/nvidia/src/kernel/gpu/mmu/gmmu_walk.c +++ b/src/nvidia/src/kernel/gpu/mmu/gmmu_walk.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -26,6 +26,7 @@ #include "mem_mgr/gpu_vaspace.h" #include "gpu/mmu/kern_gmmu.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" +#include "kernel/gpu/fifo/kernel_fifo.h" #include "gpu/mem_mgr/mem_desc.h" #include "nvRmReg.h" // NV_REG_STR_RM_* @@ -335,7 +336,8 @@ _gmmuWalkCBLevelAlloc break; } case ADDR_SYSMEM: - status = memdescAlloc(pMemDescTemp); + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_143, + pMemDescTemp); break; default: NV_ASSERT_OR_GOTO(0, done); @@ -410,10 +412,9 @@ _gmmuWalkCBLevelAlloc mmuFmtLevelVirtAddrHi(pLevelFmt, vaLimit)); #else // NV_PRINTF_STRINGS_ALLOWED NV_PRINTF(LEVEL_INFO, - "[GPU%u]: [Packed: %c] %sPA 0x%llX (0x%X bytes) for VA 0x%llX-0x%llX\n", + "[GPU%u]: [Packed: %c] PA 0x%llX (0x%X bytes) for VA 0x%llX-0x%llX\n", pUserCtx->pGpu->gpuInstance, bPacked ? 'Y' : 'N', - bMirror ? _gmmuUVMMirroringDirString[i] : ' ', memdescGetPhysAddr(pMemDesc[i], AT_GPU, 0), newMemSize, mmuFmtLevelVirtAddrLo(pLevelFmt, vaBase), mmuFmtLevelVirtAddrHi(pLevelFmt, vaLimit)); diff --git a/src/nvidia/src/kernel/gpu/mmu/kern_gmmu.c b/src/nvidia/src/kernel/gpu/mmu/kern_gmmu.c index 72d056826a..06f0c98933 100644 --- a/src/nvidia/src/kernel/gpu/mmu/kern_gmmu.c +++ b/src/nvidia/src/kernel/gpu/mmu/kern_gmmu.c @@ -219,9 +219,6 @@ _kgmmuCreateGlobalVASpace // Allow PTE in SYS constructFlags |= VASPACE_FLAGS_RETRY_PTE_ALLOC_IN_SYS; - - constructFlags |= VASPACE_FLAGS_DEFAULT_PARAMS; - constructFlags |= VASPACE_FLAGS_DEFAULT_SIZE; constructFlags |= DRF_DEF(_VASPACE, _FLAGS, _BIG_PAGE_SIZE, _DEFAULT); pGpuGrp = gpumgrGetGpuGrpFromGpu(pGpu); @@ -1089,7 +1086,8 @@ kgmmuFaultBufferAlloc_IMPL return status; } - status = memdescAlloc(pMemDesc); + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_31, + pMemDesc); if (status != NV_OK) { memdescDestroy(pMemDesc); @@ -1417,7 +1415,8 @@ _kgmmuClientShadowFaultBufferQueueAllocate return status; } - status = memdescAlloc(pQueueMemDesc); + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_32, + pQueueMemDesc); if (status != NV_OK) { memdescDestroy(pQueueMemDesc); @@ -1514,7 +1513,8 @@ _kgmmuClientShadowFaultBufferPagesAllocate return status; } - status = memdescAlloc(pMemDesc); + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_33, + pMemDesc); if (status != NV_OK) { memdescDestroy(pMemDesc); @@ -2059,8 +2059,7 @@ kgmmuInstBlkInit_IMPL if (!pInstBlkParams->bDeferFlush) { - kbusFlush_HAL(pGpu, pKernelBus, BUS_FLUSH_USE_PCIE_READ - | kbusGetFlushAperture(pKernelBus, memdescGetAddressSpace(pInstBlkDesc))); + kbusFlush_HAL(pGpu, pKernelBus, kbusGetFlushAperture(pKernelBus, memdescGetAddressSpace(pInstBlkDesc))); } return NV_OK; @@ -2202,7 +2201,12 @@ kgmmuServiceInterrupt_IMPL } case MC_ENGINE_IDX_NON_REPLAYABLE_FAULT_CPU: { - osQueueMMUFaultHandler(pGpu); + // + // This interrupt vector is used to enqueue the UVM top half so any outstanding Non-Replayable + // faults can get processed by UVM. However, since the GSP notification mechanism is interrupt based + // and the top half of the RM interrupt routine will always call into UVM's top half, it is safe to NOP here + // knowing that UVM handling already gets invoked whenever the RM top half is executed. + // status = 0; break; } diff --git a/src/nvidia/src/kernel/gpu/mmu/uvm_sw.c b/src/nvidia/src/kernel/gpu/mmu/uvm_sw.c index 9522538224..52aca3dca3 100644 --- a/src/nvidia/src/kernel/gpu/mmu/uvm_sw.c +++ b/src/nvidia/src/kernel/gpu/mmu/uvm_sw.c @@ -47,13 +47,6 @@ uvmswConstruct_IMPL RS_RES_ALLOC_PARAMS_INTERNAL *pParams ) { - NvHandle hClient = pCallContext->pClient->hClient; - RmClient *pRmClient = dynamicCast(pCallContext->pClient, RmClient); - RS_PRIV_LEVEL privLevel = pCallContext->secInfo.privLevel; - - if (!(rmclientIsAdmin(pRmClient, privLevel) || hypervisorCheckForObjectAccess(hClient))) - return NV_ERR_INSUFFICIENT_PERMISSIONS; - uvmswInitSwMethodState(pUvmSw); return NV_OK; diff --git a/src/nvidia/src/kernel/gpu/nvdec/kernel_nvdec_engdesc.c b/src/nvidia/src/kernel/gpu/nvdec/kernel_nvdec_engdesc.c index d0e4635cd2..92ea928e8e 100644 --- a/src/nvidia/src/kernel/gpu/nvdec/kernel_nvdec_engdesc.c +++ b/src/nvidia/src/kernel/gpu/nvdec/kernel_nvdec_engdesc.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/nvidia/src/kernel/gpu/nvlink/arch/hopper/kernel_nvlink_gh100.c b/src/nvidia/src/kernel/gpu/nvlink/arch/hopper/kernel_nvlink_gh100.c index 9dfcaa745e..e8e5492e54 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/arch/hopper/kernel_nvlink_gh100.c +++ b/src/nvidia/src/kernel/gpu/nvlink/arch/hopper/kernel_nvlink_gh100.c @@ -342,7 +342,7 @@ knvlinkLogAliDebugMessages_GH100 FOR_EACH_INDEX_IN_MASK(32, i, pKernelNvlink->postRxDetLinkMask) { nvErrorLog_va((void *)pGpu, ALI_TRAINING_FAIL, - "NVLink: Link training failed for link %u", + "NVLink: Link training failed for link %u" "(0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x)", i, nvlinkErrInfoParams->linkErrInfo[i].NVLIPTLnkCtrlLinkStateRequest, @@ -399,15 +399,14 @@ knvlinkIsBandwidthModeOff_GH100 NvU32 knvlinkGetNumLinksToBeReducedPerIoctrl_GH100 ( + OBJGPU *pGpu, KernelNvlink *pKernelNvlink ) { NvU32 numlinks = 0; NvU8 mode; -#if defined(INCLUDE_NVLINK_LIB) - numlinks = pKernelNvlink->pNvlinkDev->numActiveLinksPerIoctrl; -#endif + numlinks = knvlinkGetNumActiveLinksPerIoctrl(pGpu, pKernelNvlink); if (numlinks == 0) goto out; @@ -458,7 +457,8 @@ knvlinkGetEffectivePeerLinkMask_GH100 { NvU32 peerLinkMask, remotePeerLinkMask, effectivePeerLinkMask, peerLinkMaskPerIoctrl; NvU32 gpuInstance, remoteGpuInstance; - NvU32 numLinksPerIoctrl, numIoctrls; + NvU32 numLinksPerIoctrl = 0; + NvU32 numIoctrls = 0; KernelNvlink *pRemoteKernelNvlink; NvU32 numLinksToBeReduced; NvU32 linkMaskToBeReduced; @@ -494,7 +494,7 @@ knvlinkGetEffectivePeerLinkMask_GH100 NV_ASSERT(nvPopCount32(remotePeerLinkMask) == nvPopCount32(peerLinkMask)); // Find out number of active NVLinks between the two GPUs. - numLinksToBeReduced = knvlinkGetNumLinksToBeReducedPerIoctrl_HAL(pKernelNvlink); + numLinksToBeReduced = knvlinkGetNumLinksToBeReducedPerIoctrl_HAL(pGpu, pKernelNvlink); effectivePeerLinkMask = peerLinkMask; if (numLinksToBeReduced == 0) @@ -509,13 +509,9 @@ knvlinkGetEffectivePeerLinkMask_GH100 // ID, always trim peerLinkMask from the perspective of local GPU. // Otherwise, use remote GPU for the same. // -#if defined(INCLUDE_NVLINK_LIB) - numIoctrls = pKernelNvlink->pNvlinkDev->numIoctrls; - numLinksPerIoctrl = pKernelNvlink->pNvlinkDev->numLinksPerIoctrl; -#else - numIoctrls = 0; - numLinksPerIoctrl = 0; -#endif + + numIoctrls = nvPopCount32(pKernelNvlink->ioctrlMask); + numLinksPerIoctrl = knvlinkGetTotalNumLinksPerIoctrl(pGpu, pKernelNvlink); if (pGpu->gpuId < pRemoteGpu->gpuId) { diff --git a/src/nvidia/src/kernel/gpu/nvlink/arch/pascal/kernel_nvlink_gp100.c b/src/nvidia/src/kernel/gpu/nvlink/arch/pascal/kernel_nvlink_gp100.c index adabf13f7f..e16c612120 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/arch/pascal/kernel_nvlink_gp100.c +++ b/src/nvidia/src/kernel/gpu/nvlink/arch/pascal/kernel_nvlink_gp100.c @@ -364,3 +364,28 @@ knvlinkProgramLinkSpeed_GP100 return NV_OK; } + +/*! + * @brief Get the device PCI info and store it in + * nvlink_device_info struct which will be passed to corelib + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelNvlink KernelNvlink pointer + * @param[out] nvlink_device_info Nvlink device info pointer + * + */ +#if defined(INCLUDE_NVLINK_LIB) +void +knvlinkCoreGetDevicePciInfo_GP100 +( + OBJGPU *pGpu, + KernelNvlink *pKernelNvlink, + nvlink_device_info *devInfo +) +{ + devInfo->pciInfo.domain = gpuGetDomain(pGpu); + devInfo->pciInfo.bus = gpuGetBus(pGpu); + devInfo->pciInfo.device = gpuGetDevice(pGpu); + devInfo->pciInfo.function = 0; +} +#endif diff --git a/src/nvidia/src/kernel/gpu/nvlink/common_nvlinkapi.c b/src/nvidia/src/kernel/gpu/nvlink/common_nvlinkapi.c index b543ac9880..eb5e88eb5c 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/common_nvlinkapi.c +++ b/src/nvidia/src/kernel/gpu/nvlink/common_nvlinkapi.c @@ -69,6 +69,7 @@ static void _calculateNvlinkCaps NvU32 bridgedLinks, NvU32 ipVerNvlink, NvBool bMIGNvLinkP2PSupported, + NvBool bNvlinkEnabled, NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS *pParams ) { @@ -179,6 +180,11 @@ static void _calculateNvlinkCaps } } + if (bNvlinkEnabled) + { + RMCTRL_SET_CAP(tempCaps, NV2080_CTRL_NVLINK_CAPS, _VALID); + } + portMemCopy(&pParams->capsTbl, NV2080_CTRL_NVLINK_CAPS_TBL_SIZE, tempCaps, NV2080_CTRL_NVLINK_CAPS_TBL_SIZE); } @@ -241,7 +247,10 @@ nvlinkCtrlCmdBusGetNvlinkCaps // knvlinkFilterBridgeLinks_HAL(pGpu, pKernelNvlink); } - _calculateNvlinkCaps(pGpu, pKernelNvlink->bridgeSensableLinks, pKernelNvlink->bridgedLinks, pKernelNvlink->ipVerNvlink, bMIGNvLinkP2PSupported, pParams); + _calculateNvlinkCaps(pGpu, pKernelNvlink->bridgeSensableLinks, pKernelNvlink->bridgedLinks, + pKernelNvlink->ipVerNvlink, bMIGNvLinkP2PSupported, + pKernelNvlink->getProperty(pNvlink, PDB_PROP_KNVLINK_ENABLED), + pParams); pParams->discoveredLinkMask = knvlinkGetDiscoveredLinkMask(pGpu, pKernelNvlink); pParams->enabledLinkMask = knvlinkGetEnabledLinkMask(pGpu, pKernelNvlink); @@ -659,7 +668,7 @@ subdeviceCtrlCmdBusGetNvlinkStatus_IMPL if (!bMIGNvLinkP2PSupported) { - NV_PRINTF(LEVEL_ERROR, "MIG NVLink P2P is not supported.\n"); + NV_PRINTF(LEVEL_INFO, "MIG NVLink P2P is not supported.\n"); status = NV_OK; return status; } diff --git a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlink.c b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlink.c index a27d378e3f..ca8e4349e9 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlink.c +++ b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlink.c @@ -171,10 +171,11 @@ knvlinkIsP2pLoopbackSupportedPerLink_IMPL // Check the link connected to the same GPU (loopback) if (pKernelNvlink->nvlinkLinks[link].remoteEndInfo.bConnected) { - if ((pKernelNvlink->nvlinkLinks[link].remoteEndInfo.domain == gpuGetDomain(pGpu)) && + if (((pKernelNvlink->nvlinkLinks[link].remoteEndInfo.domain == gpuGetDomain(pGpu)) && (pKernelNvlink->nvlinkLinks[link].remoteEndInfo.bus == gpuGetBus(pGpu)) && (pKernelNvlink->nvlinkLinks[link].remoteEndInfo.device == gpuGetDevice(pGpu)) && - (pKernelNvlink->nvlinkLinks[link].remoteEndInfo.function == 0)) + (pKernelNvlink->nvlinkLinks[link].remoteEndInfo.function == 0)) || + pKernelNvlink->PDB_PROP_KNVLINK_FORCED_LOOPBACK_ON_SWITCH_MODE_ENABLED) { return NV_TRUE; } @@ -225,6 +226,44 @@ knvlinkIsNvlinkP2pSupported_IMPL return NV_FALSE; } +static NvBool +_knvlinkCheckFabricCliqueId +( + OBJGPU *pGpu, + OBJGPU *pPeerGpu +) +{ + NvU32 cliqueId, peerCliqueId; + NV_STATUS status; + + status = gpuFabricProbeGetFabricCliqueId(pGpu->pGpuFabricProbeInfoKernel, + &cliqueId); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "GPU %d failed to get fabric clique Id: 0x%x\n", + gpuGetInstance(pGpu), status); + return NV_FALSE; + } + + status = gpuFabricProbeGetFabricCliqueId(pPeerGpu->pGpuFabricProbeInfoKernel, + &peerCliqueId); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "GPU %d failed to get fabric clique Id 0x%x\n", + gpuGetInstance(pPeerGpu), status); + return NV_FALSE; + } + + if (cliqueId != peerCliqueId) + { + NV_PRINTF(LEVEL_ERROR, "GPU %d and Peer GPU %d cliqueId doesn't match\n", + gpuGetInstance(pGpu), gpuGetInstance(pPeerGpu)); + return NV_FALSE; + } + + return NV_TRUE; +} + /*! * @brief Checks whether necessary the config setup is done to * support P2P over NVSwitch @@ -257,6 +296,14 @@ knvlinkCheckNvswitchP2pConfig_IMPL return NV_TRUE; } + if (gpuFabricProbeIsSupported(pGpu) && gpuFabricProbeIsSupported(pPeerGpu)) + { + if (!_knvlinkCheckFabricCliqueId(pGpu, pPeerGpu)) + { + return NV_FALSE; + } + } + if (knvlinkGetUniqueFabricBaseAddress(pGpu, pKernelNvlink) == NVLINK_INVALID_FABRIC_ADDR) { @@ -318,7 +365,7 @@ knvlinkGetP2pConnectionStatus_IMPL if (pGpu1 == NULL) { - NV_PRINTF(LEVEL_ERROR, "Invalid pPeerGpu.\n"); + NV_PRINTF(LEVEL_INFO, "Invalid pPeerGpu.\n"); return NV_ERR_INVALID_ARGUMENT; } @@ -338,7 +385,7 @@ knvlinkGetP2pConnectionStatus_IMPL if (pKernelNvlink1 == NULL) { - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_INFO, "Input mask contains a GPU on which NVLink is disabled.\n"); return NV_ERR_INVALID_ARGUMENT; @@ -434,14 +481,17 @@ knvlinkGetP2pConnectionStatus_IMPL } // Peers should have the same number of links pointing back at us - NV_ASSERT_OR_RETURN(knvlinkGetNumLinksToPeer(pGpu1, pKernelNvlink1, pGpu0) == - numPeerLinks, NV_ERR_INVALID_STATE); - - NV_ASSERT_OR_RETURN(knvlinkCheckNvswitchP2pConfig(pGpu0, pKernelNvlink0, pGpu1), + NV_CHECK_OR_RETURN(LEVEL_INFO, + (knvlinkGetNumLinksToPeer(pGpu1, pKernelNvlink1, pGpu0) == numPeerLinks), NV_ERR_INVALID_STATE); - NV_ASSERT_OR_RETURN(knvlinkCheckNvswitchP2pConfig(pGpu1, pKernelNvlink1, pGpu0), - NV_ERR_INVALID_STATE); + NV_CHECK_OR_RETURN(LEVEL_INFO, + knvlinkCheckNvswitchP2pConfig(pGpu0, pKernelNvlink0, pGpu1), + NV_ERR_INVALID_STATE); + + NV_CHECK_OR_RETURN(LEVEL_INFO, + knvlinkCheckNvswitchP2pConfig(pGpu1, pKernelNvlink1, pGpu0), + NV_ERR_INVALID_STATE); NV_PRINTF(LEVEL_INFO, "NVLink P2P is supported between GPU%d and GPU%d\n", @@ -677,7 +727,6 @@ knvlinkInbandMsgCallbackDispatcher_IMPL nvlink_inband_msg_header_t *pHeader; NVLINK_INBAND_MSG_CALLBACK *pParams; NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pData = NULL; - OBJOS *pOS = GPU_GET_OS(pGpu); pHeader = (nvlink_inband_msg_header_t *)pMessage; @@ -704,8 +753,8 @@ knvlinkInbandMsgCallbackDispatcher_IMPL pData->dataSize = dataSize; portMemCopy(pData->data, pData->dataSize, pMessage, dataSize); - status = pOS->osQueueWorkItemWithFlags(pGpu, knvlinkInbandMsgCallbackDispatcher_WORKITEM, pData, - pParams->wqItemFlags); + status = osQueueWorkItemWithFlags(pGpu, knvlinkInbandMsgCallbackDispatcher_WORKITEM, pData, + pParams->wqItemFlags); if (status != NV_OK) { portMemFree(pData); @@ -841,7 +890,7 @@ knvlinkGetLinkMaskToPeer_IMPL if (pKernelNvlink1 == NULL) { - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_INFO, "on GPU%d NVLink is disabled.\n", gpuGetInstance(pGpu1)); return 0; diff --git a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelib.c b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelib.c index 104e1e4ed0..992169bf5d 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelib.c +++ b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelib.c @@ -143,8 +143,6 @@ knvlinkCoreAddDevice_IMPL #if defined(INCLUDE_NVLINK_LIB) nvlink_device *dev = NULL; - char *drvName = NULL; - char *devName = NULL; char *devIdx = NULL; // Return if the device is already registered @@ -156,50 +154,54 @@ knvlinkCoreAddDevice_IMPL } // Set the driver name - drvName = portMemAllocNonPaged(NVLINK_DRIVER_NAME_LENGTH); - if (drvName == NULL) + pKernelNvlink->driverName = portMemAllocNonPaged(NVLINK_DRIVER_NAME_LENGTH); + if (pKernelNvlink->driverName == NULL) { return NV_ERR_NO_MEMORY; } - portMemSet((void *)drvName, 0, NVLINK_DRIVER_NAME_LENGTH); - portMemCopy(drvName, sizeof(NVLINK_NVIDIA_DRIVER), NVLINK_NVIDIA_DRIVER, + portMemSet((void *)pKernelNvlink->driverName, 0, NVLINK_DRIVER_NAME_LENGTH); + portMemCopy(pKernelNvlink->driverName, sizeof(NVLINK_NVIDIA_DRIVER), NVLINK_NVIDIA_DRIVER, sizeof(NVLINK_NVIDIA_DRIVER)); // // Set the temporary device name. The actual device name will be updated // after PMU state load completes // - devName = portMemAllocNonPaged(NVLINK_DEVICE_NAME_LENGTH); - if (devName == NULL) + pKernelNvlink->deviceName = portMemAllocNonPaged(NVLINK_DEVICE_NAME_LENGTH); + if (pKernelNvlink->deviceName == NULL) { - status = NV_ERR_NO_MEMORY; - NV_PRINTF(LEVEL_ERROR, "Failed to allocate memory for device name\n"); + portMemFree(pKernelNvlink->driverName); - goto knvlinkCoreAddDevice_exit; + NV_PRINTF(LEVEL_ERROR, "Failed to allocate memory for device name\n"); + return NV_ERR_NO_MEMORY; } - portMemSet((void *)devName, 0, NVLINK_DEVICE_NAME_LENGTH); - portMemCopy(devName, sizeof("GPU"), "GPU", sizeof("GPU")); - devIdx = devName; + portMemSet((void *)pKernelNvlink->deviceName, 0, NVLINK_DEVICE_NAME_LENGTH); + + portMemCopy(pKernelNvlink->deviceName, sizeof("GPU"), "GPU", sizeof("GPU")); + devIdx = pKernelNvlink->deviceName; while (*devIdx != '\0') devIdx++; knvlinkUtoa((NvU8 *)devIdx, - NVLINK_DEVICE_NAME_LENGTH - (devIdx - devName), + NVLINK_DEVICE_NAME_LENGTH - (devIdx - pKernelNvlink->deviceName), gpuGetInstance(pGpu)); + // Allocate memory for the nvlink_device struct dev = portMemAllocNonPaged(sizeof(nvlink_device)); if (dev == NULL) { - status = NV_ERR_NO_MEMORY; + portMemFree(pKernelNvlink->driverName); + + portMemFree(pKernelNvlink->deviceName); + NV_PRINTF(LEVEL_ERROR, "Failed to create nvlink_device struct for GPU\n"); - - goto knvlinkCoreAddDevice_exit; + return NV_ERR_NO_MEMORY; } portMemSet((void *)dev, 0, sizeof(nvlink_device)); // Initialize values for the nvlink_device struct - dev->driverName = drvName; - dev->deviceName = devName; + dev->driverName = pKernelNvlink->driverName; + dev->deviceName = pKernelNvlink->deviceName; dev->type = NVLINK_DEVICE_TYPE_GPU; dev->pciInfo.domain = gpuGetDomain(pGpu); dev->pciInfo.bus = gpuGetBus(pGpu); @@ -231,9 +233,9 @@ knvlinkCoreAddDevice_IMPL knvlinkCoreAddDevice_exit: - portMemFree(drvName); + portMemFree(pKernelNvlink->driverName); - portMemFree(devName); + portMemFree(pKernelNvlink->deviceName); portMemFree(dev); @@ -265,6 +267,7 @@ knvlinkCoreUpdateDeviceUUID_IMPL char *devIdx = NULL; NvU32 flags = 0; NvU32 gidStrLen; + nvlink_device_info devInfo; if (pKernelNvlink->pNvlinkDev) { @@ -280,7 +283,7 @@ knvlinkCoreUpdateDeviceUUID_IMPL flags = FLD_SET_DRF_NUM(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _FORMAT, NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT_BINARY, flags); - if (!pKernelNvlink->pNvlinkDev->uuid) + if (!pGpu->gpuUuid.isInitialized) { status = gpuGetGidInfo(pGpu, &pGidString, &gidStrLen, flags); if (status != NV_OK) @@ -289,26 +292,42 @@ knvlinkCoreUpdateDeviceUUID_IMPL return status; } - pKernelNvlink->pNvlinkDev->uuid = (NvU8 *)pGidString; _knvlinkUpdateRemoteEndUuidInfo(pGpu, pKernelNvlink); - } - // PMU state load has completed. Update the device name - portMemSet((void *)pKernelNvlink->pNvlinkDev->deviceName, 0, NVLINK_DEVICE_NAME_LENGTH); + // + // PMU state load has completed. Update the device name in RM and then in Core library + // + + portMemSet((void *)pKernelNvlink->deviceName, 0, NVLINK_DEVICE_NAME_LENGTH); gpuGetNameString(pGpu, NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_ASCII, - pKernelNvlink->pNvlinkDev->deviceName); + pKernelNvlink->deviceName); - devIdx = pKernelNvlink->pNvlinkDev->deviceName; + devIdx = pKernelNvlink->deviceName; while (*devIdx != '\0') devIdx++; - NV_ASSERT((devIdx - pKernelNvlink->pNvlinkDev->deviceName) < NVLINK_DEVICE_NAME_LENGTH); + NV_ASSERT((devIdx - pKernelNvlink->deviceName) < NVLINK_DEVICE_NAME_LENGTH); knvlinkUtoa((NvU8 *)devIdx, - NVLINK_DEVICE_NAME_LENGTH - (devIdx - pKernelNvlink->pNvlinkDev->deviceName), + NVLINK_DEVICE_NAME_LENGTH - (devIdx - pKernelNvlink->deviceName), gpuGetInstance(pGpu)); + + // + // Any Core library Data structure should be updated only within a Core Library function + // after aquiring the appropriate locks. Hence the UUID and deviceName are updated + // as part of nvlink_lib_update_uuid_and_device_name. + // To identify the device in Core Library we pass its DBDF values. + // + + knvlinkCoreGetDevicePciInfo_HAL(pGpu, pKernelNvlink, &devInfo); + + status = nvlink_lib_update_uuid_and_device_name(&devInfo, pGidString, pKernelNvlink->deviceName); + + // Freeing pGidString here as it is malloc'd as part of gpuGetGidInfo_IMPL + if (pGidString != NULL) + portMemFree(pGidString); } #endif @@ -526,20 +545,18 @@ knvlinkCoreRemoveDevice_IMPL { nvlink_device *dev = pKernelNvlink->pNvlinkDev; nvlink_lib_unregister_device(dev); - - portMemFree((NvU8 *)dev->driverName); - portMemFree((NvU8 *)dev->deviceName); - - if (dev->uuid) - { - portMemFree((NvU8 *)dev->uuid); - } portMemFree(dev); } // Update the RM cache of the core lib device pKernelNvlink->pNvlinkDev = NULL; + if (pKernelNvlink->driverName) + portMemFree(pKernelNvlink->driverName); + + if (pKernelNvlink->deviceName) + portMemFree(pKernelNvlink->deviceName); + #endif return NV_OK; diff --git a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibcallback.c b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibcallback.c index 9d6be7d1b1..262a02ae33 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibcallback.c +++ b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibcallback.c @@ -440,7 +440,6 @@ knvlinkCoreQueueLinkChangeCallback KNVLINK_RM_LINK *pNvlinkLink; OBJGPU *pGpu = NULL; - OBJOS *pOS = NULL; NV_STATUS status = NV_OK; void *pWorkItemData; @@ -455,8 +454,6 @@ knvlinkCoreQueueLinkChangeCallback // The master should be marked as such NV_ASSERT_OR_RETURN(link_change->master->master, NV_ERR_INVALID_STATE); - pOS = GPU_GET_OS(pGpu); - pWorkItemData = portMemAllocNonPaged(sizeof(nvlink_link_change *)); NV_ASSERT_OR_RETURN(pWorkItemData != NULL, NVL_NO_MEM); @@ -466,8 +463,8 @@ knvlinkCoreQueueLinkChangeCallback // This function will free the argument if it succeeds, hence the need for // the work item data wrapper. // - status = pOS->osQueueWorkItem(pGpu, _knvlinkCorePassiveLinkChangeCallback, - pWorkItemData); + status = osQueueWorkItem(pGpu, _knvlinkCorePassiveLinkChangeCallback, + pWorkItemData); if (status != NV_OK) { portMemFree(pWorkItemData); diff --git a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibtrain.c b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibtrain.c index b23af7e960..611fe5cbaa 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibtrain.c +++ b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibtrain.c @@ -1716,12 +1716,12 @@ _knvlinkActivateDiscoveredP2pConn // Set the PCI information for remote end pKernelNvlink1->nvlinkLinks[remoteLinkId].remoteEndInfo.bConnected = NV_TRUE; - pKernelNvlink1->nvlinkLinks[remoteLinkId].remoteEndInfo.domain = pKernelNvlink0->pNvlinkDev->pciInfo.domain; - pKernelNvlink1->nvlinkLinks[remoteLinkId].remoteEndInfo.bus = pKernelNvlink0->pNvlinkDev->pciInfo.bus; - pKernelNvlink1->nvlinkLinks[remoteLinkId].remoteEndInfo.device = pKernelNvlink0->pNvlinkDev->pciInfo.device; - pKernelNvlink1->nvlinkLinks[remoteLinkId].remoteEndInfo.function = pKernelNvlink0->pNvlinkDev->pciInfo.function; - pKernelNvlink1->nvlinkLinks[remoteLinkId].remoteEndInfo.pciDeviceId = pKernelNvlink0->pNvlinkDev->pciInfo.pciDeviceId; - pKernelNvlink1->nvlinkLinks[remoteLinkId].remoteEndInfo.deviceType = pKernelNvlink0->pNvlinkDev->type; + pKernelNvlink1->nvlinkLinks[remoteLinkId].remoteEndInfo.domain = gpuGetDomain(pGpu0); + pKernelNvlink1->nvlinkLinks[remoteLinkId].remoteEndInfo.bus = gpuGetBus(pGpu0); + pKernelNvlink1->nvlinkLinks[remoteLinkId].remoteEndInfo.device = gpuGetDevice(pGpu0); + pKernelNvlink1->nvlinkLinks[remoteLinkId].remoteEndInfo.function = 0; + pKernelNvlink1->nvlinkLinks[remoteLinkId].remoteEndInfo.pciDeviceId = pGpu->idInfo.PCIDeviceID; + pKernelNvlink1->nvlinkLinks[remoteLinkId].remoteEndInfo.deviceType = NVLINK_DEVICE_TYPE_GPU; pKernelNvlink1->nvlinkLinks[remoteLinkId].remoteEndInfo.chipSid = pKernelNvlink0->nvlinkLinks[linkId].core_link->localSid; pKernelNvlink1->nvlinkLinks[remoteLinkId].remoteEndInfo.linkNumber = linkId; diff --git a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkoverrides.c b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkoverrides.c index ca243face2..f8fce7c060 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkoverrides.c +++ b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkoverrides.c @@ -263,5 +263,15 @@ knvlinkApplyRegkeyOverrides_IMPL pKernelNvlink->forcedSysmemDeviceType = NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_EBRIDGE; } + if (NV_OK == osReadRegistryDword(pGpu, + NV_REG_STR_RM_NVLINK_FORCED_LOOPBACK_ON_SWITCH, ®data)) + { + if (FLD_TEST_DRF(_REG_STR_RM, _NVLINK_FORCED_LOOPBACK_ON_SWITCH, _MODE, _ENABLED, regdata)) + { + pKernelNvlink->setProperty(pGpu, PDB_PROP_KNVLINK_FORCED_LOOPBACK_ON_SWITCH_MODE_ENABLED, NV_TRUE); + NV_PRINTF(LEVEL_INFO, + "Forced Loopback on switch is enabled\n"); + } + } return NV_OK; } diff --git a/src/nvidia/src/kernel/gpu/ofa/kernel_ofa_engdesc.c b/src/nvidia/src/kernel/gpu/ofa/kernel_ofa_engdesc.c new file mode 100644 index 0000000000..8a2cd08375 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/ofa/kernel_ofa_engdesc.c @@ -0,0 +1,110 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "os/os.h" +#include "kernel/gpu/mig_mgr/kernel_mig_manager.h" +#include "kernel/gpu/fifo/kernel_channel.h" +#include "kernel/gpu/ofa/kernel_ofa_ctx.h" +#include "kernel/gpu/device/device.h" + +#include "class/clb8fa.h" // NVB8FA_VIDEO_OFA +#include "class/clc7fa.h" // NVC7FA_VIDEO_OFA +#include "class/clc6fa.h" // NVC6FA_VIDEO_OFA +#include "class/clc9fa.h" // NVC9FA_VIDEO_OFA + +/* + * This function returns an engine descriptor corresponding to the class + * and engine instance passed in. + * + * @params[in] externalClassId Id of class being allocated + * @params[in] pAllocParams void pointer containing creation parameters. + * + * @returns + * ENG_INVALID, for unknown engine. Returns the right engine descriptor otherwise. + */ +ENGDESCRIPTOR +ofaGetEngineDescFromAllocParams +( + OBJGPU *pGpu, + NvU32 externalClassId, + void *pAllocParams +) +{ + CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + NvU32 engineInstance = 0; + NV_OFA_ALLOCATION_PARAMETERS *pOfaAllocParams = pAllocParams; + + NV_ASSERT_OR_RETURN((pOfaAllocParams != NULL), ENG_INVALID); + + if (pOfaAllocParams->size != sizeof(NV_OFA_ALLOCATION_PARAMETERS)) + { + NV_PRINTF(LEVEL_ERROR, "createParams size mismatch (rm = 0x%x / client = 0x%x)\n", + (NvU32) sizeof(NV_OFA_ALLOCATION_PARAMETERS), + pOfaAllocParams->size); + DBG_BREAKPOINT(); + return ENG_INVALID; + } + + switch (externalClassId) + { + case NVB8FA_VIDEO_OFA: + case NVC6FA_VIDEO_OFA: + case NVC7FA_VIDEO_OFA: + case NVC9FA_VIDEO_OFA: + engineInstance = 0; + break; + engineInstance = pOfaAllocParams->engineInstance; + break; + default: + return ENG_INVALID; + } + + if (IS_MIG_IN_USE(pGpu)) + { + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + MIG_INSTANCE_REF ref; + RM_ENGINE_TYPE rmEngineType; + RsResourceRef *pDeviceRef = NULL; + + NV_ASSERT_OK( + refFindAncestorOfType(pCallContext->pResourceRef, + classId(Device), &pDeviceRef)); + + if (pDeviceRef == NULL) + return ENG_INVALID; + + NV_ASSERT_OK( + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + dynamicCast(pDeviceRef->pResource, Device), + &ref)); + + NV_ASSERT_OK( + kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, + RM_ENGINE_TYPE_OFA(engineInstance), + &rmEngineType)); + return ENG_OFA(RM_ENGINE_TYPE_OFA_IDX(rmEngineType)); + } + + // Get the right class as per engine instance. + return ENG_OFA(engineInstance); +} diff --git a/src/nvidia/src/kernel/gpu/perf/kern_perf_gpuboostsync.c b/src/nvidia/src/kernel/gpu/perf/kern_perf_gpuboostsync.c index 619ceab04f..2c919b4d66 100644 --- a/src/nvidia/src/kernel/gpu/perf/kern_perf_gpuboostsync.c +++ b/src/nvidia/src/kernel/gpu/perf/kern_perf_gpuboostsync.c @@ -177,6 +177,7 @@ kperfDoSyncGpuBoostLimits_IMPL GPUBOOSTMGR_ITR_START(pBoostMgr, grpId, pGpuItr) { pKernelPerf = GPU_GET_KERNEL_PERF(pGpuItr); + NV_CHECK_OR_RETURN(LEVEL_ERROR, (pKernelPerf != NULL), NV_ERR_INVALID_POINTER); // Find min of all GPU Boost PERF_LIMITs across all the GPUs. for (i = 0; i < NV2080_CTRL_INTERNAL_PERF_SYNC_GPU_BOOST_LIMITS_NUM; i++) diff --git a/src/nvidia/src/kernel/gpu/perf/kern_perf_pwr.c b/src/nvidia/src/kernel/gpu/perf/kern_perf_pwr.c index 91ffa3fb04..6cb62011b5 100644 --- a/src/nvidia/src/kernel/gpu/perf/kern_perf_pwr.c +++ b/src/nvidia/src/kernel/gpu/perf/kern_perf_pwr.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -181,6 +181,9 @@ subdeviceCtrlCmdPerfSetAuxPowerState_KERNEL _kperfSendPostPowerStateCallback(pGpu, pKernelPerf); + // Notify clients about Dx State event + gpuNotifySubDeviceEvent(pGpu, NV2080_NOTIFIERS_AUX_POWER_EVENT, NULL, 0, 0, 0); + return status; } diff --git a/src/nvidia/src/kernel/gpu/pmu/kern_pmu.c b/src/nvidia/src/kernel/gpu/pmu/kern_pmu.c index fd1849abec..1f538a4bcd 100644 --- a/src/nvidia/src/kernel/gpu/pmu/kern_pmu.c +++ b/src/nvidia/src/kernel/gpu/pmu/kern_pmu.c @@ -29,6 +29,7 @@ ****************************************************************************/ #include "gpu/pmu/kern_pmu.h" +#include "gpu/mem_mgr/mem_mgr.h" NV_STATUS kpmuConstructEngine_IMPL(OBJGPU *pGpu, KernelPmu *pKernelPmu, ENGDESCRIPTOR engDesc) @@ -37,6 +38,21 @@ kpmuConstructEngine_IMPL(OBJGPU *pGpu, KernelPmu *pKernelPmu, ENGDESCRIPTOR engD return kpmuInitLibosLoggingStructures(pGpu, pKernelPmu); } +void +kpmuStateDestroy_IMPL +( + OBJGPU *pGpu, + KernelPmu *pKernelPmu +) +{ + if (pKernelPmu->pPmuRsvdMemdesc != NULL) + { + memdescFree(pKernelPmu->pPmuRsvdMemdesc); + memdescDestroy(pKernelPmu->pPmuRsvdMemdesc); + pKernelPmu->pPmuRsvdMemdesc = NULL; + } +} + void kpmuDestruct_IMPL(KernelPmu *pKernelPmu) { @@ -45,6 +61,24 @@ kpmuDestruct_IMPL(KernelPmu *pKernelPmu) kpmuFreeLibosLoggingStructures(pGpu, pKernelPmu); } +NvU32 kpmuReservedMemorySizeGet_IMPL +( + KernelPmu *pKernelPmu +) +{ + return 0U; +} + +NvU64 kpmuReservedMemoryOffsetGet_IMPL +( + OBJGPU *pGpu, + KernelPmu *pKernelPmu +) +{ + return 0U; +} + + /*! * Init libos PMU logging */ diff --git a/src/nvidia/src/kernel/gpu/rc/kernel_rc.c b/src/nvidia/src/kernel/gpu/rc/kernel_rc.c index ca0affa622..f852184e4a 100644 --- a/src/nvidia/src/kernel/gpu/rc/kernel_rc.c +++ b/src/nvidia/src/kernel/gpu/rc/kernel_rc.c @@ -203,6 +203,13 @@ _krcInitRegistryOverrides #endif } } + + // + // Do RC on BAR faults by default (For bug 1842228). + // Only applicable to Volta+ chips. + // + pKernelRc->bRcOnBar2Fault = NV_TRUE; + } diff --git a/src/nvidia/src/kernel/gpu/rc/kernel_rc_callback.c b/src/nvidia/src/kernel/gpu/rc/kernel_rc_callback.c index 115e29ddbb..2e4edd22bc 100644 --- a/src/nvidia/src/kernel/gpu/rc/kernel_rc_callback.c +++ b/src/nvidia/src/kernel/gpu/rc/kernel_rc_callback.c @@ -232,7 +232,6 @@ krcErrorInvokeCallback_IMPL { OBJSYS *pSys = SYS_GET_INSTANCE(); Journal *pRcDB = SYS_GET_RCDB(pSys); - OBJOS *pOS = SYS_GET_OS(pSys); KernelMIGManager *pKernelMigManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); RmClient *pClient = NULL; RC_CALLBACK_STATUS clientAction; @@ -256,9 +255,9 @@ krcErrorInvokeCallback_IMPL kmigmgrIsEnginePartitionable(pGpu, pKernelMigManager, rmEngineType)) { MIG_INSTANCE_REF ref; - status = kmigmgrGetInstanceRefFromClient(pGpu, + status = kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMigManager, - RES_GET_CLIENT_HANDLE(pKernelChannel), + GPU_RES_GET_DEVICE(pKernelChannel), &ref); if (status != NV_OK) return bReturn; @@ -281,17 +280,12 @@ krcErrorInvokeCallback_IMPL return bReturn; } - if (pOS->osCheckCallback(pGpu)) + if (osCheckCallback(pGpu)) { - NvHandle hDevice, hFifo; RC_ERROR_CONTEXT *pRcErrorContext = NULL; - Device *pDevice; - - NV_ASSERT_OK_OR_RETURN( - deviceGetByGpu(RES_GET_CLIENT(pKernelChannel), pGpu, NV_TRUE, &pDevice)); - - hDevice = RES_GET_HANDLE(pDevice); - + Device *pDevice = GPU_RES_GET_DEVICE(pKernelChannel); + NvHandle hDevice = RES_GET_HANDLE(pDevice); + NvHandle hFifo; if (!pKernelChannel->pKernelChannelGroupApi->pKernelChannelGroup ->bAllocatedByRm) @@ -327,15 +321,15 @@ krcErrorInvokeCallback_IMPL } } - clientAction = pOS->osRCCallback(pGpu, - RES_GET_CLIENT_HANDLE(pKernelChannel), - hDevice, - hFifo, - RES_GET_HANDLE(pKernelChannel), - exceptLevel, - exceptType, - (NvU32 *)pRcErrorContext, - &krcResetCallback); + clientAction = osRCCallback(pGpu, + RES_GET_CLIENT_HANDLE(pKernelChannel), + hDevice, + hFifo, + RES_GET_HANDLE(pKernelChannel), + exceptLevel, + exceptType, + (NvU32 *)pRcErrorContext, + &krcResetCallback); if (clientAction == RC_CALLBACK_IGNORE || clientAction == RC_CALLBACK_ISOLATE_NO_RESET) diff --git a/src/nvidia/src/kernel/gpu/rc/kernel_rc_notification.c b/src/nvidia/src/kernel/gpu/rc/kernel_rc_notification.c index 6255f73edc..1e5790cf15 100644 --- a/src/nvidia/src/kernel/gpu/rc/kernel_rc_notification.c +++ b/src/nvidia/src/kernel/gpu/rc/kernel_rc_notification.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -44,7 +44,7 @@ _krcErrorWriteNotifierCpuMemHelper ( OBJGPU *pGpu, Memory *pMemory, - RsClient *pClient, + Device *pDevice, NvU32 exceptType, RM_ENGINE_TYPE localRmEngineType, NV_STATUS notifierStatus @@ -56,7 +56,7 @@ _krcErrorWriteNotifierCpuMemHelper { case ADDR_VIRTUAL: notifyFillNotifierGPUVA(pGpu, - pClient, + pDevice, RES_GET_HANDLE(pMemory), memdescGetPhysAddr(pMemory->pMemDesc, AT_GPU_VA, 0), exceptType, @@ -103,7 +103,7 @@ krcErrorWriteNotifier_CPU NV_STATUS status = NV_OK; ContextDma *pContextDma; Memory *pMemory; - Device *pDevice; + Device *pDevice = GPU_RES_GET_DEVICE(pKernelChannel); // // Update the ECC error notifier for exceptTypes related to // CONTAINED/UNCONTAINED/DBE errors @@ -113,14 +113,6 @@ krcErrorWriteNotifier_CPU exceptType == ROBUST_CHANNEL_UNCONTAINED_ERROR || exceptType == ROBUST_CHANNEL_CONTAINED_ERROR); - status = deviceGetByInstance(RES_GET_CLIENT(pKernelChannel), - gpuGetDeviceInstance(pGpu), - &pDevice); - if (status != NV_OK) - { - return NV_ERR_INVALID_DEVICE; - } - if (hypervisorIsVgxHyper() && bUpdateEccNotifier && pKernelChannel->hEccErrorContext != NV01_NULL_OBJECT) { @@ -147,7 +139,7 @@ krcErrorWriteNotifier_CPU { status = _krcErrorWriteNotifierCpuMemHelper(pGpu, pMemory, - RES_GET_CLIENT(pKernelChannel), + pDevice, exceptType, localRmEngineType, notifierStatus); @@ -199,7 +191,7 @@ krcErrorWriteNotifier_CPU { status = _krcErrorWriteNotifierCpuMemHelper(pGpu, pMemory, - RES_GET_CLIENT(pKernelChannel), + pDevice, exceptType, localRmEngineType, notifierStatus); @@ -300,8 +292,8 @@ NV_STATUS krcErrorSetNotifier_IMPL KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); MIG_INSTANCE_REF ref; - status = kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, - RES_GET_CLIENT_HANDLE(pKernelChannel), + status = kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + GPU_RES_GET_DEVICE(pKernelChannel), &ref); if (status != NV_OK) goto Error; @@ -335,7 +327,7 @@ NV_STATUS krcErrorSetNotifier_IMPL } if (flushFlags != 0) { - kbusFlush_HAL(pGpu, GPU_GET_KERNEL_BUS(pGpu), flushFlags | BUS_FLUSH_USE_PCIE_READ); + kbusFlush_HAL(pGpu, GPU_GET_KERNEL_BUS(pGpu), flushFlags); } Error: diff --git a/src/nvidia/src/kernel/gpu/rc/kernel_rc_watchdog.c b/src/nvidia/src/kernel/gpu/rc/kernel_rc_watchdog.c index 9a316a44c0..2ff2610882 100644 --- a/src/nvidia/src/kernel/gpu/rc/kernel_rc_watchdog.c +++ b/src/nvidia/src/kernel/gpu/rc/kernel_rc_watchdog.c @@ -23,6 +23,7 @@ #include "kernel/core/core.h" #include "kernel/core/locks.h" +#include "gpu/subdevice/subdevice.h" #include "kernel/gpu/mem_mgr/heap.h" #include "kernel/gpu/mem_mgr/mem_mgr.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" diff --git a/src/nvidia/src/kernel/gpu/sec2/arch/hopper/kernel_sec2_gh100.c b/src/nvidia/src/kernel/gpu/sec2/arch/hopper/kernel_sec2_gh100.c index 86f2368231..c61ef7ed87 100644 --- a/src/nvidia/src/kernel/gpu/sec2/arch/hopper/kernel_sec2_gh100.c +++ b/src/nvidia/src/kernel/gpu/sec2/arch/hopper/kernel_sec2_gh100.c @@ -22,11 +22,11 @@ */ #include "gpu/sec2/kernel_sec2.h" +#include "core/core.h" + #include "gpu/conf_compute/conf_compute.h" #include "conf_compute/cc_keystore.h" -#include "core/core.h" - NV_STATUS ksec2StateLoad_GH100 ( diff --git a/src/nvidia/src/kernel/gpu/spdm/arch/hopper/spdm_gh100.c b/src/nvidia/src/kernel/gpu/spdm/arch/hopper/spdm_gh100.c index 557434d266..80235bb10f 100644 --- a/src/nvidia/src/kernel/gpu/spdm/arch/hopper/spdm_gh100.c +++ b/src/nvidia/src/kernel/gpu/spdm/arch/hopper/spdm_gh100.c @@ -838,7 +838,8 @@ spdmDeviceInit_GH100 return NV_ERR_INSUFFICIENT_RESOURCES; } - status = memdescAlloc(pIOContext->pMemDesc); + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_82, + pIOContext->pMemDesc); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "SPDM: Cannot allocate SPDM surface!\n"); @@ -886,6 +887,7 @@ spdmDeviceInit_GH100 // Ucode is responsible for setting DMA index. pCcInitCtx->guestId = pSpdm->guestId; + pCcInitCtx->rmBufferSizeInByte = NV_RM_BUFFER_SIZE_IN_BYTE; NvU64_ALIGN32_PACK(&pCcInitCtx->dmaAddr, &pIOContext->dmaAddr); gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); diff --git a/src/nvidia/src/kernel/gpu/subdevice/generic_engine.c b/src/nvidia/src/kernel/gpu/subdevice/generic_engine.c index 733732e05d..c186920639 100644 --- a/src/nvidia/src/kernel/gpu/subdevice/generic_engine.c +++ b/src/nvidia/src/kernel/gpu/subdevice/generic_engine.c @@ -29,6 +29,7 @@ #include "rmapi/client.h" #include +#include NV_STATUS @@ -82,6 +83,15 @@ genapiControl_IMPL RS_RES_CONTROL_PARAMS_INTERNAL *pParams ) { + if (RES_GET_EXT_CLASS_ID(pGenericEngineApi) == GF100_SUBDEVICE_INFOROM) + { + OBJGPU *pGpu = GPU_RES_GET_GPU(pGenericEngineApi); + OBJINFOROM *pInforom = GPU_GET_INFOROM(pGpu); + if (!IS_GSP_CLIENT(pGpu) && pInforom == NULL) + { + return NV_ERR_NOT_SUPPORTED; + } + } return gpuresControl_IMPL(staticCast(pGenericEngineApi, GpuResource), pCallContext, pParams); diff --git a/src/nvidia/src/kernel/gpu/subdevice/subdevice.c b/src/nvidia/src/kernel/gpu/subdevice/subdevice.c index 0e3082ff99..91aed43984 100644 --- a/src/nvidia/src/kernel/gpu/subdevice/subdevice.c +++ b/src/nvidia/src/kernel/gpu/subdevice/subdevice.c @@ -280,24 +280,39 @@ subdeviceGetByGpu_IMPL Subdevice **ppSubdevice ) { - Subdevice *pSubdevice = NULL; - OBJGPU *pTmpGpu = NULL; - RS_ITERATOR it; - RsResourceRef *pResourceRef; + return subdeviceGetByDeviceAndGpu(pClient, NULL, pGpu, ppSubdevice); +} + +NV_STATUS +subdeviceGetByDeviceAndGpu_IMPL +( + RsClient *pClient, + Device *pDevice, + OBJGPU *pGpu, + Subdevice **ppSubdevice +) +{ + Subdevice *pSubdevice = NULL; + RS_ITERATOR it; + RS_ITER_TYPE iterType = RS_ITERATE_DESCENDANTS; + RsResourceRef *pDeviceRef = NULL; *ppSubdevice = NULL; - it = clientRefIter(pClient, NULL, classId(Subdevice), RS_ITERATE_DESCENDANTS, NV_TRUE); - while (clientRefIterNext(pClient, &it)) + if (pDevice != NULL) { - pResourceRef = it.pResourceRef; - pSubdevice = dynamicCast(pResourceRef->pResource, Subdevice); - if (pSubdevice == NULL) - continue; + pDeviceRef = RES_GET_REF(pDevice); + iterType = RS_ITERATE_CHILDREN; + } - pTmpGpu = GPU_RES_GET_GPU(pSubdevice); + it = clientRefIter(pClient, pDeviceRef, classId(Subdevice), + iterType, NV_TRUE); + + while (clientRefIterNext(pClient, &it)) + { + pSubdevice = dynamicCast(it.pResourceRef->pResource, Subdevice); - if (pTmpGpu == pGpu) + if (GPU_RES_GET_GPU(pSubdevice) == pGpu) { *ppSubdevice = pSubdevice; return NV_OK; diff --git a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_event_kernel.c b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_event_kernel.c index 17f8122cc4..c907be0d01 100644 --- a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_event_kernel.c +++ b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_event_kernel.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2004-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c index 913b1d77ec..f1f4930e5e 100644 --- a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c +++ b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c @@ -29,9 +29,6 @@ * File contains ctrls related to general GPU */ -// FIXME XXX -#define NVOC_KERNEL_GRAPHICS_MANAGER_H_PRIVATE_ACCESS_ALLOWED - #include "core/core.h" #include "core/locks.h" #include "gpu/subdevice/subdevice.h" @@ -225,8 +222,8 @@ getGpuInfos(Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_INFO_V2_PARAMS *pParams, KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); if ((pKernelGraphicsManager == NULL) || - !pKernelGraphicsManager->legacyKgraphicsStaticInfo.bInitialized || - (pKernelGraphicsManager->legacyKgraphicsStaticInfo.pGrInfo == NULL)) + !kgrmgrGetLegacyKGraphicsStaticInfo(pGpu, pKernelGraphicsManager)->bInitialized || + (kgrmgrGetLegacyKGraphicsStaticInfo(pGpu, pKernelGraphicsManager)->pGrInfo == NULL)) { NV_PRINTF(LEVEL_ERROR, "Unable to retrieve SM version!\n"); data = NV2080_CTRL_GR_INFO_SM_VERSION_NONE; @@ -234,7 +231,7 @@ getGpuInfos(Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_INFO_V2_PARAMS *pParams, } else { - data = pKernelGraphicsManager->legacyKgraphicsStaticInfo.pGrInfo->infoList[NV2080_CTRL_GR_INFO_INDEX_SM_VERSION].data; + data = kgrmgrGetLegacyKGraphicsStaticInfo(pGpu, pKernelGraphicsManager)->pGrInfo->infoList[NV2080_CTRL_GR_INFO_INDEX_SM_VERSION].data; } break; } @@ -729,11 +726,19 @@ subdeviceCtrlCmdGpuGetEncoderCapacity_IMPL ) { NV_STATUS rmStatus = NV_OK; + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); - if ((pEncoderCapacityParams->queryType != NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_H264) && - (pEncoderCapacityParams->queryType != NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_HEVC)) + if (pEncoderCapacityParams->queryType == NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_AV1) + { + if (pGpu->bGpuNvEncAv1Supported == NV_FALSE) + { + return NV_ERR_NOT_SUPPORTED; + } + } + else if ((pEncoderCapacityParams->queryType != NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_H264) && + (pEncoderCapacityParams->queryType != NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_HEVC)) { return NV_ERR_INVALID_ARGUMENT; } @@ -2663,6 +2668,11 @@ _convertGpuFabricProbeInfoCaps fabricCaps |= NV2080_CTRL_GPU_FABRIC_PROBE_CAP_MC_SUPPORTED; break; } + case NVLINK_INBAND_FM_CAPS_MC_TEAM_SETUP_V2: + { + fabricCaps |= NV2080_CTRL_GPU_FABRIC_PROBE_CAP_MC_SUPPORTED; + break; + } default: { break; @@ -2726,6 +2736,9 @@ subdeviceCtrlCmdGetGpuFabricProbeInfo_IMPL NV_ASSERT_OK(gpuFabricProbeGetFabricPartitionId(pGpu->pGpuFabricProbeInfoKernel, &pParams->fabricPartitionId)); + NV_ASSERT_OK(gpuFabricProbeGetFabricCliqueId(pGpu->pGpuFabricProbeInfoKernel, + &pParams->fabricCliqueId)); + NV_ASSERT_OK(gpuFabricProbeGetfmCaps(pGpu->pGpuFabricProbeInfoKernel, &fmCaps)); pParams->fabricCaps = _convertGpuFabricProbeInfoCaps(fmCaps); diff --git a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_timer_kernel.c b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_timer_kernel.c index b6c8864c47..c6e42b0dc2 100644 --- a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_timer_kernel.c +++ b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_timer_kernel.c @@ -238,7 +238,7 @@ subdeviceCtrlCmdTimerGetTime_IMPL } else { - LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); } tmrGetCurrentTime(pTmr, &pParams->time_nsec); diff --git a/src/nvidia/src/kernel/gpu/timed_semaphore.c b/src/nvidia/src/kernel/gpu/timed_semaphore.c index ab908c16c6..d088675c54 100644 --- a/src/nvidia/src/kernel/gpu/timed_semaphore.c +++ b/src/nvidia/src/kernel/gpu/timed_semaphore.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2016-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -104,7 +104,7 @@ _9074TimedSemRelease ( OBJGPU *pGpu, ChannelDescendant *pObject, - RsClient *pClient, + Device *pDevice, NvU64 notifierGPUVA, NvU64 semaphoreGPUVA, NvU64 time, @@ -122,7 +122,7 @@ _9074TimedSemRelease pObject->pKernelChannel->hVASpace, releaseValue, notifierStatus, - pClient); + pDevice); // timedSemaphoreRelease_HAL will print errors on its own if (status != NV_OK) @@ -183,7 +183,7 @@ _9074TimedSemRequest { status = _9074TimedSemRelease(pGpu, pObject, - RES_GET_CLIENT(pTimedSemSw), + GPU_RES_GET_DEVICE(pTimedSemSw), notifierGPUVA, semaphoreGPUVA, currentTime, @@ -568,7 +568,7 @@ static NV_STATUS _class9074TimerCallback status = _9074TimedSemRelease(pGpu, pObject, - RES_GET_CLIENT(pTimedSemSw), + GPU_RES_GET_DEVICE(pTimedSemSw), pTimedSemEntry->NotifierGPUVA, pTimedSemEntry->SemaphoreGPUVA, currentTime, @@ -625,7 +625,7 @@ tsemaRelease_KERNEL NvU32 hVASpace, NvU32 releaseValue, NvU32 completionStatus, - RsClient *pClient + Device *pDevice ) { OBJTMR *pTmr = GPU_GET_TIMER(pGpu); @@ -636,7 +636,7 @@ tsemaRelease_KERNEL tmrGetCurrentTime(pTmr, ¤tTime); status = semaphoreFillGPUVATimestamp(pGpu, - pClient, + pDevice, hVASpace, semaphoreVA, releaseValue, @@ -652,7 +652,7 @@ tsemaRelease_KERNEL } status = notifyFillNotifierGPUVATimestamp(pGpu, - pClient, + pDevice, hVASpace, notifierVA, 0, /* Info32 */ diff --git a/src/nvidia/src/kernel/gpu/timer/timer.c b/src/nvidia/src/kernel/gpu/timer/timer.c index d0b480f2e1..ea4901a00b 100644 --- a/src/nvidia/src/kernel/gpu/timer/timer.c +++ b/src/nvidia/src/kernel/gpu/timer/timer.c @@ -1205,34 +1205,27 @@ tmrCallExpiredCallbacks_IMPL // Pull from head of list. pEvent = _tmrPullCallbackFromHead(pTmr); - if (pEvent && - ((pEvent->super.pTimeProc != NULL) || - (pEvent->pTimeProc_OBSOLETE != NULL)) ) + if (pEvent != NULL) { // Call callback. This could insert a new callback into the list. - if (pEvent->bLegacy) + if (pEvent->bLegacy && pEvent->pTimeProc_OBSOLETE != NULL) { pEvent->pTimeProc_OBSOLETE(pGpu, pTmr, pEvent->super.pUserData); + bProccessedCallback = NV_TRUE; } - else + else if (!pEvent->bLegacy && pEvent->super.pTimeProc != NULL) { pEvent->super.pTimeProc(pGpu, pTmr, (PTMR_EVENT)pEvent); + bProccessedCallback = NV_TRUE; + } + else + { + NV_ASSERT_FAILED("Attempting to execute callback with NULL procedure."); } - - bProccessedCallback = NV_TRUE; } else { - // - // Bug 372159: Hopefully by checking that the callback procedure - // is not NULL in tmrEventScheduleAbs() we should never hit - // this point, but this is just to be certain. If you hit this - // assert please update Bug 3721259 with pertinent details - // (Swak, !stacks, what you were developing/testing, etc.). - // - NV_ASSERT_FAILED( - "Attempting to execute callback with NULL procedure. " - "Please update Bug 372159 with appropriate information."); + NV_ASSERT_FAILED("Attempting to execute callback with NULL timer event."); } } diff --git a/src/nvidia/src/kernel/gpu/uvm/arch/volta/uvm_gv100.c b/src/nvidia/src/kernel/gpu/uvm/arch/volta/uvm_gv100.c index 49a569e3e9..5b3d24f4d4 100644 --- a/src/nvidia/src/kernel/gpu/uvm/arch/volta/uvm_gv100.c +++ b/src/nvidia/src/kernel/gpu/uvm/arch/volta/uvm_gv100.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -314,7 +314,8 @@ uvmInitAccessCntrBuffer_GV100 memdescSetGpuCacheAttrib(pUvmAccessCntrBufferDesc, NV_MEMORY_UNCACHED); } - status = memdescAlloc(pUvmAccessCntrBufferDesc); + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_44, + pUvmAccessCntrBufferDesc); if (status != NV_OK) { memdescDestroy(pUvmAccessCntrBufferDesc); diff --git a/src/nvidia/src/kernel/gpu/video/kernel_video_engine.c b/src/nvidia/src/kernel/gpu/video/kernel_video_engine.c new file mode 100644 index 0000000000..b38f2c21d9 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/video/kernel_video_engine.c @@ -0,0 +1,183 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#include "kernel/gpu/video/kernel_video_engine.h" +#include "kernel/gpu/mem_mgr/mem_desc.h" +#include "kernel/gpu/bus/kern_bus.h" +#include "kernel/os/os.h" +#include "nvrm_registry.h" + +NV_STATUS kvidengConstruct_IMPL +( + KernelVideoEngine *pKernelVideoEngine, + OBJGPU *pGpu, + ENGDESCRIPTOR physEngDesc +) +{ + pKernelVideoEngine->physEngDesc = physEngDesc; + return NV_OK; +} + +NV_STATUS kvidengInitLogging_IMPL +( + OBJGPU *pGpu, + KernelVideoEngine *pKernelVideoEngine +) +{ + NV_STATUS status; + NvU32 data = NV_REG_STR_RM_VIDEO_EVENT_TRACE_DISABLED; + NvBool alwaysLogging; + + if (!gpuIsVideoTraceLogSupported(pGpu)) + return NV_OK; + + NV_ASSERT_OR_RETURN(pKernelVideoEngine != NULL, NV_ERR_INVALID_STATE); + + status = osReadRegistryDword(pGpu, NV_REG_STR_RM_VIDEO_EVENT_TRACE, &data); + if (status != NV_OK) + { + // When GLOBAL_FEATURE_GR2069_VIDEO_EVENT is enabled and the registry is not set, + // default eventbuffer size to 32K and staging buffer to 4K. + data = DRF_NUM(_REG_STR, _RM_VIDEO_EVENT_TRACE, _STAGING_BUFFER_SIZE_IN_4k, 1) | + DRF_NUM(_REG_STR, _RM_VIDEO_EVENT_TRACE, _EVENT_BUFFER_SIZE_IN_4k, 0x8); + } + + alwaysLogging = DRF_VAL(_REG_STR, _RM_VIDEO_EVENT_TRACE, _ALWAYS_LOG, (data)) == + NV_REG_STR_RM_VIDEO_EVENT_TRACE_ALWAYS_LOG_ENABLED; + + if (data != NV_REG_STR_RM_VIDEO_EVENT_TRACE_DISABLED) + { + NvU32 eventBufferSize; + VIDEO_TRACE_RING_BUFFER *pTraceBuf; + NvU64 seed; + NvBool bIsFbBroken = NV_FALSE; + NV_ADDRESS_SPACE videoBufferAddressSpace = ADDR_FBMEM; + + eventBufferSize = DRF_VAL(_REG_STR, _RM_VIDEO_EVENT_TRACE, _EVENT_BUFFER_SIZE_IN_4k, (data)) * 0x1000; + + bIsFbBroken = pGpu->getProperty(pGpu, PDB_PROP_GPU_BROKEN_FB) || + pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_ALL_INST_IN_SYSMEM); + + if (bIsFbBroken) + videoBufferAddressSpace = ADDR_SYSMEM; + + // Allocate the staging buffer + NV_ASSERT_OK_OR_GOTO( + status, + memdescCreate(&pKernelVideoEngine->videoTraceInfo.pTraceBufferEngineMemDesc, + pGpu, + eventBufferSize, + 0, + NV_TRUE, + videoBufferAddressSpace, + NV_MEMORY_UNCACHED, + MEMDESC_FLAGS_NONE), + exit); + + NV_ASSERT_OK_OR_GOTO( + status, + memdescAlloc(pKernelVideoEngine->videoTraceInfo.pTraceBufferEngineMemDesc), + exit); + + pTraceBuf = (VIDEO_TRACE_RING_BUFFER *)kbusMapRmAperture_HAL(pGpu, pKernelVideoEngine->videoTraceInfo.pTraceBufferEngineMemDesc); + + NV_ASSERT_OR_ELSE(pTraceBuf != NULL, + status = NV_ERR_INSUFFICIENT_RESOURCES; + goto exit;); + + // clear trace buffer + portMemSet(pTraceBuf, 0, eventBufferSize); + + pTraceBuf->bufferSize = eventBufferSize - sizeof(VIDEO_TRACE_RING_BUFFER); + pTraceBuf->readPtr = 0; + pTraceBuf->writePtr = 0; + pTraceBuf->flags = alwaysLogging ? VIDEO_TRACE_FLAG__LOGGING_ENABLED : 0; + + pKernelVideoEngine->videoTraceInfo.pTraceBufferEngine = pTraceBuf; + + // Allocate allocate scratch pad for variable data + pKernelVideoEngine->videoTraceInfo.pTraceBufferVariableData = portMemAllocNonPaged(RM_VIDEO_TRACE_MAX_VARIABLE_DATA_SIZE); + + if (pKernelVideoEngine->videoTraceInfo.pTraceBufferVariableData == NULL) + { + status = NV_ERR_NO_MEMORY; + goto exit; + } + portMemSet(pKernelVideoEngine->videoTraceInfo.pTraceBufferVariableData, 0x00, RM_VIDEO_TRACE_MAX_VARIABLE_DATA_SIZE); + + /*! + * Random number generator used for generate noisy timestamp + */ + osGetCurrentTick(&seed); + pKernelVideoEngine->videoTraceInfo.pVideoLogPrng = portCryptoPseudoRandomGeneratorCreate(seed); + } + +exit: + if (status != NV_OK) + { + kvidengFreeLogging(pGpu, pKernelVideoEngine); + + if (status == NV_WARN_NOTHING_TO_DO) + status = NV_OK; + } + else + { + pKernelVideoEngine->bVideoTraceEnabled = NV_TRUE; + } + + return status; +} + +void kvidengFreeLogging_IMPL +( + OBJGPU *pGpu, + KernelVideoEngine *pKernelVideoEngine +) +{ + if (pKernelVideoEngine->videoTraceInfo.pTraceBufferEngine != NULL) + { + kbusUnmapRmAperture_HAL(pGpu, pKernelVideoEngine->videoTraceInfo.pTraceBufferEngineMemDesc, + &(pKernelVideoEngine->videoTraceInfo.pTraceBufferEngine), + NV_TRUE); + pKernelVideoEngine->videoTraceInfo.pTraceBufferEngine = NULL; + } + + if (pKernelVideoEngine->videoTraceInfo.pTraceBufferEngineMemDesc != NULL) + { + memdescFree(pKernelVideoEngine->videoTraceInfo.pTraceBufferEngineMemDesc); + memdescDestroy(pKernelVideoEngine->videoTraceInfo.pTraceBufferEngineMemDesc); + pKernelVideoEngine->videoTraceInfo.pTraceBufferEngineMemDesc = NULL; + } + + portMemFree(pKernelVideoEngine->videoTraceInfo.pTraceBufferVariableData); + pKernelVideoEngine->videoTraceInfo.pTraceBufferVariableData = NULL; + + /*! + * Free random number generator used for generate noisy timestamp + */ + portCryptoPseudoRandomGeneratorDestroy(pKernelVideoEngine->videoTraceInfo.pVideoLogPrng); + pKernelVideoEngine->videoTraceInfo.pVideoLogPrng = NULL; + + pKernelVideoEngine->bVideoTraceEnabled = NV_FALSE; +} diff --git a/src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c b/src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c index e795038862..4404085cdd 100644 --- a/src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c +++ b/src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c @@ -30,6 +30,7 @@ #include "core/system.h" #include "core/locks.h" #include "gpu_mgr/gpu_mgr.h" +#include "gpu/device/device.h" #include "gpu/gpu.h" #include "tls/tls.h" #include "nvrm_registry.h" @@ -48,7 +49,7 @@ // local static funcs static void gpumgrSetAttachInfo(OBJGPU *, GPUATTACHARG *); -static void gpumgrGetGpuHalFactor(NvU32 *pChipId0, NvU32 *pChipId1, NvU32 *pSocChipId0, RM_RUNTIME_VARIANT *pRmVariant, GPUATTACHARG *pAttachArg); +static void gpumgrGetGpuHalFactor(NvU32 *pChipId0, NvU32 *pChipId1, NvU32 *pSocChipId0, RM_RUNTIME_VARIANT *pRmVariant, TEGRA_CHIP_TYPE *pTegraType, GPUATTACHARG *pAttachArg); static NvBool _gpumgrGetPcieP2PCapsFromCache(NvU32 gpuMask, NvU8* pP2PWriteCapsStatus, NvU8* pP2PReadCapsStatus); static void @@ -179,6 +180,27 @@ _gpumgrDetermineConfComputeCapabilities return NV_OK; } +static void +_gpumgrCacheClearMIGGpuIdInfo(NvU32 gpuId) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); + NvU32 i; + + portSyncRwLockAcquireWrite(pGpuMgr->cachedMIGInfoLock); + + for (i = 0; i < NV_MAX_DEVICES; i++) + { + if (pGpuMgr->cachedMIGInfo[i].gpuId == gpuId) + { + portMemSet(&pGpuMgr->cachedMIGInfo[i], 0x0, sizeof(pGpuMgr->cachedMIGInfo[i])); + break; + } + } + + portSyncRwLockReleaseWrite(pGpuMgr->cachedMIGInfoLock); +} + // // ODB functions // @@ -218,6 +240,13 @@ gpumgrConstruct_IMPL(OBJGPUMGR *pGpuMgr) NV_ASSERT_OK_OR_RETURN(gpumgrInitPcieP2PCapsCache(pGpuMgr)); + pGpuMgr->cachedMIGInfoLock = + portSyncRwLockCreate(portMemAllocatorGetGlobalNonPaged()); + NV_ASSERT_OR_RETURN(pGpuMgr->cachedMIGInfoLock != NULL, + NV_ERR_INSUFFICIENT_RESOURCES); + + portMemSet(pGpuMgr->cachedMIGInfo, 0, sizeof(pGpuMgr->cachedMIGInfo)); + return NV_OK; } @@ -229,8 +258,9 @@ gpumgrDestruct_IMPL(OBJGPUMGR *pGpuMgr) portSyncMutexDestroy(pGpuMgr->probedGpusLock); - gpumgrDestroyPcieP2PCapsCache(pGpuMgr); + portSyncRwLockDestroy(pGpuMgr->cachedMIGInfoLock); + gpumgrDestroyPcieP2PCapsCache(pGpuMgr); } // @@ -595,6 +625,7 @@ gpumgrUnregisterGpuId(NvU32 gpuId) if (pProbedGpu->gpuId == gpuId) { + _gpumgrCacheClearMIGGpuIdInfo(gpuId); gpumgrRemovePcieP2PCapsFromCache(pProbedGpu->gpuId); _gpumgrUnregisterRmCapsForGpuUnderLock(pProbedGpu->gpuDomainBusDevice); pProbedGpu->gpuId = NV0000_CTRL_GPU_INVALID_ID; @@ -968,8 +999,6 @@ static NvBool gpumgrCheckRmFirmwarePolicy // // Get Gpu Hal factors those are used to init Hal binding // -// TODO : later this function will be used to read out NVOC Halspec init value for OBJGPU -// static void gpumgrGetGpuHalFactor ( @@ -977,12 +1006,15 @@ gpumgrGetGpuHalFactor NvU32 *pChipId1, NvU32 *pSocChipId0, RM_RUNTIME_VARIANT *pRmVariant, + TEGRA_CHIP_TYPE *pTegraType, GPUATTACHARG *pAttachArg ) { NvBool isVirtual; NvBool isFwClient; + *pTegraType = TEGRA_CHIP_TYPE_DEFAULT; + // get ChipId0 and ChipId1 if (pAttachArg->socDeviceArgs.specified) { @@ -1024,6 +1056,20 @@ gpumgrGetGpuHalFactor *pSocChipId0 = 0; gpumgrGetGpuHalFactorOfVirtual(&isVirtual, pAttachArg); + + // + // If socChipId0 has valid value, then running environment is SOCV. + // The Tegra chip after Ampere arch is using PCIE interface which connects + // iGPU to SoC for BAR and control accesses (interrupt). + // The code between TEGRA_CHIP_TYPE_PCIE and TEGRA_CHIP_TYPE_SOC + // shares same dGPU ARCH specific HAL mostly except manual differences due to + // latency of manual updates between nvgpu (Standlone iGPU/Full Chip Verification) + // and nvmobile (SOC) trees. + // + if (pAttachArg->socChipId0 != 0) + { + *pTegraType = TEGRA_CHIP_TYPE_SOC; + } } isFwClient = gpumgrCheckRmFirmwarePolicy(pAttachArg->nvDomainBusDeviceFunc, @@ -1038,6 +1084,10 @@ gpumgrGetGpuHalFactor *pRmVariant = RM_RUNTIME_VARIANT_PF_KERNEL_ONLY; else *pRmVariant = RM_RUNTIME_VARIANT_PF_MONOLITHIC; // default, monolithic mode + + NV_PRINTF(LEVEL_INFO, + "ChipId0[0x%x] ChipId1[0x%x] SocChipId0[0x%x] isFwClient[%d] RmVariant[%d] tegraType[%d]\n", + *pChipId0, *pChipId1, *pSocChipId0, isFwClient, *pRmVariant, *pTegraType); } @@ -1056,12 +1106,13 @@ _gpumgrCreateGpu(NvU32 gpuInstance, GPUATTACHARG *pAttachArg) OBJGPU *pGpu; NV_STATUS status; RM_RUNTIME_VARIANT rmVariant; + TEGRA_CHIP_TYPE tegraType; NvU32 chipId0; // 32-bit chipId (pmcBoot0 on GPU) NvU32 chipId1; // 32-bit chipId (pmcBoot42 on GPU) NvU32 socChipId0; // 32-bit SOC chipId NvU32 hidrev, majorRev; - gpumgrGetGpuHalFactor(&chipId0, &chipId1, &socChipId0, &rmVariant, pAttachArg); + gpumgrGetGpuHalFactor(&chipId0, &chipId1, &socChipId0, &rmVariant, &tegraType, pAttachArg); hidrev = DRF_VAL(_PAPB_MISC, _GP_HIDREV, _CHIPID, socChipId0); majorRev = DRF_VAL(_PAPB_MISC, _GP_HIDREV, _MAJORREV, socChipId0); @@ -1080,6 +1131,7 @@ _gpumgrCreateGpu(NvU32 gpuInstance, GPUATTACHARG *pAttachArg) /* ChipHal_impl = */ DRF_VAL(_PMC, _BOOT_42, _IMPLEMENTATION, chipId1), /* ChipHal_hidrev = */ hidrev, /* RmVariantHal_rmVariant = */ rmVariant, + /* TegraChipHal_tegraType = */ tegraType, /* DispIpHal_ipver = */ 0, // initialized later /* ctor.gpuInstance = */ gpuInstance); if (status != NV_OK) @@ -1580,7 +1632,7 @@ gpumgrSetAttachInfo(OBJGPU *pGpu, GPUATTACHARG *pAttachArg) // Generate GPU ID using end-point address for PCIe devices, otherwise use MMIO address gpuId = (!RMCFG_FEATURE_PLATFORM_WINDOWS_LDDM || !pGpu->bIsSOC) ? gpuGenerate32BitId(gpuGetDomain(pGpu), gpuGetBus(pGpu), gpuGetDevice(pGpu)) - : gpuGenerate32BitIdFromPhysAddr(pAttachArg->devPhysAddr); + : gpuGenerate32BitIdFromPhysAddr(pAttachArg->socDeviceArgs.deviceMapping[DEVICE_INDEX_GPU].gpuNvPAddr); if (gpuId != NV0000_CTRL_GPU_INVALID_ID) { @@ -2089,12 +2141,13 @@ gpumgrGetGpuIdInfoV2(NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS *pGpuInfo) if (gpuIsSelfHosted(pGpu) && IS_MIG_IN_USE(pGpu)) { CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); - RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams; KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); MIG_INSTANCE_REF ref; NvU32 swizzId; + Device *pDevice; - if (kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, pRmCtrlParams->hClient, &ref) == NV_OK) + if ((deviceGetByGpu(pCallContext->pClient, pGpu, NV_TRUE, &pDevice) == NV_OK) && + (kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, &ref) == NV_OK)) { swizzId = ref.pKernelMIGGpuInstance->swizzId; if (GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu)->memPartitionNumaInfo[swizzId].bInUse) @@ -3580,6 +3633,293 @@ gpumgrUnregisterRmCapsForMIGGI_IMPL(NvU64 gpuDomainBusDevice) } } +void +gpumgrCacheCreateGpuInstance_IMPL(OBJGPU *pGpu, NvU32 swizzId) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); + GPUMGR_CACHED_MIG_GPU_INSTANCE *pGpuInstances = NULL; + NvU32 i; + + portSyncRwLockAcquireWrite(pGpuMgr->cachedMIGInfoLock); + + for (i = 0; i < NV_MAX_DEVICES; i++) + { + if (pGpuMgr->cachedMIGInfo[i].gpuId == pGpu->gpuId) + { + pGpuInstances = pGpuMgr->cachedMIGInfo[i].gpuInstances; + break; + } + } + + NV_ASSERT_OR_GOTO(pGpuInstances != NULL, done); + + for (i = 0; i < GPUMGR_MAX_GPU_INSTANCES; i++) + { + if (!pGpuInstances[i].bValid) + { + pGpuInstances[i].bValid = NV_TRUE; + pGpuInstances[i].swizzId = swizzId; + goto done; + } + } + + NV_ASSERT(!"Unreachable"); + +done: + portSyncRwLockReleaseWrite(pGpuMgr->cachedMIGInfoLock); +} + +void +gpumgrCacheDestroyGpuInstance_IMPL(OBJGPU *pGpu, NvU32 swizzId) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); + GPUMGR_CACHED_MIG_GPU_INSTANCE *pGpuInstances = NULL; + NvU32 i; + + portSyncRwLockAcquireWrite(pGpuMgr->cachedMIGInfoLock); + + for (i = 0; i < NV_MAX_DEVICES; i++) + { + if (pGpuMgr->cachedMIGInfo[i].gpuId == pGpu->gpuId) + { + pGpuInstances = pGpuMgr->cachedMIGInfo[i].gpuInstances; + break; + } + } + + NV_ASSERT_OR_GOTO(pGpuInstances != NULL, done); + + for (i = 0; i < GPUMGR_MAX_GPU_INSTANCES; i++) + { + if (pGpuInstances[i].bValid && + pGpuInstances[i].swizzId == swizzId) + { + pGpuInstances[i].bValid = NV_FALSE; + goto done; + } + } + + NV_ASSERT(!"Unreachable"); + +done: + portSyncRwLockReleaseWrite(pGpuMgr->cachedMIGInfoLock); +} + +void +gpumgrCacheCreateComputeInstance_IMPL(OBJGPU *pGpu, NvU32 swizzId, NvU32 ciId) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); + GPUMGR_CACHED_MIG_GPU_INSTANCE *pGpuInstances = NULL; + NvU32 i; + + portSyncRwLockAcquireWrite(pGpuMgr->cachedMIGInfoLock); + + for (i = 0; i < NV_MAX_DEVICES; i++) + { + if (pGpuMgr->cachedMIGInfo[i].gpuId == pGpu->gpuId) + { + pGpuInstances = pGpuMgr->cachedMIGInfo[i].gpuInstances; + break; + } + } + + NV_ASSERT_OR_GOTO(pGpuInstances != NULL, done); + + for (i = 0; i < GPUMGR_MAX_GPU_INSTANCES; i++) + { + if (pGpuInstances[i].bValid && + pGpuInstances[i].swizzId == swizzId) + { + pGpuInstances[i].bValidComputeInstances[ciId] = NV_TRUE; + goto done; + } + } + + NV_ASSERT(!"Unreachable"); + +done: + portSyncRwLockReleaseWrite(pGpuMgr->cachedMIGInfoLock); +} + +void +gpumgrCacheDestroyComputeInstance_IMPL(OBJGPU *pGpu, NvU32 swizzId, NvU32 ciId) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); + GPUMGR_CACHED_MIG_GPU_INSTANCE *pGpuInstances = NULL; + NvU32 i; + + portSyncRwLockAcquireWrite(pGpuMgr->cachedMIGInfoLock); + + for (i = 0; i < NV_MAX_DEVICES; i++) + { + if (pGpuMgr->cachedMIGInfo[i].gpuId == pGpu->gpuId) + { + pGpuInstances = pGpuMgr->cachedMIGInfo[i].gpuInstances; + break; + } + } + + NV_ASSERT_OR_GOTO(pGpuInstances != NULL, done); + + for (i = 0; i < GPUMGR_MAX_GPU_INSTANCES; i++) + { + if (pGpuInstances[i].bValid && + pGpuInstances[i].swizzId == swizzId) + { + pGpuInstances[i].bValidComputeInstances[ciId] = NV_FALSE; + goto done; + } + } + + NV_ASSERT(!"Unreachable"); + +done: + portSyncRwLockReleaseWrite(pGpuMgr->cachedMIGInfoLock); +} + +void +gpumgrCacheSetMIGEnabled_IMPL(OBJGPU *pGpu, NvBool bMIGEnabled) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); + GPUMGR_CACHED_MIG_STATE *pMIGInfo = NULL; + NvU32 gpuId = pGpu->gpuId; + NvU32 i; + + portSyncRwLockAcquireWrite(pGpuMgr->cachedMIGInfoLock); + + for (i = 0; i < NV_MAX_DEVICES; i++) + { + if (pGpuMgr->cachedMIGInfo[i].bValid && + (pGpuMgr->cachedMIGInfo[i].gpuId == gpuId)) + { + pMIGInfo = &pGpuMgr->cachedMIGInfo[i]; + break; + } + } + + if (pMIGInfo == NULL) + { + // Get first invalid entry, for not yet seen gpuId. + for (i = 0; i < NV_MAX_DEVICES; i++) + { + if (!pGpuMgr->cachedMIGInfo[i].bValid) + { + pMIGInfo = &pGpuMgr->cachedMIGInfo[i]; + pMIGInfo->bValid = NV_TRUE; + pMIGInfo->gpuId = gpuId; + break; + } + } + } + + NV_ASSERT_OR_GOTO(pMIGInfo != NULL, done); + + pMIGInfo->bMIGEnabled = bMIGEnabled; + +done: + portSyncRwLockReleaseWrite(pGpuMgr->cachedMIGInfoLock); +} + +NV_STATUS +gpumgrCacheGetActiveDeviceIds_IMPL +( + NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS *pActiveDeviceIdsParams +) +{ + NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS probedGpuIds; + NV0000_CTRL_GPU_ACTIVE_DEVICE *pDevices = pActiveDeviceIdsParams->devices; + NvU32 *pNumDevices = &pActiveDeviceIdsParams->numDevices; + NvU32 total = 0; + NvU32 i; + + NV_ASSERT_OK_OR_RETURN(gpumgrGetProbedGpuIds(&probedGpuIds)); + + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); + NV_STATUS status = NV_OK; + + portSyncRwLockAcquireRead(pGpuMgr->cachedMIGInfoLock); + + // Walk probed gpus. + for (i = 0; + (i < NV0000_CTRL_GPU_MAX_PROBED_GPUS) && + (probedGpuIds.gpuIds[i] != NV0000_CTRL_GPU_INVALID_ID); i++) + { + NvU32 gpuId = probedGpuIds.gpuIds[i]; + NvBool bGpuHandled = NV_FALSE; + NvU32 gpuIdx; + + for (gpuIdx = 0; gpuIdx < NV_MAX_DEVICES; gpuIdx++) + { + NvU32 giIdx; + GPUMGR_CACHED_MIG_STATE *pMIGState = &pGpuMgr->cachedMIGInfo[gpuIdx]; + GPUMGR_CACHED_MIG_GPU_INSTANCE *pGpuInstances = pMIGState->gpuInstances; + + if (!pMIGState->bValid || (pMIGState->gpuId != gpuId)) + { + continue; + } + + // MIG not enabled, add device to list and carry on + if (!pMIGState->bMIGEnabled) + { + break; + } + + bGpuHandled = NV_TRUE; + + for (giIdx = 0; giIdx < GPUMGR_MAX_GPU_INSTANCES; giIdx++) + { + NvU32 ciIdx; + NvU32 swizzId = pGpuInstances[giIdx].swizzId; + NvBool *pbValidComputeInstances = + pGpuInstances[giIdx].bValidComputeInstances; + + if (!pGpuInstances[giIdx].bValid) + continue; + + for (ciIdx = 0; ciIdx < GPUMGR_MAX_COMPUTE_INSTANCES; ciIdx++) + { + if (pbValidComputeInstances[ciIdx]) + { + NV_ASSERT_OR_ELSE(total < NV0000_CTRL_GPU_MAX_ACTIVE_DEVICES, + status = NV_ERR_INVALID_STATE; goto done; ); + + pDevices[total].gpuId = gpuId; + pDevices[total].gpuInstanceId = swizzId; + pDevices[total].computeInstanceId = ciIdx; + total++; + } + } + } + } + + // Not in MIG mode, or we never had it in cache. + if (!bGpuHandled) + { + NV_ASSERT_OR_ELSE(total < NV0000_CTRL_GPU_MAX_ACTIVE_DEVICES, + status = NV_ERR_INVALID_STATE; goto done; ); + + pDevices[total].gpuId = gpuId; + pDevices[total].gpuInstanceId = NV0000_CTRL_GPU_INVALID_ID; + pDevices[total].computeInstanceId = NV0000_CTRL_GPU_INVALID_ID; + total++; + } + } + + *pNumDevices = total; + +done: + portSyncRwLockReleaseRead(pGpuMgr->cachedMIGInfoLock); + + return status; +} + /** * @brief Saves a pointer to the current GPU instance in thread local storage, * to be logged by NVLOG, until gpumgrSetGpuRelease is called. diff --git a/src/nvidia/src/kernel/mem_mgr/console_mem.c b/src/nvidia/src/kernel/mem_mgr/console_mem.c index 59c424ebb7..7eb4926023 100644 --- a/src/nvidia/src/kernel/mem_mgr/console_mem.c +++ b/src/nvidia/src/kernel/mem_mgr/console_mem.c @@ -40,12 +40,10 @@ conmemConstruct_IMPL ) { NV_STATUS status = NV_OK; - NvHandle hClient = pCallContext->pClient->hClient; Memory *pMemory = staticCast(pConsoleMemory, Memory); OBJGPU *pGpu = pMemory->pGpu; MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); MEMORY_DESCRIPTOR *pMemDesc = memmgrGetReservedConsoleMemDesc(pGpu, pMemoryManager); - RS_PRIV_LEVEL privLevel = pCallContext->secInfo.privLevel; NV_ASSERT_OR_RETURN(RMCFG_FEATURE_KERNEL_RM, NV_ERR_NOT_SUPPORTED); @@ -53,11 +51,6 @@ conmemConstruct_IMPL if (RS_IS_COPY_CTOR(pParams)) return NV_OK; - if (!(rmclientIsAdminByHandle(hClient, privLevel) || hypervisorCheckForObjectAccess(hClient))) - { - return NV_ERR_INVALID_CLASS; - } - if (pMemDesc == NULL) { return NV_ERR_INVALID_ARGUMENT; diff --git a/src/nvidia/src/kernel/mem_mgr/ctx_buf_pool.c b/src/nvidia/src/kernel/mem_mgr/ctx_buf_pool.c index e163a0fc67..9dab575bfa 100644 --- a/src/nvidia/src/kernel/mem_mgr/ctx_buf_pool.c +++ b/src/nvidia/src/kernel/mem_mgr/ctx_buf_pool.c @@ -72,7 +72,9 @@ ctxBufPoolIsSupported } // TODO remove when bug ID 3922001 for ap_sim_compute_uvm test case resolved - if (!IS_SILICON(pGpu)) + if (!IS_SILICON(pGpu) && + memmgrBug3922001DisableCtxBufOnSim(pGpu, pMemoryManager) && + gpuIsSelfHosted(pGpu)) { NV_PRINTF(LEVEL_INFO, "Ctx buffers not supported on simulation/emulation\n"); return NV_FALSE; @@ -509,7 +511,7 @@ ctxBufPoolFree NV_ASSERT_OK_OR_RETURN( memmgrMemSet(pMemoryManager, &surf, 0, - pMemDesc->PageCount * RM_PAGE_SIZE, + pMemDesc->Size, TRANSFER_FLAGS_NONE)); } rmMemPoolFree(pPool, (RM_POOL_ALLOC_MEMDESC*)pMemDesc, 0); diff --git a/src/nvidia/src/kernel/mem_mgr/egm_mem.c b/src/nvidia/src/kernel/mem_mgr/egm_mem.c index b0342665cb..8b0d52a14e 100644 --- a/src/nvidia/src/kernel/mem_mgr/egm_mem.c +++ b/src/nvidia/src/kernel/mem_mgr/egm_mem.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -171,7 +171,9 @@ egmmemConstruct_IMPL memdescSetGpuCacheAttrib(pMemDesc, gpuCacheAttrib); - NV_ASSERT_OK_OR_GOTO(rmStatus, memdescAlloc(pMemDesc), mem_construct_failed); + memdescTagAlloc(rmStatus, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_45, + pMemDesc); + NV_ASSERT_OK_OR_GOTO(rmStatus, rmStatus, mem_construct_failed); NV_ASSERT_OK_OR_GOTO(rmStatus, memConstructCommon(pMemory, pAllocRequest->classNum, diff --git a/src/nvidia/src/kernel/mem_mgr/fabric_vaspace.c b/src/nvidia/src/kernel/mem_mgr/fabric_vaspace.c index 8d96ae9d45..faa76f99e1 100644 --- a/src/nvidia/src/kernel/mem_mgr/fabric_vaspace.c +++ b/src/nvidia/src/kernel/mem_mgr/fabric_vaspace.c @@ -508,8 +508,7 @@ fabricvaspaceFree_IMPL NV_ASSERT(vaspaceFreeV2(pFabricVAS->pGVAS, vAddr, &blockSize) == NV_OK); kbusFlush_HAL(pGpu, pKernelBus, (BUS_FLUSH_VIDEO_MEMORY | - BUS_FLUSH_SYSTEM_MEMORY | - BUS_FLUSH_USE_PCIE_READ)); + BUS_FLUSH_SYSTEM_MEMORY)); fabricvaspaceInvalidateTlb(pFabricVAS, pGpu, PTE_DOWNGRADE); @@ -645,8 +644,7 @@ fabricvaspaceBatchFree_IMPL } kbusFlush_HAL(pGpu, pKernelBus, (BUS_FLUSH_VIDEO_MEMORY | - BUS_FLUSH_SYSTEM_MEMORY | - BUS_FLUSH_USE_PCIE_READ)); + BUS_FLUSH_SYSTEM_MEMORY)); fabricvaspaceInvalidateTlb(pFabricVAS, pGpu, PTE_DOWNGRADE); @@ -1061,6 +1059,7 @@ fabricvaspaceMapPhysMemdesc_IMPL NvU32 numRegions; MEMORY_DESCRIPTOR *pTempMemdesc; NvU32 aperture; + NvU32 peerNumber = BUS_INVALID_PEER; NV_ASSERT_OR_RETURN(pFabricMemDesc != NULL, NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN(pPhysMemDesc != NULL, NV_ERR_INVALID_ARGUMENT); @@ -1093,6 +1092,16 @@ fabricvaspaceMapPhysMemdesc_IMPL { aperture = NV_MMU_PTE_APERTURE_VIDEO_MEMORY; } + else if (memdescIsEgm(pPhysMemDesc)) + { + aperture = NV_MMU_PTE_APERTURE_PEER_MEMORY; + // + // Make sure that we receive a mapping request for EGM memory + // only if local EGM is enabled. + // + NV_ASSERT_OR_RETURN(pMemoryManager->bLocalEgmEnabled, NV_ERR_INVALID_STATE); + peerNumber = pMemoryManager->localEgmPeerId; + } else if (memdescGetAddressSpace(pPhysMemDesc) == ADDR_SYSMEM) { if (memdescGetCpuCacheAttrib(pPhysMemDesc) == NV_MEMORY_CACHED) @@ -1175,7 +1184,7 @@ fabricvaspaceMapPhysMemdesc_IMPL mapFlags, &pageArray, 0, &comprInfo, 0, NV_MMU_PTE_VALID_TRUE, aperture, - BUS_INVALID_PEER, NVLINK_INVALID_FABRIC_ADDR, + peerNumber, NVLINK_INVALID_FABRIC_ADDR, DMA_DEFER_TLB_INVALIDATE, NV_FALSE, memdescGetPageSize(pTempMemdesc, AT_GPU)); diff --git a/src/nvidia/src/kernel/mem_mgr/gpu_vaspace.c b/src/nvidia/src/kernel/mem_mgr/gpu_vaspace.c index a8145cac95..0d42361fe4 100644 --- a/src/nvidia/src/kernel/mem_mgr/gpu_vaspace.c +++ b/src/nvidia/src/kernel/mem_mgr/gpu_vaspace.c @@ -1613,8 +1613,7 @@ gvaspaceAlloc_IMPL // Invalidate TLB to apply new sparse state. kbusFlush_HAL(pGpu, pKernelBus, BUS_FLUSH_VIDEO_MEMORY | - BUS_FLUSH_SYSTEM_MEMORY | - BUS_FLUSH_USE_PCIE_READ); + BUS_FLUSH_SYSTEM_MEMORY); gvaspaceInvalidateTlb(pGVAS, pGpu, PTE_UPGRADE); } FOR_EACH_GPU_IN_MASK_UC_END @@ -1641,8 +1640,7 @@ gvaspaceAlloc_IMPL gvaspaceWalkUserCtxRelease(pGVAS, &userCtx); // Invalidate TLB to apply new sparse state. kbusFlush_HAL(pGpu, pKernelBus, BUS_FLUSH_VIDEO_MEMORY | - BUS_FLUSH_SYSTEM_MEMORY | - BUS_FLUSH_USE_PCIE_READ); + BUS_FLUSH_SYSTEM_MEMORY); gvaspaceInvalidateTlb(pGVAS, pGpu, PTE_UPGRADE); } FOR_EACH_GPU_IN_MASK_UC_END @@ -1780,8 +1778,7 @@ _gvaspaceInternalFree { KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); kbusFlush_HAL(pGpu, pKernelBus, BUS_FLUSH_VIDEO_MEMORY | - BUS_FLUSH_SYSTEM_MEMORY | - BUS_FLUSH_USE_PCIE_READ); + BUS_FLUSH_SYSTEM_MEMORY); } FOR_EACH_GPU_IN_MASK_UC_END } @@ -1836,8 +1833,7 @@ _gvaspaceInternalFree { KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); kbusFlush_HAL(pGpu, pKernelBus, BUS_FLUSH_VIDEO_MEMORY | - BUS_FLUSH_SYSTEM_MEMORY | - BUS_FLUSH_USE_PCIE_READ); + BUS_FLUSH_SYSTEM_MEMORY); gvaspaceInvalidateTlb(pGVAS, pGpu, PTE_DOWNGRADE); } FOR_EACH_GPU_IN_MASK_UC_END @@ -3403,7 +3399,7 @@ gvaspaceResize_IMPL } else { - vaLimitNew = pParams->vaSpaceSize - 1; + vaLimitNew = pVAS->vasStart + pParams->vaSpaceSize - 1; } // Abort early if not changing the size. @@ -4026,6 +4022,7 @@ gvaspaceGetPageLevelInfo_IMPL NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_STATE); } + pParams->levels[level].entryIndex = mmuFmtVirtAddrToEntryIndex(pLevelFmt, pParams->virtAddress); pLevelFmt = mmuFmtGetNextLevel(pLevelFmt, pTargetFmt); } @@ -4233,9 +4230,12 @@ vaspaceapiCtrlCmdVaspaceGetPageLevelInfo_IMPL OBJGVASPACE *pGVAS = NULL; OBJGPU *pGpu = NULL; + NV_ASSERT_OR_RETURN(pPageLevelInfoParams->flags <= + NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_FLAG_BAR1, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OK_OR_RETURN( - _gvaspaceControl_Prolog(pVaspaceApi, pPageLevelInfoParams->hSubDevice, - pPageLevelInfoParams->subDeviceId, &pGVAS, &pGpu)); + _gvaspaceControl_Prolog(pVaspaceApi, pPageLevelInfoParams->hSubDevice, + pPageLevelInfoParams->subDeviceId, &pGVAS, &pGpu)); if (NULL == pGVAS->pGpuStates) { @@ -4262,6 +4262,21 @@ vaspaceapiCtrlCmdVaspaceGetPageLevelInfo_IMPL } } + if (pPageLevelInfoParams->flags & NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_FLAG_BAR1) + { + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + RsCpuMapping *pCpuMapping = NULL; + NvU64 offset; + // switch the vaspace API pointer to bar1 ptr + pGVAS = dynamicCast(kbusGetBar1VASpace_HAL(pGpu, pKernelBus), OBJGVASPACE); + NV_ASSERT_OR_RETURN(pGVAS != NULL, NV_ERR_INVALID_ARGUMENT); + pCpuMapping = CliFindMappingInClient(RES_GET_CLIENT_HANDLE(pVaspaceApi), + RES_GET_PARENT_HANDLE(pVaspaceApi), + (NvP64)pPageLevelInfoParams->virtAddress); + offset = pPageLevelInfoParams->virtAddress - (NvU64)pCpuMapping->pLinearAddress; + pPageLevelInfoParams->virtAddress = pCpuMapping->pPrivate->gpuAddress + offset; + } + return gvaspaceGetPageLevelInfo(pGVAS, pGpu, pPageLevelInfoParams); } @@ -4515,6 +4530,33 @@ gvaspaceCopyServerReservedPdes_IMPL return status; } +NV_STATUS +vaspaceapiCtrlCmdVaspaceGetHostRmManagedSize_IMPL +( + VaSpaceApi *pVaspaceApi, + NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS *pVaspaceGetHostRmManagedSizeParams +) +{ + OBJGVASPACE *pGVAS = NULL; + OBJGPU *pGpu = NULL; + + NV_ASSERT_OK_OR_RETURN( + _gvaspaceControl_Prolog(pVaspaceApi, pVaspaceGetHostRmManagedSizeParams->hSubDevice, + pVaspaceGetHostRmManagedSizeParams->subDeviceId, &pGVAS, &pGpu)); + + // If GSP or guest-managed VA space are enabled, then RM requires extra VA range + if (IS_GSP_CLIENT(pGpu) || IS_VIRTUAL_WITH_FULL_SRIOV(pGpu)) + { + pVaspaceGetHostRmManagedSizeParams->requiredVaRange = VA_SIZE_FULL_SRIOV_OR_GSP; + } + else + { + pVaspaceGetHostRmManagedSizeParams->requiredVaRange = 0; + } + + return NV_OK; +} + /********************Local routines used in this file alone*******************/ /*! @@ -5156,7 +5198,7 @@ gvaspaceReserveMempool_IMPL ( OBJGVASPACE *pGVAS, OBJGPU *pGpu, - NvHandle hClient, + Device *pDevice, NvU64 size, NvU64 pageSizeLockMask, NvU32 flags @@ -5209,7 +5251,7 @@ gvaspaceReserveMempool_IMPL kgmmuGetSizeOfPageTables(pGpu, pKernelGmmu, pFmt, 0, size - 1, pageSizeLockMask); - NV_ASSERT_OK_OR_RETURN(memmgrPageLevelPoolsGetInfo(pGpu, pMemoryManager, hClient, &pMemPool)); + NV_ASSERT_OK_OR_RETURN(memmgrPageLevelPoolsGetInfo(pGpu, pMemoryManager, pDevice, &pMemPool)); status = rmMemPoolReserve(pMemPool, poolSize, pGVAS->flags); if ((pGVAS->flags & VASPACE_FLAGS_RETRY_PTE_ALLOC_IN_SYS) && (status == NV_ERR_NO_MEMORY)) diff --git a/src/nvidia/src/kernel/mem_mgr/mem.c b/src/nvidia/src/kernel/mem_mgr/mem.c index 6c6af7be96..7a2decd3c8 100644 --- a/src/nvidia/src/kernel/mem_mgr/mem.c +++ b/src/nvidia/src/kernel/mem_mgr/mem.c @@ -337,6 +337,9 @@ memConstructCommon_IMPL { OBJGPU *pGpu = NULL; NV_STATUS status = NV_OK; + NvHandle hClient = RES_GET_CLIENT_HANDLE(pMemory); + NvHandle hParent = RES_GET_PARENT_HANDLE(pMemory); + NvHandle hMemory = RES_GET_HANDLE(pMemory); if (pMemDesc == NULL) return NV_ERR_INVALID_ARGUMENT; @@ -472,6 +475,14 @@ memConstructCommon_IMPL if (status != NV_OK) goto done; + // Make GSP-RM aware of the memory descriptor so it can be used there + if (FLD_TEST_DRF(OS32, _ATTR2, _REGISTER_MEMDESC_TO_PHYS_RM, _TRUE, attr2)) + { + status = memdescRegisterToGSP(pGpu, hClient, hParent, hMemory); + if (status != NV_OK) + goto done; + } + // Initialize the circular list item for tracking dup/sharing of pMemDesc pMemory->dupListItem.pNext = pMemory->dupListItem.pPrev = pMemory; @@ -589,6 +600,8 @@ _memDestructCommonWithDevice pFbAllocInfo->hwResId = memdescGetHwResId(pMemory->pMemDesc); pFbAllocInfo->size = pMemory->Length; pFbAllocInfo->format = memdescGetPteKind(pMemory->pMemDesc); + pFbAllocInfo->hClient = pRsClient->hClient; + pFbAllocInfo->hDevice = hDevice; // // Note that while freeing duped memory under a device, the @@ -765,8 +778,16 @@ memControl_IMPL if (REF_VAL(NVXXXX_CTRL_CMD_CLASS, pParams->cmd) == NV04_MEMORY) { - if (pMemory->categoryClassId == NV01_MEMORY_SYSTEM_OS_DESCRIPTOR) + // + // Tegra SOC import memory usecase uses NV01_MEMORY_SYSTEM_OS_DESCRIPTOR class for + // RM resource server registration of memory, RM can return the physical memory attributes + // for these imported buffers. + // + if ((pMemory->categoryClassId == NV01_MEMORY_SYSTEM_OS_DESCRIPTOR) && + (pParams->cmd != NV0041_CTRL_CMD_GET_SURFACE_PHYS_ATTR)) + { return NV_ERR_NOT_SUPPORTED; + } } pRmCtrlParams->pGpu = pMemory->pGpu; @@ -833,7 +854,7 @@ memCopyConstruct_IMPL if (!!pSrcSubDevice != !!pDstSubDevice) { - NV_PRINTF(LEVEL_ERROR, "Parent type mismatch between Src and Dst objects" + NV_PRINTF(LEVEL_INFO, "Parent type mismatch between Src and Dst objects" "Both should be either device or subDevice\n"); return NV_ERR_INVALID_OBJECT_PARENT; } diff --git a/src/nvidia/src/kernel/mem_mgr/mem_fabric.c b/src/nvidia/src/kernel/mem_mgr/mem_fabric.c index 848ab24493..f2844a37ff 100644 --- a/src/nvidia/src/kernel/mem_mgr/mem_fabric.c +++ b/src/nvidia/src/kernel/mem_mgr/mem_fabric.c @@ -52,6 +52,7 @@ #include "gpu/bus/kern_bus.h" #include "gpu/bus/p2p_api.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" +#include "kernel/gpu/gpu_fabric_probe.h" #include "ctrl/ctrl0041.h" static NvU32 @@ -940,15 +941,51 @@ memoryfabricCtrlCmdDescribe_IMPL NV00F8_CTRL_DESCRIBE_PARAMS *pParams ) { + NV_STATUS status; Memory *pMemory = staticCast(pMemoryFabric, Memory); NvU64 *pFabricArray; NvU64 offset; NvU64 pageSize; NvU32 i; + CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + NvHandle hClient = pCallContext->pClient->hClient; + FABRIC_MEMDESC_DATA *pMemdescData; + OBJGPU *pGpu; + + if ( + !rmclientIsAdminByHandle(hClient, pCallContext->secInfo.privLevel)) + { + return NV_ERR_INSUFFICIENT_PERMISSIONS; + } if (pMemory->pMemDesc == NULL) return NV_ERR_INVALID_ARGUMENT; + pGpu = pMemory->pMemDesc->pGpu; + pMemdescData = (FABRIC_MEMDESC_DATA *)memdescGetMemData(pMemory->pMemDesc); + + pParams->memFlags = pMemdescData->allocFlags; + pParams->physAttrs = pMemdescData->physAttrs; + + pParams->attrs.pageSize = memdescGetPageSize(pMemory->pMemDesc, AT_GPU); + pParams->attrs.kind = memdescGetPteKind(pMemory->pMemDesc); + pParams->attrs.size = memdescGetSize(pMemory->pMemDesc); + + if (gpuFabricProbeIsSupported(pGpu)) + { + status = gpuFabricProbeGetFabricCliqueId(pGpu->pGpuFabricProbeInfoKernel, + &pParams->attrs.cliqueId); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "unable to query cliqueId 0x%x\n", status); + return status; + } + } + else + { + pParams->attrs.cliqueId = 0; + } + pageSize = memdescGetPageSize(pMemory->pMemDesc, AT_GPU); if (memdescGetContiguity(pMemory->pMemDesc, AT_GPU)) @@ -958,7 +995,7 @@ memoryfabricCtrlCmdDescribe_IMPL if (pParams->offset >= pParams->totalPfns) { - NV_PRINTF(LEVEL_ERROR, "offset: %llx is out of range: %llx \n", + NV_PRINTF(LEVEL_ERROR, "offset: 0x%llx is out of range: 0x%llx\n", pParams->offset, pParams->totalPfns); return NV_ERR_OUT_OF_RANGE; } @@ -972,9 +1009,8 @@ memoryfabricCtrlCmdDescribe_IMPL return NV_ERR_NO_MEMORY; offset = pParams->offset * pageSize; - memdescGetPhysAddrsForGpu(pMemory->pMemDesc, pMemory->pMemDesc->pGpu, - AT_GPU, offset, pageSize, pParams->numPfns, - pFabricArray); + memdescGetPhysAddrsForGpu(pMemory->pMemDesc, pGpu, AT_GPU, offset, + pageSize, pParams->numPfns, pFabricArray); for (i = 0; i < pParams->numPfns; i++) { diff --git a/src/nvidia/src/kernel/mem_mgr/mem_list.c b/src/nvidia/src/kernel/mem_mgr/mem_list.c index 03a73fbd9a..83ea04975f 100644 --- a/src/nvidia/src/kernel/mem_mgr/mem_list.c +++ b/src/nvidia/src/kernel/mem_mgr/mem_list.c @@ -50,15 +50,6 @@ memlistConstruct_IMPL RS_RES_ALLOC_PARAMS_INTERNAL *pParams ) { -#define CLEAR_HAL_ATTR(a) \ - a = (a & ~(DRF_SHIFTMASK(NVOS32_ATTR_COMPR) | \ - DRF_SHIFTMASK(NVOS32_ATTR_TILED) | \ - DRF_SHIFTMASK(NVOS32_ATTR_ZCULL))); - -#define CLEAR_HAL_ATTR2(a) \ - a = (a & ~(DRF_SHIFTMASK(NVOS32_ATTR2_ZBC) | \ - DRF_SHIFTMASK(NVOS32_ATTR2_GPU_CACHEABLE))); - NV_MEMORY_LIST_ALLOCATION_PARAMS *pAllocParams; RsResourceRef *pResourceRef = pCallContext->pResourceRef; NvHandle hClient = pCallContext->pClient->hClient; @@ -110,22 +101,6 @@ memlistConstruct_IMPL } continue_alloc_object: - // - // These classes are used by the vGPU support to create memory objects for memory - // assigned to a guest VM. The NV01_MEMORY_LIST_OBJECT case creates an object - // whose pages are based on another object's pages. - // - if ((externalClassId == NV01_MEMORY_LIST_FBMEM) || (externalClassId == NV01_MEMORY_LIST_OBJECT)) - { - if (!(rmclientIsAdminByHandle(hClient, privLevel) || hypervisorCheckForObjectAccess(hClient))) - return NV_ERR_INSUFFICIENT_PERMISSIONS; - } - else - { - if (!rmclientIsAdminByHandle(hClient, privLevel)) - return NV_ERR_INSUFFICIENT_PERMISSIONS; - } - if (DRF_VAL(OS02, _FLAGS, _COHERENCY, pAllocParams->flagsOs02) == NVOS02_FLAGS_COHERENCY_UNCACHED) Cache = NV_MEMORY_UNCACHED; else if (DRF_VAL(OS02, _FLAGS, _COHERENCY, pAllocParams->flagsOs02) == NVOS02_FLAGS_COHERENCY_CACHED) @@ -370,7 +345,8 @@ memlistConstruct_IMPL // this will fake a memory allocation at // the OS driver interface level - and also set pMemDesc->Allocated - status = memdescAlloc(pMemDesc); + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_46, + pMemDesc); if (status != NV_OK) { @@ -435,6 +411,7 @@ memlistConstruct_IMPL pHeap = vidmemGetHeap(pGpu, dynamicCast(pDeviceRef->pResource, Device), + NV_FALSE, NV_FALSE); // @@ -780,6 +757,8 @@ memlistConstruct_IMPL pFbAllocInfo->pageFormat->type = pAllocParams->type; pFbAllocInfo->hwResId = hwResId; pFbAllocInfo->size = memSize; + pFbAllocInfo->hClient = hClient; + pFbAllocInfo->hDevice = hParent; memmgrFreeHwResources(pGpu, pMemoryManager, pFbAllocInfo); } diff --git a/src/nvidia/src/kernel/mem_mgr/mem_multicast_fabric.c b/src/nvidia/src/kernel/mem_mgr/mem_multicast_fabric.c index e9969c37a9..ce602cf394 100644 --- a/src/nvidia/src/kernel/mem_mgr/mem_multicast_fabric.c +++ b/src/nvidia/src/kernel/mem_mgr/mem_multicast_fabric.c @@ -27,6 +27,8 @@ * This file contains the functions managing the memory multicast fabric * *****************************************************************************/ +#define NVOC_MEM_MULTICAST_FABRIC_H_PRIVATE_ACCESS_ALLOWED + #include "os/os.h" #include "core/locks.h" #include "nvport/nvport.h" @@ -45,6 +47,111 @@ #include "gpu/gpu_fabric_probe.h" +typedef struct mem_multicast_fabric_attach_mem_info_node +{ + MEMORY_DESCRIPTOR *pPhysMemDesc; + NvHandle hDupedPhysMem; + NvU64 physMapLength; + NODE node; +} MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO_NODE; + +typedef struct mem_multicast_fabric_client_info +{ + void *pOsEvent; + Memory *pMemory; +} MEM_MULTICAST_FABRIC_CLIENT_INFO; + +typedef struct mem_multicast_fabric_gpu_info +{ + void *pGpuOsInfo; + OBJGPU *pGpu; + NvU64 gpuProbeHandle; + NvU32 cliqueId; + NvBool bMcflaAlloc; + + // Tracks memory attached using NV00FD_CTRL_CMD_ATTACH_MEM + PNODE pAttachMemInfoTree; +} MEM_MULTICAST_FABRIC_GPU_INFO; + +MAKE_LIST(MemMulticastFabricClientInfoList, MEM_MULTICAST_FABRIC_CLIENT_INFO); + +MAKE_LIST(MemMulticastFabricGpuInfoList, MEM_MULTICAST_FABRIC_GPU_INFO); + +typedef enum +{ + MEM_MULTICAST_FABRIC_TEAM_SETUP_REQUEST = 0, + MEM_MULTICAST_FABRIC_TEAM_RELEASE_REQUEST, +} MEM_MULTICAST_FABRIC_REQUEST_TYPE; + +typedef struct mem_multicast_fabric_descriptor +{ + // Refcount to keep this descriptor alive + NvU64 refCount; + + // List of clients waiting on this object to be ready + MemMulticastFabricClientInfoList waitingClientsList; + + // Mask representing the list of attached GPUs + NvU32 localAttachedGpusMask; + + // List of attached GPU info + MemMulticastFabricGpuInfoList gpuInfoList; + + // Boolean to be set when pMemDesc is installed + NvBool bMemdescInstalled; + + // Memory descriptor associated with the multicast object + MEMORY_DESCRIPTOR *pMemDesc; + + // Unique handle assigned for the multicast team by FM + NvU64 mcTeamHandle; + + // Status of the multicast team + NV_STATUS mcTeamStatus; + + // + // Boolean to be set when an Inband request has been sent to FM + // and is currently in progress + // + NvBool bInbandReqInProgress; + + // + // Request Id associated with the Inband request in progress when + // bInbandReqSent is set to true + // + NvU64 inbandReqId; + + // Alignment for the multicast FLA allocation + NvU64 alignment; + + // Multicast FLA allocation size + NvU64 allocSize; + + // Page size for the multicast FLA + NvU64 pageSize; + + // Multicast FLA allocation flags + NvU32 allocFlags; + + // Max. number of unique GPUs associated with the multicast object + NvU32 numMaxGpus; + + // No. of unique GPUs currently attached to the multicast object + NvU32 numAttachedGpus; + +} MEM_MULTICAST_FABRIC_DESCRIPTOR; + +static NvBool +_memMulticastFabricIsPrime +( + NvU32 allocFlags +) +{ + NvBool bPrime = NV_TRUE; + + return bPrime; +} + static NV_STATUS _memMulticastFabricValidateAllocParams @@ -52,20 +159,23 @@ _memMulticastFabricValidateAllocParams NV00FD_ALLOCATION_PARAMETERS *pAllocParams ) { + // Nothing to verify in this case.. + if (!_memMulticastFabricIsPrime(pAllocParams->allocFlags)) + return NV_OK; + // Only page size 512MB is supported if (pAllocParams->pageSize != NV_MEMORY_MULTICAST_FABRIC_PAGE_SIZE_512M) { NV_PRINTF(LEVEL_ERROR, - "Unsupported pageSize: 0x%x. Only 512MB pagesize is supported\n", - pAllocParams->pageSize); + "Unsupported pageSize: 0x%x. Only 512MB pagesize is supported\n", + pAllocParams->pageSize); return NV_ERR_INVALID_ARGUMENT; } - // Alignment should be pageSize aligned - if (!NV_IS_ALIGNED64(pAllocParams->alignment, pAllocParams->pageSize)) + if (pAllocParams->alignment != pAllocParams->pageSize) { NV_PRINTF(LEVEL_ERROR, - "Alignment should be pageSize aligned\n"); + "Alignment must be pageSize for now\n"); return NV_ERR_INVALID_ARGUMENT; } @@ -77,17 +187,11 @@ _memMulticastFabricValidateAllocParams return NV_ERR_INVALID_ARGUMENT; } - if (pAllocParams->numGpus == 0) - { - NV_PRINTF(LEVEL_ERROR, - "Number of GPUs to attach must be non-zero\n"); - return NV_ERR_INVALID_ARGUMENT; - } - - // Allocation flags must be zero - if (pAllocParams->allocFlags != 0) + // NV_U32_MAX is reserved as a special value for non-prime MCFLA objects. + if ((pAllocParams->numGpus == 0) || + (pAllocParams->numGpus == NV_U32_MAX)) { - NV_PRINTF(LEVEL_ERROR, "allocFlags must be zero\n"); + NV_PRINTF(LEVEL_ERROR, "Invalid number of GPUs to attach\n"); return NV_ERR_INVALID_ARGUMENT; } @@ -104,11 +208,13 @@ _memMulticastFabricDescriptorAllocUnderLock { MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc; - pMulticastFabricDesc = portMemAllocNonPaged(sizeof(MEM_MULTICAST_FABRIC_DESCRIPTOR)); + pMulticastFabricDesc = portMemAllocNonPaged( + sizeof(MEM_MULTICAST_FABRIC_DESCRIPTOR)); if (pMulticastFabricDesc == NULL) return NULL; - portMemSet(pMulticastFabricDesc, 0, sizeof(MEM_MULTICAST_FABRIC_DESCRIPTOR)); + portMemSet(pMulticastFabricDesc, 0, + sizeof(MEM_MULTICAST_FABRIC_DESCRIPTOR)); listInit(&pMulticastFabricDesc->waitingClientsList, portMemAllocatorGetGlobalNonPaged()); @@ -118,12 +224,13 @@ _memMulticastFabricDescriptorAllocUnderLock pMulticastFabricDesc->refCount = 1; pMulticastFabricDesc->mcTeamStatus = NV_ERR_NOT_READY; - pMulticastFabricDesc->attachedGpusMask = 0; + pMulticastFabricDesc->localAttachedGpusMask = 0; pMulticastFabricDesc->alignment = pAllocParams->alignment; pMulticastFabricDesc->allocSize = pAllocParams->allocSize; pMulticastFabricDesc->pageSize = pAllocParams->pageSize; pMulticastFabricDesc->allocFlags = pAllocParams->allocFlags; pMulticastFabricDesc->numMaxGpus = pAllocParams->numGpus; + pMulticastFabricDesc->inbandReqId = osGetTimestamp(); return pMulticastFabricDesc; } @@ -136,7 +243,8 @@ _memMulticastFabricDescriptorFlushClientsUnderLock { MEM_MULTICAST_FABRIC_CLIENT_INFO *pNode; - while ((pNode = listHead(&pMulticastFabricDesc->waitingClientsList)) != NULL) + while ((pNode = + listHead(&pMulticastFabricDesc->waitingClientsList)) != NULL) { if (pNode->pOsEvent != NULL) { @@ -165,7 +273,8 @@ _memMulticastFabricDescriptorEnqueueWaitUnderLock if (pOsEvent != NULL) { - status = osUserHandleToKernelPtr(hClient, pOsEvent, &pValidatedOsEvent); + status = osUserHandleToKernelPtr(hClient, pOsEvent, + &pValidatedOsEvent); if (status != NV_OK) return status; } @@ -182,9 +291,15 @@ _memMulticastFabricDescriptorEnqueueWaitUnderLock pNode->pOsEvent = pValidatedOsEvent; pNode->pMemory = pMemory; - // In case the multicast object's memdesc is ready, unblock clients waiting on it + // + // In case the multicast object's memdesc is ready, unblock + // clients waiting on it + // if (pMulticastFabricDesc->bMemdescInstalled) - _memMulticastFabricDescriptorFlushClientsUnderLock(pMulticastFabricDesc); + { + _memMulticastFabricDescriptorFlushClientsUnderLock( + pMulticastFabricDesc); + } return NV_OK; } @@ -250,7 +365,7 @@ _memMulticastFabricGpuInfoAddUnderLock { NV_PRINTF(LEVEL_ERROR, "GPU %x has already attached\n", pGpu->gpuInstance); - return NV_ERR_IN_USE; + return NV_ERR_INSERT_DUPLICATE_NAME; } } @@ -280,17 +395,103 @@ _memMulticastFabricGpuInfoRemoveUnderLock while ((pNode = listHead(&pMulticastFabricDesc->gpuInfoList)) != NULL) { + freeCallback.pCb = osReleaseGpuOsInfo; freeCallback.pCbData = (void *)pNode->pGpuOsInfo; - NV_ASSERT_OK(threadStateEnqueueCallbackOnFree(pThreadNode, &freeCallback)); + NV_ASSERT_OK(threadStateEnqueueCallbackOnFree(pThreadNode, + &freeCallback)); listRemove(&pMulticastFabricDesc->gpuInfoList, pNode); } - pMulticastFabricDesc->attachedGpusMask = 0; + pMulticastFabricDesc->localAttachedGpusMask = 0; pMulticastFabricDesc->numAttachedGpus = 0; } +NV_STATUS +_memMulticastFabricSendInbandTeamSetupRequestV2UnderLock +( + OBJGPU *pGpu, + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc +) +{ + NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS *sendDataParams; + nvlink_inband_mc_team_setup_req_v2_msg_t *pMcTeamSetupReqMsg = NULL; + nvlink_inband_mc_team_setup_req_v2_t *pMcTeamSetupReq = NULL; + MEM_MULTICAST_FABRIC_GPU_INFO *pNode; + NvU32 idx = 0; + NvU32 payloadSize; + NvU32 sendDataSize; + NV_STATUS status = NV_OK; + NvU16 numKeys = 1; + + sendDataParams = + (NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS *) + portMemAllocNonPaged(sizeof(NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS)); + + if (sendDataParams == NULL) + return NV_ERR_NO_MEMORY; + + pMcTeamSetupReqMsg = + (nvlink_inband_mc_team_setup_req_v2_msg_t *)&sendDataParams->buffer[0]; + + pMcTeamSetupReq = + (nvlink_inband_mc_team_setup_req_v2_t *)&pMcTeamSetupReqMsg->mcTeamSetupReq; + + payloadSize = (NvU32)(sizeof(nvlink_inband_mc_team_setup_req_v2_t) + + (sizeof(pMcTeamSetupReq->gpuHandlesAndKeys[0]) * + (pMulticastFabricDesc->numMaxGpus + numKeys))); + + sendDataSize = (NvU32)(sizeof(nvlink_inband_msg_header_t) + payloadSize); + + if ((NvU32)sendDataSize > sizeof(sendDataParams->buffer)) + { + NV_ASSERT(0); + status = NV_ERR_INSUFFICIENT_RESOURCES; + goto done; + } + + portMemSet(sendDataParams, 0, sendDataSize); + + pMcTeamSetupReq->mcAllocSize = pMulticastFabricDesc->allocSize; + pMcTeamSetupReq->numGpuHandles = pMulticastFabricDesc->numMaxGpus; + pMcTeamSetupReq->numKeys = numKeys; + + // Fill local GPUs + for (pNode = listHead(&pMulticastFabricDesc->gpuInfoList); + pNode != NULL; + pNode = listNext(&pMulticastFabricDesc->gpuInfoList, pNode)) + pMcTeamSetupReq->gpuHandlesAndKeys[idx++] = pNode->gpuProbeHandle; + + // Fill local key + pMcTeamSetupReq->gpuHandlesAndKeys[idx++] = pMulticastFabricDesc->inbandReqId; + + if (idx != (pMcTeamSetupReq->numGpuHandles + numKeys)) + { + NV_ASSERT(0); + status = NV_ERR_INVALID_STATE; + goto done; + } + + sendDataParams->dataSize = sendDataSize; + + nvlinkInitInbandMsgHdr(&pMcTeamSetupReqMsg->msgHdr, + NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_REQ_V2, + payloadSize, pMulticastFabricDesc->inbandReqId); + + status = knvlinkSendInbandData(pGpu, GPU_GET_KERNEL_NVLINK(pGpu), + sendDataParams); + if (status != NV_OK) + goto done; + + pMulticastFabricDesc->bInbandReqInProgress = NV_TRUE; + +done: + portMemFree(sendDataParams); + + return status; +} + NV_STATUS _memMulticastFabricSendInbandTeamSetupRequestV1UnderLock ( @@ -298,12 +499,10 @@ _memMulticastFabricSendInbandTeamSetupRequestV1UnderLock MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc ) { - Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS *sendDataParams; nvlink_inband_mc_team_setup_req_msg_t *pMcTeamSetupReqMsg = NULL; nvlink_inband_mc_team_setup_req_t *pMcTeamSetupReq = NULL; MEM_MULTICAST_FABRIC_GPU_INFO *pNode; - NvU64 requestId; NvU32 idx = 0; NvU32 payloadSize; NvU32 sendDataSize; @@ -323,7 +522,8 @@ _memMulticastFabricSendInbandTeamSetupRequestV1UnderLock (nvlink_inband_mc_team_setup_req_t *)&pMcTeamSetupReqMsg->mcTeamSetupReq; payloadSize = (NvU32)(sizeof(nvlink_inband_mc_team_setup_req_t) + \ - (sizeof(pMcTeamSetupReq->gpuHandles[0]) * pMulticastFabricDesc->numMaxGpus)); + (sizeof(pMcTeamSetupReq->gpuHandles[0]) * \ + pMulticastFabricDesc->numMaxGpus)); sendDataSize = (NvU32)(sizeof(nvlink_inband_msg_header_t) + payloadSize); @@ -343,30 +543,16 @@ _memMulticastFabricSendInbandTeamSetupRequestV1UnderLock sendDataParams->dataSize = sendDataSize; - status = fabricInitInbandMsgHdr(&pMcTeamSetupReqMsg->msgHdr, - NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_REQ, - payloadSize); - - if (status != NV_OK) - goto done; - - requestId = pMcTeamSetupReqMsg->msgHdr.requestId; + nvlinkInitInbandMsgHdr(&pMcTeamSetupReqMsg->msgHdr, + NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_REQ, + payloadSize, pMulticastFabricDesc->inbandReqId); - status = fabricMulticastSetupCacheInsertUnderLock_IMPL(pFabric, - requestId, - pMulticastFabricDesc); + status = knvlinkSendInbandData(pGpu, GPU_GET_KERNEL_NVLINK(pGpu), + sendDataParams); if (status != NV_OK) goto done; - status = knvlinkSendInbandData(pGpu, GPU_GET_KERNEL_NVLINK(pGpu), sendDataParams); - if (status != NV_OK) - { - fabricMulticastSetupCacheDeleteUnderLock_IMPL(pFabric, requestId); - goto done; - } - pMulticastFabricDesc->bInbandReqInProgress = NV_TRUE; - pMulticastFabricDesc->inbandReqId = requestId; done: portMemFree(sendDataParams); @@ -386,19 +572,19 @@ _memMulticastFabricSendInbandTeamReleaseRequestV1UnderLock nvlink_inband_mc_team_release_req_t *pMcTeamReleaseReq = NULL; NvU32 payloadSize; NvU32 sendDataSize; - NV_STATUS status = NV_OK; + NV_STATUS status; - sendDataParams = \ - (NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS *)portMemAllocNonPaged(sizeof(NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS)); + sendDataParams = (NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS *) + portMemAllocNonPaged(sizeof(NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS)); if (sendDataParams == NULL) return NV_ERR_NO_MEMORY; - pMcTeamReleaseReqMsg = \ - (nvlink_inband_mc_team_release_req_msg_t *)&sendDataParams->buffer[0]; + pMcTeamReleaseReqMsg = (nvlink_inband_mc_team_release_req_msg_t *) \ + &sendDataParams->buffer[0]; - pMcTeamReleaseReq = \ - (nvlink_inband_mc_team_release_req_t *)&pMcTeamReleaseReqMsg->mcTeamReleaseReq; + pMcTeamReleaseReq = (nvlink_inband_mc_team_release_req_t *) \ + &pMcTeamReleaseReqMsg->mcTeamReleaseReq; payloadSize = (NvU32)(sizeof(nvlink_inband_mc_team_release_req_t)); @@ -408,17 +594,15 @@ _memMulticastFabricSendInbandTeamReleaseRequestV1UnderLock pMcTeamReleaseReq->mcTeamHandle = mcTeamHandle; - status = fabricInitInbandMsgHdr(&pMcTeamReleaseReqMsg->msgHdr, - NVLINK_INBAND_MSG_TYPE_MC_TEAM_RELEASE_REQ, - payloadSize); - if (status != NV_OK) - goto done; + nvlinkInitInbandMsgHdr(&pMcTeamReleaseReqMsg->msgHdr, + NVLINK_INBAND_MSG_TYPE_MC_TEAM_RELEASE_REQ, + payloadSize, osGetTimestamp()); sendDataParams->dataSize = sendDataSize; - status = knvlinkSendInbandData(pGpu, GPU_GET_KERNEL_NVLINK(pGpu), sendDataParams); + status = knvlinkSendInbandData(pGpu, GPU_GET_KERNEL_NVLINK(pGpu), + sendDataParams); -done: portMemFree(sendDataParams); return status; @@ -434,15 +618,25 @@ _memMulticastFabricSendInbandTeamSetupRequestUnderlock NvU64 fmCaps; NV_STATUS status = NV_OK; - status = gpuFabricProbeGetfmCaps(pGpu->pGpuFabricProbeInfoKernel, &fmCaps); + status = gpuFabricProbeGetfmCaps(pGpu->pGpuFabricProbeInfoKernel, + &fmCaps); if (status != NV_OK) return status; - if (!(fmCaps & NVLINK_INBAND_FM_CAPS_MC_TEAM_SETUP_V1)) + if (fmCaps & NVLINK_INBAND_FM_CAPS_MC_TEAM_SETUP_V2) + { + return _memMulticastFabricSendInbandTeamSetupRequestV2UnderLock(pGpu, + pMulticastFabricDesc); + } + else if (fmCaps & NVLINK_INBAND_FM_CAPS_MC_TEAM_SETUP_V1) + { + return _memMulticastFabricSendInbandTeamSetupRequestV1UnderLock(pGpu, + pMulticastFabricDesc); + } + else + { return NV_ERR_NOT_SUPPORTED; - - return _memMulticastFabricSendInbandTeamSetupRequestV1UnderLock(pGpu, - pMulticastFabricDesc); + } } NV_STATUS @@ -455,7 +649,12 @@ _memMulticastFabricSendInbandTeamReleaseRequestUnderLock NvU64 fmCaps; NV_STATUS status = NV_OK; - status = gpuFabricProbeGetfmCaps(pGpu->pGpuFabricProbeInfoKernel, &fmCaps); + // If mcTeamHandle is zero, nothing to do... + if (mcTeamHandle == 0) + return NV_OK; + + status = gpuFabricProbeGetfmCaps(pGpu->pGpuFabricProbeInfoKernel, + &fmCaps); if (status != NV_OK) return status; @@ -463,7 +662,7 @@ _memMulticastFabricSendInbandTeamReleaseRequestUnderLock return NV_ERR_NOT_SUPPORTED; return _memMulticastFabricSendInbandTeamReleaseRequestV1UnderLock(pGpu, - mcTeamHandle); + mcTeamHandle); } NV_STATUS @@ -480,15 +679,22 @@ _memMulticastFabricSendInbandRequestUnderLock if (pGpu == NULL) pGpu = listHead(&pMulticastFabricDesc->gpuInfoList)->pGpu; + // If nothing is attached locally... + if (pGpu == NULL) + { + NV_PRINTF(LEVEL_ERROR, "No locally attached GPU found\n"); + return NV_ERR_INVALID_STATE; + } + switch (requestType) { case MEM_MULTICAST_FABRIC_TEAM_SETUP_REQUEST: status = _memMulticastFabricSendInbandTeamSetupRequestUnderlock(pGpu, - pMulticastFabricDesc); + pMulticastFabricDesc); break; case MEM_MULTICAST_FABRIC_TEAM_RELEASE_REQUEST: status = _memMulticastFabricSendInbandTeamReleaseRequestUnderLock(pGpu, - pMulticastFabricDesc->mcTeamHandle); + pMulticastFabricDesc->mcTeamHandle); break; default: status = NV_ERR_NOT_SUPPORTED; @@ -551,7 +757,8 @@ _memorymulticastfabricBatchDetachMem btreeEnumStart(0, &pMemNode, pGpuNode->pAttachMemInfoTree); while (pMemNode != NULL) { - _memorymulticastfabricDetachMem(pFabricVAS, pFabricMemDesc, pMemNode); + _memorymulticastfabricDetachMem(pFabricVAS, pFabricMemDesc, + pMemNode); btreeUnlink(pMemNode, &pGpuNode->pAttachMemInfoTree); portMemFree(pMemNode->Data); @@ -575,65 +782,79 @@ _memMulticastFabricDescriptorFreeUnderLock MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc ) { + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + NvU32 allocFlags; + if (pMulticastFabricDesc == NULL) return; pMulticastFabricDesc->refCount--; - if (pMulticastFabricDesc->refCount == 0) + if (pMulticastFabricDesc->refCount != 0) + return; + + allocFlags = pMulticastFabricDesc->allocFlags; + + if (pMulticastFabricDesc->pMemDesc != NULL) { - if (pMulticastFabricDesc->pMemDesc != NULL) - { - NV_ASSERT(pMulticastFabricDesc->bMemdescInstalled); + NV_ASSERT(pMulticastFabricDesc->bMemdescInstalled); - _memorymulticastfabricBatchDetachMem(pMulticastFabricDesc); + _memorymulticastfabricBatchDetachMem(pMulticastFabricDesc); - _memMulticastFabricSendInbandRequestUnderLock(NULL, pMulticastFabricDesc, - MEM_MULTICAST_FABRIC_TEAM_RELEASE_REQUEST); + if (_memMulticastFabricIsPrime(allocFlags)) + { + _memMulticastFabricSendInbandRequestUnderLock( + NULL, pMulticastFabricDesc, + MEM_MULTICAST_FABRIC_TEAM_RELEASE_REQUEST); } + } - if (pMulticastFabricDesc->bInbandReqInProgress) - { - Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); - OS_WAIT_QUEUE *pWq; - THREAD_STATE_NODE *pThreadNode = NULL; - THREAD_STATE_FREE_CALLBACK freeCallback; + if (!_memMulticastFabricIsPrime(allocFlags)) + { + } - fabricMulticastSetupCacheDeleteUnderLock_IMPL(pFabric, - pMulticastFabricDesc->inbandReqId); + fabricMulticastSetupCacheDeleteUnderLock_IMPL(pFabric, + pMulticastFabricDesc->inbandReqId); - NV_ASSERT_OK(osAllocWaitQueue(&pWq)); + if (pMulticastFabricDesc->bInbandReqInProgress) + { + OS_WAIT_QUEUE *pWq; + THREAD_STATE_NODE *pThreadNode = NULL; + THREAD_STATE_FREE_CALLBACK freeCallback; - if (pWq != NULL) - { - NV_ASSERT_OK(fabricMulticastCleanupCacheInsertUnderLock_IMPL(pFabric, - pMulticastFabricDesc->inbandReqId, - pWq)); + NV_ASSERT_OK(osAllocWaitQueue(&pWq)); - NV_ASSERT_OK(threadStateGetCurrent(&pThreadNode, NULL)); + if (pWq != NULL) + { + NV_ASSERT_OK(fabricMulticastCleanupCacheInsertUnderLock_IMPL( + pFabric, + pMulticastFabricDesc->inbandReqId, + pWq)); - freeCallback.pCb = fabricMulticastWaitOnTeamCleanupCallback; - freeCallback.pCbData = (void *)pMulticastFabricDesc->inbandReqId; + NV_ASSERT_OK(threadStateGetCurrent(&pThreadNode, NULL)); - NV_ASSERT_OK(threadStateEnqueueCallbackOnFree(pThreadNode, &freeCallback)); - } + freeCallback.pCb = fabricMulticastWaitOnTeamCleanupCallback; + freeCallback.pCbData = (void *)pMulticastFabricDesc->inbandReqId; + + NV_ASSERT_OK(threadStateEnqueueCallbackOnFree(pThreadNode, + &freeCallback)); } + } - _memMulticastFabricGpuInfoRemoveUnderLock(pMulticastFabricDesc); + _memMulticastFabricGpuInfoRemoveUnderLock(pMulticastFabricDesc); - NV_ASSERT(listCount(&pMulticastFabricDesc->gpuInfoList) == 0); - listDestroy(&pMulticastFabricDesc->gpuInfoList); + NV_ASSERT(listCount(&pMulticastFabricDesc->gpuInfoList) == 0); + listDestroy(&pMulticastFabricDesc->gpuInfoList); - NV_ASSERT(pMulticastFabricDesc->numAttachedGpus == 0); - NV_ASSERT(pMulticastFabricDesc->attachedGpusMask == 0); + NV_ASSERT(pMulticastFabricDesc->numAttachedGpus == 0); + NV_ASSERT(pMulticastFabricDesc->localAttachedGpusMask == 0); - NV_ASSERT(listCount(&pMulticastFabricDesc->waitingClientsList) == 0); - listDestroy(&pMulticastFabricDesc->waitingClientsList); + NV_ASSERT(listCount(&pMulticastFabricDesc->waitingClientsList) == 0); + listDestroy(&pMulticastFabricDesc->waitingClientsList); - memdescDestroy(pMulticastFabricDesc->pMemDesc); + memdescDestroy(pMulticastFabricDesc->pMemDesc); - portMemFree(pMulticastFabricDesc); - } + portMemFree(pMulticastFabricDesc); } NV_STATUS @@ -644,21 +865,40 @@ _memMulticastFabricConstructUnderLock RS_RES_ALLOC_PARAMS_INTERNAL *pParams ) { - Memory *pMemory = staticCast(pMemoryMulticastFabric, Memory); - NV00FD_ALLOCATION_PARAMETERS *pAllocParams = pParams->pAllocParams; - MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc; - NV_STATUS status = NV_OK; + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + Memory *pMemory = staticCast(pMemoryMulticastFabric, Memory); + NV00FD_ALLOCATION_PARAMETERS *pAllocParams = pParams->pAllocParams; + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc; + NV_STATUS status = NV_OK; - pMulticastFabricDesc = _memMulticastFabricDescriptorAllocUnderLock(pMemoryMulticastFabric, - pAllocParams); + { + pMulticastFabricDesc = + _memMulticastFabricDescriptorAllocUnderLock( + pMemoryMulticastFabric, + pAllocParams); + } if (pMulticastFabricDesc == NULL) return NV_ERR_NO_MEMORY; - status = _memMulticastFabricDescriptorEnqueueWaitUnderLock(pParams->hClient, - pMulticastFabricDesc, - pAllocParams->pOsEvent, - pMemory); + // Track pMulticastFabricDesc if freshly allocated... + if (pMulticastFabricDesc->refCount == 1) + { + status = fabricMulticastSetupCacheInsertUnderLock_IMPL(pFabric, + pMulticastFabricDesc->inbandReqId, + pMulticastFabricDesc); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to track memdesc 0x%x", status); + goto fail; + } + } + + status = _memMulticastFabricDescriptorEnqueueWaitUnderLock( + pParams->hClient, + pMulticastFabricDesc, + pAllocParams->pOsEvent, + pMemory); if (status != NV_OK) goto fail; @@ -683,19 +923,22 @@ _memMulticastFabricCreateMemDescUnderLock NV_STATUS status; MEMORY_DESCRIPTOR *pTempMemDesc = NULL; - status = memdescCreate(&pTempMemDesc, NULL, pMulticastFabricDesc->allocSize, - 0, NV_TRUE, ADDR_FABRIC_MC, NV_MEMORY_UNCACHED, + status = memdescCreate(&pTempMemDesc, NULL, + pMulticastFabricDesc->allocSize, + 0, NV_TRUE, ADDR_FABRIC_MC, + NV_MEMORY_UNCACHED, MEMDESC_FLAGS_NONE); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, - "Failed to allocate memory descriptor for multicast object\n"); + "Failed to allocate memory descriptor for multicast object\n"); return status; } memdescSetPte(pTempMemDesc, AT_GPU, 0, mcAddressBase); - memdescSetPageSize(pTempMemDesc, AT_GPU, pMulticastFabricDesc->pageSize); + memdescSetPageSize(pTempMemDesc, AT_GPU, + pMulticastFabricDesc->pageSize); pTempMemDesc->_pteKind = NV_MMU_PTE_KIND_SMSKED_MESSAGE; @@ -803,7 +1046,7 @@ _memorymulticastFabricAllocVasUnderLock return status; } -NV_STATUS +static void _memMulticastFabricAttachGpuPostProcessorUnderLock ( OBJGPU *pGpu, @@ -823,9 +1066,20 @@ _memMulticastFabricAttachGpuPostProcessorUnderLock // NV_ASSERT(mcTeamStatus != NV_ERR_NOT_READY); + // Initial value is not NV_ERR_NOT_READY, means a failure was observed. + if (pMulticastFabricDesc->mcTeamStatus != NV_ERR_NOT_READY) + { + status = pMulticastFabricDesc->mcTeamStatus; + NV_ASSERT((status != NV_OK)); + goto installMemDesc; + } + if (mcTeamStatus != NV_OK) goto installMemDesc; + if (!_memMulticastFabricIsPrime(pMulticastFabricDesc->allocFlags)) + pMulticastFabricDesc->allocSize = mcAddressSize; + if (mcAddressSize < pMulticastFabricDesc->allocSize) { NV_PRINTF(LEVEL_ERROR, @@ -834,7 +1088,8 @@ _memMulticastFabricAttachGpuPostProcessorUnderLock goto installMemDesc; } - if (!NV_IS_ALIGNED64(mcAddressBase, NV_MEMORY_MULTICAST_FABRIC_PAGE_SIZE_512M)) + if (!NV_IS_ALIGNED64(mcAddressBase, + NV_MEMORY_MULTICAST_FABRIC_PAGE_SIZE_512M)) { NV_PRINTF(LEVEL_ERROR, "Insufficient mcAddressSize returned from Fabric Manager\n"); @@ -843,7 +1098,7 @@ _memMulticastFabricAttachGpuPostProcessorUnderLock } status = _memMulticastFabricCreateMemDescUnderLock(pMulticastFabricDesc, - mcAddressBase, &pMemDesc); + mcAddressBase, &pMemDesc); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "Failed to allocate fabric memdesc\n"); @@ -867,10 +1122,9 @@ _memMulticastFabricAttachGpuPostProcessorUnderLock status); if ((status != NV_OK) && (mcTeamStatus == NV_OK)) - _memMulticastFabricSendInbandRequestUnderLock(pGpu, pMulticastFabricDesc, - MEM_MULTICAST_FABRIC_TEAM_RELEASE_REQUEST); - - return status; + _memMulticastFabricSendInbandRequestUnderLock(pGpu, + pMulticastFabricDesc, + MEM_MULTICAST_FABRIC_TEAM_RELEASE_REQUEST); } void @@ -886,7 +1140,8 @@ _memorymulticastfabricDestructUnderLock memDestructCommon(pMemory); - _memMulticastFabricDescriptorDequeueWaitUnderLock(pMulticastFabricDesc, pMemory); + _memMulticastFabricDescriptorDequeueWaitUnderLock(pMulticastFabricDesc, + pMemory); _memMulticastFabricDescriptorFreeUnderLock(pMulticastFabricDesc); } @@ -951,24 +1206,23 @@ memorymulticastfabricTeamSetupResponseCallback { pMulticastFabricDesc->bInbandReqInProgress = NV_FALSE; - pMulticastFabricDesc->inbandReqId = 0; - fabricMulticastSetupCacheDeleteUnderLock_IMPL(pFabric, requestId); - (void)_memMulticastFabricAttachGpuPostProcessorUnderLock(pGpu, - pMulticastFabricDesc, - mcTeamStatus, - mcTeamHandle, - mcAddressBase, - mcAddressSize); + _memMulticastFabricAttachGpuPostProcessorUnderLock(pGpu, + pMulticastFabricDesc, + mcTeamStatus, + mcTeamHandle, + mcAddressBase, + mcAddressSize); } else { OS_WAIT_QUEUE *pWq; if (mcTeamStatus == NV_OK) - (void)_memMulticastFabricSendInbandTeamReleaseRequestUnderLock(pGpu, - mcTeamHandle); + (void)_memMulticastFabricSendInbandTeamReleaseRequestUnderLock( + pGpu, + mcTeamHandle); // // Check if there is any thread waiting for team release and @@ -983,8 +1237,9 @@ memorymulticastfabricTeamSetupResponseCallback // is received and a subsequent team release request is sent. // - pWq = (OS_WAIT_QUEUE *)fabricMulticastCleanupCacheGetUnderLock_IMPL(pFabric, - requestId); + pWq = (OS_WAIT_QUEUE *)fabricMulticastCleanupCacheGetUnderLock_IMPL( + pFabric, + requestId); if (pWq != NULL) osWakeUp(pWq); @@ -1003,9 +1258,9 @@ memorymulticastfabricConstruct_IMPL RS_RES_ALLOC_PARAMS_INTERNAL *pParams ) { - Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); NV00FD_ALLOCATION_PARAMETERS *pAllocParams = pParams->pAllocParams; - NV_STATUS status = NV_OK; + NV_STATUS status = NV_OK; if (RS_IS_COPY_CTOR(pParams)) { @@ -1014,7 +1269,8 @@ memorymulticastfabricConstruct_IMPL pParams); } - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, _memMulticastFabricValidateAllocParams(pAllocParams)); + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + _memMulticastFabricValidateAllocParams(pAllocParams)); fabricMulticastFabricOpsMutexAcquire(pFabric); @@ -1034,14 +1290,13 @@ _memorymulticastfabricCtrlAttachGpu NV00FD_CTRL_ATTACH_GPU_PARAMS *pParams ) { - MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc = \ + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc = pMemoryMulticastFabric->pMulticastFabricDesc; NV_STATUS status = NV_OK; Subdevice *pSubdevice; OBJGPU *pGpu; FABRIC_VASPACE *pFabricVAS; - NvU64 gpuProbeHandle; - MEM_MULTICAST_FABRIC_GPU_INFO *pNode = NULL; + MEM_MULTICAST_FABRIC_GPU_INFO *pNode; CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); if (pParams->flags != 0) @@ -1051,15 +1306,26 @@ _memorymulticastfabricCtrlAttachGpu } // Check if the Multicast FLA object has any additional slots for GPUs - if (pMulticastFabricDesc->numAttachedGpus == pMulticastFabricDesc->numMaxGpus) + if (pMulticastFabricDesc->numAttachedGpus == + pMulticastFabricDesc->numMaxGpus) { NV_PRINTF(LEVEL_ERROR, "Max no. of GPUs have already attached!\n"); return NV_ERR_INVALID_OPERATION; } - NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - subdeviceGetByHandle(RES_GET_CLIENT(pMemoryMulticastFabric), - pParams->hSubdevice, &pSubdevice)); + if (pMulticastFabricDesc->bMemdescInstalled) + { + NV_PRINTF(LEVEL_ERROR, "The object is already ready.\n"); + return NV_ERR_STATE_IN_USE; + } + + status = subdeviceGetByHandle(RES_GET_CLIENT(pMemoryMulticastFabric), + pParams->hSubdevice, &pSubdevice); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Unable to query subdevice\n"); + return status; + } pGpu = GPU_RES_GET_GPU(pSubdevice); @@ -1083,7 +1349,7 @@ _memorymulticastfabricCtrlAttachGpu pNode = listTail(&pMulticastFabricDesc->gpuInfoList); status = gpuFabricProbeGetGpuFabricHandle(pGpu->pGpuFabricProbeInfoKernel, - &gpuProbeHandle); + &pNode->gpuProbeHandle); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, @@ -1091,6 +1357,15 @@ _memorymulticastfabricCtrlAttachGpu goto fail; } + status = gpuFabricProbeGetFabricCliqueId(pGpu->pGpuFabricProbeInfoKernel, + &pNode->cliqueId); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Attaching GPU does not have a valid clique ID\n"); + goto fail; + } + pFabricVAS = dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE); if (pFabricVAS == NULL) { @@ -1101,22 +1376,22 @@ _memorymulticastfabricCtrlAttachGpu goto fail; } - pNode->gpuProbeHandle = gpuProbeHandle; - - if ((pMulticastFabricDesc->numAttachedGpus + 1) == pMulticastFabricDesc->numMaxGpus) + if ((pMulticastFabricDesc->numAttachedGpus + 1) + == pMulticastFabricDesc->numMaxGpus) { - status = _memMulticastFabricSendInbandRequestUnderLock(NULL, pMulticastFabricDesc, - MEM_MULTICAST_FABRIC_TEAM_SETUP_REQUEST); + status = _memMulticastFabricSendInbandRequestUnderLock(NULL, + pMulticastFabricDesc, + MEM_MULTICAST_FABRIC_TEAM_SETUP_REQUEST); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, - "Inband request submission to FM for Multicast Team Setup failed!\n"); + "Inband request Multicast Team Setup failed!\n"); goto fail; } } pMulticastFabricDesc->numAttachedGpus++; - pMulticastFabricDesc->attachedGpusMask |= NVBIT32(pGpu->gpuInstance); + pMulticastFabricDesc->localAttachedGpusMask |= NVBIT32(pGpu->gpuInstance); return NV_OK; @@ -1252,8 +1527,9 @@ _memorymulticastfabricValidatePhysMem NV_STATUS status; Memory *pMemory; - status = serverutilGetResourceRef(RES_GET_CLIENT_HANDLE(pMemoryMulticastFabric), - hPhysMem, &pPhysmemRef); + status = serverutilGetResourceRef( + RES_GET_CLIENT_HANDLE(pMemoryMulticastFabric), + hPhysMem, &pPhysmemRef); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, @@ -1465,10 +1741,10 @@ memorymulticastfabricCopyConstruct_IMPL pMulticastFabricDesc = pSourceMemoryMulticastFabric->pMulticastFabricDesc; - pMemoryMulticastFabric->pMulticastFabricDesc = pMulticastFabricDesc; - pMulticastFabricDesc->refCount++; + pMemoryMulticastFabric->pMulticastFabricDesc = pMulticastFabricDesc; + fabricMulticastFabricOpsMutexRelease(pFabric); return NV_OK; @@ -1597,8 +1873,12 @@ memorymulticastfabricControl_IMPL { NV_STATUS status = NV_OK; - if (pParams->cmd != NV00FD_CTRL_CMD_ATTACH_GPU) - status = memorymulticastfabricIsReady(pMemoryMulticastFabric, NV_FALSE); + if ( + (pParams->cmd != NV00FD_CTRL_CMD_ATTACH_GPU)) + { + status = memorymulticastfabricIsReady(pMemoryMulticastFabric, + NV_FALSE); + } // // If clients try to register when the multicast object @@ -1634,6 +1914,28 @@ memorymulticastfabricControl_IMPL pCallContext, pParams); } +NvBool +memorymulticastfabricIsExportAllowed_IMPL +( + MemoryMulticastFabric *pMemoryMulticastFabric +) +{ + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc; + NvBool bAllowed; + + fabricMulticastFabricOpsMutexAcquire(pFabric); + + pMulticastFabricDesc = pMemoryMulticastFabric->pMulticastFabricDesc; + + bAllowed = (pMulticastFabricDesc != NULL) && + _memMulticastFabricIsPrime(pMulticastFabricDesc->allocFlags); + + fabricMulticastFabricOpsMutexRelease(pFabric); + + return bAllowed; +} + NvBool memorymulticastfabricIsGpuMapAllowed_IMPL ( @@ -1643,17 +1945,17 @@ memorymulticastfabricIsGpuMapAllowed_IMPL { Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc; - NvU32 attachedGpusMask; + NvU32 localAttachedGpusMask; fabricMulticastFabricOpsMutexAcquire(pFabric); pMulticastFabricDesc = pMemoryMulticastFabric->pMulticastFabricDesc; - attachedGpusMask = pMulticastFabricDesc->attachedGpusMask; + localAttachedGpusMask = pMulticastFabricDesc->localAttachedGpusMask; fabricMulticastFabricOpsMutexRelease(pFabric); - return ((attachedGpusMask & NVBIT32(pGpu->gpuInstance)) != 0U); + return ((localAttachedGpusMask & NVBIT32(pGpu->gpuInstance)) != 0U); } NV_STATUS @@ -1668,3 +1970,4 @@ memorymulticastfabricGetMapAddrSpace_IMPL *pAddrSpace = ADDR_FABRIC_MC; return NV_OK; } + diff --git a/src/nvidia/src/kernel/mem_mgr/os_desc_mem.c b/src/nvidia/src/kernel/mem_mgr/os_desc_mem.c index 42dd00ca2d..90283638d0 100644 --- a/src/nvidia/src/kernel/mem_mgr/os_desc_mem.c +++ b/src/nvidia/src/kernel/mem_mgr/os_desc_mem.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/nvidia/src/kernel/mem_mgr/phys_mem.c b/src/nvidia/src/kernel/mem_mgr/phys_mem.c index a011309b1c..0bec14b984 100644 --- a/src/nvidia/src/kernel/mem_mgr/phys_mem.c +++ b/src/nvidia/src/kernel/mem_mgr/phys_mem.c @@ -61,7 +61,6 @@ physmemConstruct_IMPL HWRESOURCE_INFO hwResource = {0}; NvU64 heapBase; NvU64 trueLength; - RS_PRIV_LEVEL privLevel = pCallContext->secInfo.privLevel; NvBool bCompressedKind; NvU32 attr = DRF_DEF(OS32, _ATTR, _PHYSICALITY, _CONTIGUOUS) | DRF_DEF(OS32, _ATTR, _LOCATION, _VIDMEM); @@ -85,9 +84,6 @@ physmemConstruct_IMPL // // - if (!(rmclientIsAdminByHandle(hClient, privLevel) || hypervisorCheckForObjectAccess(hClient))) - return NV_ERR_INSUFFICIENT_PERMISSIONS; - pAllocParams = pParams->pAllocParams; bCompressedKind = memmgrIsKind_HAL(pMemoryManager, FB_IS_KIND_COMPRESSIBLE, pAllocParams->format); @@ -108,12 +104,14 @@ physmemConstruct_IMPL attr2 |= DRF_DEF(OS32, _ATTR2, _PAGE_SIZE_HUGE, _2MB); break; default: - if (bCompressedKind && - pKernelBus->bar1[GPU_GFID_PF].bStaticBar1Enabled) + if (bCompressedKind && kbusIsStaticBar1Enabled(pGpu, pKernelBus)) { NV_ASSERT_OR_RETURN(kgmmuIsHugePageSupported(pKernelGmmu), NV_ERR_INVALID_ARGUMENT); attr |= DRF_DEF(OS32, _ATTR, _PAGE_SIZE, _HUGE); attr2 |= DRF_DEF(OS32, _ATTR2, _PAGE_SIZE_HUGE, _2MB); + + NV_PRINTF(LEVEL_INFO, + "Default to use 2MB page size on this compressed vidmem for the static bar1\n"); } else { @@ -185,45 +183,63 @@ physmemConstruct_IMPL memdescDescribe(pMemDesc, ADDR_FBMEM, heapBase, trueLength); - if (status == NV_OK) + memdescSetPteKind(pMemDesc, pAllocParams->format); + if (bCompressedKind) + memdescSetHwResId(pMemDesc, hwResource.hwResId); + + // Track internally as NV01_MEMORY_LOCAL_USER to share regular FB mem code paths + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + memConstructCommon(pMemory, NV01_MEMORY_LOCAL_USER, 0, pMemDesc, 0, + NULL, attr, attr2, 0, 0, NVOS32_MEM_TAG_NONE, + bCompressedKind ? &hwResource : NULL), + cleanup_mem); + + if (!IS_GSP_CLIENT(pGpu)) { - memdescSetPteKind(pMemDesc, pAllocParams->format); - if (bCompressedKind) - memdescSetHwResId(pMemDesc, hwResource.hwResId); - - // Track internally as NV01_MEMORY_LOCAL_USER to share regular FB mem code paths - status = memConstructCommon(pMemory, NV01_MEMORY_LOCAL_USER, 0, pMemDesc, 0, - NULL, attr, attr2, 0, 0, NVOS32_MEM_TAG_NONE, - bCompressedKind ? &hwResource : NULL); - if (status == NV_OK) + // + // vGPU: + // + // Since vGPU does all real hardware management in the + // host, if we are in guest OS (where IS_VIRTUAL(pGpu) is true), + // do an RPC to the host to do the hardware update. + // + NV_RM_RPC_ALLOC_LOCAL_USER(pGpu, hClient, hParent, hMemory, pMemDesc, trueLength, + attr, attr2, pAllocParams->format, status); + if (status != NV_OK) { - if (!IS_GSP_CLIENT(pGpu)) - { - // - // vGPU: - // - // Since vGPU does all real hardware management in the - // host, if we are in guest OS (where IS_VIRTUAL(pGpu) is true), - // do an RPC to the host to do the hardware update. - // - NV_RM_RPC_ALLOC_LOCAL_USER(pGpu, hClient, hParent, hMemory, pMemDesc, trueLength, - attr, attr2, pAllocParams->format, status); - if (status != NV_OK) - { - // cleanup on an RPC failure - memDestructCommon(pMemory); - memdescDestroy(pMemDesc); - return status; - } - - pMemory->bRpcAlloc = NV_TRUE; - } - } - else - { - memdescDestroy(pMemDesc); + // cleanup on an RPC failure + goto cleanup_common; } + + pMemory->bRpcAlloc = NV_TRUE; } + + if (bCompressedKind && kbusIsStaticBar1Enabled(pGpu, pKernelBus)) + { + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + kbusUpdateStaticBar1VAMapping_HAL(pGpu, pKernelBus, + pMemDesc, 0, memdescGetSize(pMemDesc), NV_FALSE), + cleanup_rpc); + + memdescSetFlag(pMemDesc, + MEMDESC_FLAGS_RESTORE_PTE_KIND_ON_FREE, NV_TRUE); + } + + return NV_OK; + +cleanup_rpc: + { + NV_STATUS rpcstatus = NV_OK;; + NV_RM_RPC_FREE(pGpu, hClient, hParent, hMemory, rpcstatus); + NV_ASSERT(rpcstatus == NV_OK); + } + +cleanup_common: + memDestructCommon(pMemory); + +cleanup_mem: + memdescDestroy(pMemDesc); + return status; } diff --git a/src/nvidia/src/kernel/mem_mgr/system_mem.c b/src/nvidia/src/kernel/mem_mgr/system_mem.c index 250dc400c8..956cc98af3 100644 --- a/src/nvidia/src/kernel/mem_mgr/system_mem.c +++ b/src/nvidia/src/kernel/mem_mgr/system_mem.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -220,7 +220,46 @@ sysmemConstruct_IMPL memdescSetGpuCacheAttrib(pMemDesc, gpuCacheAttrib); - rmStatus = memdescAlloc(pMemDesc); + if (FLD_TEST_DRF(OS32, _ATTR2, _FIXED_NUMA_NODE_ID, _YES, pAllocData->attr2)) + { + // + // TODO: Add validation of NUMA Node ID. Bug: 3802992 + // Invalid ID criteria: + // * NUMA is not supported on this platform + // * NUMA Node ID is of GPU + // * When memory is protected, if requested in unprotected memory + // + // Allow kernel to validate the following: + // * NUMA Node ID is not in range of [0,MAX_NUMANODES) + // * NUMA Node has no memory present + // * NUMA Node has no free memory + // + + memdescSetNumaNode(pMemDesc, pAllocData->numaNode); + // + // In order to allow EGM memory allocation to specify + // the page granularity of the physical allocation + // we need to force set the page size here. + // + // The expectation is that the EGM NUMA allocator is able to support any requested pagesize + // and that subsequent memdesc pagesize set requests will NOP as the pagesize matches. + // + if (memdescIsEgm(pMemDesc)) + { + RM_ATTR_PAGE_SIZE pageSizeAttr = dmaNvos32ToPageSizeAttr(pAllocData->attr, pAllocData->attr2); + rmStatus = memmgrSetMemDescPageSize_HAL(pGpu, GPU_GET_MEMORY_MANAGER(pGpu), pMemDesc, + AT_GPU, pageSizeAttr); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to set memdesc page size for EGM.\n"); + memdescDestroy(pMemDesc); + goto failed; + } + } + } + + memdescTagAlloc(rmStatus, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_132, + pMemDesc); if (rmStatus != NV_OK) { NV_PRINTF(LEVEL_ERROR, @@ -282,6 +321,7 @@ sysmemConstruct_IMPL else if ((FLD_TEST_DRF(OS32, _ATTR, _PAGE_SIZE, _BIG, pAllocData->attr) || FLD_TEST_DRF(OS32, _ATTR, _PAGE_SIZE, _HUGE, pAllocData->attr)) && FLD_TEST_DRF(OS32, _ATTR, _PHYSICALITY, _NONCONTIGUOUS, pAllocData->attr) && + !memdescIsEgm(pMemDesc) && (stdmemGetSysmemPageSize_HAL(pGpu, pStdMemory) == RM_PAGE_SIZE)) { NV_PRINTF(LEVEL_ERROR, diff --git a/src/nvidia/src/kernel/mem_mgr/vaspace.c b/src/nvidia/src/kernel/mem_mgr/vaspace.c index 232967284b..653ad42cc6 100644 --- a/src/nvidia/src/kernel/mem_mgr/vaspace.c +++ b/src/nvidia/src/kernel/mem_mgr/vaspace.c @@ -101,70 +101,26 @@ vaspaceFillAllocParams_IMPL } } - if (vaspaceIsInternalVaRestricted(pVAS)) // will be true only for MAC's GPUVA. + // + // Handle 32bit pointer requests. 32b pointers are forced below 32b + // on all chips. Non-32b requests are only forced on some chips, + // typically kepler, and only if there are no other address hints. + // + // If requested size cannot be satisfied with range above 4 GB, then relax that + // restriction. + // + if (FLD_TEST_DRF(OS32, _ATTR2, _32BIT_POINTER, _ENABLE, pAllocInfo->pageFormat->attr2)) { - - if (pFlags->bClientAllocation) // client allocations - { - NvU64 partitionRangeLo = 0; - NvU64 partitionRangeHi = 0; - - // If 32 bit enforcement is set, route to the lower va range. - if (FLD_TEST_DRF(OS32, _ATTR2, _32BIT_POINTER, _ENABLE, pAllocInfo->pageFormat->attr2)) - { - partitionRangeLo = vaspaceGetVaStart(pVAS); - partitionRangeHi = NVBIT64(32) - 1; - } - else - { - // route to >4gig - partitionRangeLo = NVBIT64(32); - partitionRangeHi = vaspaceGetVaLimit(pVAS); - } - - // If fixed address is requested - the range should be entirely contained within the partition. - if (pAllocInfo->pageFormat->flags & NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE || - pAllocInfo->pageFormat->flags & NVOS32_ALLOC_FLAGS_USE_BEGIN_END) // Is this a valid expectation? - { - // Within the 32 bit or 64 bit partition. - if (!(*pRangeLo >= partitionRangeLo && *pRangeHi <=partitionRangeHi)) - { - return NV_ERR_INVALID_PARAMETER; - } - // both use_begin_end and fixed_addr_range will have this flag set - pFlags->bFixedAddressRange = NV_TRUE; - } - else - { - *pRangeLo = partitionRangeLo; - *pRangeHi = partitionRangeHi; - pFlags->bFixedAddressRange = NV_FALSE; - } - } + *pRangeHi = NV_MIN(*pRangeHi, NVBIT64(32) - 1); } - else + + else if (bEnforce32bitPtr && + !(pAllocInfo->pageFormat->flags & NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE) && + !(pAllocInfo->pageFormat->flags & NVOS32_ALLOC_FLAGS_USE_BEGIN_END) && + ((*pRangeHi - *pRangeLo + 1 - *pSize) > NVBIT64(32)) && + !(vasFlags & VASPACE_FLAGS_FLA)) { - // - // Handle 32bit pointer requests. 32b pointers are forced below 32b - // on all chips. Non-32b requests are only forced on some chips, - // typically kepler, and only if there are no other address hints. - // - // If requested size cannot be satisfied with range above 4 GB, then relax that - // restriction. - // - if (FLD_TEST_DRF(OS32, _ATTR2, _32BIT_POINTER, _ENABLE, pAllocInfo->pageFormat->attr2)) - { - *pRangeHi = NV_MIN(*pRangeHi, NVBIT64(32) - 1); - } - - else if (bEnforce32bitPtr && - !(pAllocInfo->pageFormat->flags & NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE) && - !(pAllocInfo->pageFormat->flags & NVOS32_ALLOC_FLAGS_USE_BEGIN_END) && - ((*pRangeHi - *pRangeLo + 1 - *pSize) > NVBIT64(32)) && - !(vasFlags & VASPACE_FLAGS_FLA)) - { - *pRangeLo = NV_MAX(*pRangeLo, NVBIT64(32)); - } + *pRangeLo = NV_MAX(*pRangeLo, NVBIT64(32)); } if ((*pRangeHi - *pRangeLo + 1) < *pSize) // Moved the range check here @@ -223,12 +179,6 @@ vaspaceInvalidateTlb_IMPL NV_ASSERT(0); } -NvBool -vaspaceIsInternalVaRestricted_IMPL(OBJVASPACE *pVAS) -{ - return NV_FALSE; -} - NV_STATUS vaspaceGetByHandleOrDeviceDefault_IMPL ( diff --git a/src/nvidia/src/kernel/mem_mgr/video_mem.c b/src/nvidia/src/kernel/mem_mgr/video_mem.c index c0e3327c1a..047474d2a6 100644 --- a/src/nvidia/src/kernel/mem_mgr/video_mem.c +++ b/src/nvidia/src/kernel/mem_mgr/video_mem.c @@ -133,10 +133,6 @@ _vidmemPmaAllocate PMA_ALLOCATION_OPTIONS allocOptions = {0}; NvBool bContig; NvU32 subdevInst = gpumgrGetSubDeviceInstanceFromGpu(pGpu); - NvBool bCompressed = !FLD_TEST_DRF(OS32, _ATTR, _COMPR, - _NONE, pAllocData->attr); - KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); - NvU32 gfid; NvU32 pmaConfig = PMA_QUERY_NUMA_ENABLED; status = pmaQueryConfigs(pPma, &pmaConfig); @@ -168,17 +164,6 @@ _vidmemPmaAllocate RM_LOCK_MODULES_MEM_PMA); NV_ASSERT_OR_RETURN(status == NV_OK, status); - if (bCompressed && - (vgpuGetCallingContextGfid(pGpu, &gfid) == NV_OK) && - pKernelBus->bar1[gfid].bStaticBar1Enabled) - { - // Override the attr to use 2MB page size - pAllocData->attr = FLD_SET_DRF(OS32, _ATTR, _PAGE_SIZE, _HUGE, pAllocData->attr); - - NV_PRINTF(LEVEL_INFO, - "Overrode the page size to 2MB on this compressed vidmem for the static bar1\n"); - } - NV_PRINTF(LEVEL_INFO, "PMA input\n"); NV_PRINTF(LEVEL_INFO, " Owner: 0x%x\n", pAllocData->owner); NV_PRINTF(LEVEL_INFO, " hMemory: 0x%x\n", pAllocRequest->hMemory); @@ -420,7 +405,8 @@ vidmemGetHeap ( OBJGPU *pGpu, Device *pDevice, - NvBool bSubheap + NvBool bSubheap, + NvBool bForceGlobalHeap ) { MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); @@ -434,7 +420,7 @@ vidmemGetHeap return pHeap; } - if (IS_MIG_IN_USE(pGpu)) + if (IS_MIG_IN_USE(pGpu) && !bForceGlobalHeap) { KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); Heap *pMemoryPartitionHeap = NULL; @@ -523,6 +509,7 @@ vidmemConstruct_IMPL MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); Heap *pHeap; NvBool bSubheap = NV_FALSE; + NvBool bRsvdHeap = NV_FALSE; MEMORY_DESCRIPTOR *pTopLevelMemDesc = NULL; MEMORY_DESCRIPTOR *pTempMemDesc = NULL; HWRESOURCE_INFO hwResource; @@ -541,6 +528,8 @@ vidmemConstruct_IMPL FB_ALLOC_INFO *pFbAllocInfo = NULL; FB_ALLOC_PAGE_FORMAT *pFbAllocPageFormat = NULL; NV_STATUS rmStatus = NV_OK; + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + NvBool bUpdatePteKind = NV_FALSE; NV_ASSERT_OK_OR_RETURN( refFindAncestorOfType(pResourceRef, classId(Device), &pDeviceRef)); @@ -562,6 +551,22 @@ vidmemConstruct_IMPL goto done; } + if (!FLD_TEST_DRF(OS32, _ATTR, _COMPR, _NONE, pAllocData->attr) && + kbusIsStaticBar1Enabled(pGpu, pKernelBus)) + { + if (!FLD_TEST_DRF(OS32, _ATTR, _PAGE_SIZE, _HUGE, pAllocData->attr)) + { + // Override the attr to use 2MB page size + pAllocData->attr = FLD_SET_DRF(OS32, _ATTR, _PAGE_SIZE, _HUGE, pAllocData->attr); + pAllocData->attr2 = FLD_SET_DRF(OS32, _ATTR2, _PAGE_SIZE_HUGE, _DEFAULT, pAllocData->attr2); + + NV_PRINTF(LEVEL_INFO, + "Overrode the page size to 2MB on this compressed vidmem for the static bar1\n"); + } + + bUpdatePteKind = NV_TRUE; + } + NV_CHECK_OK_OR_RETURN(LEVEL_WARNING, stdmemValidateParams(pGpu, hClient, pAllocData)); NV_CHECK_OR_RETURN(LEVEL_WARNING, DRF_VAL(OS32, _ATTR, _LOCATION, pAllocData->attr) == NVOS32_ATTR_LOCATION_VIDMEM && @@ -570,8 +575,13 @@ vidmemConstruct_IMPL stdmemDumpInputAllocParams(pAllocData, pCallContext); + if (pCallContext->secInfo.privLevel >= RS_PRIV_LEVEL_KERNEL) + { + bRsvdHeap = FLD_TEST_DRF(OS32, _ATTR, _ALLOCATE_FROM_RESERVED_HEAP, _YES, pAllocData->attr); + } + bSubheap = FLD_TEST_DRF(OS32, _ATTR2, _ALLOCATE_FROM_SUBHEAP, _YES, pAllocData->attr2); - pHeap = vidmemGetHeap(pGpu, pDevice, bSubheap); + pHeap = vidmemGetHeap(pGpu, pDevice, bSubheap, bRsvdHeap); NV_CHECK_OR_RETURN(LEVEL_INFO, pHeap != NULL, NV_ERR_INVALID_STATE); if (gpuIsCCorApmFeatureEnabled(pGpu) && @@ -608,6 +618,7 @@ vidmemConstruct_IMPL bIsPmaAlloc = memmgrIsPmaInitialized(pMemoryManager) && !bSubheap && + !bRsvdHeap && !(pAllocData->flags & NVOS32_ALLOC_FLAGS_WPR1) && !(pAllocData->flags & NVOS32_ALLOC_FLAGS_WPR2) && (!(pAllocData->flags & NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE) || @@ -623,7 +634,7 @@ vidmemConstruct_IMPL { SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY | SLI_LOOP_FLAGS_IGNORE_REENTRANCY) pAllocRequest->pGpu = pGpu; - rmStatus = _vidmemPmaAllocate(vidmemGetHeap(pGpu, pDevice, NV_FALSE), pAllocRequest); + rmStatus = _vidmemPmaAllocate(vidmemGetHeap(pGpu, pDevice, NV_FALSE, NV_FALSE), pAllocRequest); if (NV_OK != rmStatus) SLI_LOOP_GOTO(done); SLI_LOOP_END; @@ -691,8 +702,9 @@ vidmemConstruct_IMPL { MEMORY_DESCRIPTOR *pPrev = NULL; - // VGPU won't run in SLI. So no need to set subheap flags in memdesc. + // VGPU won't run in SLI. So no need to set subheap and bRsvdHeap flags in memdesc. NV_ASSERT(!bSubheap); + NV_ASSERT(!bRsvdHeap); // Create dummy top level memdesc rmStatus = memdescCreate(&pTopLevelMemDesc, pGpu, RM_PAGE_SIZE, 0, @@ -725,7 +737,7 @@ vidmemConstruct_IMPL SLI_LOOP_GOTO(done); rmStatus = vidmemAllocResources(pGpu, pMemoryManager, pAllocRequest, pFbAllocInfo, - vidmemGetHeap(pGpu, pDevice, NV_FALSE)); + vidmemGetHeap(pGpu, pDevice, NV_FALSE, NV_FALSE)); if (rmStatus != NV_OK) SLI_LOOP_GOTO(done); @@ -976,6 +988,32 @@ vidmemConstruct_IMPL } } + if (bUpdatePteKind) + { + rmStatus = kbusUpdateStaticBar1VAMapping_HAL(pGpu, pKernelBus, + pMemory->pMemDesc, 0, + memdescGetSize(pMemory->pMemDesc), NV_FALSE); + + if (rmStatus != NV_OK) + { + if (pMemory->bRpcAlloc) + { + NV_STATUS status = NV_OK; + NV_RM_RPC_FREE(pGpu, hClient, hParent, + pAllocRequest->hMemory, status); + NV_ASSERT(status == NV_OK); + } + memDestructCommon(pMemory); + memdescFree(pTopLevelMemDesc); + memdescDestroy(pTopLevelMemDesc); + pTopLevelMemDesc = NULL; + goto done; + } + + memdescSetFlag(pMemory->pMemDesc, + MEMDESC_FLAGS_RESTORE_PTE_KIND_ON_FREE, NV_TRUE); + } + pAllocData->size = sizeOut; pAllocData->offset = offsetOut; @@ -999,7 +1037,7 @@ vidmemConstruct_IMPL SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY | SLI_LOOP_FLAGS_IGNORE_REENTRANCY) if (pAllocRequest->pPmaAllocInfo[gpumgrGetSubDeviceInstanceFromGpu(pGpu)]) - vidmemPmaFree(pGpu, vidmemGetHeap(pGpu, pDevice, NV_FALSE), + vidmemPmaFree(pGpu, vidmemGetHeap(pGpu, pDevice, NV_FALSE, NV_FALSE), pAllocRequest->pPmaAllocInfo[gpumgrGetSubDeviceInstanceFromGpu(pGpu)], 0); SLI_LOOP_END; } diff --git a/src/nvidia/src/kernel/mem_mgr/virtual_mem.c b/src/nvidia/src/kernel/mem_mgr/virtual_mem.c index 6c33a5e6ca..8c5c52cb17 100644 --- a/src/nvidia/src/kernel/mem_mgr/virtual_mem.c +++ b/src/nvidia/src/kernel/mem_mgr/virtual_mem.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -316,41 +316,21 @@ virtmemConstruct_IMPL NvBool bRpcAlloc = NV_FALSE; NvBool bResAllocated = NV_FALSE; NvU32 gpuMask = 0; - NvU32 gpuMaskInitial = 0; FB_ALLOC_INFO *pFbAllocInfo = NULL; FB_ALLOC_PAGE_FORMAT *pFbAllocPageFormat = NULL; // Bulk of copy-construction is done by Memory class. Handle our members. if (RS_IS_COPY_CTOR(pParams)) { - if (!rmGpuGroupLockIsOwner(pGpu->gpuInstance, GPU_LOCK_GRP_ALL, &gpuMask)) - { - // - // If we hold some GPU locks already then acquiring more GPU locks - // may violate lock ordering and cause dead-lock. To avoid dead-lock in this case, - // attempt to take the locks with a conditional acquire. - // - gpuMaskInitial = rmGpuLocksGetOwnedMask(); - NvU32 lockFlag = (gpuMaskInitial == 0) - ? GPUS_LOCK_FLAGS_NONE - : GPU_LOCK_FLAGS_COND_ACQUIRE; - - NV_ASSERT_OK_OR_RETURN(rmGpuGroupLockAcquire(pGpu->gpuInstance, - GPU_LOCK_GRP_ALL, - lockFlag, - RM_LOCK_MODULES_MEM, - &gpuMask)); - - bLockAcquired = NV_TRUE; - } + NV_ASSERT_OK_OR_RETURN(rmGpuGroupLockAcquire(pGpu->gpuInstance, + GPU_LOCK_GRP_ALL, + GPU_LOCK_FLAGS_SAFE_LOCK_UPGRADE, + RM_LOCK_MODULES_MEM, + &gpuMask)); status = _virtmemCopyConstruct(pVirtualMemory, pCallContext, pParams); - if (bLockAcquired) - { - bLockAcquired = NV_FALSE; - rmGpuGroupLockRelease(gpuMask & (~gpuMaskInitial), GPUS_LOCK_FLAGS_NONE); - } + rmGpuGroupLockRelease(gpuMask, GPUS_LOCK_FLAGS_NONE); goto done; } @@ -397,6 +377,11 @@ virtmemConstruct_IMPL NvU64 size; NvU64 align; NvU64 pageSizeLockMask; + Device *pDevice; + + NV_ASSERT_OK_OR_GOTO(status, + deviceGetByHandle(pRsClient, hParent, &pDevice), + done); SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY | SLI_LOOP_FLAGS_IGNORE_REENTRANCY) @@ -411,7 +396,7 @@ virtmemConstruct_IMPL if (NV_OK != status) SLI_LOOP_GOTO(done); - status = vaspaceReserveMempool(pVAS, pGpu, hClient, + status = vaspaceReserveMempool(pVAS, pGpu, pDevice, size, pageSizeLockMask, VASPACE_RESERVE_FLAGS_NONE); if (NV_OK != status) @@ -944,7 +929,7 @@ NV_STATUS virtmemReserveMempool_IMPL ( VirtualMemory *pVirtualMemory, OBJGPU *pGpu, - NvHandle hDevice, + Device *pDevice, NvU64 size, NvU64 pageSizeMask ) @@ -968,10 +953,10 @@ NV_STATUS virtmemReserveMempool_IMPL } NV_ASSERT_OK_OR_RETURN( - vaspaceGetByHandleOrDeviceDefault(pClient, hDevice, + vaspaceGetByHandleOrDeviceDefault(pClient, RES_GET_HANDLE(pDevice), pVirtualMemory->hVASpace, &pVAS)); - return vaspaceReserveMempool(pVAS, pGpu, RES_GET_CLIENT_HANDLE(pVirtualMemory), + return vaspaceReserveMempool(pVAS, pGpu, pDevice, size, pageSizeMask, mempoolFlags); } diff --git a/src/nvidia/src/kernel/os/os_init.c b/src/nvidia/src/kernel/os/os_init.c index 88c1fd9ec6..1e88278de7 100644 --- a/src/nvidia/src/kernel/os/os_init.c +++ b/src/nvidia/src/kernel/os/os_init.c @@ -100,21 +100,12 @@ static void initCommonMiscOSFunctionPointers(OBJOS *pOS) { // Common OS function pointers. - pOS->osGetSimulationMode = osGetSimulationMode; } static void initStubMiscOSFunctionPointers(OBJOS *pOS) { // Stubbed OS function pointers. - pOS->osSimEscapeWrite = stubOsSimEscapeWrite; - pOS->osSimEscapeWriteBuffer = stubOsSimEscapeWriteBuffer; - pOS->osSimEscapeRead = stubOsSimEscapeRead; - pOS->osSimEscapeReadBuffer = stubOsSimEscapeReadBuffer; - - pOS->osCheckCallback = stubOsCheckCallback; - pOS->osRCCallback = stubOsRCCallback; - pOS->osPageArrayGetPhysAddr = stubOsPageArrayGetPhysAddr; pOS->osInternalReserveAllocCallback = stubOsInternalReserveAllocCallback; @@ -124,17 +115,6 @@ initStubMiscOSFunctionPointers(OBJOS *pOS) static void initWinNTStubOSFunctionPointers(OBJOS *pOS) { - pOS->osQADbgRegistryInit = stubOsQADbgRegistryInit; - pOS->osQueueWorkItem = stubOsQueueWorkItem; - pOS->osQueueWorkItemWithFlags = stubOsQueueWorkItemWithFlags; - pOS->osQueueSystemWorkItem = stubOsQueueSystemWorkItem; - pOS->osCallACPI_NVHG_GPUSTA = stubOsCallWMI_NVHG_GPUSTA; - pOS->osCallACPI_NVHG_MXDS = stubOsCallWMI_NVHG_MXDS; - pOS->osCallACPI_NVHG_MXMX = stubOsCallWMI_NVHG_MXMX; - pOS->osCallACPI_NVHG_DOS = stubOsCallWMI_NVHG_DOS; - pOS->osCallACPI_NVHG_DCS = stubOsCallWMI_NVHG_DCS; - pOS->osSetupVBlank = stubOsSetupVBlank; - pOS->osGetUefiVariable = stubOsGetUefiVariable; } static void @@ -145,8 +125,6 @@ initMacOSCoreOSFunctionPointers(OBJOS *pOS) pOS->osNv_cpuid = stubOsnv_cpuid; pOS->osNv_rdmsr = stubOsnv_rdmsr; pOS->osNv_wrmsr = stubOsnv_wrmsr; - pOS->osRobustChannelsDefaultState = stubOsRobustChannelsDefaultState; - pOS->osGetUefiVariable = stubOsGetUefiVariable; } static void diff --git a/src/nvidia/src/kernel/os/os_stubs.c b/src/nvidia/src/kernel/os/os_stubs.c index 1d8045543e..6119ed826e 100644 --- a/src/nvidia/src/kernel/os/os_stubs.c +++ b/src/nvidia/src/kernel/os/os_stubs.c @@ -56,9 +56,9 @@ static void _stubCallCheck(int funcNumber) struct OBJCL; -void stubOsQADbgRegistryInit(OBJOS *pOS) +void osQADbgRegistryInit(void) { - STUB_CHECK(61); + return; } NvU32 stubOsnv_rdcr4(OBJOS *pOS) @@ -92,51 +92,23 @@ NvU32 stubOsnv_wrmsr(OBJOS *pOS, NvU32 arg1, NvU32 arg2, NvU32 arg3) return 0; } -NvU32 stubOsRobustChannelsDefaultState(OBJOS *pOS) -{ - STUB_CHECK(128); - return 0; -} - -NV_STATUS stubOsQueueWorkItem(OBJGPU *pGpu, OSWorkItemFunction pFunction, void * pParms) -{ - STUB_CHECK(180); - return NV_ERR_NOT_SUPPORTED; -} - -NV_STATUS stubOsQueueSystemWorkItem(OSSystemWorkItemFunction pFunction, void *pParms) -{ - STUB_CHECK(181); - return NV_ERR_NOT_SUPPORTED; -} - -NV_STATUS stubOsQueueWorkItemWithFlags(OBJGPU *pGpu, OSWorkItemFunction pFunction, void * pParms, NvU32 flags) -{ - STUB_CHECK(182); - return NV_ERR_NOT_SUPPORTED; -} - -NV_STATUS stubOsSimEscapeWrite(OBJGPU *pGpu, const char *path, NvU32 Index, NvU32 Size, NvU32 Value) +NV_STATUS osSimEscapeWrite(OBJGPU *pGpu, const char *path, NvU32 Index, NvU32 Size, NvU32 Value) { - STUB_CHECK(195); return NV_ERR_GENERIC; } -NV_STATUS stubOsSimEscapeWriteBuffer(OBJGPU *pGpu, const char *path, NvU32 Index, NvU32 Size, void* pBuffer) +NV_STATUS osSimEscapeWriteBuffer(OBJGPU *pGpu, const char *path, NvU32 Index, NvU32 Size, void* pBuffer) { - STUB_CHECK(197); return NV_ERR_GENERIC; } -NV_STATUS stubOsSimEscapeRead(OBJGPU *pGpu, const char *path, NvU32 Index, NvU32 Size, NvU32 *Value) +NV_STATUS osSimEscapeRead(OBJGPU *pGpu, const char *path, NvU32 Index, NvU32 Size, NvU32 *Value) { - STUB_CHECK(196); return NV_ERR_GENERIC; } -NV_STATUS stubOsSimEscapeReadBuffer(OBJGPU *pGpu, const char *path, NvU32 Index, NvU32 Size, void* pBuffer) +NV_STATUS osSimEscapeReadBuffer(OBJGPU *pGpu, const char *path, NvU32 Index, NvU32 Size, void* pBuffer) { - STUB_CHECK(198); return NV_ERR_GENERIC; } @@ -175,33 +147,28 @@ NV_STATUS osCallACPI_NVHG_GPUOFF(OBJGPU *pGpu, NvU32 *pInOut) return NV_ERR_NOT_SUPPORTED; } -NV_STATUS stubOsCallWMI_NVHG_GPUSTA(OBJGPU *pGpu, NvU32 *pInOut) +NV_STATUS osCallACPI_NVHG_GPUSTA(OBJGPU *pGpu, NvU32 *pInOut) { - //STUB_CHECK(227); return NV_ERR_NOT_SUPPORTED; } -NV_STATUS stubOsCallWMI_NVHG_MXDS(OBJGPU *pGpu, NvU32 AcpiId, NvU32 *pInOut) +NV_STATUS osCallACPI_NVHG_MXDS(OBJGPU *pGpu, NvU32 AcpiId, NvU32 *pInOut) { - //STUB_CHECK(228); return NV_ERR_NOT_SUPPORTED; } -NV_STATUS stubOsCallWMI_NVHG_MXMX(OBJGPU *pGpu, NvU32 AcpiId, NvU32 *pInOut) +NV_STATUS osCallACPI_NVHG_MXMX(OBJGPU *pGpu, NvU32 AcpiId, NvU32 *pInOut) { - //STUB_CHECK(229); return NV_ERR_NOT_SUPPORTED; } -NV_STATUS stubOsCallWMI_NVHG_DOS(OBJGPU *pGpu, NvU32 AcpiId, NvU32 *pInOut) +NV_STATUS osCallACPI_NVHG_DOS(OBJGPU *pGpu, NvU32 AcpiId, NvU32 *pInOut) { - //STUB_CHECK(230); return NV_ERR_NOT_SUPPORTED; } -NV_STATUS stubOsCallWMI_NVHG_DCS(OBJGPU *pGpu, NvU32 AcpiId, NvU32 *pInOut) +NV_STATUS osCallACPI_NVHG_DCS(OBJGPU *pGpu, NvU32 AcpiId, NvU32 *pInOut) { - //STUB_CHECK(232); return NV_ERR_NOT_SUPPORTED; } @@ -215,13 +182,35 @@ NV_STATUS osCallACPI_LRST(OBJGPU *pGpu, NvU32 ulAcpiId, NvU32 *pInOut) return NV_ERR_NOT_SUPPORTED; } -NvBool stubOsCheckCallback(OBJGPU *pGpu) +NvBool osCheckCallback(OBJGPU *pGpu) +{ + return NV_FALSE; +} + +RC_CALLBACK_STATUS +osRCCallback +( + OBJGPU *pGpu, + NvHandle hClient, // IN The client RC is on + NvHandle hDevice, // IN The device RC is on + NvHandle hFifo, // IN The channel or TSG RC is on + NvHandle hChannel, // IN The channel RC is on + NvU32 errorLevel, // IN Error Level + NvU32 errorType, // IN Error type + NvU32 *data, // IN/OUT context of RC handler + void *pfnRmRCReenablePusher +) +{ + return RC_CALLBACK_IGNORE; +} + +NvBool osCheckCallback_v2(OBJGPU *pGpu) { return NV_FALSE; } RC_CALLBACK_STATUS -stubOsRCCallback +osRCCallback_v2 ( OBJGPU *pGpu, NvHandle hClient, // IN The client RC is on @@ -230,6 +219,7 @@ stubOsRCCallback NvHandle hChannel, // IN The channel RC is on NvU32 errorLevel, // IN Error Level NvU32 errorType, // IN Error type + NvBool bDeferRcRequested, // IN defer RC state NvU32 *data, // IN/OUT context of RC handler void *pfnRmRCReenablePusher ) @@ -237,8 +227,8 @@ stubOsRCCallback return RC_CALLBACK_IGNORE; } -NV_STATUS stubOsSetupVBlank(OBJGPU *pGpu, void * pProc, - void * pParm1, void * pParm2, NvU32 Head, void * pParm3) +NV_STATUS osSetupVBlank(OBJGPU *pGpu, void * pProc, + void * pParm1, void * pParm2, NvU32 Head, void * pParm3) { return NV_OK; } @@ -271,6 +261,16 @@ NV_STATUS osGetCurrentProcessGfid(NvU32 *pGfid) return NV_ERR_NOT_SUPPORTED; } +NV_STATUS osSetRegistryList(nv_reg_entry_t *pRegList) +{ + return NV_ERR_NOT_SUPPORTED; +} + +nv_reg_entry_t *osGetRegistryList(void) +{ + return NULL; +} + #if !(RMCFG_FEATURE_PLATFORM_UNIX || RMCFG_FEATURE_PLATFORM_DCE) || \ (RMCFG_FEATURE_PLATFORM_UNIX && !RMCFG_FEATURE_TEGRA_SOC_NVDISPLAY) NV_STATUS osTegraSocGpioGetPinState( @@ -436,7 +436,8 @@ osTegraSocParseFixedModeTimings ( OS_GPU_INFO *pOsGpuInfo, NvU32 dcbIndex, - OS_FIXED_MODE_TIMINGS *pFixedModeTimings + NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS *pTimingsPerStream, + NvU8 *pNumTimings ) { return NV_OK; @@ -616,6 +617,11 @@ NvBool osBugCheckOnTimeoutEnabled(void) return NV_FALSE; } +NvBool osDbgBreakpointEnabled(void) +{ + return NV_TRUE; +} + NV_STATUS osNvifMethod( OBJGPU *pGpu, NvU32 func, @@ -638,14 +644,12 @@ NV_STATUS osNvifInitialize( } NV_STATUS -stubOsGetUefiVariable +osGetUefiVariable ( - OBJGPU *pGpu, - char *pName, - LPGUID pGuid, - NvU8 *pBuffer, - NvU32 *pSize, - NvU32 *pAttributes + const char *pName, + LPGUID pGuid, + NvU8 *pBuffer, + NvU32 *pSize ) { return NV_ERR_NOT_SUPPORTED; diff --git a/src/nvidia/src/kernel/platform/chipset/chipset.c b/src/nvidia/src/kernel/platform/chipset/chipset.c index 315aedb1b7..e998220700 100644 --- a/src/nvidia/src/kernel/platform/chipset/chipset.c +++ b/src/nvidia/src/kernel/platform/chipset/chipset.c @@ -65,8 +65,6 @@ void clInitPropertiesFromRegistry_IMPL(OBJGPU *pGpu, OBJCL *pCl) { NvU32 data32; - OBJSYS *pSys = SYS_GET_INSTANCE(); - OBJOS *pOS = SYS_GET_OS(pSys); if (osReadRegistryDword(pGpu, NV_REG_STR_RM_DISABLE_BR03_FLOW_CONTROL, &data32) == NV_OK && data32) @@ -82,7 +80,7 @@ clInitPropertiesFromRegistry_IMPL(OBJGPU *pGpu, OBJCL *pCl) } } - pOS->osQADbgRegistryInit(pOS); + osQADbgRegistryInit(); } static void @@ -804,7 +802,6 @@ void clSyncWithGsp_IMPL(OBJCL *pCl, GspSystemInfo *pGSI) CL_SYNC_PDB(PDB_PROP_CL_UPSTREAM_LTR_SUPPORTED); CL_SYNC_PDB(PDB_PROP_CL_BUG_1340801_DISABLE_GEN3_ON_GIGABYTE_SNIPER_3); CL_SYNC_PDB(PDB_PROP_CL_BUG_1681803_WAR_DISABLE_MSCG); - CL_SYNC_PDB(PDB_PROP_CL_ON_HASWELL_HOST_BRIDGE); CL_SYNC_PDB(PDB_PROP_CL_PCIE_NON_COHERENT_USE_TC0_ONLY); CL_SYNC_PDB(PDB_PROP_CL_UNSUPPORTED_CHIPSET); CL_SYNC_PDB(PDB_PROP_CL_IS_CHIPSET_IO_COHERENT); diff --git a/src/nvidia/src/kernel/platform/chipset/chipset_info.c b/src/nvidia/src/kernel/platform/chipset/chipset_info.c index 6a1105920d..2e1fed4658 100644 --- a/src/nvidia/src/kernel/platform/chipset/chipset_info.c +++ b/src/nvidia/src/kernel/platform/chipset/chipset_info.c @@ -758,15 +758,6 @@ Intel_8C4B_setupFunc OBJCL *pCl ) { - switch (pCl->FHBBusInfo.deviceID) - { - case DEVICE_ID_INTEL_0C00_HASWELL_HOST_BRIDGE: - case DEVICE_ID_INTEL_0C04_HASWELL_HOST_BRIDGE: - pCl->setProperty(pCl, PDB_PROP_CL_ON_HASWELL_HOST_BRIDGE, NV_TRUE); - break; - default: - break; - } // Set ASPM L0S\L1 properties _Set_ASPM_L0S_L1(pCl, NV_TRUE, NV_FALSE); @@ -1314,7 +1305,7 @@ csGetInfoStrings { NvU32 i; const char* pszUnknown = "Unknown"; - NvU32 szUnknownLen = portStringLength(pszUnknown); + NvU32 szUnknownLen = portStringLength(pszUnknown) + 1; if (!pCl->chipsetIDBusAddr.valid) { diff --git a/src/nvidia/src/kernel/platform/chipset/chipset_pcie.c b/src/nvidia/src/kernel/platform/chipset/chipset_pcie.c index f27711aeab..1b5817f5e2 100644 --- a/src/nvidia/src/kernel/platform/chipset/chipset_pcie.c +++ b/src/nvidia/src/kernel/platform/chipset/chipset_pcie.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2000-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2000-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -293,8 +293,8 @@ objClInitPcieChipset(OBJGPU *pGpu, OBJCL *pCl) if (clFindFHBAndGetChipsetInfoIndex(pCl, &chipsetInfoIndex) == NV_OK) { pCl->Chipset = chipsetInfo[chipsetInfoIndex].chipset; - // If the chipset info is not found, hipsetInfo[chipsetInfoIndex].setupFunc = NULL - if ((!chipsetInfo[chipsetInfoIndex].setupFunc) || + // If the chipset info is not found, chipsetInfo[chipsetInfoIndex].setupFunc = NULL + if ((chipsetInfo[chipsetInfoIndex].setupFunc != NULL) && (chipsetInfo[chipsetInfoIndex].setupFunc(pCl) != NV_OK)) { NV_PRINTF(LEVEL_ERROR, "*** Chipset Setup Function Error!\n"); @@ -1616,9 +1616,11 @@ objClSetPortCapsOffsets PORTDATA *pPort ) { - clSetPortPcieCapOffset(pCl, pPort->addr.handle, - &pPort->PCIECapPtr); - objClSetPortPcieEnhancedCapsOffsets(pCl, pPort); + NV_CHECK_OK_OR_RETURN(LEVEL_INFO, + clSetPortPcieCapOffset(pCl, pPort->addr.handle, + &pPort->PCIECapPtr)); + NV_CHECK_OK_OR_RETURN(LEVEL_INFO, + objClSetPortPcieEnhancedCapsOffsets(pCl, pPort)); return NV_OK; } @@ -3642,8 +3644,8 @@ static NvBool scanForRsdtXsdtTables(OBJOS *pOS, * * @returns NV_OK if RDST or XDST table was found, NV_ERR_* otherwise. */ -NV_STATUS -clGetRsdtXsdtTablesAddr_IMPL +static NV_STATUS +GetRsdtXsdtTablesAddr ( OBJCL *pCl, NvU32 *pRsdtAddr, @@ -3666,9 +3668,9 @@ clGetRsdtXsdtTablesAddr_IMPL // // It doesn't make sense to search for the ACPI tables in the BIOS area - // on ARM, so just skip that here. + // on non-X86 CPUs, so just skip that here. // - if (NVCPU_IS_FAMILY_ARM) + if (!NVCPU_IS_FAMILY_X86) { return NV_ERR_NOT_SUPPORTED; } @@ -3706,14 +3708,14 @@ clGetRsdtXsdtTablesAddr_IMPL status = osGetAcpiRsdpFromUefi(&startAddr); if (status != NV_OK) { - goto clGetRsdtXsdtTablesAddr_exit; + goto GetRsdtXsdtTablesAddr_exit; } size = ACPI_RSDP_STRUCT_LEN; if (scanForRsdtXsdtTables(pOS , startAddr, size, pRsdtAddr, pXsdtAddr) == NV_TRUE) { status = NV_OK; - goto clGetRsdtXsdtTablesAddr_exit; + goto GetRsdtXsdtTablesAddr_exit; } } @@ -3731,7 +3733,7 @@ clGetRsdtXsdtTablesAddr_IMPL if (scanForRsdtXsdtTables(pOS , startAddr, size, pRsdtAddr, pXsdtAddr) == NV_TRUE) { status = NV_OK; - goto clGetRsdtXsdtTablesAddr_exit; + goto GetRsdtXsdtTablesAddr_exit; } } @@ -3743,7 +3745,7 @@ clGetRsdtXsdtTablesAddr_IMPL status = NV_OK; } -clGetRsdtXsdtTablesAddr_exit: +GetRsdtXsdtTablesAddr_exit: return status; } @@ -3756,8 +3758,8 @@ clGetRsdtXsdtTablesAddr_IMPL * * @returns NV_TRUE the RDST or XDST table has been found, NV_FALSE otherwise. */ -NvBool -clGetMcfgTableFromOS_IMPL +static NvBool +GetMcfgTableFromOS ( OBJCL *pCl, OBJOS *pOS, @@ -3821,8 +3823,8 @@ clGetMcfgTableFromOS_IMPL * * @returns the address of the DSDT table, or 0 if an error occurred. */ -NvU64 -clScanForTable_IMPL +static NvU64 +ScanForTable ( OBJCL *pCl, OBJOS *pOS, @@ -4098,19 +4100,19 @@ clStorePcieConfigSpaceBaseFromMcfg_IMPL(OBJCL *pCl) return NV_ERR_INVALID_DATA; } - if (clGetMcfgTableFromOS(pCl, pOS, (void **)&pData, &len) == NV_FALSE) + if (GetMcfgTableFromOS(pCl, pOS, (void **)&pData, &len) == NV_FALSE) { // // If OS api doesn't provide MCFG table then MCFG table address // can be found by parsing RSDT/XSDT tables. // - status = clGetRsdtXsdtTablesAddr(pCl, (NvU32*)&rsdtAddr, &xsdtAddr); + status = GetRsdtXsdtTablesAddr(pCl, (NvU32*)&rsdtAddr, &xsdtAddr); if (status != NV_OK) { goto clStorePcieConfigSpaceBaseFromMcfg_exit; } - mcfgAddr = clScanForTable(pCl, pOS, rsdtAddr, xsdtAddr, NV_ACPI_TABLE_SIGNATURE_GFCM); + mcfgAddr = ScanForTable(pCl, pOS, rsdtAddr, xsdtAddr, NV_ACPI_TABLE_SIGNATURE_GFCM); if (mcfgAddr == 0) { status = NV_ERR_INSUFFICIENT_RESOURCES; diff --git a/src/nvidia/src/kernel/platform/cpu.c b/src/nvidia/src/kernel/platform/cpu.c index 267ba07890..7b04f58641 100644 --- a/src/nvidia/src/kernel/platform/cpu.c +++ b/src/nvidia/src/kernel/platform/cpu.c @@ -751,31 +751,16 @@ void RmInitCpuInfo(void) getEmbeddedProcessorName(pSys->cpuInfo.name, sizeof(pSys->cpuInfo.name)); if (IS_INTEL(cpuinfo.Foundry)) - { cpuidInfoIntel(pSys, &cpuinfo); - pSys->cpuInfo.vendor = CPU_VENDOR_INTEL; - } else if (IS_AMD(cpuinfo.Foundry)) - { cpuidInfoAMD(pSys, &cpuinfo); - pSys->cpuInfo.vendor = CPU_VENDOR_AMD; - } #if defined(_M_IX86) || defined(NVCPU_X86) else if (IS_WINCHIP(cpuinfo.Foundry)) - { cpuidInfoWinChip(pSys, &cpuinfo); - pSys->cpuInfo.vendor = CPU_VENDOR_WINCHIP; - } else if (IS_CYRIX(cpuinfo.Foundry)) - { cpuidInfoCyrix(pSys, &cpuinfo); - pSys->cpuInfo.vendor = CPU_VENDOR_CYRIX; - } else if (IS_TRANSM(cpuinfo.Foundry)) - { cpuidInfoTransmeta(pSys, &cpuinfo); - pSys->cpuInfo.vendor = CPU_VENDOR_TRANSM; - } #endif else { @@ -1292,6 +1277,10 @@ static void cpuidInfoIntel(OBJSYS *pSys, PCPUIDINFO pCpuidInfo) pSys->cpuInfo.type = NV0000_CTRL_SYSTEM_CPU_TYPE_ATOM; break; + case 143: // Intel Xeon Sapphire Rapids(SPR) model 143 + pSys->cpuInfo.type = NV0000_CTRL_SYSTEM_CPU_TYPE_XEON_SPR; + break; + case 8: // Pentium III, Pentium III Xeon, or Celeron (Coppermine, 0.18 micron) case 10: // Pentium III Xeon (Tualatin, 0.13 micron) case 11: // Pentium III, or Celeron (Tualatin, 0.13 micron) @@ -1414,6 +1403,9 @@ static void cpuidInfoAMD(OBJSYS *pSys, PCPUIDINFO pCpuidInfo) pSys->cpuInfo.type = NV0000_CTRL_SYSTEM_CPU_TYPE_K11; break; case 0x080: + // Zen, Zen+, Zen 2 + case 0x0A0: + // Zen 3, Zen 4 pSys->cpuInfo.type = NV0000_CTRL_SYSTEM_CPU_TYPE_RYZEN; break; default: diff --git a/src/nvidia/src/kernel/platform/nbsi/nbsi_getv.c b/src/nvidia/src/kernel/platform/nbsi/nbsi_getv.c index 821229b18e..77b5475257 100644 --- a/src/nvidia/src/kernel/platform/nbsi/nbsi_getv.c +++ b/src/nvidia/src/kernel/platform/nbsi/nbsi_getv.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -262,7 +262,7 @@ NV_STATUS getNbsiValue NBSI_ELEMENT *pNbsiElement; NBSI_ELEMENT *pNbsiElementFound[MAX_NBSI_OS]; NV_STATUS status = NV_OK; - NvU16 n; + NvU32 n; NvBool bFound; NvU32 elementSize; NvU32 idx; diff --git a/src/nvidia/src/kernel/platform/nbsi/nbsi_init.c b/src/nvidia/src/kernel/platform/nbsi/nbsi_init.c index 587c235223..de45a92f51 100644 --- a/src/nvidia/src/kernel/platform/nbsi/nbsi_init.c +++ b/src/nvidia/src/kernel/platform/nbsi/nbsi_init.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -94,7 +94,7 @@ static NvU32 setNbsiOSstring if (dataLen > MAX_NBSI_OS_STR_LEN) { - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_NOTICE, "NBSI OS string length %d too long for OS ndx %d.\n", dataLen, nbsiOSndx); dataLen = MAX_NBSI_OS_STR_LEN; @@ -160,7 +160,7 @@ static NV_STATUS testObjectHash if (tableHash != pNbsiGenObj->objHdr.sig) { status = NV_ERR_INVALID_DATA; - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_NOTICE, "NBSI tbl computed hash %llx != hash %llx\n", tableHash, pNbsiGenObj->objHdr.sig); } @@ -286,7 +286,7 @@ static NV_STATUS getNbsiDirSize if (nbsiDirVer > MAXNBSIDIRVER) { - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_NOTICE, "GPU%d, source %d, NBSI dir ver %d > max ver %d.\n", idx, tblSource, nbsiDirVer, MAXNBSIDIRVER); return NV_ERR_GENERIC; @@ -341,7 +341,7 @@ static NV_STATUS testNbsiDir if (testDirSize > allocSize) { - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_NOTICE, "GPU%d, source %d, Size of NBSI dir %x > alloc mem %x.\n", idx, tblSource, testDirSize, allocSize); return NV_ERR_GENERIC; @@ -423,7 +423,7 @@ static NV_STATUS testNbsiTable // Sanity check 1 for globSize... must be larger than NBSI_MIN_GEN_OBJ_SIZE if (pNbsiGenObj->objHdr.size < NBSI_MIN_GEN_OBJ_SIZE) { - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_NOTICE, "NBSI Gpu%d Tloc=%d/Glob=%d table size 0x%x < min 0x%x\n", idx, tableLoc, i, pNbsiGenObj->objHdr.size, (NvU32)NBSI_MIN_GEN_OBJ_SIZE); @@ -433,7 +433,7 @@ static NV_STATUS testNbsiTable // Sanity check 2 for globSize... must be less than maximum if (pNbsiGenObj->objHdr.size > NBSI_MAX_TABLE_SIZE) { - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_NOTICE, "NBSI Gpu%d Tloc=%d/Glob=%d tbl size 0x%x > max 0x%x\n", idx, tableLoc, i, pNbsiGenObj->objHdr.size, NBSI_MAX_TABLE_SIZE); @@ -443,7 +443,7 @@ static NV_STATUS testNbsiTable // Sanity check 3 for globSize... must be less than allocated size if (bDoAllocSzCk & (pNbsiGenObj->objHdr.size > allocSize)) { - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_NOTICE, "NBSI Gpu%d Tloc=%d/Glob=%d table size 0x%x > alloc 0x%x\n", idx, tableLoc, i, pNbsiGenObj->objHdr.size, allocSize); @@ -454,7 +454,7 @@ static NV_STATUS testNbsiTable if ((pNbsiGenObj->objHdr.globType == NBSI_DRIVER) && (pNbsiDriverObj->numModules > NV2080_CTRL_BIOS_NBSI_NUM_MODULES)) { - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_NOTICE, "NBSI Gpu%d Tloc=%d/Glob=%d numModules %d > max %d\n", idx, tableLoc, i, pNbsiDriverObj->numModules, @@ -466,7 +466,7 @@ static NV_STATUS testNbsiTable if ((pNbsiGenObj->objHdr.globType != wantedGlobType) && bGlobTypeCk) { - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_NOTICE, "NBSI Gpu%d Tloc=%d/Glob=%d wantedGlobType = %04x != returned globtype = %04x\n", idx, tableLoc, i, wantedGlobType, pNbsiGenObj->objHdr.globType); @@ -493,7 +493,7 @@ static NV_STATUS testNbsiTable if (status != NV_OK) { // bad hash error message occurred in testObjectHash - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_NOTICE, "NBSI Gpu%d TLoc=%d/globType=%x bad hash\n", idx, tableLoc, pNbsiGenObj->objHdr.globType); @@ -719,7 +719,7 @@ static NvU8 checkUidMatch } } - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_INFO, "NBSI Gpu%d Tloc=%d/Glob=%d object match score/ver = (%x/%d)\n", idx, tableLoc, globNdx, score, tRev); } @@ -936,7 +936,7 @@ static NV_STATUS extractNBSIObjFromDir pNbsiGenObj = pBestDriverObjectMatch; curGlob = bestDriverObjectMatchGlob; bMyFound = NV_TRUE; - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_INFO, "NBSI Gpu%d Tloc=%d/Glob=%d best fit (score/ver = (%x/%d))\n", idx, tableLoc, bestDriverObjectMatchGlob, bestDriverObjectMatchScore, bestFitDriverVersion); @@ -991,7 +991,7 @@ static NV_STATUS allocNbsiCache pNbsiObj->pTblCache[idx] = portMemAllocNonPaged(cacheSize); if (pNbsiObj->pTblCache[idx] == NULL) { - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_WARNING, "Unable to allocate 0x%x memory for NBSI cache.\n", cacheSize); return NV_ERR_NO_MEMORY; @@ -1070,7 +1070,7 @@ static NV_STATUS addNbsiCacheEntry if (pCacheObj->pCacheEntry[cacheNdx] == NULL) { - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_WARNING, "Unable to alloc 0x%x mem for NBSI cache entry\n", szOfCacheEntry); return NV_ERR_NO_MEMORY; @@ -1081,7 +1081,7 @@ static NV_STATUS addNbsiCacheEntry if (pCacheObj->pCacheEntry[cacheNdx]->pObj == NULL) { - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_WARNING, "Unable to alloc 0x%x mem for NBSI cache entry\n", testObjSize); return NV_ERR_NO_MEMORY; @@ -1431,7 +1431,7 @@ static NV_STATUS getNbsiDirFromRegistry // do some minimal testing of first block? if (nbsiDirSize > NBSI_MAX_TABLE_SIZE) { - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_WARNING, "Emulated NBSI table too big. 0x%x > than 0x%x!\n", nbsiDirSize, NBSI_MAX_TABLE_SIZE); return NV_ERR_GENERIC; @@ -1441,7 +1441,7 @@ static NV_STATUS getNbsiDirFromRegistry *pNbsiDir = portMemAllocNonPaged(nbsiDirSize); if (*pNbsiDir == NULL) { - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_WARNING, "Can't allocate 0x%x mem for emulated NBSI table.\n", nbsiDirSize); return NV_ERR_NO_MEMORY; @@ -1454,7 +1454,7 @@ static NV_STATUS getNbsiDirFromRegistry &nbsiDirSize); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_WARNING, "Unable to read emulated NBSI table from reg.\n"); portMemFree((void*)pNbsiDir); pNbsiDir = NULL; @@ -1671,7 +1671,11 @@ static NV_STATUS nbsiObjTypeCallAcpi NvU16 acpiRtnSize = (NvU16) inOutDataSz; // curGlob fits in 15:12... so make sure we don't ask for anything higher (can happen if the SBIOS keeps sending us the same one). - NV_ASSERT_OR_RETURN((curGlob < 16), NV_ERR_INVALID_ARGUMENT); + if (curGlob >= 16) + { + NV_PRINTF(LEVEL_NOTICE, "curGlob bits do not fit in 15:12. Returning early\n"); + return NV_ERR_INVALID_ARGUMENT; + } leftToRead = *sizeToRead; *sizeToRead = 0; @@ -1761,12 +1765,10 @@ static NV_STATUS nbsiObjTypeCallUefi uefiVariableName[11] = globTypeWanted & 0xFF; uefiVariableName[12] = curGlob + (curGlob < 10 ? '0' : 'A' - 10); - status = pGpu->pOS->osGetUefiVariable(pGpu, - uefiVariableName, - (LPGUID)&NV_GUID_UEFI_VARIABLE, - inOutData, - &uefiRtnSize, - NULL); + status = osGetUefiVariable(uefiVariableName, + (LPGUID)&NV_GUID_UEFI_VARIABLE, + inOutData, + &uefiRtnSize); if (status == NV_OK) { @@ -2042,7 +2044,7 @@ static NV_STATUS getTableUsingObjTypeCall curGlob = bestDriverObjectMatchGlob; curGlobSize = bestDriverObjectMatchSize; bMyFound = NV_TRUE; - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_INFO, "NBSI Gpu%d Tloc=%d/Glob=%d best fit (score/ver = (%x/%d))\n", idx, NBSI_TBL_SOURCE_ACPI_BY_OBJ_TYPE, bestDriverObjectMatchGlob, bestDriverObjectMatchScore, @@ -2056,7 +2058,7 @@ static NV_STATUS getTableUsingObjTypeCall pNbsiDrvrObj = portMemAllocNonPaged(curGlobSize); if (pNbsiDrvrObj == NULL) { - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_WARNING, "Can't alloc 0x%x bytes for ACPI NBSI table.\n", curGlobSize); return NV_ERR_GENERIC; @@ -2482,7 +2484,7 @@ static NV_STATUS getTableUsingAllObjectCall curOffset = bestDriverObjectMatchOffset; curGlobSize = bestDriverObjectMatchSize; bMyFound = NV_TRUE; - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_INFO, "NBSI Gpu%d Tloc=%d/Glob=%d best fit (score/ver = (%x/%d))\n", idx, NBSI_TBL_SOURCE_ACPI_BY_ALL_OBJ, bestDriverObjectIndex, bestDriverObjectMatchScore, @@ -2507,7 +2509,7 @@ static NV_STATUS getTableUsingAllObjectCall pNbsiDrvrObj = portMemAllocNonPaged(curGlobSize); if (pNbsiDrvrObj == NULL) { - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_WARNING, "Can't alloc 0x%x bytes for ACPI NBSI table.\n", curGlobSize); return NV_ERR_GENERIC; @@ -2656,7 +2658,7 @@ static NV_STATUS _extractNBSIObjFromACPIDir inOutData = portMemAllocNonPaged(inOutDataSz); if (inOutData == NULL) { - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_WARNING, "Unable to allocate 0x%x bytes for ACPI parm memory.\n", inOutDataSz); status = NV_ERR_NO_MEMORY; @@ -2667,7 +2669,7 @@ static NV_STATUS _extractNBSIObjFromACPIDir tmpBuffer = portMemAllocNonPaged(tmpBufferSz); if (tmpBuffer == NULL) { - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_WARNING, "Unable to allocate 0x%x bytes for ACPI parm memory.\n", tmpBufferSz); status = NV_ERR_NO_MEMORY; @@ -2837,7 +2839,7 @@ NV_STATUS getNbsiObjByType idx = gpuGetInstance(pGpu); if (idx >= NV_MAX_DEVICES) { - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_NOTICE, "Invalid gpu index %d. Aborting NBSI get object.\n", idx); return NV_ERR_GENERIC; @@ -3176,13 +3178,13 @@ NV_STATUS initNbsiTable(OBJGPU *pGpu) idx = gpuGetInstance(pGpu); if (idx >= NV_MAX_DEVICES) { - NV_PRINTF(LEVEL_ERROR, "Invalid gpu index %d. Aborting NBSI init.\n", idx); + NV_PRINTF(LEVEL_WARNING, "Invalid gpu index %d. Aborting NBSI init.\n", idx); return NV_ERR_GENERIC; } if (pNbsiObj->nbsiDrvrTable[idx] != NULL) { - NV_PRINTF(LEVEL_ERROR, "NBSI table already initialized for GPU index %d. Aborting NBSI init.\n", idx); + NV_PRINTF(LEVEL_NOTICE, "NBSI table already initialized for GPU index %d. Aborting NBSI init.\n", idx); return NV_WARN_NOTHING_TO_DO; } @@ -3346,7 +3348,7 @@ void freeNbsiTable(OBJGPU *pGpu) if (idx >= NV_MAX_DEVICES) { - NV_PRINTF(LEVEL_ERROR, + NV_PRINTF(LEVEL_WARNING, "Invalid gpu index %d. Aborting free NBSI table.\n", idx); return; diff --git a/src/nvidia/src/kernel/platform/p2p/p2p_caps.c b/src/nvidia/src/kernel/platform/p2p/p2p_caps.c index 9591e74d30..3a3408b3cc 100644 --- a/src/nvidia/src/kernel/platform/p2p/p2p_caps.c +++ b/src/nvidia/src/kernel/platform/p2p/p2p_caps.c @@ -21,9 +21,6 @@ * DEALINGS IN THE SOFTWARE. */ -// FIXME XXX -#define NVOC_KERNEL_NVLINK_H_PRIVATE_ACCESS_ALLOWED - #include "core/system.h" #include "gpu_mgr/gpu_mgr.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" @@ -564,44 +561,21 @@ _p2pCapsGetHostSystemStatusOverPcieBar1 ) { OBJSYS *pSys = SYS_GET_INSTANCE(); - NvU32 cpuFamily = DRF_VAL(0000_CTRL, _SYSTEM, _CPU_FAMILY, pSys->cpuInfo.family); - if (bCommonPciSwitchFound) - { - // Both of GPUs are on the same PCIE switch - *pP2PWriteCapStatus = NV0000_P2P_CAPS_STATUS_OK; - *pP2PReadCapStatus = NV0000_P2P_CAPS_STATUS_OK; - - NV_PRINTF(LEVEL_INFO, "A common switch detected\n"); - } - else if (cpuFamily == NV0000_CTRL_SYSTEM_CPU_ID_AMD_FAMILY) - { - *pP2PWriteCapStatus = NV0000_P2P_CAPS_STATUS_OK; - - if (pSys->cpuInfo.type == NV0000_CTRL_SYSTEM_CPU_TYPE_RYZEN) - *pP2PReadCapStatus = NV0000_P2P_CAPS_STATUS_OK; - else - *pP2PReadCapStatus = NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED; + *pP2PWriteCapStatus = NV0000_P2P_CAPS_STATUS_OK; - NV_PRINTF(LEVEL_INFO, "AMD CPU detected\n"); - } - else if (cpuFamily == NV0000_CTRL_SYSTEM_CPU_ID_INTEL_FAMILY) + if (bCommonPciSwitchFound || + (pSys->cpuInfo.type == NV0000_CTRL_SYSTEM_CPU_TYPE_RYZEN) || + (pSys->cpuInfo.type == NV0000_CTRL_SYSTEM_CPU_TYPE_XEON_SPR)) { - *pP2PWriteCapStatus = NV0000_P2P_CAPS_STATUS_OK; - *pP2PReadCapStatus = NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED; - - NV_PRINTF(LEVEL_INFO, "Intel CPU detected\n"); + *pP2PReadCapStatus = NV0000_P2P_CAPS_STATUS_OK; } else { - *pP2PWriteCapStatus = NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED; - *pP2PReadCapStatus = NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED; - - NV_PRINTF(LEVEL_INFO, "Unsupported HW config\n"); + *pP2PReadCapStatus = NV0000_P2P_CAPS_STATUS_CHIPSET_NOT_SUPPORTED; + NV_PRINTF(LEVEL_INFO, "Unrecognized CPU. Read Cap is disabled\n"); } - NV_PRINTF(LEVEL_INFO, "WriteCap 0x%x ReadCap 0x%x\n", *pP2PWriteCapStatus, *pP2PReadCapStatus); - return NV_OK; } @@ -637,6 +611,13 @@ _kp2pCapsGetStatusOverPcieBar1 return NV_ERR_NOT_SUPPORTED; } + // Check if any overrides are enabled. + if (_kp2pCapsCheckStatusOverridesForPcie(gpuMask, pP2PWriteCapStatus, + pP2PReadCapStatus)) + { + return NV_OK; + } + // // Re-initialize to check loop back configuration if only single GPU in // requested mask. @@ -661,10 +642,10 @@ _kp2pCapsGetStatusOverPcieBar1 if (*pP2PReadCapStatus == NV0000_P2P_CAPS_STATUS_OK) *pP2PReadCapStatus = readCapStatus; - if ((*pP2PReadCapStatus != NV0000_P2P_CAPS_STATUS_OK) && + if ((*pP2PReadCapStatus != NV0000_P2P_CAPS_STATUS_OK) || (*pP2PWriteCapStatus != NV0000_P2P_CAPS_STATUS_OK)) { - // return not supported if it does not support any operation + // return not supported if it does not support both operations return NV_ERR_NOT_SUPPORTED; } @@ -740,7 +721,7 @@ p2pGetCapsStatus while ((pGpu = gpumgrGetNextGpu(gpuMask, &gpuInstance)) != NULL) { pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); - if (pKernelNvlink != NULL && pKernelNvlink->discoveredLinks != 0 && + if (pKernelNvlink != NULL && knvlinkGetDiscoveredLinkMask(pGpu, pKernelNvlink) != 0 && (pSys->getProperty(pSys, PDB_PROP_SYS_NVSWITCH_IS_PRESENT) || knvlinkIsNvswitchProxyPresent(pGpu, pKernelNvlink) || GPU_IS_NVSWITCH_DETECTED(pGpu))) diff --git a/src/nvidia/src/kernel/platform/platform_request_handler.c b/src/nvidia/src/kernel/platform/platform_request_handler.c index e2f5edaa80..1008e0dab1 100644 --- a/src/nvidia/src/kernel/platform/platform_request_handler.c +++ b/src/nvidia/src/kernel/platform/platform_request_handler.c @@ -84,7 +84,7 @@ pfmreqhndlrInitGpu // Invalid GPU configuration if (gpuCount < 1 || gpuCount > PFM_REQ_HNDLR_MAX_GPU_SUPPORTED) { - NV_PRINTF(LEVEL_ERROR, "PLATFORM_REQUEST_HANDLER: Cannot support %u GPUs yet\n", gpuCount); + NV_PRINTF(LEVEL_INFO, "PLATFORM_REQUEST_HANDLER: Cannot support %u GPUs yet\n", gpuCount); } else { @@ -773,39 +773,54 @@ _pfmreqhndlrSupportExists OBJGPU *pGpu ) { - NvU64 supportedFunction = 0; - NvU16 outDataSize = 0; + NvU16 outDataSize = 0U; + NV_STATUS status = NV_OK; + NvU8 supportFuncs[MAX_DSM_SUPPORTED_FUNCS_RTN_LEN]; + NvU8 i; if (pPlatformRequestHandler->dsmVersion == ACPI_DSM_FUNCTION_INVALID) { - return NV_ERR_NOT_SUPPORTED; + status = NV_ERR_NOT_SUPPORTED; + goto _pfmreqhndlrSupportExists_exit; } - outDataSize = sizeof(supportedFunction); + portMemSet(supportFuncs, 0, sizeof(supportFuncs)); + outDataSize = sizeof(supportFuncs); if (osCallACPI_DSM(pGpu, pPlatformRequestHandler->dsmVersion, GPS_FUNC_SUPPORT, - (NvU32 *)&supportedFunction, + (NvU32 *)&supportFuncs, &outDataSize) != NV_OK) { NV_PRINTF(LEVEL_ERROR, "GPS FUNC_SUPPORT is not supported on this Platform, Failing ACPI-GPS subfunction 0x%x.\n", GPS_FUNC_SUPPORT); - return NV_ERR_NOT_SUPPORTED; + status = NV_ERR_NOT_SUPPORTED; + goto _pfmreqhndlrSupportExists_exit; } else { - if (supportedFunction == 0) + for (i = 0; i < MAX_DSM_SUPPORTED_FUNCS_RTN_LEN; i++) { - NV_PRINTF(LEVEL_INFO, - "PRH : This system doesn't support any ACPI-GPS-subfunctions.\n"); - return NV_ERR_NOT_SUPPORTED; + if (supportFuncs[i] != 0) + { + // Atleast one subfunction is enabled for PRH, platform support exists for PRH + status = NV_OK; + goto _pfmreqhndlrSupportExists_exit; + } } + + // None of the subfunctions are enabled for PRH, no platform support exists for PRH + NV_PRINTF(LEVEL_INFO, + "PRH : This system doesn't support any ACPI-GPS-subfunctions.\n"); + status = NV_ERR_NOT_SUPPORTED; + goto _pfmreqhndlrSupportExists_exit; } - return NV_OK; +_pfmreqhndlrSupportExists_exit: + return status; } /*! diff --git a/src/nvidia/src/kernel/platform/platform_request_handler_ctrl.c b/src/nvidia/src/kernel/platform/platform_request_handler_ctrl.c index af913ef15d..8bba2fd6e2 100644 --- a/src/nvidia/src/kernel/platform/platform_request_handler_ctrl.c +++ b/src/nvidia/src/kernel/platform/platform_request_handler_ctrl.c @@ -254,7 +254,6 @@ pfmreqhndlrOperatingLimitUpdate_IMPL { NV_STATUS status = NV_OK; OBJGPU *pGpu = pfmreqhndlrGetGpu(pPlatformRequestHandler); - OBJOS *pOs = GPU_GET_OS(pGpu); if (id >= PFM_REQ_HNDLR_PSHAREPARAMS_COUNT) { @@ -302,7 +301,7 @@ pfmreqhndlrOperatingLimitUpdate_IMPL // if (!pPlatformRequestHandler->sysControlData.bWorkItemPending) { - status = pOs->osQueueWorkItem(pGpu, + status = osQueueWorkItem(pGpu, _pfmreqhndlrUpdateSystemParamLimitWorkItem, NULL); if (status != NV_OK) @@ -722,10 +721,9 @@ cliresCtrlCmdSystemPfmreqhndlrCtrl_IMPL status = NV_ERR_BUSY_RETRY; if (!pPlatformRequestHandler->ppmData.bWorkItemPending) { - OBJOS *pOS = GPU_GET_OS(pGpu); pPlatformRequestHandler->ppmData.ppmIdxRequested = clientPpmIdx; // Create a workItem to change Platform Power Mode - status = pOS->osQueueWorkItem(pGpu, _pfmreqhndlrUpdatePlatformPowerModeWorkItem, NULL); + status = osQueueWorkItem(pGpu, _pfmreqhndlrUpdatePlatformPowerModeWorkItem, NULL); if (status == NV_OK) { // Queing workitem succeeded, mark it as pending. @@ -1336,6 +1334,7 @@ pfmreqhndlrSampleCounter case PFM_REQ_HNDLR_VPS_PS20_SUPPORT: { _pfmreqhndlrUpdateCounter(pPfmreqhndlrData, PFM_REQ_HNDLR_VPS_PS20_SUPPORT, NV_TRUE, pPlatformRequestHandler->vPstateCache.bVpsPs20Supported, timeStamp); + break; } case PFM_REQ_HNDLR_TC_ENABLE: { @@ -1762,10 +1761,8 @@ pfmreqhndlrHandlePlatformSetEdppLimitInfo_IMPL if (!pEdppLimit->bWorkItemPending) { - OBJOS *pOS = GPU_GET_OS(pGpu); - // Queue workitem to send the EDP limit info to platform - status = pOS->osQueueWorkItem(pGpu, + status = osQueueWorkItem(pGpu, _pfmreqhndlrHandlePlatformSetEdppLimitInfoWorkItem, NULL); if(status == NV_OK) { diff --git a/src/nvidia/src/kernel/platform/sli/sli.c b/src/nvidia/src/kernel/platform/sli/sli.c index 3cd89ef393..536965bcad 100644 --- a/src/nvidia/src/kernel/platform/sli/sli.c +++ b/src/nvidia/src/kernel/platform/sli/sli.c @@ -190,13 +190,15 @@ static NvU32 RmRunSLISupportCheck // RMCONFIG: is SLI enabled in this build? + OBJSYS *pSys = SYS_GET_INSTANCE(); + if (IS_VIRTUAL(pGpu) || IS_GSP_CLIENT(pGpu)) { gpuSliStatus |= NV0000_CTRL_SLI_STATUS_GPU_NOT_SUPPORTED; // Detect SLI link before failing on GSP client RM if (!IS_GSP_CLIENT(pGpu)) - goto done; + goto fail; } // get gpu attach info @@ -207,7 +209,20 @@ static NvU32 RmRunSLISupportCheck { // Do not cache this status in pGpu->sliStatus as it is dependent on the GPU count gpuSliStatus |= NV0000_CTRL_SLI_STATUS_INVALID_GPU_COUNT; - goto done; + goto fail; + } + + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + + // Do not run the SLI check with NVSwitch + if ((pSys->getProperty(pSys, PDB_PROP_SYS_NVSWITCH_IS_PRESENT) || + ((pKernelNvlink != NULL) && + ((GPU_IS_NVSWITCH_DETECTED(pGpu)) || + knvlinkIsNvswitchProxyPresent(pGpu, pKernelNvlink)))) && + pSys->getProperty(pSys, PDB_PROP_SYS_FABRIC_IS_EXTERNALLY_MANAGED)) + { + gpuSliStatus |= NV0000_CTRL_SLI_STATUS_GPU_NOT_SUPPORTED; + goto fail; } // For 9 GPUs and above, we do not check the SLI configs @@ -231,6 +246,11 @@ static NvU32 RmRunSLISupportCheck pGpu->sliStatus = gpuSliStatus; } } +goto done; + +fail: + pGpu->sliStatus = gpuSliStatus; + done: NV_PRINTF(LEVEL_INFO, "gpuSliStatus 0x%x\n", gpuSliStatus); diff --git a/src/nvidia/src/kernel/power/gpu_boost_mgr.c b/src/nvidia/src/kernel/power/gpu_boost_mgr.c index 1d881dee24..a3dcb1ab31 100644 --- a/src/nvidia/src/kernel/power/gpu_boost_mgr.c +++ b/src/nvidia/src/kernel/power/gpu_boost_mgr.c @@ -667,6 +667,8 @@ _gpuboostmgrApplyPolicyFilters(NV0000_SYNC_GPU_BOOST_GROUP_CONFIG *pBoostConfig) for (i = 0; i < pBoostConfig->gpuCount; i++) { pGpuItr = gpumgrGetGpuFromId(pBoostConfig->gpuIds[i]); + NV_ASSERT_OR_RETURN(NULL != pGpuItr, NV_ERR_OBJECT_NOT_FOUND); + if (IsUnlinkedSLIEnabled(pGpuItr)) { continue; @@ -724,6 +726,7 @@ _gpuboostmgrApplyPolicyFilters(NV0000_SYNC_GPU_BOOST_GROUP_CONFIG *pBoostConfig) NvU16 subDeviceItr = 0; pGpuItr = gpumgrGetGpuFromId(pBoostConfig->gpuIds[i]); + NV_ASSERT_OR_RETURN(NULL != pGpuItr, NV_ERR_OBJECT_NOT_FOUND); // Extract values for the GPU in the iteration. { diff --git a/src/nvidia/src/kernel/rmapi/alloc_free.c b/src/nvidia/src/kernel/rmapi/alloc_free.c index 0dd98174fd..4d4e0ef3c2 100644 --- a/src/nvidia/src/kernel/rmapi/alloc_free.c +++ b/src/nvidia/src/kernel/rmapi/alloc_free.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -215,40 +215,33 @@ serverAllocApiCopyOut return status; } -NV_STATUS -serverLookupSecondClient +NvHandle +serverAllocLookupSecondClient ( - RS_RES_ALLOC_PARAMS_INTERNAL *pParams, - NvHandle *phClient + NvU32 externalClassId, + void *pAllocParams ) { - *phClient = 0; - - switch (pParams->externalClassId) + if (pAllocParams != NULL) { - case GT200_DEBUGGER: - { - NV83DE_ALLOC_PARAMETERS *pNv83deParams = pParams->pAllocParams; - - if (pNv83deParams->hAppClient != pParams->hClient) - *phClient = pNv83deParams->hAppClient; - - break; - } - case UVM_CHANNEL_RETAINER: + switch (externalClassId) { - NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS *pUvmChannelRetainerParams = pParams->pAllocParams; - - if (pUvmChannelRetainerParams->hClient != pParams->hClient) - *phClient = pUvmChannelRetainerParams->hClient; - - break; + case GT200_DEBUGGER: + { + return ((NV83DE_ALLOC_PARAMETERS *) pAllocParams)->hAppClient; + break; + } + case UVM_CHANNEL_RETAINER: + { + return ((NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS *) pAllocParams)->hClient; + break; + } + default: + break; } - default: - break; } - return NV_OK; + return NV01_NULL_OBJECT; } NV_STATUS @@ -622,8 +615,45 @@ _fixupAllocParams return NV_OK; } -static -NV_STATUS +static NV_STATUS +_serverAlloc_ValidateVgpu +( + RsClient *pClient, + NvU32 hParent, + NvU32 externalClassId, + RS_PRIV_LEVEL privLevel, + const NvU32 flags +) +{ + // + // Get any GPU to check environmental properties + // Assume: In multi-vGPU systems, no mix and matching SRIOV and non-SRIOV GPUs. + // Assume: This POBJGPU will only used to read system properties. + // + OBJGPU *pGpu = gpumgrGetSomeGpu(); + + // Check whether context is already sufficiently privileged + if (flags & RS_FLAGS_ALLOC_PRIVILEGED) + { + if (privLevel >= RS_PRIV_LEVEL_USER_ROOT) + { + return NV_TRUE; + } + } + + // Check whether object is allowed in current environment + if + ( + (IS_SRIOV_WITH_VGPU_GSP_ENABLED(pGpu) && (flags & RS_FLAGS_ALLOC_CPU_PLUGIN_FOR_VGPU_GSP)) + ) + { + return NV_TRUE; + } + + return NV_FALSE; +} + +static NV_STATUS _serverAllocValidatePrivilege ( RsServer *pServer, @@ -631,25 +661,36 @@ _serverAllocValidatePrivilege RS_RES_ALLOC_PARAMS *pParams ) { - if (hypervisorIsVgxHyper()) + RsClient *pClient = pParams->pClient; + + // Reject allocations for objects with no flags. + if (!(pResDesc->flags & RS_FLAGS_ALLOC_NON_PRIVILEGED) && + !(pResDesc->flags & RS_FLAGS_ALLOC_PRIVILEGED) && + !(pResDesc->flags & RS_FLAGS_ALLOC_KERNEL_PRIVILEGED)) { - // Host CPU-RM context - // Don't check here, allow it to pass to the inline constructor check. - // TODO: GPUSWSEC-1552 Hypervisor + // See GPUSWSEC-1560 for more details on object privilege flag requirements + NV_PRINTF(LEVEL_WARNING, "external class 0x%08x is missing its privilege flag in RS_ENTRY\n", pParams->externalClassId); + return NV_ERR_INSUFFICIENT_PERMISSIONS; } - else - { - RS_PRIV_LEVEL privLevel = pParams->pSecInfo->privLevel; - // Reject allocations for objects with no flags. - if (!(pResDesc->flags & RS_FLAGS_ALLOC_NON_PRIVILEGED) && - !(pResDesc->flags & RS_FLAGS_ALLOC_PRIVILEGED) && - !(pResDesc->flags & RS_FLAGS_ALLOC_KERNEL_PRIVILEGED)) + if (hypervisorIsVgxHyper() && + clientIsAdmin(pClient, clientGetCachedPrivilege(pClient)) && + (pParams->pSecInfo->privLevel != RS_PRIV_LEVEL_KERNEL) && + !(pResDesc->flags & RS_FLAGS_ALLOC_NON_PRIVILEGED)) + { + // Host CPU-RM context + if (!_serverAlloc_ValidateVgpu(pClient, pParams->hParent, pParams->externalClassId, + pParams->pSecInfo->privLevel, pResDesc->flags)) { - // See GPUSWSEC-1560 for more details on privilege flag requirements - NV_PRINTF(LEVEL_WARNING, "external class 0x%08x is missing its privilege flag in RS_ENTRY\n", pParams->externalClassId); + NV_PRINTF(LEVEL_WARNING, + "hClient: 0x%08x, externalClassId: 0x%08x: CPU hypervisor does not have permission to allocate object\n", + pParams->hClient, pParams->externalClassId); return NV_ERR_INSUFFICIENT_PERMISSIONS; } + } + else + { + RS_PRIV_LEVEL privLevel = pParams->pSecInfo->privLevel; // Default case, verify admin and kernel privileges if (pResDesc->flags & RS_FLAGS_ALLOC_PRIVILEGED) @@ -728,7 +769,10 @@ serverAllocResourceUnderLock if (pRmAllocParams->hResource == hClient) { if (pResDesc->pParentList[i] != 0) + { status = NV_ERR_INVALID_OBJECT_PARENT; + goto done; + } hParent = 0; // Single instance restriction is implied @@ -1158,6 +1202,7 @@ rmapiAllocWithSecInfo NvU32 allocInitStates = RM_ALLOC_STATES_NONE; RM_API_CONTEXT rmApiContext = {0}; RS_LOCK_INFO *pLockInfo; + NvHandle hSecondClient = NV01_NULL_OBJECT; status = rmapiPrologue(pRmApi, &rmApiContext); if (status != NV_OK) @@ -1170,8 +1215,16 @@ rmapiAllocWithSecInfo goto done; } + if (pSecInfo->paramLocation == PARAM_LOCATION_KERNEL) + { + hSecondClient = serverAllocLookupSecondClient(hClass, + NvP64_VALUE(pAllocParams)); + } + portMemSet(pLockInfo, 0, sizeof(*pLockInfo)); - rmapiInitLockInfo(pRmApi, hClient, pLockInfo); + status = rmapiInitLockInfo(pRmApi, hClient, hSecondClient, pLockInfo); + if (status != NV_OK) + goto done; // RS-TODO: Fix calls that use RMAPI_GPU_LOCK_INTERNAL without holding the API lock if (pRmApi->bGpuLockInternal && !rmapiLockIsOwner()) @@ -1398,7 +1451,12 @@ rmapiFreeWithSecInfo return status; portMemSet(&lockInfo, 0, sizeof(lockInfo)); - rmapiInitLockInfo(pRmApi, hClient, &lockInfo); + status = rmapiInitLockInfo(pRmApi, hClient, NV01_NULL_OBJECT, &lockInfo); + if (status != NV_OK) + { + rmapiEpilogue(pRmApi, &rmApiContext); + return status; + } // RS-TODO: Fix calls that use RMAPI_GPU_LOCK_INTERNAL without holding the API lock if (pRmApi->bGpuLockInternal && !rmapiLockIsOwner()) @@ -1537,7 +1595,7 @@ serverRwApiLockIsOwner RsServer *pServer ) { - return rmapiLockIsOwner(); + return rmapiLockIsWriteOwner(); } NV_STATUS diff --git a/src/nvidia/src/kernel/rmapi/client.c b/src/nvidia/src/kernel/rmapi/client.c index c253a54fe9..2fbbe988a2 100644 --- a/src/nvidia/src/kernel/rmapi/client.c +++ b/src/nvidia/src/kernel/rmapi/client.c @@ -66,6 +66,9 @@ rmclientConstruct_IMPL API_SECURITY_INFO *pSecInfo = pParams->pSecInfo; OBJGPU *pGpu = NULL; + // RM client objects can only be created/destroyed with the RW API lock. + LOCK_ASSERT_AND_RETURN(rmapiLockIsWriteOwner()); + if (RMCFG_FEATURE_PLATFORM_GSP) { pGpu = gpumgrGetSomeGpu(); @@ -87,12 +90,14 @@ rmclientConstruct_IMPL // TODO: Revisit in M2, see GPUSWSEC-1176 if (RMCFG_FEATURE_PLATFORM_GSP && IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)) { - if (pSecInfo->pProcessToken != NULL && ((NvU64) pSecInfo->pProcessToken) < VMMU_MAX_GFID) + if (pSecInfo->pProcessToken != NULL && + ((NvU64) pSecInfo->pProcessToken) < VMMU_MAX_GFID) { // Trunc to NvU32 to fit ProcID (VMMU_MAX_GFID << MAX_INT) pClient->ProcID = (NvU32)((NvU64)pSecInfo->pProcessToken); - NV_PRINTF(LEVEL_INFO, "Client allocation with GFID = %u\n", (NvU32)((NvU64)pSecInfo->pProcessToken)); + NV_PRINTF(LEVEL_INFO, "Client allocation with GFID = %u\n", + (NvU32)((NvU64)pSecInfo->pProcessToken)); } } else @@ -225,12 +230,10 @@ rmclientDestruct_IMPL ) { NV_STATUS status = NV_OK; - RsClient *pRsClient = staticCast(pClient, RsClient); - NV_STATUS tmpStatus; - NvHandle hClient = pRsClient->hClient; NvBool bReleaseLock = NV_FALSE; - RS_ITERATOR it; - RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + // RM client objects can only be created/destroyed with the RW API lock. + NV_ASSERT(rmapiLockIsWriteOwner()); NV_PRINTF(LEVEL_INFO, " type: client\n"); @@ -241,26 +244,6 @@ rmclientDestruct_IMPL osPutPidInfo(pClient->pOsPidInfo); - // - // Free all of the devices of the client (do it in reverse order to - // facilitate tear down of things like ctxdmas, etc) - // - it = clientRefIter(pRsClient, NULL, classId(Device), RS_ITERATE_CHILDREN, NV_TRUE); - while (clientRefIterNext(it.pClient, &it)) - { - Device *pDeviceInfo = dynamicCast(it.pResourceRef->pResource, Device); - - // This path is deprecated. - NV_ASSERT(0); - - tmpStatus = pRmApi->Free(pRmApi, hClient, RES_GET_HANDLE(pDeviceInfo)); - if ((tmpStatus != NV_OK) && (status == NV_OK)) - status = tmpStatus; - - // re-snap iterator as Device list was mutated - it = clientRefIter(pRsClient, NULL, classId(Device), RS_ITERATE_CHILDREN, NV_TRUE); - } - // Updating the client list just before client handle unregister // // in case child free functions need to iterate over all clients // if (!rmGpuLockIsOwner()) @@ -577,6 +560,12 @@ NvBool rmclientIsAdminByHandle(NvHandle hClient, RS_PRIV_LEVEL privLevel) return pClient ? rmclientIsAdmin(pClient, privLevel) : NV_FALSE; } +NvBool rmclientIsKernelOnlyByHandle(NvHandle hClient) +{ + RmClient *pClient = serverutilGetClientUnderLock(hClient); + return pClient ? (pClient->pSecurityToken == NULL) : NV_FALSE; +} + NvBool rmclientSetClientFlagsByHandle(NvHandle hClient, NvU32 clientFlags) { RmClient *pClient = serverutilGetClientUnderLock(hClient); diff --git a/src/nvidia/src/kernel/rmapi/client_resource.c b/src/nvidia/src/kernel/rmapi/client_resource.c index 2c443a2d72..dc898ca791 100644 --- a/src/nvidia/src/kernel/rmapi/client_resource.c +++ b/src/nvidia/src/kernel/rmapi/client_resource.c @@ -1,6 +1,6 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -1116,6 +1116,36 @@ cliresCtrlCmdSystemSetMemorySize_IMPL return NV_OK; } +// +// cliresCtrlCmdSystemGetLockTimes +// +// Get API and GPU lock hold/wait times. +// +// Lock Requirements: +// None +// +NV_STATUS +cliresCtrlCmdSystemGetLockTimes_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + + // Check if lock time collection is enabled first + if (!pSys->getProperty(pSys, PDB_PROP_SYS_RM_LOCK_TIME_COLLECT)) + return NV_ERR_NOT_SUPPORTED; + + // Fetch API lock hold/wait times + rmapiLockGetTimes(pParams); + + // Fetch GPU lock hold/wait times + rmGpuLockGetTimes(pParams); + + return NV_OK; +} + static NV_STATUS classGetSystemClasses(NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS *pParams) { @@ -1403,6 +1433,25 @@ cliresCtrlCmdGpuGetDeviceIds_IMPL return NV_OK; } +// +// cliresCtrlCmdGpuGetActiveDeviceIds +// +// Lock Requirements: +// Assert that API lock held on entry +// No GPUs lock +// +NV_STATUS +cliresCtrlCmdGpuGetActiveDeviceIds_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS *pActiveDeviceIdsParams +) +{ + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); + + return gpumgrCacheGetActiveDeviceIds(pActiveDeviceIdsParams); +} + // // cliresCtrlCmdGpuGetPciInfo // @@ -1942,7 +1991,6 @@ cliresCtrlCmdGpuAcctGetAccountingPids_IMPL return gpuacctGetAcctPids(pGpuAcct, pAcctPidsParams); } - NV_STATUS cliresCtrlCmdSystemPfmreqhndlrControl_IMPL ( @@ -2575,7 +2623,7 @@ _validateConfigStaticTable_2x { NV_STATUS status = NV_OK; NvU8 checkSum; - NvU8 idx; + NvU16 idx; NV_ASSERT_OR_RETURN(pData != NULL, NV_ERR_INVALID_POINTER); NV_ASSERT_OR_RETURN(pDataSize != NULL, NV_ERR_INVALID_POINTER); @@ -2756,7 +2804,7 @@ cliresCtrlCmdSystemNVPCFGetPowerModeInfo_IMPL DYNAMIC_PARAMS_HEADER_2X headerOut = { 0 }; DYNAMIC_PARAMS_COMMON_2X commonOut = { 0 }; DYNAMIC_PARAMS_ENTRY_2X entriesOut = { 0 }; - NvU8 idx; + NvU32 idx; const char *pSzHeaderFmt = NVPCF_DYNAMIC_PARAMS_2X_HEADER_FMT_SIZE_05; @@ -4385,7 +4433,7 @@ cliresCtrlCmdNvdGetRcerrRpt_IMPL // Note that this will result in clients receivinga rptIdx value // larger than MAX_RCDB_RCDIAG_WRAP_BUFF. // - NvU16 indexOffset = gpuIdx * MAX_RCDB_RCDIAG_WRAP_BUFF; + NvU16 indexOffset = pGpu->gpuInstance * MAX_RCDB_RCDIAG_WRAP_BUFF; *pParams = *pLocalParams; pParams->startIdx += indexOffset; @@ -4616,4 +4664,3 @@ cliresCtrlCmdSystemGetExtendedPerfSensorCounters_IMPL { return NV_OK; } - diff --git a/src/nvidia/src/kernel/rmapi/control.c b/src/nvidia/src/kernel/rmapi/control.c index 59c3bb20b8..f7989fe822 100644 --- a/src/nvidia/src/kernel/rmapi/control.c +++ b/src/nvidia/src/kernel/rmapi/control.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2004-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -620,10 +620,29 @@ _rmapiRmControl(NvHandle hClient, NvHandle hObject, NvU32 cmd, NvP64 pUserParams RM_API_CONTEXT rmApiContext = {0}; rmStatus = rmapiPrologue(pRmApi, &rmApiContext); if (rmStatus != NV_OK) - goto done; + goto epilogue; + + // + // If this is an internal request within the same RM instance, make + // sure we don't double lock clients and preserve previous lock state. + // + if (bInternalRequest && resservGetTlsCallContext() != NULL) + { + rmStatus = rmapiInitLockInfo(pRmApi, hClient, NV01_NULL_OBJECT, &lockInfo); + if (rmStatus != NV_OK) + goto epilogue; + + // + // rmapiInitLockInfo overwrites lockInfo.flags, re-add + // RM_LOCK_FLAGS_NO_API_LOCK if it was originally added. + // + if (pRmApi->bApiLockInternal) + lockInfo.flags |= RM_LOCK_FLAGS_NO_API_LOCK; + } lockInfo.flags |= RM_LOCK_FLAGS_RM_SEMA; rmStatus = serverControl(&g_resServ, &rmCtrlParams); +epilogue: rmapiEpilogue(pRmApi, &rmApiContext); } done: @@ -837,12 +856,10 @@ serverControlLookupLockFlags { // // Calls with LOCK_TOP doesn't fill in the cookie param correctly. - // This is just a WAR for this. Since the optimisation that depends on this - // flag only works in full GSP offload mode, it's gated to that. + // This is just a WAR for this. // - NvBool areAllGpusInOffloadMode = gpumgrAreAllGpusInOffloadMode(); NvU32 controlFlags = pRmCtrlExecuteCookie->ctrlFlags; - if (controlFlags == 0 && !RMCFG_FEATURE_PLATFORM_GSP && areAllGpusInOffloadMode) + if (controlFlags == 0 && !RMCFG_FEATURE_PLATFORM_GSP) { NV_STATUS status = rmapiutilGetControlInfo(pRmCtrlParams->cmd, &controlFlags, NULL); if (status != NV_OK) @@ -853,6 +870,8 @@ serverControlLookupLockFlags } } + NvBool areAllGpusInOffloadMode = gpumgrAreAllGpusInOffloadMode(); + // // If the control is ROUTE_TO_PHYSICAL, and we're in GSP offload mode, // we can use a more relaxed locking mode: diff --git a/src/nvidia/src/kernel/rmapi/embedded_param_copy.c b/src/nvidia/src/kernel/rmapi/embedded_param_copy.c index fb7d35996c..53cb82f1ff 100644 --- a/src/nvidia/src/kernel/rmapi/embedded_param_copy.c +++ b/src/nvidia/src/kernel/rmapi/embedded_param_copy.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/nvidia/src/kernel/rmapi/event.c b/src/nvidia/src/kernel/rmapi/event.c index 5ebc0854b1..b561673908 100644 --- a/src/nvidia/src/kernel/rmapi/event.c +++ b/src/nvidia/src/kernel/rmapi/event.c @@ -285,9 +285,11 @@ NV_STATUS notifyUnregisterEvent_IMPL // host, if we are in guest OS (where IS_VIRTUAL(pGpu) is true), // do an RPC to the host to do the hardware update. // - if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu) || + if ( + !(IS_GSP_CLIENT(pGpu) && (pNotifierRef->internalClassId == classId(KernelHostVgpuDeviceApi))) && + (IS_VIRTUAL_WITHOUT_SRIOV(pGpu) || (IS_GSP_CLIENT(pGpu) && pNotifierRef->internalClassId != classId(ContextDma)) || - (IS_VIRTUAL_WITH_SRIOV(pGpu) && !((*ppEventNotification)->bNonStallIntrEvent))) + (IS_VIRTUAL_WITH_SRIOV(pGpu) && !((*ppEventNotification)->bNonStallIntrEvent)))) { // // In SR-IOV enabled systems, nonstall events are registered diff --git a/src/nvidia/src/kernel/rmapi/event_notification.c b/src/nvidia/src/kernel/rmapi/event_notification.c index 53b33d62f3..97187e0705 100644 --- a/src/nvidia/src/kernel/rmapi/event_notification.c +++ b/src/nvidia/src/kernel/rmapi/event_notification.c @@ -542,8 +542,8 @@ eventGetEngineTypeFromSubNotifyIndex case NV2080_NOTIFIERS_NVJPEG7: *pRmEngineId = RM_ENGINE_TYPE_NVJPEG7; break; - case NV2080_NOTIFIERS_OFA: - *pRmEngineId = RM_ENGINE_TYPE_OFA; + case NV2080_NOTIFIERS_OFA0: + *pRmEngineId = RM_ENGINE_TYPE_OFA0; break; default: NV_PRINTF(LEVEL_WARNING, @@ -618,7 +618,8 @@ NV_STATUS registerEventNotification MIG_INSTANCE_REF ref; NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_ERROR, - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hEventClient, &ref), + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + GPU_RES_GET_DEVICE(pSubDevice), &ref), free_entry); NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_ERROR, @@ -827,7 +828,8 @@ NV_STATUS unregisterEventNotificationWithData MIG_INSTANCE_REF ref; NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_ERROR, - kmigmgrGetInstanceRefFromClient(pGpu, pKernelMIGManager, hEventClient, &ref), + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, + GPU_RES_GET_DEVICE(pSubDevice), &ref), free_entry); NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_ERROR, diff --git a/src/nvidia/src/kernel/rmapi/mapping.c b/src/nvidia/src/kernel/rmapi/mapping.c index 720c4bf8b4..0ebeb5ff62 100644 --- a/src/nvidia/src/kernel/rmapi/mapping.c +++ b/src/nvidia/src/kernel/rmapi/mapping.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -85,6 +85,7 @@ serverInterMap_Prologue return NV_ERR_INVALID_OBJECT; pGpu = GPU_RES_GET_GPU(pSubdevice); + pDevice = GPU_RES_GET_DEVICE(pSubdevice); GPU_RES_SET_THREAD_BC_STATE(pSubdevice); hBroadcastDevice = RES_GET_HANDLE(pSubdevice->pDevice); @@ -121,7 +122,7 @@ serverInterMap_Prologue } NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - virtmemReserveMempool(pVirtualMemory, pGpu, hBroadcastDevice, + virtmemReserveMempool(pVirtualMemory, pGpu, pDevice, pParams->length, pageSize)); } } @@ -378,7 +379,13 @@ rmapiMapWithSecInfo return status; portMemSet(&lockInfo, 0, sizeof(lockInfo)); - rmapiInitLockInfo(pRmApi, hClient, &lockInfo); + status = rmapiInitLockInfo(pRmApi, hClient, NV01_NULL_OBJECT, &lockInfo); + if (status != NV_OK) + { + rmapiEpilogue(pRmApi, &rmApiContext); + return status; + } + lockInfo.flags |= RM_LOCK_FLAGS_GPU_GROUP_LOCK | RM_LOCK_FLAGS_NO_GPUS_LOCK; @@ -496,7 +503,12 @@ rmapiUnmapWithSecInfo return status; portMemSet(&lockInfo, 0, sizeof(lockInfo)); - rmapiInitLockInfo(pRmApi, hClient, &lockInfo); + status = rmapiInitLockInfo(pRmApi, hClient, NV01_NULL_OBJECT, &lockInfo); + if (status != NV_OK) + { + rmapiEpilogue(pRmApi, &rmApiContext); + return status; + } lockInfo.flags |= RM_LOCK_FLAGS_GPU_GROUP_LOCK | RM_LOCK_FLAGS_NO_GPUS_LOCK; diff --git a/src/nvidia/src/kernel/rmapi/mapping_cpu.c b/src/nvidia/src/kernel/rmapi/mapping_cpu.c index 91c1587887..e7bfb85a5f 100644 --- a/src/nvidia/src/kernel/rmapi/mapping_cpu.c +++ b/src/nvidia/src/kernel/rmapi/mapping_cpu.c @@ -768,26 +768,7 @@ memUnmap_IMPL } else if (memdescGetAddressSpace(pMemDesc) == ADDR_VIRTUAL) { - // If the memory is tiled, then it's being mapped through BAR1 - if( DRF_VAL(OS32, _ATTR, _TILED, pMemory->Attr) ) - { - // BAR1 mapping. Unmap it. - if (pCpuMapping->pPrivate->bKernel) - { - osUnmapPciMemoryKernel64(pGpu, pCpuMapping->pLinearAddress); - } - else - { - osUnmapPciMemoryUser(pGpu->pOsGpuInfo, - pCpuMapping->pLinearAddress, - pCpuMapping->length, - pCpuMapping->pPrivate->pPriv); - } - } - else - { - NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_STATE); - } + NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_STATE); } else if (memdescGetAddressSpace(pMemDesc) == ADDR_REGMEM) { @@ -1157,7 +1138,12 @@ rmapiMapToCpuWithSecInfoV2 NV_PRINTF(LEVEL_INFO, "MMU_PROFILER Nv04MapMemory 0x%x\n", *flags); portMemSet(&lockInfo, 0, sizeof(lockInfo)); - rmapiInitLockInfo(pRmApi, hClient, &lockInfo); + status = rmapiInitLockInfo(pRmApi, hClient, NV01_NULL_OBJECT, &lockInfo); + if (status != NV_OK) + { + rmapiEpilogue(pRmApi, &rmApiContext); + return status; + } LOCK_METER_DATA(MAPMEM, flags, 0, 0); @@ -1327,7 +1313,12 @@ rmapiUnmapFromCpuWithSecInfo return status; portMemSet(&lockInfo, 0, sizeof(lockInfo)); - rmapiInitLockInfo(pRmApi, hClient, &lockInfo); + status = rmapiInitLockInfo(pRmApi, hClient, NV01_NULL_OBJECT, &lockInfo); + if (status != NV_OK) + { + rmapiEpilogue(pRmApi, &rmApiContext); + return NV_OK; + } LOCK_METER_DATA(UNMAPMEM, flags, 0, 0); diff --git a/src/nvidia/src/kernel/rmapi/nv_gpu_ops.c b/src/nvidia/src/kernel/rmapi/nv_gpu_ops.c index 60211a9295..a1d816aa77 100644 --- a/src/nvidia/src/kernel/rmapi/nv_gpu_ops.c +++ b/src/nvidia/src/kernel/rmapi/nv_gpu_ops.c @@ -27,9 +27,6 @@ #include "core/prelude.h" -// FIXME XXX -#define NVOC_KERNEL_GRAPHICS_MANAGER_H_PRIVATE_ACCESS_ALLOWED - #include #include #include // NV01_MEMORY_SYSTEM @@ -208,6 +205,9 @@ typedef struct // region. NvHandle clientRegionHandle; volatile void *clientRegionMapping; + + NvHandle hP2pObject; + volatile NvU64 p2pObjectRef; } subDeviceDesc; struct gpuSession @@ -432,6 +432,13 @@ static NV_STATUS _nvGpuOpsRetainChannelResources(struct gpuDevice *device, gpuRetainedChannel *retainedChannel, gpuChannelInstanceInfo *channelInstanceInfo); static void _nvGpuOpsReleaseChannelResources(gpuRetainedChannel *retainedChannel); +static NV_STATUS _nvGpuOpsP2pObjectCreate(struct gpuDevice *device1, + struct gpuDevice *device2, + NvHandle *hP2pObject, + RMAPI_TYPE rmapiType); +static NV_STATUS _nvGpuOpsP2pObjectDestroy(struct gpuSession *session, + NvHandle hP2pObject, + RMAPI_TYPE rmapiType); static NV_STATUS nvGpuOpsQueryGpuConfidentialComputeCaps(NvHandle hClient, @@ -900,6 +907,18 @@ static NV_STATUS nvGpuOpsEnableVaSpaceChannels(struct gpuAddressSpace *vaSpace) return status; } +// Differentiate between different MIG instances. +static NvU64 makeDeviceDescriptorKey(const struct gpuDevice *device) +{ + NvU64 key = device->deviceInstance; + NvU64 swizzid = device->info.smcSwizzId; + + if (device->info.smcEnabled) + key |= (swizzid << 32); + + return key; +} + static NV_STATUS nvGpuOpsRmDeviceCreate(struct gpuDevice *device) { NV_STATUS status; @@ -908,12 +927,13 @@ static NV_STATUS nvGpuOpsRmDeviceCreate(struct gpuDevice *device) struct gpuSession *session = device->session; RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); PORT_MEM_ALLOCATOR *pAlloc = portMemAllocatorGetGlobalNonPaged(); + NvU64 deviceKey = makeDeviceDescriptorKey(device); OBJGPU *pGpu; // Find the existing rmDevice. // Otherwise, allocate an rmDevice. portSyncRwLockAcquireRead(session->btreeLock); - status = findDescriptor(session->devices, device->deviceInstance, (void**)&rmDevice); + status = findDescriptor(session->devices, deviceKey, (void**)&rmDevice); portSyncRwLockReleaseRead(session->btreeLock); if (status == NV_OK) { @@ -948,7 +968,7 @@ static NV_STATUS nvGpuOpsRmDeviceCreate(struct gpuDevice *device) rmDevice->subDeviceCount = 0; portSyncRwLockAcquireWrite(session->btreeLock); - status = trackDescriptor(&session->devices, device->deviceInstance, rmDevice); + status = trackDescriptor(&session->devices, deviceKey, rmDevice); portSyncRwLockReleaseWrite(session->btreeLock); if (status != NV_OK) goto cleanup_device; @@ -985,8 +1005,10 @@ static void nvGpuOpsRmDeviceDestroy(struct gpuDevice *device) if (rmDevice->subDeviceCount == 0) { struct gpuSession *session = device->session; + NvU64 deviceKey = makeDeviceDescriptorKey(device); + portSyncRwLockAcquireWrite(session->btreeLock); - deleteDescriptor(&session->devices, device->deviceInstance, (void**)&rmDevice); + deleteDescriptor(&session->devices, deviceKey, (void**)&rmDevice); pRmApi->Free(pRmApi, session->handle, rmDevice->deviceHandle); portSyncRwLockDestroy(rmDevice->btreeLock); portMemFree(rmDevice); @@ -1330,7 +1352,7 @@ static NV_STATUS nvGpuOpsRmSmcPartitionCreate(struct gpuDevice *device, const gp NV_STATUS status; OBJGPU *pGpu = NULL; subDeviceDesc *rmSubDevice = device->rmSubDevice; - NvHandle dupUserHandle; + NvHandle dupUserHandle = NV01_NULL_OBJECT; RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); struct gpuSession *session = device->session; RsResourceRef *pSmcResourceRef; @@ -1419,12 +1441,13 @@ static NV_STATUS nvGpuOpsRmSubDeviceCreate(struct gpuDevice *device) subDeviceDesc *rmSubDevice = NULL; struct gpuSession *session = device->session; RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); + NvU64 deviceKey = makeDeviceDescriptorKey(device); NV_ASSERT(session); // Query the rmDevice which needed to create an rmSubDevice. portSyncRwLockAcquireRead(session->btreeLock); - status = findDescriptor(session->devices, device->deviceInstance, (void**)&rmDevice); + status = findDescriptor(session->devices, deviceKey, (void**)&rmDevice); if (status != NV_OK) { portSyncRwLockReleaseRead(session->btreeLock); @@ -1694,6 +1717,7 @@ NV_STATUS nvGpuOpsDeviceCreate(struct gpuSession *session, struct gpuDevice *device = NULL; NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS gpuIdInfoParams = {{0}}; RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); + NvBool bPreCreated; OBJGPU *pGpu; device = portMemAllocNonPaged(sizeof(*device)); @@ -1727,27 +1751,32 @@ NV_STATUS nvGpuOpsDeviceCreate(struct gpuSession *session, if (status != NV_OK) goto cleanup_rm_device; - if (bCreateSmcPartition) + bPreCreated = (bCreateSmcPartition && (device->rmSubDevice->smcPartition.info != NULL)); + + if (bCreateSmcPartition && !bPreCreated) { status = nvGpuOpsRmSmcPartitionCreate(device, pGpuInfo); if (status != NV_OK) goto cleanup_rm_subdevice; } - // Create the work submission info mapping: - // * SMC is disabled, we create for the device. - // * SMC is enabled, we create only for SMC partitions. - if (isDeviceVoltaPlus(device) && (!pGpuInfo->smcEnabled || bCreateSmcPartition)) + if (!bPreCreated) { - status = gpuDeviceMapUsermodeRegion(device); + // Create the work submission info mapping: + // * SMC is disabled, we create for the device. + // * SMC is enabled, we create only for SMC partitions. + if (isDeviceVoltaPlus(device) && (!pGpuInfo->smcEnabled || bCreateSmcPartition)) + { + status = gpuDeviceMapUsermodeRegion(device); + if (status != NV_OK) + goto cleanup_smc_partition; + } + + status = gpuDeviceRmSubDeviceInitEcc(device); if (status != NV_OK) - goto cleanup_smc_partition; + goto cleanup_subdevice_usermode; } - status = gpuDeviceRmSubDeviceInitEcc(device); - if (status != NV_OK) - goto cleanup_subdevice_usermode; - status = queryFbInfo(device); if (status != NV_OK) goto cleanup_ecc; @@ -1829,6 +1858,10 @@ NV_STATUS nvGpuOpsDeviceDestroy(struct gpuDevice *device) rmDevice->subDeviceCount--; deleteDescriptor(&rmDevice->subDevices, device->subdeviceInstance, (void**)&rmSubDevice); pRmApi->Free(pRmApi, device->session->handle, rmSubDevice->subDeviceHandle); + + NV_ASSERT(rmSubDevice->hP2pObject == 0); + NV_ASSERT(rmSubDevice->p2pObjectRef == 0); + portMemFree(rmSubDevice); portSyncRwLockReleaseWrite(rmDevice->btreeLock); @@ -2438,9 +2471,10 @@ static NV_STATUS gpusHaveNpuNvlink(NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARA static NV_STATUS rmSystemP2PCapsControl(struct gpuDevice *device1, struct gpuDevice *device2, - NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS *p2pCapsParams) + NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS *p2pCapsParams, + RMAPI_TYPE rmapiType) { - RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); + RM_API *pRmApi = rmapiGetInterface(rmapiType); portMemSet(p2pCapsParams, 0, sizeof(*p2pCapsParams)); p2pCapsParams->gpuIds[0] = device1->gpuId; @@ -2466,7 +2500,8 @@ static NV_STATUS rmSystemP2PCapsControl(struct gpuDevice *device1, // Get R/W/A access capabilities and the link type between the two given GPUs static NV_STATUS getSystemP2PCaps(struct gpuDevice *device1, struct gpuDevice *device2, - struct systemP2PCaps *p2pCaps) + struct systemP2PCaps *p2pCaps, + RMAPI_TYPE rmapiType) { NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS *p2pCapsParams = NULL; NV_STATUS status = NV_OK; @@ -2478,7 +2513,7 @@ static NV_STATUS getSystemP2PCaps(struct gpuDevice *device1, goto done; } - status = rmSystemP2PCapsControl(device1, device2, p2pCapsParams); + status = rmSystemP2PCapsControl(device1, device2, p2pCapsParams, rmapiType); if (status != NV_OK) goto done; @@ -2504,8 +2539,19 @@ static NV_STATUS getSystemP2PCaps(struct gpuDevice *device1, if (p2pCaps->nvlinkSupported || p2pCaps->indirectAccessSupported) { + // // Exactly one CE is expected to be recommended for transfers between - // NvLink peers + // NvLink peers. + // + // In case of a single GPU, kceGetP2PCes() returns all possible CEs. In + // that case, set the lowest bit only to keep the assert happy. + // + if (device1 == device2) + { + p2pCapsParams->p2pOptimalWriteCEs &= + (~p2pCapsParams->p2pOptimalWriteCEs + 1); + } + NV_ASSERT(nvPopCount32(p2pCapsParams->p2pOptimalWriteCEs) == 1); // Query the write mask only; UVM has no use for the read mask @@ -2513,10 +2559,16 @@ static NV_STATUS getSystemP2PCaps(struct gpuDevice *device1, // Query the P2P capabilities of device2->device1, which may be // different from those of device1->device2 - status = rmSystemP2PCapsControl(device2, device1, p2pCapsParams); + status = rmSystemP2PCapsControl(device2, device1, p2pCapsParams, rmapiType); if (status != NV_OK) goto done; + if (device1 == device2) + { + p2pCapsParams->p2pOptimalWriteCEs &= + (~p2pCapsParams->p2pOptimalWriteCEs + 1); + } + NV_ASSERT(nvPopCount32(p2pCapsParams->p2pOptimalWriteCEs) == 1); p2pCaps->optimalNvlinkWriteCEs[1] = BIT_IDX_32(p2pCapsParams->p2pOptimalWriteCEs); @@ -2628,7 +2680,8 @@ NV_STATUS nvGpuOpsGetP2PCaps(struct gpuDevice *device1, p2pCapsParams->p2pLink = UVM_LINK_TYPE_NONE; p2pCapsParams->indirectAccess = NV_FALSE; - status = getSystemP2PCaps(device1, device2, &p2pCaps); + status = getSystemP2PCaps(device1, device2, &p2pCaps, + RMAPI_EXTERNAL_KERNEL); if (status != NV_OK) goto cleanup; @@ -2785,6 +2838,10 @@ static GMMU_APERTURE nvGpuOpsGetExternalAllocAperture(PMEMORY_DESCRIPTOR pMemDes } else { + if (memdescIsEgm(pMemDesc)) + { + return GMMU_APERTURE_PEER; + } return GMMU_APERTURE_SYS_COH; } } @@ -3540,6 +3597,48 @@ NV_STATUS nvGpuOpsGetExternalAllocPtes(struct gpuAddressSpace *vaSpace, goto freeGpaMemdesc; } } + else if (memdescIsEgm(pAdjustedMemDesc)) + { + // + // Remote EGM case. Ideally the check should be between the GPU where + // EGM is local and the mapping GPU but currently cross socket + // EGM allocation is not allowed, so the GPU where EGM is local is same as + // pAdjustedMemDesc->pGpu. + // + if (pAdjustedMemDesc->pGpu->gpuId != pMappingGpu->gpuId) + { + // + // If P2P doesn't exist between the two GPUs, then + // kbusGetEgmPeerId_HAL returns BUS_INVALID_PEER. The P2P check + // here is global and not per-client, UVM should check if the + // client has P2P between the GPUs before this is called. + // + peerId = kbusGetEgmPeerId_HAL(pMappingGpu, + GPU_GET_KERNEL_BUS(pMappingGpu), + pAdjustedMemDesc->pGpu); + + if (peerId == BUS_INVALID_PEER) + { + NV_PRINTF(LEVEL_ERROR, "UVM GPU%d->GPU%d: remote EGM peer id not found\n", + pMappingGpu->gpuInstance, + pAdjustedMemDesc->pGpu->gpuInstance); + status = NV_ERR_INVALID_ARGUMENT; + goto freeGpaMemdesc; + } + NV_PRINTF(LEVEL_INFO, "UVM GPU%d->GPU%d: peer Id: %d\n", + pMappingGpu->gpuInstance, + pAdjustedMemDesc->pGpu->gpuInstance, + peerId); + } + else + { + peerId = memmgrLocalEgmPeerId(GPU_GET_MEMORY_MANAGER(pMappingGpu)); + NV_PRINTF(LEVEL_INFO, "UVM GPU%d->CPU: Local EGM peer Id: %d\n", + pMappingGpu->gpuInstance, peerId); + NV_ASSERT_TRUE_OR_GOTO(status, peerId != BUS_INVALID_PEER, + NV_ERR_INVALID_STATE, freeGpaMemdesc); + } + } status = nvGpuOpsBuildExternalAllocPtes(pVAS, pMappingGpu, pAdjustedMemDesc, pMemory, offset, size, isIndirectPeerSupported, isPeerSupported, peerId, @@ -4770,7 +4869,6 @@ static NV_STATUS channelAllocate(const gpuTsgHandle tsg, hTsg = channel->tsg->tsgHandle; } - channel->channelHandle = NV01_NULL_OBJECT; status = pRmApi->Alloc(pRmApi, session->handle, hTsg, @@ -4792,7 +4890,7 @@ static NV_STATUS channelAllocate(const gpuTsgHandle tsg, ENGINE_INFO_TYPE_RUNLIST, &channel->hwRunlistId); if (status != NV_OK) - goto cleanup_free_virtual; + goto cleanup_free_channel; // Query channel ID status = nvGpuOpsChannelGetHwChannelId(channel, &channel->hwChannelId); @@ -4829,7 +4927,6 @@ static NV_STATUS channelAllocate(const gpuTsgHandle tsg, // Allocate the SW method class for fault cancel if (isDevicePascalPlus(device) && (channel->tsg->engineType != UVM_GPU_CHANNEL_ENGINE_TYPE_SEC2)) { - channel->hFaultCancelSwMethodClass = NV01_NULL_OBJECT; status = pRmApi->Alloc(pRmApi, session->handle, channel->channelHandle, @@ -5029,7 +5126,7 @@ void nvGpuOpsChannelDestroy(struct gpuChannel *channel) pRmApi->Free(pRmApi, session->handle, channel->engineHandle); // Tear down the channel - if (isDevicePascalPlus(device)) + if (channel->hFaultCancelSwMethodClass != NV01_NULL_OBJECT) pRmApi->Free(pRmApi, session->handle, channel->hFaultCancelSwMethodClass); if (isDeviceVoltaPlus(device)) @@ -5511,6 +5608,10 @@ static NV_STATUS findVaspaceFromPid(unsigned pid, unsigned gpuId, RmClient *pClient; RsClient *pRsClient; + pGpu = gpumgrGetGpuFromId(gpuId); + if (!pGpu) + return NV_ERR_INVALID_ARGUMENT; + for (ppClient = serverutilGetFirstClientUnderLock(); ppClient; ppClient = serverutilGetNextClientUnderLock(ppClient)) @@ -5519,24 +5620,15 @@ static NV_STATUS findVaspaceFromPid(unsigned pid, unsigned gpuId, pRsClient = staticCast(pClient, RsClient); if (pClient->ProcID == pid) { - pGpu = gpumgrGetGpuFromId(gpuId); - if (!pGpu) - return NV_ERR_INVALID_ARGUMENT; - - status = subdeviceGetByGpu(pRsClient, pGpu, &pSubDevice); - - if (status != NV_OK) - continue; - - GPU_RES_SET_THREAD_BC_STATE(pSubDevice); - status = deviceGetByGpu(pRsClient, pGpu, NV_TRUE, &pDevice); if (status == NV_OK) { - hDeviceLocal = RES_GET_HANDLE(pDevice); + status = subdeviceGetByDeviceAndGpu(pRsClient, pDevice, pGpu, &pSubDevice); + if (status != NV_OK) + continue; - if (pSubDevice != NULL) - hSubDeviceLocal = RES_GET_HANDLE(pSubDevice); + hDeviceLocal = RES_GET_HANDLE(pDevice); + hSubDeviceLocal = RES_GET_HANDLE(pSubDevice); *hClient = pRsClient->hClient; *hDevice = hDeviceLocal; @@ -5626,15 +5718,15 @@ static void getGpcTpcInfo(OBJGPU *pGpu, gpuInfo *pGpuInfo) pGpuInfo->gpcCount = 0; pGpuInfo->tpcCount = 0; - NV_ASSERT_OR_RETURN_VOID(pKernelGraphicsManager->legacyKgraphicsStaticInfo.bInitialized); - NV_ASSERT_OR_RETURN_VOID(pKernelGraphicsManager->legacyKgraphicsStaticInfo.pGrInfo != NULL); + NV_ASSERT_OR_RETURN_VOID(kgrmgrGetLegacyKGraphicsStaticInfo(pGpu, pKernelGraphicsManager)->bInitialized); + NV_ASSERT_OR_RETURN_VOID(kgrmgrGetLegacyKGraphicsStaticInfo(pGpu, pKernelGraphicsManager)->pGrInfo != NULL); pGpuInfo->maxTpcPerGpcCount = - pKernelGraphicsManager->legacyKgraphicsStaticInfo.pGrInfo->infoList[NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC].data; + kgrmgrGetLegacyKGraphicsStaticInfo(pGpu, pKernelGraphicsManager)->pGrInfo->infoList[NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC].data; pGpuInfo->maxGpcCount = - pKernelGraphicsManager->legacyKgraphicsStaticInfo.pGrInfo->infoList[NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS].data; + kgrmgrGetLegacyKGraphicsStaticInfo(pGpu, pKernelGraphicsManager)->pGrInfo->infoList[NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS].data; pGpuInfo->gpcCount = - nvPopCount32(pKernelGraphicsManager->legacyKgraphicsStaticInfo.floorsweepingMasks.gpcMask); + nvPopCount32(kgrmgrGetLegacyKGraphicsStaticInfo(pGpu, pKernelGraphicsManager)->floorsweepingMasks.gpcMask); // // When MIG GPU partitioning is enabled, compute the upper bound on the number @@ -5805,6 +5897,45 @@ static NV_STATUS getSysmemLinkInfo(NvHandle hClient, return NV_OK; } +static NV_STATUS getEgmInfo(NvHandle hClient, + NvHandle hSubDevice, + gpuInfo *pGpuInfo) +{ + NvU32 egmInfo; + NV2080_CTRL_GPU_GET_INFO_V2_PARAMS *gpuInfoParams; + RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); + NV_STATUS status; + + gpuInfoParams = portMemAllocNonPaged(sizeof(*gpuInfoParams)); + if (gpuInfoParams == NULL) + return NV_ERR_INSUFFICIENT_RESOURCES; + + portMemSet(gpuInfoParams, 0, sizeof(*gpuInfoParams)); + gpuInfoParams->gpuInfoListSize = 1; + gpuInfoParams->gpuInfoList[0].index = + NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY; + status = pRmApi->Control(pRmApi, + hClient, + hSubDevice, + NV2080_CTRL_CMD_GPU_GET_INFO_V2, + gpuInfoParams, + sizeof(*gpuInfoParams)); + egmInfo = gpuInfoParams->gpuInfoList[0].data; + portMemFree(gpuInfoParams); + + if (status != NV_OK) + return status; + + pGpuInfo->egmEnabled = + ((egmInfo & 0x1) == NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY_YES); + pGpuInfo->egmPeerId = DRF_VAL(2080_CTRL_GPU_INFO, _INDEX_GPU_LOCAL_EGM, + _PEERID, egmInfo); + + NV_PRINTF(LEVEL_INFO, "EGM enabled: %u peerId: %u\n", pGpuInfo->egmEnabled, + pGpuInfo->egmPeerId); + return NV_OK; +} + static NV_STATUS getSystemMemoryWindow(OBJGPU *pGpu, gpuInfo *pGpuInfo) { KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); @@ -6058,6 +6189,10 @@ NV_STATUS nvGpuOpsGetGpuInfo(const NvProcessorUuid *pUuid, if (status != NV_OK) goto cleanup; + status = getEgmInfo(clientHandle, subDeviceHandle, pGpuInfo); + if (status != NV_OK) + goto cleanup; + cleanup: if (isSubdeviceAllocated) pRmApi->Free(pRmApi, clientHandle, subDeviceHandle); @@ -6228,6 +6363,8 @@ static NV_STATUS nvGpuOpsFillGpuMemoryInfo(PMEMORY_DESCRIPTOR pMemDesc, pGpuMemoryInfo->contig = memdescGetContiguity(pMemDesc, AT_GPU); + pGpuMemoryInfo->egm = memdescIsEgm(pMemDesc); + if (pGpuMemoryInfo->contig) { GMMU_APERTURE aperture = nvGpuOpsGetExternalAllocAperture(pMemDesc, NV_FALSE, NV_FALSE); @@ -6265,10 +6402,36 @@ static NV_STATUS nvGpuOpsFillGpuMemoryInfo(PMEMORY_DESCRIPTOR pMemDesc, return NV_OK; } -static NvBool memdescIsSysmem(PMEMORY_DESCRIPTOR pMemDesc) +static NvBool memdescRequiresIommuMapping(PMEMORY_DESCRIPTOR pMemDesc) +{ + return ((memdescGetAddressSpace(pMemDesc) == ADDR_SYSMEM) && + !memdescGetFlag(pMemDesc, MEMDESC_FLAGS_MAP_SYSCOH_OVER_BAR1) && + !memdescIsEgm(pMemDesc)); +} + +// +// nvGpuOpsFreeDupedHandle() invokes this helper with only RO RMAPI lock taken, +// thus: +// a. Use portAtomicExDecrementU64 to ensure thread safety of p2pObjectRef. +// b. Pass RMAPI_API_LOCK_INTERNAL to _nvGpuOpsP2pObjectDestroy(). +// c. _enablePeerAccess() and _disablePeerAccess() are mutually exclusive due +// to RMAPI lock. +// +static void _disablePeerAccess(struct gpuDevice *device, + NvU32 addressSpace) +{ +} + +// +// nvGpuOpsDupMemory() invokes this helper with all locks taken, +// thus: +// a. Pass RMAPI_GPU_LOCK_INTERNAL to _nvGpuOpsP2pObjectCreate(). +// +static NV_STATUS _enablePeerAccess(struct gpuDevice *device, + NvU32 addressSpace) { - return (memdescGetAddressSpace(pMemDesc) == ADDR_SYSMEM) && - !(memdescGetFlag(pMemDesc, MEMDESC_FLAGS_MAP_SYSCOH_OVER_BAR1)); + + return NV_OK; } static NV_STATUS dupMemory(struct gpuDevice *device, @@ -6352,7 +6515,7 @@ static NV_STATUS dupMemory(struct gpuDevice *device, // For SYSMEM or indirect peer mappings bIsIndirectPeer = gpumgrCheckIndirectPeer(pMappingGpu, pAdjustedMemDesc->pGpu); if (bIsIndirectPeer || - memdescIsSysmem(pAdjustedMemDesc)) + memdescRequiresIommuMapping(pAdjustedMemDesc)) { // For sysmem allocations, the dup done below is very shallow and in // particular doesn't create IOMMU mappings required for the mapped GPU @@ -6419,8 +6582,23 @@ static NV_STATUS dupMemory(struct gpuDevice *device, if (status != NV_OK) goto freeGpaMemdesc; + // + // Always check the original memdesc here, because the pAdjustedMemDesc + // can be vidmem memdesc if fabric memory is being mapped on the + // owner GPU. Otherwise, it will break refcounting in + // nvGpuOpsFreeDupedHandle(), which always uses the original + // memdesc. + // + status = _enablePeerAccess(device, memdescGetAddressSpace(pMemDesc)); + if (status != NV_OK) + goto freeDupedMem; + *hDupMemory = dupedMemHandle; +freeDupedMem: + if (status != NV_OK) + pRmApi->Free(pRmApi, session->handle, dupedMemHandle); + freeGpaMemdesc: if (pAdjustedMemDesc != pMemDesc) fabricvaspacePutGpaMemdesc(pFabricVAS, pAdjustedMemDesc); @@ -7261,7 +7439,7 @@ NV_STATUS nvGpuOpsFreeDupedHandle(struct gpuDevice *device, if (status != NV_OK) goto out; - if (memdescIsSysmem(pMemory->pMemDesc)) + if (memdescRequiresIommuMapping(pMemory->pMemDesc)) { // Release the mappings acquired in nvGpuOpsDupMemory(). // @@ -7269,6 +7447,8 @@ NV_STATUS nvGpuOpsFreeDupedHandle(struct gpuDevice *device, memdescUnmapIommu(pMemory->pMemDesc, pMappingGpu->busInfo.iovaspaceId); } + _disablePeerAccess(device, memdescGetAddressSpace(pMemory->pMemDesc)); + out: pRmApi->Free(pRmApi, device->session->handle, hPhysHandle); _nvGpuOpsLocksRelease(&acquiredLocks); @@ -9219,15 +9399,16 @@ NV_STATUS nvGpuOpsGetPmaObject(struct gpuDevice *device, return status; } -NV_STATUS nvGpuOpsP2pObjectCreate(struct gpuDevice *device1, - struct gpuDevice *device2, - NvHandle *hP2pObject) +static NV_STATUS _nvGpuOpsP2pObjectCreate(struct gpuDevice *device1, + struct gpuDevice *device2, + NvHandle *hP2pObject, + RMAPI_TYPE rmapiType) { NV_STATUS status; NV503B_ALLOC_PARAMETERS p2pAllocParams = {0}; NvHandle hTemp = 0; struct systemP2PCaps p2pCaps; - RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); + RM_API *pRmApi = rmapiGetInterface(rmapiType); struct gpuSession *session; if (!device1 || !device2 || !hP2pObject) @@ -9236,7 +9417,7 @@ NV_STATUS nvGpuOpsP2pObjectCreate(struct gpuDevice *device1, if (device1->session != device2->session) return NV_ERR_INVALID_ARGUMENT; - status = getSystemP2PCaps(device1, device2, &p2pCaps); + status = getSystemP2PCaps(device1, device2, &p2pCaps, rmapiType); if (status != NV_OK) return status; @@ -9248,18 +9429,28 @@ NV_STATUS nvGpuOpsP2pObjectCreate(struct gpuDevice *device1, session = device1->session; hTemp = NV01_NULL_OBJECT; - status = pRmApi->Alloc(pRmApi, session->handle, session->handle, &hTemp, NV50_P2P, &p2pAllocParams, sizeof(p2pAllocParams)); + status = pRmApi->Alloc(pRmApi, session->handle, session->handle, &hTemp, + NV50_P2P, &p2pAllocParams, sizeof(p2pAllocParams)); if (status == NV_OK) *hP2pObject = hTemp; return status; } -NV_STATUS nvGpuOpsP2pObjectDestroy(struct gpuSession *session, - NvHandle hP2pObject) +NV_STATUS nvGpuOpsP2pObjectCreate(struct gpuDevice *device1, + struct gpuDevice *device2, + NvHandle *hP2pObject) +{ + return _nvGpuOpsP2pObjectCreate(device1, device2, hP2pObject, + RMAPI_EXTERNAL_KERNEL); +} + +static NV_STATUS _nvGpuOpsP2pObjectDestroy(struct gpuSession *session, + NvHandle hP2pObject, + RMAPI_TYPE rmapiType) { NV_STATUS status = NV_OK; - RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); + RM_API *pRmApi = rmapiGetInterface(rmapiType); NV_ASSERT(session); status = pRmApi->Free(pRmApi, session->handle, hP2pObject); @@ -9267,6 +9458,13 @@ NV_STATUS nvGpuOpsP2pObjectDestroy(struct gpuSession *session, return status; } +NV_STATUS nvGpuOpsP2pObjectDestroy(struct gpuSession *session, + NvHandle hP2pObject) +{ + return _nvGpuOpsP2pObjectDestroy(session, hP2pObject, + RMAPI_EXTERNAL_KERNEL); +} + NV_STATUS nvGpuOpsReportNonReplayableFault(struct gpuDevice *device, const void *pFaultPacket) { diff --git a/src/nvidia/src/kernel/rmapi/resource_desc_flags.h b/src/nvidia/src/kernel/rmapi/resource_desc_flags.h index 313d9f1bcf..6f4574dde8 100644 --- a/src/nvidia/src/kernel/rmapi/resource_desc_flags.h +++ b/src/nvidia/src/kernel/rmapi/resource_desc_flags.h @@ -26,28 +26,28 @@ // Flags for RS_ENTRY #define RS_FLAGS_NONE 0 -#define RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_ALLOC NVBIT(0) ///< GPUs Lock is acquired on allocation -#define RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE NVBIT(1) ///< GPUs Lock is acquired for free +#define RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_ALLOC NVBIT(0) ///< GPUs Lock is acquired on allocation +#define RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE NVBIT(1) ///< GPUs Lock is acquired for free #define RS_FLAGS_ACQUIRE_GPUS_LOCK (RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_ALLOC | RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE) -#define RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK_ON_ALLOC NVBIT(2) ///< GPU Group Lock is acquired on allocation -#define RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK_ON_FREE NVBIT(3) ///< GPU Group Lock is acquired for free +#define RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK_ON_ALLOC NVBIT(2) ///< GPU Group Lock is acquired on allocation +#define RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK_ON_FREE NVBIT(3) ///< GPU Group Lock is acquired for free #define RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK (RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK_ON_ALLOC | RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK_ON_FREE) -#define RS_FLAGS_ALLOC_RPC_TO_VGPU_HOST NVBIT(4) ///< Issue RPC to host to allocate resource for virtual GPUs +#define RS_FLAGS_ALLOC_RPC_TO_VGPU_HOST NVBIT(4) ///< Issue RPC to host to allocate resource for virtual GPUs -#define RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC NVBIT(5) ///< Acquire the RO API lock for allocation, default is RW API lock +#define RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC NVBIT(5) ///< Acquire the RO API lock for allocation, default is RW API lock -#define RS_FLAGS_ALLOC_RPC_TO_PHYS_RM NVBIT(6) ///< Issue RPC to allocate resource in physical RM +#define RS_FLAGS_ALLOC_RPC_TO_PHYS_RM NVBIT(6) ///< Issue RPC to allocate resource in physical RM #define RS_FLAGS_ALLOC_RPC_TO_ALL (RS_FLAGS_ALLOC_RPC_TO_VGPU_HOST | RS_FLAGS_ALLOC_RPC_TO_PHYS_RM) -#define RS_FLAGS_INTERNAL_ONLY NVBIT(7) ///< Class cannot be allocated outside of RM +#define RS_FLAGS_INTERNAL_ONLY NVBIT(7) ///< Class cannot be allocated outside of RM #define RS_FLAGS_CHANNEL_DESCENDANT_COMMON (RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL) #define RS_FREE_PRIORITY_DEFAULT 0 -#define RS_FREE_PRIORITY_HIGH 1 ///< Resources with this priority will be freed ahead of others +#define RS_FREE_PRIORITY_HIGH 1 ///< Resources with this priority will be freed ahead of others #define RS_FLAGS_ALLOC_NON_PRIVILEGED NVBIT(8) ///< Class is non privileged @@ -55,4 +55,24 @@ #define RS_FLAGS_ALLOC_KERNEL_PRIVILEGED NVBIT(10) ///< Class requires at least kernel privilege +/** + * CPU_PLUGIN_FOR_* indicates object can be allocated in the respective environment + * if the context is at least cached admin privileged + * - Cached-admin Hyper-V may access flagged privileged and kernel privileged objects + * - Other, runtime-admin hosts may access flagged kernel privileged objects + * - Note that runtime-admin hosts do not need the flag to allocate admin privileged objects + * + * GSP_PLUGIN_FOR_* is even stricter; any admin and kernel privileged object allocated in a VF context + * is required to have the flag or it will be rejected. + */ +#define RS_FLAGS_ALLOC_CPU_PLUGIN_FOR_VGPU_GSP NVBIT(11) ///< CPU-RM, SRIOV, vGPU-GSP enabled, hypervisor environment + +#define RS_FLAGS_ALLOC_CPU_PLUGIN_FOR_SRIOV NVBIT(12) ///< CPU-RM, SRIOV, vGPU-GSP disabled, hypervisor environment + +#define RS_FLAGS_ALLOC_CPU_PLUGIN_FOR_LEGACY NVBIT(13) ///< CPU-RM, non-SRIOV or SRIOV-Heavy, hypervisor environment. + +#define RS_FLAGS_ALLOC_GSP_PLUGIN_FOR_VGPU_GSP NVBIT(14) ///< GSP-RM, SRIOV, vGPU-GSP enabled, VF context. + +#define RS_FLAGS_ALLOC_ALL_VGPU_PLUGINS (RS_FLAGS_ALLOC_CPU_PLUGIN_FOR_VGPU_GSP | RS_FLAGS_ALLOC_CPU_PLUGIN_FOR_SRIOV | RS_FLAGS_ALLOC_CPU_PLUGIN_FOR_LEGACY | RS_FLAGS_ALLOC_GSP_PLUGIN_FOR_VGPU_GSP) + #endif // _RESOURCE_DESC_FLAGS_H_ diff --git a/src/nvidia/src/kernel/rmapi/resource_list.h b/src/nvidia/src/kernel/rmapi/resource_list.h index b4809d5c11..43de0b1e7e 100644 --- a/src/nvidia/src/kernel/rmapi/resource_list.h +++ b/src/nvidia/src/kernel/rmapi/resource_list.h @@ -329,7 +329,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Device), classId(KernelChannelGroupApi)), /* Alloc Param Info */ RS_REQUIRED(NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_HIGH, - /* Flags */ RS_FLAGS_ALLOC_KERNEL_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_KERNEL_PRIVILEGED | RS_FLAGS_ALLOC_ALL_VGPU_PLUGINS | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -429,7 +429,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Device)), /* Alloc Param Info */ RS_REQUIRED(NV_PHYSICAL_MEMORY_ALLOCATION_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ALLOC_CPU_PLUGIN_FOR_SRIOV | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -529,7 +529,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Device), classId(Subdevice)), /* Alloc Param Info */ RS_REQUIRED(NV_MEMORY_LIST_ALLOCATION_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ALLOC_CPU_PLUGIN_FOR_SRIOV | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -539,7 +539,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Device), classId(Subdevice)), /* Alloc Param Info */ RS_REQUIRED(NV_MEMORY_LIST_ALLOCATION_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ALLOC_CPU_PLUGIN_FOR_SRIOV | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -623,6 +623,16 @@ RS_ENTRY( /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) +RS_ENTRY( + /* External Class */ GF100_SUBDEVICE_INFOROM, + /* Internal Class */ GenericEngineApi, + /* Multi-Instance */ NV_TRUE, + /* Parents */ RS_LIST(classId(Subdevice)), + /* Alloc Param Info */ RS_NONE, + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC | RS_FLAGS_ALLOC_RPC_TO_PHYS_RM, + /* Required Access Rights */ RS_ACCESS_NONE +) RS_ENTRY( /* External Class */ NV01_TIMER, /* Internal Class */ TimerApi, @@ -780,7 +790,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_REQUIRED(NV_VIDMEM_ACCESS_BIT_ALLOCATION_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_PHYS_RM, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ALLOC_CPU_PLUGIN_FOR_SRIOV | RS_FLAGS_ALLOC_CPU_PLUGIN_FOR_VGPU_GSP | RS_FLAGS_ALLOC_GSP_PLUGIN_FOR_VGPU_GSP | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_PHYS_RM, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1062,7 +1072,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_NONE, /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ALLOC_CPU_PLUGIN_FOR_SRIOV | RS_FLAGS_ALLOC_GSP_PLUGIN_FOR_VGPU_GSP | RS_FLAGS_CHANNEL_DESCENDANT_COMMON, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( diff --git a/src/nvidia/src/kernel/rmapi/rmapi.c b/src/nvidia/src/kernel/rmapi/rmapi.c index 6ecccf1716..3797abe608 100644 --- a/src/nvidia/src/kernel/rmapi/rmapi.c +++ b/src/nvidia/src/kernel/rmapi/rmapi.c @@ -36,6 +36,7 @@ #include "core/thread_state.h" #include "gpu_mgr/gpu_mgr.h" #include "resource_desc.h" +#include "ctrl/ctrl0000/ctrl0000system.h" typedef struct { @@ -46,6 +47,9 @@ typedef struct NvU64 tlsEntryId; volatile NvU32 contentionCount; NvU32 lowPriorityAging; + volatile NvU64 totalWaitTime; + volatile NvU64 totalRwHoldTime; + volatile NvU64 totalRoHoldTime; } RMAPI_LOCK; RsServer g_resServ; @@ -376,33 +380,97 @@ rmapiEpilogue } } -void +NV_STATUS rmapiInitLockInfo ( - RM_API *pRmApi, - NvHandle hClient, - RS_LOCK_INFO *pLockInfo + RM_API *pRmApi, + NvHandle hClient, + NvHandle hSecondClient, + RS_LOCK_INFO *pLockInfo ) { - NV_ASSERT_OR_RETURN_VOID(pLockInfo != NULL); + CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + + NV_ASSERT_OR_RETURN(pLockInfo != NULL, NV_ERR_INVALID_STATE); pLockInfo->flags = 0; pLockInfo->state = 0; if (hClient != 0) { - CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); if ((pCallContext != NULL) && (pCallContext->pLockInfo != NULL)) { pLockInfo->state = pCallContext->pLockInfo->state; - if ((pCallContext->pLockInfo->pClient != NULL) && - (pCallContext->pLockInfo->pClient->hClient == hClient)) + // If no clients are locked, then we need to acquire client locks + if (pCallContext->pLockInfo->pClient == NULL) + pLockInfo->state &= ~RM_LOCK_STATES_CLIENT_LOCK_ACQUIRED; + + // If we only need one client locked + else if (hSecondClient == NV01_NULL_OBJECT) + { + if (pCallContext->pLockInfo->pClient->hClient == hClient) + pLockInfo->pClient = pCallContext->pLockInfo->pClient; + else if ((pCallContext->pLockInfo->pSecondClient != NULL) && + (pCallContext->pLockInfo->pSecondClient->hClient == hClient)) + { + pLockInfo->pClient = pCallContext->pLockInfo->pSecondClient; + } + else + pLockInfo->state &= ~RM_LOCK_STATES_CLIENT_LOCK_ACQUIRED; + } + + // If we only have one client locked, but we need two + else if (pCallContext->pLockInfo->pSecondClient == NULL) { - pLockInfo->pClient = pCallContext->pLockInfo->pClient; + if ((pCallContext->pLockInfo->pClient->hClient == hClient) || + (pCallContext->pLockInfo->pClient->hClient == hSecondClient)) + { + pLockInfo->pClient = pCallContext->pLockInfo->pClient; + + // + // Special case: if both clients are the same - + // Set both pClient's so _serverLockDualClientWithLockInfo + // doesn't complain about the lock state being invalid. + // + if (hClient == hSecondClient) + pLockInfo->pSecondClient = pCallContext->pLockInfo->pClient; + } + else + pLockInfo->state &= ~RM_LOCK_STATES_CLIENT_LOCK_ACQUIRED; } + + // If we need two clients locked, and already have two else { - pLockInfo->state &= ~RM_LOCK_STATES_CLIENT_LOCK_ACQUIRED; + // + // Check whether both clients match, keep the original order of the + // clients (dual client locking always locks the lower numbered client + // handle first). + // + if (((pCallContext->pLockInfo->pClient->hClient == hClient) && + (pCallContext->pLockInfo->pSecondClient->hClient == hSecondClient)) || + ((pCallContext->pLockInfo->pClient->hClient == hSecondClient) && + (pCallContext->pLockInfo->pSecondClient->hClient == hClient))) + { + pLockInfo->pClient = pCallContext->pLockInfo->pClient; + pLockInfo->pSecondClient = pCallContext->pLockInfo->pSecondClient; + } + + // Check whether one client handle matches + else if ((pCallContext->pLockInfo->pClient->hClient == hClient) || + (pCallContext->pLockInfo->pClient->hClient == hSecondClient)) + { + pLockInfo->pClient = pCallContext->pLockInfo->pClient; + pLockInfo->state &= ~RM_LOCK_STATES_CLIENT_LOCK_ACQUIRED; + } + else if ((pCallContext->pLockInfo->pSecondClient->hClient == hClient) || + (pCallContext->pLockInfo->pSecondClient->hClient == hSecondClient)) + { + pLockInfo->pClient = pCallContext->pLockInfo->pSecondClient; + pLockInfo->state &= ~RM_LOCK_STATES_CLIENT_LOCK_ACQUIRED; + } + else + pLockInfo->state &= ~RM_LOCK_STATES_CLIENT_LOCK_ACQUIRED; } } } @@ -414,13 +482,92 @@ rmapiInitLockInfo { pLockInfo->state |= RM_LOCK_STATES_API_LOCK_ACQUIRED; - // RS-TODO: Assert that API rwlock is taken if no client is locked - if (pLockInfo->pClient == NULL) - pLockInfo->flags |= RM_LOCK_FLAGS_NO_CLIENT_LOCK; + // + // If we don't have the exact clients we need locked, + // and this is an internal call we MUST have the RW API lock in order + // to prevent the client from being modified concurrently. + // + if (((hClient != NV01_NULL_OBJECT) && (pLockInfo->pClient == NULL)) || + ((hSecondClient != NV01_NULL_OBJECT) && (pLockInfo->pSecondClient == NULL))) + { + NvBool bPrevClientsLocked = + ((pCallContext != NULL && + pCallContext->pLockInfo != NULL) && + (pCallContext->pLockInfo->pClient != NULL || + pCallContext->pLockInfo->pSecondClient != NULL)); + + // + // Check for the RW API lock only if we have one or more non-internal client + // handles that aren't already locked. Assume that in the case of RM + // internal clients the caller, which can only be RM for internal clients, + // has checked the path's locking properly and doesn't require the RW API + // lock. However, ensure that at least the RO API lock is held. + // + + // If we haven't locked either hClient or hSecondClient yet + if (pLockInfo->pClient == NULL) + { + // + // Both client handles have to be kernel only to execute with the + // RO API lock. + // + if (!rmclientIsKernelOnlyByHandle(hClient) || + ((hSecondClient != NV01_NULL_OBJECT) && + (!rmclientIsKernelOnlyByHandle(hSecondClient)))) + { + LOCK_ASSERT_AND_RETURN(rmapiLockIsWriteOwner()); + } + + // + // Require the API lock if there are previous clients locked since + // that will prevent us from locking any individual client objects + // and therefore prevent them from being freed concurrently. + // + else if (bPrevClientsLocked) + { + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); + } + } + + // If we have 1 client already locked but we're using 2 + else if ((hSecondClient != NV01_NULL_OBJECT) && + (pLockInfo->pSecondClient == NULL)) + { + NvHandle hUnlockedClient = (pLockInfo->pClient->hClient == hClient ? + hSecondClient : hClient); + + // + // The unlocked client handle has to be unusable from user space to + // execute with the RO API lock. + // + if (!rmclientIsKernelOnlyByHandle(hUnlockedClient)) + { + LOCK_ASSERT_AND_RETURN(rmapiLockIsWriteOwner()); + } + + // + // Require the API lock if there are previous clients locked since + // that will prevent us from locking any individual client objects + // and therefore prevent them from being freed concurrently. + // + else if (bPrevClientsLocked) + { + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); + } + } + + // Don't acquire client locks if we already hold the API lock. + if (rmapiLockIsOwner()) + { + pLockInfo->flags |= RM_LOCK_FLAGS_NO_CLIENT_LOCK; + } + } } if (pRmApi->bGpuLockInternal) pLockInfo->state |= RM_LOCK_STATES_ALLOW_RECURSIVE_LOCKS; + + return NV_OK; } static NV_STATUS @@ -466,26 +613,34 @@ _rmapiLockFree(void) NV_STATUS rmapiLockAcquire(NvU32 flags, NvU32 module) { + OBJSYS *pSys = SYS_GET_INSTANCE(); NV_STATUS rmStatus = NV_OK; NvU64 threadId = portThreadGetCurrentThreadId(); NvU64 myPriority = 0; + NvU64 startWaitTime; LOCK_ASSERT_AND_RETURN(!rmapiLockIsOwner()); + // Ensure that GPU locks are NEVER acquired before the API lock + LOCK_ASSERT_AND_RETURN(rmGpuLocksGetOwnedMask() == 0); + // // If a read-only lock was requested, check to see if the module is allowed // to take read-only locks // if ((flags & RMAPI_LOCK_FLAGS_READ) && (module != RM_LOCK_MODULES_NONE)) { - OBJSYS *pSys = SYS_GET_INSTANCE(); if ((pSys->apiLockModuleMask & RM_LOCK_MODULE_GRP(module)) == 0) { flags &= ~RMAPI_LOCK_FLAGS_READ; } } + // Get start wait time measuring lock wait times + if (pSys->getProperty(pSys, PDB_PROP_SYS_RM_LOCK_TIME_COLLECT)) + osGetCurrentTick(&startWaitTime); + // // For conditional acquires and DISPATCH_LEVEL we want to exit // immediately without waiting. @@ -527,6 +682,7 @@ rmapiLockAcquire(NvU32 flags, NvU32 module) if (flags & RMAPI_LOCK_FLAGS_LOW_PRIORITY) { NvS32 age = g_RmApiLock.lowPriorityAging; + portSyncRwLockAcquireWrite(g_RmApiLock.pLock); while ((g_RmApiLock.contentionCount > 0) && (age--)) { @@ -551,6 +707,10 @@ rmapiLockAcquire(NvU32 flags, NvU32 module) NvU64 timestamp; osGetCurrentTick(×tamp); + // Update total API lock wait time if measuring lock times + if (pSys->getProperty(pSys, PDB_PROP_SYS_RM_LOCK_TIME_COLLECT)) + portAtomicExAddU64(&g_RmApiLock.totalWaitTime, timestamp - startWaitTime); + if (g_RmApiLock.threadId == threadId) g_RmApiLock.timestamp = timestamp; @@ -578,10 +738,17 @@ rmapiLockAcquire(NvU32 flags, NvU32 module) } } - NvP64 *pAcquireAddress = tlsEntryAcquire(g_RmApiLock.tlsEntryId); - if (pAcquireAddress != NULL) + NvP64 *pStartTime = tlsEntryAcquire(g_RmApiLock.tlsEntryId); + if (pStartTime != NULL) { - *pAcquireAddress = (NvP64)(NvUPtr)NV_RETURN_ADDRESS(); + // + // Store start time to track lock hold time. This is done + // regardless of the value of PDB_PROP_SYS_RM_LOCK_TIME_COLLECT since + // the API lock can be acquired before PDB properties are initialized + // and released after they are which could lead to uninitialized memory + // being present in TLS. + // + osGetCurrentTick((NvU64 *) pStartTime); } return rmStatus; @@ -590,8 +757,14 @@ rmapiLockAcquire(NvU32 flags, NvU32 module) void rmapiLockRelease(void) { + OBJSYS *pSys = SYS_GET_INSTANCE(); NvU64 threadId = portThreadGetCurrentThreadId(); NvU64 timestamp; + NvU64 startTime = 0; + + // Fetch start of hold time from TLS if measuring lock times + if (pSys->getProperty(pSys, PDB_PROP_SYS_RM_LOCK_TIME_COLLECT)) + startTime = (NvU64) tlsEntryGet(g_RmApiLock.tlsEntryId); osGetCurrentTick(×tamp); @@ -615,11 +788,20 @@ rmapiLockRelease(void) // g_RmApiLock.threadId = ~0ull; g_RmApiLock.timestamp = timestamp; + + // Update total RW API lock hold time if measuring lock times + if (pSys->getProperty(pSys, PDB_PROP_SYS_RM_LOCK_TIME_COLLECT)) + portAtomicExAddU64(&g_RmApiLock.totalRwHoldTime, timestamp - startTime); + portSyncRwLockReleaseWrite(g_RmApiLock.pLock); } else { + // Update total RO API lock hold time if measuring lock times + if (pSys->getProperty(pSys, PDB_PROP_SYS_RM_LOCK_TIME_COLLECT)) + portAtomicExAddU64(&g_RmApiLock.totalRoHoldTime, timestamp - startTime); + portSyncRwLockReleaseRead(g_RmApiLock.pLock); } @@ -629,7 +811,26 @@ rmapiLockRelease(void) NvBool rmapiLockIsOwner(void) { - return tlsEntryGet(g_RmApiLock.tlsEntryId) != NvP64_NULL; + return tlsEntryGet(g_RmApiLock.tlsEntryId) != 0; +} + +NvBool +rmapiLockIsWriteOwner(void) +{ + NvU64 threadId = portThreadGetCurrentThreadId(); + + return (rmapiLockIsOwner() && (threadId == g_RmApiLock.threadId)); +} + +// +// Retrieve total RM API lock wait and hold times +// +void +rmapiLockGetTimes(NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS *pParams) +{ + pParams->waitApiLock = g_RmApiLock.totalWaitTime; + pParams->holdRoApiLock = g_RmApiLock.totalRoHoldTime; + pParams->holdRwApiLock = g_RmApiLock.totalRwHoldTime; } // diff --git a/src/nvidia/src/kernel/rmapi/sharing.c b/src/nvidia/src/kernel/rmapi/sharing.c index 74956112d8..fbf729c03d 100644 --- a/src/nvidia/src/kernel/rmapi/sharing.c +++ b/src/nvidia/src/kernel/rmapi/sharing.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -118,22 +118,11 @@ rmapiDupObjectWithSecInfo } portMemSet(&lockInfo, 0, sizeof(lockInfo)); - rmapiInitLockInfo(pRmApi, hClient, &lockInfo); - - if (pRmApi->bApiLockInternal) + status = rmapiInitLockInfo(pRmApi, hClient, hClientSrc, &lockInfo); + if (status != NV_OK) { - // - // DupObject requires taking two client locks, but internal calls have probably - // already taken one client lock. Taking a second would require unlocking - // the first lock in the middle of the API call, which could mess with the client. - // In such cases, we need an exclusive API lock, then skip taking client locks. - // - if (lockInfo.pClient != NULL) - { - NV_ASSERT(rmapiLockIsOwner()); - // RS-TODO assert RW api lock - lockInfo.flags |= RM_LOCK_FLAGS_NO_CLIENT_LOCK; - } + rmapiEpilogue(pRmApi, &rmApiContext); + return NV_OK; } status = _RmDupObject(hClient, hParent, phObject, hClientSrc, hObjectSrc, flags, pSecInfo, &lockInfo); @@ -236,6 +225,7 @@ rmapiShareWithSecInfo NV_STATUS status; RM_API_CONTEXT rmApiContext = {0}; RS_LOCK_INFO lockInfo; + NvHandle hSecondClient = NV01_NULL_OBJECT; NV_PRINTF(LEVEL_INFO, "Nv04Share: hClient:0x%x hObject:0x%x pSharePolicy:%p\n", @@ -247,8 +237,19 @@ rmapiShareWithSecInfo return status; } + if ((pSecInfo->paramLocation == PARAM_LOCATION_KERNEL) && + (pSharePolicy->type == RS_SHARE_TYPE_CLIENT)) + { + hSecondClient = pSharePolicy->target; + } + portMemSet(&lockInfo, 0, sizeof(lockInfo)); - rmapiInitLockInfo(pRmApi, hClient, &lockInfo); + status = rmapiInitLockInfo(pRmApi, hClient, hSecondClient, &lockInfo); + if (status != NV_OK) + { + rmapiEpilogue(pRmApi, &rmApiContext); + return NV_OK; + } // // Currently, Share should have no internal callers. diff --git a/src/nvidia/src/kernel/virtualization/common_vgpu_mgr.c b/src/nvidia/src/kernel/virtualization/common_vgpu_mgr.c index 23eb740ad0..32bf7028cf 100644 --- a/src/nvidia/src/kernel/virtualization/common_vgpu_mgr.c +++ b/src/nvidia/src/kernel/virtualization/common_vgpu_mgr.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2012-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2012-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -39,7 +39,7 @@ vgpuMgrReserveSystemChannelIDs NvU32 gfid, NvU32 *pChidOffset, NvU32 *pChannelCount, - NvHandle hClient, + Device *pMigDevice, NvU32 numChannels, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *engineFifoList @@ -55,7 +55,7 @@ vgpuMgrFreeSystemChannelIDs NvU32 gfid, NvU32 *pChidOffset, NvU32 *pChannelCount, - NvHandle hClient, + Device *pMigDevice, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *engineFifoList ) diff --git a/src/nvidia/src/kernel/virtualization/hypervisor/hypervisor.c b/src/nvidia/src/kernel/virtualization/hypervisor/hypervisor.c index 0a898c46e9..48cf63a509 100644 --- a/src/nvidia/src/kernel/virtualization/hypervisor/hypervisor.c +++ b/src/nvidia/src/kernel/virtualization/hypervisor/hypervisor.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -71,7 +71,6 @@ NvBool hypervisorPcieP2pDetection_IMPL { if (_hypervisorCheckVirtualPcieP2PApproval(pHypervisor, gpuMask)) return NV_TRUE; - if (hypervisorIsVgxHyper()) return NV_FALSE; diff --git a/src/nvidia/src/libraries/containers/list.c b/src/nvidia/src/libraries/containers/list.c index 250f59e72a..4f5155b7be 100644 --- a/src/nvidia/src/libraries/containers/list.c +++ b/src/nvidia/src/libraries/containers/list.c @@ -338,6 +338,7 @@ ListIterBase listIterRange_IMPL NV_ASSERT_CHECKED(it.pNode == NULL || it.pNode->pList == pList); NV_ASSERT_CHECKED(it.pLast == NULL || it.pLast->pList == pList); NV_ASSERT_CHECKED(_listIterRangeCheck(pList, it.pNode, it.pLast)); + NV_CHECKED_ONLY(it.bValid = NV_TRUE); return it; } @@ -346,7 +347,15 @@ NvBool listIterNext_IMPL(ListIterBase *pIt) { NV_ASSERT_OR_RETURN(NULL != pIt, NV_FALSE); - NV_ASSERT_CHECKED(pIt->versionNumber == pIt->pList->versionNumber); +#if PORT_IS_CHECKED_BUILD + if (pIt->bValid && !CONT_ITER_IS_VALID(pIt->pList, pIt)) + { + NV_ASSERT(CONT_ITER_IS_VALID(pIt->pList, pIt)); + PORT_DUMP_STACK(); + + pIt->bValid = NV_FALSE; + } +#endif if (!pIt->pNode) return NV_FALSE; diff --git a/src/nvidia/src/libraries/containers/map.c b/src/nvidia/src/libraries/containers/map.c index db339e6250..cfc153fdbe 100644 --- a/src/nvidia/src/libraries/containers/map.c +++ b/src/nvidia/src/libraries/containers/map.c @@ -525,12 +525,14 @@ NvBool mapIterNext_IMPL(MapIterBase *pIt) { NV_ASSERT_OR_RETURN(pIt, NV_FALSE); - // - // Check whether the map was mutated during the iteration. - // If the map changed (by adding or removing entries), - // the iterator becomes invalid and must be reinitialized. - // - NV_ASSERT_CHECKED(pIt->versionNumber == pIt->pMap->versionNumber); +#if PORT_IS_CHECKED_BUILD + if (pIt->bValid && !CONT_ITER_IS_VALID(pIt->pMap, pIt)) + { + NV_ASSERT(CONT_ITER_IS_VALID(pIt->pMap, pIt)); + PORT_DUMP_STACK(); + pIt->bValid = NV_FALSE; + } +#endif if (!pIt->pNode) return NV_FALSE; diff --git a/src/nvidia/src/libraries/containers/vector.c b/src/nvidia/src/libraries/containers/vector.c index a2ae403f9b..73d61301ab 100644 --- a/src/nvidia/src/libraries/containers/vector.c +++ b/src/nvidia/src/libraries/containers/vector.c @@ -82,6 +82,13 @@ void vectDestroy_IMPL(Vector *pVector) pVector->size = 0; } +void vectClear_IMPL(Vector *pVector) +{ + NV_ASSERT_OR_RETURN_VOID(pVector != NULL); + NV_CHECKED_ONLY(pVector->versionNumber++); + pVector->size = 0; +} + void *vectAt_IMPL ( Vector *pVector, @@ -279,6 +286,8 @@ VectorIterBase vectIterRange_IMPL } NV_CHECKED_ONLY(it.versionNumber = pVector->versionNumber); + NV_CHECKED_ONLY(it.bValid = NV_TRUE); + if ((pVector->size == 0) || (pFirst == NULL) || (first >= pVector->size) || (pLast == NULL) || (last >= pVector->size)) { @@ -315,7 +324,14 @@ NvBool vectIterNext_IMPL return NV_FALSE; } - NV_ASSERT_CHECKED(pIter->versionNumber == pIter->pVector->versionNumber); +#if PORT_IS_CHECKED_BUILD + if (pIter->bValid && !CONT_ITER_IS_VALID(pIter->pVector, pIter)) + { + NV_ASSERT(CONT_ITER_IS_VALID(pIter->pVector, pIter)); + PORT_DUMP_STACK(); + pIter->bValid = NV_FALSE; + } +#endif *ppValue = (void *)((NvU8 *)pIter->pVector->pHead + pIter->nextIndex * pIter->pVector->valueSize); @@ -350,7 +366,14 @@ NvBool vectIterPrev_IMPL return NV_FALSE; } - NV_ASSERT_CHECKED(pIter->versionNumber == pIter->pVector->versionNumber); +#if PORT_IS_CHECKED_BUILD + if (pIter->bValid && !CONT_ITER_IS_VALID(pIter->pVector, pIter)) + { + NV_ASSERT(CONT_ITER_IS_VALID(pIter->pVector, pIter)); + PORT_DUMP_STACK(); + pIter->bValid = NV_FALSE; + } +#endif *ppValue = (void *)((NvU8 *)pIter->pVector->pHead + pIter->prevIndex * pIter->pVector->valueSize); diff --git a/src/nvidia/src/libraries/eventbuffer/eventbufferproducer.c b/src/nvidia/src/libraries/eventbuffer/eventbufferproducer.c index 0876ba2a94..f542c6431b 100644 --- a/src/nvidia/src/libraries/eventbuffer/eventbufferproducer.c +++ b/src/nvidia/src/libraries/eventbuffer/eventbufferproducer.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2017-2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -170,7 +170,7 @@ eventBufferProducerAddEvent EVENT_BUFFER_PRODUCER_INFO *info, NvU16 eventType, NvU16 eventSubtype, - EVENT_BUFFER_PRODUCER_DATA* pData + EVENT_BUFFER_PRODUCER_DATA *pData ) { NV_EVENT_BUFFER_RECORD *record; @@ -180,6 +180,10 @@ eventBufferProducerAddEvent record = _eventBufferGetFreeRecord(info); if (record) { + RECORD_BUFFER_INFO *pRecInfo = &info->recordBuffer; + NV_EVENT_BUFFER_HEADER *pHeader = pRecInfo->pHeader; + NvU32 putNext = (pHeader->recordPut + 1) % pRecInfo->totalRecordCount; + record->recordHeader.type = eventType; record->recordHeader.subtype = eventSubtype; @@ -188,22 +192,21 @@ eventBufferProducerAddEvent NvP64_VALUE(pData->pPayload), pData->payloadSize); _eventBufferAddVardata(info, pData->pVardata, pData->vardataSize, &record->recordHeader); + + pHeader->recordPut = putNext; } } } -NV_EVENT_BUFFER_RECORD* +NV_EVENT_BUFFER_RECORD * _eventBufferGetFreeRecord(EVENT_BUFFER_PRODUCER_INFO *info) { - RECORD_BUFFER_INFO* pRecInfo = &info->recordBuffer; - NV_EVENT_BUFFER_HEADER* pHeader = pRecInfo->pHeader; + RECORD_BUFFER_INFO *pRecInfo = &info->recordBuffer; + NV_EVENT_BUFFER_HEADER *pHeader = pRecInfo->pHeader; NvU32 recordOffset = 0; - NV_EVENT_BUFFER_RECORD* pFreeRecord = NULL; - - NvU32 putNext = pHeader->recordPut + 1; + NV_EVENT_BUFFER_RECORD *pFreeRecord = NULL; - if (putNext == pRecInfo->totalRecordCount) - putNext = 0; + NvU32 putNext = (pHeader->recordPut + 1) % pRecInfo->totalRecordCount; if ((!info->isKeepNewest) && (putNext == pHeader->recordGet)) { @@ -212,10 +215,7 @@ _eventBufferGetFreeRecord(EVENT_BUFFER_PRODUCER_INFO *info) else { recordOffset = pHeader->recordPut * pRecInfo->recordSize; - pFreeRecord = (NV_EVENT_BUFFER_RECORD*)((NvUPtr)pRecInfo->recordBuffAddr + recordOffset); - - pHeader->recordCount++; - pHeader->recordPut = putNext; + pFreeRecord = (NV_EVENT_BUFFER_RECORD *)((NvUPtr)pRecInfo->recordBuffAddr + recordOffset); } return pFreeRecord; } diff --git a/src/nvidia/src/libraries/mmu/mmu_walk.c b/src/nvidia/src/libraries/mmu/mmu_walk.c index 4f14b95db8..5d2c7ced16 100644 --- a/src/nvidia/src/libraries/mmu/mmu_walk.c +++ b/src/nvidia/src/libraries/mmu/mmu_walk.c @@ -223,12 +223,9 @@ mmuWalkFindLevel ) { const MMU_WALK_LEVEL *pLevel = &pWalk->root; - while (pLevel != NULL && pLevel->pFmt != pLevelFmt) + while (pLevel->pFmt != pLevelFmt) { NvU32 subLevel; - - NV_ASSERT_OR_RETURN(pLevel->pFmt != NULL, NULL); - // Single sub-level always continues. if (1 == pLevel->pFmt->numSubLevels) { @@ -273,11 +270,10 @@ NV_STATUS mmuWalkProcessPdes NvU64 vaHi ) { - if (pWalk->flags.bUseIterative) { - // Iterative MMU Walker Implementation NV_STATUS status = NV_OK; + const MMU_WALK_LEVEL *pLevelOrig = pLevel; NV_ASSERT_OR_RETURN(pOpParams != NULL, NV_ERR_INVALID_ARGUMENT); // Call opFunc inititially to see if we need to walk @@ -302,63 +298,17 @@ NV_STATUS mmuWalkProcessPdes NvU64 vaLevelBase = mmuFmtLevelVirtAddrLo(pLevel->pFmt, vaLo); NvU32 entryIndexLo = mmuFmtVirtAddrToEntryIndex(pLevel->pFmt, vaLo); NvU32 entryIndexHi = mmuFmtVirtAddrToEntryIndex(pLevel->pFmt, vaHi); - NvU32 entryIndex; - NvU32 index; + NvU32 entryIndex = entryIndexLo; NvU32 entryIndexFillStart = 0; - NvU32 entryIndexFillEnd; - NvU32 pendingFillCount = 0; - - // Declarations for mmuWalk recursion conversion - MMU_WALK_PROCESS_PDES_ENTRY *pProcessPdeEntry; - MMU_WALK_RELEASE_PDES_ENTRY *pReleasePdeEntry; - PROCESS_PDES_STACK processPdesStack; - RELEASE_PDES_STACK releasePdesStack; - listInit(&processPdesStack, portMemAllocatorGetGlobalNonPaged()); - listInit(&releasePdesStack, portMemAllocatorGetGlobalNonPaged()); + NvU32 entryIndexFillEnd = 0; + NvU32 pendingFillCount = 0; // - // Walk over each relevant entry (PDE) within this Page Level - // Do one initial loop to kick off iteration - // Add entries in reverse order because processPdesStack is a stack + // entryIndex, entryIndexHi are modified in the loop itself + // as we iterate through levels. // - for (entryIndex = entryIndexHi; entryIndex >= entryIndexLo; entryIndex--) + while (entryIndex <= entryIndexHi) { - pProcessPdeEntry = listPrependNew(&processPdesStack); - if (pProcessPdeEntry == NULL) - { - status = NV_ERR_NO_MEMORY; - NV_ASSERT_OR_GOTO(0, cleanupIter); - } - - // - // The values pushed to the stack must NOT be pointers to variables on the stack - // All of these are simple values or pointers to a variable allocated by a function - // calling the MMU Walker. - // - pProcessPdeEntry->pLevel = pLevel; - pProcessPdeEntry->pLevelInst = pLevelInst; - pProcessPdeEntry->vaLo = vaLo; - pProcessPdeEntry->vaHi = vaHi; - pProcessPdeEntry->vaLevelBase = vaLevelBase; - pProcessPdeEntry->entryIndexHi = entryIndexHi; - pProcessPdeEntry->entryIndex = entryIndex; - - // Prevent underflow because of adding entries in reverse order - if (entryIndex == 0) break; - } - - while ((pProcessPdeEntry = listHead(&processPdesStack)) != NULL) - { - pLevel = pProcessPdeEntry->pLevel; - pLevelInst = pProcessPdeEntry->pLevelInst; - vaLo = pProcessPdeEntry->vaLo; - vaHi = pProcessPdeEntry->vaHi; - vaLevelBase = pProcessPdeEntry->vaLevelBase; - entryIndexHi = pProcessPdeEntry->entryIndexHi; - entryIndex = pProcessPdeEntry->entryIndex; - - listRemove(&processPdesStack, pProcessPdeEntry); - const NvU64 entryVaLo = mmuFmtEntryIndexVirtAddrLo(pLevel->pFmt, vaLevelBase, entryIndex); const NvU64 entryVaHi = mmuFmtEntryIndexVirtAddrHi(pLevel->pFmt, @@ -375,7 +325,9 @@ NV_STATUS mmuWalkProcessPdes // Skip this entry if it is neither a PDE nor marked as a hybrid entry. if ((MMU_ENTRY_STATE_IS_PDE != currEntryState) && !pLevelInst->pStateTracker[entryIndex].bHybrid) - continue; + { + goto check_last_entry; + } } // Optimizations for fill operations. @@ -408,12 +360,19 @@ NV_STATUS mmuWalkProcessPdes // Not the last iteration, keep batching.. if (entryIndex < entryIndexHi) - continue; + { + // + // This won't be the last entry, but we'll + // do the iteration there + // + goto check_last_entry; + } } if (pendingFillCount != 0) { NvU32 progress = 0; + NvU32 index; // Flush pending fills pWalk->pCb->FillEntries(pWalk->pUserCtx, @@ -438,7 +397,9 @@ NV_STATUS mmuWalkProcessPdes // Recheck the state after fill. If nothing to do, continue.. if (pTarget->entryState == mmuWalkGetEntryState(pLevelInst, entryIndex)) - continue; + { + goto check_last_entry; + } } // End of fill optimizations. @@ -468,7 +429,7 @@ NV_STATUS mmuWalkProcessPdes // Release op is done if the target sub-level is absent. if (pOpParams->bRelease && (NULL == pSubLevelInsts[subLevel])) { - continue; + goto check_last_entry; } // @@ -540,61 +501,57 @@ NV_STATUS mmuWalkProcessPdes // going by doing everything the recursion previously did. // status = NV_OK; - pReleasePdeEntry = listPrependNew(&releasePdesStack); - if (pReleasePdeEntry == NULL) - { - status = NV_ERR_NO_MEMORY; - NV_ASSERT_OR_GOTO(0, cleanupIter); - } - // - // Queue the current level for pdeRelease so that pdeRelease - // can be called AFTER exploring the current level's sublevels. - // - pReleasePdeEntry->pLevel = pLevel; - pReleasePdeEntry->pLevelInst = pLevelInst; - pReleasePdeEntry->entryVaLo = entryVaLo; - pReleasePdeEntry->entryIndexHi = entryIndexHi; - pReleasePdeEntry->entryIndex = entryIndex; + // Save off the current state of iteration for this level + pLevel->iterInfo.pLevelInst = pLevelInst; + pLevel->iterInfo.vaLo = vaLo; + pLevel->iterInfo.vaHi = vaHi; + pLevel->iterInfo.vaLevelBase = vaLevelBase; + pLevel->iterInfo.entryIndexHi = entryIndexHi; + pLevel->iterInfo.entryIndex = entryIndex; + pLevel->iterInfo.entryIndexFillStart = entryIndexFillStart; + pLevel->iterInfo.entryIndexFillEnd = entryIndexFillEnd; + pLevel->iterInfo.pendingFillCount = pendingFillCount; + pLevel->iterInfo.entryVaLo = entryVaLo; // // Here use variables that would be used in the next recursion downwards. // Calculate new vaLevelBase, entryIndexLo, entryIndexHi, entryIndex // - vaLevelBase = mmuFmtLevelVirtAddrLo((pLevel->subLevels + subLevel)->pFmt, clippedVaLo); - entryIndexLo = mmuFmtVirtAddrToEntryIndex((pLevel->subLevels + subLevel)->pFmt, clippedVaLo); - entryIndexHi = mmuFmtVirtAddrToEntryIndex((pLevel->subLevels + subLevel)->pFmt, clippedVaHi); - - for (entryIndex = entryIndexHi; entryIndex >= entryIndexLo; entryIndex--) - { - pProcessPdeEntry = listPrependNew(&processPdesStack); - if (pProcessPdeEntry == NULL) - { - status = NV_ERR_NO_MEMORY; - NV_ASSERT_OR_GOTO(0, cleanupIter); - } - - pProcessPdeEntry->pLevel = pLevel->subLevels + subLevel; - pProcessPdeEntry->pLevelInst = pSubLevelInsts[subLevel]; - pProcessPdeEntry->vaLo = clippedVaLo; - pProcessPdeEntry->vaHi = clippedVaHi; - pProcessPdeEntry->vaLevelBase = vaLevelBase; - pProcessPdeEntry->entryIndexHi = entryIndexHi; - pProcessPdeEntry->entryIndex = entryIndex; - - if (entryIndex == 0) break; - } + pLevel = pLevel->subLevels + subLevel; + + vaLevelBase = mmuFmtLevelVirtAddrLo(pLevel->pFmt, clippedVaLo); + entryIndexLo = mmuFmtVirtAddrToEntryIndex(pLevel->pFmt, clippedVaLo); + entryIndexHi = mmuFmtVirtAddrToEntryIndex(pLevel->pFmt, clippedVaHi); + + // Now replace the current stack frame with the frame that is one level down + // pLevel replaced above + pLevelInst = pSubLevelInsts[subLevel]; + vaLo = clippedVaLo; + vaHi = clippedVaHi; + vaLevelBase = vaLevelBase; + entryIndexHi = entryIndexHi; + entryIndex = entryIndexLo; + entryIndexFillStart = 0; + entryIndexFillEnd = 0; + pendingFillCount = 0; } - else if (NV_OK == status) + else { + NV_ASSERT_OR_GOTO(NV_OK == status, cleanupIter); // // If NV_OK is returned above, the recursive MMU Walker would have reached // the target format level and so reached the base case of its recursion. - // It would then return from recursive function calls an call pdeRelease + // It would then return from recursive function calls and call pdeRelease // for all levels whose sublevels are done being processed. // +cleanupIter: // PdeRelease itself immediately since this level does not recurse. +#if defined(__GNUC__) && !defined(__clang__) + // gcc is falsely reporting entryVaLo; entryVaLo is definitely initialized +#pragma GCC diagnostic ignored "-Wmaybe-uninitialized" +#endif _mmuWalkPdeRelease(pWalk, pOpParams, pLevel, @@ -602,83 +559,96 @@ NV_STATUS mmuWalkProcessPdes entryIndex, entryVaLo); +check_last_entry: + // + // If the recursive MMU Walker did a continue on the current level, + // then it didn't do a pdeRelease of the current level. + // Even with the continue, for the current iteration, + // if entryIndex == entryIndexHi, then we're done with this level + // and need to do a pdeRelease on the next level up since we would + // return from the recursion. + // + + // + // If we're at the original level and entryIndex = entryIndexHi, + // then we're done and need to exit the entire loop. + // If this is true, we've already done the _mmuWalkPdeRelease: + // Either we already called _mmuWalkPdeRelease right before this + // or we skipped it from a goto check_last_entry continue. + // The MMU Walker is re-entrant and will otherwise pick up on + // parent levels when mmuWalkProcessPdes is called on sublevels + // + if ((pLevel == pLevelOrig) && (entryIndex == entryIndexHi)) + { + goto done; + } + + // + // Now restore and finish previous frame(s) // - // If this is the last processed sublevel of a level, pdeRelease the level. + // If this is the last processed sublevel of a level or an error has + // previously occurred, pdeRelease the level. // Continue doing so for all parent levels. + // Once we're reached a non-finished level, iterate to the next entry. // - while (entryIndex == entryIndexHi) + while (entryIndex == entryIndexHi || status != NV_OK) { - if ((pReleasePdeEntry = listHead(&releasePdesStack)) != NULL) - { - // Extract variables for the next loop around. - entryIndexHi = pReleasePdeEntry->entryIndexHi; - entryIndex = pReleasePdeEntry->entryIndex; - - _mmuWalkPdeRelease(pWalk, - pOpParams, - pReleasePdeEntry->pLevel, - pReleasePdeEntry->pLevelInst, - pReleasePdeEntry->entryIndex, - pReleasePdeEntry->entryVaLo); - - listRemove(&releasePdesStack, pReleasePdeEntry); - } - else + // + // Now replace the current stack frame with the frame that was one + // level above. This should never be NULL, since we'll already have + // exited after processing the root level. If it is NULL, we can't + // clean up any more anyway, so return immediately. + // + NV_ASSERT_OR_RETURN(pLevel->pParent != NULL, NV_ERR_INVALID_STATE); + + pLevel = pLevel->pParent; + pLevelInst = pLevel->iterInfo.pLevelInst; + vaLo = pLevel->iterInfo.vaLo; + vaHi = pLevel->iterInfo.vaHi; + vaLevelBase = pLevel->iterInfo.vaLevelBase; + entryIndexHi = pLevel->iterInfo.entryIndexHi; + entryIndex = pLevel->iterInfo.entryIndex; + entryIndexFillStart = pLevel->iterInfo.entryIndexFillStart; + entryIndexFillEnd = pLevel->iterInfo.entryIndexFillEnd; + pendingFillCount = pLevel->iterInfo.pendingFillCount; + + _mmuWalkPdeRelease(pWalk, + pOpParams, + pLevel, + pLevelInst, + entryIndex, + pLevel->iterInfo.entryVaLo); + + // + // If we're at the original level and entryIndex = entryIndexHi, + // then we're done and need to exit the entire loop + // + if ((pLevel == pLevelOrig) && (entryIndex == entryIndexHi)) { - break; + goto done; } } - } - else - { - // Stop processing PDEs if we are in error state. - goto cleanupIter; + + // + // Once the above loop is done and we reach here, then we're + // ready to process the next entry in the list. Only iterate here, + // not in the overall loop since we may have iterated down in the + // above else block and don't want to increment before processing + // the first entry on a new lower level. + // + entryIndex++; } } // per entry loop - - if (listHead(&processPdesStack) != NULL) - { - // - // If this assertion fails, it is a result of a programming - // error in the iterative MMU Walker implementation. - // - status = NV_ERR_INVALID_STATE; - NV_ASSERT_OR_GOTO(0, cleanupIter); - } - - // - // Note that if releasePdesStack is not empty at this point, - // we hit an empty sublevel, but we still need to pdeRelease - // the parent sublevels in cleanup below. - // - -// Temporarily change the name of this label to avoid conflicting with other "cleanup" -cleanupIter: - // - // In the recrusive MMU Walker, when a sublevel failed, that level would pdeRelease, - // return to the parent, and the parent would pdeRelease and return to its parent and so on. - // Here emulate that and pdeRelease all parents. + // If this assertion fails, it is a result of a programming + // error in the iterative MMU Walker implementation. We should + // have iterated back updwards through the MMU state to the original + // level even on failure. // - - while ((pReleasePdeEntry = listHead(&releasePdesStack)) != NULL) - { - _mmuWalkPdeRelease(pWalk, - pOpParams, - pReleasePdeEntry->pLevel , - pReleasePdeEntry->pLevelInst, - pReleasePdeEntry->entryIndex, - pReleasePdeEntry->entryVaLo); - - listRemove(&releasePdesStack, pReleasePdeEntry); - } - - listDestroy(&processPdesStack); - listDestroy(&releasePdesStack); - - + NV_ASSERT_OR_RETURN(pLevel != pLevelOrig, NV_ERR_INVALID_STATE); } +done: return status; } else diff --git a/src/nvidia/src/libraries/mmu/mmu_walk_private.h b/src/nvidia/src/libraries/mmu/mmu_walk_private.h index fb2fa5b23f..5ddc5a5dcc 100644 --- a/src/nvidia/src/libraries/mmu/mmu_walk_private.h +++ b/src/nvidia/src/libraries/mmu/mmu_walk_private.h @@ -31,7 +31,6 @@ extern "C" { /* ------------------------ Includes --------------------------------------- */ #include "mmu/mmu_walk.h" #include "containers/btree.h" -#include "containers/list.h" /* --------------------------- Macros ---------------------------------------- */ #define HI_PRI_SUBLEVEL_INDEX 0 @@ -43,9 +42,6 @@ typedef struct MMU_WALK_LEVEL_INST MMU_WALK_LEVEL_INST; typedef struct MMU_WALK_LEVEL MMU_WALK_LEVEL; typedef struct MMU_WALK_OP_PARAMS MMU_WALK_OP_PARAMS; -typedef struct MMU_WALK_PROCESS_PDES_ENTRY MMU_WALK_PROCESS_PDES_ENTRY; -typedef struct MMU_WALK_RELEASE_PDES_ENTRY MMU_WALK_RELEASE_PDES_ENTRY; - /*! * Higher-level PDE/PTE states. */ @@ -97,6 +93,32 @@ typedef struct NvU8 bReserved : 1; } MMU_ENTRY_INFO; +/*! + * Information about the current level iteration state. + * Used for converting the MMU walker to be iterative. + */ +typedef struct +{ + /*! + * Variables cached for traversal/pdeRelease. + */ + MMU_WALK_LEVEL_INST *pLevelInst; + NvU64 vaLo; + NvU64 vaHi; + NvU64 vaLevelBase; + NvU32 entryIndexHi; + NvU32 entryIndex; + NvU32 entryIndexFillStart; + NvU32 entryIndexFillEnd; + NvU32 pendingFillCount; + /*! + * Variable only cached for pdeRelease and not restored + * on the stack + */ + NvU64 entryVaLo; +} MMU_WALK_ITER_INFO; + + /*! * Describes an entire (horizontal) level of an MMU level hiearchy. */ @@ -122,6 +144,11 @@ struct MMU_WALK_LEVEL */ MMU_WALK_LEVEL_INST *pInstances; + /*! + * Struct storing all variables needed for iterative MMU walker + */ + MMU_WALK_ITER_INFO iterInfo; + /*! * Tree tracking ranges of VA that are reserved (locked down) * for this level. @see mmuWalkReserveEntries. @@ -291,28 +318,6 @@ typedef struct extern const MMU_WALK_OP_PARAMS g_opParamsSparsify; extern const MMU_WALK_OP_PARAMS g_opParamsUnmap; -struct MMU_WALK_PROCESS_PDES_ENTRY -{ - MMU_WALK_LEVEL *pLevel; - MMU_WALK_LEVEL_INST *pLevelInst; - NvU64 vaLo; - NvU64 vaHi; - NvU64 vaLevelBase; - NvU32 entryIndexHi; - NvU32 entryIndex; -}; -MAKE_LIST(PROCESS_PDES_STACK, MMU_WALK_PROCESS_PDES_ENTRY); - -struct MMU_WALK_RELEASE_PDES_ENTRY -{ - MMU_WALK_LEVEL *pLevel; - MMU_WALK_LEVEL_INST *pLevelInst; - NvU64 entryVaLo; - NvU32 entryIndexHi; - NvU32 entryIndex; -}; -MAKE_LIST(RELEASE_PDES_STACK, MMU_WALK_RELEASE_PDES_ENTRY); - /*----------------------------Private Interface--------------------------------*/ const MMU_WALK_LEVEL * mmuWalkFindLevel(const MMU_WALK *pWalk, diff --git a/src/nvidia/src/libraries/nvbitvector/nvbitvector.c b/src/nvidia/src/libraries/nvbitvector/nvbitvector.c index 75f487673b..ef5bacfa5b 100644 --- a/src/nvidia/src/libraries/nvbitvector/nvbitvector.c +++ b/src/nvidia/src/libraries/nvbitvector/nvbitvector.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -58,7 +58,7 @@ bitVectorClrAll_IMPL NvU16 bitVectorLast ) { - NvU32 byteSize = NV_BITVECTOR_BYTE_SIZE(bitVectorLast); + NvLength byteSize = NV_BITVECTOR_BYTE_SIZE(bitVectorLast); NV_ASSERT_OR_RETURN(NULL != pBitVector, NV_ERR_INVALID_ARGUMENT); portMemSet(&pBitVector->qword, 0x0, byteSize); @@ -77,8 +77,8 @@ bitVectorClr_IMPL ) { NvU64 *qword; - NvU16 qwordIdx = NV_BITVECTOR_IDX(idx); - NvU16 qwordOffset = NV_BITVECTOR_OFFSET(idx); + NvU32 qwordIdx = NV_BITVECTOR_IDX(idx); + NvU32 qwordOffset = NV_BITVECTOR_OFFSET(idx); NV_ASSERT_OR_RETURN(NULL != pBitVector, NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN(idx < bitVectorLast, NV_ERR_INVALID_ARGUMENT); @@ -139,9 +139,9 @@ bitVectorSetAll_IMPL ) { NvU64 *qword; - NvU32 byteSize = NV_BITVECTOR_BYTE_SIZE(bitVectorLast); + NvLength byteSize = NV_BITVECTOR_BYTE_SIZE(bitVectorLast); NvU32 arraySize = NV_BITVECTOR_ARRAY_SIZE(bitVectorLast); - NvU16 qwordOffset = NV_BITVECTOR_OFFSET(bitVectorLast - 1); + NvU32 qwordOffset = NV_BITVECTOR_OFFSET(bitVectorLast - 1); NV_ASSERT_OR_RETURN(NULL != pBitVector, NV_ERR_INVALID_ARGUMENT); @@ -164,8 +164,8 @@ bitVectorSet_IMPL ) { NvU64 *qword; - NvU16 qwordIdx = NV_BITVECTOR_IDX(idx); - NvU16 qwordOffset = NV_BITVECTOR_OFFSET(idx); + NvU32 qwordIdx = NV_BITVECTOR_IDX(idx); + NvU32 qwordOffset = NV_BITVECTOR_OFFSET(idx); NV_ASSERT_OR_RETURN(NULL != pBitVector, NV_ERR_INVALID_ARGUMENT); @@ -227,8 +227,8 @@ bitVectorInv_IMPL ) { NvU64 *qword; - NvU16 qwordIdx = NV_BITVECTOR_IDX(idx); - NvU16 qwordOffset = NV_BITVECTOR_OFFSET(idx); + NvU32 qwordIdx = NV_BITVECTOR_IDX(idx); + NvU32 qwordOffset = NV_BITVECTOR_OFFSET(idx); NV_ASSERT_OR_RETURN(NULL != pBitVector, NV_ERR_INVALID_ARGUMENT); @@ -327,9 +327,9 @@ bitVectorTestAllSet_IMPL ) { const NvU64 *qword; - NvU16 idx; + NvU32 idx; NvU32 arraySize = NV_BITVECTOR_ARRAY_SIZE(bitVectorLast); - NvU16 qwordOffset = NV_BITVECTOR_OFFSET(bitVectorLast - 1); + NvU32 qwordOffset = NV_BITVECTOR_OFFSET(bitVectorLast - 1); NvU64 mask; NV_ASSERT_OR_RETURN(NULL != pBitVector, NV_FALSE); @@ -360,9 +360,9 @@ bitVectorTestAllCleared_IMPL ) { const NvU64 *qword; - NvU16 idx; + NvU32 idx; NvU32 arraySize = NV_BITVECTOR_ARRAY_SIZE(bitVectorLast); - NvU16 qwordOffset = NV_BITVECTOR_OFFSET(bitVectorLast - 1); + NvU32 qwordOffset = NV_BITVECTOR_OFFSET(bitVectorLast - 1); NvU64 mask; NV_ASSERT_OR_RETURN(NULL != pBitVector, NV_FALSE); @@ -396,9 +396,9 @@ bitVectorTestEqual_IMPL { const NvU64 *qwordA; const NvU64 *qwordB; - NvU16 idx; + NvU32 idx; NvU32 arraySize = NV_BITVECTOR_ARRAY_SIZE(bitVectorALast); - NvU16 qwordOffset = NV_BITVECTOR_OFFSET(bitVectorALast - 1); + NvU32 qwordOffset = NV_BITVECTOR_OFFSET(bitVectorALast - 1); NvU64 mask; NV_ASSERT_OR_RETURN(NULL != pBitVectorA, NV_ERR_INVALID_ARGUMENT); @@ -436,9 +436,9 @@ bitVectorTestIsSubset_IMPL { const NvU64 *qwordA; const NvU64 *qwordB; - NvU16 idx; + NvU32 idx; NvU32 arraySize = NV_BITVECTOR_ARRAY_SIZE(bitVectorALast); - NvU16 qwordOffset = NV_BITVECTOR_OFFSET(bitVectorALast - 1); + NvU32 qwordOffset = NV_BITVECTOR_OFFSET(bitVectorALast - 1); NvU64 mask; NV_ASSERT_OR_RETURN(NULL != pBitVectorA, NV_ERR_INVALID_ARGUMENT); @@ -473,8 +473,8 @@ bitVectorTest_IMPL ) { const NvU64 *qword; - NvU16 qwordIdx = NV_BITVECTOR_IDX(idx); - NvU16 qwordOffset = NV_BITVECTOR_OFFSET(idx); + NvU32 qwordIdx = NV_BITVECTOR_IDX(idx); + NvU32 qwordOffset = NV_BITVECTOR_OFFSET(idx); NV_ASSERT_OR_RETURN(NULL != pBitVector, NV_FALSE); NV_ASSERT_OR_RETURN(idx < bitVectorLast, NV_FALSE); @@ -508,9 +508,9 @@ bitVectorAnd_IMPL NvU64 *qwordDst; const NvU64 *qwordA; const NvU64 *qwordB; - NvU16 idx; + NvU32 idx; NvU32 arraySize = NV_BITVECTOR_ARRAY_SIZE(bitVectorDstLast); - NvU16 qwordOffset = NV_BITVECTOR_OFFSET(bitVectorDstLast - 1); + NvU32 qwordOffset = NV_BITVECTOR_OFFSET(bitVectorDstLast - 1); NvU64 mask; NV_ASSERT_OR_RETURN(NULL != pBitVectorDst, NV_ERR_INVALID_ARGUMENT); @@ -558,9 +558,9 @@ bitVectorOr_IMPL NvU64 *qwordDst; const NvU64 *qwordA; const NvU64 *qwordB; - NvU16 idx; + NvU32 idx; NvU32 arraySize = NV_BITVECTOR_ARRAY_SIZE(bitVectorDstLast); - NvU16 qwordOffset = NV_BITVECTOR_OFFSET(bitVectorDstLast - 1); + NvU32 qwordOffset = NV_BITVECTOR_OFFSET(bitVectorDstLast - 1); NvU64 mask; NV_ASSERT_OR_RETURN(NULL != pBitVectorDst, NV_ERR_INVALID_ARGUMENT); @@ -608,9 +608,9 @@ bitVectorXor_IMPL NvU64 *qwordDst; const NvU64 *qwordA; const NvU64 *qwordB; - NvU16 idx; + NvU32 idx; NvU32 arraySize = NV_BITVECTOR_ARRAY_SIZE(bitVectorDstLast); - NvU16 qwordOffset = NV_BITVECTOR_OFFSET(bitVectorDstLast - 1); + NvU32 qwordOffset = NV_BITVECTOR_OFFSET(bitVectorDstLast - 1); NvU64 mask; NV_ASSERT_OR_RETURN(NULL != pBitVectorDst, NV_ERR_INVALID_ARGUMENT); @@ -654,9 +654,9 @@ bitVectorComplement_IMPL { NvU64 *qwordDst; const NvU64 *qwordSrc; - NvU16 idx; + NvU32 idx; NvU32 arraySize = NV_BITVECTOR_ARRAY_SIZE(bitVectorDstLast); - NvU16 qwordOffset = NV_BITVECTOR_OFFSET(bitVectorDstLast - 1); + NvU32 qwordOffset = NV_BITVECTOR_OFFSET(bitVectorDstLast - 1); NvU64 mask; NV_ASSERT_OR_RETURN(NULL != pBitVectorDst, NV_ERR_INVALID_ARGUMENT); @@ -695,8 +695,8 @@ bitVectorCopy_IMPL NvU16 bitVectorSrcLast ) { - NvU32 byteSizeDst = NV_BITVECTOR_BYTE_SIZE(bitVectorDstLast); - NvU32 byteSizeSrc = NV_BITVECTOR_BYTE_SIZE(bitVectorSrcLast); + NvLength byteSizeDst = NV_BITVECTOR_BYTE_SIZE(bitVectorDstLast); + NvLength byteSizeSrc = NV_BITVECTOR_BYTE_SIZE(bitVectorSrcLast); NV_ASSERT_OR_RETURN(NULL != pBitVectorDst, NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN(NULL != pBitVectorSrc, NV_ERR_INVALID_ARGUMENT); @@ -721,9 +721,9 @@ bitVectorCountTrailingZeros_IMPL ) { const NvU64 *qword; - NvU16 idx; + NvU32 idx; NvU32 arraySize = NV_BITVECTOR_ARRAY_SIZE(bitVectorLast); - NvU16 qwordOffset = NV_BITVECTOR_OFFSET(bitVectorLast - 1); + NvU32 qwordOffset = NV_BITVECTOR_OFFSET(bitVectorLast - 1); NvU64 mask; NV_ASSERT_OR_RETURN(NULL != pBitVector, 0); @@ -758,16 +758,16 @@ bitVectorCountLeadingZeros_IMPL ) { const NvU64 *qword; - NvU16 idx; - NvU16 arraySize = NV_BITVECTOR_ARRAY_SIZE(bitVectorLast); - NvU16 qwordOffset = NV_BITVECTOR_OFFSET(bitVectorLast - 1); - NvU16 qwordUnused = 63 - qwordOffset; + NvU32 idx; + NvU32 arraySize = NV_BITVECTOR_ARRAY_SIZE(bitVectorLast); + NvU32 qwordOffset = NV_BITVECTOR_OFFSET(bitVectorLast - 1); + NvU32 qwordUnused = 63 - qwordOffset; NvU64 mask; NV_ASSERT_OR_RETURN(NULL != pBitVector, 0); qword = (const NvU64 *)&pBitVector->qword; - for (idx = (arraySize - 1); idx != ((NvU16)-1); idx--) + for (idx = (arraySize - 1); idx != (NvU32)-1; idx--) { mask = (idx < arraySize - 1) ? NV_U64_MAX : (NV_U64_MAX >> (63 - qwordOffset)); @@ -798,9 +798,9 @@ bitVectorCountSetBits_IMPL ) { const NvU64 *qword; - NvU16 idx; - NvU16 arraySize = NV_BITVECTOR_ARRAY_SIZE(bitVectorLast); - NvU16 qwordOffset = NV_BITVECTOR_OFFSET(bitVectorLast - 1); + NvU32 idx; + NvU32 arraySize = NV_BITVECTOR_ARRAY_SIZE(bitVectorLast); + NvU32 qwordOffset = NV_BITVECTOR_OFFSET(bitVectorLast - 1); NvU64 mask; NvU32 count; @@ -830,7 +830,7 @@ bitVectorToRaw_IMPL NvU32 rawMaskSize ) { - const NvU32 byteSize = NV_BITVECTOR_BYTE_SIZE(bitVectorLast); + const NvLength byteSize = NV_BITVECTOR_BYTE_SIZE(bitVectorLast); NV_ASSERT_OR_RETURN(NULL != pBitVector, NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN(NULL != pRawMask, NV_ERR_INVALID_ARGUMENT); @@ -852,7 +852,7 @@ bitVectorFromRaw_IMPL NvU32 rawMaskSize ) { - const NvU32 byteSize = NV_BITVECTOR_BYTE_SIZE(bitVectorLast); + const NvLength byteSize = NV_BITVECTOR_BYTE_SIZE(bitVectorLast); NV_ASSERT_OR_RETURN(NULL != pBitVector, NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN(NULL != pRawMask, NV_ERR_INVALID_ARGUMENT); diff --git a/src/nvidia/src/libraries/nvoc/src/runtime.c b/src/nvidia/src/libraries/nvoc/src/runtime.c index ba7314c225..f05c00608f 100644 --- a/src/nvidia/src/libraries/nvoc/src/runtime.c +++ b/src/nvidia/src/libraries/nvoc/src/runtime.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -173,6 +173,12 @@ void __nvoc_objDelete(Dynamic *pDynamic) { return; } + // objCreate might be skipped for NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT objects. + // In result, objDelete will be called on zeroed objects, skip their destruction. + if (pDynamic->__nvoc_rtti == NULL) + { + return; + } pDynamic->__nvoc_rtti->dtor(pDynamic); diff --git a/src/nvidia/src/libraries/nvport/memory/memory_tracking.c b/src/nvidia/src/libraries/nvport/memory/memory_tracking.c index d30f321c42..2cc0f4cc8f 100644 --- a/src/nvidia/src/libraries/nvport/memory/memory_tracking.c +++ b/src/nvidia/src/libraries/nvport/memory/memory_tracking.c @@ -459,7 +459,7 @@ _portMemCallerInfoInitTracking _portMemCallerInfoInitMem(pMem, PORT_MEM_CALLERINFO_PARAM) #if PORT_MEM_TRACK_USE_CALLERINFO_IP -#if NVCPU_IS_RISCV64 +#if NVOS_IS_LIBOS // // Libos has custom %a format specifier that decodes an instruction pointer into // a function / file / line reference when the binary output is decoded. @@ -467,7 +467,7 @@ _portMemCallerInfoInitTracking #define PORT_MEM_CALLERINFO_PRINT_ARGS(x) "@ %a\n", x #else #define PORT_MEM_CALLERINFO_PRINT_ARGS(x) "@ 0x%016x\n", x -#endif // NVCPU_IS_RISCV64 +#endif // NVOS_IS_LIBOS #else #define PORT_MEM_CALLERINFO_PRINT_ARGS(x) "@ %s:%u (%s)\n", x.file, x.line, x.func #endif // PORT_MEM_TRACK_USE_CALLERINFO_IP diff --git a/src/nvidia/src/libraries/resserv/src/rs_server.c b/src/nvidia/src/libraries/resserv/src/rs_server.c index 7e51ea0630..c775f83024 100644 --- a/src/nvidia/src/libraries/resserv/src/rs_server.c +++ b/src/nvidia/src/libraries/resserv/src/rs_server.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -672,10 +672,8 @@ serverAllocResource } else { - status = serverLookupSecondClient(pParams, &hSecondClient); - - if (status != NV_OK) - goto done; + hSecondClient = serverAllocLookupSecondClient(pParams->externalClassId, + pParams->pAllocParams); if (hSecondClient == 0) { @@ -1190,8 +1188,7 @@ serverFreeResourceTree if (bPopFreeStack) { - if (pClient != NULL) - pClient->pFreeStack = freeStack.pPrev; + pClient->pFreeStack = freeStack.pPrev; bPopFreeStack = NV_FALSE; } @@ -1213,7 +1210,7 @@ serverFreeResourceTree if (bReAcquireLock) { serverTopLock_Epilogue(pServer, topLockAccess, pLockInfo, &releaseFlags); - serverTopLock_Prologue(pServer, LOCK_ACCESS_WRITE, pLockInfo, &releaseFlags); + NV_CHECK_OK(status, LEVEL_INFO, serverTopLock_Prologue(pServer, LOCK_ACCESS_WRITE, pLockInfo, &releaseFlags)); _serverFreeClient(pServer, &clientFreeParams); serverTopLock_Epilogue(pServer, LOCK_ACCESS_WRITE, pLockInfo, &releaseFlags); initialLockState &= ~RS_LOCK_STATE_CLIENT_LOCK_ACQUIRED; @@ -2433,10 +2430,10 @@ _serverLockClient } pClient = pClientEntry->pClient; - NV_ASSERT(pClient->hClient == pClientEntry->hClient); if ((pClient == NULL) || (pClient->hClient != hClient)) { + NV_ASSERT(0); if (access == LOCK_ACCESS_READ) RS_RWLOCK_RELEASE_READ(pClientEntry->pLock, &pClientEntry->lockVal); else @@ -3320,16 +3317,14 @@ serverAllocEpilogue_WAR return status; } -NV_STATUS -serverLookupSecondClient +NvHandle +serverAllocLookupSecondClient ( - RS_RES_ALLOC_PARAMS_INTERNAL *pParams, - NvHandle *phClient + NvU32 externalClassId, + void *pAllocParams ) { - *phClient = 0; - - return NV_OK; + return 0; } NV_STATUS serverTopLock_Prologue @@ -3856,7 +3851,7 @@ NV_STATUS serverControl_Prologue if (status != NV_OK) return status; - serverControlLookupLockFlags(pServer, RS_LOCK_RESOURCE, pParams, pParams->pCookie, pAccess); + status = serverControlLookupLockFlags(pServer, RS_LOCK_RESOURCE, pParams, pParams->pCookie, pAccess); if (status != NV_OK) return status; diff --git a/src/nvidia/src/libraries/utils/nvassert.c b/src/nvidia/src/libraries/utils/nvassert.c index 828e34b790..4856cf6606 100644 --- a/src/nvidia/src/libraries/utils/nvassert.c +++ b/src/nvidia/src/libraries/utils/nvassert.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -35,9 +35,6 @@ #include "os/os.h" #include "nvrm_registry.h" #include "rmconfig.h" -#include "gpu/gpu.h" -#include "gpu/gpu_user_shared_data.h" -#include "class/cl00de.h" #elif !defined(RMCFG_FEATURE_ENABLED) #define RMCFG_FEATURE_x 0 #endif @@ -55,44 +52,26 @@ void rcdbRmAssertStatus(NvU32 status, NvU32 lineNum, NvU64 ip); #define NV_JOURNAL_ASSERT_FAILURE_STATUS(lineNum, ip, status) ((void)0) #endif /* NV_JOURNAL_ASSERT_ENABLE*/ -#if defined(GSP_PLUGIN_BUILD) || (defined(NVRM) && NVCPU_IS_RISCV64) +#if defined(GSP_PLUGIN_BUILD) || (defined(NVRM) && NVOS_IS_LIBOS) #if NV_JOURNAL_ASSERT_ENABLE -static void -_logAssertCount(void) -{ - static NvU32 assertCount = 0; - NV00DE_SHARED_DATA *pSharedData; - - if (g_pGpu == NULL) - { - return; - } - - pSharedData = gpushareddataWriteStart(g_pGpu); - pSharedData->gspAssertCount = ++assertCount; - gpushareddataWriteFinish(g_pGpu); -} - /* * Helper function for NV_ASSERT_FAILED */ void nvAssertFailed(void) { - _logAssertCount(); NV_JOURNAL_ASSERT_FAILURE(NV_RM_ASSERT_UNKNOWN_LINE_NUM, portUtilGetReturnAddress()); } void nvAssertOkFailed(NvU32 status) { - _logAssertCount(); NV_JOURNAL_ASSERT_FAILURE_STATUS(NV_RM_ASSERT_UNKNOWN_LINE_NUM, portUtilGetReturnAddress(), status); } #endif -#else //defined(GSP_PLUGIN_BUILD) || (defined(NVRM) && NVCPU_IS_RISCV64) +#else //defined(GSP_PLUGIN_BUILD) || (defined(NVRM) && NVOS_IS_LIBOS) #if NV_ASSERT_FAILED_USES_STRINGS #define NV_ASSERT_FAILED_PRINTF_FMT "%s @ %s:%d\n" @@ -277,7 +256,7 @@ nvCheckOkFailedNoLog nvAssertStatusToString(status), status, NV_ASSERT_FAILED_PRINTF_PARAM); } -#endif // defined(GSP_PLUGIN_BUILD) || (defined(NVRM) && NVCPU_IS_RISCV64) +#endif // defined(GSP_PLUGIN_BUILD) || (defined(NVRM) && NVOS_IS_LIBOS) #endif // NV_PRINTF_ENABLED || NV_JOURNAL_ASSERT_ENABLE /* @@ -290,11 +269,11 @@ nvCheckOkFailedNoLog */ #if !defined(NV_PRINTF_STRING_SECTION) -#if defined(NVRM) && NVCPU_IS_RISCV64 -#define NV_PRINTF_STRING_SECTION __attribute__ ((section (".logging"))) -#else // defined(NVRM) && NVCPU_IS_RISCV64 +#if defined(NVRM) && NVOS_IS_LIBOS +#define NV_PRINTF_STRING_SECTION LIBOS_SECTION_LOGGING +#else // defined(NVRM) && NVOS_IS_LIBOS #define NV_PRINTF_STRING_SECTION -#endif // defined(NVRM) && NVCPU_IS_RISCV64 +#endif // defined(NVRM) && NVOS_IS_LIBOS #endif // !defined(NV_PRINTF_STRING_SECTION) #undef NV_STATUS_CODE diff --git a/src/nvidia/srcs.mk b/src/nvidia/srcs.mk index 4a61ee1a34..3497ff2428 100644 --- a/src/nvidia/srcs.mk +++ b/src/nvidia/srcs.mk @@ -112,6 +112,7 @@ SRCS += generated/g_kernel_sched_mgr_nvoc.c SRCS += generated/g_kernel_sec2_nvoc.c SRCS += generated/g_kernel_sm_debugger_session_nvoc.c SRCS += generated/g_kernel_vgpu_mgr_nvoc.c +SRCS += generated/g_kernel_video_engine_nvoc.c SRCS += generated/g_mem_fabric_nvoc.c SRCS += generated/g_mem_list_nvoc.c SRCS += generated/g_mem_mapper_nvoc.c @@ -192,6 +193,7 @@ SRCS += ../common/nvlink/kernel/nvlink/core/nvlink_logger.c SRCS += ../common/nvlink/kernel/nvlink/core/nvlink_shutdown.c SRCS += ../common/nvlink/kernel/nvlink/core/nvlink_training.c SRCS += ../common/nvlink/kernel/nvlink/interface/nvlink_ioctl_entry.c +SRCS += ../common/nvlink/kernel/nvlink/interface/nvlink_kern_device_mgmt_entry.c SRCS += ../common/nvlink/kernel/nvlink/interface/nvlink_kern_discovery_entry.c SRCS += ../common/nvlink/kernel/nvlink/interface/nvlink_kern_initialize_entry.c SRCS += ../common/nvlink/kernel/nvlink/interface/nvlink_kern_link_mgmt_entry.c @@ -325,6 +327,7 @@ SRCS += src/kernel/gpu/arch/turing/kern_gpu_tu102.c SRCS += src/kernel/gpu/audio/hda_codec_api.c SRCS += src/kernel/gpu/bif/arch/ada/kernel_bif_ad102.c SRCS += src/kernel/gpu/bif/arch/ampere/kernel_bif_ga100.c +SRCS += src/kernel/gpu/bif/arch/ampere/kernel_bif_ga102.c SRCS += src/kernel/gpu/bif/arch/hopper/kernel_bif_gh100.c SRCS += src/kernel/gpu/bif/arch/maxwell/kernel_bif_gm107.c SRCS += src/kernel/gpu/bif/arch/turing/kernel_bif_tu102.c @@ -442,6 +445,7 @@ SRCS += src/kernel/gpu/gpu_suspend.c SRCS += src/kernel/gpu/gpu_timeout.c SRCS += src/kernel/gpu/gpu_user_shared_data.c SRCS += src/kernel/gpu/gpu_uuid.c +SRCS += src/kernel/gpu/gr/arch/ampere/kgrmgr_ga100.c SRCS += src/kernel/gpu/gr/arch/maxwell/kgraphics_gm200.c SRCS += src/kernel/gpu/gr/arch/pascal/kgraphics_gp100.c SRCS += src/kernel/gpu/gr/arch/turing/kgraphics_tu102.c @@ -495,6 +499,7 @@ SRCS += src/kernel/gpu/mem_mgr/arch/ampere/mem_mgr_ga102.c SRCS += src/kernel/gpu/mem_mgr/arch/hopper/mem_utils_gh100.c SRCS += src/kernel/gpu/mem_mgr/arch/hopper/virt_mem_allocator_gh100.c SRCS += src/kernel/gpu/mem_mgr/arch/maxwell/fbsr_gm107.c +SRCS += src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_cmn_gm107.c SRCS += src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm107.c SRCS += src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm200.c SRCS += src/kernel/gpu/mem_mgr/arch/maxwell/mem_utils_gm107.c @@ -594,6 +599,7 @@ SRCS += src/kernel/gpu/nvlink/kernel_nvlinkcorelibtrain.c SRCS += src/kernel/gpu/nvlink/kernel_nvlinkoverrides.c SRCS += src/kernel/gpu/nvlink/kernel_nvlinkstate.c SRCS += src/kernel/gpu/ofa/kernel_ofa_ctx.c +SRCS += src/kernel/gpu/ofa/kernel_ofa_engdesc.c SRCS += src/kernel/gpu/perf/kern_cuda_limit.c SRCS += src/kernel/gpu/perf/kern_perf.c SRCS += src/kernel/gpu/perf/kern_perf_boost.c @@ -646,6 +652,7 @@ SRCS += src/kernel/gpu/uvm/access_cntr_buffer_ctrl.c SRCS += src/kernel/gpu/uvm/arch/turing/uvm_tu102.c SRCS += src/kernel/gpu/uvm/arch/volta/uvm_gv100.c SRCS += src/kernel/gpu/uvm/uvm.c +SRCS += src/kernel/gpu/video/kernel_video_engine.c SRCS += src/kernel/gpu_mgr/gpu_db.c SRCS += src/kernel/gpu_mgr/gpu_group.c SRCS += src/kernel/gpu_mgr/gpu_mgmt_api.c diff --git a/utils.mk b/utils.mk index b29a709d91..bfa4b05121 100644 --- a/utils.mk +++ b/utils.mk @@ -565,11 +565,26 @@ endef # $(1): Path to the file to convert ############################################################################## +LD_TARGET_EMULATION_FLAG = +LD_TARGET_EMULATION_FLAG_Linux_x86 = elf_i386 +LD_TARGET_EMULATION_FLAG_Linux_x86_64 = elf_x86_64 +LD_TARGET_EMULATION_FLAG_Linux_aarch64 = aarch64elf +LD_TARGET_EMULATION_FLAG_Linux_ppc64le = elf64lppc +LD_TARGET_EMULATION_FLAG_SunOS_x86 = elf_i386_sol2 +LD_TARGET_EMULATION_FLAG_SunOS_x86_64 = elf_x86_64_sol2 +LD_TARGET_EMULATION_FLAG_FreeBSD_x86 = elf_i386_fbsd +LD_TARGET_EMULATION_FLAG_FreeBSD_x86_64 = elf_x86_64_fbsd + +ifdef LD_TARGET_EMULATION_FLAG_$(TARGET_OS)_$(TARGET_ARCH) + LD_TARGET_EMULATION_FLAG = -m $(LD_TARGET_EMULATION_FLAG_$(TARGET_OS)_$(TARGET_ARCH)) +endif + define READ_ONLY_OBJECT_FROM_FILE_RULE $$(OUTPUTDIR)/$$(notdir $(1)).o: $(1) $(at_if_quiet)$$(MKDIR) $$(OUTPUTDIR) $(at_if_quiet)cd $$(dir $(1)); \ $$(call quiet_cmd_no_at,LD) -r -z noexecstack --format=binary \ + $$(LD_TARGET_EMULATION_FLAG) \ $$(notdir $(1)) -o $$(OUTPUTDIR_ABSOLUTE)/$$(notdir $$@) $$(call quiet_cmd,OBJCOPY) \ --rename-section .data=.rodata,contents,alloc,load,data,readonly \ diff --git a/version.mk b/version.mk index 2c20c473a0..428c7dfe8b 100644 --- a/version.mk +++ b/version.mk @@ -1,4 +1,4 @@ -NVIDIA_VERSION = 535.113.01 +NVIDIA_VERSION = 545.23.06 # This file. VERSION_MK_FILE := $(lastword $(MAKEFILE_LIST))