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vivado_7824.backup.log
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vivado_7824.backup.log
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#-----------------------------------------------------------
# Vivado v2020.2 (64-bit)
# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
# IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
# Start of session at: Tue Jan 4 13:59:14 2022
# Process ID: 7824
# Current directory: D:/Projet_instrum_MHAH
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent5892 D:\Projet_instrum_MHAH\Projet_instrum_MHAH.xpr
# Log file: D:/Projet_instrum_MHAH/vivado.log
# Journal file: D:/Projet_instrum_MHAH\vivado.jou
#-----------------------------------------------------------
start_gui
open_project D:/Projet_instrum_MHAH/Projet_instrum_MHAH.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2020.2/data/ip'.
open_project: Time (s): cpu = 00:00:18 ; elapsed = 00:00:12 . Memory (MB): peak = 1091.355 ; gain = 0.000
update_compile_order -fileset sources_1
set_property SOURCE_SET sources_1 [get_filesets sim_1]
close [ open D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sim_1/new/tb_division.vhd w ]
add_files -fileset sim_1 D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sim_1/new/tb_division.vhd
update_compile_order -fileset sim_1
set_property top division [current_fileset]
update_compile_order -fileset sources_1
set_property top tb_division [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
update_compile_order -fileset sim_1
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2020.2/data/xsim/xsim.ini' copied to run dir:'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_division' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj tb_division_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/division.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'division'
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sim_1/new/tb_division.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'tb_division'
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xelab -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_division_behav xil_defaultlib.tb_division -log elaborate.log"
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_division_behav xil_defaultlib.tb_division -log elaborate.log
Using 2 slave threads.
Starting static elaboration
ERROR: [VRFC 10-664] expression has 46 elements ; expected 36 [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/division.vhd:45]
ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit tb_division in library work failed.
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
INFO: [USF-XSim-99] Step results log file:'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim/elaborate.log'
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim/elaborate.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:10 . Memory (MB): peak = 1091.355 ; gain = 0.000
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2020.2/data/xsim/xsim.ini' copied to run dir:'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_division' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj tb_division_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/division.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'division'
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xelab -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_division_behav xil_defaultlib.tb_division -log elaborate.log"
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_division_behav xil_defaultlib.tb_division -log elaborate.log
Using 2 slave threads.
Starting static elaboration
ERROR: [VRFC 10-664] expression has 15 elements ; expected 14 [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/division.vhd:57]
ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit tb_division in library work failed.
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
INFO: [USF-XSim-99] Step results log file:'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim/elaborate.log'
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim/elaborate.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
launch_simulation: Time (s): cpu = 00:00:00 ; elapsed = 00:00:08 . Memory (MB): peak = 1091.355 ; gain = 0.000
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2020.2/data/xsim/xsim.ini' copied to run dir:'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_division' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj tb_division_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/division.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'division'
INFO: [USF-XSim-69] 'compile' step finished in '4' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xelab -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_division_behav xil_defaultlib.tb_division -log elaborate.log"
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_division_behav xil_defaultlib.tb_division -log elaborate.log
Using 2 slave threads.
Starting static elaboration
ERROR: [VRFC 10-664] expression has 46 elements ; expected 47 [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/division.vhd:45]
ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit tb_division in library work failed.
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
INFO: [USF-XSim-99] Step results log file:'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim/elaborate.log'
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim/elaborate.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 1091.355 ; gain = 0.000
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2020.2/data/xsim/xsim.ini' copied to run dir:'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_division' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj tb_division_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/division.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'division'
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xelab -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_division_behav xil_defaultlib.tb_division -log elaborate.log"
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_division_behav xil_defaultlib.tb_division -log elaborate.log
Using 2 slave threads.
Starting static elaboration
ERROR: [VRFC 10-664] expression has 27 elements ; expected 14 [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/division.vhd:70]
ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit tb_division in library work failed.
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
INFO: [USF-XSim-99] Step results log file:'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim/elaborate.log'
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim/elaborate.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1091.355 ; gain = 0.000
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2020.2/data/xsim/xsim.ini' copied to run dir:'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_division' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj tb_division_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/division.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'division'
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xelab -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_division_behav xil_defaultlib.tb_division -log elaborate.log"
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_division_behav xil_defaultlib.tb_division -log elaborate.log
Using 2 slave threads.
Starting static elaboration
WARNING: [VRFC 10-975] left bound value <27> of slice is out of range [26:0] of array <resultat> [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/division.vhd:70]
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling architecture behavioral of entity xil_defaultlib.division [division_default]
Compiling architecture behavioral of entity xil_defaultlib.tb_division
Built simulation snapshot tb_division_behav
****** Webtalk v2020.2 (64-bit)
**** SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
**** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
source D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim/xsim.dir/tb_division_behav/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Tue Jan 4 15:31:42 2022...
run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:08 . Memory (MB): peak = 1091.355 ; gain = 0.000
INFO: [USF-XSim-69] 'elaborate' step finished in '8' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_division_behav -key {Behavioral:sim_1:Functional:tb_division} -tclbatch {tb_division.tcl} -view {D:/Projet_instrum_MHAH/tb_filter_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2020.2
Time resolution is 1 ps
open_wave_config D:/Projet_instrum_MHAH/tb_filter_behav.wcfg
WARNING: Simulation object /tb_filter/s_input_filt was not found in the design.
WARNING: Simulation object /tb_filter/s_output_filt was not found in the design.
WARNING: Simulation object /tb_filter/s_clk was not found in the design.
WARNING: Simulation object /tb_filter/clk_period was not found in the design.
WARNING: Simulation object /tb_filter/U_filter/enable_latch was not found in the design.
WARNING: Simulation object /tb_filter/U_filter/xk_1 was not found in the design.
WARNING: Simulation object /tb_filter/U_filter/xk was not found in the design.
WARNING: Simulation object /tb_filter/U_filter/yk_1 was not found in the design.
WARNING: Simulation object /tb_filter/U_filter/yk was not found in the design.
source tb_division.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_division_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:08 ; elapsed = 00:00:18 . Memory (MB): peak = 1091.355 ; gain = 0.000
save_wave_config {D:/Projet_instrum_MHAH/tb_filter_behav.wcfg}
run 200 ns
run 1 ms
save_wave_config {D:/Projet_instrum_MHAH/tb_filter_behav.wcfg}
close_sim
INFO: [Simtcl 6-16] Simulation closed
close_sim: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 1167.348 ; gain = 0.000
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2020.2/data/xsim/xsim.ini' copied to run dir:'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_division' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj tb_division_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sim_1/new/tb_division.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'tb_division'
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xelab -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_division_behav xil_defaultlib.tb_division -log elaborate.log"
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_division_behav xil_defaultlib.tb_division -log elaborate.log
Using 2 slave threads.
Starting static elaboration
WARNING: [VRFC 10-975] left bound value <27> of slice is out of range [26:0] of array <resultat> [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/division.vhd:70]
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling architecture behavioral of entity xil_defaultlib.division [division_default]
Compiling architecture behavioral of entity xil_defaultlib.tb_division
Built simulation snapshot tb_division_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_division_behav -key {Behavioral:sim_1:Functional:tb_division} -tclbatch {tb_division.tcl} -view {D:/Projet_instrum_MHAH/tb_filter_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2020.2
Time resolution is 1 ps
open_wave_config D:/Projet_instrum_MHAH/tb_filter_behav.wcfg
source tb_division.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_division_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:10 . Memory (MB): peak = 1167.348 ; gain = 0.000
save_wave_config {D:/Projet_instrum_MHAH/tb_filter_behav.wcfg}
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2020.2/data/xsim/xsim.ini' copied to run dir:'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_division' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj tb_division_vhdl.prj"
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xelab -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_division_behav xil_defaultlib.tb_division -log elaborate.log"
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_division_behav xil_defaultlib.tb_division -log elaborate.log
Using 2 slave threads.
Starting static elaboration
WARNING: [VRFC 10-975] left bound value <27> of slice is out of range [26:0] of array <resultat> [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/division.vhd:70]
Completed static elaboration
INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_division_behav -key {Behavioral:sim_1:Functional:tb_division} -tclbatch {tb_division.tcl} -view {D:/Projet_instrum_MHAH/tb_filter_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2020.2
Time resolution is 1 ps
open_wave_config D:/Projet_instrum_MHAH/tb_filter_behav.wcfg
source tb_division.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_division_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:10 . Memory (MB): peak = 1167.348 ; gain = 0.000
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2020.2/data/xsim/xsim.ini' copied to run dir:'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_division' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj tb_division_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/division.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'division'
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sim_1/new/tb_division.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'tb_division'
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xelab -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_division_behav xil_defaultlib.tb_division -log elaborate.log"
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_division_behav xil_defaultlib.tb_division -log elaborate.log
Using 2 slave threads.
Starting static elaboration
WARNING: [VRFC 10-975] left bound value <27> of slice is out of range [26:0] of array <resultat> [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/division.vhd:71]
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling architecture behavioral of entity xil_defaultlib.division [division_default]
Compiling architecture behavioral of entity xil_defaultlib.tb_division
Built simulation snapshot tb_division_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_division_behav -key {Behavioral:sim_1:Functional:tb_division} -tclbatch {tb_division.tcl} -view {D:/Projet_instrum_MHAH/tb_filter_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2020.2
Time resolution is 1 ps
open_wave_config D:/Projet_instrum_MHAH/tb_filter_behav.wcfg
source tb_division.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_division_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:12 . Memory (MB): peak = 1180.148 ; gain = 0.000
save_wave_config {D:/Projet_instrum_MHAH/tb_filter_behav.wcfg}
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2020.2/data/xsim/xsim.ini' copied to run dir:'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_division' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj tb_division_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/division.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'division'
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xelab -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_division_behav xil_defaultlib.tb_division -log elaborate.log"
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_division_behav xil_defaultlib.tb_division -log elaborate.log
Using 2 slave threads.
Starting static elaboration
WARNING: [VRFC 10-975] left bound value <27> of slice is out of range [26:0] of array <resultat> [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/division.vhd:71]
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling architecture behavioral of entity xil_defaultlib.division [division_default]
Compiling architecture behavioral of entity xil_defaultlib.tb_division
Built simulation snapshot tb_division_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_division_behav -key {Behavioral:sim_1:Functional:tb_division} -tclbatch {tb_division.tcl} -view {D:/Projet_instrum_MHAH/tb_filter_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2020.2
Time resolution is 1 ps
open_wave_config D:/Projet_instrum_MHAH/tb_filter_behav.wcfg
source tb_division.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_division_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:12 . Memory (MB): peak = 1180.148 ; gain = 0.000
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2020.2/data/xsim/xsim.ini' copied to run dir:'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_division' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj tb_division_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/division.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'division'
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xelab -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_division_behav xil_defaultlib.tb_division -log elaborate.log"
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_division_behav xil_defaultlib.tb_division -log elaborate.log
Using 2 slave threads.
Starting static elaboration
WARNING: [VRFC 10-975] left bound value <27> of slice is out of range [26:0] of array <resultat> [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/division.vhd:71]
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling architecture behavioral of entity xil_defaultlib.division [division_default]
Compiling architecture behavioral of entity xil_defaultlib.tb_division
Built simulation snapshot tb_division_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_division_behav -key {Behavioral:sim_1:Functional:tb_division} -tclbatch {tb_division.tcl} -view {D:/Projet_instrum_MHAH/tb_filter_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2020.2
Time resolution is 1 ps
open_wave_config D:/Projet_instrum_MHAH/tb_filter_behav.wcfg
source tb_division.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
FATAL_ERROR: Vivado Simulator kernel has discovered an exceptional condition from which it cannot recover. Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.
Time: 690 ns Iteration: 1 Process: /tb_division/division1/line__54
File: D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/division.vhd
HDL Line: D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/division.vhd:71
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_division_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:12 . Memory (MB): peak = 1180.148 ; gain = 0.000
run 100 ns
ERROR: [Simulator 45-1] A fatal run-time error was detected. Simulation cannot continue.
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2020.2/data/xsim/xsim.ini' copied to run dir:'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_division' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj tb_division_vhdl.prj"
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xelab -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_division_behav xil_defaultlib.tb_division -log elaborate.log"
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_division_behav xil_defaultlib.tb_division -log elaborate.log
Using 2 slave threads.
Starting static elaboration
WARNING: [VRFC 10-975] left bound value <27> of slice is out of range [26:0] of array <resultat> [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/division.vhd:71]
Completed static elaboration
INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_division_behav -key {Behavioral:sim_1:Functional:tb_division} -tclbatch {tb_division.tcl} -view {D:/Projet_instrum_MHAH/tb_filter_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2020.2
Time resolution is 1 ps
open_wave_config D:/Projet_instrum_MHAH/tb_filter_behav.wcfg
source tb_division.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
FATAL_ERROR: Vivado Simulator kernel has discovered an exceptional condition from which it cannot recover. Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.
Time: 690 ns Iteration: 1 Process: /tb_division/division1/line__54
File: D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/division.vhd
HDL Line: D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/division.vhd:71
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_division_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 1180.148 ; gain = 0.000
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2020.2/data/xsim/xsim.ini' copied to run dir:'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_division' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj tb_division_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/division.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'division'
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xelab -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_division_behav xil_defaultlib.tb_division -log elaborate.log"
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_division_behav xil_defaultlib.tb_division -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling architecture behavioral of entity xil_defaultlib.division [division_default]
Compiling architecture behavioral of entity xil_defaultlib.tb_division
Built simulation snapshot tb_division_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_division_behav -key {Behavioral:sim_1:Functional:tb_division} -tclbatch {tb_division.tcl} -view {D:/Projet_instrum_MHAH/tb_filter_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2020.2
Time resolution is 1 ps
open_wave_config D:/Projet_instrum_MHAH/tb_filter_behav.wcfg
source tb_division.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_division_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:12 . Memory (MB): peak = 1180.148 ; gain = 0.000
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2020.2/data/xsim/xsim.ini' copied to run dir:'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_division' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj tb_division_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sim_1/new/tb_division.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'tb_division'
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xelab -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_division_behav xil_defaultlib.tb_division -log elaborate.log"
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_division_behav xil_defaultlib.tb_division -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling architecture behavioral of entity xil_defaultlib.division [division_default]
Compiling architecture behavioral of entity xil_defaultlib.tb_division
Built simulation snapshot tb_division_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_division_behav -key {Behavioral:sim_1:Functional:tb_division} -tclbatch {tb_division.tcl} -view {D:/Projet_instrum_MHAH/tb_filter_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2020.2
Time resolution is 1 ps
open_wave_config D:/Projet_instrum_MHAH/tb_filter_behav.wcfg
source tb_division.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_division_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:11 . Memory (MB): peak = 1180.148 ; gain = 0.000
save_wave_config {D:/Projet_instrum_MHAH/tb_filter_behav.wcfg}
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2020.2/data/xsim/xsim.ini' copied to run dir:'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_division' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj tb_division_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/division.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'division'
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xelab -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_division_behav xil_defaultlib.tb_division -log elaborate.log"
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_division_behav xil_defaultlib.tb_division -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling architecture behavioral of entity xil_defaultlib.division [division_default]
Compiling architecture behavioral of entity xil_defaultlib.tb_division
Built simulation snapshot tb_division_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_division_behav -key {Behavioral:sim_1:Functional:tb_division} -tclbatch {tb_division.tcl} -view {D:/Projet_instrum_MHAH/tb_filter_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2020.2
Time resolution is 1 ps
open_wave_config D:/Projet_instrum_MHAH/tb_filter_behav.wcfg
source tb_division.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_division_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:10 . Memory (MB): peak = 1180.148 ; gain = 0.000
launch_simulation -mode post-synthesis -type functional
Command: launch_simulation -mode post-synthesis -type functional
INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/synth/func/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
Design is defaulting to impl run constrset: constrs_1
Design is defaulting to synth run part: xc7a100tcsg324-3
INFO: [Device 21-403] Loading part xc7a100tcsg324-3
INFO: [Common 17-41] Interrupt caught. Command should exit soon.
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1472.961 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 5 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2020.2
open_run: Time (s): cpu = 00:00:08 ; elapsed = 00:00:16 . Memory (MB): peak = 1474.180 ; gain = 294.031
INFO: [Common 17-344] 'open_run' was cancelled
INFO: [Vivado 12-5357] 'setup' step aborted
launch_simulation: Time (s): cpu = 00:00:08 ; elapsed = 00:00:16 . Memory (MB): peak = 1474.180 ; gain = 294.031
INFO: [Common 17-344] 'launch_simulation' was cancelled
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2020.2/data/xsim/xsim.ini' copied to run dir:'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_division' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj tb_division_vhdl.prj"
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xelab -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_division_behav xil_defaultlib.tb_division -log elaborate.log"
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_division_behav xil_defaultlib.tb_division -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_division_behav -key {Behavioral:sim_1:Functional:tb_division} -tclbatch {tb_division.tcl} -view {D:/Projet_instrum_MHAH/tb_filter_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2020.2
Time resolution is 1 ps
open_wave_config D:/Projet_instrum_MHAH/tb_filter_behav.wcfg
source tb_division.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_division_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 1474.180 ; gain = 0.000
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2020.2/data/xsim/xsim.ini' copied to run dir:'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_division' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj tb_division_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/division.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'division'
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xelab -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_division_behav xil_defaultlib.tb_division -log elaborate.log"
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_division_behav xil_defaultlib.tb_division -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling architecture behavioral of entity xil_defaultlib.division [division_default]
Compiling architecture behavioral of entity xil_defaultlib.tb_division
Built simulation snapshot tb_division_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_division_behav -key {Behavioral:sim_1:Functional:tb_division} -tclbatch {tb_division.tcl} -view {D:/Projet_instrum_MHAH/tb_filter_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2020.2
Time resolution is 1 ps
open_wave_config D:/Projet_instrum_MHAH/tb_filter_behav.wcfg
source tb_division.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_division_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:11 . Memory (MB): peak = 2459.922 ; gain = 0.000
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2020.2/data/xsim/xsim.ini' copied to run dir:'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_division' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj tb_division_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sim_1/new/tb_division.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'tb_division'
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xelab -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_division_behav xil_defaultlib.tb_division -log elaborate.log"
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_division_behav xil_defaultlib.tb_division -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling architecture behavioral of entity xil_defaultlib.division [division_default]
Compiling architecture behavioral of entity xil_defaultlib.tb_division
Built simulation snapshot tb_division_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_division_behav -key {Behavioral:sim_1:Functional:tb_division} -tclbatch {tb_division.tcl} -view {D:/Projet_instrum_MHAH/tb_filter_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2020.2
Time resolution is 1 ps
open_wave_config D:/Projet_instrum_MHAH/tb_filter_behav.wcfg
source tb_division.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_division_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:11 . Memory (MB): peak = 2459.922 ; gain = 0.000
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2020.2/data/xsim/xsim.ini' copied to run dir:'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_division' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj tb_division_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/division.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'division'
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xelab -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_division_behav xil_defaultlib.tb_division -log elaborate.log"
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_division_behav xil_defaultlib.tb_division -log elaborate.log
Using 2 slave threads.
Starting static elaboration
ERROR: [VRFC 10-664] expression has 13 elements ; expected 14 [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/division.vhd:72]
ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit tb_division in library work failed.
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
INFO: [USF-XSim-99] Step results log file:'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim/elaborate.log'
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim/elaborate.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 2459.922 ; gain = 0.000
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2020.2/data/xsim/xsim.ini' copied to run dir:'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_division' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj tb_division_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/division.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'division'
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design