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vivado_1700.backup.log
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vivado_1700.backup.log
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#-----------------------------------------------------------
# Vivado v2020.2 (64-bit)
# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
# IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
# Start of session at: Sun Jan 16 16:20:28 2022
# Process ID: 1700
# Current directory: D:/Projet_instrum_MHAH
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent11048 D:\Projet_instrum_MHAH\Projet_instrum_MHAH.xpr
# Log file: D:/Projet_instrum_MHAH/vivado.log
# Journal file: D:/Projet_instrum_MHAH\vivado.jou
#-----------------------------------------------------------
start_gui
open_project D:/Projet_instrum_MHAH/Projet_instrum_MHAH.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2020.2/data/ip'.
open_project: Time (s): cpu = 00:00:15 ; elapsed = 00:00:08 . Memory (MB): peak = 1110.664 ; gain = 0.000
update_compile_order -fileset sources_1
create_fileset -simset sim_2
set_property SOURCE_SET sources_1 [get_filesets sim_1]
close [ open D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sim_1/new/tb_compt_period.vhd w ]
add_files -fileset sim_1 D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sim_1/new/tb_compt_period.vhd
update_compile_order -fileset sim_1
set_property top tb_compt_period [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
update_compile_order -fileset sim_1
set_property top tb_division [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
update_compile_order -fileset sim_1
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2020.2/data/xsim/xsim.ini' copied to run dir:'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_division' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj tb_division_vhdl.prj"
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xelab -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_division_behav xil_defaultlib.tb_division -log elaborate.log"
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_division_behav xil_defaultlib.tb_division -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_division_behav -key {Behavioral:sim_1:Functional:tb_division} -tclbatch {tb_division.tcl} -view {D:/Projet_instrum_MHAH/tb_filter_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2020.2
Time resolution is 1 ps
open_wave_config D:/Projet_instrum_MHAH/tb_filter_behav.wcfg
source tb_division.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_division_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1110.664 ; gain = 0.000
set_property top tb_compt_period [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
update_compile_order -fileset sim_1
set_property top compt_period [current_fileset]
update_compile_order -fileset sources_1
launch_simulation
Command: launch_simulation
boost::filesystem::remove: Le processus ne peut pas accéder au fichier car ce fichier est utilisé par un autre processus: "D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim/simulate.log"
launch_simulation
Command: launch_simulation
boost::filesystem::remove: Le processus ne peut pas accéder au fichier car ce fichier est utilisé par un autre processus: "D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim/simulate.log"
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2020.2/data/xsim/xsim.ini' copied to run dir:'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_compt_period' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj tb_compt_period_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/compt_period.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'compt_period'
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sim_1/new/tb_compt_period.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'tb_compt_period'
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xelab -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_compt_period_behav xil_defaultlib.tb_compt_period -log elaborate.log"
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_compt_period_behav xil_defaultlib.tb_compt_period -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling architecture behavioral of entity xil_defaultlib.compt_period [compt_period_default]
Compiling architecture behavioral of entity xil_defaultlib.tb_compt_period
Built simulation snapshot tb_compt_period_behav
****** Webtalk v2020.2 (64-bit)
**** SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
**** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
source D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim/xsim.dir/tb_compt_period_behav/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Sun Jan 16 16:31:27 2022...
run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:06 . Memory (MB): peak = 1110.664 ; gain = 0.000
INFO: [USF-XSim-69] 'elaborate' step finished in '6' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_compt_period_behav -key {Behavioral:sim_1:Functional:tb_compt_period} -tclbatch {tb_compt_period.tcl} -view {D:/Projet_instrum_MHAH/tb_filter_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2020.2
Time resolution is 1 ps
open_wave_config D:/Projet_instrum_MHAH/tb_filter_behav.wcfg
WARNING: Simulation object /tb_division/division1/frequency was not found in the design.
WARNING: Simulation object /tb_division/division1/resultat was not found in the design.
WARNING: Simulation object /tb_division/division1/etatp was not found in the design.
WARNING: Simulation object /tb_division/division1/etatf was not found in the design.
source tb_compt_period.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_compt_period_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:12 . Memory (MB): peak = 1110.664 ; gain = 0.000
restart
INFO: [Simtcl 6-17] Simulation restarted
run 100ms
run: Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1110.664 ; gain = 0.000
restart
INFO: [Simtcl 6-17] Simulation restarted
run 10ms
save_wave_config {D:/Projet_instrum_MHAH/tb_filter_behav.wcfg}
close_sim
INFO: [Simtcl 6-16] Simulation closed
close_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 1110.664 ; gain = 0.000
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2020.2/data/xsim/xsim.ini' copied to run dir:'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_compt_period' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj tb_compt_period_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/compt_period.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'compt_period'
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xelab -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_compt_period_behav xil_defaultlib.tb_compt_period -log elaborate.log"
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_compt_period_behav xil_defaultlib.tb_compt_period -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling architecture behavioral of entity xil_defaultlib.compt_period [compt_period_default]
Compiling architecture behavioral of entity xil_defaultlib.tb_compt_period
Built simulation snapshot tb_compt_period_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_compt_period_behav -key {Behavioral:sim_1:Functional:tb_compt_period} -tclbatch {tb_compt_period.tcl} -view {D:/Projet_instrum_MHAH/tb_filter_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2020.2
Time resolution is 1 ps
open_wave_config D:/Projet_instrum_MHAH/tb_filter_behav.wcfg
source tb_compt_period.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_compt_period_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:12 . Memory (MB): peak = 1110.664 ; gain = 0.000
run 2ms
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2020.2/data/xsim/xsim.ini' copied to run dir:'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_compt_period' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj tb_compt_period_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/compt_period.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'compt_period'
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xelab -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_compt_period_behav xil_defaultlib.tb_compt_period -log elaborate.log"
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_compt_period_behav xil_defaultlib.tb_compt_period -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling architecture behavioral of entity xil_defaultlib.compt_period [compt_period_default]
Compiling architecture behavioral of entity xil_defaultlib.tb_compt_period
Built simulation snapshot tb_compt_period_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_compt_period_behav -key {Behavioral:sim_1:Functional:tb_compt_period} -tclbatch {tb_compt_period.tcl} -view {D:/Projet_instrum_MHAH/tb_filter_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2020.2
Time resolution is 1 ps
open_wave_config D:/Projet_instrum_MHAH/tb_filter_behav.wcfg
source tb_compt_period.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_compt_period_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:10 . Memory (MB): peak = 1110.664 ; gain = 0.000
run 4ms
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2020.2/data/xsim/xsim.ini' copied to run dir:'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_compt_period' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj tb_compt_period_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/compt_period.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'compt_period'
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xelab -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_compt_period_behav xil_defaultlib.tb_compt_period -log elaborate.log"
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_compt_period_behav xil_defaultlib.tb_compt_period -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling architecture behavioral of entity xil_defaultlib.compt_period [compt_period_default]
Compiling architecture behavioral of entity xil_defaultlib.tb_compt_period
Built simulation snapshot tb_compt_period_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_compt_period_behav -key {Behavioral:sim_1:Functional:tb_compt_period} -tclbatch {tb_compt_period.tcl} -view {D:/Projet_instrum_MHAH/tb_filter_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2020.2
Time resolution is 1 ps
open_wave_config D:/Projet_instrum_MHAH/tb_filter_behav.wcfg
source tb_compt_period.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_compt_period_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:10 . Memory (MB): peak = 1110.664 ; gain = 0.000
run 3ms
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2020.2/data/xsim/xsim.ini' copied to run dir:'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_compt_period' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj tb_compt_period_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/compt_period.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'compt_period'
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xelab -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_compt_period_behav xil_defaultlib.tb_compt_period -log elaborate.log"
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_compt_period_behav xil_defaultlib.tb_compt_period -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling architecture behavioral of entity xil_defaultlib.compt_period [compt_period_default]
Compiling architecture behavioral of entity xil_defaultlib.tb_compt_period
Built simulation snapshot tb_compt_period_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_compt_period_behav -key {Behavioral:sim_1:Functional:tb_compt_period} -tclbatch {tb_compt_period.tcl} -view {D:/Projet_instrum_MHAH/tb_filter_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2020.2
Time resolution is 1 ps
open_wave_config D:/Projet_instrum_MHAH/tb_filter_behav.wcfg
source tb_compt_period.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_compt_period_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:12 . Memory (MB): peak = 1110.664 ; gain = 0.000
run 4 ms
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2020.2/data/xsim/xsim.ini' copied to run dir:'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_compt_period' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj tb_compt_period_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/compt_period.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'compt_period'
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xelab -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_compt_period_behav xil_defaultlib.tb_compt_period -log elaborate.log"
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_compt_period_behav xil_defaultlib.tb_compt_period -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling architecture behavioral of entity xil_defaultlib.compt_period [compt_period_default]
Compiling architecture behavioral of entity xil_defaultlib.tb_compt_period
Built simulation snapshot tb_compt_period_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_compt_period_behav -key {Behavioral:sim_1:Functional:tb_compt_period} -tclbatch {tb_compt_period.tcl} -view {D:/Projet_instrum_MHAH/tb_filter_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2020.2
Time resolution is 1 ps
open_wave_config D:/Projet_instrum_MHAH/tb_filter_behav.wcfg
source tb_compt_period.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_compt_period_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:11 . Memory (MB): peak = 1110.664 ; gain = 0.000
run 4 ms
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2020.2/data/xsim/xsim.ini' copied to run dir:'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_compt_period' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj tb_compt_period_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/compt_period.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'compt_period'
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xelab -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_compt_period_behav xil_defaultlib.tb_compt_period -log elaborate.log"
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_compt_period_behav xil_defaultlib.tb_compt_period -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling architecture behavioral of entity xil_defaultlib.compt_period [compt_period_default]
Compiling architecture behavioral of entity xil_defaultlib.tb_compt_period
Built simulation snapshot tb_compt_period_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_compt_period_behav -key {Behavioral:sim_1:Functional:tb_compt_period} -tclbatch {tb_compt_period.tcl} -view {D:/Projet_instrum_MHAH/tb_filter_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2020.2
Time resolution is 1 ps
open_wave_config D:/Projet_instrum_MHAH/tb_filter_behav.wcfg
source tb_compt_period.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_compt_period_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:10 . Memory (MB): peak = 1898.582 ; gain = 0.000
run 4 ms
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2020.2/data/xsim/xsim.ini' copied to run dir:'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_compt_period' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj tb_compt_period_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/compt_period.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'compt_period'
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xelab -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_compt_period_behav xil_defaultlib.tb_compt_period -log elaborate.log"
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_compt_period_behav xil_defaultlib.tb_compt_period -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling architecture behavioral of entity xil_defaultlib.compt_period [compt_period_default]
Compiling architecture behavioral of entity xil_defaultlib.tb_compt_period
Built simulation snapshot tb_compt_period_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_compt_period_behav -key {Behavioral:sim_1:Functional:tb_compt_period} -tclbatch {tb_compt_period.tcl} -view {D:/Projet_instrum_MHAH/tb_filter_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2020.2
Time resolution is 1 ps
open_wave_config D:/Projet_instrum_MHAH/tb_filter_behav.wcfg
source tb_compt_period.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_compt_period_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:11 . Memory (MB): peak = 1898.582 ; gain = 0.000
run 4 ms
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2020.2/data/xsim/xsim.ini' copied to run dir:'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_compt_period' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj tb_compt_period_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/compt_period.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'compt_period'
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xelab -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_compt_period_behav xil_defaultlib.tb_compt_period -log elaborate.log"
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_compt_period_behav xil_defaultlib.tb_compt_period -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling architecture behavioral of entity xil_defaultlib.compt_period [compt_period_default]
Compiling architecture behavioral of entity xil_defaultlib.tb_compt_period
Built simulation snapshot tb_compt_period_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_compt_period_behav -key {Behavioral:sim_1:Functional:tb_compt_period} -tclbatch {tb_compt_period.tcl} -view {D:/Projet_instrum_MHAH/tb_filter_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2020.2
Time resolution is 1 ps
open_wave_config D:/Projet_instrum_MHAH/tb_filter_behav.wcfg
source tb_compt_period.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_compt_period_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:12 . Memory (MB): peak = 1898.582 ; gain = 0.000
run 4ms
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2020.2/data/xsim/xsim.ini' copied to run dir:'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_compt_period' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj tb_compt_period_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/compt_period.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'compt_period'
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xelab -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_compt_period_behav xil_defaultlib.tb_compt_period -log elaborate.log"
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_compt_period_behav xil_defaultlib.tb_compt_period -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling architecture behavioral of entity xil_defaultlib.compt_period [compt_period_default]
Compiling architecture behavioral of entity xil_defaultlib.tb_compt_period
Built simulation snapshot tb_compt_period_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_compt_period_behav -key {Behavioral:sim_1:Functional:tb_compt_period} -tclbatch {tb_compt_period.tcl} -view {D:/Projet_instrum_MHAH/tb_filter_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2020.2
Time resolution is 1 ps
open_wave_config D:/Projet_instrum_MHAH/tb_filter_behav.wcfg
source tb_compt_period.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_compt_period_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:12 . Memory (MB): peak = 1898.582 ; gain = 0.000
run 4ms
save_wave_config {D:/Projet_instrum_MHAH/tb_filter_behav.wcfg}
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2020.2/data/xsim/xsim.ini' copied to run dir:'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_compt_period' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj tb_compt_period_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/compt_period.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'compt_period'
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xelab -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_compt_period_behav xil_defaultlib.tb_compt_period -log elaborate.log"
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_compt_period_behav xil_defaultlib.tb_compt_period -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling architecture behavioral of entity xil_defaultlib.compt_period [compt_period_default]
Compiling architecture behavioral of entity xil_defaultlib.tb_compt_period
Built simulation snapshot tb_compt_period_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_compt_period_behav -key {Behavioral:sim_1:Functional:tb_compt_period} -tclbatch {tb_compt_period.tcl} -view {D:/Projet_instrum_MHAH/tb_filter_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2020.2
Time resolution is 1 ps
open_wave_config D:/Projet_instrum_MHAH/tb_filter_behav.wcfg
source tb_compt_period.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_compt_period_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 1898.582 ; gain = 0.000
run 4ms
save_wave_config {D:/Projet_instrum_MHAH/tb_filter_behav.wcfg}
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2020.2/data/xsim/xsim.ini' copied to run dir:'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_compt_period' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj tb_compt_period_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/compt_period.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'compt_period'
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xelab -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_compt_period_behav xil_defaultlib.tb_compt_period -log elaborate.log"
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_compt_period_behav xil_defaultlib.tb_compt_period -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling architecture behavioral of entity xil_defaultlib.compt_period [compt_period_default]
Compiling architecture behavioral of entity xil_defaultlib.tb_compt_period
Built simulation snapshot tb_compt_period_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_compt_period_behav -key {Behavioral:sim_1:Functional:tb_compt_period} -tclbatch {tb_compt_period.tcl} -view {D:/Projet_instrum_MHAH/tb_filter_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2020.2
Time resolution is 1 ps
open_wave_config D:/Projet_instrum_MHAH/tb_filter_behav.wcfg
source tb_compt_period.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_compt_period_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:11 . Memory (MB): peak = 1898.582 ; gain = 0.000
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2020.2/data/xsim/xsim.ini' copied to run dir:'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_compt_period' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj tb_compt_period_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/compt_period.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'compt_period'
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xelab -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_compt_period_behav xil_defaultlib.tb_compt_period -log elaborate.log"
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_compt_period_behav xil_defaultlib.tb_compt_period -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling architecture behavioral of entity xil_defaultlib.compt_period [compt_period_default]
Compiling architecture behavioral of entity xil_defaultlib.tb_compt_period
Built simulation snapshot tb_compt_period_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_compt_period_behav -key {Behavioral:sim_1:Functional:tb_compt_period} -tclbatch {tb_compt_period.tcl} -view {D:/Projet_instrum_MHAH/tb_filter_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2020.2
Time resolution is 1 ps
open_wave_config D:/Projet_instrum_MHAH/tb_filter_behav.wcfg
source tb_compt_period.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_compt_period_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:10 . Memory (MB): peak = 1898.582 ; gain = 0.000
restart
INFO: [Simtcl 6-17] Simulation restarted
run 4ms
save_wave_config {D:/Projet_instrum_MHAH/tb_filter_behav.wcfg}
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2020.2/data/xsim/xsim.ini' copied to run dir:'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_compt_period' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj tb_compt_period_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/compt_period.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'compt_period'
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xelab -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_compt_period_behav xil_defaultlib.tb_compt_period -log elaborate.log"
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_compt_period_behav xil_defaultlib.tb_compt_period -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling architecture behavioral of entity xil_defaultlib.compt_period [compt_period_default]
Compiling architecture behavioral of entity xil_defaultlib.tb_compt_period
Built simulation snapshot tb_compt_period_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_compt_period_behav -key {Behavioral:sim_1:Functional:tb_compt_period} -tclbatch {tb_compt_period.tcl} -view {D:/Projet_instrum_MHAH/tb_filter_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2020.2
Time resolution is 1 ps
open_wave_config D:/Projet_instrum_MHAH/tb_filter_behav.wcfg
source tb_compt_period.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_compt_period_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:11 . Memory (MB): peak = 1898.582 ; gain = 0.000
run 3ms
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2020.2/data/xsim/xsim.ini' copied to run dir:'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_compt_period' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj tb_compt_period_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/compt_period.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'compt_period'
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xelab -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_compt_period_behav xil_defaultlib.tb_compt_period -log elaborate.log"
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto 78de84b91bcf4d27b7efd64ed4731d67 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot tb_compt_period_behav xil_defaultlib.tb_compt_period -log elaborate.log
Using 2 slave threads.
Starting static elaboration
ERROR: [VRFC 10-664] expression has 1 elements ; expected 20 [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/compt_period.vhd:87]
ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit tb_compt_period in library work failed.
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
INFO: [USF-XSim-99] Step results log file:'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim/elaborate.log'
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim/elaborate.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:08 . Memory (MB): peak = 1898.582 ; gain = 0.000
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2020.2/data/xsim/xsim.ini' copied to run dir:'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_compt_period' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj tb_compt_period_vhdl.prj"