In this chapter we will experiment with binary operations in VHDL, using the switches for input and LEDs for output.
This chapter is much easier than the last one, as you will only be changing one or two lines in your existing design, but there are a few short challenges with a lot more thinking and problem solving.
On finishing this chapter you should have re-familiarized yourself with the binary operators, learnt a bit about the VHDL STD_LOGIC data type, combined one or more signals to generate an output and then tested the design in hardware.
During this process you will be building familiarity with the design tools and you might even have a small insight into the fundamentals of digital logic.
As previously mentioned, an STD_LOGIC signal is analogous to a wire carrying a single bit of data.
Confusingly, it is a lot more. Each STD_LOGIC signal can take on one of 9 different values at any one time!
However, for most designs, only three are used:
| Value | Meaning |
|---|---|
'0' |
Logical 'Low' |
'1' |
Logical 'High' |
'Z' |
High impedance (only used on bidirectional signals) |
It is important to note that these values are not numbers-- in the source code they are enclosed in a single quote (').
The 'Z' state does not actually happen inside the FPGA these days. Apart from on the input/output pins, no tri-state logic exists within an FPGA-- it is all mapped to multiplexers by the EDA tools. Because of this, using tri-state logic for internal buses is not recommended as it makes the synthesis software work much harder.
The other possible values are "Weak high" ('H'), "Weak low" ('L') which are used mostly in interfacing, and the "Uninitialized" ('U'), "Weak Uninitialized" ('W'), "Forcing unknown" ('X'), and "don’t care" ('-') that are only seen when simulating a design.
In most situations, you will encounter four Boolean operations in VHDL:
| Operation | Result |
|---|---|
NOT x |
Result is '0' when x is '1', otherwise '1' |
x AND y |
Result is '1' when both x and y are '1', otherwise '0' |
x OR y |
Result is '1' when either x is '1' and/or y is '1', otherwise '0' |
x XOR y |
Result is '1' when only one of either x or y is '1', otherwise '0' |
Three other less common binary operations are supported:
| Operation | Equivalent expression |
|---|---|
x NAND y |
NOT(x AND y) |
x NOR y |
NOT(x OR y) |
x NXOR y |
NOT(x XOR y) |
Using these operators is pretty simple. Open up the project from Chapter 6 and make the changes to lines 13 and 14 as follows:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Switches_LEDs is
Port ( switch_0 : in STD_LOGIC;
switch_1 : in STD_LOGIC;
LED_0 : out STD_LOGIC;
LED_1 : out STD_LOGIC);
end Switches_LEDs;
architecture Behavioral of Switches_LEDs is
begin
LED_0 <= switch_0 AND switch_1;
LED_1 <= switch_0 OR switch_1;
end Behavioral;Using the instructions in Chapter 6, you will now be able to build this project and download it to your FPGA.
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Compare ''switch_0 NAND switch_1'' with ''NOT(switch_0 AND switch_1)''
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Compare ''switch_0 NAND switch_1'' with ''NOT(switch_0) OR NOT(switch_1)''
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Compare ''NOT(switch_0)'' with ''switch_0 XOR switch_1'', when switch 1 is on.
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Can you make a design that will only light an LED when switch 0 is off and switch 1 is on?
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Can you make the AND operator out of only OR and NOT operations?
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Can you make the OR operator out of only AND and NOT operations?
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Can you make the OR operator out of only NOR operations? (hint, you can use the input values more than once)
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Experiment with XOR operator. Can you make an equivalent function out of only AND, OR and NOT? Can you make either an AND or OR using only the XOR operations?
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Are any of the Boolean operations "fundamental" (meaning that all other operations can be built from them)? This ability to implement any logic function using a set of generic components is core to how FPGAs implement your designs.
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For the operations that are not fundamental, what special ingredient are they missing?