One of the other resources on the Spartan 3E FPGA is the Digital Clock Manager. These are very handy!
DCMs receive an incoming clock and can do the following and more:
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Generate a faster or slower clock signal using an input clock as a reference
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Generate signals with a known phase shift (e.g., 90, 180 or 270 degrees out of phase)
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Correct clock duty cycles, ensuring that the high and low times are 50%
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Phase shift the internal FPGA clock signals to compensate for internal clock distribution delays
DCMs can also be cascaded, allowing multiple clocks to be used. For example, one external 50MHz clock can be used to generate 100MHz controlling memory and 25MHz for the VGA pixel clock.
Because of this flexibility they are quite complex to use. I find using the CORE Generator is the best way to configure a DCM.
Pick any project you like, and add a "New Source", using the "IP (CORE Generator…)" option to create a component "my_dcm":
Once again choose the "Only IP compatible with chosen part" option, then drill down to "Single DCM_SP":
Click "Next" then "Finish" to start the CORE Generator.
You will then be presented with this dialog box:
Just click "OK" to open the Clocking Wizard’s General Setup dialogue box:
Here you can choose what signals you will use and set the input clock frequency. The most common output I use is the CLKFX (which is the synthesized output frequency). You may want to untick the RST (reset) signal if this is the only clock for the entire project:
The next screen allows you to choose what clock buffers are being used. For most projects you will use "Global Buffers" - being global the clock signal is available to all logic on the FPGA:
The next screen is the interesting one - it’s where you get to set the output frequency. Input the desired frequency and press "Calculate":
You will now get the summary screen, where you can click "Finish":
Once generated, you will be able to use the instantiation templates to add a "my_dcm" component to your project.