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The complete Papilio One constraint file

 ##################################################################################
 ## BPC3003_2.03+.ucf
 ##
 ## Author: Jack Gassett
 ##
 ## Details: http://gadgetforge.gadgetfactory.net/gf/project/butterfly_one/
 ##
 ## Contains assignment and iostandard information for
 ## all used pins as well as timing and area constraints for Papilio One 2.03 and higher boards. Papilio One boards started using 32Mhz oscillators at version 2.02 and above.
 ##
 ##################################################################################

 # Crystal Clock - use 32MHz onboard oscillator
 NET "clk" LOC = "P89" | IOSTANDARD = LVCMOS25 | PERIOD = 31.25ns ;

 # Wing1 Column A
 NET "W1A<0>" LOC = "P18" ;	# LogicStart 7Seg anode(0)
 NET "W1A<1>" LOC = "P23" ;  	# LogicStart 7seg Decimal Point
 NET "W1A<2>" LOC = "P26" ;  	# LogicStart 7Seg anode(1)
 NET "W1A<3>" LOC = "P33" ;  	# LogicStart 7seg segment E
 NET "W1A<4>" LOC = "P35" ;  	# LogicStart 7seg segment F
 NET "W1A<5>" LOC = "P40" ;  	# LogicStart 7seg segment C
 NET "W1A<6>" LOC = "P53" ;  	# LogicStart 7seg segment D
 NET "W1A<7>" LOC = "P57" ;  	# LogicStart 7seg segment A
 NET "W1A<8>" LOC = "P60" ;  	# LogicStart 7seg anode(2)
 NET "W1A<9>" LOC = "P62" ;     # LogicStart 7seg segment G
 NET "W1A<10>" LOC = "P65" ;	# LogicStart 7seg segment B
 NET "W1A<11>" LOC = "P67" ;	# LogicStart 7seg anode(3)
 NET "W1A<12>" LOC = "P70" ;	# LogicStart A2D SPI_CS
 NET "W1A<13>" LOC = "P79" ;	# LogicStart A2D SPI_DOUT
 NET "W1A<14>" LOC = "P84" ;	# LogicStart A2D SPI_DIN
 NET "W1A<15>" LOC = "P86" ;	# LogicStart A2D SPI_SCLK

 # Wing1 Column B
 NET "W1B<0>" LOC = "P85" ;	# LogicStart vsync
 NET "W1B<1>" LOC = "P83" ;	# LogicStart hsync
 NET "W1B<2>" LOC = "P78" ;	# LogicStart blue1
 NET "W1B<3>" LOC = "P71" ;	# LogicStart blue2
 NET "W1B<4>" LOC = "P68" ;	# LogicStart green0
 NET "W1B<5>" LOC = "P66" ;	# LogicStart green1
 NET "W1B<6>" LOC = "P63" ;	# LogicStart green2
 NET "W1B<7>" LOC = "P61" ;	# LogicStart red0
 NET "W1B<8>" LOC = "P58" ;	# LogicStart red1
 NET "W1B<9>" LOC = "P54" ;	# LogicStart red2
 NET "W1B<10>" LOC = "P41" ;	# LogicStart audio
 NET "W1B<11>" LOC = "P36" ;	# LogicStart joystick right
 NET "W1B<12>" LOC = "P34" ;	# LogicStart joystick left
 NET "W1B<13>" LOC = "P32" ;	# LogicStart joystick down
 NET "W1B<14>" LOC = "P25" ;	# LogicStart Joystick up
 NET "W1B<15>" LOC = "P22" ;	# LogicStart Joystick Select

 # Wing2 Column C
 NET "W2C<0>" LOC = "P91" ;	 # LogicStart Switch 7
 NET "W2C<1>" LOC = "P92" ;  	 # LogicStart Switch 6
 NET "W2C<2>" LOC = "P94" ;  	 # LogicStart Switch 5
 NET "W2C<3>" LOC = "P95" ;  	 # LogicStart Switch 4
 NET "W2C<4>" LOC = "P98" ;  	 # LogicStart Switch 3
 NET "W2C<5>" LOC = "P2" ;  	 # LogicStart Switch 2
 NET "W2C<6>" LOC = "P3" ;  	 # LogicStart Switch 1
 NET "W2C<7>" LOC = "P4" ;  	 # LogicStart Switch 0
 NET "W2C<8>" LOC = "P5" ;  	 # LogicStart LED 7
 NET "W2C<9>" LOC = "P9" ;       # LogicStart LED 6
 NET "W2C<10>" LOC = "P10" ;	 # LogicStart LED 5
 NET "W2C<11>" LOC = "P11" ;	 # LogicStart LED 4
 NET "W2C<12>" LOC = "P12" ;	 # LogicStart LED 3
 NET "W2C<13>" LOC = "P15" ;	 # LogicStart LED 2
 NET "W2C<14>" LOC = "P16" ;	 # LogicStart LED 1
 NET "W2C<15>" LOC = "P17" ;	 # LogicStart LED 0

 ## RS232
 NET "rx"  LOC = "P88" | IOSTANDARD = LVCMOS25 ;
 NET "tx"  LOC = "P90" | IOSTANDARD = LVCMOS25 | DRIVE = 4 | SLEW = SLOW ;

The complete Basys2 constraint file

 # This file is a general .ucf for Basys2 rev C board
 # To use it in a project:
 # - remove or comment the lines corresponding to unused pins
 # - rename the used signals according to the project

 # clock pin for Basys2 Board
 NET "mclk" LOC = "B8"; # Bank = 0, Signal name = MCLK
 NET "uclk" LOC = "M6"; # Bank = 2, Signal name = UCLK
 NET "mclk" CLOCK_DEDICATED_ROUTE = FALSE;
 NET "uclk" CLOCK_DEDICATED_ROUTE = FALSE;

 # Pin assignment for EppCtl
 # Connected to Basys2 onBoard USB controller
 NET "EppAstb" LOC = "F2"; # Bank = 3
 NET "EppDstb" LOC = "F1"; # Bank = 3
 NET "EppWR"       LOC = "C2"; # Bank = 3

 NET "EppWait" LOC = "D2"; # Bank = 3


 NET "EppDB<0>" LOC = "N2"; # Bank = 2
 NET "EppDB<1>" LOC = "M2"; # Bank = 2
 NET "EppDB<2>" LOC = "M1"; # Bank = 3
 NET "EppDB<3>" LOC = "L1"; # Bank = 3
 NET "EppDB<4>" LOC = "L2"; # Bank = 3
 NET "EppDB<5>" LOC = "H2"; # Bank = 3
 NET "EppDB<6>" LOC = "H1"; # Bank = 3
 NET "EppDB<7>" LOC = "H3"; # Bank = 3


 # Pin assignment for DispCtl
 # Connected to Basys2 onBoard 7seg display
 NET "seg<0>" LOC = "L14"; # Bank = 1, Signal name = CA
 NET "seg<1>" LOC = "H12"; # Bank = 1, Signal name = CB
 NET "seg<2>" LOC = "N14"; # Bank = 1, Signal name = CC
 NET "seg<3>" LOC = "N11"; # Bank = 2, Signal name = CD
 NET "seg<4>" LOC = "P12"; # Bank = 2, Signal name = CE
 NET "seg<5>" LOC = "L13"; # Bank = 1, Signal name = CF
 NET "seg<6>" LOC = "M12"; # Bank = 1, Signal name = CG
 NET "dp" LOC = "N13"; # Bank = 1, Signal name = DP

 NET "an<3>" LOC = "K14"; # Bank = 1, Signal name = AN3
 NET "an<2>" LOC = "M13"; # Bank = 1, Signal name = AN2
 NET "an<1>" LOC = "J12"; # Bank = 1, Signal name = AN1
 NET "an<0>" LOC = "F12"; # Bank = 1, Signal name = AN0

 # Pin assignment for LEDs
 NET "Led<7>" LOC = "G1" ; # Bank = 3, Signal name = LD7
 NET "Led<6>" LOC = "P4" ; # Bank = 2, Signal name = LD6
 NET "Led<5>" LOC = "N4" ;  # Bank = 2, Signal name = LD5
 NET "Led<4>" LOC = "N5" ;  # Bank = 2, Signal name = LD4
 NET "Led<3>" LOC = "P6" ; # Bank = 2, Signal name = LD3
 NET "Led<2>" LOC = "P7" ; # Bank = 3, Signal name = LD2
 NET "Led<1>" LOC = "M11" ; # Bank = 2, Signal name = LD1
 NET "Led<0>" LOC = "M5" ;  # Bank = 2, Signal name = LD0

 # Pin assignment for SWs
 NET "sw<7>" LOC = "N3";  # Bank = 2, Signal name = SW7
 NET "sw<6>" LOC = "E2";  # Bank = 3, Signal name = SW6
 NET "sw<5>" LOC = "F3";  # Bank = 3, Signal name = SW5
 NET "sw<4>" LOC = "G3";  # Bank = 3, Signal name = SW4
 NET "sw<3>" LOC = "B4";  # Bank = 3, Signal name = SW3
 NET "sw<2>" LOC = "K3";  # Bank = 3, Signal name = SW2
 NET "sw<1>" LOC = "L3";  # Bank = 3, Signal name = SW1
 NET "sw<0>" LOC = "P11";  # Bank = 2, Signal name = SW0

 NET "btn<3>" LOC = "A7";  # Bank = 1, Signal name = BTN3
 NET "btn<2>" LOC = "M4";  # Bank = 0, Signal name = BTN2
 NET "btn<1>" LOC = "C11"; # Bank = 2, Signal name = BTN1
 NET "btn<0>" LOC = "G12"; # Bank = 0, Signal name = BTN0

 # Loop back/demo signals
 # Pin assignment for PS2
 NET "PS2C"    LOC = "B1"   | DRIVE = 2  | PULLUP ; # Bank = 3, Signal name = PS2C
 NET "PS2D"    LOC = "C3"   | DRIVE = 2  | PULLUP ; # Bank = 3, Signal name = PS2D

 # Pin assignment for VGA
 NET "HSYNC"   LOC = "J14"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = HSYNC
 NET "VSYNC"   LOC = "K13"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = VSYNC

 NET "OutRed<2>"  LOC = "F13"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = RED2
 NET "OutRed<1>"  LOC = "D13"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = RED1
 NET "OutRed<0>"  LOC = "C14"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = RED0
 NET "OutGreen<2>"  LOC = "G14"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = GRN2
 NET "OutGreen<1>"  LOC = "G13"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = GRN1
 NET "OutGreen<0>"  LOC = "F14"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = GRN0
 NET "OutBlue<2>"  LOC = "J13"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = BLU2
 NET "OutBlue<1>"  LOC = "H13"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = BLU1

 # Loop Back only tested signals
 NET "PIO<72>" LOC = "B2"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = JA1
 NET "PIO<73>" LOC = "A3"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = JA2
 NET "PIO<74>" LOC = "J3"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = JA3
 NET "PIO<75>" LOC = "B5"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = JA4

 NET "PIO<76>" LOC = "C6"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = JB1
 NET "PIO<77>" LOC = "B6"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = JB2
 NET "PIO<78>" LOC = "C5"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = JB3
 NET "PIO<79>" LOC = "B7"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = JB4

 NET "PIO<80>" LOC = "A9"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = JC1
 NET "PIO<81>" LOC = "B9"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = JC2
 NET "PIO<82>" LOC = "A10" | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = JC3
 NET "PIO<83>" LOC = "C9"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = JC4

 NET "PIO<84>" LOC = "C12"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = JD1
 NET "PIO<85>" LOC = "A13"  | DRIVE = 2  | PULLUP ; # Bank = 2, Signal name = JD2
 NET "PIO<86>" LOC = "C13"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = JD3
 NET "PIO<87>" LOC = "D12"  | DRIVE = 2  | PULLUP ; # Bank = 2, Signal name = JD4