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camera_init_top.vhd
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camera_init_top.vhd
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`timescale 1ns / 1ps
// ÉãÏñÍ·³õÊŒ»¯
module camera_init_top(
input clk, // 25MHzʱÖÓ
input reset, // žŽÎ»ÐźÅ
// ÒÔÏÂÊÇÓëÉãÏñÍ·ÏàÁ¬µÄ¹ÜœÅ
output sio_c,
inout sio_d,
output pwdn,
output ret,
output xclk
);
// pwdnžßµçÆœÓÐЧ retµÍµçÆœÓÐЧ
assign pwdn = 0;
assign ret = 1;
// sio_džß×è̬
pullup up (sio_d);
// ž³žøxclkʱÖÓÐźÅ
assign xclk = clk;
wire cfg_ok, sccb_ok;
wire [15: 0] data_sent;
// ʵÀý»¯ÅäÖÃÐŽÈëÄ£¿é
camera_reg_cfg reg_cfg(
.clk(clk),
.reset(reset),
.data_out(data_sent),
.cfg_ok(cfg_ok),
.sccb_ok(sccb_ok)
);
// ʵÀý»¯sccb·¢ËÍÄ£¿é
camera_sccb_sender sccb_sender(
.clk(clk),
.reset(reset),
.sio_c(sio_c),
.sio_d(sio_d),
.cfg_ok(cfg_ok),
.sccb_ok(sccb_ok),
.reg_addr(data_sent[15:8]),
.value(data_sent[7:0])
);
endmodule