diff --git a/src/vhdl/mega65r3.vhdl b/src/vhdl/mega65r3.vhdl
index 2648a689c..e53d6725b 100644
--- a/src/vhdl/mega65r3.vhdl
+++ b/src/vhdl/mega65r3.vhdl
@@ -123,7 +123,7 @@ entity container is
          iec_atn_en_n : out std_logic;
          iec_data_en : out std_logic;
          iec_clk_en : out std_logic;
-         iec_srq_en_n : out std_logic;
+         iec_srq_en : out std_logic;
          iec_clk_o : out std_logic := '0';
          iec_data_o : out std_logic := '0';
          iec_srq_o : out std_logic := '0';
@@ -1194,7 +1194,7 @@ begin
       -- Finally, because we have the output value of 0 hard-wired
       -- on the output drivers, we need only gate the EN line.
       -- But we only do this if the DDR is set to output
-      iec_srq_en_n <= iec_srq_en_n_drive;
+      iec_srq_en <= not iec_srq_en_n_drive;
       iec_clk_en <= not iec_clk_en_n_drive;
       iec_data_en <= not iec_data_en_n_drive;
 
diff --git a/src/vhdl/mega65r3.xdc b/src/vhdl/mega65r3.xdc
index f228c5d3d..38486cf64 100644
--- a/src/vhdl/mega65r3.xdc
+++ b/src/vhdl/mega65r3.xdc
@@ -132,7 +132,7 @@ set_property -dict {PACKAGE_PIN Y19  IOSTANDARD LVCMOS33} [get_ports iec_clk_o]
 set_property -dict {PACKAGE_PIN Y18  IOSTANDARD LVCMOS33 PULLUP true} [get_ports iec_clk_i]
 set_property -dict {PACKAGE_PIN U20  IOSTANDARD LVCMOS33} [get_ports iec_srq_o]
 set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS33} [get_ports iec_srq_i]
-set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS33} [get_ports iec_srq_en_n]
+set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS33} [get_ports iec_srq_en]
 
 # C64 Cartridge port control lines
 # *_dir=1 means FPGA->Port, =0 means Port->FPGA