-
Notifications
You must be signed in to change notification settings - Fork 1
/
Copy pathStart_V3.LST
executable file
·2664 lines (2482 loc) · 186 KB
/
Start_V3.LST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
A166 MACRO ASSEMBLER START_V3 03/15/2019 15:27:40 PAGE 1
MACRO ASSEMBLER A166 V5.33
OBJECT MODULE PLACED IN Start_V3.OBJ
ASSEMBLER INVOKED BY: F:\Softeware\Fury\Keil\C166\BIN\A166.EXE Start_V3.A66 MODV2 SEGMENTED MODV2 SET(SMALL) DEBUG EP
LOC OBJ LINE SOURCE
1 $MODV2 ; Define C166v2 core mode
2 ;
3 ;------------------------------------------------------------------------------
4 ; This file is part of the C166 Compiler package
5 ; Copyright KEIL ELEKTRONIK GmbH 1993 - 2008
6 ; Version 5.09
7 ; *** <<< Use Configuration Wizard in Context Menu >>> ***
8 ;
9 ;------------------------------------------------------------------------------
10 ; START_V3.A66: This code is executed after processor reset and provides the
11 ; startup sequence for the Infineon XC2xxx and XE16x devices.
12 ;
13 ; You may add this file to a uVision3 project - in this case it will be
14 ; automatically assembled and linked.
15 ;
16 ; For manual translation of this file use A166 with the following invocation:
17 ;
18 ; A166 START_V3.A66 SET (model)
19 ;
20 ; model determines the memory model and can be one of the following:
21 ; TINY, SMALL, COMPACT, HCOMPACT, MEDIUM, LARGE, HLARGE, XLARGE
22 ;
23 ; Example: A166 START_V2.A66 SET (SMALL)
24 ;
25 ; For manual linkage of the modified START_V3.OBJ file to your application
26 ; use the following L166 invocation:
27 ;
28 ; L166 your object file list, START_V3.OBJ controls
29 ;
30 ;------------------------------------------------------------------------------
31 ; Setup model-dependend Assembler controls
32 $CASE
33 $IF NOT TINY
34 $SEGMENTED
35 $ENDIF
36
37 ; Settings for ADDRSEL calculation (do not change!)
0400 38 KB EQU 0x400 ; define KB constant for CS _SIZE calculation
00100000 39 MB EQU 0x400*KB ; define MB as 1024KB
40 ;------------------------------------------------------------------------------
41 ;
42 ; <h>Definitions for System and User Stack
43 ; ========================================
44 ;
45 ; <o>STKSZ: Maximum System Stack Size selection <0x0-0x1000:0x2>
46 ; <i> Defines the system stack space that is used by CALL/RET and PUSH/POP
47 ; <i> instructions. The system stack space must be adjusted according the actual
48 ; <i> requirements of the application.
0200 49 SSTSZ EQU 0x200
50 ; <o> USTSZ: User Stack Size Definition <0x0-0x4000:0x2>
51 ; <i> Defines the user stack space available for automatics. This stack space is
52 ; <i> accessed by R0. The user stack space must be adjusted according the actual
53 ; <i> requirements of the application.
0200 54 USTSZ EQU 0x200 ; set User Stack Size to 200H Bytes.
55 ;
56 ; <o> UST1SZ: User Stack Size for local register bank 1 <0x0-0x4000:0x2>
57 ; <i> Defines the user stack space available for the interrupt functions that are
58 ; <i> assigned to the local register bank 1. Since the compiler cannot copy the R0
A166 MACRO ASSEMBLER START_V3 03/15/2019 15:27:40 PAGE 2
59 ; <i> value to local register banks, the user stack must be assign separately.
60 ; <i> If you have no interrupt functions assigned to local register bank 1, you may
61 ; <i> set UST1SZ to 0.
0020 62 UST1SZ EQU 0x20 ; set User Stack Size to 20H Bytes.
63 ;
64 ; <o> UST2SZ: User Stack Size for local register bank 2 <0x0-0x4000:0x2>
65 ; <i> Defines the user stack space available for the interrupt functions that are
66 ; <i> assigned to the local register bank 1. Since the compiler cannot copy the R0
67 ; <i> value to local register banks, the user stack must be assign separately.
68 ; If you have no interrupt functions assigned to local register bank 2, you may
69 ; set UST2SZ to 0.
0020 70 UST2SZ EQU 0x20 ; set User Stack Size to 20H Bytes.
71 ;
72 ; </h>
73 ; <h>Definitions for Startup Code
74 ; ===============================
75 ;
76 ; <q> CLR_MEMORY: Enable/Disable Memory Zero Initialization of RAM area
77 ; --- <i> Set CLR_MEMORY = 0 to disable memory zero initialization
78 $SET (CLR_MEMORY = 1)
79 ;
80 ; <q> INIT_VARS: Enable/Disable Variable Initialization
81 ; --- <i> Set INIT_VARS = 0 to disable variable initialization
82 $SET (INIT_VARS = 1)
83 ;
84 ; <q> DPPUSE: Allow re-assign of DPP registers
85 ; --- <i> Set DPPUSE = 0 to reduce the code size of the startup code, if you
86 ; <i> are not using the L166 DPPUSE directive.
87 $SET (DPPUSE = 1)
88 ;
89 ; <q> DPP3USE: Use DPP3 register during variable initialization
90 ; --- <i> Set DPP3USE = 0 to disable the usage of DPP3 during initialization of
91 ; <i> variables. This option might be required if you write
92 ; <i> program parts that are reloaded during application
93 ; <i> execution and increase code size of the startup code.
94 $SET (DPP3USE = 1)
95 ;
96 ;</h>
97 ; <h> CPU Configuration
98 ; =====================
99 ;
100 ; <e> Definitions for CPU Configuration Register CPUCON1
101 ; ======================================================
102 ;
103 ; INIT_CPUCON1: Init CPUCON1 register
104 ; --- <i>Set INIT_CPUCON1 = 1 to initialize the CPUCON1 register
105 $SET (INIT_CPUCON1 = 0) ; default: do not initialize CPUCON1 /Dave/
106 ;
107 ; <q> ZCJ: Enable Zero Cycle Jump Function (CPUCON1.0):
0001 108 _ZCJ EQU 1 ; 0 = Disable Zero Cycle Jump Function /Dave/
109 ; 1 = Enable Zero Cycle Jump Function
110 ;
111 ; <q> BP: Enable Branch Prediction Unit (CPUCON1.1):
0001 112 _BP EQU 1 ; 0 = Disable Branch Prediction Unit /Dave/
113 ; 1 = Enable Branch Prediction Unit
114 ;
115 ; <q> INTSCXT: Enable Interruptability of Switch Context Instruction (CPUCON1.2):
0001 116 _INTSCXT EQU 1 ; 0 = Disable Interruption of SCXT instruction /Dave/
117 ; 1 = Enable Interruption of SCXT instruction
118 ;
119 ; SGTDIS: Disable Segmentation Control (CPUCON1.3):
$IF TINY
A166 MACRO ASSEMBLER START_V3 03/15/2019 15:27:40 PAGE 3
_SGTDIS EQU 0 ; disable segmented mode for TINY model /Dave/
122 $ELSE
0000 123 _SGTDIS EQU 0 ; enable segmented mode (Reset Value)
124 $ENDIF
125 ;
126 ; <o> WDTCTL: Watchdog Timer Control (CPUCON1.4):
127 ; <0=> DISWDT executable until end of EINIT <1=> DISWDT/ENWDT always executable
0000 128 _WDTCTL EQU 0 ; 0 = DISWDT executable until end of EINIT /Dave/
129 ; 1 = DISWDT/ENWDT always executable
130 ;
131 ; <o> VECSC: Vector Table Scaling Factor (CPUCON1.5 .. CPUCON1.6)
132 ; <0=> 2 words <1=> 4 words <2=> 8 words <3=> 16 words
0000 133 _VECSC EQU 0 ; 0 = Space between two vectors is 2 words /Dave/
134 ; 1 = Space between two vectors is 4 words
135 ; 2 = Space between two vectors is 8 words
136 ; 3 = Space between two vectors is 16 words
137 ;
138 ; </e>
139 ;
140 ; <e> Definitions for CPU Configuration Register CPUCON2
141 ; ======================================================
142 ;
143 ; INIT_CPUCON2: Init CPUCON2 register
144 ; --- <i>Set INIT_CPUCON2 = 1 to initialize the CPUCON2 register
145 $SET (INIT_CPUCON2 = 0) ; default: do not initialize CPUCON2 /Dave/
146 ;
147 ; <q> SL: Enable Short Loop Mode (CPUCON2.0)
0001 148 _SL EQU 1 ; 0 = Short Loop mode disabled /Dave/
149 ; 1 = Short Loop mode enabled
150 ;
151 ; <q> DAID: Disable Atomic Injection Deny (CPUCON2.1)
0001 152 _DAID EQU 1 ; 0 = Injection-requests are denied during Atomic
153 ; 1 = Injection-requests are not denied during Atomic
154 ;
155 ; <q> RETST: Enable Return Stack (CPUCON2.3)
0001 156 _RETST EQU 1 ; 0 = Return Stack disabled /Dave/
157 ; 1 = Return Stack enabled
158 ;
159 ; <q> OVRUN: Allow Pipeline Bubble Overrun (CPUCON2.4)
0001 160 _OVRUN EQU 1 ; 0 = Overrun of Pipeline Bubbles not allowed /Dave/
161 ; 1 = Overrun of Pipeline Bubbles allowed
162 ;
163 ; <q> LFIC: Linear Follower Instruction Cache (CPUCON2.5)
0001 164 _LFIC EQU 1 ; 0 = Zero Cycle Jump Cache disabled /Dave/
165 ; 1 = Zero Cycle Jump Cache enabled
166 ;
167 ; <q> STEN: Enable Stall Instruction (CPUCON2.6)
0000 168 _STEN EQU 0 ; 0 = Stall instruction disabled /Dave/
169 ; 1 = Stall instruction enabled
170 ;
171 ; <q> EIOIAEN: Early IO Injection Acknowledge guaranteed (CPUCON2.7)
0001 172 _EIOIAEN EQU 1 ; 0 = Injection ack. by destructive read not guaranteed
173 ; ; 1 = Injection ack. by destructive read guaranteed
174 ;
175 ; <q> BYPF: Enable Fetch Bypass Control (CPUCON2.8)
0001 176 _BYPF EQU 1 ; 0 = Bypass Path from Fetch to Decode disabled /Dave/
A166 MACRO ASSEMBLER START_V3 03/15/2019 15:27:40 PAGE 4
177 ; 1 = Bypass Path from Fetch to Decode enabled
178 ;
179 ; <q> BYPPF: Enable Prefecth Bypass Control (CPUCON2.9)
0001 180 _BYPPF EQU 1 ; 0 = Bypass Path from Prefetch to Decode disabled /Dave/
181 ; 1 = Bypass Path from Prefetch to Decode enabled
182 ;
183 ; <o> FIFOFED: FIFO Fill Configuration (CPUCON2.10 .. CPUCON2.11)
184 ; <0=> FIFO disabled <1=> 1 instruction
185 ; <2=> 2 instructions <3=> 3 instructions
0003 186 _FIFOFED EQU 3 ; 0 = FIFO disabled /Dave/
187 ; 1 = FIFO filled with up to 1 instruction per cycle
188 ; 2 = FIFO filled with up to 2 instructions per cycle
189 ; 3 = FIFO filled with up to 3 instructions per cycle
190 ;
191 ;<o> FIFODEPTH: FIFO Depth Configuration (CPUCON2.12 .. CPUCON2.15) <0-8>
0008 192 _FIFODEPTH EQU 8 ; 0 = No FIFO entries (No FIFO) /Dave/
193 ; 1 = 1 FIFO entry
194 ; ...
195 ; 8 = 8 FIFO entries
196 ; 9 - 15 = reserved
197 ;</e>
198
199 ; <e> Internal Memory Block Control
200 ; =================================
201 ;
202 ; INIT_IMBCTR: Init IMBCTR register
203 ; --- <i>Set INIT_IMBCTR = 1 to initialize the IMBCTRL/H register
204 $SET (INIT_IMBCTR = 0) ; default: do not initialize IMBCTR /Dave/
205 ;
206 ; <h> Definitions for Internal Memory Block Control Register IMBCTRL
207 ; ==================================================================
208 ;
209 ; <o> WSFLASH: Wait States for the Flash Memory (IMBCTRL.0 .. IMBCTRL.2)<1-7>
210 ; <i> this value also specifies the read time of the PSRAM in the flash emulation addr
ess range
0000 211 _WSFLASH EQU 0 ; 0 = No waitstates (forbidden!) /Dave/
212 ; 1-7 = One to seven waitstate
213 ;
214 ; <q> DLCPF: Disable Linear Code Pre-Fetch (IMBCTRL.3)
215 ; <0=> High Speed Mode
216 ; <1=> Low Power Mode
0000 217 _DLCPF EQU 0 ; 0 = High Speed Mode /Dave/
218 ; 1 = Low Power Mode
219 ;
220 ; <o> DCF: Disable Code Fetch from Flash Memory (IMBCTRL.12 .. IMBCTRL.13)
221 ; <i> values 0 and 3 are not allowed
222 ; <1=> no instruction fetch if RPA 1
223 ; <2=> instructions can always be fetched
0000 224 _DCF EQU 0 ; 0 = Illegal state /Dave/
225 ; 1 = no instruction fetch if RPA=1
226 ; 2 = instructions can always be fetched
227 ; 3 = Illegal state
228 ;
229 ; <o> DDF: Disable Data Fetch from Flash Memory (IMBCTRL.14 .. IMBCTRL.15)
230 ; <i> values 0 and 3 are not allowed
231 ; <1=> no data read if RPA=1
232 ; <2=> data can always be read
0000 233 _DDF EQU 0 ; 0 = Illegal state /Dave/
234 ; 1 = no data read if RPA=1
235 ; 2 = data can always be read
A166 MACRO ASSEMBLER START_V3 03/15/2019 15:27:40 PAGE 5
236 ; 3 = Illegal state
237 ;
238 ;</h>
239
240 ; <h> Definitions for Internal Memory Block Control Register IMBCTRH
241 ; ==================================================================
242 ;
243 ; <o> PSPROT: PSRAM Write Protection (IMBCTRH.8 .. IMBCTRH.15)<0-255>
244 ; <i> The start address of the writable range is E00000H + 1000H*PSPROT
0000 245 _PSPROT EQU 0 ; 0 = Complete PSRAM is writable /Dave/
246 ; ...
247 ; 16 or bigger = PSRAM is write protected
248 ;</h>
249 ;</e>
250 ;
251 ;</h>
252 ;
253 ; <h> Oscillator Control
254 ; ======================
255 ;
256 ; <e> Definitions for Wake-up Clock Register WUOSCCON
257 ; ===================================================
258 ;
259 ; INIT_WUOSCCON: Init WUOSCCON register
260 ; --- Set INIT_WUOSCCON = 1 to initialize the WUOSCCON register
261 $SET (INIT_WUOSCCON = 0) ; /Dave/
262 ;
263 ; <o> FREQSEL: System Clock Select (WUOSCCON.0 .. WUOSCCON.1)
264 ; <0=> 500kHz <1=> 300 kHz
265 ; <2=> 200kHz <3=> 130 kHz
0000 266 _FREQSEL EQU 0 ; 0 = 500 kHz /Dave/
267 ; 1 = 300 kHz
268 ; 2 = 200 kHz
269 ; 3 = 130 kHz
270 ;
271 ; <o> PWSEL: Power Consumption Selection (WUOSCCON.2 .. WUOSCCON.3)
272 ; <0=> not specified <1=> not specified
273 ; <2=> not specified <3=> not specified
0000 274 _PWSEL EQU 0 ; 0 = not specified /Dave/
275 ; 1 = not specified
276 ; 2 = not specified
277 ; 3 = not specified
278 ;
279 ; <q> DIS: Clock Disable (WUOSCCON.4)
280 ; <i> enables the automatic asyncronous switch to the emergency clock
281 ; <i> in case of an OSCWDT or VCOLCK emergency event
0000 282 _DIS EQU 0 ; 0 = Clock is enabled /Dave/
283 ; 1 = Clock is disabled
284 ;
285 ; </e>
286 ;
287 ; <e> Definitions for High Precision Oscillator Register HPOSCCON
288 ; ================================================================
289 ;
290 ; INIT_HPOSCCON: Init HPOSCCON register
291 ; --- Set INIT_HPOSCCON = 1 to initialize the HPOSCCON register
292 $SET (INIT_HPOSCCON = 0) ; /Dave/
293 ;
294 ; <q> OSCWDTRST: Oscillator Watchdog Reset (HPOSCCON.1)
295 ; <i> specifies if the oscillator watchdog will be reset
0000 296 _OSCWDTRST EQU 0 ; 0 = The oscillator watchdog of the PLL is not reset and remains act
ive /Dave/
297 ; 1 = The oscillator watchdog of the PLL is reset and restarte
d
A166 MACRO ASSEMBLER START_V3 03/15/2019 15:27:40 PAGE 6
298 ;
299 ; <o> MODE: Oscillator Mode (HPOSCCON.2 .. HPOSCCON.3)
300 ; <0=>External Crystal Mode. Power-Saving Mode is not entered <1=>OSC_HP disabled.
Power-Saving Mode is not entered
301 ; <2=>External Input Clock Mode. Power-Saving Mode is not entered <3=>OSC_HP disabled.
Power-Saving Mode is entered
0000 302 _MODE EQU 0 ; 0 = External Crystal Mode. Power-Saving Mode is not entered /Dave/
303 ; 1 = OSC_HP disabled. Power-Saving Mode is not entered
304 ; 2 = External Input Clock Mode. Power-Saving Mode is not ente
red
305 ; 3 = OSC_HP disabled. Power-Saving Mode is entered (default)
306 ;
307 ; <q> X1DEN: XTAL1 Data Enable (HPOSCCON.7)
308 ; <i> specifies if X1D reflects the inverted level of XTAL1
0000 309 _X1DEN EQU 0 ; 0 = Bit X1D is not updated /Dave/
310 ; 1 = Bit X1D reflects the inverted level of XTAL1
311 ;
312 ; <q> SHBY: Shaper Bypass (HPOSCCON.8)
313 ; <i> Switch shaper or/off
0000 314 _SHBY EQU 0 ; 0 = The shaper is not bypassed /Dave/
315 ; 1 = The shaper is bypassed
316 ;
317 ; <q> EMCLKEN: OSCWDT Emergency System Clock Source Select Enable (HPOSCCON.9)
318 ; <i> Clock selection in case of an OSCWDT emergency
0000 319 _HP_EMCLKEN EQU 0 ; 0 = MCM controlled by SYSCON0.CLKSEL /Dave/
320 ; 1 = MCM controlled by SYSCON0.EMCLKSEL
321 ;
322 ; <q> EMFINDISEN: Emergency Input Clock Disconnect Enable (HPOSCCON.10)
323 ; <i> defines whether bit PLLSTAT.FINDIS is set in an emergency
0000 324 _HP_EMFINDISEN EQU 0 ; 0 = No update of PLLSTAT.FINDIS /Dave/
325 ; 1 = PLLSTAT.FINDIS is set in an OSCWDT emergency case
326 ;
327 ; </e>
328 ;
329 ; <e> Definitions for PLL Clock Register PLLOSCCON
330 ; =================================================
331 ;
332 ; INIT_PLLOSCCON: Init PLLOSCCON register
333 ; --- Set INIT_PLLOSCCON = 1 to initialize the PLLOSCCON register
334 $SET (INIT_PLLOSCCON = 0) ; /Dave/
335 ;
336 ; <q> OSCPD: Internal Clock IOSC Power Saving Mode (PLLOSCCON.0)
337 ; <i> specifies if IOSC is active or not
0000 338 _OSCPD EQU 0 ; 0 = IOSC is active /Dave/
339 ; 1 = IOSC is no longer powered
340 ;
341 ; </e>
342 ; </h>
343 ;
344 ; <e> PLL Control
345 ; ===============
346 ;
347 ; INIT_PLLCON: Init PLLCON register
348 ; --- Set INIT_PLLCON = 1 to initialize all the PLLCONx register
349 $SET (INIT_PLLCON = 0) ; /Dave/
350 ;
351 ; <h> Definitions for PLL Clock Register PLLCON0
352 ; ===============================================
353 ;
354 ; <o> VCOBY: VCO Bypass (PLLCON0.0)
A166 MACRO ASSEMBLER START_V3 03/15/2019 15:27:40 PAGE 7
355 ; <i> specifies if VCO is bypassed or not
356 ; <0=> Normal operation, VCO is not bypassed
357 ; <1=> Prescaler Mode. VCO is bypassed
0000 358 _VCOBY EQU 0 ; 0 = Normal operation, VCO is not bypassed /Dave/
359 ; 1 = Prescaler Mode. VCO is bypassed
360 ;
361 ; <q> VCOPWD: VCO Power Saving Mode (PLLCON0.1)
362 ; <i> disables VCO
0000 363 _VCOPWD EQU 0 ; 0 = VCO is active /Dave/
364 ; 1 = VCO is inactive in power saving mode
365 ;
366 ; <o> VCOSEL: VCO Range Select (PLLCON0.2)
367 ; <0=> 48...112 MHz
368 ; <1=> 96...160 MHz
369 ; <i> VCOSEL VCO Range Select
0000 370 _VCOSEL EQU 0 ; 0 = 48...112 MHz /Dave/
371 ; 1 = 96...160 MHz
372 ;
373 ; <o> NDIV: N-Divider Value (PLLCON0.8 .. PLLCON0.13) <16-40>
374 ; <i> The resulting factor N for the N-Divider is (NDIV+1)
375 ; <i> Only values between 16 and 40 are allowed
0000 376 _NDIV EQU 0 ; /Dave/
377 ;
378 ; </h>
379 ;
380 ; <h> Definitions for PLL Clock Register PLLCON1
381 ; ===============================================
382 ;
383 ; <q> PLLPWD: Power Saving Mode (PLLCON1.0)
384 ; <i> disables PLL in power saving mode
0000 385 _PLLPWD EQU 0 ; 0 = Normal Mode /Dave/
386 ; 1 = Complete PLL block is inactive in power saving mode
387 ;
388 ; <o> OSCSEL: Clock Input Selection (PLLCON1.1)
389 ; <i> selects PLL input clock
390 ; <0=> external oscillator (OSC_HP)
391 ; <1=> internal oscillator (IOSC)
0000 392 _OSCSEL EQU 0 ; 0 = PLL input clock is OSC_HP output /Dave/
393 ; 1 = PLL input clock is IOSC output
394 ;
395 ; <q> AOSCSEL: Asyncronous Clock Input Selection (PLLCON1.3)
396 ; <i>
0000 397 _AOSCSEL EQU 0 ; 0 = Configuration is controlled via bis OSCSEL /Dave/
398 ; 1 = PLL internal clock IOSC is selected asyncronously
399 ;
400 ; <q> EMCLKEN: VCOLCK Emergency System Clock Source Select Enable (PLLCON1.5)
401 ; <i> Master clock selection in case of emergency
0000 402 _PLL_EMCLKEN EQU 0 ; 0 = MCM controlled by SZSCON0.CLKSEL /Dave/
403 ; 1 = MCM controlled by SZSCON0.EMCLKSEL in a VCOLCK emergency
case
404 ;
405 ; <q> EMFINDISEN: Emergency Input Clock Disconnect Enable (PLLCON1.6)
406 ; <i> specifies if PLLSTAT.FINDIS is set in a VCOLCK emergency case
0000 407 _PLL_EMFINDISEN EQU 0 ; 0 = No update of PLLSTAT.FINDIS /Dave/
408 ; 1 = PLLSTAT.FINDIS is set in a VCOLCK emergency case
409 ;
410 ; <o> PDIV: P-Divider Value (PLLCON1.8 .. PLLCON1.11) <0-15>
411 ; <i> The resulting factor P for the P-Divider is (PDIV+1)
0000 412 _PDIV EQU 0 ; /Dave/
413 ;
A166 MACRO ASSEMBLER START_V3 03/15/2019 15:27:40 PAGE 8
414 ; </h>
415 ;
416 ; <h> Definitions for PLL Clock Register PLLCON2
417 ; ===============================================
418 ;
419 ; <o> K1DIV: K1-Divider Value (PLLCON2.0 .. PLLCON2.9) <0-1023>
420 ; <i> The resulting factor K1 for the K1-Divider is (K1DIV+1)
0000 421 _K1DIV EQU 0 ; /Dave/
422 ;
423 ; </h>
424 ;
425 ; <h> Definitions for PLL Clock Register PLLCON3
426 ; ===============================================
427 ;
428 ; <o> K2DIV: K2-Divider Value (PLLCON3.0 .. PLLCON3.9) <0-1023>
429 ; <i> The resulting factor K2 for the K2-Divider is (K2DIV+1)
0000 430 _K2DIV EQU 0 ; /Dave/
431 ;
432 ; </h>
433 ; </e>
434 ;
435 ; <h> System Contol
436 ; =================
437 ;
438 ; <e> Definitions for System Configuration Register SYSCON0
439 ; =========================================================
440 ;
441 ; INIT_SYSCON0: Init SYSCON0 register
442 ; --- Set INIT_SYSCON0 = 1 to initialize the SYSCON0 register
443 $SET (INIT_SYSCON0 = 0) ; /Dave/
444 ;
445 ; <o> CLKSEL: System Clock Select (SYSCON0.0 .. SYSCON0.1)
446 ; <0=> WUT clock output <1=> OSC_HP output
447 ; <2=> PLL clock output <3=> DIRIN clock input
0000 448 _CLKSEL EQU 0 ; 0 = WUT clock output /Dave/
449 ; 1 = OSC_HP output
450 ; 2 = PLL clock output
451 ; 3 = Direct Input clock DIRIN
452 ;
453 ; <o> EMCLKSEL: Emergency Clock Select (SYSCON0.3 .. SYSCON0.4)
454 ; <0=> WUT clock output <1=> OSC_HP output
455 ; <2=> PLL clock output <3=> DIRIN clock input
0000 456 _EMCLKSEL EQU 0 ; 0 = WUT clock output /Dave/
457 ; 1 = OSC_HP output
458 ; 2 = PLL clock output
459 ; 3 = Direct Input clock DIRIN
460 ;
461 ; <q> EMCLKSELEN: Emergency Clock Select Enable (SYSCON0.6)
462 ; <i> enables the automatic asyncronous switch to the emergency clock
463 ; <i> in case of an OSCWDT or VCOLCK emergency event
0000 464 _EMCLKSELEN EQU 0 ; 0 = Emergency clock switch is disabled /Dave/
465 ; 1 = Emergency clock switch is enabled
466 ;
467 ; </e>
468 ;</h>
469 ;
470 ;
471 ; <e> Definitions for External Service Request (ESR) Pins
472 ; =======================================================
473 ;
474 ; INIT_ESRCFG: Init ESRCFG0/1/2 register
475 ; --- Set INIT_ESRCFG = 1 to initilize the ESRCFG0/1/2 register
476 $SET (INIT_ESRCFG = 0)
A166 MACRO ASSEMBLER START_V3 03/15/2019 15:27:40 PAGE 9
477 ;
478 ; <o> ESR 0: Pin Control(ESRCFG.PC)
479 ; <0=> No pull device activated. Input is not inverted
480 ; <1=> Pull-down device activated. Input is not inverted
481 ; <2=> Pull-up device activated. Input is not inverted
482 ; <3=> No pull device activated. Input is not inverted
483 ; <4=> No pull device activated. Input is inverted
484 ; <5=> Pull-down device activated. Input is inverted
485 ; <6=> Pull-up device activated. Input is inverted
486 ; <7=> No pull device activated. Input is inverted
487 ; <8=> Output of ESRCFGx.OUT. Push-pull
488 ; <9=> Output of ESRCFGx.OUT. Push-pull
489 ; <10=> Output drives a 0 for an Internal Application Reset, a 1 otherwise. Push-pull
490 ; <11=> Output drives a 0 for an Application Reset, a 1 otherwise. Push-pull
491 ; <12=> Output of ESRCFGx.OUT. Open-drain
492 ; <13=> Output of ESRCFGx.OUT. Open-drain
493 ; <14=> Output drives a 0 for an Internal Application Reset. Open-drain
494 ; <15=> Output drives a 0 for an Application Reset. Open-drain
000E 495 _ESR_PC0 EQU 14 ; 0 = No pull device activated. Input is not inverted
496 ; 1 = Pull-down device activated. Input is not inverted
497 ; 2 = Pull-up device activated. Input is not inverted
498 ; 3 = No pull device activated. Input is not inverted
499 ; 4 = No pull device activated. Input is inverted
500 ; 5 = Pull-down device activated. Input is inverted
501 ; 6 = Pull-up device activated. Input is inverted
502 ; 7 = No pull device activated. Input is inverted
503 ; 8 = Output of ESRCFGx.OUT. Push-pull
504 ; 9 = Output of ESRCFGx.OUT. Push-pull
505 ; 10 = Output drives a 0 for an Internal Application Reset, a
1 otherwise. Push-pull
506 ; 11 = Output drives a 0 for an Application Reset, a 1 otherwi
se. Push-pull
507 ; 12 = Output of ESRCFGx.OUT. Open-drain
508 ; 13 = Output of ESRCFGx.OUT. Open-drain
509 ; 14 = Output drives a 0 for an Internal Application Reset. Op
en-drain
510 ; 15 = Output drives a 0 for an Application Reset. Open-drain
511
512
513 ; <o> ESR 1: Pin Control(ESRCFG.PC) if avalible
514 ; <0=> No pull device activated. Input is not inverted
515 ; <1=> Pull-down device activated. Input is not inverted
516 ; <2=> Pull-up device activated. Input is not inverted
517 ; <3=> No pull device activated. Input is not inverted
518 ; <4=> No pull device activated. Input is inverted
519 ; <5=> Pull-down device activated. Input is inverted
520 ; <6=> Pull-up device activated. Input is inverted
521 ; <7=> No pull device activated. Input is inverted
522 ; <8=> Output of ESRCFGx.OUT. Push-pull
523 ; <9=> Output of ESRCFGx.OUT. Push-pull
524 ; <10=> Output drives a 0 for an Internal Application Reset, a 1 otherwise. Push-pull
525 ; <11=> Output drives a 0 for an Application Reset, a 1 otherwise. Push-pull
526 ; <12=> Output of ESRCFGx.OUT. Open-drain
527 ; <13=> Output of ESRCFGx.OUT. Open-drain
528 ; <14=> Output drives a 0 for an Internal Application Reset. Open-drain
529 ; <15=> Output drives a 0 for an Application Reset. Open-drain
0002 530 _ESR_PC1 EQU 2 ; 0 = No pull device activated. Input is not inverted
531 ; 1 = Pull-down device activated. Input is not inverted
532 ; 2 = Pull-up device activated. Input is not inverted
533 ; 3 = No pull device activated. Input is not inverted
534 ; 4 = No pull device activated. Input is inverted
535 ; 5 = Pull-down device activated. Input is inverted
536 ; 6 = Pull-up device activated. Input is inverted
537 ; 7 = No pull device activated. Input is inverted
538 ; 8 = Output of ESRCFGx.OUT. Push-pull
539 ; 9 = Output of ESRCFGx.OUT. Push-pull
A166 MACRO ASSEMBLER START_V3 03/15/2019 15:27:40 PAGE 10
540 ; 10 = Output drives a 0 for an Internal Application Reset, a
1 otherwise. Push-pull
541 ; 11 = Output drives a 0 for an Application Reset, a 1 otherwi
se. Push-pull
542 ; 12 = Output of ESRCFGx.OUT. Open-drain
543 ; 13 = Output of ESRCFGx.OUT. Open-drain
544 ; 14 = Output drives a 0 for an Internal Application Reset. Op
en-drain
545 ; 15 = Output drives a 0 for an Application Reset. Open-drain
546
547
548 ; <o> ESR 2: Pin Control(ESRCFG.PC) if avalible
549 ; <0=> No pull device activated. Input is not inverted
550 ; <1=> Pull-down device activated. Input is not inverted
551 ; <2=> Pull-up device activated. Input is not inverted
552 ; <3=> No pull device activated. Input is not inverted
553 ; <4=> No pull device activated. Input is inverted
554 ; <5=> Pull-down device activated. Input is inverted
555 ; <6=> Pull-up device activated. Input is inverted
556 ; <7=> No pull device activated. Input is inverted
557 ; <8=> Output of ESRCFGx.OUT. Push-pull
558 ; <9=> Output of ESRCFGx.OUT. Push-pull
559 ; <10=> Output drives a 0 for an Internal Application Reset, a 1 otherwise. Push-pull
560 ; <11=> Output drives a 0 for an Application Reset, a 1 otherwise. Push-pull
561 ; <12=> Output of ESRCFGx.OUT. Open-drain
562 ; <13=> Output of ESRCFGx.OUT. Open-drain
563 ; <14=> Output drives a 0 for an Internal Application Reset. Open-drain
564 ; <15=> Output drives a 0 for an Application Reset. Open-drain
0002 565 _ESR_PC2 EQU 2 ; 0 = No pull device activated. Input is not inverted
566 ; 1 = Pull-down device activated. Input is not inverted
567 ; 2 = Pull-up device activated. Input is not inverted
568 ; 3 = No pull device activated. Input is not inverted
569 ; 4 = No pull device activated. Input is inverted
570 ; 5 = Pull-down device activated. Input is inverted
571 ; 6 = Pull-up device activated. Input is inverted
572 ; 7 = No pull device activated. Input is inverted
573 ; 8 = Output of ESRCFGx.OUT. Push-pull
574 ; 9 = Output of ESRCFGx.OUT. Push-pull
575 ; 10 = Output drives a 0 for an Internal Application Reset, a
1 otherwise. Push-pull
576 ; 11 = Output drives a 0 for an Application Reset, a 1 otherwi
se. Push-pull
577 ; 12 = Output of ESRCFGx.OUT. Open-drain
578 ; 13 = Output of ESRCFGx.OUT. Open-drain
579 ; 14 = Output drives a 0 for an Internal Application Reset. Op
en-drain
580 ; 15 = Output drives a 0 for an Application Reset. Open-drain
581 ; </e>
582 ;
583 ;
584 ;
585 ; <e> Watchdog Timer
586 ; ==================
587 ;
588 ; --- Set WATCHDOG = 0 to enable the Hardware watchdog and initialize the WDTCON regis
ter
589 $SET (WATCHDOG = 0) ; 0 = Disabled Hardware watchdog /Dave/
590 ;
591 ; <o> IR: Input Frequency Request Bit (WDTCS.8)
592 ; <0=> Peripheral Frequency divided by 16384
593 ; <1=> Peripheral Frequency divided by 256
0000 594 _IR EQU 0 ; 0 = frequency f_peripheral / 16384 (CPU default) /Dave/
595 ; 1 = frequency f_peripheral / 256
596 ;
A166 MACRO ASSEMBLER START_V3 03/15/2019 15:27:40 PAGE 11
597 ; <o> WDTREL: Watchdog Timer Reload Value (WDTREL0 .. WDTREL15) <0-65535>
598 ; <i> Reload value of WDT (counts up, overflow gives Watchdog reset)
FFFC 599 _WDTREL EQU 65532 ; /Dave/
600 ;
601 ; </e>
602 ;
603 ; <h> External Bus Configuration
604 ;
605 ; <e> Configure External Bus (EBC) Behaviour
606 ; ==========================================
607 ;
608 ; --- Set CONFIG_EBC = 0 to initialize the EBCMOD0/EBCMOD1 registers
609 $SET (CONFIG_EBC = 0) ; 0 = EBCMOD0/EBCMOD1 are set during reset according the /Dave/
610 ; of configuration bus (typical Port0) values.
611 ; 1 = the following external bus configuration values
612 ; are written to EBCMOD and BUSACT0
613 ;
614 ; <h> Definitions for EBC Mode 0 register EBCMOD0
615 ; ===============================================
616 ;
617 ; <o> SAPEN: Segment Address Pins Enabled (EBCMOD0.0 .. EBCMOD0.3) <0-8>
618 ; <i> Number of active Address Lines (A16-A23)
0000 619 _SAPEN EQU 0 ; 0 = No segment address pins enabled /Dave/
620 ; 1 = One (A16) segment address pin enabled
621 ; : = :
622 ; 8 = Eight (A16 .. A23) address pins enabled
623 ; 9 - 15 = reserved
624 ;
625 ; <o> CSPEN: CSx Pins Enabled (EBCMOD0.4 .. EBCMOD0.7) <0-8>
626 ; <i> Number of active ChipSelect pins
0000 627 _CSPEN EQU 0 ; 0 = No CS pins enabled /Dave/
628 ; 1 = One CS (CS0) pin enabled
629 ; : = :
630 ; 8 = Eight CS (CS0 .. CS7) pins enabled
631 ; 9 - 15 = reserved
632 ; Note: the number of available CS pins depends on the chip used
633 ;
634 ; <q> ARBEN: Enable Bus Arbitration Pins (EBCMOD0.8)
0000 635 _ARBEN EQU 0 ; 0 = HOLD, HLDA and BREQ pins are tristate or act as GPIO /Dave/
636 ; 1 = HOLD, HLDA and BREQ pins act normally
637 ;
638 ; <o> SLAVE: SLAVE mode enable (EBCMOD0.9)
639 ; <0=> Master Mode <1=> Slave Mode
0000 640 _SLAVE EQU 0 ; 0 = Bus arbiter acts in master mode /Dave/
641 ; 1 = Bus arbiter acts in slave mode
642 ;
643 ; <q> EBCDIS: Disable EBC pins (EBCMOD0.10)
0000 644 _EBCDIS EQU 0 ; 0 = EBC is using the pins for external bus /Dave/
645 ; 1 = EBC off (pins to be used as GPIO if implemented)
646 ;
647 ; <o> WRCFG: Configuration for pins WR/WRL and BHE/WRH (EBCMOD0.11)
648 ; <0=> WR and BHE <1=> WRL and WRH
0000 649 _WRCFG EQU 0 ; 0 = Pins act as WR and BHE /Dave/
650 ; 1 = Pins act as WRL and WRH
651 ;
652 ; <q> BYTDIS: Disable BHE pin (EBCMOD0.12)
0000 653 _BYTDIS EQU 0 ; 0 = BHE enabled /Dave/
654 ; 1 = BHE disabled (GPIO function if implemented)
655 ;
A166 MACRO ASSEMBLER START_V3 03/15/2019 15:27:40 PAGE 12
656 ; <q> ALEDIS: Disable ALE pin (EBCMOD0.13)
0000 657 _ALEDIS EQU 0 ; 0 = ALE pin enabled /Dave/
658 ; 1 = ALE pin disabled (GPIO function if implemented)
659 ;
660 ; <q> RDYDIS: Disable READY pin (EBCMOD0.14)
0000 661 _RDYDIS EQU 0 ; 0 = READY enabled /Dave/
662 ; 1 = READY disabled (GPIO function if implemented)
663 ;
664 ; <o> RDYPOL: READY pin polarity (EBCMOD0.15)
665 ; <0=> Active Low <1=> Active High
0000 666 _RDYPOL EQU 0 ; 0 = READY pin is active low /Dave/
667 ; 1 = READY pin is active high
668 ;
669 ;</h>
670 ;
671 ; <h>Definitions for EBC Mode 1 register EBCMOD1
672 ; ==============================================
673 ;
674 ; <o> APDIS: Address Port Pins Disable (EBCMOD1.0 .. EBCMOD1.3) <0-15>
0000 675 _APDIS EQU 0 ; 0 = Address bus pins 15-1 of PORT1 enabled /Dave/
676 ; 1 = Pin A15 disabled, A14-1 enabled
677 ; 2 = Pin A15-A14 disabled, A13-1 enabled
678 ; ...
679 ; 15 = Pins A15-A1 disabled
680 ;
681 ; <q> A0PDIS: Address Bit 0 Pin Disable (EBCMOD1.4)
0000 682 _A0PDIS EQU 0 ; 0 = Address bus pin 0 of PORT1 enabled /Dave/
683 ; 1 = Address bus pin 0 of PORT1 disabled
684 ;
685 ; <q> ALPDIS: Address Low Pins Disable (EBCMOD1.5)
0000 686 _ALPDIS EQU 0 ; 0 = Address bus pin 7-0 generally enabled /Dave/
687 ; 1 = Address bus pin 7-0 of PORT1 disabled
688 ;
689 ; <q> DHPDIS: Data High Port Pins Disable (EBCMOD1.6)
0000 690 _DHPDIS EQU 0 ; 0 = Data bus pins 15-8 of PORT0 enabled /Dave/
691 ; 1 = Data bus pins 15-8 disabled (used as GPIO)
692 ;
693 ; <q> WRPDIS: WR/WRL Pin Disable (EBCMOD1.7)
0000 694 _WRPDIS EQU 0 ; 0 = WR/WRL pin of Port P20 enabled /Dave/
695 ; 1 = WR/WRL pin of Port P20 disabled
696 ;
697 ;</h></e>
698 ;
699 ; <e> Configure External Bus Behaviour for CS0 area
700 ; =================================================
701 ;
702 ; --- Set CONFIG_CS0 = 1 to initialize the FCONCS0/TCONCS0 registers
703 $SET (CONFIG_CS0 = 0) ; /Dave/
704 ;
705 ; <h>Definitions for Function Configuration Register FCONCS0
706 ; ==========================================================
707 ;
708 ; <q> ENCS0: Enable Chip Select (FCONCS0.0)
0000 709 _ENCS0 EQU 0 ; 0 = Chip Select 0 disabled /Dave/
710 ; 1 = Chip Select 0 enabled
711 ;
712 ; <q> RDYEN0: Ready Enable (FCONCS0.1)
A166 MACRO ASSEMBLER START_V3 03/15/2019 15:27:40 PAGE 13
0000 713 _RDYEN0 EQU 0 ; 0 = Access time controlled by TCONCS0.PHE0 /Dave/
714 ; 1 = Access time cont. by TCONCS0.PHE0 and READY signal
715 ;
716 ; <o> RDYMOD0: Ready Mode (FCONCS0.2)
717 ; <0=> Asynchronous <1=> Synchronous
0000 718 _RDYMOD0 EQU 0 ; 0 = Asynchronous READY /Dave/
719 ; 1 = Synchronous READY
720 ;
721 ; <o> BTYP0: Bus Type Selection (FCONCS0.4 .. FCONCS0.5)
722 ; <0=> 8-bit Demultiplexed Bus <1=> 8-bit Multiplexed Bus
723 ; <2=> 16-bit Demultiplexed Bus <3=> 16-bit Multiplexed Bus
0000 724 _BTYP0 EQU 0 ; 0 = 8 bit Demultiplexed bus /Dave/
725 ; 1 = 8 bit Multiplexed bus
726 ; 2 = 16 bit Demultiplexed bus
727 ; 3 = 16 bit Multiplexed bus
728 ; </h>
729 ;
730 ; <h> TCONCS0: Definitions for the Timing Configuration register
731 ; ==============================================================
732 ;
733 ; <o> PHA0: Phase A clock cycles (TCONCS0.0 .. TCONCS0.1) <0-3>
0000 734 _PHA0 EQU 0 ; 0 = 0 clock cycles /Dave/
735 ; : = :
736 ; 3 = 3 clock cycles
737 ;
738 ; <o> PHB0: Phase B clock cycles (TCONCS0.2) <1-2> <#-1>
0000 739 _PHB0 EQU 0 ; 0 = 1 clock cycle /Dave/
740 ; 1 = 2 clock cycles
741 ;
742 ; <o> PHC0: Phase C clock cycles (TCONCS0.3 .. TCONCS0.4) <0-3>
0000 743 _PHC0 EQU 0 ; 0 = 0 clock cycles /Dave/
744 ; : = :
745 ; 3 = 3 clock cycles
746 ;
747 ; <o> PHD0: Phase D clock cycle (TCONCS0.5) <0-1>
0000 748 _PHD0 EQU 0 ; 0 = 0 clock cycles /Dave/
749 ; 1 = 1 clock cycle
750 ;
751 ; <o> PHE0: Phase E clock cycles (TCONCS0.6 .. TCONCS0.10) <1-32> <#-1>
0000 752 _PHE0 EQU 0 ; 0 = 1 clock cycle /Dave/
753 ; : = :
754 ; 31 = 32 clock cycles
755 ;
756 ; <o> RDPHF0: Phase F read clock cycles (TCONCS0.11 .. TCONCS0.12) <0-3>
0000 757 _RDPHF0 EQU 0 ; 0 = 0 clock cycles /Dave/
758 ; : = :
759 ; 3 = 3 clock cycles
760 ;
761 ; <o> WRPHF0: Phase F write clock cycles (TCONCS0.13 .. TCONCS0.14) <0-3>
0000 762 _WRPHF0 EQU 0 ; 0 = 0 clock cycles /Dave/
763 ; : = :
764 ; 3 = 3 clock cycles
765 ;</h> </e>
766 ;
767 ; <e> Configure External Bus Behaviour for CS1 Area
768 ; =================================================
769 ;
770 ; --- Set CONFIG_CS1 = 1 to initialize the ADDRSEL1/FCONCS1/TCONCS1 registers
771 $SET (CONFIG_CS1 = 0) ; /Dave/
772 ;
773 ; <h>Definitions for Address Select register ADDRSEL1
A166 MACRO ASSEMBLER START_V3 03/15/2019 15:27:40 PAGE 14
774 ; ===================================================
775 ; <o> CS1 Start Address <0x0-0xFFFFFF:0x1000>
0000 776 _ADDR1 EQU 0x0 ; Set CS1# Start Address (default 100000H) /Dave/
777
778 ; <o> CS1 Size in KB
779 ; <4=> 4KB <8=> 8KB <16=> 16KB <32=> 32KB
780 ; <64=> 64KB <128=> 128KB <256=> 256KB <512=> 512KB
781 ; <1024=> 1024KB <2048=> 2048KB <4096=> 4096KB <8192=> 8192KB
1000 782 _SIZE1 EQU 4*KB ; Set CS1# Size (default 1024*KB = 1*MB) /Dave/
783 ; possible values for _SIZE1 are:
784 ; 4*KB (gives RGSZ1 = 0)
785 ; 8*KB (gives RGSZ1 = 1)
786 ; 16*KB (gives RGSZ1 = 2)
787 ; 32*KB (gives RGSZ1 = 3)
788 ; 64*KB (gives RGSZ1 = 4)
789 ; 128*KB (gives RGSZ1 = 5)
790 ; 256*KB (gives RGSZ1 = 6)
791 ; 512*KB (gives RGSZ1 = 7)
792 ; 1024*KB or 1*MB (gives RGSZ1 = 8)
793 ; 2048*KB or 2*MB (gives RGSZ1 = 9)
794 ; 4096*KB or 4*MB (gives RGSZ1 = 10)
795 ; 8192*KB or 8*MB (gives RGSZ1 = 11)
796 ; (RGSZ1 = 12 .. 15 reserved)
797 ;</h>
798 ;
799 ; <h>Definitions for Function Configuration Register FCONCS1
800 ; ==========================================================
801 ;
802 ; <q> ENCS1: Enable Chip Select (FCONCS1.0)
0000 803 _ENCS1 EQU 0 ; 0 = Chip Select 0 disabled /Dave/
804 ; 1 = Chip Select 0 enabled
805 ;
806 ; <q> RDYEN1: Ready Enable (FCONCS1.1)
0000 807 _RDYEN1 EQU 0 ; 0 = Access time controlled by TCONCS1.PHE1 /Dave/
808 ; 1 = Access time cont. by TCONCS1.PHE1 and READY signal
809 ;
810 ; <o> RDYMOD1: Ready Mode (FCONCS1.2)
811 ; <0=> Asynchronous <1=> Synchronous
0000 812 _RDYMOD1 EQU 0 ; 0 = Asynchronous READY /Dave/
813 ; 1 = Synchronous READY
814 ;
815 ; <o> BTYP1: Bus Type Selection (FCONCS1.4 .. FCONCS1.5)
816 ; <0=> 8-bit Demultiplexed Bus <1=> 8-bit Multiplexed Bus
817 ; <2=> 16-bit Demultiplexed Bus <3=> 16-bit Multiplexed Bus
0000 818 _BTYP1 EQU 0 ; 0 = 8 bit Demultiplexed bus /Dave/
819 ; 1 = 8 bit Multiplexed bus
820 ; 2 = 16 bit Demultiplexed bus
821 ; 3 = 16 bit Multiplexed bus
822 ;</h>
823 ;
824 ; <h>TCONCS1: Definitions for the Timing Configuration register
825 ; =============================================================
826 ;
827 ; <o>PHA1: Phase A clock cycles (TCONCS1.0 .. TCONCS1.1) <0-3>
0000 828 _PHA1 EQU 0 ; 0 = 0 clock cycles /Dave/
829 ; : = :
830 ; 3 = 3 clock cycles
831 ;
832 ; <o>PHB1: Phase B clock cycles (TCONCS1.2) <1-2> <#-1>
0000 833 _PHB1 EQU 0 ; 0 = 1 clock cycle /Dave/
A166 MACRO ASSEMBLER START_V3 03/15/2019 15:27:40 PAGE 15
834 ; 1 = 2 clock cycles
835 ;
836 ; <o>PHC1: Phase C clock cycles (TCONCS1.3 .. TCONCS1.4) <0-3>
0000 837 _PHC1 EQU 0 ; 0 = 0 clock cycles /Dave/
838 ; : = :
839 ; 3 = 3 clock cycles
840 ;
841 ; <o>PHD1: Phase D clock cycles (TCONCS1.5) <0-1>
0000 842 _PHD1 EQU 0 ; 0 = 0 clock cycles /Dave/
843 ; 1 = 1 clock cycle
844 ;
845 ; <o> PHE1: Phase E clock cycles (TCONCS1.6 .. TCONCS1.10) <1-32> <#-1>
0000 846 _PHE1 EQU 0 ; 0 = 1 clock cycle /Dave/
847 ; : = :
848 ; 31 = 32 clock cycles
849 ;
850 ; <o>RDPHF1: Phase F read clock cycles (TCONCS1.11 .. TCONCS1.12) <0-3>
0000 851 _RDPHF1 EQU 0 ; 0 = 0 clock cycles /Dave/
852 ; : = :
853 ; 3 = 3 clock cycles
854 ;
855 ; <o>WRPHF1: Phase F write clock cycles (TCONCS1.13 .. TCONCS1.14) <0-3>
0000 856 _WRPHF1 EQU 0 ; 0 = 0 clock cycles /Dave/
857 ; : = :
858 ; 3 = 3 clock cycles
859 ;</h> </e>
860 ;
861 ;<e>Configure External Bus Behaviour for CS2 Area
862 ; =============================================
863 ;
864 ; --- Set CONFIG_CS2 = 1 to initialize the ADDRSEL2/FCONCS2/TCONCS2 registers
865 $SET (CONFIG_CS2 = 0) ; /Dave/
866 ;
867 ; <h>Definitions for Address Select register ADDRSEL2
868 ; ===================================================
869 ; <o> CS2 Start Address <0x0-0xFFFFFF:0x1000>
0000 870 _ADDR2 EQU 0x0 ; Set CS2# Start Address (default 100000H) /Dave/
871
872 ; <o> CS2 Size in KB
873 ; <4=> 4KB <8=> 8KB <16=> 16KB <32=> 32KB
874 ; <64=> 64KB <128=> 128KB <256=> 256KB <512=> 512KB
875 ; <1024=> 1024KB <2048=> 2048KB <4096=> 4096KB <8192=> 8192KB
1000 876 _SIZE2 EQU 4*KB ; Set CS2# Size (default 1024*KB = 1*MB) /Dave/