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SCS.LST
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C166 COMPILER V7.00, SCS 03/15/2019 15:27:40 PAGE 1
C166 COMPILER V7.00, COMPILATION OF MODULE SCS
OBJECT MODULE PLACED IN SCS.OBJ
COMPILER INVOKED BY: F:\Softeware\Fury\Keil\C166\BIN\C166.EXE SCS.C MODV2 BROWSE MODV2 DEBUG
stmt lvl source
1 //****************************************************************************
2 // @Module Project Settings
3 // @Filename SCS.C
4 // @Project test3.dav
5 //----------------------------------------------------------------------------
6 // @Controller Infineon XC2267M-104F80
7 //
8 // @Compiler Keil
9 //
10 // @Codegenerator 2.0
11 //
12 // @Description This file contains the SCS driver.
13 //
14 // Note:
15 // This file should not be changed by
16 // the user.
17 //
18 //----------------------------------------------------------------------------
19 // @Date 2018/11/1 16:59:43
20 //
21 //****************************************************************************
22
23 // USER CODE BEGIN (SCS_General,1)
24
25 // USER CODE END
26
27
28
29 //****************************************************************************
30 // @Project Includes
31 //****************************************************************************
32
33 #include "MAIN.H"
34
35 // USER CODE BEGIN (SCS_General,2)
36
37 // USER CODE END
38
39
40 //****************************************************************************
41 // @Macros
42 //****************************************************************************
43
44
45 //****************************************************************************
46 // @Defines
47 //****************************************************************************
48
49 // USER CODE BEGIN (SCS_General,3)
50
51 // USER CODE END
52
53
54 // Function-like macros ******************************************************
55
C166 COMPILER V7.00, SCS 03/15/2019 15:27:40 PAGE 2
56 // PLLSTAT_COND_3: For polling a PLLSTAT condition up to 3 times; an "if"
57 // construct needs at least 12 instruction cycles before 3rd check. "
58 // Depending on the compiler (optimization) and the program location, the
59 // effective number of instruction cycles may be higher.
60 #define PLLSTAT_COND_3(Condition) (((Condition) && (Condition)) && (Condition))
61
62 // GET_CYCLES: Converts Time[us] and MaxSysFreq[Hz] into cycles for timer,
63 // rounding up; for compile-time use only.
64 #define GET_CYCLES(Time, MaxSysFreq) \
65 ((unsigned int)(((((long)(Time))*((MaxSysFreq)/1000))+15999)/16000))
66
67 // Constants that may be overwritten by the user *****************************
68
69 // If not user defined:
70 // Number of attempts for high precision osc. start
71 #ifndef SCS_ATTEMPTS_OSC_HP
72 #define SCS_ATTEMPTS_OSC_HP 10
73 #endif
74
75 // If not user defined:
76 // Timeout in [us] for PLLV after high precision osc. start
77 #ifndef SCS_TIME_OSC_HP_PLLV
78 #define SCS_TIME_OSC_HP_PLLV 5000
79 #endif
80
81 // If not user defined:
82 // Delay time/timeout in [us] for 1024 cycles after high precision osc. start
83 #ifndef SCS_TIME_OSC_HP_1024
84 #define SCS_TIME_OSC_HP_1024 1000
85 #endif
86
87 // Constants that cannot be overwritten by the user **************************
88
89 // Maximum system frequency values in [Hz]
90 #define SCS_F_INT_5MHZ 5200000
91 #define SCS_F_INT_10MHZ 10400000
92
93 // Other times in [us]
94 #define SCS_TIME_VCO_BAND_SWITCH 150
95 #define SCS_TIME_VCO_FINDIS_TO_BASE 50
96 #define SCS_TIME_VCO_K2 5
97 #define SCS_TIME_VCO_LOCK 200
98
99 // Check clock parameters ****************************************************
100
101 // Check fXTAL
102 #if SCS_F_XTAL < 4000000 || SCS_F_XTAL > 25000000
# error "SCS_F_XTAL out of range"
#endif
105
106 // Check fPLL target frequency
107 #if SCS_F_PLL_TARGET < 1000000 || SCS_F_PLL_TARGET > 80000000
# error "SCS_F_PLL_TARGET out of range"
#endif
110
111 // check fP
112 #if SCS_F_P < 4000000 || SCS_F_P > 16000000
# error "SCS_F_P out of range"
#endif
115
116 // check fVCO
117 #if SCS_F_VCO < 10000000 || SCS_F_VCO > 160000000
C166 COMPILER V7.00, SCS 03/15/2019 15:27:40 PAGE 3
# error "SCS_F_VCO out of range"
#endif
120
121 // Check P divider
122 #if SCS_P < 1 || SCS_P > 16
# error "SCS_P out of range"
#endif
125
126 // Check N divider
127 #if SCS_N < 16 || SCS_N > 40
# error "SCS_N out of range"
#endif
130
131 // Check K2_5MHZ divider
132 #if SCS_K2_5MHZ < 1 || SCS_K2_5MHZ > 512
# error "SCS_K2_5MHZ out of range"
#endif
135
136 // Check K2 divider and additional K2 divider steps if defined
137
138 #if SCS_K2 < 1 || SCS_K2 > 512
# error "SCS_K2 out of range"
#endif
141
142 #ifdef SCS_K2_1
143 # if SCS_K2_1 < 1 || SCS_K2_1 > 512
# error "SCS_K2_1 out of range"
# endif
146 #endif
147
148 #ifdef SCS_K2_2
149 # if SCS_K2_2 < 1 || SCS_K2_2 > 512
# error "SCS_K2_2 out of range"
# endif
152 #endif
153
154 #ifdef SCS_K2_3
155 # if SCS_K2_3 < 1 || SCS_K2_3 > 512
# error "SCS_K2_3 out of range"
# endif
158 #endif
159
160 #ifdef SCS_K2_4
# if SCS_K2_4 < 1 || SCS_K2_4 > 512
# error "SCS_K2_4 out of range"
# endif
#endif
165
166
167
168 //****************************************************************************
169 // @Typedefs
170 //****************************************************************************
171
172
173
174 //****************************************************************************
175 // @Imported Global Variables
176 //****************************************************************************
177
178
179
C166 COMPILER V7.00, SCS 03/15/2019 15:27:40 PAGE 4
180 //****************************************************************************
181 // @Global Variables
182 //****************************************************************************
183
184
185
186 //****************************************************************************
187 // @Privare Variables
188 //****************************************************************************
189
190 // Saved value of CCU60_KSCFG
191 static unsigned int Ccu60KscfgSave;
192
193 // Saved value of CCU60 MCFG
194 static unsigned int Ccu60McfgSave;
195
196 // Saved value of CCU60 TCTR0
197 static unsigned int Ccu60Tctr0Save;
198
199 // Saved value of CCU60 TCTR2
200 static unsigned int Ccu60Tctr2Save;
201
202 // Saved value of CCU60 PISELH
203 static unsigned int Ccu60PiselhSave;
204
205
206
207 //****************************************************************************
208 // @External Prototypes
209 //****************************************************************************
210
211
212
213 //****************************************************************************
214 // @Prototypes Of Local Functions
215 //****************************************************************************
216
217 static SCS_ErrorType SCS_RampUpPllInNormalMode(void);
218
219
220 //****************************************************************************
221 // @Local Functions
222 //****************************************************************************
223
224 //****************************************************************************;
225 // @Function inline void SCS_EnableOscHiPrecCrystal(void)
226 //
227 //-----------------------------------------------------------------------------
228 // @Description This expert level function configures the high precision
229 // oscillator for crystal mode.
230 //
231 // Notes:
232 // - The user is responsible for disabling the register
233 // protection.
234 //
235 //-----------------------------------------------------------------------------
236 // @Returnvalue None
237 //
238 //-----------------------------------------------------------------------------
239 // @Parameters None
240 //
241 //-----------------------------------------------------------------------------
C166 COMPILER V7.00, SCS 03/15/2019 15:27:40 PAGE 5
242 // @Date 2018/11/1
243 //
244 //-----------------------------------------------------------------------------
245
246 // USER CODE BEGIN (SCS_EnableOscHiPrecCrystal,1)
247
248 // USER CODE END
249
250 _inline void SCS_EnableOscHiPrecCrystal(void)
251 {
252 1 // clear MODE for external crystal/clock, clear SHBY to disable shaper bypass,
253 1 // clear rh and w bits, leave other bits unchanged
254 1 SCU_HPOSCCON &=
255 1 ((0U <<0U) | // PLLV for PLL Valid Status Bit (rh)
256 1 // 0: OSC_HP frequency is not usable
257 1 // 1: OSC_HP frequency is usable
258 1 (0U <<1U) | // OSCWDTRST Oscillator Watchdog Reset
259 1 // 0 : Osc. watchdog is not reset and remains active
260 1 // 1 : Osc. watchdog is reset and restarted
261 1 (0U <<2U) | // MODE Oscillator Mode
262 1 // 0 : External crystal/clock, no osc. power-saving mode
263 1 // 1 : OSC_HP disabled, no osc. power-saving mode
264 1 // 2 : External clock, osc. power-saving mode
265 1 // 3 : OSC_HP disabled, osc. power-saving mode
266 1 (0U <<4U) | // GAINSEL Oscillator Gain Selection (rh)
267 1 // 0: gain control from 4 MHz to 8 MHz
268 1 // 1: gain control from 4 MHz to 16 MHz
269 1 // 2: gain control from 4 MHz to 20 MHz
270 1 // 3: gain control from 4 MHz to 25 MHz
271 1 (0U <<6U) | // X1D XTAL1 Data Value (rh)
272 1 // inverted level of pin XTAL1 if X1DEN is set
273 1 (1U <<7U) | // X1DEN XTAL1 Data Enable
274 1 // 0 : 0 Bit X1D is not updated
275 1 // 1 : 1 Bit X1D can be updated
276 1 (0U <<8U) | // SHBY Shaper Bypass
277 1 // 0 : 0 Shaper is not bypassed
278 1 // 1 : 1 Shaper is bypassed
279 1 (1U <<9U) | // EMCLKEN OSCWDT Emergency System Clock Source Select Enable
280 1 // 0 : MCM controlled by SYSCON0.CLKSEL in OSCWDT emergency case
281 1 // 1 : MCM controlled by SYSCON0.EMCLKSEL in OSCWDT emergency case
282 1 (1U <<10U)| // EMFINDISEN Emergency Input Clock Disconnect Enable
283 1 // 0 : PLLSTAT.FINDIS not updated in OSCWDT emergency case
284 1 // 1 : PLLSTAT.FINDIS is set in OSCWDT emergency case
285 1 (0U <<11U)| // OSC2L1 OSCWDT Reached Status (rh)
286 1 // 0: OSCWDT did not detect frequency below limit
287 1 // 1: OSCWDT detected frequency below limit
288 1 (0U <<12U));// OSC2L0 OSCWDT Left Status (rh)
289 1 // 0: OSCWDT did not detect frequency above limit
290 1 // 1: OSCWDT detected frequency above limit
291 1
292 1 } // end of function SCS_EnableOscHiPrecCrystal
293
294 //****************************************************************************;
295 // @Function inline void SCS_RestartVcoLockDetect(void)
296 //
297 //-----------------------------------------------------------------------------
298 // @Description This expert level function restarts the VCO lock detection.
299 //
300 // Notes:
301 // - The user is responsible for disabling the register
302 // protection.
303 //
C166 COMPILER V7.00, SCS 03/15/2019 15:27:40 PAGE 6
304 //-----------------------------------------------------------------------------
305 // @Returnvalue None
306 //
307 //-----------------------------------------------------------------------------
308 // @Parameters None
309 //
310 //-----------------------------------------------------------------------------
311 // @Date 2018/11/1
312 //
313 //-----------------------------------------------------------------------------
314
315 // USER CODE BEGIN (SCS_RestartVcoLockDetect,1)
316
317 // USER CODE END
318
319 _inline void SCS_RestartVcoLockDetect(void)
320 {
321 1 // restart VCO lock detection
322 1 SCU_PLLCON1_RESLD =
323 1 1U; // RESLD: Restart VCO Lock Detection (w)
324 1 // Setting this bit will reset bit PLLSTAT.VCOLOCK and
325 1 // restart the VCO lock detection
326 1
327 1 } // end of function SCS_RestartVcoLockDetect
328
329 //****************************************************************************;
330 // @Function inline void SCS_DisconnectVcoInput(void)
331 //
332 //-----------------------------------------------------------------------------
333 // @Description This expert level function disconnects VCO from its clock
334 // input.
335 //
336 // Notes:
337 // - The user is responsible for disabling the register
338 // protection.
339 //
340 //-----------------------------------------------------------------------------
341 // @Returnvalue None
342 //
343 //-----------------------------------------------------------------------------
344 // @Parameters None
345 //
346 //-----------------------------------------------------------------------------
347 // @Date 2018/11/1
348 //
349 //-----------------------------------------------------------------------------
350
351 // USER CODE BEGIN (SCS_DisconnectVcoInput,1)
352
353 // USER CODE END
354
355 _inline void SCS_DisconnectVcoInput(void)
356 {
357 1 // disconnect VCO from its clock input
358 1 SCU_STATCLR1 =
359 1 (0U <<0U) | // Clear PLLSTAT.VCOL0 (w)
360 1 (0U <<1U) | // Clear PLLSTAT.VCOL1 (w)
361 1 (0U <<2U) | // Clear HPOSCCON.OSC2L1 (w)
362 1 (0U <<3U) | // Clear HPOSCCON.OSC2L2 (w)
363 1 (1U <<4U) | // Set PLLSTAT.FINDIS (w)
364 1 (0U <<5U) ; // Clear PLLSTAT.FINDIS (w)
365 1
C166 COMPILER V7.00, SCS 03/15/2019 15:27:40 PAGE 7
366 1 } // end of function SCS_DisconnectVcoInput
367
368 //****************************************************************************;
369 // @Function inline void SCS_ConnectVcoInput(void)
370 //
371 //-----------------------------------------------------------------------------
372 // @Description This expert level function connects VCO from its clock
373 // input.
374 //
375 // Notes:
376 // - The user is responsible for disabling the register
377 // protection.
378 //
379 //-----------------------------------------------------------------------------
380 // @Returnvalue None
381 //
382 //-----------------------------------------------------------------------------
383 // @Parameters None
384 //
385 //-----------------------------------------------------------------------------
386 // @Date 2018/11/1
387 //
388 //-----------------------------------------------------------------------------
389
390 // USER CODE BEGIN (SCS_ConnectVcoInput,1)
391
392 // USER CODE END
393
394 _inline void SCS_ConnectVcoInput(void)
395 {
396 1 // connect VCO from its clock input
397 1 SCU_STATCLR1 =
398 1 (0U <<0U) | // Clear PLLSTAT.VCOL0 (w)
399 1 (0U <<1U) | // Clear PLLSTAT.VCOL1 (w)
400 1 (0U <<2U) | // Clear HPOSCCON.OSC2L1 (w)
401 1 (0U <<3U) | // Clear HPOSCCON.OSC2L2 (w)
402 1 (0U <<4U) | // Set PLLSTAT.FINDIS (w)
403 1 (1U <<5U) ; // Clear PLLSTAT.FINDIS (w)
404 1
405 1 } // end of function SCS_ConnectVcoInput
406
407 //****************************************************************************;
408 // @Function inline void SCS_SelectVcoBand(unsigned int VcoBand)
409 //
410 //-----------------------------------------------------------------------------
411 // @Description This expert level function sets the required VCO band.
412 //
413 // Notes:
414 // - The user is responsible for disabling the register
415 // protection.
416 //
417 //-----------------------------------------------------------------------------
418 // @Returnvalue None
419 //
420 //-----------------------------------------------------------------------------
421 // @Parameters VcoBand: 0 or 1
422 //
423 //-----------------------------------------------------------------------------
424 // @Date 2018/11/1
425 //
426 //-----------------------------------------------------------------------------
427
C166 COMPILER V7.00, SCS 03/15/2019 15:27:40 PAGE 8
428 // USER CODE BEGIN (SCS_SelectVcoBand,1)
429
430 // USER CODE END
431
432 _inline void SCS_SelectVcoBand(unsigned int VcoBand)
433 {
434 1 // select VCO band
435 1 SCU_PLLCON0_VCOSEL = VcoBand;
436 1
437 1 } // end of function SCS_SelectVcoBand
438
439 //****************************************************************************;
440 // @Function inline void SCS_StartTimer(unsigned int Cycles)
441 //
442 //-----------------------------------------------------------------------------
443 // @Description This expert level function starts timer T13 for counting
444 // a certain number of clocks.
445 //
446 // Notes:
447 // - It is assumed that the timer is already initialized by
448 // SCS_InitTimer.
449 // - Cycles < 3 are set to 3 for hardware reasons.
450 //
451 //-----------------------------------------------------------------------------
452 // @Returnvalue None
453 //
454 //-----------------------------------------------------------------------------
455 // @Parameters Cycles: Number of T13 clocks to count, 0...65535
456 //
457 //-----------------------------------------------------------------------------
458 // @Date 2018/11/1
459 //
460 //-----------------------------------------------------------------------------
461
462 // USER CODE BEGIN (SCS_StartTimer,1)
463
464 // USER CODE END
465
466 _inline void SCS_StartTimer(unsigned int Cycles)
467 {
468 1 // stop T13 for security reasons, clear T13
469 1 CCU60_TCTR4 =
470 1 (0U <<0U) | // T12RR Timer 12 Run Reset (w)
471 1 (0U <<1U) | // T12RS Timer 12 Run Set (w)
472 1 (0U <<2U) | // T12RES Timer 12 Reset (w)
473 1 (0U <<3U) | // DTRES Dead-Time Counter Reset (w))
474 1 (0U <<5U) | // T12CNT Timer T12 Count Event if enabled (PISELH) (w)
475 1 (0U <<6U) | // T12STR Timer 12 Shadow Transfer Request (w)
476 1 (0U <<7U) | // T12STD Timer 12 Shadow Transfer Disable (w)
477 1 (1U <<8U) | // T13RR Timer 13 Run Reset (w)
478 1 (0U <<9U) | // T13RS Timer 13 Run Set (w)
479 1 (1U <<10U)| // T13RES Timer 13 Reset (w)
480 1 (0U <<13U)| // T13CNT Timer T13 Count Event if enabled (PISELH) (w)
481 1 (0U <<14U)| // T13STR Timer 13 Shadow Transfer Request (w)
482 1 (0U <<15U); // T13STD Timer 13 Shadow Transfer Disable (w)
483 1
484 1 // limit T13 period
485 1 if (Cycles < 3U)
486 1 {
487 2 Cycles = 3U;
488 2 }
489 1
C166 COMPILER V7.00, SCS 03/15/2019 15:27:40 PAGE 9
490 1 //set T13 period
491 1 CCU60_T13PR = Cycles - 2U;
492 1
493 1 // enable T13 shadow transfer for period setting
494 1 CCU60_TCTR4 =
495 1 (0U <<0U) | // T12RR Timer 12 Run Reset (w)
496 1 (0U <<1U) | // T12RS Timer 12 Run Set (w)
497 1 (0U <<2U) | // T12RES Timer 12 Reset (w)
498 1 (0U <<3U) | // DTRES Dead-Time Counter Reset (w))
499 1 (0U <<5U) | // T12CNT Timer T12 Count Event if enabled (PISELH) (w)
500 1 (0U <<6U) | // T12STR Timer 12 Shadow Transfer Request (w)
501 1 (0U <<7U) | // T12STD Timer 12 Shadow Transfer Disable (w)
502 1 (0U <<8U) | // T13RR Timer 13 Run Reset (w)
503 1 (0U <<9U) | // T13RS Timer 13 Run Set (w)
504 1 (0U <<10U)| // T13RES Timer 13 Reset (w)
505 1 (0U <<13U)| // T13CNT Timer T13 Count Event if enabled (PISELH) (w)
506 1 (1U <<14U)| // T13STR Timer 13 Shadow Transfer Request (w)
507 1 (0U <<15U); // T13STD Timer 13 Shadow Transfer Disable (w)
508 1
509 1 // start T13
510 1 CCU60_TCTR4 =
511 1 (0U <<0U) | // T12RR Timer 12 Run Reset (w)
512 1 (0U <<1U) | // T12RS Timer 12 Run Set (w)
513 1 (0U <<2U) | // T12RES Timer 12 Reset (w)
514 1 (0U <<3U) | // DTRES Dead-Time Counter Reset (w))
515 1 (0U <<5U) | // T12CNT Timer T12 Count Event if enabled (PISELH) (w)
516 1 (0U <<6U) | // T12STR Timer 12 Shadow Transfer Request (w)
517 1 (0U <<7U) | // T12STD Timer 12 Shadow Transfer Disable (w)
518 1 (0U <<8U) | // T13RR Timer 13 Run Reset (w)
519 1 (1U <<9U) | // T13RS Timer 13 Run Set (w)
520 1 (0U <<10U)| // T13RES Timer 13 Reset (w)
521 1 (0U <<13U)| // T13CNT Timer T13 Count Event if enabled (PISELH) (w)
522 1 (0U <<14U)| // T13STR Timer 13 Shadow Transfer Request (w)
523 1 (0U <<15U); // T13STD Timer 13 Shadow Transfer Disable (w)
524 1
525 1 } // end of function SCS_StartTimer
526
527 //****************************************************************************;
528 // @Function inline void SCS_DelayByTimer(unsigned int Cycles)
529 //
530 //-----------------------------------------------------------------------------
531 // @Description This expert level function starts timer T13 and waits until
532 // the specified number of clocks is counted.
533 //
534 // Notes:
535 // - It is assumed that the timer is already initialized by
536 // SCS_InitTimer.
537 // - Cycles < 3 are set to 3 for hardware reasons.
538 //
539 //-----------------------------------------------------------------------------
540 // @Returnvalue None
541 //
542 //-----------------------------------------------------------------------------
543 // @Parameters Cycles: Number of T13 clocks to count, 0...65535
544 //
545 //-----------------------------------------------------------------------------
546 // @Date 2018/11/1
547 //
548 //-----------------------------------------------------------------------------
549
550 // USER CODE BEGIN (SCS_DelayByTimer,1)
551
C166 COMPILER V7.00, SCS 03/15/2019 15:27:40 PAGE 10
552 // USER CODE END
553
554 _inline void SCS_DelayByTimer(unsigned int Cycles)
555 {
556 1 // start delay timer T13
557 1 SCS_StartTimer(Cycles);
558 1
559 1 // wait until delay time clocks are counted
560 1 do
561 1 {
562 2 }
563 1 while(CCU60_TCTR0_T13R);
564 1
565 1 } // end of function SCS_DelayByTimer
566
567
568 //****************************************************************************;
569 // @Function SCS_ErrorType SCS_RampUpPllInNormalMode (void)
570 //
571 //-----------------------------------------------------------------------------
572 // @Description This private function performs a ramp-up of the PLL in
573 // Normal Operation Mode.
574 //
575 // Notes:
576 // - The user is responsible for disabling the register
577 // protection.
578 //-----------------------------------------------------------------------------
579 // @Returnvalue Error code
580 //
581 //-----------------------------------------------------------------------------
582 // @Parameters None
583 //
584 //-----------------------------------------------------------------------------
585 // @Date 2018/11/1
586 //
587 //-----------------------------------------------------------------------------
588
589 // USER CODE BEGIN (SCS_RampUpPllInNormalMode,1)
590
591 // USER CODE END
592
593
594 static SCS_ErrorType SCS_RampUpPllInNormalMode(void)
595 {
596 1 SCS_ErrorType Error;
597 1
598 1 #ifdef SCS_K2_1
599 1 // set additional K2 divider step SCS_K2_1 if needed
600 1 Error = SCS_ApplyNewK2Div(((unsigned int)SCS_K2_1) - 1U);
601 1 if(Error)
602 1 {
603 2 return Error;
604 2 }
605 1
606 1 #ifdef SCS_K2_2
607 1 // wait delay time for K2 with new system clock
608 1 SCS_DelayByTimer(GET_CYCLES(SCS_TIME_VCO_K2, SCS_F_VCO/SCS_K2_1));
609 1
610 1 // set additional K2 divider step SCS_K2_2 if needed
611 1 Error = SCS_ApplyNewK2Div(((unsigned int)SCS_K2_2) - 1U);
612 1 if(Error)
613 1 {
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614 2 return Error;
615 2 }
616 1
617 1 #ifdef SCS_K2_3
618 1 // wait delay time for K2 switch with new system clock
619 1 SCS_DelayByTimer(GET_CYCLES(SCS_TIME_VCO_K2, SCS_F_VCO/SCS_K2_2));
620 1
621 1 // set additional K2 divider step SCS_K2_3 if needed
622 1 Error = SCS_ApplyNewK2Div((((unsigned int)SCS_K2_3)) - 1U);
623 1 if(Error)
624 1 {
625 2 return Error;
626 2 }
627 1 // wait delay time for K2_3 with new system clock
628 1 SCS_DelayByTimer(GET_CYCLES(SCS_TIME_VCO_K2, SCS_F_VCO/SCS_K2_3));
629 1 #else
// no SCS_K2_3: wait delay time for K2_2 with new system clock
SCS_DelayByTimer(GET_CYCLES(SCS_TIME_VCO_K2, SCS_F_VCO/SCS_K2_2));
#endif // SCS_K2_3
633 1
634 1 #else
// no SCS_K2_2: wait delay time for K2_1 with new system clock
SCS_DelayByTimer(GET_CYCLES(SCS_TIME_VCO_K2, SCS_F_VCO/SCS_K2_1));
#endif // SCS_K2_2
638 1
639 1 #endif // SCS_K2_1
640 1
641 1 // set final K2 divider SCS_K2
642 1 Error = SCS_ApplyNewK2Div((((unsigned int)SCS_K2)) - 1U);
643 1 if(Error)
644 1 {
645 2 return Error;
646 2 }
647 1
648 1 // no error
649 1 return SCS_STATE_NO_ERROR;
650 1
651 1 } // end of function SCS_RampUpPllInNormalMode
652
653
654 //****************************************************************************;
655 // @Function SCS_ErrorType SCS_GoFromBaseToNormalMode (void)
656 //
657 //-----------------------------------------------------------------------------
658 // @Description This use case function performs a transition from Base Mode
659 // to Normal Operation Mode.
660 //
661 // Notes:
662 // - The user is responsible for disabling the register
663 // protection.
664 //-----------------------------------------------------------------------------
665 // @Returnvalue Error code
666 //
667 //-----------------------------------------------------------------------------
668 // @Parameters None
669 //
670 //-----------------------------------------------------------------------------
671 // @Date 2018/11/1
672 //
673 //-----------------------------------------------------------------------------
674
675 // USER CODE BEGIN (SCS_GoFromBaseToNormalMode,1)
C166 COMPILER V7.00, SCS 03/15/2019 15:27:40 PAGE 12
676
677 // USER CODE END
678
679
680 SCS_ErrorType SCS_GoFromBaseToNormalMode(void)
681 {
682 1 SCS_ErrorType Error;
683 1
684 1 // enable high precision oscillator for crystal
685 1 SCS_EnableOscHiPrecCrystal();
686 1
687 1 // check high precision oscillator frequency
688 1 Error = SCS_CheckFreqOscHiPrec();
689 1 if(Error)
690 1 {
691 2 return Error;
692 2 }
693 1
694 1 // set K1 divider = 1 for VCO bypass frequency of 5 MHz
695 1 Error = SCS_ApplyNewK1Div(1U - 1U);
696 1 if(Error)
697 1 {
698 2 return Error;
699 2 }
700 1
701 1 // enable VCO bypass, new fSYS = 5 MHz
702 1 Error = SCS_EnableVcoBypass();
703 1 if(Error)
704 1 {
705 2 return Error;
706 2 }
707 1
708 1 if(!SCU_PLLCON0_VCOSEL)
709 1 { // current VCO band = 0:
710 2
711 2 // select VCO band 1
712 2 SCS_SelectVcoBand(1U);
713 2
714 2 // wait band switch delay time with 5 MHz int. osc.
715 2 SCS_DelayByTimer(GET_CYCLES(SCS_TIME_VCO_BAND_SWITCH, SCS_F_INT_5MHZ));
716 2 }
717 1 else
718 1 { // current VCO band = 1:
719 2
720 2 // set K2 divider = 8
721 2 Error = SCS_ApplyNewK2Div(8U - 1U);
722 2 if(Error)
723 2 {
724 3 return Error;
725 3 }
726 2 }
727 1
728 1 // set final P divider
729 1 Error = SCS_ApplyNewPDiv((((unsigned int)SCS_P)) - 1U);
730 1 if(Error)
731 1 {
732 2 return Error;
733 2 }
734 1
735 1 // set final N divider
736 1 Error = SCS_ApplyNewNDiv((((unsigned int)SCS_N)) - 1U);
737 1 if(Error)
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738 1 {
739 2 return Error;
740 2 }
741 1
742 1 // disconnect VCO from clock input (enable free-running oscillator)
743 1 SCS_DisconnectVcoInput();
744 1
745 1 // wait until base frequency is reached with 10 MHz int. osc.
746 1 SCS_DelayByTimer(GET_CYCLES(SCS_TIME_VCO_FINDIS_TO_BASE, SCS_F_INT_10MHZ));
747 1
748 1 // disable VCO bypass, new fSYS ~ (50 MHz / 8) ~ 6.3 MHz
749 1 Error = SCS_DisableVcoBypass();
750 1 if(Error)
751 1 {
752 2 return Error;
753 2 }
754 1
755 1 // select high precision oscillator as VCO source
756 1 Error = SCS_SelectVcoSrcOscHiPrec();
757 1 if(Error)
758 1 {
759 2 return Error;
760 2 }
761 1
762 1 // set K2 for fSYS = 5 MHz with final settings, new fSYS ~ (50 MHz / K2)
763 1 // for fVCO = 160 MHz: K2 = 32, new fSYS ~ 1.6 MHz
764 1 Error = SCS_ApplyNewK2Div(((unsigned int)SCS_K2_5MHZ) - 1U);
765 1 if(Error)
766 1 {
767 2 return Error;
768 2 }
769 1
770 1 // connect VCO to clock input, new fSYS ~ 5MHz
771 1 SCS_ConnectVcoInput();
772 1
773 1 // restart VCO lock detection
774 1 SCS_RestartVcoLockDetect();
775 1
776 1 // start timer for VCO lock with maximum ~ 5 MHz
777 1 SCS_StartTimer(GET_CYCLES(SCS_TIME_VCO_LOCK, SCS_F_INT_5MHZ));
778 1
779 1 // wait until lock occurs or timeout is over
780 1 do
781 1 {
782 2 }
783 1 while((!SCU_PLLSTAT_VCOLOCK) && CCU60_TCTR0_T13R);
784 1 if(!SCU_PLLSTAT_VCOLOCK)
785 1 {
786 2 // no VCO lock
787 2 return SCS_STATE_TO_VCO_LOCK;
788 2 }
789 1
790 1 // enable VCOLCK emergency
791 1 Error = SCS_EnableVcoLockEmerg();
792 1 if(Error)
793 1 {
794 2 return Error;
795 2 }
796 1
797 1 // ramp up PLL for fSys = final value in normal operation mode
798 1 Error = SCS_RampUpPllInNormalMode();
799 1 if(Error)
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800 1 {
801 2 return Error;
802 2 }
803 1
804 1 // no error
805 1 return SCS_STATE_NO_ERROR;
806 1
807 1 } // end of function SCS_GoFromBaseToNormalMode
808
809
810 //****************************************************************************;
811 // @Function void SCS_InitTimer (void)
812 //-----------------------------------------------------------------------------
813 // @Description This function configures CCU6 timer T13 as one-shot timer with
814 // a resolution of 16 CCU6 clocks = 16 system clocks.
815 //
816 // Notes:
817 // - The function will enable CCU6 and will overwrite previous
818 // settings for T13.
819 // - The function will save the previous CCU6 register contents;
820 // they may be restored via SCS_RestoreTimer.
821 // - The user must call this function before any other SCS driver
822 // function. (except SCS_SelectBandgapHiPrec if needed).
823 // - The user is responsible for disabling the register protection.
824 //
825 //-----------------------------------------------------------------------------
826 // @Returnvalue None
827 //
828 //-----------------------------------------------------------------------------
829 // @Parameters None
830 //
831 //-----------------------------------------------------------------------------
832 // @Date 2018/11/1
833 //
834 //-----------------------------------------------------------------------------
835
836 // USER CODE BEGIN (SCS_InitTimer,1)
837
838 // USER CODE END
839
840 void SCS_InitTimer(void)
841 {
842 1 volatile unsigned int Work;
843 1
844 1 // save CCU60_KSCFG
845 1 Ccu60KscfgSave = CCU60_KSCFG;
846 1
847 1 // enable CC60 module
848 1 CCU60_KSCFG |=
849 1 (1U <<0U) | // MODEN Module Enable
850 1 (1U <<1U) | // BPMODEN Bit Protection for MODEN, set to 1 for change (w)
851 1 (0U <<4U) | // NOMCFG Normal Operation Mode Configuration
852 1 // kernel mode applied in normal operation mode
853 1 (0U <<7U) | // BPNOM Bit Protection for NOMCFG, set to 1 for change (w)
854 1 (0U <<8U) | // SUMCFG Suspend Mode Configuration
855 1 // Kernel mode applied in suspend mode
856 1 (0U <<11U)| // BPSUM Bit Protection for SUMCFG, set to 1 for change (w)
857 1 (0U <<12U)| // COMCFG Clock Off Mode Configuration
858 1 // kernel mode applied in clock off mode
859 1 (0U <<15U); // BPCOM Bit Protection for COMCFG, set to 1 for change (w)
860 1
861 1 // read SFR back to avoid pipeline effects
C166 COMPILER V7.00, SCS 03/15/2019 15:27:40 PAGE 15
862 1 Work = CCU60_KSCFG;
863 1
864 1 // save CCU60_MCFG
865 1 Ccu60McfgSave = CCU60_MCFG;
866 1
867 1 // enable T13 functionality, leave other bits unchanged
868 1 CCU60_MCFG |=
869 1 (0U <<0U) | // T12 T12 Available
870 1 (1U <<1U) | // T13 T13 Available
871 1 (0U <<2U); // MCM Multi-Channel Mode Available
872 1
873 1 // stop T13, clear T13
874 1 // (CCU60_TCTR4 needs not be saved)
875 1 CCU60_TCTR4 =
876 1 (0U <<0U) | // T12RR Timer 12 Run Reset (w)
877 1 (0U <<1U) | // T12RS Timer 12 Run Set (w)
878 1 (0U <<2U) | // T12RES Timer 12 Reset (w)
879 1 (0U <<3U) | // DTRES Dead-Time Counter Reset (w)
880 1 (0U <<5U) | // T12CNT Timer T12 Count Event if enabled (PISELH) (w)
881 1 (0U <<6U) | // T12STR Timer 12 Shadow Transfer Request (w)
882 1 (0U <<7U) | // T12STD Timer 12 Shadow Transfer Disable (w)
883 1 (1U <<8U) | // T13RR Timer 13 Run Reset (w)
884 1 (0U <<9U) | // T13RS Timer 13 Run Set (w)
885 1 (1U <<10U)| // T13RES Timer 13 Reset (w)
886 1 (0U <<13U)| // T13CNT Timer T13 Count Event if enabled (PISELH) (w)
887 1 (0U <<14U)| // T13STR Timer 13 Shadow Transfer Request (w)
888 1 (0U <<15U); // T13STD Timer 13 Shadow Transfer Disable (w)
889 1
890 1 // save CCU60_TCTR0
891 1 Ccu60Tctr0Save = CCU60_TCTR0;
892 1
893 1 // set T13 period, for fCC6/16, clear T13PRE to disable additional prescaler,
894 1 // leave bits T12CLK, T12PRE, CTM unchanged
895 1 CCU60_TCTR0 = (CCU60_TCTR0 & ((7U <<0U)|(1U <<3U)|(1U <<7U))) |
896 1 ((0U <<0U) | // T12CLK Timer T12 Input Clock Select
897 1 // 0: f = fCC6
898 1 // 1: f = fCC6 / 2
899 1 // 2: f = fCC6 / 4
900 1 // 3: f = fCC6 / 8
901 1 // 4: f = fCC6 / 16
902 1 // 5: f = fCC6 / 32
903 1 // 6: f = fCC6 / 64
904 1 // 7: f = fCC6 / 128
905 1 (0U <<3U) | // T12PRE Timer T12 Prescaler Bit
906 1 // 0: additional prescaler disabled
907 1 // 1: additional prescaler enabled
908 1 (0U <<4U) | // T12R Timer T12 Run Bit (rh)
909 1 // 0: Timer is stopped
910 1 // 1: Timer is running
911 1 (0U <<5U) | // STE12 Timer T12 Shadow Transfer Enable (rh)
912 1 // 0: Shadow register transfer is disabled
913 1 // 1: Shadow register transfer is enabled
914 1 (0U <<6U) | // CDIR Count Direction of Timer T12 (rh)
915 1 // 0: T12 counts up
916 1 // 1: T12 counts down
917 1 (0U <<7U) | // CTM T12 Operating Mode
918 1 // 0: Edge-aligned Mode
919 1 // 1: Center-aligned Mode
920 1 (4U <<8U) | // T13CLK Timer T13 Input Clock Select
921 1 // 0: f = fCC6
922 1 // 1: f = fCC6 / 2
923 1 // 2: f = fCC6 / 4
C166 COMPILER V7.00, SCS 03/15/2019 15:27:40 PAGE 16
924 1 // 3: f = fCC6 / 8
925 1 // 4: f = fCC6 / 16
926 1 // 5: f = fCC6 / 32
927 1 // 6: f = fCC6 / 64
928 1 // 7: f = fCC6 / 128
929 1 (0U <<11U)| // T13PRE Timer T13 Prescaler Bit
930 1 // 0: additional prescaler disabled
931 1 // 1: additional prescaler enabled
932 1 (0U <<12U)| // T13R Timer T13 Run Bit (rh)
933 1 // 0: Timer is stopped
934 1 // 1: Timer is running
935 1 (0U <<13U));// STE13 Timer T13 Shadow Transfer Enable (rh)
936 1 // 0: Shadow register transfer is disabled
937 1 // 1: Shadow register transfer is enabled
938 1
939 1 // save CCU60_TCTR2
940 1 Ccu60Tctr2Save = CCU60_TCTR2;
941 1
942 1 // enable T13 single-shot, clear other T13 bits,
943 1 // leave bits T12SSC and T12RSEL unchanged
944 1 CCU60_TCTR2 = (CCU60_TCTR2 & ((1U <<0U)|(3U <<8U))) |
945 1 ((0U <<0U) | // T12SSC T12 Single Shot Control
946 1 (1U <<1U) | // T13SSC T13 Single Shot Control
947 1 (0U <<2U) | // T13TEC T13 Trigger Event Control to start T13
948 1 // 0: No action
949 1 // 1: T13R set on T12 compare event on channel 0
950 1 // 2: T13R set on T12 compare event on channel 1
951 1 // 3: T13R set on T12 compare event on channel 2
952 1 // 4: T13R set on any T12 compare event (ch. 0, 1, 2)
953 1 // 5: T13R set on period-match of T12
954 1 // 6: T13R set on zero-match of T12 (while counting up)
955 1 // 7: Any edge of inputs CCPOSx
956 1 (0U <<5U) | // T13TED T13 Trigger Event Direction for T13TEC trigger
957 1 // 0: Reserved, no action
958 1 // 1: While T12 is counting up
959 1 // 2: While T12 is counting down
960 1 // 3: Independent on the count direction of T12
961 1 (0U <<8U) | // T12RSEL T12 External Run Selection