forked from ShervinAmbrose/FloatingPointAddition
-
Notifications
You must be signed in to change notification settings - Fork 0
/
FinalProject.v.bak
258 lines (251 loc) · 7.05 KB
/
FinalProject.v.bak
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:16:57 03/14/2017
// Design Name:
// Module Name: DIgitalClock
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FinalProject(input M_CLOCK, // FPGA clock
input Row1,Row2,Row3,Row4,
output reg Column1,Column2,Column3,Column4,
input [3:0] IO_PB,
output [3:0] F_LED, // FPGA LEDs
output [7:0] IO_LED, // IO Board LEDs
output reg [3:0] IO_SSEGD, // IO Board Seven Segment Digits
output reg [7:0] IO_SSEG, // 7=dp, 6=g, 5=f,4=e, 3=d,2=c,1=b, 0=a
output IO_SSEG_COL,
output DEC_POINT);
assign IO_SSEG_COL = 1; // deactivate the colon displays
assign F_LED = ~IO_PB;
assign DEC_POINT = 1'b1;
assign IO_LED = 8'b00000000;
wire FlagCheck = 1'b0;
reg [7:0] AllPins;
reg [31:0] ColumnCounter = 0;
reg [31:0] DisplayCounter = 0;
reg [1:0] ColumnState = 0;
reg Columns = 0;
reg DisplayResults = 0;
reg FLAGG = 1'b0;
reg checkflag = 1'b0;
reg [7:0] SEG1;
//**************CLOCK RATE***************************//
always @(posedge M_CLOCK) begin
ColumnCounter <= ColumnCounter + 1;
DisplayCounter <= DisplayCounter + 1;
if (ColumnCounter == 1850000) begin //22000 208000
Columns <= ~Columns;
ColumnCounter <= 0;
end
if (DisplayCounter == 125000) begin //34500000
DisplayResults <= ~DisplayResults;
DisplayCounter <= 0;
end
end
//***************************************************//
//***************Going Through Columns**************//
always @(posedge Columns) begin // THE SEGMENTS
case(ColumnState)
0: begin
{Column1,Column2,Column3,Column4} <= 4'b1000;
case ({Row1,Row2,Row3,Row4})
4'b1000: begin
AllPins <= ({Row1,Row2,Row3,Row4,Column1,Column2,Column3,Column4});
FLAGG <= 1'b1;
checkflag = 1'b1;
end
4'b0100: begin
AllPins <= ({Row1,Row2,Row3,Row4,Column1,Column2,Column3,Column4});
FLAGG <= 1'b1;
checkflag = 1'b1;
end
4'b0010: begin
AllPins <= ({Row1,Row2,Row3,Row4,Column1,Column2,Column3,Column4});
FLAGG <= 1'b1;
checkflag = 1'b1;
end
4'b0001: begin
AllPins <= ({Row1,Row2,Row3,Row4,Column1,Column2,Column3,Column4});
FLAGG <= 1'b1;
checkflag = 1'b1;
end
default: begin
FLAGG <= 1'b0;
ColumnState <= 1;
end
endcase
end
1: begin
{Column1,Column2,Column3,Column4} <= 4'b0100;
case ({Row1,Row2,Row3,Row4})
4'b1000: begin
AllPins <= ({Row1,Row2,Row3,Row4,Column1,Column2,Column3,Column4});
FLAGG <= 1'b1;
checkflag = 1'b1;
end
4'b0100: begin
AllPins <= ({Row1,Row2,Row3,Row4,Column1,Column2,Column3,Column4});
FLAGG <= 1'b1;
checkflag = 1'b1;
end
4'b0010: begin
AllPins <= ({Row1,Row2,Row3,Row4,Column1,Column2,Column3,Column4});
FLAGG <= 1'b1;
checkflag = 1'b1;
end
4'b0001: begin
AllPins <= ({Row1,Row2,Row3,Row4,Column1,Column2,Column3,Column4});
FLAGG <= 1'b1;
checkflag = 1'b1;
end
default: begin
FLAGG <= 1'b0;
ColumnState <= 2;
end
endcase
end
2: begin
{Column1,Column2,Column3,Column4} <= 4'b0010;
case ({Row1,Row2,Row3,Row4})
4'b1000: begin
AllPins <= ({Row1,Row2,Row3,Row4,Column1,Column2,Column3,Column4});
FLAGG <= 1'b1;
checkflag = 1'b1;
end
4'b0100: begin
AllPins <= ({Row1,Row2,Row3,Row4,Column1,Column2,Column3,Column4});
FLAGG <= 1'b1;
checkflag = 1'b1;
end
4'b0010: begin
AllPins <= ({Row1,Row2,Row3,Row4,Column1,Column2,Column3,Column4});
FLAGG <= 1'b1;
checkflag = 1'b1;
end
4'b0001: begin
AllPins <= ({Row1,Row2,Row3,Row4,Column1,Column2,Column3,Column4});
FLAGG <= 1'b1;
checkflag = 1'b1;
end
default: begin
FLAGG <= 1'b0;
ColumnState <= 3;
end
endcase
end
3: begin
{Column1,Column2,Column3,Column4} <= 4'b0001;
case ({Row1,Row2,Row3,Row4})
4'b1000: begin
AllPins <= ({Row1,Row2,Row3,Row4,Column1,Column2,Column3,Column4});
FLAGG <= 1'b1;
checkflag = 1'b1;
end
4'b0100: begin
AllPins <= ({Row1,Row2,Row3,Row4,Column1,Column2,Column3,Column4});
FLAGG <= 1'b1;
checkflag = 1'b1;
end
4'b0010: begin
AllPins <= ({Row1,Row2,Row3,Row4,Column1,Column2,Column3,Column4});
FLAGG <= 1'b1;
checkflag = 1'b1;
end
4'b0001: begin
AllPins <= ({Row1,Row2,Row3,Row4,Column1,Column2,Column3,Column4});
FLAGG <= 1'b1;
checkflag = 1'b1;
end
default: begin
FLAGG <= 1'b0;
ColumnState <= 0;
end
endcase
end
default: begin
ColumnState <= 0;
end
endcase
end
//***************************************************//
//******************Getting the Value Number********//
//***************************************************//
always @(FLAGG) begin
case (AllPins)
8'b10001000: begin // Row1 Column1
SEG1 <= {DEC_POINT, 7'b1111001}; //1
end
8'b10000100: begin //Row1 Column2
SEG1 <= {DEC_POINT, 7'b0100100}; //2
end
8'b10000010: begin //Row1 Column3
SEG1 <= {DEC_POINT, 7'b0110000}; //3
end
8'b10000001: begin //Row1 Column4
SEG1 <= {DEC_POINT, 7'b0001000}; //A
end
///
8'b01001000: begin // Row2 Column1
SEG1 <= {DEC_POINT, 7'b0011001}; //4
end
8'b01000100: begin //Row2 Column2
SEG1 <= {DEC_POINT, 7'b0010010}; //5
end
8'b01000010: begin //Row2 Column3
SEG1 <= {DEC_POINT, 7'b0000010}; //6
end
8'b01000001: begin //Row2 Column4
SEG1 <= {DEC_POINT, 7'b0000011}; //b
end
///
8'b00101000: begin // Row3 Column1
SEG1 <= {DEC_POINT, 7'b1111000}; //7
end
8'b00100100: begin //Row3 Column2
SEG1 <= {DEC_POINT, 7'b0000000}; //8
end
8'b00100010: begin //Row3 Column3
SEG1 <= {DEC_POINT, 7'b0011000}; //9
end
8'b00100001: begin //Row3 Column4
SEG1 <= {DEC_POINT, 7'b1000110}; //C
end
///
8'b00011000: begin // Row4 Column1
SEG1 <= {DEC_POINT, 7'b1000000}; //* = 0
end
8'b00010100: begin //Row4 Column2
SEG1 <= {DEC_POINT, 7'b1000000}; // 0
end
8'b00010010: begin //Row4 Column3
SEG1 <= {DEC_POINT, 7'b1000000}; //# = 0
end
8'b00010001: begin //Row4 Column4
SEG1 <= {DEC_POINT, 7'b0100001}; // d
end
default: begin
if (checkflag == 0)
SEG1 <= {DEC_POINT, 7'b00000000};
else
SEG1 <= SEG1;
end
endcase
end
always @(posedge DisplayResults) begin // THE SEGMENTS
IO_SSEGD <= 4'b0111;
IO_SSEG <= SEG1;
end
endmodule