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Significantly reworked design. Added simultaneous computing several hashes during POW operation. The number of POW computing cores determined by CALC_UNIT_NUMBER parameter in soc_top.v
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4 files changed

+254
-172
lines changed

4 files changed

+254
-172
lines changed

pow_accel_soc/hardware/LFSR27trit.v

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,8 @@ SOFTWARE.*/
2222

2323
module LFSR27trit(i_clk, i_arst_n, o_rnd_trits);
2424

25+
parameter UNIT_NUMBER = 0;
26+
2527
input i_clk;
2628
input i_arst_n;
2729
output reg [53:0] o_rnd_trits;
@@ -35,7 +37,7 @@ integer i = 0;
3537
always @(posedge i_clk, negedge i_arst_n) begin
3638

3739
if (~i_arst_n) begin
38-
lfsr <= '0;
40+
lfsr <= (1'b1 << 2*UNIT_NUMBER);
3941
end else begin
4042
lfsr <= {lfsr[52:0], lfsr_lsb};
4143
end

pow_accel_soc/hardware/curl_avalon.v

Lines changed: 15 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -43,6 +43,8 @@ module curl_avalon ( i_clk,
4343
i_master_readdata
4444
);
4545

46+
parameter CU_NUM = 10;
47+
4648
localparam MASTER_DATA_WIDTH = 128;
4749
localparam MASTER_BE_WIDTH = MASTER_DATA_WIDTH/8;
4850
localparam MASTER_ADDR_WIDTH = 28;
@@ -112,7 +114,8 @@ reg curl_transform_ff;
112114
reg curl_pow_ff;
113115
reg [31:0] curl_pow_mwm_mask;
114116
reg [53:0] curl_idata_ff;
115-
wire [53:0] curl_odata;
117+
wire [161:0] curl_nonce;
118+
reg [80:0][1:0] curl_nonce_trits;
116119
wire curl_otransforming;
117120
wire curl_pow_finish;
118121

@@ -138,7 +141,7 @@ reg arm_user_data_available;
138141
reg [2:0] state_ff;
139142

140143
reg [3:0] mem_trit_cnt_ff;
141-
reg [4:0] curl_trit_cnt_ff;
144+
reg [6:0] curl_trit_cnt_ff;
142145

143146
reg rw_master_ctrl;
144147

@@ -153,7 +156,8 @@ integer i;
153156

154157
assign o_finish_int = finish_ff;
155158

156-
curl_pow curl_pow_inst (.i_clk ( i_clk ),
159+
curl_pow #(.CU_NUM(CU_NUM))
160+
curl_pow_inst (.i_clk ( i_clk ),
157161
.i_arst_n ( curl_rst_n),
158162
.i_we ( curl_we_ff ),
159163
.i_addr ( curl_addr_ff ),
@@ -164,7 +168,7 @@ curl_pow curl_pow_inst (.i_clk ( i_clk ),
164168
.o_transforming ( curl_otransforming ),
165169
.o_pow_finish ( curl_pow_finish ),
166170
.o_pow_hash_finish( hash_cnt_en ),
167-
.o_data ( curl_odata )
171+
.o_data ( curl_nonce )
168172
);
169173

170174
write_master #( .DATAWIDTH ( MASTER_DATA_WIDTH ),
@@ -445,10 +449,8 @@ always @(posedge i_clk, posedge i_arst) begin
445449

446450
state_ff <= STORE_S;
447451
awm_control_go <= 1'b1;
448-
curl_addr_ff <= '0;
449452
curl_trit_cnt_ff <= '0;
450453
mem_trit_cnt_ff <= '0;
451-
trits_to_process <= 16'd81;
452454
rw_master_ctrl <= 1'b0;
453455
tick_cnt_en_ff <= 1'b0;
454456

@@ -460,28 +462,11 @@ always @(posedge i_clk, posedge i_arst) begin
460462

461463
if (!awm_user_buffer_full) begin
462464

463-
if (trits_to_process) begin
464-
465-
awm_user_buffer_data[8*mem_trit_cnt_ff +: 8] <= $signed(curl_odata[2*curl_trit_cnt_ff +: 2]);
466-
trits_to_process <= trits_to_process - 1'b1;
467-
468-
end else begin
469-
470-
awm_user_buffer_data[8*mem_trit_cnt_ff +: 8] <= '0;
471-
472-
end
473-
465+
awm_user_buffer_data[8*mem_trit_cnt_ff +: 8] <= $signed(curl_nonce_trits[curl_trit_cnt_ff]);
466+
474467
curl_trit_cnt_ff <= curl_trit_cnt_ff + 1'b1;
475468
mem_trit_cnt_ff <= mem_trit_cnt_ff + 1'b1;
476469

477-
478-
if (5'd26 == curl_trit_cnt_ff) begin
479-
480-
curl_trit_cnt_ff <= '0;
481-
curl_addr_ff <= curl_addr_ff + 1'b1;
482-
483-
end
484-
485470
if (4'd15 == mem_trit_cnt_ff) begin
486471

487472
awm_user_write_buffer <= 1'b1;
@@ -554,8 +539,12 @@ always @(posedge i_clk) begin
554539
if (rst_cnt_ff)
555540
hash_cnt <= '0;
556541
else if (hash_cnt_en)
557-
hash_cnt <= hash_cnt + 1'b1;
542+
hash_cnt <= hash_cnt + CU_NUM;
543+
544+
end
558545

546+
always @* begin
547+
curl_nonce_trits = curl_nonce;
559548
end
560549

561550
endmodule

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