forked from cseagle/sk3wldbg
-
Notifications
You must be signed in to change notification settings - Fork 0
/
sk3wldbg_sparc.cpp
133 lines (111 loc) · 5.66 KB
/
sk3wldbg_sparc.cpp
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
/*
Source for Sk3wlDbg IdaPro plugin
Copyright (c) 2016 Chris Eagle
This program is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the Free
Software Foundation; either version 2 of the License, or (at your option)
any later version.
This program is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
this program; if not, write to the Free Software Foundation, Inc., 59 Temple
Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include "sk3wldbg_sparc.h"
static const char *sparc_register_classes[] = {
"General registers",
NULL
};
enum SparcRegClass {
SPARC_GENERAL = 1
};
static const char* sparc_flags[] = {
"CWP", "CWP", "CWP", "CWP", "CWP", "ET", "PS", "S", "PIL", "PIL", "PIL", "PIL",
"EF", "EC", NULL, NULL, NULL, NULL, NULL, NULL, "C", "V", "Z", "N",
"VER", "VER", "VER", "VER", "IMPL", "IMPL", "IMPL", "IMPL"
};
static struct register_info_t sparc_regs[] = {
{"g0", 0, SPARC_GENERAL, dt_dword, NULL, 0},
{"g1", REGISTER_ADDRESS, SPARC_GENERAL, dt_dword, NULL, 0},
{"g2", REGISTER_ADDRESS, SPARC_GENERAL, dt_dword, NULL, 0},
{"g3", REGISTER_ADDRESS, SPARC_GENERAL, dt_dword, NULL, 0},
{"g4", REGISTER_ADDRESS, SPARC_GENERAL, dt_dword, NULL, 0},
{"g5", REGISTER_ADDRESS, SPARC_GENERAL, dt_dword, NULL, 0},
{"g6", REGISTER_ADDRESS, SPARC_GENERAL, dt_dword, NULL, 0},
{"g7", REGISTER_ADDRESS, SPARC_GENERAL, dt_dword, NULL, 0},
{"o0", REGISTER_ADDRESS, SPARC_GENERAL, dt_dword, NULL, 0},
{"o1", REGISTER_ADDRESS, SPARC_GENERAL, dt_dword, NULL, 0},
{"o2", REGISTER_ADDRESS, SPARC_GENERAL, dt_dword, NULL, 0},
{"o3", REGISTER_ADDRESS, SPARC_GENERAL, dt_dword, NULL, 0},
{"o4", REGISTER_ADDRESS, SPARC_GENERAL, dt_dword, NULL, 0},
{"o5", REGISTER_ADDRESS, SPARC_GENERAL, dt_dword, NULL, 0},
{"sp", REGISTER_ADDRESS | REGISTER_SP, SPARC_GENERAL, dt_dword, NULL, 0},
{"o7", REGISTER_ADDRESS, SPARC_GENERAL, dt_dword, NULL, 0},
{"l0", REGISTER_ADDRESS, SPARC_GENERAL, dt_dword, NULL, 0},
{"l1", REGISTER_ADDRESS, SPARC_GENERAL, dt_dword, NULL, 0},
{"l2", REGISTER_ADDRESS, SPARC_GENERAL, dt_dword, NULL, 0},
{"l3", REGISTER_ADDRESS, SPARC_GENERAL, dt_dword, NULL, 0},
{"l4", REGISTER_ADDRESS, SPARC_GENERAL, dt_dword, NULL, 0},
{"l5", REGISTER_ADDRESS, SPARC_GENERAL, dt_dword, NULL, 0},
{"l6", REGISTER_ADDRESS, SPARC_GENERAL, dt_dword, NULL, 0},
{"l7", REGISTER_ADDRESS, SPARC_GENERAL, dt_dword, NULL, 0},
{"i0", REGISTER_ADDRESS, SPARC_GENERAL, dt_dword, NULL, 0},
{"i1", REGISTER_ADDRESS, SPARC_GENERAL, dt_dword, NULL, 0},
{"i2", REGISTER_ADDRESS, SPARC_GENERAL, dt_dword, NULL, 0},
{"i3", REGISTER_ADDRESS, SPARC_GENERAL, dt_dword, NULL, 0},
{"i4", REGISTER_ADDRESS, SPARC_GENERAL, dt_dword, NULL, 0},
{"i5", REGISTER_ADDRESS, SPARC_GENERAL, dt_dword, NULL, 0},
{"fp", REGISTER_ADDRESS, SPARC_GENERAL, dt_dword, NULL, 0},
{"i7", REGISTER_ADDRESS, SPARC_GENERAL, dt_dword, NULL, 0},
{"PC", REGISTER_ADDRESS | REGISTER_IP, SPARC_GENERAL, dt_dword, NULL, 0},
{"PSR", 0, SPARC_GENERAL, dt_dword, sparc_flags, 0xFFF03FFF},
};
#define SPARC_LR 15
static int32_t sparc_reg_map[] = {
UC_SPARC_REG_G0, UC_SPARC_REG_G1, UC_SPARC_REG_G2, UC_SPARC_REG_G3,
UC_SPARC_REG_G4, UC_SPARC_REG_G5, UC_SPARC_REG_G6, UC_SPARC_REG_G7,
UC_SPARC_REG_O0, UC_SPARC_REG_O1, UC_SPARC_REG_O2, UC_SPARC_REG_O3,
UC_SPARC_REG_O4, UC_SPARC_REG_O5, UC_SPARC_REG_SP, UC_SPARC_REG_O7,
UC_SPARC_REG_L0, UC_SPARC_REG_L1, UC_SPARC_REG_L2, UC_SPARC_REG_L3,
UC_SPARC_REG_L4, UC_SPARC_REG_L5, UC_SPARC_REG_L6, UC_SPARC_REG_L7,
UC_SPARC_REG_I0, UC_SPARC_REG_I1, UC_SPARC_REG_I2, UC_SPARC_REG_I3,
UC_SPARC_REG_I4, UC_SPARC_REG_I5, UC_SPARC_REG_FP, UC_SPARC_REG_I7,
UC_SPARC_REG_PC, UC_SPARC_REG_ICC
};
#define sparc64_reg_map sparc_reg_map
sk3wldbg_sparc::sk3wldbg_sparc() : sk3wldbg("sparcl", UC_ARCH_SPARC, UC_MODE_32) {
//reset any overridden function pointers and setup register name fields
if (debug_mode & UC_MODE_BIG_ENDIAN) {
processor = "sparcb";
}
register_classes = sparc_register_classes;
register_classes_default = SPARC_GENERAL; ///< Mask of default printed register classes
_registers = sparc_regs; ///< Array of registers. Use registers() to access it
registers_size = qnumber(sparc_regs); ///< Number of registers
reg_map = sparc_reg_map;
bpt_bytes = NULL; ///< Array of bytes for a breakpoint instruction
bpt_size = 0; ///< Size of this array
}
bool sk3wldbg_sparc::save_ret_addr(uint64_t retaddr) {
uc_reg_write(uc, reg_map[SPARC_LR], &retaddr);
return true;
}
sk3wldbg_sparc64::sk3wldbg_sparc64() : sk3wldbg("sparcl", UC_ARCH_SPARC, UC_MODE_64) {
//reset any overridden function pointers and setup register name fields
if (debug_mode & UC_MODE_BIG_ENDIAN) {
processor = "sparcb";
}
register_classes = sparc_register_classes;
register_classes_default = SPARC_GENERAL; ///< Mask of default printed register classes
_registers = sparc_regs; ///< Array of registers. Use registers() to access it
registers_size = qnumber(sparc_regs); ///< Number of registers
reg_map = sparc64_reg_map;
bpt_bytes = NULL; ///< Array of bytes for a breakpoint instruction
bpt_size = 0; ///< Size of this array
}
bool sk3wldbg_sparc64::save_ret_addr(uint64_t retaddr) {
uc_reg_write(uc, reg_map[SPARC_LR], &retaddr);
return true;
}