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FILD
FILD — Load Integer
| Opcode | Instruction | 64-Bit Mode | Compat/ Leg Mode | Description |
| DF /0 | FILD m16int | Valid | Valid | Push m16int onto the FPU register stack. |
| DB /0 | FILD m32int | Valid | Valid | Push m32int onto the FPU register stack. |
| DF /5 | FILD m64int | Valid | Valid | Push m64int onto the FPU register stack. |
Converts the signed-integer source operand into double extended-precision floating-point format and pushes the value onto the FPU register stack. The source operand can be a word, doubleword, or quadword integer. It is loaded without rounding errors. The sign of the source operand is preserved.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
TOP ← TOP − 1;
ST(0) ← ConvertToDoubleExtendedPrecisionFP(SRC);C1 Set to 1 if stack overflow occurred; set to 0 otherwise. C0, C2, C3 Undefined.
\#IS Stack overflow occurred.
\#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector.
\#SS(0) If a memory operand effective address is outside the SS segment limit.
\#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
\#PF(fault-code) If a page fault occurs.
\#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
\#UD If the LOCK prefix is used.
\#GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
\#SS If a memory operand effective address is outside the SS segment limit.
\#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
\#UD If the LOCK prefix is used.
\#GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
\#SS(0) If a memory operand effective address is outside the SS segment limit.
\#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
\#PF(fault-code) If a page fault occurs.
\#AC(0) If alignment checking is enabled and an unaligned memory reference is made.
\#UD If the LOCK prefix is used.
Same exceptions as in protected mode.
\#SS(0) If a memory address referencing the SS segment is in a non-canonical form.
\#GP(0) If the memory address is in a non-canonical form.
\#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
\#MF If there is a pending x87 FPU exception.
\#PF(fault-code) If a page fault occurs.
\#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
\#UD If the LOCK prefix is used.
Source: Intel Architecture Software Developer's Manual (July 2017)