From 59131339dc3594c34e74d396390e56256bf55b71 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Risto=20Peja=C5=A1inovi=C4=87?=
<risto.pejasinovic@gmail.com>
Date: Sun, 22 Dec 2024 00:54:09 +0100
Subject: [PATCH] Vcs support (#112)
---
cmake/sim/cadence/xcelium.cmake | 4 +
cmake/sim/synopsys/vcs.cmake | 379 +++++++++---------
cmake/sim/synopsys/vcs_toolchain.cmake | 32 --
examples/dpi-c/CMakeLists.txt | 21 +-
examples/dpi-c/hello/CMakeLists.txt | 4 +-
examples/modelsim/simple/CMakeLists.txt | 20 -
examples/sim_example/CMakeLists.txt | 19 -
examples/sim_example/deps/CPM.cmake | 31 --
examples/sim_example/deps/deps.cmake | 8 -
examples/sim_example/tb.v | 6 -
examples/simple_mixed_language/CMakeLists.txt | 32 ++
.../adder/CMakeLists.txt | 2 +-
.../adder/adder.vhdl | 0
.../simple => simple_mixed_language}/tb.v | 19 +-
examples/simple_verilog/CMakeLists.txt | 41 ++
examples/simple_verilog/adder/CMakeLists.txt | 6 +
examples/simple_verilog/adder/adder.v | 8 +
examples/simple_verilog/tb.v | 22 +
examples/vcs/CMakeLists.txt | 51 ---
examples/vcs/deps/CPM.cmake | 31 --
examples/vcs/deps/deps.cmake | 8 -
examples/vcs/sc_main.cpp | 64 ---
examples/verilator/adder/CMakeLists.txt | 4 +-
23 files changed, 337 insertions(+), 475 deletions(-)
delete mode 100644 cmake/sim/synopsys/vcs_toolchain.cmake
delete mode 100644 examples/modelsim/simple/CMakeLists.txt
delete mode 100644 examples/sim_example/CMakeLists.txt
delete mode 100644 examples/sim_example/deps/CPM.cmake
delete mode 100644 examples/sim_example/deps/deps.cmake
delete mode 100644 examples/sim_example/tb.v
create mode 100644 examples/simple_mixed_language/CMakeLists.txt
rename examples/{modelsim/simple => simple_mixed_language}/adder/CMakeLists.txt (66%)
rename examples/{modelsim/simple => simple_mixed_language}/adder/adder.vhdl (100%)
rename examples/{modelsim/simple => simple_mixed_language}/tb.v (63%)
create mode 100644 examples/simple_verilog/CMakeLists.txt
create mode 100644 examples/simple_verilog/adder/CMakeLists.txt
create mode 100644 examples/simple_verilog/adder/adder.v
create mode 100644 examples/simple_verilog/tb.v
delete mode 100644 examples/vcs/CMakeLists.txt
delete mode 100644 examples/vcs/deps/CPM.cmake
delete mode 100644 examples/vcs/deps/deps.cmake
delete mode 100644 examples/vcs/sc_main.cpp
diff --git a/cmake/sim/cadence/xcelium.cmake b/cmake/sim/cadence/xcelium.cmake
index 38fab42..c2e0df4 100644
--- a/cmake/sim/cadence/xcelium.cmake
+++ b/cmake/sim/cadence/xcelium.cmake
@@ -83,6 +83,7 @@ function(xcelium IP_LIB)
## XMSIM command for running simulation
set(__xmsim_cmd xmsim
+ -64bit
${__lib_args}
${ARG_RUN_ARGS}
${LIBRARY}.${ARG_TOP_MODULE}
@@ -156,6 +157,7 @@ function(__xcelium_compile_lib IP_LIB)
set(DESCRIPTION "Compile Verilog and SV files of ${IP_LIB} with xcelium xmvlog in library ${LIBRARY}")
set(__xmvlog_cmd COMMAND xmvlog
+ -64bit
-sv
${ARG_XMVLOG_ARGS}
${SV_ARG_INCDIRS}
@@ -180,6 +182,7 @@ function(__xcelium_compile_lib IP_LIB)
endforeach()
set(__xmvhdl_cmd COMMAND xmvhdl
+ -64bit
${ARG_XMVHDL_ARGS}
${VHDL_ARG_INCDIRS}
${VHDL_CMP_DEFS_ARG}
@@ -189,6 +192,7 @@ function(__xcelium_compile_lib IP_LIB)
endif()
set(__xmelab_cmd COMMAND xmelab
+ -64bit
${ARG_XMELAB_ARGS}
worklib.${IP_NAME}
# -work ${OUTDIR}/${LIBRARY}
diff --git a/cmake/sim/synopsys/vcs.cmake b/cmake/sim/synopsys/vcs.cmake
index 43ded43..a86393f 100644
--- a/cmake/sim/synopsys/vcs.cmake
+++ b/cmake/sim/synopsys/vcs.cmake
@@ -1,12 +1,7 @@
include_guard(GLOBAL)
-set(__VCS__CMAKE__CURRENT_LIST_DIR ${CMAKE_CURRENT_LIST_DIR} CACHE INTERNAL "")
-macro(vcs_init)
- set(CMAKE_TOOLCHAIN_FILE ${__VCS__CMAKE__CURRENT_LIST_DIR}/vcs_toolchain.cmake)
-endmacro()
-
-function(vcs_vlogan IP_LIB)
- cmake_parse_arguments(ARG "" "TOP_MODULE;OUTDIR" "" ${ARGN})
+function(vcs IP_LIB)
+ cmake_parse_arguments(ARG "TARGET_PER_IP;NO_RUN_TARGET;GUI" "EXECUTABLE_NAME;RUN_TARGET_NAME" "VLOGAN_ARGS;VHDLAN_ARGS;VCS_ARGS;RUN_ARGS" ${ARGN})
if(ARG_UNPARSED_ARGUMENTS)
message(FATAL_ERROR "${CMAKE_CURRENT_FUNCTION} passed unrecognized argument " "${ARG_UNPARSED_ARGUMENTS}")
endif()
@@ -16,204 +11,210 @@ function(vcs_vlogan IP_LIB)
alias_dereference(IP_LIB ${IP_LIB})
get_target_property(BINARY_DIR ${IP_LIB} BINARY_DIR)
- get_ip_sources(SOURCES ${IP_LIB} SYSTEMVERILOG VERILOG VHDL)
+ if(NOT ARG_OUTDIR)
+ set(OUTDIR ${BINARY_DIR}/${IP_LIB}_vcs)
+ else()
+ set(OUTDIR ${ARG_OUTDIR})
+ endif()
+ file(MAKE_DIRECTORY ${OUTDIR})
- get_ip_include_directories(INC_DIRS ${IP_LIB} SYSTEMVERILOG VERILOG VHDL)
+ # get_target_property(LIBRARY ${IP_LIB} LIBRARY)
+ # if(NOT LIBRARY)
+ set(LIBRARY work)
+ # endif()
- foreach(dir ${INC_DIRS})
- list(APPEND ARG_INCDIRS -incdir ${dir})
- endforeach()
+ if(NOT ARG_TOP_MODULE)
+ get_target_property(IP_NAME ${IP_LIB} IP_NAME)
+ set(ARG_TOP_MODULE ${IP_NAME})
+ endif()
- get_ip_compile_definitions(COMP_DEFS ${IP_LIB} SYSTEMVERILOG VERILOG VHDL)
- foreach(def ${COMP_DEFS})
- list(APPEND CMP_DEFS_ARG -D${def})
+ if(ARG_VLOGAN_ARGS)
+ set(ARG_VLOGAN_ARGS VLOGAN_ARGS ${ARG_VLOGAN_ARGS})
+ endif()
+ if(ARG_VHDLAN_ARGS)
+ set(ARG_VHDLAN_ARGS VHDLAN_ARGS ${ARG_VHDLAN_ARGS})
+ endif()
+ if(ARG_VCS_ARGS)
+ set(ARG_VCS_ARGS VCS_ARGS ${ARG_VCS_ARGS})
+ endif()
+
+ get_ip_links(IPS_LIST ${IP_LIB})
+
+ unset(__lib_args)
+ foreach(ip ${IPS_LIST})
+ get_target_property(ip_type ${ip} TYPE)
+ if(ip_type STREQUAL "SHARED_LIBRARY" OR ip_type STREQUAL "STATIC_LIBRARY")
+ list(APPEND __lib_args $<TARGET_FILE:${ip}>)
+ endif()
endforeach()
- if(ARG_TOP_MODULE)
- set(ARG_TOP_MODULE ${ARG_TOP_MODULE})
+ if(ARG_TARGET_PER_IP) # In case TARGET_PER_IP is passed, a compile target is created per IP block
+ set(list_comp_libs ${IPS_LIST})
+ set(__no_deps_arg NO_DEPS)
else()
- get_target_property(ARG_TOP_MODULE ${IP_LIB} IP_NAME)
+ set(list_comp_libs ${IP_LIB})
+ unset(__no_deps_arg)
+ endif()
+
+ unset(__comp_tgts)
+ foreach(ip ${list_comp_libs})
+ get_target_property(ip_name ${ip} IP_NAME)
+ if(ip_name) # If IP_NAME IS set, its SoCMake's IP_LIBRARY
+ __vcs_compile_lib(${ip} ${__no_deps_arg}
+ OUTDIR ${OUTDIR}
+ ${ARG_VLOGAN_ARGS}
+ ${ARG_VHDLAN_ARGS}
+ ${ARG_VCS_ARGS}
+ )
+ list(APPEND __comp_tgts ${ip}_vcs_complib)
+ endif()
+ endforeach()
+
+ if(NOT ARG_EXECUTABLE_NAME)
+ set(ARG_EXECUTABLE_NAME ${IP_LIB}_vcs_exec)
+ endif()
+ set(SIM_EXEC_PATH ${OUTDIR}/${ARG_EXECUTABLE_NAME})
+
+ ## VCS command for compiling executable
+ set(__vcs_cmd vcs
+ -full64
+ -q
+ ${__lib_args}
+ -o ${SIM_EXEC_PATH}
+ ${ARG_VCS_ARGS}
+ ${LIBRARY}.${ARG_TOP_MODULE}
+ # $<$<BOOL:${ARG_GUI}>:-gui>
+ )
+ set(DESCRIPTION "Compile testbench ${IP_LIB} with ${CMAKE_CURRENT_FUNCTION}")
+ set(STAMP_FILE "${BINARY_DIR}/${IP_LIB}_vcs.stamp")
+ add_custom_command(
+ OUTPUT ${SIM_EXEC_PATH} ${STAMP_FILE}
+ COMMAND ${__vcs_cmd}
+ COMMAND touch ${STAMP_FILE}
+ COMMENT ${DESCRIPTION}
+ BYPRODUCTS ${OUTDIR}/csrc ${OUTDIR}/${ARG_EXECUTABLE_NAME}.daidir
+ WORKING_DIRECTORY ${OUTDIR}
+ DEPENDS ${__comp_tgts} ${VCS_COMPLIB_STAMP_FILE}
+ )
+
+ add_custom_target(${IP_LIB}_vcs
+ DEPENDS ${STAMP_FILE} ${IP_LIB}
+ )
+ set_property(TARGET ${IP_LIB}_vcs PROPERTY DESCRIPTION ${DESCRIPTION})
+
+ set(__vcsrun_cmd ${SIM_EXEC_PATH} ${ARG_RUN_ARGS})
+ if(NOT ARG_NO_RUN_TARGET)
+ if(NOT ARG_RUN_TARGET_NAME)
+ set(ARG_RUN_TARGET_NAME run_${IP_LIB}_${CMAKE_CURRENT_FUNCTION})
+ endif()
+ set(DESCRIPTION "Run simulation on ${IP_LIB} with ${CMAKE_CURRENT_FUNCTION}")
+ add_custom_target(${ARG_RUN_TARGET_NAME}
+ COMMAND ${__vcsrun_cmd}
+ COMMENT ${DESCRIPTION}
+ WORKING_DIRECTORY ${OUTDIR}
+ DEPENDS ${IP_LIB}_vcs
+ )
+ set_property(TARGET ${ARG_RUN_TARGET_NAME} PROPERTY DESCRIPTION ${DESCRIPTION})
+ endif()
+ set(SIM_RUN_CMD ${__vcsrun_cmd} PARENT_SCOPE)
+
+endfunction()
+
+function(__vcs_compile_lib IP_LIB)
+ cmake_parse_arguments(ARG "NO_DEPS" "OUTDIR;TOP_MODULE" "VLOGAN_ARGS;VHDLAN_ARGS;VCS_ARGS" ${ARGN})
+ # Check for any unrecognized arguments
+ if(ARG_UNPARSED_ARGUMENTS)
+ message(FATAL_ERROR "${CMAKE_CURRENT_FUNCTION} passed unrecognized argument " "${ARG_UNPARSED_ARGUMENTS}")
endif()
- if(ARG_OUTDIR)
+ include("${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../hwip.cmake")
+
+ alias_dereference(IP_LIB ${IP_LIB})
+ get_target_property(BINARY_DIR ${IP_LIB} BINARY_DIR)
+
+ # get_target_property(LIBRARY ${IP_LIB} LIBRARY)
+ # if(NOT LIBRARY)
+ set(LIBRARY work)
+ # endif()
+
+ if(NOT ARG_OUTDIR)
+ set(OUTDIR ${BINARY_DIR}/${IP_LIB}_vcs)
+ else()
set(OUTDIR ${ARG_OUTDIR})
+ endif()
+ file(MAKE_DIRECTORY ${OUTDIR})
+
+ if(NOT ARG_TOP_MODULE)
+ get_target_property(IP_NAME ${IP_LIB} IP_NAME)
+ set(ARG_TOP_MODULE ${IP_NAME})
+ endif()
+
+ if(ARG_NO_DEPS)
+ set(ARG_NO_DEPS NO_DEPS)
else()
- set(OUTDIR ${BINARY_DIR})
+ unset(ARG_NO_DEPS)
endif()
- file(MAKE_DIRECTORY ${OUTDIR}/csrc/sysc/include)
- find_program(VLOGAN_EXECUTABLE vlogan REQUIRED
- HINTS ${VCS_HOME} $ENV{VCS_HOME}
- )
+ # SystemVerilog and Verilog files and arguments
+ get_ip_sources(SV_SOURCES ${IP_LIB} SYSTEMVERILOG VERILOG ${ARG_NO_DEPS})
+ if(SV_SOURCES)
+ get_ip_include_directories(SV_INC_DIRS ${IP_LIB} SYSTEMVERILOG VERILOG)
+ get_ip_compile_definitions(SV_COMP_DEFS ${IP_LIB} SYSTEMVERILOG VERILOG)
+
+ foreach(dir ${SV_INC_DIRS})
+ list(APPEND SV_ARG_INCDIRS +incdir+${dir})
+ endforeach()
+
+ foreach(def ${SV_COMP_DEFS})
+ list(APPEND SV_CMP_DEFS_ARG +define+${def})
+ endforeach()
+
+ set(DESCRIPTION "Compile Verilog and SV files of ${IP_LIB} with vcs vlogan in library ${LIBRARY}")
+ set(__vlogan_cmd COMMAND vlogan
+ -full64
+ -q
+ -sverilog
+ ${ARG_VLOGAN_ARGS}
+ ${SV_ARG_INCDIRS}
+ ${SV_CMP_DEFS_ARG}
+ ${SV_SOURCES}
+ # -work ${OUTDIR}/${LIBRARY}
+ )
+ endif()
- set(STAMP_FILE "${OUTDIR}/${IP_LIB}_${CMAKE_CURRENT_FUNCTION}.stamp")
- add_custom_command(
- OUTPUT ${STAMP_FILE}
- WORKING_DIRECTORY ${OUTDIR}
- COMMAND ${VLOGAN_EXECUTABLE}
- -full64 -nc -sverilog
- -sc_model ${ARG_TOP_MODULE}
- ${SOURCES}
- ${COMP_DEFS}
+ # VHDL files and arguments
+ get_ip_sources(VHDL_SOURCES ${IP_LIB} VHDL ${ARG_NO_DEPS})
+ if(VHDL_SOURCES)
+ set(__vhdlan_cmd COMMAND vhdlan
+ -full64
+ -q
+ ${ARG_VHDLAN_ARGS}
+ ${VHDL_SOURCES}
+ # -work ${OUTDIR}/${LIBRARY}
+ )
+ endif()
- COMMAND touch ${STAMP_FILE}
- DEPENDS ${SOURCES}
- COMMENT "Running ${CMAKE_CURRENT_FUNCTION} on ${IP_LIB}"
+ if(NOT TARGET ${IP_LIB}_vcs_complib)
+ set(DESCRIPTION "Compile VHDL, SV, and Verilog files for ${IP_LIB} with vcs in library ${LIBRARY}")
+ set(STAMP_FILE "${BINARY_DIR}/${IP_LIB}_${CMAKE_CURRENT_FUNCTION}.stamp")
+ add_custom_command(
+ OUTPUT ${STAMP_FILE}
+ ${__vlogan_cmd}
+ ${__vhdlan_cmd}
+ COMMAND touch ${STAMP_FILE}
+ WORKING_DIRECTORY ${OUTDIR}
+ BYPRODUCTS ${OUTDIR}/64 ${OUTDIR}/AN.DB
+ DEPENDS ${SV_SOURCES} ${VHDL_SOURCES}
+ COMMENT ${DESCRIPTION}
)
- add_custom_target(
- ${IP_LIB}_${CMAKE_CURRENT_FUNCTION}
- DEPENDS ${STAMP_FILE}
+ add_custom_target(
+ ${IP_LIB}_vcs_complib
+ DEPENDS ${STAMP_FILE} ${STAMP_FILE_VHDL} ${IP_LIB}
)
+ set_property(TARGET ${IP_LIB}_vcs_complib PROPERTY
+ DESCRIPTION "Compile VHDL, SV, and Verilog files for ${IP_LIB} with vcs in library ${LIBRARY}")
+ set(VCS_COMPLIB_STAMP_FILE ${STAMP_FILE} PARENT_SCOPE)
+ endif()
- set(__VCS_LIB ${IP_LIB}__vcs)
- add_library(${__VCS_LIB} OBJECT IMPORTED)
- add_dependencies(${__VCS_LIB} ${IP_LIB}_${CMAKE_CURRENT_FUNCTION})
- target_include_directories(${__VCS_LIB} INTERFACE
- ${OUTDIR}/csrc/sysc/include)
- #target_link_libraries(${__VCS_LIB} INTERFACE -lpthread)
-
- string(REPLACE "__" "::" ALIAS_NAME "${__VCS_LIB}")
- add_library(${ALIAS_NAME} ALIAS ${__VCS_LIB})
-
- # add_dependencies(${IP_LIB}_${CMAKE_CURRENT_FUNCTION} ${IP_LIB})
endfunction()
-
-# syscan -full64 -sysc=scv20 sc_main.cpp
-
-#function(vcs EXEC)
-# cmake_parse_arguments(ARG "" "OUTDIR" "DEPENDS" ${ARGN})
-# if(ARG_UNPARSED_ARGUMENTS)
-# message(FATAL_ERROR "${CMAKE_CURRENT_FUNCTION} passed unrecognized argument " "${ARG_UNPARSED_ARGUMENTS}")
-# endif()
-#
-# include("${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../hwip.cmake")
-#
-# get_target_property(BINARY_DIR ${EXEC} BINARY_DIR)
-#
-# safe_get_target_property(INTERFACE_SOURCES ${EXEC} INTERFACE_SOURCES "")
-# safe_get_target_property(SOURCES ${EXEC} SOURCES "")
-# list(APPEND SOURCES ${INTERFACE_SOURCES})
-# message("SOURCES: ${SOURCES}")
-#
-# if(NOT ARG_OUTDIR)
-# set(OUTDIR "${BINARY_DIR}/${EXEC}_vcs")
-# else()
-# set(OUTDIR ${ARG_OUTDIR})
-# endif()
-# file(MAKE_DIRECTORY ${OUTDIR})
-#
-# ######################################
-# ##### Get libraries from EXEC ########
-# ######################################
-#
-# safe_get_target_property(INTERFACE_LINK_LIBRARIES ${EXEC} INTERFACE_LINK_LIBRARIES "")
-# safe_get_target_property(LINK_LIBRARIES ${EXEC} LINK_LIBRARIES "")
-# list(APPEND LINK_LIBRARIES ${INTERFACE_LINK_LIBRARIES})
-# list(REMOVE_DUPLICATES LINK_LIBRARIES)
-# message("====== LINK_LIBRARIES: ${LINK_LIBRARIES}")
-#
-# unset(VCS_LDFLAG_RPATH)
-# unset(VCS_LDFLAGS_LIBS)
-# string(APPEND VCS_LDFLAG_RPATH "-LDFLAGS -Wl,-rpath,")
-# foreach(lib ${LINK_LIBRARIES})
-# if(TARGET ${lib})
-# get_target_property(IMPORTED_LOCATION ${lib} IMPORTED_LOCATION)
-# if(IMPORTED_LOCATION)
-# set(lib ${IMPORTED_LOCATION})
-# cmake_path(GET lib PARENT_PATH lib_dir)
-# string(APPEND VCS_LDFLAG_RPATH ${lib_dir}:)
-# list(APPEND VCS_LDFLAGS_LIBS -LDFLAGS ${lib})
-# else()
-# get_target_property(BINARY_DIR ${lib} BINARY_DIR)
-# set(lib_dir ${BINARY_DIR})
-# string(APPEND VCS_LDFLAG_RPATH ${lib_dir}:)
-# message("------ ADDING LIB: ${lib}")
-# list(APPEND VCS_LIBS_ARG -LDFLAGS -L${lib_dir} -l${lib})
-# endif()
-# endif()
-# endforeach()
-#
-# # string (REPLACE ";" " " VCS_LDFLAG_RPATH "${VCS_LDFLAG_RPATH}")
-# message("LIBS: ${VCS_LDFLAG_RPATH}")
-#
-# ######################################
-# ##### Get Include Directories ########
-# ######################################
-#
-# safe_get_target_property(INTERFACE_INCLUDE_DIRECTORIES ${EXEC} INTERFACE_INCLUDE_DIRECTORIES "")
-# safe_get_target_property(INCLUDE_DIRECTORIES ${EXEC} INCLUDE_DIRECTORIES "")
-# message("INCLUDE: ${INCLUDE_DIRECTORIES}, INTF_INC: ${INTERFACE_INCLUDE_DIRECTORIES}")
-# foreach(incdir ${INCLUDE_DIRECTORIES} ${INTERFACE_INCLUDE_DIRECTORIES})
-# list(APPEND _VCS_CFLAGS -CFLAGS -I${incdir})
-# endforeach()
-#
-# foreach(lib ${LINK_LIBRARIES})
-# if(TARGET ${lib})
-# safe_get_target_property(intf_inc_dirs ${lib} INTERFACE_INCLUDE_DIRECTORIES "")
-# safe_get_target_property(inc_dirs ${lib} INCLUDE_DIRECTORIES "")
-# message("LIB: ${lib} DIR: ${intf_inc_dirs} inc_dirs: ${inc_dirs}")
-# foreach(incdir ${inc_dirs} ${intf_inc_dirs})
-# list(APPEND _VCS_CFLAGS -CFLAGS -I${incdir})
-# endforeach()
-# endif()
-# endforeach()
-#
-#
-# set(CMAKE_FIND_DEBUG_MODE TRUE)
-# find_program(_SYSCAN_EXECUTABLE syscan REQUIRED
-# HINTS ${VCS_HOME} $ENV{VCS_HOME}
-# )
-# set(CMAKE_FIND_DEBUG_MODE FALSE)
-#
-# set(STAMP_FILE "${OUTDIR}/${EXEC}_syscan.stamp")
-# add_custom_command(
-# OUTPUT ${STAMP_FILE}
-# WORKING_DIRECTORY ${OUTDIR}
-# COMMAND ${_SYSCAN_EXECUTABLE}
-# -full64 -sysc=scv20
-# ${_VCS_CFLAGS}
-# ${SOURCES}
-#
-# COMMAND touch ${STAMP_FILE}
-# DEPENDS ${SOURCES} ${ARG_DEPENDS}
-# COMMENT "Running ${CMAKE_CURRENT_FUNCTION} on ${EXEC}"
-# )
-#
-# add_custom_target(
-# ${EXEC}_syscan
-# DEPENDS ${STAMP_FILE}
-# )
-#
-## vcs -V -full64 -nc -j16 -sverilog -sysc=scv20 sc_main -timescale=1ns/1ps
-#
-# find_program(_VCS_EXECUTABLE vcs REQUIRED
-# HINTS ${VCS_HOME} $ENV{VCS_HOME}
-# )
-#
-# message("DEPENDS: ${ARG_DEPENDS}")
-# set(STAMP_FILE "${OUTDIR}/${EXEC}_vcs.stamp")
-# add_custom_command(
-# OUTPUT ${STAMP_FILE} ${PROJECT_BINARY_DIR}/${EXEC}
-# WORKING_DIRECTORY ${OUTDIR}
-# COMMAND ${_VCS_EXECUTABLE}
-# -full64 -nc -sysc=scv20
-# sc_main
-# -timescale=1ns/1ps
-# ${VCS_LDFLAG_RPATH}
-# ${VCS_LDFLAGS_LIBS}
-# ${VCS_LIBS_ARG}
-# -o ${PROJECT_BINARY_DIR}/${EXEC}
-#
-# COMMAND touch ${STAMP_FILE}
-# DEPENDS ${SOURCES} ${EXEC}_syscan ${ARG_DEPENDS} ${LINK_LIBRARIES}
-# COMMENT "Running ${CMAKE_CURRENT_FUNCTION} on ${EXEC}"
-# )
-#
-# add_custom_target(
-# ${EXEC}_vcs
-# DEPENDS ${STAMP_FILE}
-# )
-#
-# # add_dependencies(${IP_LIB}_${CMAKE_CURRENT_FUNCTION} ${IP_LIB})
-#endfunction()
diff --git a/cmake/sim/synopsys/vcs_toolchain.cmake b/cmake/sim/synopsys/vcs_toolchain.cmake
deleted file mode 100644
index d40bea1..0000000
--- a/cmake/sim/synopsys/vcs_toolchain.cmake
+++ /dev/null
@@ -1,32 +0,0 @@
-set(CMAKE_LINKER ${VCS_HOME}/gnu/linux64/binutils-64/bin/ld)
-set(CMAKE_C_COMPILER ${VCS_HOME}/gnu/linux64/gcc-64/bin/gcc)
-set(CMAKE_CXX_COMPILER ${VCS_HOME}/gnu/linux64/gcc-64/bin/g++)
-
-set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -L${VCS_HOME}/gnu/linux64/gcc-64/lib64/ ")
-set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -L${VCS_HOME}/gnu/linux64/gcc-64/lib64/ ")
-
-
-if(NOT TARGET vcs__libs)
- add_library(vcs__libs INTERFACE)
- add_library(vcs::libs ALIAS vcs__libs)
-
- target_include_directories(vcs__libs INTERFACE
- ${VCS_HOME}/etc/systemc/accellera_install/systemc233-gcc9/include
- ${VCS_HOME}/include/systemc233
- ${VCS_HOME}/include/scv-2.0
- ${VCS_HOME}/lib
- ${VCS_HOME}/include
- ${VCS_HOME}/include/cosim/bf
- )
-endif()
-
-find_program(VCS_EXECUTABLE vcs REQUIRED
- HINTS ${VCS_HOME} $ENV{VCS_HOME}
- )
-
-set(CMAKE_SHARED_LIBRARY_RUNTIME_CXX_FLAG "-LDFLAGS -Wl,-rpath,")
-set(CMAKE_CXX_LINK_EXECUTABLE "${VCS_EXECUTABLE} -full64 -nc -sysc=scv20 sc_main -timescale=1ns/1ps <OBJECTS> <CMAKE_CXX_LINK_FLAGS> <LINK_LIBRARIES> -o <TARGET>")
-
-unset(CMAKE_CXX_COMPILER_WORKS CACHE)
-set(CMAKE_CXX_COMPILER_WORKS TRUE)
-
diff --git a/examples/dpi-c/CMakeLists.txt b/examples/dpi-c/CMakeLists.txt
index c3e7acc..ab05721 100644
--- a/examples/dpi-c/CMakeLists.txt
+++ b/examples/dpi-c/CMakeLists.txt
@@ -3,7 +3,10 @@ project(dpi_example NONE)
include("../../SoCMakeConfig.cmake")
-option_enum(SIMULATOR "Which simulator to use" "questa;modelsim;xcelium;verilator" "modelsim")
+option_enum(SIMULATOR "Which simulator to use" "questa;modelsim;xcelium;vcs;verilator;all" "modelsim")
+if(SIMULATOR STREQUAL "all")
+ set(ALL_SIMS TRUE)
+endif()
add_ip(tb
DESCRIPTION "Simple verilog testbench"
@@ -17,17 +20,23 @@ add_subdirectory(hello)
ip_link(${IP} hello_dpi)
-if(SIMULATOR STREQUAL "questa" OR SIMULATOR STREQUAL "modelsim")
+if(SIMULATOR STREQUAL "questa" OR SIMULATOR STREQUAL "modelsim" OR ALL_SIMS)
modelsim(${IP})
+endif()
-elseif(SIMULATOR STREQUAL "xcelium")
+if(SIMULATOR STREQUAL "xcelium" OR ALL_SIMS)
xcelium(${IP})
+endif()
+
+if(SIMULATOR STREQUAL "vcs" OR ALL_SIMS)
+ vcs(${IP})
+endif()
-elseif(SIMULATOR STREQUAL "verilator")
+if(SIMULATOR STREQUAL "verilator" OR ALL_SIMS)
enable_language(CXX)
verilator(${IP})
- add_executable(main Vtb__main.cpp)
- target_link_libraries(main tb__vlt)
+ add_executable(verilator_tb EXCLUDE_FROM_ALL Vtb__main.cpp )
+ target_link_libraries(verilator_tb tb__vlt)
endif()
help()
diff --git a/examples/dpi-c/hello/CMakeLists.txt b/examples/dpi-c/hello/CMakeLists.txt
index 71d9b5a..a30eb4b 100644
--- a/examples/dpi-c/hello/CMakeLists.txt
+++ b/examples/dpi-c/hello/CMakeLists.txt
@@ -1,11 +1,13 @@
cmake_minimum_required(VERSION 3.25)
project(hello_dpi CXX)
+set(CMAKE_CXX_STANDARD 11)
+
add_library(hello_dpi SHARED
./hello.cpp
)
-if(NOT SIMULATOR STREQUAL "verilator")
+if(SIMULATOR STREQUAL "modelsim")
target_compile_options(hello_dpi PRIVATE -m32)
target_link_options(hello_dpi PRIVATE -m32)
endif()
diff --git a/examples/modelsim/simple/CMakeLists.txt b/examples/modelsim/simple/CMakeLists.txt
deleted file mode 100644
index 65a6342..0000000
--- a/examples/modelsim/simple/CMakeLists.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-cmake_minimum_required(VERSION 3.25)
-project(example NONE)
-
-include("../../../SoCMakeConfig.cmake")
-
-add_ip(tb
- DESCRIPTION "Simple verilog testbench"
- )
-
-ip_sources(${IP} VERILOG
- ${PROJECT_SOURCE_DIR}/tb.v
- )
-
-add_subdirectory(adder)
-
-ip_link(${IP} adder)
-
-modelsim(${IP} TARGET_PER_IP)
-
-help()
diff --git a/examples/sim_example/CMakeLists.txt b/examples/sim_example/CMakeLists.txt
deleted file mode 100644
index cf960a7..0000000
--- a/examples/sim_example/CMakeLists.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-cmake_minimum_required(VERSION 3.25)
-project(example NONE)
-
-include("deps/deps.cmake")
-
-add_ip(cern::ip::tb::0.0.1
- DESCRIPTION "Simple verilog testbench"
- )
-
-ip_sources(${IP} VERILOG # Add source files to the VERILOG file set
- ${PROJECT_SOURCE_DIR}/tb.v
- )
-
-iverilog(${IP})
-
-verilator(${IP} # Create verilate target
- MAIN) # Let Verilator create a main.cpp testbench
-
-help()
diff --git a/examples/sim_example/deps/CPM.cmake b/examples/sim_example/deps/CPM.cmake
deleted file mode 100644
index 5600efe..0000000
--- a/examples/sim_example/deps/CPM.cmake
+++ /dev/null
@@ -1,31 +0,0 @@
-if(CPM_SOURCE_CACHE)
- set(CPM_DOWNLOAD_LOCATION "${CPM_SOURCE_CACHE}/cpm/CPM_${CPM_DOWNLOAD_VERSION}.cmake")
-elseif(DEFINED ENV{CPM_SOURCE_CACHE})
- set(CPM_DOWNLOAD_LOCATION "$ENV{CPM_SOURCE_CACHE}/cpm/CPM_${CPM_DOWNLOAD_VERSION}.cmake")
-else()
- set(CPM_DOWNLOAD_LOCATION "${CMAKE_BINARY_DIR}/cmake/CPM_${CPM_DOWNLOAD_VERSION}.cmake")
-endif()
-
-# Expand relative path. This is important if the provided path contains a tilde (~)
-get_filename_component(CPM_DOWNLOAD_LOCATION ${CPM_DOWNLOAD_LOCATION} ABSOLUTE)
-
-function(download_cpm)
- message(STATUS "Downloading CPM.cmake to ${CPM_DOWNLOAD_LOCATION}")
- file(DOWNLOAD
- https://github.com/cpm-cmake/CPM.cmake/releases/download/v${CPM_DOWNLOAD_VERSION}/CPM.cmake
- ${CPM_DOWNLOAD_LOCATION}
- )
-endfunction()
-
-if(NOT (EXISTS ${CPM_DOWNLOAD_LOCATION}))
- download_cpm()
-else()
- # resume download if it previously failed
- file(READ ${CPM_DOWNLOAD_LOCATION} check)
- if("${check}" STREQUAL "")
- download_cpm()
- endif()
- unset(check)
-endif()
-
-include(${CPM_DOWNLOAD_LOCATION})
diff --git a/examples/sim_example/deps/deps.cmake b/examples/sim_example/deps/deps.cmake
deleted file mode 100644
index 2659496..0000000
--- a/examples/sim_example/deps/deps.cmake
+++ /dev/null
@@ -1,8 +0,0 @@
-set(CPM_DOWNLOAD_VERSION 0.40.2) # Define CPM version to be downloaded
-include(${CMAKE_CURRENT_LIST_DIR}/CPM.cmake) # Include the CPM.cmake downloader
-
-CPMAddPackage( # Add SoCMake as a package
- NAME SoCMake
- GIT_TAG develop # You can define GIT_TAG or VERSION for versioning
- GIT_REPOSITORY "https://github.com/HEP-SoC/SoCMake.git" # GIT_REPOSITORY or URL
- )
diff --git a/examples/sim_example/tb.v b/examples/sim_example/tb.v
deleted file mode 100644
index 7d32df2..0000000
--- a/examples/sim_example/tb.v
+++ /dev/null
@@ -1,6 +0,0 @@
-module tb;
- initial begin
- $display("Hello world, from SoCMake build system\n");
- $finish();
- end
- endmodule
diff --git a/examples/simple_mixed_language/CMakeLists.txt b/examples/simple_mixed_language/CMakeLists.txt
new file mode 100644
index 0000000..9ce3196
--- /dev/null
+++ b/examples/simple_mixed_language/CMakeLists.txt
@@ -0,0 +1,32 @@
+cmake_minimum_required(VERSION 3.25)
+project(simple_mixed_language NONE)
+
+include("../../SoCMakeConfig.cmake")
+
+option_enum(SIMULATOR "Which simulator to use" "questa;modelsim;xcelium;vcs;all" "modelsim")
+if(SIMULATOR STREQUAL "all")
+ set(ALL_SIMS TRUE)
+endif()
+
+add_ip(tb
+ DESCRIPTION "Simple verilog testbench")
+
+ip_sources(${IP} VERILOG
+ tb.v)
+
+add_subdirectory(adder)
+ip_link(${IP} adder)
+
+if(SIMULATOR STREQUAL "questa" OR SIMULATOR STREQUAL "modelsim" OR ALL_SIMS)
+ modelsim(${IP})
+endif()
+
+if(SIMULATOR STREQUAL "xcelium" OR ALL_SIMS)
+ xcelium(${IP})
+endif()
+
+if(SIMULATOR STREQUAL "vcs" OR ALL_SIMS)
+ vcs(${IP})
+endif()
+
+help()
diff --git a/examples/modelsim/simple/adder/CMakeLists.txt b/examples/simple_mixed_language/adder/CMakeLists.txt
similarity index 66%
rename from examples/modelsim/simple/adder/CMakeLists.txt
rename to examples/simple_mixed_language/adder/CMakeLists.txt
index 307f212..5b4d612 100644
--- a/examples/modelsim/simple/adder/CMakeLists.txt
+++ b/examples/simple_mixed_language/adder/CMakeLists.txt
@@ -3,5 +3,5 @@ add_ip(adder
DESCRIPTION "Just a simple adder")
ip_sources(${IP} VHDL
- ${CMAKE_CURRENT_LIST_DIR}/adder.vhdl
+ adder.vhdl
)
diff --git a/examples/modelsim/simple/adder/adder.vhdl b/examples/simple_mixed_language/adder/adder.vhdl
similarity index 100%
rename from examples/modelsim/simple/adder/adder.vhdl
rename to examples/simple_mixed_language/adder/adder.vhdl
diff --git a/examples/modelsim/simple/tb.v b/examples/simple_mixed_language/tb.v
similarity index 63%
rename from examples/modelsim/simple/tb.v
rename to examples/simple_mixed_language/tb.v
index 99f03e0..1247c03 100644
--- a/examples/modelsim/simple/tb.v
+++ b/examples/simple_mixed_language/tb.v
@@ -1,10 +1,6 @@
module tb;
- initial begin
- $display("Hello world, from SoCMake build system\n");
- $finish();
- end
-
- wire [4:0] a, b, o;
+ reg [4:0] a, b;
+ wire [4:0] o;
adder adder_i (
.NUM1(a),
@@ -12,4 +8,15 @@ module tb;
.SUM(o)
);
+ initial begin
+ a = 5;
+ b = 10;
+ #1;
+
+ $display("Hello world, from SoCMake build system\n");
+ $display("%d + %d = %d", a, b, o);
+ $finish();
+ end
+
+
endmodule
diff --git a/examples/simple_verilog/CMakeLists.txt b/examples/simple_verilog/CMakeLists.txt
new file mode 100644
index 0000000..20f9955
--- /dev/null
+++ b/examples/simple_verilog/CMakeLists.txt
@@ -0,0 +1,41 @@
+cmake_minimum_required(VERSION 3.25)
+project(simple_verilog_example NONE)
+
+include("../../SoCMakeConfig.cmake")
+
+option_enum(SIMULATOR "Which simulator to use" "iverilog;questa;modelsim;xcelium;vcs;verilator;all" "iverilog")
+if(SIMULATOR STREQUAL "all")
+ set(ALL_SIMS TRUE)
+endif()
+
+add_ip(tb
+ DESCRIPTION "Simple verilog testbench")
+
+ip_sources(${IP} VERILOG
+ tb.v)
+
+add_subdirectory(adder)
+ip_link(${IP} adder)
+
+
+if(SIMULATOR STREQUAL "iverilog" OR ALL_SIMS)
+ iverilog(${IP})
+endif()
+
+if(SIMULATOR STREQUAL "questa" OR SIMULATOR STREQUAL "modelsim" OR ALL_SIMS)
+ modelsim(${IP})
+endif()
+
+if(SIMULATOR STREQUAL "xcelium" OR ALL_SIMS)
+ xcelium(${IP})
+endif()
+
+if(SIMULATOR STREQUAL "verilator" OR ALL_SIMS)
+ verilator(${IP} MAIN VERILATOR_ARGS --timing)
+endif()
+
+if(SIMULATOR STREQUAL "vcs" OR ALL_SIMS)
+ vcs(${IP})
+endif()
+
+help()
diff --git a/examples/simple_verilog/adder/CMakeLists.txt b/examples/simple_verilog/adder/CMakeLists.txt
new file mode 100644
index 0000000..f6cac6f
--- /dev/null
+++ b/examples/simple_verilog/adder/CMakeLists.txt
@@ -0,0 +1,6 @@
+add_ip(adder
+ DESCRIPTION "Just a simple adder")
+
+ip_sources(${IP} VERILOG
+ adder.v
+ )
diff --git a/examples/simple_verilog/adder/adder.v b/examples/simple_verilog/adder/adder.v
new file mode 100644
index 0000000..f635684
--- /dev/null
+++ b/examples/simple_verilog/adder/adder.v
@@ -0,0 +1,8 @@
+module adder(
+ input [4:0] NUM1,
+ input [4:0] NUM2,
+ output [4:0] SUM
+ );
+
+ assign SUM = NUM1 + NUM2;
+endmodule
diff --git a/examples/simple_verilog/tb.v b/examples/simple_verilog/tb.v
new file mode 100644
index 0000000..1247c03
--- /dev/null
+++ b/examples/simple_verilog/tb.v
@@ -0,0 +1,22 @@
+module tb;
+ reg [4:0] a, b;
+ wire [4:0] o;
+
+ adder adder_i (
+ .NUM1(a),
+ .NUM2(b),
+ .SUM(o)
+ );
+
+ initial begin
+ a = 5;
+ b = 10;
+ #1;
+
+ $display("Hello world, from SoCMake build system\n");
+ $display("%d + %d = %d", a, b, o);
+ $finish();
+ end
+
+
+ endmodule
diff --git a/examples/vcs/CMakeLists.txt b/examples/vcs/CMakeLists.txt
deleted file mode 100644
index afbf5d4..0000000
--- a/examples/vcs/CMakeLists.txt
+++ /dev/null
@@ -1,51 +0,0 @@
-include("deps/deps.cmake")
-
-if(SIM_VCS)
- if(NOT VCS_HOME AND NOT ENV{VCS_HOME})
- set(VCS_HOME /eda/synopsys/2022-23/RHELx86/VCS_2022.06-SP2)
- endif()
- vcs_init()
-else()
- set(VERILATOR_HOME /cerneda/various/RHELx86/verilator-4.228/)
- set(SYSTEMC_HOME /scratch/rpejasin/socmake/SoCMake-Ibex/deps/_deps/verisc/open/systemc-2.3.3/)
-endif()
-
-cmake_minimum_required(VERSION 3.25)
-project(example CXX C)
-
-if(NOT SIM_VCS)
- find_package(SystemCLanguage REQUIRED
- HINTS ${SYSTEMC_HOME}/*/*/*
- )
- set(CMAKE_CXX_STANDARD ${SystemC_CXX_STANDARD})
-endif()
-
-add_subdirectory(../verilator/adder "adder")
-
-add_executable(test sc_main.cpp)
-
-if(SIM_VCS)
- vcs_vlogan(cern::ip::adder::0.0.1
- OUTDIR ${PROJECT_BINARY_DIR})
-
- target_link_libraries(test
- cern::ip::adder::0.0.1::vcs
- vcs::libs
- )
-else()
- verilate(cern::ip::adder::0.0.1
- SYSTEMC
- PREFIX adder
- VERILATOR_ARGS --pins-bv 1
- )
-
- target_link_libraries(test
- cern::ip::adder::0.0.1::vlt
- SystemC::systemc
- )
-endif()
-
-target_compile_definitions(test PUBLIC
- VERBOSE=1
- )
-
diff --git a/examples/vcs/deps/CPM.cmake b/examples/vcs/deps/CPM.cmake
deleted file mode 100644
index 5600efe..0000000
--- a/examples/vcs/deps/CPM.cmake
+++ /dev/null
@@ -1,31 +0,0 @@
-if(CPM_SOURCE_CACHE)
- set(CPM_DOWNLOAD_LOCATION "${CPM_SOURCE_CACHE}/cpm/CPM_${CPM_DOWNLOAD_VERSION}.cmake")
-elseif(DEFINED ENV{CPM_SOURCE_CACHE})
- set(CPM_DOWNLOAD_LOCATION "$ENV{CPM_SOURCE_CACHE}/cpm/CPM_${CPM_DOWNLOAD_VERSION}.cmake")
-else()
- set(CPM_DOWNLOAD_LOCATION "${CMAKE_BINARY_DIR}/cmake/CPM_${CPM_DOWNLOAD_VERSION}.cmake")
-endif()
-
-# Expand relative path. This is important if the provided path contains a tilde (~)
-get_filename_component(CPM_DOWNLOAD_LOCATION ${CPM_DOWNLOAD_LOCATION} ABSOLUTE)
-
-function(download_cpm)
- message(STATUS "Downloading CPM.cmake to ${CPM_DOWNLOAD_LOCATION}")
- file(DOWNLOAD
- https://github.com/cpm-cmake/CPM.cmake/releases/download/v${CPM_DOWNLOAD_VERSION}/CPM.cmake
- ${CPM_DOWNLOAD_LOCATION}
- )
-endfunction()
-
-if(NOT (EXISTS ${CPM_DOWNLOAD_LOCATION}))
- download_cpm()
-else()
- # resume download if it previously failed
- file(READ ${CPM_DOWNLOAD_LOCATION} check)
- if("${check}" STREQUAL "")
- download_cpm()
- endif()
- unset(check)
-endif()
-
-include(${CPM_DOWNLOAD_LOCATION})
diff --git a/examples/vcs/deps/deps.cmake b/examples/vcs/deps/deps.cmake
deleted file mode 100644
index c95faf0..0000000
--- a/examples/vcs/deps/deps.cmake
+++ /dev/null
@@ -1,8 +0,0 @@
-set(CPM_DOWNLOAD_VERSION 0.40.2)
-include(${CMAKE_CURRENT_LIST_DIR}/CPM.cmake)
-
-CPMAddPackage(
- NAME SoCMake
- GIT_TAG master
- GIT_REPOSITORY "https://github.com/HEP-SoC/SoCMake.git"
- )
diff --git a/examples/vcs/sc_main.cpp b/examples/vcs/sc_main.cpp
deleted file mode 100644
index a4e2fbf..0000000
--- a/examples/vcs/sc_main.cpp
+++ /dev/null
@@ -1,64 +0,0 @@
-#include <iostream>
-#include <systemc>
-
-#include "adder.h"
-
-using namespace sc_core;
-using namespace sc_dt;
-
-SC_MODULE(TESTBENCH) {
- sc_signal<sc_bv<8>> a_in;
- sc_signal<sc_bv<8>> b_in;
- sc_signal<sc_bv<9>> out;
-
- adder dut{"dut"};
-
- void stimulus() {
- a_in.write(0);
- b_in.write(50);
- while (true) {
- a_in.write(a_in.read().to_uint() + 1);
- b_in.write(b_in.read().to_uint() + 2);
-
- wait(5, SC_NS);
- }
- }
-
- void checker() {
-#ifdef VERBOSE
- std::cout << "Value a_in: " << a_in.read().to_uint()
- << " b_in: " << b_in.read().to_uint()
- << " Out: " << out.read().to_uint() << "\n";
-#endif
- if (a_in.read().to_uint() + b_in.read().to_uint() != out.read().to_uint()) {
- std::cout << "Error in verilog\n";
- std::cout << "Value a_in: " << a_in.read().to_uint()
- << " b_in: " << b_in.read().to_uint()
- << " Out: " << out.read().to_uint() << "\n";
- exit(-1);
- }
- }
-
-
- SC_CTOR(TESTBENCH) {
- dut.a(a_in);
- dut.b(b_in);
- dut.o(out);
-
- SC_THREAD(stimulus);
-
- SC_METHOD(checker);
- sensitive << out;
- }
-};
-
-int sc_main(int argc, char **argv) {
- std::cout << "Simple SystemC test with verilator dut\n";
-
- TESTBENCH tb("tb");
-
- sc_start(1000, SC_NS);
-
- return 0;
-}
-
diff --git a/examples/verilator/adder/CMakeLists.txt b/examples/verilator/adder/CMakeLists.txt
index bbacdf9..7a83c8b 100644
--- a/examples/verilator/adder/CMakeLists.txt
+++ b/examples/verilator/adder/CMakeLists.txt
@@ -5,6 +5,6 @@ add_ip(cern::ip::adder::0.0.1
DESCRIPTION "Just a simple adder"
)
-ip_sources(adder VERILOG
- ${PROJECT_SOURCE_DIR}/adder.v
+ip_sources(${IP} VERILOG
+ adder.v
)