From 58cf5685e3b13a3339dd47227c4047794b1673bb Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Risto=20Peja=C5=A1inovi=C4=87?=
<risto.pejasinovic@gmail.com>
Date: Sun, 22 Dec 2024 00:20:18 +0100
Subject: [PATCH] Xcelium always use 64bit compilation
---
cmake/sim/cadence/xcelium.cmake | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/cmake/sim/cadence/xcelium.cmake b/cmake/sim/cadence/xcelium.cmake
index 38fab42..c2e0df4 100644
--- a/cmake/sim/cadence/xcelium.cmake
+++ b/cmake/sim/cadence/xcelium.cmake
@@ -83,6 +83,7 @@ function(xcelium IP_LIB)
## XMSIM command for running simulation
set(__xmsim_cmd xmsim
+ -64bit
${__lib_args}
${ARG_RUN_ARGS}
${LIBRARY}.${ARG_TOP_MODULE}
@@ -156,6 +157,7 @@ function(__xcelium_compile_lib IP_LIB)
set(DESCRIPTION "Compile Verilog and SV files of ${IP_LIB} with xcelium xmvlog in library ${LIBRARY}")
set(__xmvlog_cmd COMMAND xmvlog
+ -64bit
-sv
${ARG_XMVLOG_ARGS}
${SV_ARG_INCDIRS}
@@ -180,6 +182,7 @@ function(__xcelium_compile_lib IP_LIB)
endforeach()
set(__xmvhdl_cmd COMMAND xmvhdl
+ -64bit
${ARG_XMVHDL_ARGS}
${VHDL_ARG_INCDIRS}
${VHDL_CMP_DEFS_ARG}
@@ -189,6 +192,7 @@ function(__xcelium_compile_lib IP_LIB)
endif()
set(__xmelab_cmd COMMAND xmelab
+ -64bit
${ARG_XMELAB_ARGS}
worklib.${IP_NAME}
# -work ${OUTDIR}/${LIBRARY}