Skip to content

Latest commit

 

History

History
14 lines (10 loc) · 927 Bytes

README.md

File metadata and controls

14 lines (10 loc) · 927 Bytes

(Original readme for the template repository here)

This repo is an experiment in using Verilog source files instead of Wokwi diagrams for TinyTapeout, implementing a 5-bit PDM driver.

The Verilog flow is:

  1. Fork this Repo
  2. Create a wokwi project to get an ID
  3. Update WOWKI_PROJECT_ID in Makefile
  4. grep -rl "341154068332282450" ./src | sed -i "s/341154068332282450/YOUR_WOKWI_ID/g" from the top of the repo to find and replace all occurences of the old ID in src with yours, and rename the user_module, user_module_tb and scan_wrapper files to use your ID
  5. Replace behavioural code in user_module_ID.v with your own, likewise change the testbench
  6. Push changes, which triggers the GitHub Action to build the project