Trouble with creation of a custom I- and O-Tile (one direction)

[yannickreiss]

My goal

I want to create custom tiles on the west side with four inputs and on the east side with four outputs each.
For that I tried modifying the RAM_IO, but seem to have made some mistakes.

The problem

The flow does not run through, indicating, that there is some problem with the LUTAB (expects 24 bits, got 4).

I am not sure how the tiles can be connected and specially external ports are defined.

I_TILE

Switch matrix

# Connect input to output
PIN_OUT[0|1|2|3],[A_I|B_I|C_I|D_I]

Tile description in fabric.csv

#!in,4,0,0
TILE,I_TILE,,,,,,,,,,,,,,,,,
#direction,source_name,X-offset,Y-offset,destination_name,wires,,,,,,,,,,,,,
#WEST,NULL,-1,0,EXT_IN,4,,,,,,,,,,,,,
EAST,PIN_OUT,6,0,NULL,4,,,,,,,,,,,,,
JUMP,NULL,0,0,GND,1,,,,,,,,,,,,,
JUMP,NULL,0,0,VCC,1,,,,,,,,,,,,,
BEL,./Tile/I_TILE/I_TILE_port.v,A_,,,,,,,,,,,,,,,,
BEL,./Tile/I_TILE/I_TILE_port.v,B_,,,,,,,,,,,,,,,,
BEL,./Tile/I_TILE/I_TILE_port.v,C_,,,,,,,,,,,,,,,,
BEL,./Tile/I_TILE/I_TILE_port.v,D_,,,,,,,,,,,,,,,,
MATRIX,./Tile/I_TILE/I_TILE_switch_matrix.list,,,,,,,,,,,,,,,,,
EndTILE,,,,,,,,,,,,,,,,,,

BEL

module I_Tile #(
    parameter NoConfigBits = 0
) (
    I,
    O_top
);

  output I;
  (* FABulous, EXTERNAL *) input O_top;

  assign I = O_top;
endmodule

Question

What do I need to change to connect the I/O_TILES to the LUTAB Tiles?

[KelvinChung2000]

This will depend on your LUTAB tile. In your LUTAB tile, it should have something that receives the PIN_OUT.