Skip to content

Latest commit

 

History

History
57 lines (42 loc) · 1.48 KB

README.md

File metadata and controls

57 lines (42 loc) · 1.48 KB

Reference: https://github.com/OpenXiangShan/difftest

Difftest Submodule

Difftest (差分测试) co-sim framework

Usage

  1. Init this submodule in your design, add it to dependency list.
  2. Add difftest to your design.
  3. Generate verilog files for simulation.
  4. Assign SIM_TOP, DESIGN_DIR for difftest/Makefile
  5. cd difftest and make emu, then start simulating & debugging!

To use difftest in XiangShan project:

cd XiangShan
make init
# cd difftest
make emu

API

Difftest functions:

  • DifftestArchEvent (essential)
  • DifftestInstrCommit (essential)
  • DifftestTrapEvent (essential)
  • DifftestCSRState (essential)
  • DifftestArchIntRegState (essential)
  • DifftestArchFpRegState
  • DifftestSbufferEvent
  • DifftestStoreEvent
  • DifftestLoadEvent
  • DifftestAtomicEvent
  • DifftestPtwEvent

Simulation top:

  • LogCtrlIO
  • PerfInfoIO
  • UARTIO

Simulation memory:

  • RAMHelper (essential)

To use difftest, include all these modules / simtopIO in your design.

Further reference