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Add UDP ethernet capability
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Add formal
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Futur small use case to debug system behavior : filter out all packets exept MPID = OPTU and attactch the print to my motivation letter
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Found memory leak in iverilog : look into leak source and eventually fix ?
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Send end of session messages for mold when sequence number for testing the feature and when seq gets to close to the max range of a uint64_t
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Add predictable random number generator and print it's value along fpos for wave creation
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Add ability to start dumping waves at a set time ( future debuging )
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Add system verilog structure to contain itch wave values ( convert field to little endian for readability )
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Better doc
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Add tb feature to skip packets and compare expected skip start-end to mold missing packet detector ( used in re-replay )
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Connect re-replay feature to udp
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Stop being cheap and go buy that fpga ... ( and the fiber switch ) :moneywithwings:
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Implement O+ ?
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reset : SR port on fpga resgisters is active high ... need to move to using reset instead on nreset to prevent infering of an additional not gate ... via a LUT -> git grep nreset