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azido_to_axi_v2_1_0.mpd
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azido_to_axi_v2_1_0.mpd
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###################################################################
##
## Name : azido_to_axi
## Desc : Microprocessor Peripheral Description
## : Derived by Kent Gilson from auto PCore example
##
###################################################################
BEGIN azido_to_axi
## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = VHDL
OPTION IP_GROUP = MICROBLAZE:USER
OPTION DESC = AZIDO_TO_AXI
OPTION ARCH_SUPPORT_MAP = (others=DEVELOPMENT)
OPTION STYLE = MIX
OPTION RUN_NGCBUILD = TRUE
## Bus Interfaces
BUS_INTERFACE BUS = M_AXI, BUS_STD = AXI, BUS_TYPE = MASTER
BUS_INTERFACE BUS = S_AXI, BUS_STD = AXI, BUS_TYPE = SLAVE
## Generics for VHDL or Parameters for Verilog
PARAMETER C_S_AXI_DATA_WIDTH = 32, DT = INTEGER, BUS = S_AXI, ASSIGNMENT = CONSTANT
PARAMETER C_S_AXI_ADDR_WIDTH = 32, DT = INTEGER, BUS = S_AXI, ASSIGNMENT = CONSTANT
PARAMETER C_S_AXI_MIN_SIZE = 0x000001ff, DT = std_logic_vector, BUS = S_AXI
PARAMETER C_USE_WSTRB = 1, DT = INTEGER, ASSIGNMENT = CONSTANT
PARAMETER C_DPHASE_TIMEOUT = 8, DT = INTEGER
PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x200, PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = S_AXI
PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_BASEADDR, ADDRESS = HIGH, BUS = S_AXI
PARAMETER C_FAMILY = virtex6, DT = STRING
PARAMETER C_NUM_REG = 8, DT = INTEGER, ASSIGNMENT = CONSTANT
PARAMETER C_NUM_MEM = 1, DT = INTEGER
PARAMETER C_SLV_AWIDTH = 32, DT = INTEGER
PARAMETER C_SLV_DWIDTH = 32, DT = INTEGER
PARAMETER C_M_AXI_ADDR_WIDTH = 32, DT = INTEGER, BUS = M_AXI, ASSIGNMENT = CONSTANT
PARAMETER C_M_AXI_DATA_WIDTH = 32, DT = INTEGER, BUS = M_AXI, ASSIGNMENT = CONSTANT
PARAMETER C_MAX_BURST_LEN = 256, DT = INTEGER, ASSIGNMENT = CONSTANT
PARAMETER C_NATIVE_DATA_WIDTH = 32, DT = INTEGER, ASSIGNMENT = CONSTANT
PARAMETER C_LENGTH_WIDTH = 12, DT = INTEGER, RANGE = (12:20)
PARAMETER C_ADDR_PIPE_DEPTH = 1, DT = INTEGER, RANGE = (1:14)
PARAMETER C_M_AXI_PROTOCOL = AXI4, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, DT = STRING, BUS = M_AXI
PARAMETER C_S_AXI_PROTOCOL = AXI4LITE, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, DT = STRING, BUS = S_AXI
## Ports
PORT S_AXI_ACLK = "", DIR = I, SIGIS = CLK, BUS = S_AXI
PORT S_AXI_ARESETN = ARESETN, DIR = I, SIGIS = RST, BUS = S_AXI
PORT S_AXI_AWADDR = AWADDR, DIR = I, VEC = [(C_S_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_AWVALID = AWVALID, DIR = I, BUS = S_AXI
PORT S_AXI_WDATA = WDATA, DIR = I, VEC = [(C_S_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_WSTRB = WSTRB, DIR = I, VEC = [((C_S_AXI_DATA_WIDTH/8)-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_WVALID = WVALID, DIR = I, BUS = S_AXI
PORT S_AXI_BREADY = BREADY, DIR = I, BUS = S_AXI
PORT S_AXI_ARADDR = ARADDR, DIR = I, VEC = [(C_S_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_ARVALID = ARVALID, DIR = I, BUS = S_AXI
PORT S_AXI_RREADY = RREADY, DIR = I, BUS = S_AXI
PORT S_AXI_ARREADY = ARREADY, DIR = O, BUS = S_AXI
PORT S_AXI_RDATA = RDATA, DIR = O, VEC = [(C_S_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_RRESP = RRESP, DIR = O, VEC = [1:0], BUS = S_AXI
PORT S_AXI_RVALID = RVALID, DIR = O, BUS = S_AXI
PORT S_AXI_WREADY = WREADY, DIR = O, BUS = S_AXI
PORT S_AXI_BRESP = BRESP, DIR = O, VEC = [1:0], BUS = S_AXI
PORT S_AXI_BVALID = BVALID, DIR = O, BUS = S_AXI
PORT S_AXI_AWREADY = AWREADY, DIR = O, BUS = S_AXI
PORT m_axi_aclk = "", DIR = I, SIGIS = CLK, BUS = M_AXI
PORT m_axi_aresetn = ARESETN, DIR = I, SIGIS = RST, BUS = M_AXI
PORT md_error = "", DIR = O
PORT m_axi_arready = ARREADY, DIR = I, BUS = M_AXI
PORT m_axi_arvalid = ARVALID, DIR = O, BUS = M_AXI
PORT m_axi_araddr = ARADDR, DIR = O, VEC = [(C_M_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE, BUS = M_AXI
PORT m_axi_arlen = ARLEN, DIR = O, VEC = [7:0], BUS = M_AXI
PORT m_axi_arsize = ARSIZE, DIR = O, VEC = [2:0], BUS = M_AXI
PORT m_axi_arburst = ARBURST, DIR = O, VEC = [1:0], BUS = M_AXI
PORT m_axi_arprot = ARPROT, DIR = O, VEC = [2:0], BUS = M_AXI
PORT m_axi_arcache = ARCACHE, DIR = O, VEC = [3:0], BUS = M_AXI
PORT m_axi_rready = RREADY, DIR = O, BUS = M_AXI
PORT m_axi_rvalid = RVALID, DIR = I, BUS = M_AXI
PORT m_axi_rdata = RDATA, DIR = I, VEC = [(C_M_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE, BUS = M_AXI
PORT m_axi_rresp = RRESP, DIR = I, VEC = [1:0], BUS = M_AXI
PORT m_axi_rlast = RLAST, DIR = I, BUS = M_AXI
PORT m_axi_awready = AWREADY, DIR = I, BUS = M_AXI
PORT m_axi_awvalid = AWVALID, DIR = O, BUS = M_AXI
PORT m_axi_awaddr = AWADDR, DIR = O, VEC = [(C_M_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE, BUS = M_AXI
PORT m_axi_awlen = AWLEN, DIR = O, VEC = [7:0], BUS = M_AXI
PORT m_axi_awsize = AWSIZE, DIR = O, VEC = [2:0], BUS = M_AXI
PORT m_axi_awburst = AWBURST, DIR = O, VEC = [1:0], BUS = M_AXI
PORT m_axi_awprot = AWPROT, DIR = O, VEC = [2:0], BUS = M_AXI
PORT m_axi_awcache = AWCACHE, DIR = O, VEC = [3:0], BUS = M_AXI
PORT m_axi_wready = WREADY, DIR = I, BUS = M_AXI
PORT m_axi_wvalid = WVALID, DIR = O, BUS = M_AXI
PORT m_axi_wdata = WDATA, DIR = O, VEC = [(C_M_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE, BUS = M_AXI
PORT m_axi_wstrb = WSTRB, DIR = O, VEC = [((C_M_AXI_DATA_WIDTH/8)-1):0], ENDIAN = LITTLE, BUS = M_AXI
PORT m_axi_wlast = WLAST, DIR = O, BUS = M_AXI
PORT m_axi_bready = BREADY, DIR = O, BUS = M_AXI
PORT m_axi_bvalid = BVALID, DIR = I, BUS = M_AXI
PORT m_axi_bresp = BRESP, DIR = I, VEC = [1:0], BUS = M_AXI
END