RT 159670: adjust eNVM accesss timings depending on CPU speed for LPC1788

Author: ayurtsev

cpu/arm_cortexm3/lpc178x/clock.c

@@ -469,6 +469,24 @@ static void clock_setup(void)
  */
 void clock_init(void)
 {
+	/* adjust eNVM access timings */
+	if (LPC178X_CPU_RATE/1000000 >= 80) {
+	    LPC178X_SCC->flashcfg &= ~LPC178X_SCC_FLASHCFG_FTIM_MSK;
+	    LPC178X_SCC->flashcfg |= LPC178X_SCC_FLASHCFG_FTIM_5CLK;
+	} else if (LPC178X_CPU_RATE/1000000 >= 60) {
+	    LPC178X_SCC->flashcfg &= ~LPC178X_SCC_FLASHCFG_FTIM_MSK;
+	    LPC178X_SCC->flashcfg |= LPC178X_SCC_FLASHCFG_FTIM_4CLK;
+	} else if (LPC178X_CPU_RATE/1000000 >= 40) {
+	    LPC178X_SCC->flashcfg &= ~LPC178X_SCC_FLASHCFG_FTIM_MSK;
+	    LPC178X_SCC->flashcfg |= LPC178X_SCC_FLASHCFG_FTIM_3CLK;
+	} else if (LPC178X_CPU_RATE/1000000 >= 20) {
+	    LPC178X_SCC->flashcfg &= ~LPC178X_SCC_FLASHCFG_FTIM_MSK;
+	    LPC178X_SCC->flashcfg |= LPC178X_SCC_FLASHCFG_FTIM_2CLK;
+	} else {
+	    LPC178X_SCC->flashcfg &= ~LPC178X_SCC_FLASHCFG_FTIM_MSK;
+	    LPC178X_SCC->flashcfg |= LPC178X_SCC_FLASHCFG_FTIM_1CLK;
+	}
+
 	clock_setup();
 
 	/*

include/asm-arm/arch-lpc178x/lpc178x.h

@@ -61,6 +61,17 @@
 #define LPC178X_SCC_PCONP_PCENET_MSK	(1 << 30)
 #define LPC178X_SCC_PCONP_PCUSB_MSK	(1 << 31)
 
+/*
+ * Flash Accelerator Configuration register values
+ */
+#define LPC178X_SCC_FLASHCFG_FTIM_MSK	(0xF << 12)
+#define LPC178X_SCC_FLASHCFG_FTIM_1CLK	(0x0 << 12)
+#define LPC178X_SCC_FLASHCFG_FTIM_2CLK	(0x1 << 12)
+#define LPC178X_SCC_FLASHCFG_FTIM_3CLK	(0x2 << 12)
+#define LPC178X_SCC_FLASHCFG_FTIM_4CLK	(0x3 << 12)
+#define LPC178X_SCC_FLASHCFG_FTIM_5CLK	(0x4 << 12)
+#define LPC178X_SCC_FLASHCFG_FTIM_6CLK	(0x5 << 12)
+
 /*
  * PLL register map
  * Used for PLL0 at 0x400FC080 and for PLL1 at 0x400FC0A0.
@@ -84,7 +95,10 @@ struct lpc178x_pll_regs {
  */
 struct lpc178x_scc_regs {
 	/* 0x400FC000: Flash Accelerator Configuration Register */
-	u32 rsv0[32];
+	u32 flashcfg;
+
+	/* 0x400FC004: reserved */
+	u32 rsv0[31];
 
 	/* 0x400FC080: PLL0 registers */
 	struct lpc178x_pll_regs pll0; /* PLL0 registers */