stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.002076                       # Number of seconds simulated
sim_ticks                                  2076353830                       # Number of ticks simulated
final_tick                                 2076353830                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 117706                       # Simulator instruction rate (inst/s)
host_op_rate                                   250246                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               88575327                       # Simulator tick rate (ticks/s)
host_mem_usage                                2400964                       # Number of bytes of host memory used
host_seconds                                    23.44                       # Real time elapsed on the host
sim_insts                                     2759218                       # Number of instructions simulated
sim_ops                                       5866170                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED   2076353830                       # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::cpu0.inst          50432                       # Number of bytes read from this memory
system.mem_ctrls.bytes_read::cpu0.data         322112                       # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total             372544                       # Number of bytes read from this memory
system.mem_ctrls.bytes_inst_read::cpu0.inst        50432                       # Number of instructions bytes read from this memory
system.mem_ctrls.bytes_inst_read::total         50432                       # Number of instructions bytes read from this memory
system.mem_ctrls.num_reads::cpu0.inst             788                       # Number of read requests responded to by this memory
system.mem_ctrls.num_reads::cpu0.data            5033                       # Number of read requests responded to by this memory
system.mem_ctrls.num_reads::total                5821                       # Number of read requests responded to by this memory
system.mem_ctrls.bw_read::cpu0.inst          24288731                       # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_read::cpu0.data         155133482                       # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_read::total             179422213                       # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_inst_read::cpu0.inst     24288731                       # Instruction read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_inst_read::total         24288731                       # Instruction read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_total::cpu0.inst         24288731                       # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.bw_total::cpu0.data        155133482                       # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.bw_total::total            179422213                       # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.readReqs                        5821                       # Number of read requests accepted
system.mem_ctrls.writeReqs                          0                       # Number of write requests accepted
system.mem_ctrls.readBursts                      5821                       # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrls.writeBursts                        0                       # Number of DRAM write bursts, including those merged in the write queue
system.mem_ctrls.bytesReadDRAM                 372544                       # Total number of bytes read from DRAM
system.mem_ctrls.bytesReadWrQ                       0                       # Total number of bytes read from write queue
system.mem_ctrls.bytesWritten                       0                       # Total number of bytes written to DRAM
system.mem_ctrls.bytesReadSys                  372544                       # Total read bytes from the system interface side
system.mem_ctrls.bytesWrittenSys                    0                       # Total written bytes from the system interface side
system.mem_ctrls.servicedByWrQ                      0                       # Number of DRAM read bursts serviced by the write queue
system.mem_ctrls.mergedWrBursts                     0                       # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
system.mem_ctrls.perBankRdBursts::0               342                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::1               372                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::2               309                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::3               235                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::4               259                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::5               318                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::6               310                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::7               357                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::8               278                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::9               392                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::10              499                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::11              444                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::12              414                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::13              449                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::14              420                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::15              423                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::0                 0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::1                 0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::2                 0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::3                 0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::4                 0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::5                 0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::6                 0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::7                 0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::8                 0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::9                 0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::10                0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::11                0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::12                0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::13                0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::14                0                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::15                0                       # Per bank write bursts
system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
system.mem_ctrls.totGap                    2076136203                       # Total gap between requests
system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::3                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::4                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::5                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::6                  5821                       # Read request sizes (log2)
system.mem_ctrls.writePktSize::0                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::1                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::2                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::3                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::6                    0                       # Write request sizes (log2)
system.mem_ctrls.rdQLenPdf::0                    4859                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::1                     835                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::2                      92                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3                      30                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::4                       4                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::5                       1                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::6                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::7                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::8                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::9                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::10                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::11                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::12                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::13                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::14                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::15                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::16                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::17                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::18                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::19                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::20                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::21                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::22                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::23                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::24                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::25                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::26                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::27                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::28                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::29                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::30                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::31                      0                       # What read queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::0                       0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::1                       0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::2                       0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::3                       0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::4                       0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::5                       0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::6                       0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::7                       0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::8                       0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::9                       0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::10                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::11                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::12                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::13                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::14                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::15                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::16                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::17                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::18                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::19                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::20                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::21                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::22                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::23                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::24                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::25                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::26                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::27                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::28                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::29                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::30                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::31                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::32                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::33                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::34                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::35                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::36                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::37                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::38                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::39                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::40                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::41                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::42                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::43                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::44                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::45                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::46                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::47                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::48                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::49                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::50                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::51                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::52                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::53                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::54                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::55                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::56                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::57                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::58                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::59                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::60                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
system.mem_ctrls.bytesPerActivate::samples         1641                       # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::mean    226.008531                       # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::gmean   137.932276                       # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::stdev   280.917282                       # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::0-127          733     44.67%     44.67% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::128-255          521     31.75%     76.42% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::256-383          130      7.92%     84.34% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::384-511           40      2.44%     86.78% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::512-639           32      1.95%     88.73% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::640-767           21      1.28%     90.01% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::768-895           17      1.04%     91.04% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::896-1023           15      0.91%     91.96% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::1024-1151          132      8.04%    100.00% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::total         1641                       # Bytes accessed per row activation
system.mem_ctrls.totQLat                    136364089                       # Total ticks spent queuing
system.mem_ctrls.totMemAccLat               245507839                       # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrls.totBusLat                   29105000                       # Total ticks spent in databus transfers
system.mem_ctrls.avgQLat                     23426.23                       # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat                    5000.00                       # Average bus latency per DRAM burst
system.mem_ctrls.avgMemAccLat                42176.23                       # Average memory access latency per DRAM burst
system.mem_ctrls.avgRdBW                       179.42                       # Average DRAM read bandwidth in MiByte/s
system.mem_ctrls.avgWrBW                         0.00                       # Average achieved write bandwidth in MiByte/s
system.mem_ctrls.avgRdBWSys                    179.42                       # Average system read bandwidth in MiByte/s
system.mem_ctrls.avgWrBWSys                      0.00                       # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
system.mem_ctrls.busUtil                         1.40                       # Data bus utilization in percentage
system.mem_ctrls.busUtilRead                     1.40                       # Data bus utilization in percentage for reads
system.mem_ctrls.busUtilWrite                    0.00                       # Data bus utilization in percentage for writes
system.mem_ctrls.avgRdQLen                       1.54                       # Average read queue length when enqueuing
system.mem_ctrls.avgWrQLen                       0.00                       # Average write queue length when enqueuing
system.mem_ctrls.readRowHits                     4171                       # Number of row buffer hits during reads
system.mem_ctrls.writeRowHits                       0                       # Number of row buffer hits during writes
system.mem_ctrls.readRowHitRate                 71.65                       # Row buffer hit rate for reads
system.mem_ctrls.writeRowHitRate                  nan                       # Row buffer hit rate for writes
system.mem_ctrls.avgGap                     356663.15                       # Average gap between requests
system.mem_ctrls.pageHitRate                    71.65                       # Row buffer hit rate, read and write combined
system.mem_ctrls_0.actEnergy                  5526360                       # Energy for activate commands per rank (pJ)
system.mem_ctrls_0.preEnergy                  2918355                       # Energy for precharge commands per rank (pJ)
system.mem_ctrls_0.readEnergy                17864280                       # Energy for read commands per rank (pJ)
system.mem_ctrls_0.writeEnergy                      0                       # Energy for write commands per rank (pJ)
system.mem_ctrls_0.refreshEnergy         84820320.000000                       # Energy for refresh commands per rank (pJ)
system.mem_ctrls_0.actBackEnergy             49153380                       # Energy for active background per rank (pJ)
system.mem_ctrls_0.preBackEnergy              3847680                       # Energy for precharge background per rank (pJ)
system.mem_ctrls_0.actPowerDownEnergy       275203980                       # Energy for active power-down per rank (pJ)
system.mem_ctrls_0.prePowerDownEnergy        77027520                       # Energy for precharge power-down per rank (pJ)
system.mem_ctrls_0.selfRefreshEnergy        289242285                       # Energy for self refresh per rank (pJ)
system.mem_ctrls_0.totalEnergy              805699500                       # Total energy per rank (pJ)
system.mem_ctrls_0.averagePower            388.035524                       # Core power per rank (mW)
system.mem_ctrls_0.totalIdleTime           1958218081                       # Total Idle time Per DRAM Rank
system.mem_ctrls_0.memoryStateTime::IDLE      6507219                       # Time in different power states
system.mem_ctrls_0.memoryStateTime::REF      36078000                       # Time in different power states
system.mem_ctrls_0.memoryStateTime::SREF   1154219053                       # Time in different power states
system.mem_ctrls_0.memoryStateTime::PRE_PDN    200589004                       # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT      75396872                       # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT_PDN    603563682                       # Time in different power states
system.mem_ctrls_1.actEnergy                  6254640                       # Energy for activate commands per rank (pJ)
system.mem_ctrls_1.preEnergy                  3309240                       # Energy for precharge commands per rank (pJ)
system.mem_ctrls_1.readEnergy                23697660                       # Energy for read commands per rank (pJ)
system.mem_ctrls_1.writeEnergy                      0                       # Energy for write commands per rank (pJ)
system.mem_ctrls_1.refreshEnergy         109405920.000000                       # Energy for refresh commands per rank (pJ)
system.mem_ctrls_1.actBackEnergy             64221900                       # Energy for active background per rank (pJ)
system.mem_ctrls_1.preBackEnergy              6214080                       # Energy for precharge background per rank (pJ)
system.mem_ctrls_1.actPowerDownEnergy       396939450                       # Energy for active power-down per rank (pJ)
system.mem_ctrls_1.prePowerDownEnergy        81984480                       # Energy for precharge power-down per rank (pJ)
system.mem_ctrls_1.selfRefreshEnergy        212081640                       # Energy for self refresh per rank (pJ)
system.mem_ctrls_1.totalEnergy              904109010                       # Total energy per rank (pJ)
system.mem_ctrls_1.averagePower            435.430844                       # Core power per rank (mW)
system.mem_ctrls_1.totalIdleTime           1919308434                       # Total Idle time Per DRAM Rank
system.mem_ctrls_1.memoryStateTime::IDLE     10948051                       # Time in different power states
system.mem_ctrls_1.memoryStateTime::REF      46502000                       # Time in different power states
system.mem_ctrls_1.memoryStateTime::SREF    835352699                       # Time in different power states
system.mem_ctrls_1.memoryStateTime::PRE_PDN    213494127                       # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT      99595345                       # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN    870461608                       # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED   2076353830                       # Cumulative time (in ticks) in various power states
system.cpu0.branchPred.lookups                1166727                       # Number of BP lookups
system.cpu0.branchPred.condPredicted          1166727                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect            47557                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups              857045                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits                      0                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct             0.000000                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                 133586                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect              4031                       # Number of incorrect RAS predictions.
system.cpu0.branchPred.indirectLookups         857045                       # Number of indirect predictor lookups.
system.cpu0.branchPred.indirectHits            472004                       # Number of indirect target hits.
system.cpu0.branchPred.indirectMisses          385041                       # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted         9747                       # Number of mispredicted indirect branches.
system.cpu_voltage_domain.voltage                   1                       # Voltage in Volts
system.cpu_clk_domain.clock                       769                       # Clock period in ticks
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED   2076353830                       # Cumulative time (in ticks) in various power states
system.cpu0.apic_clk_domain.clock               12304                       # Clock period in ticks
system.cpu0.interrupts.pwrStateResidencyTicks::UNDEFINED   2076353830                       # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED   2076353830                       # Cumulative time (in ticks) in various power states
system.cpu0.workload.num_syscalls                  20                       # Number of system calls
system.cpu0.pwrStateResidencyTicks::ON     2076353830                       # Cumulative time (in ticks) in various power states
system.cpu0.numCycles                         2700071                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles             61118                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                       4877053                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                    1166727                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches            605590                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                      2526631                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                  95451                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                         3                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles                 597                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles         1946                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles           14                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles           54                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                   808627                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes                  670                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.rateDist::samples           2638088                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             3.824738                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            3.430752                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                  950723     36.04%     36.04% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                   94255      3.57%     39.61% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                   84055      3.19%     42.80% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                  151555      5.74%     48.54% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                  195485      7.41%     55.95% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  107249      4.07%     60.02% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                  141884      5.38%     65.40% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                   99579      3.77%     69.17% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                  813303     30.83%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total             2638088                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.432110                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       1.806268                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                  230279                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles              1067678                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                  1042296                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles               250110                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles                 47725                       # Number of cycles decode is squashing
system.cpu0.decode.DecodedInsts               9124226                       # Number of instructions handled by decode
system.cpu0.rename.SquashCycles                 47725                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                  337268                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles                 515518                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles          5684                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                  1178411                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles               553482                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts               8807153                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                15303                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                163374                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents                 19985                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents                305194                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands            9882593                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups             22974084                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups        12630840                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups           766346                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps              6499635                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                 3382958                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts              1429                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts          1460                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                   862340                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads             1072597                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores             501235                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads            37279                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores           17970                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                   8319603                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded               1143                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                  7600451                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued            56276                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined        2454576                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined      2897892                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved          1123                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples      2638088                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        2.881045                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       2.863083                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0            1012010     38.36%     38.36% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1             147016      5.57%     43.93% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2             193944      7.35%     51.29% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3             230762      8.75%     60.03% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4             204006      7.73%     67.77% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5             168937      6.40%     74.17% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6             252984      9.59%     83.76% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7             232784      8.82%     92.58% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8             195645      7.42%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total        2638088                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                 213385     94.42%     94.42% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                     0      0.00%     94.42% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     94.42% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                 1844      0.82%     95.24% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     95.24% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     95.24% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     95.24% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMultAcc                0      0.00%     95.24% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     95.24% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMisc                   0      0.00%     95.24% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     95.24% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     95.24% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     95.24% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     95.24% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     95.24% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     95.24% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     95.24% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     95.24% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     95.24% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     95.24% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     95.24% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     95.24% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     95.24% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     95.24% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     95.24% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     95.24% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     95.24% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     95.24% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     95.24% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     95.24% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     95.24% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead                  6430      2.85%     98.09% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite                 4120      1.82%     99.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMemRead              186      0.08%     99.99% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMemWrite              19      0.01%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass            92468      1.22%      1.22% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu              5711448     75.15%     76.36% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult                9571      0.13%     76.49% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                16935      0.22%     76.71% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd             294242      3.87%     80.58% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     80.58% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     80.58% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     80.58% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMultAcc              0      0.00%     80.58% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     80.58% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMisc                 0      0.00%     80.58% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     80.58% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     80.58% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     80.58% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     80.58% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     80.58% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     80.58% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     80.58% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     80.58% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     80.58% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     80.58% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     80.58% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     80.58% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     80.58% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     80.58% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     80.58% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     80.58% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     80.58% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     80.58% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     80.58% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     80.58% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     80.58% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead              893070     11.75%     92.33% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite             460114      6.05%     98.39% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMemRead         120395      1.58%     99.97% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMemWrite          2208      0.03%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total               7600451                       # Type of FU issued
system.cpu0.iq.rate                          2.814908                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                     225984                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.029733                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads          17283694                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes         10203302                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses      7045362                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads             837556                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes            572073                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses       410308                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses               7315045                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                 418922                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          160344                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads       300485                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses          333                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation           59                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores       104735                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads         2114                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked         2419                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles                 47725                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                 333270                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles                 6046                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts            8320746                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts             1498                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts              1072597                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts              501235                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts               963                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                  2949                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents                 2095                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents            59                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect         19183                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect        38779                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts               57962                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts              7493920                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts               988370                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           106531                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                            0                       # number of nop insts executed
system.cpu0.iew.exec_refs                     1442066                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                  814959                       # Number of branches executed
system.cpu0.iew.exec_stores                    453696                       # Number of stores executed
system.cpu0.iew.exec_rate                    2.775453                       # Inst execution rate
system.cpu0.iew.wb_sent                       7474772                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                      7455670                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                  5461174                       # num instructions producing a value
system.cpu0.iew.wb_consumers                  9795774                       # num instructions consuming a value
system.cpu0.iew.wb_rate                      2.761287                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.557503                       # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts        2454580                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls             20                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts            47683                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples      2287556                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     2.564383                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     3.108576                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0       999246     43.68%     43.68% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1       194034      8.48%     52.16% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2       277574     12.13%     64.30% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3       176186      7.70%     72.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4        85299      3.73%     75.73% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5        39032      1.71%     77.44% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6        21488      0.94%     78.37% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7        34430      1.51%     79.88% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8       460267     20.12%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total      2287556                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts             2759218                       # Number of instructions committed
system.cpu0.commit.committedOps               5866170                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                       1168612                       # Number of memory references committed
system.cpu0.commit.loads                       772112                       # Number of loads committed
system.cpu0.commit.membars                          0                       # Number of memory barriers committed
system.cpu0.commit.branches                    660175                       # Number of branches committed
system.cpu0.commit.fp_insts                    305483                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                  5626119                       # Number of committed integer instructions.
system.cpu0.commit.function_calls               60183                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass        59621      1.02%      1.02% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu         4394757     74.92%     75.93% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult           5000      0.09%     76.02% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv           16914      0.29%     76.31% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd        221266      3.77%     80.08% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     80.08% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     80.08% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     80.08% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMultAcc            0      0.00%     80.08% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     80.08% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMisc            0      0.00%     80.08% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     80.08% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     80.08% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     80.08% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     80.08% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     80.08% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     80.08% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     80.08% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     80.08% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     80.08% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     80.08% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     80.08% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     80.08% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     80.08% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     80.08% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     80.08% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     80.08% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     80.08% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc            0      0.00%     80.08% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     80.08% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     80.08% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     80.08% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead         690085     11.76%     91.84% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite        394338      6.72%     98.56% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMemRead        82027      1.40%     99.96% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMemWrite         2162      0.04%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total          5866170                       # Class of committed instruction
system.cpu0.commit.bw_lim_events               460267                       # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads                    10148039                       # The number of ROB reads
system.cpu0.rob.rob_writes                   16994935                       # The number of ROB writes
system.cpu0.timesIdled                            435                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                          61983                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.committedInsts                    2759218                       # Number of Instructions Simulated
system.cpu0.committedOps                      5866170                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              0.978564                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        0.978564                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              1.021906                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        1.021906                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads                10486033                       # number of integer regfile reads
system.cpu0.int_regfile_writes                5829762                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                   701310                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                  353911                       # number of floating regfile writes
system.cpu0.cc_regfile_reads                  4709856                       # number of cc regfile reads
system.cpu0.cc_regfile_writes                 2149037                       # number of cc regfile writes
system.cpu0.misc_regfile_reads                3004030                       # number of misc regfile reads
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED   2076353830                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements            20428                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          476.395752                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs            1156389                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs            20940                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            55.223926                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle        602300794                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   476.395752                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.930460                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.930460                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0           78                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          213                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2          221                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses          9779636                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses         9779636                       # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED   2076353830                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data       763212                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total         763212                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data       392625                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total        392625                       # number of WriteReq hits
system.cpu0.dcache.demand_hits::cpu0.data      1155837                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total         1155837                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data      1155837                       # number of overall hits
system.cpu0.dcache.overall_hits::total        1155837                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data        59994                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total        59994                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data         4006                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total         4006                       # number of WriteReq misses
system.cpu0.dcache.demand_misses::cpu0.data        64000                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total         64000                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data        64000                       # number of overall misses
system.cpu0.dcache.overall_misses::total        64000                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   3379132110                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   3379132110                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data    409591701                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total    409591701                       # number of WriteReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data   3788723811                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total   3788723811                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data   3788723811                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total   3788723811                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data       823206                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total       823206                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data       396631                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total       396631                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data      1219837                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total      1219837                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data      1219837                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total      1219837                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.072878                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.072878                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.010100                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.010100                       # miss rate for WriteReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.052466                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.052466                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.052466                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.052466                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 56324.500950                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 56324.500950                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 102244.558412                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 102244.558412                       # average WriteReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 59198.809547                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 59198.809547                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 59198.809547                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 59198.809547                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs        10060                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs              694                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    14.495677                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks        20428                       # number of writebacks
system.cpu0.dcache.writebacks::total            20428                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        42513                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total        42513                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data            2                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total            2                       # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data        42515                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total        42515                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data        42515                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total        42515                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data        17481                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total        17481                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data         4004                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total         4004                       # number of WriteReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data        21485                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total        21485                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data        21485                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total        21485                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data    655550199                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total    655550199                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data    406369591                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total    406369591                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   1061919790                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total   1061919790                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   1061919790                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total   1061919790                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.021235                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.021235                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.010095                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.010095                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.017613                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.017613                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.017613                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.017613                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37500.726446                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37500.726446                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 101490.906843                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 101490.906843                       # average WriteReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 49426.101466                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 49426.101466                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 49426.101466                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 49426.101466                       # average overall mshr miss latency
system.cpu0.dtb_walker_cache.tags.pwrStateResidencyTicks::UNDEFINED   2076353830                       # Cumulative time (in ticks) in various power states
system.cpu0.dtb_walker_cache.tags.replacements            0                       # number of replacements
system.cpu0.dtb_walker_cache.tags.tagsinuse            0                       # Cycle average of tags in use
system.cpu0.dtb_walker_cache.tags.total_refs            0                       # Total number of references to valid blocks.
system.cpu0.dtb_walker_cache.tags.sampled_refs            0                       # Sample count of references to valid blocks.
system.cpu0.dtb_walker_cache.tags.avg_refs          nan                       # Average number of references to valid blocks.
system.cpu0.dtb_walker_cache.tags.warmup_cycle            0                       # Cycle when the warmup percentage was hit.
system.cpu0.dtb_walker_cache.tags.tag_accesses            0                       # Number of tag accesses
system.cpu0.dtb_walker_cache.tags.data_accesses            0                       # Number of data accesses
system.cpu0.dtb_walker_cache.pwrStateResidencyTicks::UNDEFINED   2076353830                       # Cumulative time (in ticks) in various power states
system.cpu0.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu0.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED   2076353830                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements              300                       # number of replacements
system.cpu0.icache.tags.tagsinuse          483.471750                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs             807518                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs              809                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs           998.168109                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   483.471750                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.944281                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.944281                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          509                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           72                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1           17                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2           43                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3          377                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024     0.994141                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses          6469817                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses         6469817                       # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED   2076353830                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst       807518                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total         807518                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst       807518                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total          807518                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst       807518                       # number of overall hits
system.cpu0.icache.overall_hits::total         807518                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst         1108                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total         1108                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst         1108                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total          1108                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst         1108                       # number of overall misses
system.cpu0.icache.overall_misses::total         1108                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst    161734542                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total    161734542                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst    161734542                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total    161734542                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst    161734542                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total    161734542                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst       808626                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total       808626                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst       808626                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total       808626                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst       808626                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total       808626                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.001370                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.001370                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.001370                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.001370                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.001370                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.001370                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 145969.803249                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 145969.803249                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 145969.803249                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 145969.803249                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 145969.803249                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 145969.803249                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs          728                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets          633                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs               10                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              2                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    72.800000                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets   316.500000                       # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks          300                       # number of writebacks
system.cpu0.icache.writebacks::total              300                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst          298                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total          298                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst          298                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total          298                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst          298                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total          298                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          810                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total          810                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst          810                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total          810                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst          810                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total          810                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst    118577493                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total    118577493                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst    118577493                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total    118577493                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst    118577493                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total    118577493                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.001002                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.001002                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.001002                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.001002                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.001002                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.001002                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 146391.966667                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 146391.966667                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 146391.966667                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 146391.966667                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 146391.966667                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 146391.966667                       # average overall mshr miss latency
system.cpu0.itb_walker_cache.tags.pwrStateResidencyTicks::UNDEFINED   2076353830                       # Cumulative time (in ticks) in various power states
system.cpu0.itb_walker_cache.tags.replacements            0                       # number of replacements
system.cpu0.itb_walker_cache.tags.tagsinuse            0                       # Cycle average of tags in use
system.cpu0.itb_walker_cache.tags.total_refs            0                       # Total number of references to valid blocks.
system.cpu0.itb_walker_cache.tags.sampled_refs            0                       # Sample count of references to valid blocks.
system.cpu0.itb_walker_cache.tags.avg_refs          nan                       # Average number of references to valid blocks.
system.cpu0.itb_walker_cache.tags.warmup_cycle            0                       # Cycle when the warmup percentage was hit.
system.cpu0.itb_walker_cache.tags.tag_accesses            0                       # Number of tag accesses
system.cpu0.itb_walker_cache.tags.data_accesses            0                       # Number of data accesses
system.cpu0.itb_walker_cache.pwrStateResidencyTicks::UNDEFINED   2076353830                       # Cumulative time (in ticks) in various power states
system.cpu0.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu0.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED   2076353830                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.tags.replacements            4741                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse        2668.208314                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs             34178                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs            8837                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            3.867602                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle      1984619820                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks    28.808827                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst   339.784299                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data  2299.615187                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.007033                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.082955                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.561429                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.651418                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          213                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          349                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         2678                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3          856                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses          180905                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses         180905                       # Number of data accesses
system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED   2076353830                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.WritebackDirty_hits::writebacks        17986                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total        17986                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks         2736                       # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total         2736                       # number of WritebackClean hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data          544                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total          544                       # number of UpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data          656                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total          656                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst           12                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total           12                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data        12449                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total        12449                       # number of ReadSharedReq hits
system.cpu0.l2cache.demand_hits::cpu0.inst           12                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data        13105                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total          13117                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.inst           12                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data        13105                       # number of overall hits
system.cpu0.l2cache.overall_hits::total         13117                       # number of overall hits
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data            1                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total            1                       # number of UpgradeReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data         2803                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total         2803                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst          798                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total          798                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data         5032                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total         5032                       # number of ReadSharedReq misses
system.cpu0.l2cache.demand_misses::cpu0.inst          798                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data         7835                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total         8633                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.inst          798                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data         7835                       # number of overall misses
system.cpu0.l2cache.overall_misses::total         8633                       # number of overall misses
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data    387757484                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total    387757484                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst    117171761                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total    117171761                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data    502486132                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total    502486132                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst    117171761                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data    890243616                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total   1007415377                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst    117171761                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data    890243616                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total   1007415377                       # number of overall miss cycles
system.cpu0.l2cache.WritebackDirty_accesses::writebacks        17986                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total        17986                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks         2736                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total         2736                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data          545                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total          545                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data         3459                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total         3459                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst          810                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total          810                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data        17481                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total        17481                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.inst          810                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data        20940                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total        21750                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst          810                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data        20940                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total        21750                       # number of overall (read+write) accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.001835                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.001835                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.810350                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.810350                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.985185                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.985185                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.287855                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.287855                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.985185                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.374164                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.396920                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.985185                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.374164                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.396920                       # miss rate for overall accesses
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 138336.597931                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 138336.597931                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 146831.780702                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 146831.780702                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 99858.134340                       # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 99858.134340                       # average ReadSharedReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 146831.780702                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 113623.945884                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 116693.545349                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 146831.780702                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 113623.945884                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 116693.545349                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.writebacks::writebacks         4741                       # number of writebacks
system.cpu0.l2cache.writebacks::total            4741                       # number of writebacks
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data            1                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total            1                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data         2803                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total         2803                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst          798                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total          798                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data         5032                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total         5032                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst          798                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data         7835                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total         8633                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst          798                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data         7835                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total         8633                       # number of overall MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data        39219                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total        39219                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data    361891400                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total    361891400                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst    109817045                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total    109817045                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data    456050836                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total    456050836                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst    109817045                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data    817942236                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total    927759281                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst    109817045                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data    817942236                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total    927759281                       # number of overall MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.001835                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.001835                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.810350                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.810350                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.985185                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.985185                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.287855                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.287855                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.985185                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.374164                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.396920                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.985185                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.374164                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.396920                       # mshr miss rate for overall accesses
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data        39219                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total        39219                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 129108.597931                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 129108.597931                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 137615.344612                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 137615.344612                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 90630.134340                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 90630.134340                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 137615.344612                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 104395.945884                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 107466.614271                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 137615.344612                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 104395.945884                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 107466.614271                       # average overall mshr miss latency
system.cpu0.toL2Bus.snoop_filter.tot_requests        43023                       # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests        21274                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests            6                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops          612                       # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops          612                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED   2076353830                       # Cumulative time (in ticks) in various power states
system.cpu0.toL2Bus.trans_dist::ReadResp        18290                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty        21703                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean         3766                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq          545                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp          545                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq         3459                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp         3459                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq          810                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq        17481                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side         1919                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side        63398                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total            65317                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side        70976                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2647552                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total           2718528                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                       4741                       # Total snoops (count)
system.cpu0.toL2Bus.snoopTraffic               303424                       # Total snoop traffic (bytes)
system.cpu0.toL2Bus.snoop_fanout::samples        27036                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       0.022895                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.149573                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0             26417     97.71%     97.71% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1               619      2.29%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2                 0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::3                 0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::4                 0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total         27036                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy      64964351                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          3.1                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy      1866363                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy     48727685                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          2.3                       # Layer utilization (%)
system.cpu1.branchPred.lookups                      0                       # Number of BP lookups
system.cpu1.branchPred.condPredicted                0                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect                0                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups                   0                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits                      0                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct                  nan                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS                      0                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect                 0                       # Number of incorrect RAS predictions.
system.cpu1.branchPred.indirectLookups              0                       # Number of indirect predictor lookups.
system.cpu1.branchPred.indirectHits                 0                       # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses               0                       # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted            0                       # Number of mispredicted indirect branches.
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED   2076353830                       # Cumulative time (in ticks) in various power states
system.cpu1.apic_clk_domain.clock               12304                       # Clock period in ticks
system.cpu1.interrupts.pwrStateResidencyTicks::UNDEFINED   2076353830                       # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED   2076353830                       # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::ON     2076353830                       # Cumulative time (in ticks) in various power states
system.cpu1.numCycles                               0                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.rateDist::samples                 0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean                  nan                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev                 nan                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                       0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                       0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                       0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                       0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                       0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                       0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                       0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                       0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                       0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total                   0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.idleRate                        nan                       # Percent of cycles fetch was idle
system.cpu1.fetch.branchRate                      nan                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                            nan                       # Number of inst fetches per cycle
system.cpu1.rename.serializeStallCycles             0                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.serializingInsts                 0                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts             0                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                        0                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads                   0                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores                  0                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads                0                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores               0                       # Number of conflicting stores.
system.cpu1.iq.issued_per_cycle::samples            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean             nan                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev            nan                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0                  0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1                  0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2                  0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3                  0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4                  0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5                  0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6                  0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7                  0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8                  0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total              0                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0                       # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                      0                       # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                     0                       # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0                       # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0                       # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0                       # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0                       # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0                       # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMultAcc                0                       # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0                       # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMisc                   0                       # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0                       # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0                       # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0                       # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0                       # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0                       # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0                       # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0                       # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0                       # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0                       # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0                       # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0                       # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0                       # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0                       # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0                       # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0                       # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0                       # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0                       # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0                       # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0                       # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0                       # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0                       # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead                     0                       # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite                    0                       # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMemRead                0                       # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMemWrite               0                       # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0                       # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0                       # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass                0                       # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu                    0                       # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult                   0                       # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0                       # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0                       # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0                       # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0                       # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0                       # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMultAcc              0                       # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0                       # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMisc                 0                       # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0                       # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0                       # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0                       # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0                       # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0                       # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0                       # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0                       # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0                       # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0                       # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0                       # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0                       # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0                       # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0                       # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0                       # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0                       # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0                       # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0                       # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc             0                       # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0                       # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0                       # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0                       # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead                   0                       # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite                  0                       # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMemRead              0                       # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMemWrite             0                       # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0                       # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0                       # Type of FU issued
system.cpu1.iq.FU_type_0::total                     0                       # Type of FU issued
system.cpu1.iq.rate                               nan                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                          0                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                       nan                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads                 0                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes                0                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses            0                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses                     0                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads               0                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads            0                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses            0                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation            0                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores            0                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles                     0                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                      0                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles                    0                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts                  0                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts                    0                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts                   0                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts                 0                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                     0                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents             0                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect             0                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect            0                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts                   0                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts                    0                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts                    0                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts                0                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                            0                       # number of nop insts executed
system.cpu1.iew.exec_refs                           0                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                       0                       # Number of branches executed
system.cpu1.iew.exec_stores                         0                       # Number of stores executed
system.cpu1.iew.exec_rate                         nan                       # Inst execution rate
system.cpu1.iew.wb_sent                             0                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                            0                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                        0                       # num instructions producing a value
system.cpu1.iew.wb_consumers                        0                       # num instructions consuming a value
system.cpu1.iew.wb_rate                           nan                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                         nan                       # average fanout of values written-back
system.cpu1.commit.committed_per_cycle::samples            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean          nan                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev          nan                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total            0                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts                   0                       # Number of instructions committed
system.cpu1.commit.committedOps                     0                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                             0                       # Number of memory references committed
system.cpu1.commit.loads                            0                       # Number of loads committed
system.cpu1.commit.membars                          0                       # Number of memory barriers committed
system.cpu1.commit.branches                         0                       # Number of branches committed
system.cpu1.commit.fp_insts                         0                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                        0                       # Number of committed integer instructions.
system.cpu1.commit.function_calls                   0                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass            0                       # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu               0                       # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult              0                       # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv               0                       # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             0                       # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0                       # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0                       # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0                       # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMultAcc            0                       # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0                       # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMisc            0                       # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0                       # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0                       # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0                       # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0                       # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0                       # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0                       # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0                       # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0                       # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0                       # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0                       # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0                       # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0                       # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            0                       # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0                       # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp            0                       # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt            0                       # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0                       # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc            0                       # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0                       # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0                       # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0                       # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead              0                       # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite             0                       # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMemRead            0                       # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMemWrite            0                       # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0                       # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0                       # Class of committed instruction
system.cpu1.commit.op_class_0::total                0                       # Class of committed instruction
system.cpu1.commit.bw_lim_events                    0                       # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads                           0                       # The number of ROB reads
system.cpu1.rob.rob_writes                          0                       # The number of ROB writes
system.cpu1.committedInsts                          0                       # Number of Instructions Simulated
system.cpu1.committedOps                            0                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                                   nan                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                             nan                       # CPI: Total CPI of All Threads
system.cpu1.ipc                                   nan                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                             nan                       # IPC: Total IPC of All Threads
system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED   2076353830                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements                0                       # number of replacements
system.cpu1.dcache.tags.tagsinuse                   0                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs                  0                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs                0                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs                  nan                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.tag_accesses                0                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses               0                       # Number of data accesses
system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED   2076353830                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dtb_walker_cache.tags.pwrStateResidencyTicks::UNDEFINED   2076353830                       # Cumulative time (in ticks) in various power states
system.cpu1.dtb_walker_cache.tags.replacements            0                       # number of replacements
system.cpu1.dtb_walker_cache.tags.tagsinuse            0                       # Cycle average of tags in use
system.cpu1.dtb_walker_cache.tags.total_refs            0                       # Total number of references to valid blocks.
system.cpu1.dtb_walker_cache.tags.sampled_refs            0                       # Sample count of references to valid blocks.
system.cpu1.dtb_walker_cache.tags.avg_refs          nan                       # Average number of references to valid blocks.
system.cpu1.dtb_walker_cache.tags.warmup_cycle            0                       # Cycle when the warmup percentage was hit.
system.cpu1.dtb_walker_cache.tags.tag_accesses            0                       # Number of tag accesses
system.cpu1.dtb_walker_cache.tags.data_accesses            0                       # Number of data accesses
system.cpu1.dtb_walker_cache.pwrStateResidencyTicks::UNDEFINED   2076353830                       # Cumulative time (in ticks) in various power states
system.cpu1.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu1.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED   2076353830                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements                0                       # number of replacements
system.cpu1.icache.tags.tagsinuse                   0                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs                  0                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs                0                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs                  nan                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.tag_accesses                0                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses               0                       # Number of data accesses
system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED   2076353830                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.itb_walker_cache.tags.pwrStateResidencyTicks::UNDEFINED   2076353830                       # Cumulative time (in ticks) in various power states
system.cpu1.itb_walker_cache.tags.replacements            0                       # number of replacements
system.cpu1.itb_walker_cache.tags.tagsinuse            0                       # Cycle average of tags in use
system.cpu1.itb_walker_cache.tags.total_refs            0                       # Total number of references to valid blocks.
system.cpu1.itb_walker_cache.tags.sampled_refs            0                       # Sample count of references to valid blocks.
system.cpu1.itb_walker_cache.tags.avg_refs          nan                       # Average number of references to valid blocks.
system.cpu1.itb_walker_cache.tags.warmup_cycle            0                       # Cycle when the warmup percentage was hit.
system.cpu1.itb_walker_cache.tags.tag_accesses            0                       # Number of tag accesses
system.cpu1.itb_walker_cache.tags.data_accesses            0                       # Number of data accesses
system.cpu1.itb_walker_cache.pwrStateResidencyTicks::UNDEFINED   2076353830                       # Cumulative time (in ticks) in various power states
system.cpu1.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu1.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED   2076353830                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.tags.replacements               0                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse                  0                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs                 0                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs               0                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs                 nan                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.tag_accesses               0                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses              0                       # Number of data accesses
system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED   2076353830                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.toL2Bus.snoop_filter.tot_requests            0                       # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED   2076353830                       # Cumulative time (in ticks) in various power states
system.cpu1.toL2Bus.snoops                          0                       # Total snoops (count)
system.cpu1.toL2Bus.snoopTraffic                    0                       # Total snoop traffic (bytes)
system.cpu1.toL2Bus.snoop_fanout::samples            0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean            nan                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev           nan                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0                 0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1                 0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2                 0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::3                 0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::4                 0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total             0                       # Request fanout histogram
system.l3.tags.pwrStateResidencyTicks::UNDEFINED   2076353830                       # Cumulative time (in ticks) in various power states
system.l3.tags.replacements                         0                       # number of replacements
system.l3.tags.tagsinuse                  3292.905604                       # Cycle average of tags in use
system.l3.tags.total_refs                        6944                       # Total number of references to valid blocks.
system.l3.tags.sampled_refs                      5821                       # Sample count of references to valid blocks.
system.l3.tags.avg_refs                      1.192922                       # Average number of references to valid blocks.
system.l3.tags.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
system.l3.tags.occ_blocks::cpu0.inst       617.027895                       # Average occupied blocks per requestor
system.l3.tags.occ_blocks::cpu0.data      2675.877710                       # Average occupied blocks per requestor
system.l3.tags.occ_percent::cpu0.inst        0.009415                       # Average percentage of cache occupancy
system.l3.tags.occ_percent::cpu0.data        0.040831                       # Average percentage of cache occupancy
system.l3.tags.occ_percent::total            0.050246                       # Average percentage of cache occupancy
system.l3.tags.occ_task_id_blocks::1024          5821                       # Occupied blocks per task id
system.l3.tags.age_task_id_blocks_1024::0           83                       # Occupied blocks per task id
system.l3.tags.age_task_id_blocks_1024::1           33                       # Occupied blocks per task id
system.l3.tags.age_task_id_blocks_1024::2         2245                       # Occupied blocks per task id
system.l3.tags.age_task_id_blocks_1024::3         3460                       # Occupied blocks per task id
system.l3.tags.occ_task_id_percent::1024     0.088821                       # Percentage of cache occupancy per task id
system.l3.tags.tag_accesses                    210061                       # Number of tag accesses
system.l3.tags.data_accesses                   210061                       # Number of data accesses
system.l3.pwrStateResidencyTicks::UNDEFINED   2076353830                       # Cumulative time (in ticks) in various power states
system.l3.WritebackDirty_hits::writebacks         3717                       # number of WritebackDirty hits
system.l3.WritebackDirty_hits::total             3717                       # number of WritebackDirty hits
system.l3.WritebackClean_hits::writebacks          415                       # number of WritebackClean hits
system.l3.WritebackClean_hits::total              415                       # number of WritebackClean hits
system.l3.UpgradeReq_hits::cpu0.data                1                       # number of UpgradeReq hits
system.l3.UpgradeReq_hits::total                    1                       # number of UpgradeReq hits
system.l3.ReadExReq_hits::cpu0.data                33                       # number of ReadExReq hits
system.l3.ReadExReq_hits::total                    33                       # number of ReadExReq hits
system.l3.ReadSharedReq_hits::cpu0.inst             9                       # number of ReadSharedReq hits
system.l3.ReadSharedReq_hits::cpu0.data          2769                       # number of ReadSharedReq hits
system.l3.ReadSharedReq_hits::total              2778                       # number of ReadSharedReq hits
system.l3.demand_hits::cpu0.inst                    9                       # number of demand (read+write) hits
system.l3.demand_hits::cpu0.data                 2802                       # number of demand (read+write) hits
system.l3.demand_hits::total                     2811                       # number of demand (read+write) hits
system.l3.overall_hits::cpu0.inst                   9                       # number of overall hits
system.l3.overall_hits::cpu0.data                2802                       # number of overall hits
system.l3.overall_hits::total                    2811                       # number of overall hits
system.l3.ReadExReq_misses::cpu0.data            2770                       # number of ReadExReq misses
system.l3.ReadExReq_misses::total                2770                       # number of ReadExReq misses
system.l3.ReadSharedReq_misses::cpu0.inst          788                       # number of ReadSharedReq misses
system.l3.ReadSharedReq_misses::cpu0.data         2263                       # number of ReadSharedReq misses
system.l3.ReadSharedReq_misses::total            3051                       # number of ReadSharedReq misses
system.l3.demand_misses::cpu0.inst                788                       # number of demand (read+write) misses
system.l3.demand_misses::cpu0.data               5033                       # number of demand (read+write) misses
system.l3.demand_misses::total                   5821                       # number of demand (read+write) misses
system.l3.overall_misses::cpu0.inst               788                       # number of overall misses
system.l3.overall_misses::cpu0.data              5033                       # number of overall misses
system.l3.overall_misses::total                  5821                       # number of overall misses
system.l3.ReadExReq_miss_latency::cpu0.data    330771508                       # number of ReadExReq miss cycles
system.l3.ReadExReq_miss_latency::total     330771508                       # number of ReadExReq miss cycles
system.l3.ReadSharedReq_miss_latency::cpu0.inst    100976621                       # number of ReadSharedReq miss cycles
system.l3.ReadSharedReq_miss_latency::cpu0.data    322499375                       # number of ReadSharedReq miss cycles
system.l3.ReadSharedReq_miss_latency::total    423475996                       # number of ReadSharedReq miss cycles
system.l3.demand_miss_latency::cpu0.inst    100976621                       # number of demand (read+write) miss cycles
system.l3.demand_miss_latency::cpu0.data    653270883                       # number of demand (read+write) miss cycles
system.l3.demand_miss_latency::total        754247504                       # number of demand (read+write) miss cycles
system.l3.overall_miss_latency::cpu0.inst    100976621                       # number of overall miss cycles
system.l3.overall_miss_latency::cpu0.data    653270883                       # number of overall miss cycles
system.l3.overall_miss_latency::total       754247504                       # number of overall miss cycles
system.l3.WritebackDirty_accesses::writebacks         3717                       # number of WritebackDirty accesses(hits+misses)
system.l3.WritebackDirty_accesses::total         3717                       # number of WritebackDirty accesses(hits+misses)
system.l3.WritebackClean_accesses::writebacks          415                       # number of WritebackClean accesses(hits+misses)
system.l3.WritebackClean_accesses::total          415                       # number of WritebackClean accesses(hits+misses)
system.l3.UpgradeReq_accesses::cpu0.data            1                       # number of UpgradeReq accesses(hits+misses)
system.l3.UpgradeReq_accesses::total                1                       # number of UpgradeReq accesses(hits+misses)
system.l3.ReadExReq_accesses::cpu0.data          2803                       # number of ReadExReq accesses(hits+misses)
system.l3.ReadExReq_accesses::total              2803                       # number of ReadExReq accesses(hits+misses)
system.l3.ReadSharedReq_accesses::cpu0.inst          797                       # number of ReadSharedReq accesses(hits+misses)
system.l3.ReadSharedReq_accesses::cpu0.data         5032                       # number of ReadSharedReq accesses(hits+misses)
system.l3.ReadSharedReq_accesses::total          5829                       # number of ReadSharedReq accesses(hits+misses)
system.l3.demand_accesses::cpu0.inst              797                       # number of demand (read+write) accesses
system.l3.demand_accesses::cpu0.data             7835                       # number of demand (read+write) accesses
system.l3.demand_accesses::total                 8632                       # number of demand (read+write) accesses
system.l3.overall_accesses::cpu0.inst             797                       # number of overall (read+write) accesses
system.l3.overall_accesses::cpu0.data            7835                       # number of overall (read+write) accesses
system.l3.overall_accesses::total                8632                       # number of overall (read+write) accesses
system.l3.ReadExReq_miss_rate::cpu0.data     0.988227                       # miss rate for ReadExReq accesses
system.l3.ReadExReq_miss_rate::total         0.988227                       # miss rate for ReadExReq accesses
system.l3.ReadSharedReq_miss_rate::cpu0.inst     0.988708                       # miss rate for ReadSharedReq accesses
system.l3.ReadSharedReq_miss_rate::cpu0.data     0.449722                       # miss rate for ReadSharedReq accesses
system.l3.ReadSharedReq_miss_rate::total     0.523417                       # miss rate for ReadSharedReq accesses
system.l3.demand_miss_rate::cpu0.inst        0.988708                       # miss rate for demand accesses
system.l3.demand_miss_rate::cpu0.data        0.642374                       # miss rate for demand accesses
system.l3.demand_miss_rate::total            0.674351                       # miss rate for demand accesses
system.l3.overall_miss_rate::cpu0.inst       0.988708                       # miss rate for overall accesses
system.l3.overall_miss_rate::cpu0.data       0.642374                       # miss rate for overall accesses
system.l3.overall_miss_rate::total           0.674351                       # miss rate for overall accesses
system.l3.ReadExReq_avg_miss_latency::cpu0.data 119412.096751                       # average ReadExReq miss latency
system.l3.ReadExReq_avg_miss_latency::total 119412.096751                       # average ReadExReq miss latency
system.l3.ReadSharedReq_avg_miss_latency::cpu0.inst 128142.920051                       # average ReadSharedReq miss latency
system.l3.ReadSharedReq_avg_miss_latency::cpu0.data 142509.666372                       # average ReadSharedReq miss latency
system.l3.ReadSharedReq_avg_miss_latency::total 138799.080957                       # average ReadSharedReq miss latency
system.l3.demand_avg_miss_latency::cpu0.inst 128142.920051                       # average overall miss latency
system.l3.demand_avg_miss_latency::cpu0.data 129797.513014                       # average overall miss latency
system.l3.demand_avg_miss_latency::total 129573.527573                       # average overall miss latency
system.l3.overall_avg_miss_latency::cpu0.inst 128142.920051                       # average overall miss latency
system.l3.overall_avg_miss_latency::cpu0.data 129797.513014                       # average overall miss latency
system.l3.overall_avg_miss_latency::total 129573.527573                       # average overall miss latency
system.l3.blocked_cycles::no_mshrs                  0                       # number of cycles access was blocked
system.l3.blocked_cycles::no_targets                0                       # number of cycles access was blocked
system.l3.blocked::no_mshrs                         0                       # number of cycles access was blocked
system.l3.blocked::no_targets                       0                       # number of cycles access was blocked
system.l3.avg_blocked_cycles::no_mshrs            nan                       # average number of cycles each access was blocked
system.l3.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l3.ReadExReq_mshr_misses::cpu0.data         2770                       # number of ReadExReq MSHR misses
system.l3.ReadExReq_mshr_misses::total           2770                       # number of ReadExReq MSHR misses
system.l3.ReadSharedReq_mshr_misses::cpu0.inst          788                       # number of ReadSharedReq MSHR misses
system.l3.ReadSharedReq_mshr_misses::cpu0.data         2263                       # number of ReadSharedReq MSHR misses
system.l3.ReadSharedReq_mshr_misses::total         3051                       # number of ReadSharedReq MSHR misses
system.l3.demand_mshr_misses::cpu0.inst           788                       # number of demand (read+write) MSHR misses
system.l3.demand_mshr_misses::cpu0.data          5033                       # number of demand (read+write) MSHR misses
system.l3.demand_mshr_misses::total              5821                       # number of demand (read+write) MSHR misses
system.l3.overall_mshr_misses::cpu0.inst          788                       # number of overall MSHR misses
system.l3.overall_mshr_misses::cpu0.data         5033                       # number of overall MSHR misses
system.l3.overall_mshr_misses::total             5821                       # number of overall MSHR misses
system.l3.ReadExReq_mshr_miss_latency::cpu0.data    253078797                       # number of ReadExReq MSHR miss cycles
system.l3.ReadExReq_mshr_miss_latency::total    253078797                       # number of ReadExReq MSHR miss cycles
system.l3.ReadSharedReq_mshr_miss_latency::cpu0.inst     78860793                       # number of ReadSharedReq MSHR miss cycles
system.l3.ReadSharedReq_mshr_miss_latency::cpu0.data    258995193                       # number of ReadSharedReq MSHR miss cycles
system.l3.ReadSharedReq_mshr_miss_latency::total    337855986                       # number of ReadSharedReq MSHR miss cycles
system.l3.demand_mshr_miss_latency::cpu0.inst     78860793                       # number of demand (read+write) MSHR miss cycles
system.l3.demand_mshr_miss_latency::cpu0.data    512073990                       # number of demand (read+write) MSHR miss cycles
system.l3.demand_mshr_miss_latency::total    590934783                       # number of demand (read+write) MSHR miss cycles
system.l3.overall_mshr_miss_latency::cpu0.inst     78860793                       # number of overall MSHR miss cycles
system.l3.overall_mshr_miss_latency::cpu0.data    512073990                       # number of overall MSHR miss cycles
system.l3.overall_mshr_miss_latency::total    590934783                       # number of overall MSHR miss cycles
system.l3.ReadExReq_mshr_miss_rate::cpu0.data     0.988227                       # mshr miss rate for ReadExReq accesses
system.l3.ReadExReq_mshr_miss_rate::total     0.988227                       # mshr miss rate for ReadExReq accesses
system.l3.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.988708                       # mshr miss rate for ReadSharedReq accesses
system.l3.ReadSharedReq_mshr_miss_rate::cpu0.data     0.449722                       # mshr miss rate for ReadSharedReq accesses
system.l3.ReadSharedReq_mshr_miss_rate::total     0.523417                       # mshr miss rate for ReadSharedReq accesses
system.l3.demand_mshr_miss_rate::cpu0.inst     0.988708                       # mshr miss rate for demand accesses
system.l3.demand_mshr_miss_rate::cpu0.data     0.642374                       # mshr miss rate for demand accesses
system.l3.demand_mshr_miss_rate::total       0.674351                       # mshr miss rate for demand accesses
system.l3.overall_mshr_miss_rate::cpu0.inst     0.988708                       # mshr miss rate for overall accesses
system.l3.overall_mshr_miss_rate::cpu0.data     0.642374                       # mshr miss rate for overall accesses
system.l3.overall_mshr_miss_rate::total      0.674351                       # mshr miss rate for overall accesses
system.l3.ReadExReq_avg_mshr_miss_latency::cpu0.data 91364.186643                       # average ReadExReq mshr miss latency
system.l3.ReadExReq_avg_mshr_miss_latency::total 91364.186643                       # average ReadExReq mshr miss latency
system.l3.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 100077.148477                       # average ReadSharedReq mshr miss latency
system.l3.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 114447.721167                       # average ReadSharedReq mshr miss latency
system.l3.ReadSharedReq_avg_mshr_miss_latency::total 110736.147493                       # average ReadSharedReq mshr miss latency
system.l3.demand_avg_mshr_miss_latency::cpu0.inst 100077.148477                       # average overall mshr miss latency
system.l3.demand_avg_mshr_miss_latency::cpu0.data 101743.292271                       # average overall mshr miss latency
system.l3.demand_avg_mshr_miss_latency::total 101517.743171                       # average overall mshr miss latency
system.l3.overall_avg_mshr_miss_latency::cpu0.inst 100077.148477                       # average overall mshr miss latency
system.l3.overall_avg_mshr_miss_latency::cpu0.data 101743.292271                       # average overall mshr miss latency
system.l3.overall_avg_mshr_miss_latency::total 101517.743171                       # average overall mshr miss latency
system.membus.snoop_filter.tot_requests          5821                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED   2076353830                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp               3051                       # Transaction distribution
system.membus.trans_dist::ReadExReq              2770                       # Transaction distribution
system.membus.trans_dist::ReadExResp             2770                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq          3051                       # Transaction distribution
system.membus.pkt_count_system.l3.mem_side::system.mem_ctrls.port        11642                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l3.mem_side::total        11642                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                  11642                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l3.mem_side::system.mem_ctrls.port       372544                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l3.mem_side::total       372544                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                  372544                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples              5821                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                    5821    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total                5821                       # Request fanout histogram
system.membus.reqLayer4.occupancy             8714419                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.4                       # Layer utilization (%)
system.membus.respLayer1.occupancy           31153567                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              1.5                       # Layer utilization (%)
system.tol3bus.snoop_filter.tot_requests        12765                       # Total number of requests made to the snoop filter.
system.tol3bus.snoop_filter.hit_single_requests         4135                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.tol3bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.tol3bus.snoop_filter.tot_snoops              0                       # Total number of snoops made to the snoop filter.
system.tol3bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.tol3bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.tol3bus.pwrStateResidencyTicks::UNDEFINED   2076353830                       # Cumulative time (in ticks) in various power states
system.tol3bus.trans_dist::ReadResp              5829                       # Transaction distribution
system.tol3bus.trans_dist::WritebackDirty         3717                       # Transaction distribution
system.tol3bus.trans_dist::WritebackClean          415                       # Transaction distribution
system.tol3bus.trans_dist::UpgradeReq               1                       # Transaction distribution
system.tol3bus.trans_dist::UpgradeResp              1                       # Transaction distribution
system.tol3bus.trans_dist::ReadExReq             2803                       # Transaction distribution
system.tol3bus.trans_dist::ReadExResp            2803                       # Transaction distribution
system.tol3bus.trans_dist::ReadSharedReq         5829                       # Transaction distribution
system.tol3bus.pkt_count_system.cpu0.l2cache.mem_side::system.l3.cpu_side        21398                       # Packet count per connected master and slave (bytes)
system.tol3bus.pkt_count::total                 21398                       # Packet count per connected master and slave (bytes)
system.tol3bus.pkt_size_system.cpu0.l2cache.mem_side::system.l3.cpu_side       816896                       # Cumulative packet size per connected master and slave (bytes)
system.tol3bus.pkt_size::total                 816896                       # Cumulative packet size per connected master and slave (bytes)
system.tol3bus.snoops                               0                       # Total snoops (count)
system.tol3bus.snoopTraffic                         0                       # Total snoop traffic (bytes)
system.tol3bus.snoop_fanout::samples             8633                       # Request fanout histogram
system.tol3bus.snoop_fanout::mean                   0                       # Request fanout histogram
system.tol3bus.snoop_fanout::stdev                  0                       # Request fanout histogram
system.tol3bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.tol3bus.snoop_fanout::0                   8633    100.00%    100.00% # Request fanout histogram
system.tol3bus.snoop_fanout::1                      0      0.00%    100.00% # Request fanout histogram
system.tol3bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
system.tol3bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.tol3bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.tol3bus.snoop_fanout::max_value              0                       # Request fanout histogram
system.tol3bus.snoop_fanout::total               8633                       # Request fanout histogram
system.tol3bus.reqLayer0.occupancy           16171301                       # Layer occupancy (ticks)
system.tol3bus.reqLayer0.utilization              0.8                       # Layer utilization (%)
system.tol3bus.respLayer0.occupancy          19914793                       # Layer occupancy (ticks)
system.tol3bus.respLayer0.utilization             1.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------