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camvolution.ucf
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camvolution.ucf
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###########################################
# Setting VCCAUX for different SP601 board
###########################################
CONFIG VCCAUX = 3.3;
########################################
# Reset button and LEDs
########################################
NET SW6 LOC = P15 | IOSTANDARD = LVCMOS33;
NET SW7 LOC = P16 | IOSTANDARD = LVCMOS33;
NET LED LOC = N11 | IOSTANDARD = LVCMOS33;
##############################################################################
# SYSCLK Input
##############################################################################
Net clk120 TNM_NET = clk120;
TIMESPEC TS_clk120 = PERIOD clk120 120000.0 kHz;
NET "clk120" LOC = "C9" | IOSTANDARD = LVCMOS33 | PERIOD = 120 MHz;
#INST "pixelclock_BUFIO2" LOC = BUFIO2_X2Y29;
#INST "pixel_clk_BUFG" LOC = BUFGMUX_X2Y2;
# Constraint for RX0
#
NET "hdmi/dvi_rx0/rxclk" TNM_NET = DVI_CLOCK0;
TIMESPEC TS_DVI_CLOCK0 = PERIOD "DVI_CLOCK0" 120 MHz HIGH 50%;
#INST "dvi_rx0/ibuf_rxclk" LOC =
#INST "dvi_rx0/ioclk_buf" LOC = BUFPLL_X1Y5;
#INST "dvi_rx0/bufio_tmdsclk" LOC = BUFIO2_X2Y29;
#
#INST "dvi_rx0/tmdsclk_bufg" LOC = PAD9;
#
# Multi-cycle paths for TX0
#
TIMEGRP "bramgrp_0" = RAMS(hdmi/dvi_tx0/pixel2x/dataint<*>);
TIMEGRP "fddbgrp_0" = FFS(hdmi/dvi_tx0/pixel2x/db<*>);
TIMEGRP "bramra_0" = FFS(hdmi/dvi_tx0/pixel2x/ra<*>);
#
TIMESPEC "TS_ramdo_0" = FROM "bramgrp_0" TO "fddbgrp_0" TS_DVI_CLOCK0;
TIMESPEC "TS_ramra_0" = FROM "bramra_0" TO "fddbgrp_0" TS_DVI_CLOCK0;
##############################################################################
# DCM/PLL/BUFPLL positions // probably not to be uncommented
##############################################################################
#INST "PCLK_GEN_INST" LOC = "DCM_X0Y3";
#INST "PLL_OSERDES" LOC = "PLL_ADV_X0Y1";
#INST "ioclk_buf" LOC = "BUFPLL_X1Y0";
###########################################
# Timing Constraints // FROM HDMI
###########################################
#NET "sysclk_50" TNM_NET = "TNM_sysclk_50";
#TIMESPEC "TS_sysclk_50" = PERIOD "TNM_sysclk_50" 50 MHz HIGH 50 % PRIORITY 0 ;
#NET "clk50m_bufg" TNM_NET = "TNM_CLK50M";
#TIMESPEC "TS_CLK50M" = PERIOD "TNM_CLK50M" 50 MHz HIGH 50 % PRIORITY 0 ;
#NET "pclk" TNM_NET = "TNM_PCLK";
#TIMESPEC "TS_PCLK" = PERIOD "TNM_PCLK" 108 MHz HIGH 50 % PRIORITY 0 ;
#NET "pclkx2" TNM_NET = "TNM_PCLKX2";
#TIMESPEC "TS_PCLKX2" = PERIOD "TNM_PCLKX2" TS_PCLK * 2;
#NET "pclkx10" TNM_NET = "TNM_PCLKX10";
#TIMESPEC "TS_PCLKX10" = PERIOD "TNM_PCLKX10" TS_PCLK * 10;
#
# Multi-cycle paths
#
#TIMEGRP "bramgrp" = RAMS(enc0/pixel2x/dataint<*>);
#TIMEGRP "fddbgrp" = FFS(enc0/pixel2x/db<*>);
#TIMEGRP "bramra" = FFS(enc0/pixel2x/ra<*>);
#TIMESPEC "TS_ramdo" = FROM "bramgrp" TO "fddbgrp" TS_PCLK;
#TIMESPEC "TS_ramra" = FROM "bramra" TO "fddbgrp" TS_PCLK;
############################
# TMDS pairs on the top
############################
# HDMI input
NET "RX0_TMDS(3)" LOC = "B9" |IOSTANDARD = TMDS_33 ; # CLK
NET "RX0_TMDSB(3)" LOC = "A9" |IOSTANDARD = TMDS_33 ;
NET "RX0_TMDS(2)" LOC = "C10" |IOSTANDARD = TMDS_33 ; # Red
NET "RX0_TMDSB(2)" LOC = "A10" |IOSTANDARD = TMDS_33 ;
NET "RX0_TMDS(1)" LOC = "D11" |IOSTANDARD = TMDS_33 ; # Green
NET "RX0_TMDSB(1)" LOC = "C11" |IOSTANDARD = TMDS_33 ;
NET "RX0_TMDS(0)" LOC = "G9" |IOSTANDARD = TMDS_33 ; # Blue
NET "RX0_TMDSB(0)" LOC = "F9" |IOSTANDARD = TMDS_33 ;
# HDMI output
NET "TX0_TMDS(3)" LOC = "B4" |IOSTANDARD = TMDS_33 ; # Clock
NET "TX0_TMDSB(3)" LOC = "A4" |IOSTANDARD = TMDS_33 ;
NET "TX0_TMDS(2)" LOC = "B3" |IOSTANDARD = TMDS_33 ; # Red
NET "TX0_TMDSB(2)" LOC = "A3" |IOSTANDARD = TMDS_33 ;
NET "TX0_TMDS(1)" LOC = "D6" |IOSTANDARD = TMDS_33 ; # Green
NET "TX0_TMDSB(1)" LOC = "C6" |IOSTANDARD = TMDS_33 ;
NET "TX0_TMDS(0)" LOC = "B2" |IOSTANDARD = TMDS_33 ; # Blue
NET "TX0_TMDSB(0)" LOC = "A2" |IOSTANDARD = TMDS_33 ;
# Reset button for HDMI
NET "rstbtn_n" LOC = "T15" | IOSTANDARD = LVCMOS33;
########################################
# SRAM 1
########################################
NET SRAM1_CE LOC = V8 | IOSTANDARD = LVCMOS33;
NET SRAM1_LB LOC = M8 | IOSTANDARD = LVCMOS33;
NET SRAM1_UB LOC = N8 | IOSTANDARD = LVCMOS33;
NET SRAM1_OE LOC = U8 | IOSTANDARD = LVCMOS33;
NET SRAM1_WE LOC = U7 | IOSTANDARD = LVCMOS33;
NET SRAM1_ADDRESS[0] LOC = H15 | IOSTANDARD = LVCMOS33;
NET SRAM1_ADDRESS[1] LOC = H14 | IOSTANDARD = LVCMOS33;
NET SRAM1_ADDRESS[2] LOC = H13 | IOSTANDARD = LVCMOS33;
NET SRAM1_ADDRESS[3] LOC = F18 | IOSTANDARD = LVCMOS33;
NET SRAM1_ADDRESS[4] LOC = F17 | IOSTANDARD = LVCMOS33;
NET SRAM1_ADDRESS[5] LOC = K13 | IOSTANDARD = LVCMOS33;
NET SRAM1_ADDRESS[6] LOC = K12 | IOSTANDARD = LVCMOS33;
NET SRAM1_ADDRESS[7] LOC = E18 | IOSTANDARD = LVCMOS33;
NET SRAM1_ADDRESS[8] LOC = E16 | IOSTANDARD = LVCMOS33;
NET SRAM1_ADDRESS[9] LOC = G13 | IOSTANDARD = LVCMOS33;
NET SRAM1_ADDRESS[10] LOC = H12 | IOSTANDARD = LVCMOS33;
NET SRAM1_ADDRESS[11] LOC = D18 | IOSTANDARD = LVCMOS33;
NET SRAM1_ADDRESS[12] LOC = D17 | IOSTANDARD = LVCMOS33;
NET SRAM1_ADDRESS[13] LOC = G14 | IOSTANDARD = LVCMOS33;
NET SRAM1_ADDRESS[14] LOC = F14 | IOSTANDARD = LVCMOS33;
NET SRAM1_ADDRESS[15] LOC = C18 | IOSTANDARD = LVCMOS33;
NET SRAM1_ADDRESS[16] LOC = C17 | IOSTANDARD = LVCMOS33;
NET SRAM1_ADDRESS[17] LOC = F16 | IOSTANDARD = LVCMOS33;
NET SRAM1_ADDRESS[18] LOC = F15 | IOSTANDARD = LVCMOS33;
NET SRAM1_DATA[0] LOC = K17 | IOSTANDARD = LVCMOS33;
NET SRAM1_DATA[1] LOC = J18 | IOSTANDARD = LVCMOS33;
NET SRAM1_DATA[2] LOC = J16 | IOSTANDARD = LVCMOS33;
NET SRAM1_DATA[3] LOC = H18 | IOSTANDARD = LVCMOS33;
NET SRAM1_DATA[4] LOC = H17 | IOSTANDARD = LVCMOS33;
NET SRAM1_DATA[5] LOC = L16 | IOSTANDARD = LVCMOS33;
NET SRAM1_DATA[6] LOC = L15 | IOSTANDARD = LVCMOS33;
NET SRAM1_DATA[7] LOC = K16 | IOSTANDARD = LVCMOS33;
NET SRAM1_DATA[8] LOC = K15 | IOSTANDARD = LVCMOS33;
NET SRAM1_DATA[9] LOC = L13 | IOSTANDARD = LVCMOS33;
NET SRAM1_DATA[10] LOC = L12 | IOSTANDARD = LVCMOS33;
NET SRAM1_DATA[11] LOC = K14 | IOSTANDARD = LVCMOS33;
NET SRAM1_DATA[12] LOC = J13 | IOSTANDARD = LVCMOS33;
NET SRAM1_DATA[13] LOC = G18 | IOSTANDARD = LVCMOS33;
NET SRAM1_DATA[14] LOC = G16 | IOSTANDARD = LVCMOS33;
NET SRAM1_DATA[15] LOC = H16 | IOSTANDARD = LVCMOS33;
########################################
# SRAM 2
########################################
NET SRAM2_CE LOC = T6 | IOSTANDARD = LVCMOS33;
NET SRAM2_LB LOC = V7 | IOSTANDARD = LVCMOS33;
NET SRAM2_UB LOC = N7 | IOSTANDARD = LVCMOS33;
NET SRAM2_OE LOC = P8 | IOSTANDARD = LVCMOS33;
NET SRAM2_WE LOC = V6 | IOSTANDARD = LVCMOS33;
NET SRAM2_ADDRESS[0] LOC = M13 | IOSTANDARD = LVCMOS33;
NET SRAM2_ADDRESS[1] LOC = L14 | IOSTANDARD = LVCMOS33;
NET SRAM2_ADDRESS[2] LOC = N14 | IOSTANDARD = LVCMOS33;
NET SRAM2_ADDRESS[3] LOC = M14 | IOSTANDARD = LVCMOS33;
NET SRAM2_ADDRESS[4] LOC = U18 | IOSTANDARD = LVCMOS33;
NET SRAM2_ADDRESS[5] LOC = U17 | IOSTANDARD = LVCMOS33;
NET SRAM2_ADDRESS[6] LOC = T18 | IOSTANDARD = LVCMOS33;
NET SRAM2_ADDRESS[7] LOC = T17 | IOSTANDARD = LVCMOS33;
NET SRAM2_ADDRESS[8] LOC = N16 | IOSTANDARD = LVCMOS33;
NET SRAM2_ADDRESS[9] LOC = N15 | IOSTANDARD = LVCMOS33;
NET SRAM2_ADDRESS[10] LOC = P18 | IOSTANDARD = LVCMOS33;
NET SRAM2_ADDRESS[11] LOC = P17 | IOSTANDARD = LVCMOS33;
NET SRAM2_ADDRESS[12] LOC = N18 | IOSTANDARD = LVCMOS33;
NET SRAM2_ADDRESS[13] LOC = N17 | IOSTANDARD = LVCMOS33;
NET SRAM2_ADDRESS[14] LOC = M18 | IOSTANDARD = LVCMOS33;
NET SRAM2_ADDRESS[15] LOC = M16 | IOSTANDARD = LVCMOS33;
NET SRAM2_ADDRESS[16] LOC = L18 | IOSTANDARD = LVCMOS33;
NET SRAM2_ADDRESS[17] LOC = L17 | IOSTANDARD = LVCMOS33;
NET SRAM2_ADDRESS[18] LOC = K18 | IOSTANDARD = LVCMOS33;
NET SRAM2_DATA[0] LOC = V3 | IOSTANDARD = LVCMOS33;
NET SRAM2_DATA[1] LOC = U3 | IOSTANDARD = LVCMOS33;
NET SRAM2_DATA[2] LOC = P6 | IOSTANDARD = LVCMOS33;
NET SRAM2_DATA[3] LOC = N5 | IOSTANDARD = LVCMOS33;
NET SRAM2_DATA[4] LOC = V4 | IOSTANDARD = LVCMOS33;
NET SRAM2_DATA[5] LOC = T4 | IOSTANDARD = LVCMOS33;
NET SRAM2_DATA[6] LOC = T3 | IOSTANDARD = LVCMOS33;
NET SRAM2_DATA[7] LOC = R3 | IOSTANDARD = LVCMOS33;
NET SRAM2_DATA[8] LOC = V5 | IOSTANDARD = LVCMOS33;
NET SRAM2_DATA[9] LOC = U5 | IOSTANDARD = LVCMOS33;
NET SRAM2_DATA[10] LOC = T5 | IOSTANDARD = LVCMOS33;
NET SRAM2_DATA[11] LOC = R5 | IOSTANDARD = LVCMOS33;
NET SRAM2_DATA[12] LOC = P7 | IOSTANDARD = LVCMOS33;
NET SRAM2_DATA[13] LOC = N6 | IOSTANDARD = LVCMOS33;
NET SRAM2_DATA[14] LOC = T7 | IOSTANDARD = LVCMOS33;
NET SRAM2_DATA[15] LOC = R7 | IOSTANDARD = LVCMOS33;
#########################################
## EBI
#########################################
NET EBI_WEN LOC = U10 | IOSTANDARD = LVCMOS33;
NET EBI_REN LOC = F2 | IOSTANDARD = LVCMOS33;
NET EBI_CS0 LOC = F1 | IOSTANDARD = LVCMOS33;
NET EBI_CS1 LOC = H6 | IOSTANDARD = LVCMOS33;
TIMESPEC TS_EBI_WEN = PERIOD EBI_WEN 24 MHz;
NET EBI_ADDRESS[0] LOC = M1 | IOSTANDARD = LVCMOS33;
NET EBI_ADDRESS[1] LOC = M3 | IOSTANDARD = LVCMOS33;
NET EBI_ADDRESS[2] LOC = N1 | IOSTANDARD = LVCMOS33;
NET EBI_ADDRESS[3] LOC = N2 | IOSTANDARD = LVCMOS33;
NET EBI_ADDRESS[4] LOC = P1 | IOSTANDARD = LVCMOS33;
NET EBI_ADDRESS[5] LOC = P2 | IOSTANDARD = LVCMOS33;
NET EBI_ADDRESS[6] LOC = T1 | IOSTANDARD = LVCMOS33;
NET EBI_ADDRESS[7] LOC = T2 | IOSTANDARD = LVCMOS33;
NET EBI_ADDRESS[8] LOC = U1 | IOSTANDARD = LVCMOS33;
NET EBI_ADDRESS[9] LOC = U2 | IOSTANDARD = LVCMOS33;
NET EBI_ADDRESS[10] LOC = M5 | IOSTANDARD = LVCMOS33;
NET EBI_ADDRESS[11] LOC = L6 | IOSTANDARD = LVCMOS33;
NET EBI_ADDRESS[12] LOC = P3 | IOSTANDARD = LVCMOS33;
NET EBI_ADDRESS[13] LOC = P4 | IOSTANDARD = LVCMOS33;
NET EBI_ADDRESS[14] LOC = N3 | IOSTANDARD = LVCMOS33;
NET EBI_ADDRESS[15] LOC = N4 | IOSTANDARD = LVCMOS33;
NET EBI_ADDRESS[16] LOC = L7 | IOSTANDARD = LVCMOS33;
NET EBI_ADDRESS[17] LOC = K6 | IOSTANDARD = LVCMOS33;
NET EBI_ADDRESS[18] LOC = G3 | IOSTANDARD = LVCMOS33;
NET EBI_ADDRESS[19] LOC = G1 | IOSTANDARD = LVCMOS33;
NET EBI_DATA[0] LOC = H3 | IOSTANDARD = LVCMOS33;
NET EBI_DATA[1] LOC = H4 | IOSTANDARD = LVCMOS33;
NET EBI_DATA[2] LOC = K5 | IOSTANDARD = LVCMOS33;
NET EBI_DATA[3] LOC = L5 | IOSTANDARD = LVCMOS33;
NET EBI_DATA[4] LOC = K3 | IOSTANDARD = LVCMOS33;
NET EBI_DATA[5] LOC = K4 | IOSTANDARD = LVCMOS33;
NET EBI_DATA[6] LOC = H1 | IOSTANDARD = LVCMOS33;
NET EBI_DATA[7] LOC = H2 | IOSTANDARD = LVCMOS33;
NET EBI_DATA[8] LOC = J1 | IOSTANDARD = LVCMOS33;
NET EBI_DATA[9] LOC = J3 | IOSTANDARD = LVCMOS33;
NET EBI_DATA[10] LOC = L3 | IOSTANDARD = LVCMOS33;
NET EBI_DATA[11] LOC = L4 | IOSTANDARD = LVCMOS33;
NET EBI_DATA[12] LOC = K1 | IOSTANDARD = LVCMOS33;
NET EBI_DATA[13] LOC = K2 | IOSTANDARD = LVCMOS33;
NET EBI_DATA[14] LOC = L1 | IOSTANDARD = LVCMOS33;
NET EBI_DATA[15] LOC = L2 | IOSTANDARD = LVCMOS33;
#