Assertions - Signal Indication that something wrong has happened. (Or coverage point - something should happen)

[amichai-bd]

Assertions are primarily used to validate the behavior of a design. ("Is it working correctly?")
They may also be used to provide functional coverage information for a design ("How good is the test?").

You should have a list of assumptions and illegal events.
The assumption are coded (in TB using XMR or in RTL but logic is not "loaded" so wont affect BE.)
In case the illegal condition is asserted, it should trigger a EOT (end of test) sequence that will do what ever happens in EOT.
such as snapshot, collect information, close files, etc., and should clearly DISPLAY that the test ended due to assertion!
Simple example:

• program counter overflow,
• access to illegal memory Space,
• Non existing Instruciton
• Non exciting ALU operation
• Memory RD&Wr access in the same cycle

Another use is to make sure each corner case we expect to test actually occurred in the simulation.
We call it "coverage point".
When a "coverage point" is asserted (XMR or in FE) , we track it using indications in the TB env.
And in EOT we will indicate what are the coverage point were reached in the specific test in the EOT log.