nestang9k-ps2.gprj

<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
    <Template>FPGA</Template>
    <Version>5</Version>
    <Device name="GW1NR-9C" pn="GW1NR-LV9QN88PC6/I5">gw1nr9c-004</Device>
    <FileList>
        <File path="src/DeltaSigmadac.v" type="file.verilog" enable="1"/>
        <File path="src/MicroCode.v" type="file.verilog" enable="1"/>
        <File path="src/NES_TN9.v" type="file.verilog" enable="1"/>
        <File path="src/apu.v" type="file.verilog" enable="1"/>
        <File path="src/compat.v" type="file.verilog" enable="1"/>
        <File path="src/cpu.v" type="file.verilog" enable="1"/>
        <File path="src/dualshock_controller.v" type="file.verilog" enable="1"/>
        <File path="src/gowin_clkdiv/gowin_clkdiv.v" type="file.verilog" enable="1"/>
        <File path="src/gowin_rpll/gowin_rpll.v" type="file.verilog" enable="1"/>
        <File path="src/gowin_rpll/gowin_rpll2.v" type="file.verilog" enable="1"/>
        <File path="src/gowin_sp/gowin_sp_2KBx8.v" type="file.verilog" enable="1"/>
        <File path="src/hdmi+a/audio_clock_regeneration_packet.sv" type="file.verilog" enable="1"/>
        <File path="src/hdmi+a/audio_info_frame.sv" type="file.verilog" enable="1"/>
        <File path="src/hdmi+a/audio_sample_packet.sv" type="file.verilog" enable="1"/>
        <File path="src/hdmi+a/auxiliary_video_information_info_frame.sv" type="file.verilog" enable="1"/>
        <File path="src/hdmi+a/hdmi.sv" type="file.verilog" enable="1"/>
        <File path="src/hdmi+a/packet_assembler.sv" type="file.verilog" enable="1"/>
        <File path="src/hdmi+a/packet_picker.sv" type="file.verilog" enable="1"/>
        <File path="src/hdmi+a/serializer.sv" type="file.verilog" enable="1"/>
        <File path="src/hdmi+a/source_product_description_info_frame.sv" type="file.verilog" enable="1"/>
        <File path="src/hdmi+a/tmds_channel.sv" type="file.verilog" enable="1"/>
        <File path="src/hq2x.v" type="file.verilog" enable="1"/>
        <File path="src/hw_led.v" type="file.verilog" enable="1"/>
        <File path="src/hw_uart.v" type="file.verilog" enable="1"/>
        <File path="src/mmu.v" type="file.verilog" enable="1"/>
        <File path="src/nes.v" type="file.verilog" enable="1"/>
        <File path="src/ppu.v" type="file.verilog" enable="1"/>
        <File path="src/psram_memory_interface_hs_2ch/psram_memory_interface_hs_WB16.v" type="file.verilog" enable="1"/>
        <File path="src/rs232c_tx_rx.v" type="file.verilog" enable="1"/>
        <File path="src/ukp2nes.v" type="file.verilog" enable="1"/>
        <File path="src/ukprom.v" type="file.verilog" enable="1"/>
        <File path="src/vga.v" type="file.verilog" enable="1"/>
        <File path="src/sd_controller.vhd" type="file.vhdl" enable="1"/>
        <File path="src/NES_TN9.cst" type="file.cst" enable="1"/>
        <File path="src/gao/fpganes_vga.rao" type="file.gao" enable="0"/>
    </FileList>
</Project>