@@ -1845,6 +1845,50 @@ static int stm32_ospi_write_status_register(const struct device *dev, uint8_t re
18451845 return ospi_write_access (dev , & s_command , regs_p , size );
18461846}
18471847
1848+ static int stm32_ospi_program_addr_4b (const struct device * dev , bool write_enable )
1849+ {
1850+ uint8_t statReg ;
1851+ struct flash_stm32_ospi_data * data = dev -> data ;
1852+ OSPI_HandleTypeDef * hospi = & data -> hospi ;
1853+ uint8_t nor_mode = OSPI_SPI_MODE ;
1854+ uint8_t nor_rate = OSPI_STR_TRANSFER ;
1855+ OSPI_RegularCmdTypeDef s_command = ospi_prepare_cmd (nor_mode , nor_rate );
1856+
1857+ if (write_enable ) {
1858+ if (stm32_ospi_write_enable (data , nor_mode , nor_rate ) < 0 ) {
1859+ LOG_ERR ("program_addr_4b failed to write_enable" );
1860+ return - EIO ;
1861+ }
1862+ }
1863+
1864+ /* Initialize the write enable command */
1865+ s_command .Instruction = SPI_NOR_CMD_4BA ;
1866+ if (nor_mode != OSPI_OPI_MODE ) {
1867+ /* force 1-line InstructionMode for any non-OSPI transfer */
1868+ s_command .InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE ;
1869+ }
1870+ s_command .AddressMode = HAL_OSPI_ADDRESS_NONE ;
1871+ s_command .DataMode = HAL_OSPI_DATA_NONE ;
1872+ s_command .DummyCycles = 0U ;
1873+
1874+ if (HAL_OSPI_Command (hospi , & s_command , HAL_OSPI_TIMEOUT_DEFAULT_VALUE ) != HAL_OK ) {
1875+ LOG_ERR ("OSPI Address Mode Change cmd failed" );
1876+ return - EIO ;
1877+ }
1878+
1879+ /* Check that ADS Bit in Status Reg 3 is now set indicating 4 Byte Address mode */
1880+ if (stm32_ospi_read_status_register (dev , 3 , & statReg )) {
1881+ LOG_ERR ("Status reg read failed" );
1882+ return - EIO ;
1883+ }
1884+
1885+ if (statReg & 0x01 ) {
1886+ return 0 ;
1887+ }
1888+ return - EIO ;
1889+ }
1890+
1891+
18481892static int stm32_ospi_enable_qe (const struct device * dev )
18491893{
18501894 struct flash_stm32_ospi_data * data = dev -> data ;
0 commit comments