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[CHERI] Generate CodeGen tests for RVY32/64
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‎llvm/test/CodeGen/CHERI-Generic/Inputs/global-capinit-hybrid.ll‎

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@@ -3,10 +3,14 @@
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@IF-MIPS@; RUN: FileCheck %s --check-prefix=ASM -DPTR_DIRECTIVE=.8byte
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@IF-RISCV64@; RUN: FileCheck %s --check-prefix=ASM -DPTR_DIRECTIVE=.quad
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@IF-RISCV32@; RUN: FileCheck %s --check-prefix=ASM -DPTR_DIRECTIVE=.word
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@IF-RISCV64Y@; RUN: FileCheck %s --check-prefix=ASM -DPTR_DIRECTIVE=.quad
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@IF-RISCV32Y@; RUN: FileCheck %s --check-prefix=ASM -DPTR_DIRECTIVE=.word
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; RUN: llc @HYBRID_HARDFLOAT_ARGS@ %s -filetype=obj -o - | llvm-objdump -r -t - | \
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@IF-MIPS@; RUN: FileCheck %s --check-prefix=RELOCS '-DINTEGER_RELOC=R_MIPS_64/R_MIPS_NONE/R_MIPS_NONE' '-DCAPABILITY_RELOC=R_MIPS_CHERI_CAPABILITY/R_MIPS_NONE/R_MIPS_NONE'
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@IF-RISCV64@; RUN: FileCheck %s --check-prefix=RELOCS -DINTEGER_RELOC=R_RISCV_64 '-DCAPABILITY_RELOC=R_RISCV_CHERI_CAPABILITY'
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@IF-RISCV32@; RUN: FileCheck %s --check-prefix=RELOCS -DINTEGER_RELOC=R_RISCV_32 '-DCAPABILITY_RELOC=R_RISCV_CHERI_CAPABILITY'
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@IF-RISCV64Y@; RUN: FileCheck %s --check-prefix=RELOCS -DINTEGER_RELOC=R_RISCV_64 '-DCAPABILITY_RELOC=R_RISCV_CHERI_CAPABILITY'
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@IF-RISCV32Y@; RUN: FileCheck %s --check-prefix=RELOCS -DINTEGER_RELOC=R_RISCV_32 '-DCAPABILITY_RELOC=R_RISCV_CHERI_CAPABILITY'
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target datalayout = "@HYBRID_DATALAYOUT@"
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declare void @extern_fn()

‎llvm/test/CodeGen/CHERI-Generic/Inputs/hoist-alloca.ll‎

Lines changed: 44 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -32,28 +32,66 @@
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; RUN: FileCheck --input-file=%t.dbg --check-prefix=MACHINELICM-DBG %s
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; Check that MachineLICM hoists the CheriBoundedStackPseudoImm (MIPS) / IncOffset+SetBoundsImm (RISCV) instructions
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; MACHINELICM-DBG-LABEL: ******** Pre-regalloc Machine LICM: hoist_alloca_uncond
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@IF-RISCV32Y@; MACHINELICM-DBG: Hoisting [[IMM:%[0-9]+]]:gpr = ADDI $x0, 512
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@IF-RISCV32Y@; MACHINELICM-DBG-NEXT: from %bb.2 to %bb.0
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@IF-RISCV64Y@; MACHINELICM-DBG: Hoisting [[IMM:%[0-9]+]]:gpr = ADDI $x0, 492
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@IF-RISCV64Y@; MACHINELICM-DBG-NEXT: from %bb.2 to %bb.0
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@IF-MIPS@; MACHINELICM-DBG: Hoisting %{{[0-9]+}}:cherigpr = CheriBoundedStackPseudoImm %stack.0.buf1, 0, 492
36-
@IF-RISCV@; MACHINELICM-DBG: Hoisting [[INC:%[0-9]+]]:gpcr = CIncOffsetImm %stack.0.buf1, 0
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@IF-RISCV32@; MACHINELICM-DBG: Hoisting [[INC:%[0-9]+]]:gpcr = CIncOffsetImm %stack.0.buf1, 0
41+
@IF-RISCV64@; MACHINELICM-DBG: Hoisting [[INC:%[0-9]+]]:gpcr = CIncOffsetImm %stack.0.buf1, 0
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@IF-RISCV32Y@; MACHINELICM-DBG: Hoisting [[INC:%[0-9]+]]:gpcr = ADDIY %stack.0.buf1, 0
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@IF-RISCV64Y@; MACHINELICM-DBG: Hoisting [[INC:%[0-9]+]]:gpcr = ADDIY %stack.0.buf1, 0
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; MACHINELICM-DBG-NEXT: from %bb.2 to %bb.0
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@IF-RISCV32@; MACHINELICM-DBG: Hoisting [[BOUNDS:%[0-9]+]]:gpcr = CSetBoundsImm [[INC]]:gpcr, 512
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@IF-RISCV64@; MACHINELICM-DBG: Hoisting [[BOUNDS:%[0-9]+]]:gpcr = CSetBoundsImm [[INC]]:gpcr, 492
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@IF-RISCV32Y@; MACHINELICM-DBG: Hoisting [[BOUNDS:%[0-9]+]]:gpcr = YBNDSRW [[INC]]:gpcr, [[IMM]]:gpr
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@IF-RISCV64Y@; MACHINELICM-DBG: Hoisting [[BOUNDS:%[0-9]+]]:gpcr = YBNDSRW [[INC]]:gpcr, [[IMM]]:gpr
4049
@IF-RISCV@; MACHINELICM-DBG-NEXT: from %bb.2 to %bb.0
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@IF-RISCV32Y@; MACHINELICM-DBG: Hoisting [[IMM:%[0-9]+]]:gpr = ADDI $x0, 88
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@IF-RISCV32Y@; MACHINELICM-DBG-NEXT: from %bb.2 to %bb.0
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@IF-RISCV64Y@; MACHINELICM-DBG: Hoisting [[IMM:%[0-9]+]]:gpr = ADDI $x0, 88
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@IF-RISCV64Y@; MACHINELICM-DBG-NEXT: from %bb.2 to %bb.0
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@IF-MIPS@; MACHINELICM-DBG: Hoisting %{{[0-9]+}}:cherigpr = CheriBoundedStackPseudoImm %stack.1.buf2, 0, 88
42-
@IF-RISCV@; MACHINELICM-DBG: Hoisting [[INC:%[0-9]+]]:gpcr = CIncOffsetImm %stack.1.buf2, 0
55+
@IF-RISCV32@; MACHINELICM-DBG: Hoisting [[INC:%[0-9]+]]:gpcr = CIncOffsetImm %stack.1.buf2, 0
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@IF-RISCV64@; MACHINELICM-DBG: Hoisting [[INC:%[0-9]+]]:gpcr = CIncOffsetImm %stack.1.buf2, 0
57+
@IF-RISCV32Y@; MACHINELICM-DBG: Hoisting [[INC:%[0-9]+]]:gpcr = ADDIY %stack.1.buf2, 0
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@IF-RISCV64Y@; MACHINELICM-DBG: Hoisting [[INC:%[0-9]+]]:gpcr = ADDIY %stack.1.buf2, 0
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; MACHINELICM-DBG-NEXT: from %bb.2 to %bb.0
44-
@IF-RISCV@; MACHINELICM-DBG: Hoisting [[BOUNDS:%[0-9]+]]:gpcr = CSetBoundsImm [[INC]]:gpcr, 88
60+
@IF-RISCV64@; MACHINELICM-DBG: Hoisting [[BOUNDS:%[0-9]+]]:gpcr = CSetBoundsImm [[INC]]:gpcr, 88
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@IF-RISCV32@; MACHINELICM-DBG: Hoisting [[BOUNDS:%[0-9]+]]:gpcr = CSetBoundsImm [[INC]]:gpcr, 88
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@IF-RISCV32Y@; MACHINELICM-DBG: Hoisting [[BOUNDS:%[0-9]+]]:gpcr = YBNDSRW [[INC]]:gpcr, [[IMM]]:gpr
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@IF-RISCV64Y@; MACHINELICM-DBG: Hoisting [[BOUNDS:%[0-9]+]]:gpcr = YBNDSRW [[INC]]:gpcr, [[IMM]]:gpr
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@IF-RISCV@; MACHINELICM-DBG-NEXT: from %bb.2 to %bb.0
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; MACHINELICM-DBG-LABEL: ******** Pre-regalloc Machine LICM: hoist_alloca_cond
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@IF-MIPS@; MACHINELICM-DBG: Hoisting %{{[0-9]+}}:cherigpr = CheriBoundedStackPseudoImm %stack.0.buf1, 0, 492
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@IF-RISCV@; MACHINELICM-DBG: Hoisting [[INC:%[0-9]+]]:gpcr = CIncOffsetImm %stack.0.buf1, 0
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@IF-RISCV32Y@; MACHINELICM-DBG: Hoisting [[IMM:%[0-9]+]]:gpr = ADDI $x0, 512
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@IF-RISCV32Y@; from %bb.3 to %bb.0
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@IF-RISCV64Y@; MACHINELICM-DBG: Hoisting [[IMM:%[0-9]+]]:gpr = ADDI $x0, 492
70+
@IF-RISCV64Y@; from %bb.3 to %bb.0
71+
@IF-RISCV32@; MACHINELICM-DBG: Hoisting [[INC:%[0-9]+]]:gpcr = CIncOffsetImm %stack.0.buf1, 0
72+
@IF-RISCV64@; MACHINELICM-DBG: Hoisting [[INC:%[0-9]+]]:gpcr = CIncOffsetImm %stack.0.buf1, 0
73+
@IF-RISCV32Y@; MACHINELICM-DBG: Hoisting [[INC:%[0-9]+]]:gpcr = ADDIY %stack.0.buf1, 0
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@IF-RISCV64Y@; MACHINELICM-DBG: Hoisting [[INC:%[0-9]+]]:gpcr = ADDIY %stack.0.buf1, 0
4975
; MACHINELICM-DBG-NEXT: from %bb.3 to %bb.0
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@IF-RISCV32@; MACHINELICM-DBG: Hoisting [[BOUNDS:%[0-9]+]]:gpcr = CSetBoundsImm [[INC]]:gpcr, 512
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@IF-RISCV64@; MACHINELICM-DBG: Hoisting [[BOUNDS:%[0-9]+]]:gpcr = CSetBoundsImm [[INC]]:gpcr, 492
78+
@IF-RISCV32Y@; MACHINELICM-DBG: Hoisting [[BOUNDS:%[0-9]+]]:gpcr = YBNDSRW [[INC]]:gpcr, [[IMM]]:gpr
79+
@IF-RISCV64Y@; MACHINELICM-DBG: Hoisting [[BOUNDS:%[0-9]+]]:gpcr = YBNDSRW [[INC]]:gpcr, [[IMM]]:gpr
5280
@IF-RISCV@; MACHINELICM-DBG-NEXT: from %bb.3 to %bb.0
81+
@IF-RISCV32Y@; MACHINELICM-DBG: Hoisting [[IMM:%[0-9]+]]:gpr = ADDI $x0, 88
82+
@IF-RISCV32Y@; MACHINELICM-DBG-NEXT: from %bb.3 to %bb.0
83+
@IF-RISCV64Y@; MACHINELICM-DBG: Hoisting [[IMM:%[0-9]+]]:gpr = ADDI $x0, 88
84+
@IF-RISCV64Y@; MACHINELICM-DBG-NEXT: from %bb.3 to %bb.0
5385
@IF-MIPS@; MACHINELICM-DBG: Hoisting %{{[0-9]+}}:cherigpr = CheriBoundedStackPseudoImm %stack.1.buf2, 0, 88
54-
@IF-RISCV@; MACHINELICM-DBG: Hoisting [[INC:%[0-9]+]]:gpcr = CIncOffsetImm %stack.1.buf2, 0
86+
@IF-RISCV32@; MACHINELICM-DBG: Hoisting [[INC:%[0-9]+]]:gpcr = CIncOffsetImm %stack.1.buf2, 0
87+
@IF-RISCV64@; MACHINELICM-DBG: Hoisting [[INC:%[0-9]+]]:gpcr = CIncOffsetImm %stack.1.buf2, 0
88+
@IF-RISCV32Y@; MACHINELICM-DBG: Hoisting [[INC:%[0-9]+]]:gpcr = ADDIY %stack.1.buf2, 0
89+
@IF-RISCV64Y@; MACHINELICM-DBG: Hoisting [[INC:%[0-9]+]]:gpcr = ADDIY %stack.1.buf2, 0
5590
; MACHINELICM-DBG-NEXT: from %bb.3 to %bb.0
56-
@IF-RISCV@; MACHINELICM-DBG: Hoisting [[BOUNDS:%[0-9]+]]:gpcr = CSetBoundsImm [[INC]]:gpcr, 88
91+
@IF-RISCV64@; MACHINELICM-DBG: Hoisting [[BOUNDS:%[0-9]+]]:gpcr = CSetBoundsImm [[INC]]:gpcr, 88
92+
@IF-RISCV32@; MACHINELICM-DBG: Hoisting [[BOUNDS:%[0-9]+]]:gpcr = CSetBoundsImm [[INC]]:gpcr, 88
93+
@IF-RISCV32Y@; MACHINELICM-DBG: Hoisting [[BOUNDS:%[0-9]+]]:gpcr = YBNDSRW [[INC]]:gpcr, [[IMM]]:gpr
94+
@IF-RISCV64Y@; MACHINELICM-DBG: Hoisting [[BOUNDS:%[0-9]+]]:gpcr = YBNDSRW [[INC]]:gpcr, [[IMM]]:gpr
5795
@IF-RISCV@; MACHINELICM-DBG-NEXT: from %bb.3 to %bb.0
5896

5997
; RUN: llc @PURECAP_HARDFLOAT_ARGS@ -O1 -o - < %s | FileCheck %s

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