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jvdweteringjvdwetering
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Merge pull request zxcalc#108 from CQCL/phase_poly_routing
Add routing methods for phase polynomials
2 parents d1c1555 + c3ea117 commit e695d6d

24 files changed

+1803
-2
lines changed

‎circuits/steiner/5qubits/2/Original0.qasm

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// Initial wiring: [0, 1, 2, 3, 4]
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// Resulting wiring: [0, 1, 2, 3, 4]
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OPENQASM 2.0;
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include "qelib1.inc";
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qreg q[5];
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cx q[0], q[4];
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cx q[1], q[0];

‎circuits/steiner/5qubits/2/Original1.qasm

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// Initial wiring: [0, 1, 2, 3, 4]
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// Resulting wiring: [0, 1, 2, 3, 4]
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OPENQASM 2.0;
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include "qelib1.inc";
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qreg q[5];
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cx q[1], q[0];
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cx q[4], q[1];

‎circuits/steiner/5qubits/2/Original10.qasm

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// Initial wiring: [0, 1, 2, 3, 4]
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// Resulting wiring: [0, 1, 2, 3, 4]
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OPENQASM 2.0;
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include "qelib1.inc";
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qreg q[5];
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cx q[4], q[3];
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cx q[3], q[2];

‎circuits/steiner/5qubits/2/Original11.qasm

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// Initial wiring: [0, 1, 2, 3, 4]
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// Resulting wiring: [0, 1, 2, 3, 4]
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OPENQASM 2.0;
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include "qelib1.inc";
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qreg q[5];
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cx q[3], q[4];
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cx q[3], q[4];

‎circuits/steiner/5qubits/2/Original12.qasm

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// Initial wiring: [0, 1, 2, 3, 4]
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// Resulting wiring: [0, 1, 2, 3, 4]
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OPENQASM 2.0;
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include "qelib1.inc";
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qreg q[5];
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cx q[4], q[3];
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cx q[2], q[0];

‎circuits/steiner/5qubits/2/Original13.qasm

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// Initial wiring: [0, 1, 2, 3, 4]
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// Resulting wiring: [0, 1, 2, 3, 4]
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OPENQASM 2.0;
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include "qelib1.inc";
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qreg q[5];
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cx q[1], q[0];
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cx q[3], q[2];

‎circuits/steiner/5qubits/2/Original14.qasm

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// Initial wiring: [0, 1, 2, 3, 4]
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// Resulting wiring: [0, 1, 2, 3, 4]
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OPENQASM 2.0;
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include "qelib1.inc";
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qreg q[5];
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cx q[0], q[1];
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cx q[1], q[3];

‎circuits/steiner/5qubits/2/Original15.qasm

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// Initial wiring: [0, 1, 2, 3, 4]
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// Resulting wiring: [0, 1, 2, 3, 4]
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OPENQASM 2.0;
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include "qelib1.inc";
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qreg q[5];
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cx q[2], q[3];
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cx q[0], q[3];

‎circuits/steiner/5qubits/2/Original16.qasm

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// Initial wiring: [0, 1, 2, 3, 4]
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// Resulting wiring: [0, 1, 2, 3, 4]
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OPENQASM 2.0;
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include "qelib1.inc";
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qreg q[5];
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cx q[1], q[3];
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cx q[3], q[0];

‎circuits/steiner/5qubits/2/Original17.qasm

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// Initial wiring: [0, 1, 2, 3, 4]
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// Resulting wiring: [0, 1, 2, 3, 4]
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OPENQASM 2.0;
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include "qelib1.inc";
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qreg q[5];
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cx q[4], q[2];
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cx q[0], q[3];

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